1 /* 2 * Intel 5100 Memory Controllers kernel module 3 * 4 * This file may be distributed under the terms of the 5 * GNU General Public License. 6 * 7 * This module is based on the following document: 8 * 9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet 10 * http://download.intel.com/design/chipsets/datashts/318378.pdf 11 * 12 * The intel 5100 has two independent channels. EDAC core currently 13 * can not reflect this configuration so instead the chip-select 14 * rows for each respective channel are layed out one after another, 15 * the first half belonging to channel 0, the second half belonging 16 * to channel 1. 17 */ 18 #include <linux/module.h> 19 #include <linux/init.h> 20 #include <linux/pci.h> 21 #include <linux/pci_ids.h> 22 #include <linux/slab.h> 23 #include <linux/edac.h> 24 #include <linux/delay.h> 25 #include <linux/mmzone.h> 26 27 #include "edac_core.h" 28 29 /* register addresses */ 30 31 /* device 16, func 1 */ 32 #define I5100_MC 0x40 /* Memory Control Register */ 33 #define I5100_MC_SCRBEN_MASK (1 << 7) 34 #define I5100_MC_SCRBDONE_MASK (1 << 4) 35 #define I5100_MS 0x44 /* Memory Status Register */ 36 #define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */ 37 #define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */ 38 #define I5100_TOLM 0x6c /* Top of Low Memory */ 39 #define I5100_MIR0 0x80 /* Memory Interleave Range 0 */ 40 #define I5100_MIR1 0x84 /* Memory Interleave Range 1 */ 41 #define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */ 42 #define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */ 43 #define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */ 44 #define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16) 45 #define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15) 46 #define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14) 47 #define I5100_FERR_NF_MEM_M12ERR_MASK (1 << 12) 48 #define I5100_FERR_NF_MEM_M11ERR_MASK (1 << 11) 49 #define I5100_FERR_NF_MEM_M10ERR_MASK (1 << 10) 50 #define I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6) 51 #define I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5) 52 #define I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4) 53 #define I5100_FERR_NF_MEM_M1ERR_MASK 1 54 #define I5100_FERR_NF_MEM_ANY_MASK \ 55 (I5100_FERR_NF_MEM_M16ERR_MASK | \ 56 I5100_FERR_NF_MEM_M15ERR_MASK | \ 57 I5100_FERR_NF_MEM_M14ERR_MASK | \ 58 I5100_FERR_NF_MEM_M12ERR_MASK | \ 59 I5100_FERR_NF_MEM_M11ERR_MASK | \ 60 I5100_FERR_NF_MEM_M10ERR_MASK | \ 61 I5100_FERR_NF_MEM_M6ERR_MASK | \ 62 I5100_FERR_NF_MEM_M5ERR_MASK | \ 63 I5100_FERR_NF_MEM_M4ERR_MASK | \ 64 I5100_FERR_NF_MEM_M1ERR_MASK) 65 #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */ 66 #define I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */ 67 68 /* device 21 and 22, func 0 */ 69 #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */ 70 #define I5100_DMIR 0x15c /* DIMM Interleave Range */ 71 #define I5100_VALIDLOG 0x18c /* Valid Log Markers */ 72 #define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */ 73 #define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */ 74 #define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */ 75 #define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */ 76 #define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */ 77 #define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */ 78 #define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */ 79 80 /* bit field accessors */ 81 82 static inline u32 i5100_mc_scrben(u32 mc) 83 { 84 return mc >> 7 & 1; 85 } 86 87 static inline u32 i5100_mc_errdeten(u32 mc) 88 { 89 return mc >> 5 & 1; 90 } 91 92 static inline u32 i5100_mc_scrbdone(u32 mc) 93 { 94 return mc >> 4 & 1; 95 } 96 97 static inline u16 i5100_spddata_rdo(u16 a) 98 { 99 return a >> 15 & 1; 100 } 101 102 static inline u16 i5100_spddata_sbe(u16 a) 103 { 104 return a >> 13 & 1; 105 } 106 107 static inline u16 i5100_spddata_busy(u16 a) 108 { 109 return a >> 12 & 1; 110 } 111 112 static inline u16 i5100_spddata_data(u16 a) 113 { 114 return a & ((1 << 8) - 1); 115 } 116 117 static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba, 118 u32 data, u32 cmd) 119 { 120 return ((dti & ((1 << 4) - 1)) << 28) | 121 ((ckovrd & 1) << 27) | 122 ((sa & ((1 << 3) - 1)) << 24) | 123 ((ba & ((1 << 8) - 1)) << 16) | 124 ((data & ((1 << 8) - 1)) << 8) | 125 (cmd & 1); 126 } 127 128 static inline u16 i5100_tolm_tolm(u16 a) 129 { 130 return a >> 12 & ((1 << 4) - 1); 131 } 132 133 static inline u16 i5100_mir_limit(u16 a) 134 { 135 return a >> 4 & ((1 << 12) - 1); 136 } 137 138 static inline u16 i5100_mir_way1(u16 a) 139 { 140 return a >> 1 & 1; 141 } 142 143 static inline u16 i5100_mir_way0(u16 a) 144 { 145 return a & 1; 146 } 147 148 static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a) 149 { 150 return a >> 28 & 1; 151 } 152 153 static inline u32 i5100_ferr_nf_mem_any(u32 a) 154 { 155 return a & I5100_FERR_NF_MEM_ANY_MASK; 156 } 157 158 static inline u32 i5100_nerr_nf_mem_any(u32 a) 159 { 160 return i5100_ferr_nf_mem_any(a); 161 } 162 163 static inline u32 i5100_dmir_limit(u32 a) 164 { 165 return a >> 16 & ((1 << 11) - 1); 166 } 167 168 static inline u32 i5100_dmir_rank(u32 a, u32 i) 169 { 170 return a >> (4 * i) & ((1 << 2) - 1); 171 } 172 173 static inline u16 i5100_mtr_present(u16 a) 174 { 175 return a >> 10 & 1; 176 } 177 178 static inline u16 i5100_mtr_ethrottle(u16 a) 179 { 180 return a >> 9 & 1; 181 } 182 183 static inline u16 i5100_mtr_width(u16 a) 184 { 185 return a >> 8 & 1; 186 } 187 188 static inline u16 i5100_mtr_numbank(u16 a) 189 { 190 return a >> 6 & 1; 191 } 192 193 static inline u16 i5100_mtr_numrow(u16 a) 194 { 195 return a >> 2 & ((1 << 2) - 1); 196 } 197 198 static inline u16 i5100_mtr_numcol(u16 a) 199 { 200 return a & ((1 << 2) - 1); 201 } 202 203 204 static inline u32 i5100_validlog_redmemvalid(u32 a) 205 { 206 return a >> 2 & 1; 207 } 208 209 static inline u32 i5100_validlog_recmemvalid(u32 a) 210 { 211 return a >> 1 & 1; 212 } 213 214 static inline u32 i5100_validlog_nrecmemvalid(u32 a) 215 { 216 return a & 1; 217 } 218 219 static inline u32 i5100_nrecmema_merr(u32 a) 220 { 221 return a >> 15 & ((1 << 5) - 1); 222 } 223 224 static inline u32 i5100_nrecmema_bank(u32 a) 225 { 226 return a >> 12 & ((1 << 3) - 1); 227 } 228 229 static inline u32 i5100_nrecmema_rank(u32 a) 230 { 231 return a >> 8 & ((1 << 3) - 1); 232 } 233 234 static inline u32 i5100_nrecmema_dm_buf_id(u32 a) 235 { 236 return a & ((1 << 8) - 1); 237 } 238 239 static inline u32 i5100_nrecmemb_cas(u32 a) 240 { 241 return a >> 16 & ((1 << 13) - 1); 242 } 243 244 static inline u32 i5100_nrecmemb_ras(u32 a) 245 { 246 return a & ((1 << 16) - 1); 247 } 248 249 static inline u32 i5100_redmemb_ecc_locator(u32 a) 250 { 251 return a & ((1 << 18) - 1); 252 } 253 254 static inline u32 i5100_recmema_merr(u32 a) 255 { 256 return i5100_nrecmema_merr(a); 257 } 258 259 static inline u32 i5100_recmema_bank(u32 a) 260 { 261 return i5100_nrecmema_bank(a); 262 } 263 264 static inline u32 i5100_recmema_rank(u32 a) 265 { 266 return i5100_nrecmema_rank(a); 267 } 268 269 static inline u32 i5100_recmema_dm_buf_id(u32 a) 270 { 271 return i5100_nrecmema_dm_buf_id(a); 272 } 273 274 static inline u32 i5100_recmemb_cas(u32 a) 275 { 276 return i5100_nrecmemb_cas(a); 277 } 278 279 static inline u32 i5100_recmemb_ras(u32 a) 280 { 281 return i5100_nrecmemb_ras(a); 282 } 283 284 /* some generic limits */ 285 #define I5100_MAX_RANKS_PER_CHAN 6 286 #define I5100_CHANNELS 2 287 #define I5100_MAX_RANKS_PER_DIMM 4 288 #define I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */ 289 #define I5100_MAX_DIMM_SLOTS_PER_CHAN 4 290 #define I5100_MAX_RANK_INTERLEAVE 4 291 #define I5100_MAX_DMIRS 5 292 #define I5100_SCRUB_REFRESH_RATE (5 * 60 * HZ) 293 294 struct i5100_priv { 295 /* ranks on each dimm -- 0 maps to not present -- obtained via SPD */ 296 int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN]; 297 298 /* 299 * mainboard chip select map -- maps i5100 chip selects to 300 * DIMM slot chip selects. In the case of only 4 ranks per 301 * channel, the mapping is fairly obvious but not unique. 302 * we map -1 -> NC and assume both channels use the same 303 * map... 304 * 305 */ 306 int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM]; 307 308 /* memory interleave range */ 309 struct { 310 u64 limit; 311 unsigned way[2]; 312 } mir[I5100_CHANNELS]; 313 314 /* adjusted memory interleave range register */ 315 unsigned amir[I5100_CHANNELS]; 316 317 /* dimm interleave range */ 318 struct { 319 unsigned rank[I5100_MAX_RANK_INTERLEAVE]; 320 u64 limit; 321 } dmir[I5100_CHANNELS][I5100_MAX_DMIRS]; 322 323 /* memory technology registers... */ 324 struct { 325 unsigned present; /* 0 or 1 */ 326 unsigned ethrottle; /* 0 or 1 */ 327 unsigned width; /* 4 or 8 bits */ 328 unsigned numbank; /* 2 or 3 lines */ 329 unsigned numrow; /* 13 .. 16 lines */ 330 unsigned numcol; /* 11 .. 12 lines */ 331 } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN]; 332 333 u64 tolm; /* top of low memory in bytes */ 334 unsigned ranksperchan; /* number of ranks per channel */ 335 336 struct pci_dev *mc; /* device 16 func 1 */ 337 struct pci_dev *ch0mm; /* device 21 func 0 */ 338 struct pci_dev *ch1mm; /* device 22 func 0 */ 339 340 struct delayed_work i5100_scrubbing; 341 int scrub_enable; 342 }; 343 344 /* map a rank/chan to a slot number on the mainboard */ 345 static int i5100_rank_to_slot(const struct mem_ctl_info *mci, 346 int chan, int rank) 347 { 348 const struct i5100_priv *priv = mci->pvt_info; 349 int i; 350 351 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) { 352 int j; 353 const int numrank = priv->dimm_numrank[chan][i]; 354 355 for (j = 0; j < numrank; j++) 356 if (priv->dimm_csmap[i][j] == rank) 357 return i * 2 + chan; 358 } 359 360 return -1; 361 } 362 363 static const char *i5100_err_msg(unsigned err) 364 { 365 static const char *merrs[] = { 366 "unknown", /* 0 */ 367 "uncorrectable data ECC on replay", /* 1 */ 368 "unknown", /* 2 */ 369 "unknown", /* 3 */ 370 "aliased uncorrectable demand data ECC", /* 4 */ 371 "aliased uncorrectable spare-copy data ECC", /* 5 */ 372 "aliased uncorrectable patrol data ECC", /* 6 */ 373 "unknown", /* 7 */ 374 "unknown", /* 8 */ 375 "unknown", /* 9 */ 376 "non-aliased uncorrectable demand data ECC", /* 10 */ 377 "non-aliased uncorrectable spare-copy data ECC", /* 11 */ 378 "non-aliased uncorrectable patrol data ECC", /* 12 */ 379 "unknown", /* 13 */ 380 "correctable demand data ECC", /* 14 */ 381 "correctable spare-copy data ECC", /* 15 */ 382 "correctable patrol data ECC", /* 16 */ 383 "unknown", /* 17 */ 384 "SPD protocol error", /* 18 */ 385 "unknown", /* 19 */ 386 "spare copy initiated", /* 20 */ 387 "spare copy completed", /* 21 */ 388 }; 389 unsigned i; 390 391 for (i = 0; i < ARRAY_SIZE(merrs); i++) 392 if (1 << i & err) 393 return merrs[i]; 394 395 return "none"; 396 } 397 398 /* convert csrow index into a rank (per channel -- 0..5) */ 399 static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow) 400 { 401 const struct i5100_priv *priv = mci->pvt_info; 402 403 return csrow % priv->ranksperchan; 404 } 405 406 /* convert csrow index into a channel (0..1) */ 407 static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow) 408 { 409 const struct i5100_priv *priv = mci->pvt_info; 410 411 return csrow / priv->ranksperchan; 412 } 413 414 static unsigned i5100_rank_to_csrow(const struct mem_ctl_info *mci, 415 int chan, int rank) 416 { 417 const struct i5100_priv *priv = mci->pvt_info; 418 419 return chan * priv->ranksperchan + rank; 420 } 421 422 static void i5100_handle_ce(struct mem_ctl_info *mci, 423 int chan, 424 unsigned bank, 425 unsigned rank, 426 unsigned long syndrome, 427 unsigned cas, 428 unsigned ras, 429 const char *msg) 430 { 431 const int csrow = i5100_rank_to_csrow(mci, chan, rank); 432 433 printk(KERN_ERR 434 "CE chan %d, bank %u, rank %u, syndrome 0x%lx, " 435 "cas %u, ras %u, csrow %u, label \"%s\": %s\n", 436 chan, bank, rank, syndrome, cas, ras, 437 csrow, mci->csrows[csrow].channels[0].label, msg); 438 439 mci->ce_count++; 440 mci->csrows[csrow].ce_count++; 441 mci->csrows[csrow].channels[0].ce_count++; 442 } 443 444 static void i5100_handle_ue(struct mem_ctl_info *mci, 445 int chan, 446 unsigned bank, 447 unsigned rank, 448 unsigned long syndrome, 449 unsigned cas, 450 unsigned ras, 451 const char *msg) 452 { 453 const int csrow = i5100_rank_to_csrow(mci, chan, rank); 454 455 printk(KERN_ERR 456 "UE chan %d, bank %u, rank %u, syndrome 0x%lx, " 457 "cas %u, ras %u, csrow %u, label \"%s\": %s\n", 458 chan, bank, rank, syndrome, cas, ras, 459 csrow, mci->csrows[csrow].channels[0].label, msg); 460 461 mci->ue_count++; 462 mci->csrows[csrow].ue_count++; 463 } 464 465 static void i5100_read_log(struct mem_ctl_info *mci, int chan, 466 u32 ferr, u32 nerr) 467 { 468 struct i5100_priv *priv = mci->pvt_info; 469 struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm; 470 u32 dw; 471 u32 dw2; 472 unsigned syndrome = 0; 473 unsigned ecc_loc = 0; 474 unsigned merr; 475 unsigned bank; 476 unsigned rank; 477 unsigned cas; 478 unsigned ras; 479 480 pci_read_config_dword(pdev, I5100_VALIDLOG, &dw); 481 482 if (i5100_validlog_redmemvalid(dw)) { 483 pci_read_config_dword(pdev, I5100_REDMEMA, &dw2); 484 syndrome = dw2; 485 pci_read_config_dword(pdev, I5100_REDMEMB, &dw2); 486 ecc_loc = i5100_redmemb_ecc_locator(dw2); 487 } 488 489 if (i5100_validlog_recmemvalid(dw)) { 490 const char *msg; 491 492 pci_read_config_dword(pdev, I5100_RECMEMA, &dw2); 493 merr = i5100_recmema_merr(dw2); 494 bank = i5100_recmema_bank(dw2); 495 rank = i5100_recmema_rank(dw2); 496 497 pci_read_config_dword(pdev, I5100_RECMEMB, &dw2); 498 cas = i5100_recmemb_cas(dw2); 499 ras = i5100_recmemb_ras(dw2); 500 501 /* FIXME: not really sure if this is what merr is... 502 */ 503 if (!merr) 504 msg = i5100_err_msg(ferr); 505 else 506 msg = i5100_err_msg(nerr); 507 508 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg); 509 } 510 511 if (i5100_validlog_nrecmemvalid(dw)) { 512 const char *msg; 513 514 pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2); 515 merr = i5100_nrecmema_merr(dw2); 516 bank = i5100_nrecmema_bank(dw2); 517 rank = i5100_nrecmema_rank(dw2); 518 519 pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2); 520 cas = i5100_nrecmemb_cas(dw2); 521 ras = i5100_nrecmemb_ras(dw2); 522 523 /* FIXME: not really sure if this is what merr is... 524 */ 525 if (!merr) 526 msg = i5100_err_msg(ferr); 527 else 528 msg = i5100_err_msg(nerr); 529 530 i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg); 531 } 532 533 pci_write_config_dword(pdev, I5100_VALIDLOG, dw); 534 } 535 536 static void i5100_check_error(struct mem_ctl_info *mci) 537 { 538 struct i5100_priv *priv = mci->pvt_info; 539 u32 dw; 540 541 542 pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw); 543 if (i5100_ferr_nf_mem_any(dw)) { 544 u32 dw2; 545 546 pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2); 547 if (dw2) 548 pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, 549 dw2); 550 pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw); 551 552 i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw), 553 i5100_ferr_nf_mem_any(dw), 554 i5100_nerr_nf_mem_any(dw2)); 555 } 556 } 557 558 /* The i5100 chipset will scrub the entire memory once, then 559 * set a done bit. Continuous scrubbing is achieved by enqueing 560 * delayed work to a workqueue, checking every few minutes if 561 * the scrubbing has completed and if so reinitiating it. 562 */ 563 564 static void i5100_refresh_scrubbing(struct work_struct *work) 565 { 566 struct delayed_work *i5100_scrubbing = container_of(work, 567 struct delayed_work, 568 work); 569 struct i5100_priv *priv = container_of(i5100_scrubbing, 570 struct i5100_priv, 571 i5100_scrubbing); 572 u32 dw; 573 574 pci_read_config_dword(priv->mc, I5100_MC, &dw); 575 576 if (priv->scrub_enable) { 577 578 pci_read_config_dword(priv->mc, I5100_MC, &dw); 579 580 if (i5100_mc_scrbdone(dw)) { 581 dw |= I5100_MC_SCRBEN_MASK; 582 pci_write_config_dword(priv->mc, I5100_MC, dw); 583 pci_read_config_dword(priv->mc, I5100_MC, &dw); 584 } 585 586 schedule_delayed_work(&(priv->i5100_scrubbing), 587 I5100_SCRUB_REFRESH_RATE); 588 } 589 } 590 /* 591 * The bandwidth is based on experimentation, feel free to refine it. 592 */ 593 static int i5100_set_scrub_rate(struct mem_ctl_info *mci, 594 u32 *bandwidth) 595 { 596 struct i5100_priv *priv = mci->pvt_info; 597 u32 dw; 598 599 pci_read_config_dword(priv->mc, I5100_MC, &dw); 600 if (*bandwidth) { 601 priv->scrub_enable = 1; 602 dw |= I5100_MC_SCRBEN_MASK; 603 schedule_delayed_work(&(priv->i5100_scrubbing), 604 I5100_SCRUB_REFRESH_RATE); 605 } else { 606 priv->scrub_enable = 0; 607 dw &= ~I5100_MC_SCRBEN_MASK; 608 cancel_delayed_work(&(priv->i5100_scrubbing)); 609 } 610 pci_write_config_dword(priv->mc, I5100_MC, dw); 611 612 pci_read_config_dword(priv->mc, I5100_MC, &dw); 613 614 *bandwidth = 5900000 * i5100_mc_scrben(dw); 615 616 return 0; 617 } 618 619 static int i5100_get_scrub_rate(struct mem_ctl_info *mci, 620 u32 *bandwidth) 621 { 622 struct i5100_priv *priv = mci->pvt_info; 623 u32 dw; 624 625 pci_read_config_dword(priv->mc, I5100_MC, &dw); 626 627 *bandwidth = 5900000 * i5100_mc_scrben(dw); 628 629 return 0; 630 } 631 632 static struct pci_dev *pci_get_device_func(unsigned vendor, 633 unsigned device, 634 unsigned func) 635 { 636 struct pci_dev *ret = NULL; 637 638 while (1) { 639 ret = pci_get_device(vendor, device, ret); 640 641 if (!ret) 642 break; 643 644 if (PCI_FUNC(ret->devfn) == func) 645 break; 646 } 647 648 return ret; 649 } 650 651 static unsigned long __devinit i5100_npages(struct mem_ctl_info *mci, 652 int csrow) 653 { 654 struct i5100_priv *priv = mci->pvt_info; 655 const unsigned chan_rank = i5100_csrow_to_rank(mci, csrow); 656 const unsigned chan = i5100_csrow_to_chan(mci, csrow); 657 unsigned addr_lines; 658 659 /* dimm present? */ 660 if (!priv->mtr[chan][chan_rank].present) 661 return 0ULL; 662 663 addr_lines = 664 I5100_DIMM_ADDR_LINES + 665 priv->mtr[chan][chan_rank].numcol + 666 priv->mtr[chan][chan_rank].numrow + 667 priv->mtr[chan][chan_rank].numbank; 668 669 return (unsigned long) 670 ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE); 671 } 672 673 static void __devinit i5100_init_mtr(struct mem_ctl_info *mci) 674 { 675 struct i5100_priv *priv = mci->pvt_info; 676 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm }; 677 int i; 678 679 for (i = 0; i < I5100_CHANNELS; i++) { 680 int j; 681 struct pci_dev *pdev = mms[i]; 682 683 for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) { 684 const unsigned addr = 685 (j < 4) ? I5100_MTR_0 + j * 2 : 686 I5100_MTR_4 + (j - 4) * 2; 687 u16 w; 688 689 pci_read_config_word(pdev, addr, &w); 690 691 priv->mtr[i][j].present = i5100_mtr_present(w); 692 priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w); 693 priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w); 694 priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w); 695 priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w); 696 priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w); 697 } 698 } 699 } 700 701 /* 702 * FIXME: make this into a real i2c adapter (so that dimm-decode 703 * will work)? 704 */ 705 static int i5100_read_spd_byte(const struct mem_ctl_info *mci, 706 u8 ch, u8 slot, u8 addr, u8 *byte) 707 { 708 struct i5100_priv *priv = mci->pvt_info; 709 u16 w; 710 unsigned long et; 711 712 pci_read_config_word(priv->mc, I5100_SPDDATA, &w); 713 if (i5100_spddata_busy(w)) 714 return -1; 715 716 pci_write_config_dword(priv->mc, I5100_SPDCMD, 717 i5100_spdcmd_create(0xa, 1, ch * 4 + slot, addr, 718 0, 0)); 719 720 /* wait up to 100ms */ 721 et = jiffies + HZ / 10; 722 udelay(100); 723 while (1) { 724 pci_read_config_word(priv->mc, I5100_SPDDATA, &w); 725 if (!i5100_spddata_busy(w)) 726 break; 727 udelay(100); 728 } 729 730 if (!i5100_spddata_rdo(w) || i5100_spddata_sbe(w)) 731 return -1; 732 733 *byte = i5100_spddata_data(w); 734 735 return 0; 736 } 737 738 /* 739 * fill dimm chip select map 740 * 741 * FIXME: 742 * o not the only way to may chip selects to dimm slots 743 * o investigate if there is some way to obtain this map from the bios 744 */ 745 static void __devinit i5100_init_dimm_csmap(struct mem_ctl_info *mci) 746 { 747 struct i5100_priv *priv = mci->pvt_info; 748 int i; 749 750 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) { 751 int j; 752 753 for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++) 754 priv->dimm_csmap[i][j] = -1; /* default NC */ 755 } 756 757 /* only 2 chip selects per slot... */ 758 if (priv->ranksperchan == 4) { 759 priv->dimm_csmap[0][0] = 0; 760 priv->dimm_csmap[0][1] = 3; 761 priv->dimm_csmap[1][0] = 1; 762 priv->dimm_csmap[1][1] = 2; 763 priv->dimm_csmap[2][0] = 2; 764 priv->dimm_csmap[3][0] = 3; 765 } else { 766 priv->dimm_csmap[0][0] = 0; 767 priv->dimm_csmap[0][1] = 1; 768 priv->dimm_csmap[1][0] = 2; 769 priv->dimm_csmap[1][1] = 3; 770 priv->dimm_csmap[2][0] = 4; 771 priv->dimm_csmap[2][1] = 5; 772 } 773 } 774 775 static void __devinit i5100_init_dimm_layout(struct pci_dev *pdev, 776 struct mem_ctl_info *mci) 777 { 778 struct i5100_priv *priv = mci->pvt_info; 779 int i; 780 781 for (i = 0; i < I5100_CHANNELS; i++) { 782 int j; 783 784 for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) { 785 u8 rank; 786 787 if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0) 788 priv->dimm_numrank[i][j] = 0; 789 else 790 priv->dimm_numrank[i][j] = (rank & 3) + 1; 791 } 792 } 793 794 i5100_init_dimm_csmap(mci); 795 } 796 797 static void __devinit i5100_init_interleaving(struct pci_dev *pdev, 798 struct mem_ctl_info *mci) 799 { 800 u16 w; 801 u32 dw; 802 struct i5100_priv *priv = mci->pvt_info; 803 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm }; 804 int i; 805 806 pci_read_config_word(pdev, I5100_TOLM, &w); 807 priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024; 808 809 pci_read_config_word(pdev, I5100_MIR0, &w); 810 priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28; 811 priv->mir[0].way[1] = i5100_mir_way1(w); 812 priv->mir[0].way[0] = i5100_mir_way0(w); 813 814 pci_read_config_word(pdev, I5100_MIR1, &w); 815 priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28; 816 priv->mir[1].way[1] = i5100_mir_way1(w); 817 priv->mir[1].way[0] = i5100_mir_way0(w); 818 819 pci_read_config_word(pdev, I5100_AMIR_0, &w); 820 priv->amir[0] = w; 821 pci_read_config_word(pdev, I5100_AMIR_1, &w); 822 priv->amir[1] = w; 823 824 for (i = 0; i < I5100_CHANNELS; i++) { 825 int j; 826 827 for (j = 0; j < 5; j++) { 828 int k; 829 830 pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw); 831 832 priv->dmir[i][j].limit = 833 (u64) i5100_dmir_limit(dw) << 28; 834 for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++) 835 priv->dmir[i][j].rank[k] = 836 i5100_dmir_rank(dw, k); 837 } 838 } 839 840 i5100_init_mtr(mci); 841 } 842 843 static void __devinit i5100_init_csrows(struct mem_ctl_info *mci) 844 { 845 int i; 846 unsigned long total_pages = 0UL; 847 struct i5100_priv *priv = mci->pvt_info; 848 849 for (i = 0; i < mci->nr_csrows; i++) { 850 const unsigned long npages = i5100_npages(mci, i); 851 const unsigned chan = i5100_csrow_to_chan(mci, i); 852 const unsigned rank = i5100_csrow_to_rank(mci, i); 853 854 if (!npages) 855 continue; 856 857 /* 858 * FIXME: these two are totally bogus -- I don't see how to 859 * map them correctly to this structure... 860 */ 861 mci->csrows[i].first_page = total_pages; 862 mci->csrows[i].last_page = total_pages + npages - 1; 863 mci->csrows[i].page_mask = 0UL; 864 865 mci->csrows[i].nr_pages = npages; 866 mci->csrows[i].grain = 32; 867 mci->csrows[i].csrow_idx = i; 868 mci->csrows[i].dtype = 869 (priv->mtr[chan][rank].width == 4) ? DEV_X4 : DEV_X8; 870 mci->csrows[i].ue_count = 0; 871 mci->csrows[i].ce_count = 0; 872 mci->csrows[i].mtype = MEM_RDDR2; 873 mci->csrows[i].edac_mode = EDAC_SECDED; 874 mci->csrows[i].mci = mci; 875 mci->csrows[i].nr_channels = 1; 876 mci->csrows[i].channels[0].chan_idx = 0; 877 mci->csrows[i].channels[0].ce_count = 0; 878 mci->csrows[i].channels[0].csrow = mci->csrows + i; 879 snprintf(mci->csrows[i].channels[0].label, 880 sizeof(mci->csrows[i].channels[0].label), 881 "DIMM%u", i5100_rank_to_slot(mci, chan, rank)); 882 883 total_pages += npages; 884 } 885 } 886 887 static int __devinit i5100_init_one(struct pci_dev *pdev, 888 const struct pci_device_id *id) 889 { 890 int rc; 891 struct mem_ctl_info *mci; 892 struct i5100_priv *priv; 893 struct pci_dev *ch0mm, *ch1mm; 894 int ret = 0; 895 u32 dw; 896 int ranksperch; 897 898 if (PCI_FUNC(pdev->devfn) != 1) 899 return -ENODEV; 900 901 rc = pci_enable_device(pdev); 902 if (rc < 0) { 903 ret = rc; 904 goto bail; 905 } 906 907 /* ECC enabled? */ 908 pci_read_config_dword(pdev, I5100_MC, &dw); 909 if (!i5100_mc_errdeten(dw)) { 910 printk(KERN_INFO "i5100_edac: ECC not enabled.\n"); 911 ret = -ENODEV; 912 goto bail_pdev; 913 } 914 915 /* figure out how many ranks, from strapped state of 48GB_Mode input */ 916 pci_read_config_dword(pdev, I5100_MS, &dw); 917 ranksperch = !!(dw & (1 << 8)) * 2 + 4; 918 919 /* enable error reporting... */ 920 pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw); 921 dw &= ~I5100_FERR_NF_MEM_ANY_MASK; 922 pci_write_config_dword(pdev, I5100_EMASK_MEM, dw); 923 924 /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */ 925 ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL, 926 PCI_DEVICE_ID_INTEL_5100_21, 0); 927 if (!ch0mm) { 928 ret = -ENODEV; 929 goto bail_pdev; 930 } 931 932 rc = pci_enable_device(ch0mm); 933 if (rc < 0) { 934 ret = rc; 935 goto bail_ch0; 936 } 937 938 /* device 22, func 0, Channel 1 Memory Map, Error Flag/Mask, etc... */ 939 ch1mm = pci_get_device_func(PCI_VENDOR_ID_INTEL, 940 PCI_DEVICE_ID_INTEL_5100_22, 0); 941 if (!ch1mm) { 942 ret = -ENODEV; 943 goto bail_disable_ch0; 944 } 945 946 rc = pci_enable_device(ch1mm); 947 if (rc < 0) { 948 ret = rc; 949 goto bail_ch1; 950 } 951 952 mci = edac_mc_alloc(sizeof(*priv), ranksperch * 2, 1, 0); 953 if (!mci) { 954 ret = -ENOMEM; 955 goto bail_disable_ch1; 956 } 957 958 mci->dev = &pdev->dev; 959 960 priv = mci->pvt_info; 961 priv->ranksperchan = ranksperch; 962 priv->mc = pdev; 963 priv->ch0mm = ch0mm; 964 priv->ch1mm = ch1mm; 965 966 INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing); 967 968 /* If scrubbing was already enabled by the bios, start maintaining it */ 969 pci_read_config_dword(pdev, I5100_MC, &dw); 970 if (i5100_mc_scrben(dw)) { 971 priv->scrub_enable = 1; 972 schedule_delayed_work(&(priv->i5100_scrubbing), 973 I5100_SCRUB_REFRESH_RATE); 974 } 975 976 i5100_init_dimm_layout(pdev, mci); 977 i5100_init_interleaving(pdev, mci); 978 979 mci->mtype_cap = MEM_FLAG_FB_DDR2; 980 mci->edac_ctl_cap = EDAC_FLAG_SECDED; 981 mci->edac_cap = EDAC_FLAG_SECDED; 982 mci->mod_name = "i5100_edac.c"; 983 mci->mod_ver = "not versioned"; 984 mci->ctl_name = "i5100"; 985 mci->dev_name = pci_name(pdev); 986 mci->ctl_page_to_phys = NULL; 987 988 mci->edac_check = i5100_check_error; 989 mci->set_sdram_scrub_rate = i5100_set_scrub_rate; 990 mci->get_sdram_scrub_rate = i5100_get_scrub_rate; 991 992 i5100_init_csrows(mci); 993 994 /* this strange construction seems to be in every driver, dunno why */ 995 switch (edac_op_state) { 996 case EDAC_OPSTATE_POLL: 997 case EDAC_OPSTATE_NMI: 998 break; 999 default: 1000 edac_op_state = EDAC_OPSTATE_POLL; 1001 break; 1002 } 1003 1004 if (edac_mc_add_mc(mci)) { 1005 ret = -ENODEV; 1006 goto bail_scrub; 1007 } 1008 1009 return ret; 1010 1011 bail_scrub: 1012 priv->scrub_enable = 0; 1013 cancel_delayed_work_sync(&(priv->i5100_scrubbing)); 1014 edac_mc_free(mci); 1015 1016 bail_disable_ch1: 1017 pci_disable_device(ch1mm); 1018 1019 bail_ch1: 1020 pci_dev_put(ch1mm); 1021 1022 bail_disable_ch0: 1023 pci_disable_device(ch0mm); 1024 1025 bail_ch0: 1026 pci_dev_put(ch0mm); 1027 1028 bail_pdev: 1029 pci_disable_device(pdev); 1030 1031 bail: 1032 return ret; 1033 } 1034 1035 static void __devexit i5100_remove_one(struct pci_dev *pdev) 1036 { 1037 struct mem_ctl_info *mci; 1038 struct i5100_priv *priv; 1039 1040 mci = edac_mc_del_mc(&pdev->dev); 1041 1042 if (!mci) 1043 return; 1044 1045 priv = mci->pvt_info; 1046 1047 priv->scrub_enable = 0; 1048 cancel_delayed_work_sync(&(priv->i5100_scrubbing)); 1049 1050 pci_disable_device(pdev); 1051 pci_disable_device(priv->ch0mm); 1052 pci_disable_device(priv->ch1mm); 1053 pci_dev_put(priv->ch0mm); 1054 pci_dev_put(priv->ch1mm); 1055 1056 edac_mc_free(mci); 1057 } 1058 1059 static const struct pci_device_id i5100_pci_tbl[] __devinitdata = { 1060 /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */ 1061 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) }, 1062 { 0, } 1063 }; 1064 MODULE_DEVICE_TABLE(pci, i5100_pci_tbl); 1065 1066 static struct pci_driver i5100_driver = { 1067 .name = KBUILD_BASENAME, 1068 .probe = i5100_init_one, 1069 .remove = __devexit_p(i5100_remove_one), 1070 .id_table = i5100_pci_tbl, 1071 }; 1072 1073 static int __init i5100_init(void) 1074 { 1075 int pci_rc; 1076 1077 pci_rc = pci_register_driver(&i5100_driver); 1078 1079 return (pci_rc < 0) ? pci_rc : 0; 1080 } 1081 1082 static void __exit i5100_exit(void) 1083 { 1084 pci_unregister_driver(&i5100_driver); 1085 } 1086 1087 module_init(i5100_init); 1088 module_exit(i5100_exit); 1089 1090 MODULE_LICENSE("GPL"); 1091 MODULE_AUTHOR 1092 ("Arthur Jones <ajones@riverbed.com>"); 1093 MODULE_DESCRIPTION("MC Driver for Intel I5100 memory controllers"); 1094