1 /* 2 * Intel 3000/3010 Memory Controller kernel module 3 * Copyright (C) 2007 Akamai Technologies, Inc. 4 * Shamelessly copied from: 5 * Intel D82875P Memory Controller kernel module 6 * (C) 2003 Linux Networx (http://lnxi.com) 7 * 8 * This file may be distributed under the terms of the 9 * GNU General Public License. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/init.h> 14 #include <linux/pci.h> 15 #include <linux/pci_ids.h> 16 #include <linux/slab.h> 17 #include <linux/edac.h> 18 #include "edac_core.h" 19 20 #define I3000_REVISION "1.1" 21 22 #define EDAC_MOD_STR "i3000_edac" 23 24 #define I3000_RANKS 8 25 #define I3000_RANKS_PER_CHANNEL 4 26 #define I3000_CHANNELS 2 27 28 /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */ 29 30 #define I3000_MCHBAR 0x44 /* MCH Memory Mapped Register BAR */ 31 #define I3000_MCHBAR_MASK 0xffffc000 32 #define I3000_MMR_WINDOW_SIZE 16384 33 34 #define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b) 35 * 36 * 7:1 reserved 37 * 0 bit 32 of address 38 */ 39 #define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b) 40 * 41 * 31:7 address 42 * 6:1 reserved 43 * 0 Error channel 0/1 44 */ 45 #define I3000_DEAP_GRAIN (1 << 7) 46 47 /* 48 * Helper functions to decode the DEAP/EDEAP hardware registers. 49 * 50 * The type promotion here is deliberate; we're deriving an 51 * unsigned long pfn and offset from hardware regs which are u8/u32. 52 */ 53 54 static inline unsigned long deap_pfn(u8 edeap, u32 deap) 55 { 56 deap >>= PAGE_SHIFT; 57 deap |= (edeap & 1) << (32 - PAGE_SHIFT); 58 return deap; 59 } 60 61 static inline unsigned long deap_offset(u32 deap) 62 { 63 return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK; 64 } 65 66 static inline int deap_channel(u32 deap) 67 { 68 return deap & 1; 69 } 70 71 #define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b) 72 * 73 * 7:0 DRAM ECC Syndrome 74 */ 75 76 #define I3000_ERRSTS 0xc8 /* Error Status Register (16b) 77 * 78 * 15:12 reserved 79 * 11 MCH Thermal Sensor Event 80 * for SMI/SCI/SERR 81 * 10 reserved 82 * 9 LOCK to non-DRAM Memory Flag (LCKF) 83 * 8 Received Refresh Timeout Flag (RRTOF) 84 * 7:2 reserved 85 * 1 Multi-bit DRAM ECC Error Flag (DMERR) 86 * 0 Single-bit DRAM ECC Error Flag (DSERR) 87 */ 88 #define I3000_ERRSTS_BITS 0x0b03 /* bits which indicate errors */ 89 #define I3000_ERRSTS_UE 0x0002 90 #define I3000_ERRSTS_CE 0x0001 91 92 #define I3000_ERRCMD 0xca /* Error Command (16b) 93 * 94 * 15:12 reserved 95 * 11 SERR on MCH Thermal Sensor Event 96 * (TSESERR) 97 * 10 reserved 98 * 9 SERR on LOCK to non-DRAM Memory 99 * (LCKERR) 100 * 8 SERR on DRAM Refresh Timeout 101 * (DRTOERR) 102 * 7:2 reserved 103 * 1 SERR Multi-Bit DRAM ECC Error 104 * (DMERR) 105 * 0 SERR on Single-Bit ECC Error 106 * (DSERR) 107 */ 108 109 /* Intel MMIO register space - device 0 function 0 - MMR space */ 110 111 #define I3000_DRB_SHIFT 25 /* 32MiB grain */ 112 113 #define I3000_C0DRB 0x100 /* Channel 0 DRAM Rank Boundary (8b x 4) 114 * 115 * 7:0 Channel 0 DRAM Rank Boundary Address 116 */ 117 #define I3000_C1DRB 0x180 /* Channel 1 DRAM Rank Boundary (8b x 4) 118 * 119 * 7:0 Channel 1 DRAM Rank Boundary Address 120 */ 121 122 #define I3000_C0DRA 0x108 /* Channel 0 DRAM Rank Attribute (8b x 2) 123 * 124 * 7 reserved 125 * 6:4 DRAM odd Rank Attribute 126 * 3 reserved 127 * 2:0 DRAM even Rank Attribute 128 * 129 * Each attribute defines the page 130 * size of the corresponding rank: 131 * 000: unpopulated 132 * 001: reserved 133 * 010: 4 KB 134 * 011: 8 KB 135 * 100: 16 KB 136 * Others: reserved 137 */ 138 #define I3000_C1DRA 0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */ 139 140 static inline unsigned char odd_rank_attrib(unsigned char dra) 141 { 142 return (dra & 0x70) >> 4; 143 } 144 145 static inline unsigned char even_rank_attrib(unsigned char dra) 146 { 147 return dra & 0x07; 148 } 149 150 #define I3000_C0DRC0 0x120 /* DRAM Controller Mode 0 (32b) 151 * 152 * 31:30 reserved 153 * 29 Initialization Complete (IC) 154 * 28:11 reserved 155 * 10:8 Refresh Mode Select (RMS) 156 * 7 reserved 157 * 6:4 Mode Select (SMS) 158 * 3:2 reserved 159 * 1:0 DRAM Type (DT) 160 */ 161 162 #define I3000_C0DRC1 0x124 /* DRAM Controller Mode 1 (32b) 163 * 164 * 31 Enhanced Addressing Enable (ENHADE) 165 * 30:0 reserved 166 */ 167 168 enum i3000p_chips { 169 I3000 = 0, 170 }; 171 172 struct i3000_dev_info { 173 const char *ctl_name; 174 }; 175 176 struct i3000_error_info { 177 u16 errsts; 178 u8 derrsyn; 179 u8 edeap; 180 u32 deap; 181 u16 errsts2; 182 }; 183 184 static const struct i3000_dev_info i3000_devs[] = { 185 [I3000] = { 186 .ctl_name = "i3000"}, 187 }; 188 189 static struct pci_dev *mci_pdev; 190 static int i3000_registered = 1; 191 static struct edac_pci_ctl_info *i3000_pci; 192 193 static void i3000_get_error_info(struct mem_ctl_info *mci, 194 struct i3000_error_info *info) 195 { 196 struct pci_dev *pdev; 197 198 pdev = to_pci_dev(mci->dev); 199 200 /* 201 * This is a mess because there is no atomic way to read all the 202 * registers at once and the registers can transition from CE being 203 * overwritten by UE. 204 */ 205 pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts); 206 if (!(info->errsts & I3000_ERRSTS_BITS)) 207 return; 208 pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap); 209 pci_read_config_dword(pdev, I3000_DEAP, &info->deap); 210 pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn); 211 pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts2); 212 213 /* 214 * If the error is the same for both reads then the first set 215 * of reads is valid. If there is a change then there is a CE 216 * with no info and the second set of reads is valid and 217 * should be UE info. 218 */ 219 if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) { 220 pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap); 221 pci_read_config_dword(pdev, I3000_DEAP, &info->deap); 222 pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn); 223 } 224 225 /* 226 * Clear any error bits. 227 * (Yes, we really clear bits by writing 1 to them.) 228 */ 229 pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS, 230 I3000_ERRSTS_BITS); 231 } 232 233 static int i3000_process_error_info(struct mem_ctl_info *mci, 234 struct i3000_error_info *info, 235 int handle_errors) 236 { 237 int row, multi_chan, channel; 238 unsigned long pfn, offset; 239 240 multi_chan = mci->csrows[0].nr_channels - 1; 241 242 if (!(info->errsts & I3000_ERRSTS_BITS)) 243 return 0; 244 245 if (!handle_errors) 246 return 1; 247 248 if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) { 249 edac_mc_handle_ce_no_info(mci, "UE overwrote CE"); 250 info->errsts = info->errsts2; 251 } 252 253 pfn = deap_pfn(info->edeap, info->deap); 254 offset = deap_offset(info->deap); 255 channel = deap_channel(info->deap); 256 257 row = edac_mc_find_csrow_by_page(mci, pfn); 258 259 if (info->errsts & I3000_ERRSTS_UE) 260 edac_mc_handle_ue(mci, pfn, offset, row, "i3000 UE"); 261 else 262 edac_mc_handle_ce(mci, pfn, offset, info->derrsyn, row, 263 multi_chan ? channel : 0, "i3000 CE"); 264 265 return 1; 266 } 267 268 static void i3000_check(struct mem_ctl_info *mci) 269 { 270 struct i3000_error_info info; 271 272 debugf1("MC%d: %s()\n", mci->mc_idx, __func__); 273 i3000_get_error_info(mci, &info); 274 i3000_process_error_info(mci, &info, 1); 275 } 276 277 static int i3000_is_interleaved(const unsigned char *c0dra, 278 const unsigned char *c1dra, 279 const unsigned char *c0drb, 280 const unsigned char *c1drb) 281 { 282 int i; 283 284 /* 285 * If the channels aren't populated identically then 286 * we're not interleaved. 287 */ 288 for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++) 289 if (odd_rank_attrib(c0dra[i]) != odd_rank_attrib(c1dra[i]) || 290 even_rank_attrib(c0dra[i]) != 291 even_rank_attrib(c1dra[i])) 292 return 0; 293 294 /* 295 * If the rank boundaries for the two channels are different 296 * then we're not interleaved. 297 */ 298 for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) 299 if (c0drb[i] != c1drb[i]) 300 return 0; 301 302 return 1; 303 } 304 305 static int i3000_probe1(struct pci_dev *pdev, int dev_idx) 306 { 307 int rc; 308 int i; 309 struct mem_ctl_info *mci = NULL; 310 unsigned long last_cumul_size; 311 int interleaved, nr_channels; 312 unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS]; 313 unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2]; 314 unsigned char *c0drb = drb, *c1drb = &drb[I3000_RANKS_PER_CHANNEL]; 315 unsigned long mchbar; 316 void __iomem *window; 317 318 debugf0("MC: %s()\n", __func__); 319 320 pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar); 321 mchbar &= I3000_MCHBAR_MASK; 322 window = ioremap_nocache(mchbar, I3000_MMR_WINDOW_SIZE); 323 if (!window) { 324 printk(KERN_ERR "i3000: cannot map mmio space at 0x%lx\n", 325 mchbar); 326 return -ENODEV; 327 } 328 329 c0dra[0] = readb(window + I3000_C0DRA + 0); /* ranks 0,1 */ 330 c0dra[1] = readb(window + I3000_C0DRA + 1); /* ranks 2,3 */ 331 c1dra[0] = readb(window + I3000_C1DRA + 0); /* ranks 0,1 */ 332 c1dra[1] = readb(window + I3000_C1DRA + 1); /* ranks 2,3 */ 333 334 for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) { 335 c0drb[i] = readb(window + I3000_C0DRB + i); 336 c1drb[i] = readb(window + I3000_C1DRB + i); 337 } 338 339 iounmap(window); 340 341 /* 342 * Figure out how many channels we have. 343 * 344 * If we have what the datasheet calls "asymmetric channels" 345 * (essentially the same as what was called "virtual single 346 * channel mode" in the i82875) then it's a single channel as 347 * far as EDAC is concerned. 348 */ 349 interleaved = i3000_is_interleaved(c0dra, c1dra, c0drb, c1drb); 350 nr_channels = interleaved ? 2 : 1; 351 mci = edac_mc_alloc(0, I3000_RANKS / nr_channels, nr_channels, 0); 352 if (!mci) 353 return -ENOMEM; 354 355 debugf3("MC: %s(): init mci\n", __func__); 356 357 mci->dev = &pdev->dev; 358 mci->mtype_cap = MEM_FLAG_DDR2; 359 360 mci->edac_ctl_cap = EDAC_FLAG_SECDED; 361 mci->edac_cap = EDAC_FLAG_SECDED; 362 363 mci->mod_name = EDAC_MOD_STR; 364 mci->mod_ver = I3000_REVISION; 365 mci->ctl_name = i3000_devs[dev_idx].ctl_name; 366 mci->dev_name = pci_name(pdev); 367 mci->edac_check = i3000_check; 368 mci->ctl_page_to_phys = NULL; 369 370 /* 371 * The dram rank boundary (DRB) reg values are boundary addresses 372 * for each DRAM rank with a granularity of 32MB. DRB regs are 373 * cumulative; the last one will contain the total memory 374 * contained in all ranks. 375 * 376 * If we're in interleaved mode then we're only walking through 377 * the ranks of controller 0, so we double all the values we see. 378 */ 379 for (last_cumul_size = i = 0; i < mci->nr_csrows; i++) { 380 u8 value; 381 u32 cumul_size; 382 struct csrow_info *csrow = &mci->csrows[i]; 383 384 value = drb[i]; 385 cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT); 386 if (interleaved) 387 cumul_size <<= 1; 388 debugf3("MC: %s(): (%d) cumul_size 0x%x\n", 389 __func__, i, cumul_size); 390 if (cumul_size == last_cumul_size) { 391 csrow->mtype = MEM_EMPTY; 392 continue; 393 } 394 395 csrow->first_page = last_cumul_size; 396 csrow->last_page = cumul_size - 1; 397 csrow->nr_pages = cumul_size - last_cumul_size; 398 last_cumul_size = cumul_size; 399 csrow->grain = I3000_DEAP_GRAIN; 400 csrow->mtype = MEM_DDR2; 401 csrow->dtype = DEV_UNKNOWN; 402 csrow->edac_mode = EDAC_UNKNOWN; 403 } 404 405 /* 406 * Clear any error bits. 407 * (Yes, we really clear bits by writing 1 to them.) 408 */ 409 pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS, 410 I3000_ERRSTS_BITS); 411 412 rc = -ENODEV; 413 if (edac_mc_add_mc(mci)) { 414 debugf3("MC: %s(): failed edac_mc_add_mc()\n", __func__); 415 goto fail; 416 } 417 418 /* allocating generic PCI control info */ 419 i3000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); 420 if (!i3000_pci) { 421 printk(KERN_WARNING 422 "%s(): Unable to create PCI control\n", 423 __func__); 424 printk(KERN_WARNING 425 "%s(): PCI error report via EDAC not setup\n", 426 __func__); 427 } 428 429 /* get this far and it's successful */ 430 debugf3("MC: %s(): success\n", __func__); 431 return 0; 432 433 fail: 434 if (mci) 435 edac_mc_free(mci); 436 437 return rc; 438 } 439 440 /* returns count (>= 0), or negative on error */ 441 static int __devinit i3000_init_one(struct pci_dev *pdev, 442 const struct pci_device_id *ent) 443 { 444 int rc; 445 446 debugf0("MC: %s()\n", __func__); 447 448 if (pci_enable_device(pdev) < 0) 449 return -EIO; 450 451 rc = i3000_probe1(pdev, ent->driver_data); 452 if (!mci_pdev) 453 mci_pdev = pci_dev_get(pdev); 454 455 return rc; 456 } 457 458 static void __devexit i3000_remove_one(struct pci_dev *pdev) 459 { 460 struct mem_ctl_info *mci; 461 462 debugf0("%s()\n", __func__); 463 464 if (i3000_pci) 465 edac_pci_release_generic_ctl(i3000_pci); 466 467 mci = edac_mc_del_mc(&pdev->dev); 468 if (!mci) 469 return; 470 471 edac_mc_free(mci); 472 } 473 474 static const struct pci_device_id i3000_pci_tbl[] __devinitdata = { 475 { 476 PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 477 I3000}, 478 { 479 0, 480 } /* 0 terminated list. */ 481 }; 482 483 MODULE_DEVICE_TABLE(pci, i3000_pci_tbl); 484 485 static struct pci_driver i3000_driver = { 486 .name = EDAC_MOD_STR, 487 .probe = i3000_init_one, 488 .remove = __devexit_p(i3000_remove_one), 489 .id_table = i3000_pci_tbl, 490 }; 491 492 static int __init i3000_init(void) 493 { 494 int pci_rc; 495 496 debugf3("MC: %s()\n", __func__); 497 498 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 499 opstate_init(); 500 501 pci_rc = pci_register_driver(&i3000_driver); 502 if (pci_rc < 0) 503 goto fail0; 504 505 if (!mci_pdev) { 506 i3000_registered = 0; 507 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 508 PCI_DEVICE_ID_INTEL_3000_HB, NULL); 509 if (!mci_pdev) { 510 debugf0("i3000 pci_get_device fail\n"); 511 pci_rc = -ENODEV; 512 goto fail1; 513 } 514 515 pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl); 516 if (pci_rc < 0) { 517 debugf0("i3000 init fail\n"); 518 pci_rc = -ENODEV; 519 goto fail1; 520 } 521 } 522 523 return 0; 524 525 fail1: 526 pci_unregister_driver(&i3000_driver); 527 528 fail0: 529 if (mci_pdev) 530 pci_dev_put(mci_pdev); 531 532 return pci_rc; 533 } 534 535 static void __exit i3000_exit(void) 536 { 537 debugf3("MC: %s()\n", __func__); 538 539 pci_unregister_driver(&i3000_driver); 540 if (!i3000_registered) { 541 i3000_remove_one(mci_pdev); 542 pci_dev_put(mci_pdev); 543 } 544 } 545 546 module_init(i3000_init); 547 module_exit(i3000_exit); 548 549 MODULE_LICENSE("GPL"); 550 MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott"); 551 MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers"); 552 553 module_param(edac_op_state, int, 0444); 554 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 555