1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Intel(R) 10nm server memory controller. 4 * Copyright (c) 2019, Intel Corporation. 5 * 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/io.h> 10 #include <asm/cpu_device_id.h> 11 #include <asm/intel-family.h> 12 #include <asm/mce.h> 13 #include "edac_module.h" 14 #include "skx_common.h" 15 16 #define I10NM_REVISION "v0.0.5" 17 #define EDAC_MOD_STR "i10nm_edac" 18 19 /* Debug macros */ 20 #define i10nm_printk(level, fmt, arg...) \ 21 edac_printk(level, "i10nm", fmt, ##arg) 22 23 #define I10NM_GET_SCK_BAR(d, reg) \ 24 pci_read_config_dword((d)->uracu, 0xd0, &(reg)) 25 #define I10NM_GET_IMC_BAR(d, i, reg) \ 26 pci_read_config_dword((d)->uracu, 0xd8 + (i) * 4, &(reg)) 27 #define I10NM_GET_SAD(d, offset, i, reg)\ 28 pci_read_config_dword((d)->sad_all, (offset) + (i) * 8, &(reg)) 29 #define I10NM_GET_HBM_IMC_BAR(d, reg) \ 30 pci_read_config_dword((d)->uracu, 0xd4, &(reg)) 31 #define I10NM_GET_CAPID3_CFG(d, reg) \ 32 pci_read_config_dword((d)->pcu_cr3, 0x90, &(reg)) 33 #define I10NM_GET_DIMMMTR(m, i, j) \ 34 readl((m)->mbase + ((m)->hbm_mc ? 0x80c : 0x2080c) + \ 35 (i) * (m)->chan_mmio_sz + (j) * 4) 36 #define I10NM_GET_MCDDRTCFG(m, i) \ 37 readl((m)->mbase + ((m)->hbm_mc ? 0x970 : 0x20970) + \ 38 (i) * (m)->chan_mmio_sz) 39 #define I10NM_GET_MCMTR(m, i) \ 40 readl((m)->mbase + ((m)->hbm_mc ? 0xef8 : 0x20ef8) + \ 41 (i) * (m)->chan_mmio_sz) 42 #define I10NM_GET_AMAP(m, i) \ 43 readl((m)->mbase + ((m)->hbm_mc ? 0x814 : 0x20814) + \ 44 (i) * (m)->chan_mmio_sz) 45 #define I10NM_GET_REG32(m, i, offset) \ 46 readl((m)->mbase + (i) * (m)->chan_mmio_sz + (offset)) 47 #define I10NM_GET_REG64(m, i, offset) \ 48 readq((m)->mbase + (i) * (m)->chan_mmio_sz + (offset)) 49 #define I10NM_SET_REG32(m, i, offset, v) \ 50 writel(v, (m)->mbase + (i) * (m)->chan_mmio_sz + (offset)) 51 52 #define I10NM_GET_SCK_MMIO_BASE(reg) (GET_BITFIELD(reg, 0, 28) << 23) 53 #define I10NM_GET_IMC_MMIO_OFFSET(reg) (GET_BITFIELD(reg, 0, 10) << 12) 54 #define I10NM_GET_IMC_MMIO_SIZE(reg) ((GET_BITFIELD(reg, 13, 23) - \ 55 GET_BITFIELD(reg, 0, 10) + 1) << 12) 56 #define I10NM_GET_HBM_IMC_MMIO_OFFSET(reg) \ 57 ((GET_BITFIELD(reg, 0, 10) << 12) + 0x140000) 58 59 #define I10NM_HBM_IMC_MMIO_SIZE 0x9000 60 #define I10NM_IS_HBM_PRESENT(reg) GET_BITFIELD(reg, 27, 30) 61 #define I10NM_IS_HBM_IMC(reg) GET_BITFIELD(reg, 29, 29) 62 63 #define I10NM_MAX_SAD 16 64 #define I10NM_SAD_ENABLE(reg) GET_BITFIELD(reg, 0, 0) 65 #define I10NM_SAD_NM_CACHEABLE(reg) GET_BITFIELD(reg, 5, 5) 66 67 #define RETRY_RD_ERR_LOG_UC BIT(1) 68 #define RETRY_RD_ERR_LOG_NOOVER BIT(14) 69 #define RETRY_RD_ERR_LOG_EN BIT(15) 70 #define RETRY_RD_ERR_LOG_NOOVER_UC (BIT(14) | BIT(1)) 71 #define RETRY_RD_ERR_LOG_OVER_UC_V (BIT(2) | BIT(1) | BIT(0)) 72 73 static struct list_head *i10nm_edac_list; 74 75 static struct res_config *res_cfg; 76 static int retry_rd_err_log; 77 static int decoding_via_mca; 78 static bool mem_cfg_2lm; 79 80 static u32 offsets_scrub_icx[] = {0x22c60, 0x22c54, 0x22c5c, 0x22c58, 0x22c28, 0x20ed8}; 81 static u32 offsets_scrub_spr[] = {0x22c60, 0x22c54, 0x22f08, 0x22c58, 0x22c28, 0x20ed8}; 82 static u32 offsets_scrub_spr_hbm0[] = {0x2860, 0x2854, 0x2b08, 0x2858, 0x2828, 0x0ed8}; 83 static u32 offsets_scrub_spr_hbm1[] = {0x2c60, 0x2c54, 0x2f08, 0x2c58, 0x2c28, 0x0fa8}; 84 static u32 offsets_demand_icx[] = {0x22e54, 0x22e60, 0x22e64, 0x22e58, 0x22e5c, 0x20ee0}; 85 static u32 offsets_demand_spr[] = {0x22e54, 0x22e60, 0x22f10, 0x22e58, 0x22e5c, 0x20ee0}; 86 static u32 offsets_demand2_spr[] = {0x22c70, 0x22d80, 0x22f18, 0x22d58, 0x22c64, 0x20f10}; 87 static u32 offsets_demand_spr_hbm0[] = {0x2a54, 0x2a60, 0x2b10, 0x2a58, 0x2a5c, 0x0ee0}; 88 static u32 offsets_demand_spr_hbm1[] = {0x2e54, 0x2e60, 0x2f10, 0x2e58, 0x2e5c, 0x0fb0}; 89 90 static void __enable_retry_rd_err_log(struct skx_imc *imc, int chan, bool enable, 91 u32 *offsets_scrub, u32 *offsets_demand, 92 u32 *offsets_demand2) 93 { 94 u32 s, d, d2; 95 96 s = I10NM_GET_REG32(imc, chan, offsets_scrub[0]); 97 d = I10NM_GET_REG32(imc, chan, offsets_demand[0]); 98 if (offsets_demand2) 99 d2 = I10NM_GET_REG32(imc, chan, offsets_demand2[0]); 100 101 if (enable) { 102 /* Save default configurations */ 103 imc->chan[chan].retry_rd_err_log_s = s; 104 imc->chan[chan].retry_rd_err_log_d = d; 105 if (offsets_demand2) 106 imc->chan[chan].retry_rd_err_log_d2 = d2; 107 108 s &= ~RETRY_RD_ERR_LOG_NOOVER_UC; 109 s |= RETRY_RD_ERR_LOG_EN; 110 d &= ~RETRY_RD_ERR_LOG_NOOVER_UC; 111 d |= RETRY_RD_ERR_LOG_EN; 112 113 if (offsets_demand2) { 114 d2 &= ~RETRY_RD_ERR_LOG_UC; 115 d2 |= RETRY_RD_ERR_LOG_NOOVER; 116 d2 |= RETRY_RD_ERR_LOG_EN; 117 } 118 } else { 119 /* Restore default configurations */ 120 if (imc->chan[chan].retry_rd_err_log_s & RETRY_RD_ERR_LOG_UC) 121 s |= RETRY_RD_ERR_LOG_UC; 122 if (imc->chan[chan].retry_rd_err_log_s & RETRY_RD_ERR_LOG_NOOVER) 123 s |= RETRY_RD_ERR_LOG_NOOVER; 124 if (!(imc->chan[chan].retry_rd_err_log_s & RETRY_RD_ERR_LOG_EN)) 125 s &= ~RETRY_RD_ERR_LOG_EN; 126 if (imc->chan[chan].retry_rd_err_log_d & RETRY_RD_ERR_LOG_UC) 127 d |= RETRY_RD_ERR_LOG_UC; 128 if (imc->chan[chan].retry_rd_err_log_d & RETRY_RD_ERR_LOG_NOOVER) 129 d |= RETRY_RD_ERR_LOG_NOOVER; 130 if (!(imc->chan[chan].retry_rd_err_log_d & RETRY_RD_ERR_LOG_EN)) 131 d &= ~RETRY_RD_ERR_LOG_EN; 132 133 if (offsets_demand2) { 134 if (imc->chan[chan].retry_rd_err_log_d2 & RETRY_RD_ERR_LOG_UC) 135 d2 |= RETRY_RD_ERR_LOG_UC; 136 if (!(imc->chan[chan].retry_rd_err_log_d2 & RETRY_RD_ERR_LOG_NOOVER)) 137 d2 &= ~RETRY_RD_ERR_LOG_NOOVER; 138 if (!(imc->chan[chan].retry_rd_err_log_d2 & RETRY_RD_ERR_LOG_EN)) 139 d2 &= ~RETRY_RD_ERR_LOG_EN; 140 } 141 } 142 143 I10NM_SET_REG32(imc, chan, offsets_scrub[0], s); 144 I10NM_SET_REG32(imc, chan, offsets_demand[0], d); 145 if (offsets_demand2) 146 I10NM_SET_REG32(imc, chan, offsets_demand2[0], d2); 147 } 148 149 static void enable_retry_rd_err_log(bool enable) 150 { 151 struct skx_imc *imc; 152 struct skx_dev *d; 153 int i, j; 154 155 edac_dbg(2, "\n"); 156 157 list_for_each_entry(d, i10nm_edac_list, list) 158 for (i = 0; i < I10NM_NUM_IMC; i++) { 159 imc = &d->imc[i]; 160 if (!imc->mbase) 161 continue; 162 163 for (j = 0; j < I10NM_NUM_CHANNELS; j++) { 164 if (imc->hbm_mc) { 165 __enable_retry_rd_err_log(imc, j, enable, 166 res_cfg->offsets_scrub_hbm0, 167 res_cfg->offsets_demand_hbm0, 168 NULL); 169 __enable_retry_rd_err_log(imc, j, enable, 170 res_cfg->offsets_scrub_hbm1, 171 res_cfg->offsets_demand_hbm1, 172 NULL); 173 } else { 174 __enable_retry_rd_err_log(imc, j, enable, 175 res_cfg->offsets_scrub, 176 res_cfg->offsets_demand, 177 res_cfg->offsets_demand2); 178 } 179 } 180 } 181 } 182 183 static void show_retry_rd_err_log(struct decoded_addr *res, char *msg, 184 int len, bool scrub_err) 185 { 186 struct skx_imc *imc = &res->dev->imc[res->imc]; 187 u32 log0, log1, log2, log3, log4; 188 u32 corr0, corr1, corr2, corr3; 189 u32 lxg0, lxg1, lxg3, lxg4; 190 u32 *xffsets = NULL; 191 u64 log2a, log5; 192 u64 lxg2a, lxg5; 193 u32 *offsets; 194 int n, pch; 195 196 if (!imc->mbase) 197 return; 198 199 if (imc->hbm_mc) { 200 pch = res->cs & 1; 201 202 if (pch) 203 offsets = scrub_err ? res_cfg->offsets_scrub_hbm1 : 204 res_cfg->offsets_demand_hbm1; 205 else 206 offsets = scrub_err ? res_cfg->offsets_scrub_hbm0 : 207 res_cfg->offsets_demand_hbm0; 208 } else { 209 if (scrub_err) { 210 offsets = res_cfg->offsets_scrub; 211 } else { 212 offsets = res_cfg->offsets_demand; 213 xffsets = res_cfg->offsets_demand2; 214 } 215 } 216 217 log0 = I10NM_GET_REG32(imc, res->channel, offsets[0]); 218 log1 = I10NM_GET_REG32(imc, res->channel, offsets[1]); 219 log3 = I10NM_GET_REG32(imc, res->channel, offsets[3]); 220 log4 = I10NM_GET_REG32(imc, res->channel, offsets[4]); 221 log5 = I10NM_GET_REG64(imc, res->channel, offsets[5]); 222 223 if (xffsets) { 224 lxg0 = I10NM_GET_REG32(imc, res->channel, xffsets[0]); 225 lxg1 = I10NM_GET_REG32(imc, res->channel, xffsets[1]); 226 lxg3 = I10NM_GET_REG32(imc, res->channel, xffsets[3]); 227 lxg4 = I10NM_GET_REG32(imc, res->channel, xffsets[4]); 228 lxg5 = I10NM_GET_REG64(imc, res->channel, xffsets[5]); 229 } 230 231 if (res_cfg->type == SPR) { 232 log2a = I10NM_GET_REG64(imc, res->channel, offsets[2]); 233 n = snprintf(msg, len, " retry_rd_err_log[%.8x %.8x %.16llx %.8x %.8x %.16llx", 234 log0, log1, log2a, log3, log4, log5); 235 236 if (len - n > 0) { 237 if (xffsets) { 238 lxg2a = I10NM_GET_REG64(imc, res->channel, xffsets[2]); 239 n += snprintf(msg + n, len - n, " %.8x %.8x %.16llx %.8x %.8x %.16llx]", 240 lxg0, lxg1, lxg2a, lxg3, lxg4, lxg5); 241 } else { 242 n += snprintf(msg + n, len - n, "]"); 243 } 244 } 245 } else { 246 log2 = I10NM_GET_REG32(imc, res->channel, offsets[2]); 247 n = snprintf(msg, len, " retry_rd_err_log[%.8x %.8x %.8x %.8x %.8x %.16llx]", 248 log0, log1, log2, log3, log4, log5); 249 } 250 251 if (imc->hbm_mc) { 252 if (pch) { 253 corr0 = I10NM_GET_REG32(imc, res->channel, 0x2c18); 254 corr1 = I10NM_GET_REG32(imc, res->channel, 0x2c1c); 255 corr2 = I10NM_GET_REG32(imc, res->channel, 0x2c20); 256 corr3 = I10NM_GET_REG32(imc, res->channel, 0x2c24); 257 } else { 258 corr0 = I10NM_GET_REG32(imc, res->channel, 0x2818); 259 corr1 = I10NM_GET_REG32(imc, res->channel, 0x281c); 260 corr2 = I10NM_GET_REG32(imc, res->channel, 0x2820); 261 corr3 = I10NM_GET_REG32(imc, res->channel, 0x2824); 262 } 263 } else { 264 corr0 = I10NM_GET_REG32(imc, res->channel, 0x22c18); 265 corr1 = I10NM_GET_REG32(imc, res->channel, 0x22c1c); 266 corr2 = I10NM_GET_REG32(imc, res->channel, 0x22c20); 267 corr3 = I10NM_GET_REG32(imc, res->channel, 0x22c24); 268 } 269 270 if (len - n > 0) 271 snprintf(msg + n, len - n, 272 " correrrcnt[%.4x %.4x %.4x %.4x %.4x %.4x %.4x %.4x]", 273 corr0 & 0xffff, corr0 >> 16, 274 corr1 & 0xffff, corr1 >> 16, 275 corr2 & 0xffff, corr2 >> 16, 276 corr3 & 0xffff, corr3 >> 16); 277 278 /* Clear status bits */ 279 if (retry_rd_err_log == 2) { 280 if (log0 & RETRY_RD_ERR_LOG_OVER_UC_V) { 281 log0 &= ~RETRY_RD_ERR_LOG_OVER_UC_V; 282 I10NM_SET_REG32(imc, res->channel, offsets[0], log0); 283 } 284 285 if (xffsets && (lxg0 & RETRY_RD_ERR_LOG_OVER_UC_V)) { 286 lxg0 &= ~RETRY_RD_ERR_LOG_OVER_UC_V; 287 I10NM_SET_REG32(imc, res->channel, xffsets[0], lxg0); 288 } 289 } 290 } 291 292 static struct pci_dev *pci_get_dev_wrapper(int dom, unsigned int bus, 293 unsigned int dev, unsigned int fun) 294 { 295 struct pci_dev *pdev; 296 297 pdev = pci_get_domain_bus_and_slot(dom, bus, PCI_DEVFN(dev, fun)); 298 if (!pdev) { 299 edac_dbg(2, "No device %02x:%02x.%x\n", 300 bus, dev, fun); 301 return NULL; 302 } 303 304 if (unlikely(pci_enable_device(pdev) < 0)) { 305 edac_dbg(2, "Failed to enable device %02x:%02x.%x\n", 306 bus, dev, fun); 307 return NULL; 308 } 309 310 pci_dev_get(pdev); 311 312 return pdev; 313 } 314 315 static bool i10nm_check_2lm(struct res_config *cfg) 316 { 317 struct skx_dev *d; 318 u32 reg; 319 int i; 320 321 list_for_each_entry(d, i10nm_edac_list, list) { 322 d->sad_all = pci_get_dev_wrapper(d->seg, d->bus[1], 323 PCI_SLOT(cfg->sad_all_devfn), 324 PCI_FUNC(cfg->sad_all_devfn)); 325 if (!d->sad_all) 326 continue; 327 328 for (i = 0; i < I10NM_MAX_SAD; i++) { 329 I10NM_GET_SAD(d, cfg->sad_all_offset, i, reg); 330 if (I10NM_SAD_ENABLE(reg) && I10NM_SAD_NM_CACHEABLE(reg)) { 331 edac_dbg(2, "2-level memory configuration.\n"); 332 return true; 333 } 334 } 335 } 336 337 return false; 338 } 339 340 /* 341 * Check whether the error comes from DDRT by ICX/Tremont model specific error code. 342 * Refer to SDM vol3B 16.11.3 Intel IMC MC error codes for IA32_MCi_STATUS. 343 */ 344 static bool i10nm_mscod_is_ddrt(u32 mscod) 345 { 346 switch (mscod) { 347 case 0x0106: case 0x0107: 348 case 0x0800: case 0x0804: 349 case 0x0806 ... 0x0808: 350 case 0x080a ... 0x080e: 351 case 0x0810: case 0x0811: 352 case 0x0816: case 0x081e: 353 case 0x081f: 354 return true; 355 } 356 357 return false; 358 } 359 360 static bool i10nm_mc_decode_available(struct mce *mce) 361 { 362 u8 bank; 363 364 if (!decoding_via_mca || mem_cfg_2lm) 365 return false; 366 367 if ((mce->status & (MCI_STATUS_MISCV | MCI_STATUS_ADDRV)) 368 != (MCI_STATUS_MISCV | MCI_STATUS_ADDRV)) 369 return false; 370 371 bank = mce->bank; 372 373 switch (res_cfg->type) { 374 case I10NM: 375 if (bank < 13 || bank > 26) 376 return false; 377 378 /* DDRT errors can't be decoded from MCA bank registers */ 379 if (MCI_MISC_ECC_MODE(mce->misc) == MCI_MISC_ECC_DDRT) 380 return false; 381 382 if (i10nm_mscod_is_ddrt(MCI_STATUS_MSCOD(mce->status))) 383 return false; 384 385 /* Check whether one of {13,14,17,18,21,22,25,26} */ 386 return ((bank - 13) & BIT(1)) == 0; 387 default: 388 return false; 389 } 390 } 391 392 static bool i10nm_mc_decode(struct decoded_addr *res) 393 { 394 struct mce *m = res->mce; 395 struct skx_dev *d; 396 u8 bank; 397 398 if (!i10nm_mc_decode_available(m)) 399 return false; 400 401 list_for_each_entry(d, i10nm_edac_list, list) { 402 if (d->imc[0].src_id == m->socketid) { 403 res->socket = m->socketid; 404 res->dev = d; 405 break; 406 } 407 } 408 409 switch (res_cfg->type) { 410 case I10NM: 411 bank = m->bank - 13; 412 res->imc = bank / 4; 413 res->channel = bank % 2; 414 break; 415 default: 416 return false; 417 } 418 419 if (!res->dev) { 420 skx_printk(KERN_ERR, "No device for src_id %d imc %d\n", 421 m->socketid, res->imc); 422 return false; 423 } 424 425 res->column = GET_BITFIELD(m->misc, 9, 18) << 2; 426 res->row = GET_BITFIELD(m->misc, 19, 39); 427 res->bank_group = GET_BITFIELD(m->misc, 40, 41); 428 res->bank_address = GET_BITFIELD(m->misc, 42, 43); 429 res->bank_group |= GET_BITFIELD(m->misc, 44, 44) << 2; 430 res->rank = GET_BITFIELD(m->misc, 56, 58); 431 res->dimm = res->rank >> 2; 432 res->rank = res->rank % 4; 433 434 return true; 435 } 436 437 static int i10nm_get_ddr_munits(void) 438 { 439 struct pci_dev *mdev; 440 void __iomem *mbase; 441 unsigned long size; 442 struct skx_dev *d; 443 int i, j = 0; 444 u32 reg, off; 445 u64 base; 446 447 list_for_each_entry(d, i10nm_edac_list, list) { 448 d->util_all = pci_get_dev_wrapper(d->seg, d->bus[1], 29, 1); 449 if (!d->util_all) 450 return -ENODEV; 451 452 d->uracu = pci_get_dev_wrapper(d->seg, d->bus[0], 0, 1); 453 if (!d->uracu) 454 return -ENODEV; 455 456 if (I10NM_GET_SCK_BAR(d, reg)) { 457 i10nm_printk(KERN_ERR, "Failed to socket bar\n"); 458 return -ENODEV; 459 } 460 461 base = I10NM_GET_SCK_MMIO_BASE(reg); 462 edac_dbg(2, "socket%d mmio base 0x%llx (reg 0x%x)\n", 463 j++, base, reg); 464 465 for (i = 0; i < I10NM_NUM_DDR_IMC; i++) { 466 mdev = pci_get_dev_wrapper(d->seg, d->bus[0], 467 12 + i, 0); 468 if (i == 0 && !mdev) { 469 i10nm_printk(KERN_ERR, "No IMC found\n"); 470 return -ENODEV; 471 } 472 if (!mdev) 473 continue; 474 475 d->imc[i].mdev = mdev; 476 477 if (I10NM_GET_IMC_BAR(d, i, reg)) { 478 i10nm_printk(KERN_ERR, "Failed to get mc bar\n"); 479 return -ENODEV; 480 } 481 482 off = I10NM_GET_IMC_MMIO_OFFSET(reg); 483 size = I10NM_GET_IMC_MMIO_SIZE(reg); 484 edac_dbg(2, "mc%d mmio base 0x%llx size 0x%lx (reg 0x%x)\n", 485 i, base + off, size, reg); 486 487 mbase = ioremap(base + off, size); 488 if (!mbase) { 489 i10nm_printk(KERN_ERR, "Failed to ioremap 0x%llx\n", 490 base + off); 491 return -ENODEV; 492 } 493 494 d->imc[i].mbase = mbase; 495 } 496 } 497 498 return 0; 499 } 500 501 static bool i10nm_check_hbm_imc(struct skx_dev *d) 502 { 503 u32 reg; 504 505 if (I10NM_GET_CAPID3_CFG(d, reg)) { 506 i10nm_printk(KERN_ERR, "Failed to get capid3_cfg\n"); 507 return false; 508 } 509 510 return I10NM_IS_HBM_PRESENT(reg) != 0; 511 } 512 513 static int i10nm_get_hbm_munits(void) 514 { 515 struct pci_dev *mdev; 516 void __iomem *mbase; 517 u32 reg, off, mcmtr; 518 struct skx_dev *d; 519 int i, lmc; 520 u64 base; 521 522 list_for_each_entry(d, i10nm_edac_list, list) { 523 d->pcu_cr3 = pci_get_dev_wrapper(d->seg, d->bus[1], 30, 3); 524 if (!d->pcu_cr3) 525 return -ENODEV; 526 527 if (!i10nm_check_hbm_imc(d)) { 528 i10nm_printk(KERN_DEBUG, "No hbm memory\n"); 529 return -ENODEV; 530 } 531 532 if (I10NM_GET_SCK_BAR(d, reg)) { 533 i10nm_printk(KERN_ERR, "Failed to get socket bar\n"); 534 return -ENODEV; 535 } 536 base = I10NM_GET_SCK_MMIO_BASE(reg); 537 538 if (I10NM_GET_HBM_IMC_BAR(d, reg)) { 539 i10nm_printk(KERN_ERR, "Failed to get hbm mc bar\n"); 540 return -ENODEV; 541 } 542 base += I10NM_GET_HBM_IMC_MMIO_OFFSET(reg); 543 544 lmc = I10NM_NUM_DDR_IMC; 545 546 for (i = 0; i < I10NM_NUM_HBM_IMC; i++) { 547 mdev = pci_get_dev_wrapper(d->seg, d->bus[0], 548 12 + i / 4, 1 + i % 4); 549 if (i == 0 && !mdev) { 550 i10nm_printk(KERN_ERR, "No hbm mc found\n"); 551 return -ENODEV; 552 } 553 if (!mdev) 554 continue; 555 556 d->imc[lmc].mdev = mdev; 557 off = i * I10NM_HBM_IMC_MMIO_SIZE; 558 559 edac_dbg(2, "hbm mc%d mmio base 0x%llx size 0x%x\n", 560 lmc, base + off, I10NM_HBM_IMC_MMIO_SIZE); 561 562 mbase = ioremap(base + off, I10NM_HBM_IMC_MMIO_SIZE); 563 if (!mbase) { 564 pci_dev_put(d->imc[lmc].mdev); 565 d->imc[lmc].mdev = NULL; 566 567 i10nm_printk(KERN_ERR, "Failed to ioremap for hbm mc 0x%llx\n", 568 base + off); 569 return -ENOMEM; 570 } 571 572 d->imc[lmc].mbase = mbase; 573 d->imc[lmc].hbm_mc = true; 574 575 mcmtr = I10NM_GET_MCMTR(&d->imc[lmc], 0); 576 if (!I10NM_IS_HBM_IMC(mcmtr)) { 577 iounmap(d->imc[lmc].mbase); 578 d->imc[lmc].mbase = NULL; 579 d->imc[lmc].hbm_mc = false; 580 pci_dev_put(d->imc[lmc].mdev); 581 d->imc[lmc].mdev = NULL; 582 583 i10nm_printk(KERN_ERR, "This isn't an hbm mc!\n"); 584 return -ENODEV; 585 } 586 587 lmc++; 588 } 589 } 590 591 return 0; 592 } 593 594 static struct res_config i10nm_cfg0 = { 595 .type = I10NM, 596 .decs_did = 0x3452, 597 .busno_cfg_offset = 0xcc, 598 .ddr_chan_mmio_sz = 0x4000, 599 .sad_all_devfn = PCI_DEVFN(29, 0), 600 .sad_all_offset = 0x108, 601 .offsets_scrub = offsets_scrub_icx, 602 .offsets_demand = offsets_demand_icx, 603 }; 604 605 static struct res_config i10nm_cfg1 = { 606 .type = I10NM, 607 .decs_did = 0x3452, 608 .busno_cfg_offset = 0xd0, 609 .ddr_chan_mmio_sz = 0x4000, 610 .sad_all_devfn = PCI_DEVFN(29, 0), 611 .sad_all_offset = 0x108, 612 .offsets_scrub = offsets_scrub_icx, 613 .offsets_demand = offsets_demand_icx, 614 }; 615 616 static struct res_config spr_cfg = { 617 .type = SPR, 618 .decs_did = 0x3252, 619 .busno_cfg_offset = 0xd0, 620 .ddr_chan_mmio_sz = 0x8000, 621 .hbm_chan_mmio_sz = 0x4000, 622 .support_ddr5 = true, 623 .sad_all_devfn = PCI_DEVFN(10, 0), 624 .sad_all_offset = 0x300, 625 .offsets_scrub = offsets_scrub_spr, 626 .offsets_scrub_hbm0 = offsets_scrub_spr_hbm0, 627 .offsets_scrub_hbm1 = offsets_scrub_spr_hbm1, 628 .offsets_demand = offsets_demand_spr, 629 .offsets_demand2 = offsets_demand2_spr, 630 .offsets_demand_hbm0 = offsets_demand_spr_hbm0, 631 .offsets_demand_hbm1 = offsets_demand_spr_hbm1, 632 }; 633 634 static const struct x86_cpu_id i10nm_cpuids[] = { 635 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0), 636 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1), 637 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0), 638 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1), 639 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_D, X86_STEPPINGS(0x0, 0xf), &i10nm_cfg1), 640 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SAPPHIRERAPIDS_X, X86_STEPPINGS(0x0, 0xf), &spr_cfg), 641 {} 642 }; 643 MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids); 644 645 static bool i10nm_check_ecc(struct skx_imc *imc, int chan) 646 { 647 u32 mcmtr; 648 649 mcmtr = I10NM_GET_MCMTR(imc, chan); 650 edac_dbg(1, "ch%d mcmtr reg %x\n", chan, mcmtr); 651 652 return !!GET_BITFIELD(mcmtr, 2, 2); 653 } 654 655 static int i10nm_get_dimm_config(struct mem_ctl_info *mci, 656 struct res_config *cfg) 657 { 658 struct skx_pvt *pvt = mci->pvt_info; 659 struct skx_imc *imc = pvt->imc; 660 u32 mtr, amap, mcddrtcfg; 661 struct dimm_info *dimm; 662 int i, j, ndimms; 663 664 for (i = 0; i < imc->num_channels; i++) { 665 if (!imc->mbase) 666 continue; 667 668 ndimms = 0; 669 amap = I10NM_GET_AMAP(imc, i); 670 mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i); 671 for (j = 0; j < imc->num_dimms; j++) { 672 dimm = edac_get_dimm(mci, i, j, 0); 673 mtr = I10NM_GET_DIMMMTR(imc, i, j); 674 edac_dbg(1, "dimmmtr 0x%x mcddrtcfg 0x%x (mc%d ch%d dimm%d)\n", 675 mtr, mcddrtcfg, imc->mc, i, j); 676 677 if (IS_DIMM_PRESENT(mtr)) 678 ndimms += skx_get_dimm_info(mtr, 0, amap, dimm, 679 imc, i, j, cfg); 680 else if (IS_NVDIMM_PRESENT(mcddrtcfg, j)) 681 ndimms += skx_get_nvdimm_info(dimm, imc, i, j, 682 EDAC_MOD_STR); 683 } 684 if (ndimms && !i10nm_check_ecc(imc, i)) { 685 i10nm_printk(KERN_ERR, "ECC is disabled on imc %d channel %d\n", 686 imc->mc, i); 687 return -ENODEV; 688 } 689 } 690 691 return 0; 692 } 693 694 static struct notifier_block i10nm_mce_dec = { 695 .notifier_call = skx_mce_check_error, 696 .priority = MCE_PRIO_EDAC, 697 }; 698 699 #ifdef CONFIG_EDAC_DEBUG 700 /* 701 * Debug feature. 702 * Exercise the address decode logic by writing an address to 703 * /sys/kernel/debug/edac/i10nm_test/addr. 704 */ 705 static struct dentry *i10nm_test; 706 707 static int debugfs_u64_set(void *data, u64 val) 708 { 709 struct mce m; 710 711 pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val); 712 713 memset(&m, 0, sizeof(m)); 714 /* ADDRV + MemRd + Unknown channel */ 715 m.status = MCI_STATUS_ADDRV + 0x90; 716 /* One corrected error */ 717 m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT); 718 m.addr = val; 719 skx_mce_check_error(NULL, 0, &m); 720 721 return 0; 722 } 723 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n"); 724 725 static void setup_i10nm_debug(void) 726 { 727 i10nm_test = edac_debugfs_create_dir("i10nm_test"); 728 if (!i10nm_test) 729 return; 730 731 if (!edac_debugfs_create_file("addr", 0200, i10nm_test, 732 NULL, &fops_u64_wo)) { 733 debugfs_remove(i10nm_test); 734 i10nm_test = NULL; 735 } 736 } 737 738 static void teardown_i10nm_debug(void) 739 { 740 debugfs_remove_recursive(i10nm_test); 741 } 742 #else 743 static inline void setup_i10nm_debug(void) {} 744 static inline void teardown_i10nm_debug(void) {} 745 #endif /*CONFIG_EDAC_DEBUG*/ 746 747 static int __init i10nm_init(void) 748 { 749 u8 mc = 0, src_id = 0, node_id = 0; 750 const struct x86_cpu_id *id; 751 struct res_config *cfg; 752 const char *owner; 753 struct skx_dev *d; 754 int rc, i, off[3] = {0xd0, 0xc8, 0xcc}; 755 u64 tolm, tohm; 756 757 edac_dbg(2, "\n"); 758 759 owner = edac_get_owner(); 760 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR))) 761 return -EBUSY; 762 763 if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) 764 return -ENODEV; 765 766 id = x86_match_cpu(i10nm_cpuids); 767 if (!id) 768 return -ENODEV; 769 770 cfg = (struct res_config *)id->driver_data; 771 res_cfg = cfg; 772 773 rc = skx_get_hi_lo(0x09a2, off, &tolm, &tohm); 774 if (rc) 775 return rc; 776 777 rc = skx_get_all_bus_mappings(cfg, &i10nm_edac_list); 778 if (rc < 0) 779 goto fail; 780 if (rc == 0) { 781 i10nm_printk(KERN_ERR, "No memory controllers found\n"); 782 return -ENODEV; 783 } 784 785 mem_cfg_2lm = i10nm_check_2lm(cfg); 786 skx_set_mem_cfg(mem_cfg_2lm); 787 788 rc = i10nm_get_ddr_munits(); 789 790 if (i10nm_get_hbm_munits() && rc) 791 goto fail; 792 793 list_for_each_entry(d, i10nm_edac_list, list) { 794 rc = skx_get_src_id(d, 0xf8, &src_id); 795 if (rc < 0) 796 goto fail; 797 798 rc = skx_get_node_id(d, &node_id); 799 if (rc < 0) 800 goto fail; 801 802 edac_dbg(2, "src_id = %d node_id = %d\n", src_id, node_id); 803 for (i = 0; i < I10NM_NUM_IMC; i++) { 804 if (!d->imc[i].mdev) 805 continue; 806 807 d->imc[i].mc = mc++; 808 d->imc[i].lmc = i; 809 d->imc[i].src_id = src_id; 810 d->imc[i].node_id = node_id; 811 if (d->imc[i].hbm_mc) { 812 d->imc[i].chan_mmio_sz = cfg->hbm_chan_mmio_sz; 813 d->imc[i].num_channels = I10NM_NUM_HBM_CHANNELS; 814 d->imc[i].num_dimms = I10NM_NUM_HBM_DIMMS; 815 } else { 816 d->imc[i].chan_mmio_sz = cfg->ddr_chan_mmio_sz; 817 d->imc[i].num_channels = I10NM_NUM_DDR_CHANNELS; 818 d->imc[i].num_dimms = I10NM_NUM_DDR_DIMMS; 819 } 820 821 rc = skx_register_mci(&d->imc[i], d->imc[i].mdev, 822 "Intel_10nm Socket", EDAC_MOD_STR, 823 i10nm_get_dimm_config, cfg); 824 if (rc < 0) 825 goto fail; 826 } 827 } 828 829 rc = skx_adxl_get(); 830 if (rc) 831 goto fail; 832 833 opstate_init(); 834 mce_register_decode_chain(&i10nm_mce_dec); 835 setup_i10nm_debug(); 836 837 if (retry_rd_err_log && res_cfg->offsets_scrub && res_cfg->offsets_demand) { 838 skx_set_decode(i10nm_mc_decode, show_retry_rd_err_log); 839 if (retry_rd_err_log == 2) 840 enable_retry_rd_err_log(true); 841 } else { 842 skx_set_decode(i10nm_mc_decode, NULL); 843 } 844 845 i10nm_printk(KERN_INFO, "%s\n", I10NM_REVISION); 846 847 return 0; 848 fail: 849 skx_remove(); 850 return rc; 851 } 852 853 static void __exit i10nm_exit(void) 854 { 855 edac_dbg(2, "\n"); 856 857 if (retry_rd_err_log && res_cfg->offsets_scrub && res_cfg->offsets_demand) { 858 skx_set_decode(NULL, NULL); 859 if (retry_rd_err_log == 2) 860 enable_retry_rd_err_log(false); 861 } 862 863 teardown_i10nm_debug(); 864 mce_unregister_decode_chain(&i10nm_mce_dec); 865 skx_adxl_put(); 866 skx_remove(); 867 } 868 869 module_init(i10nm_init); 870 module_exit(i10nm_exit); 871 872 static int set_decoding_via_mca(const char *buf, const struct kernel_param *kp) 873 { 874 unsigned long val; 875 int ret; 876 877 ret = kstrtoul(buf, 0, &val); 878 879 if (ret || val > 1) 880 return -EINVAL; 881 882 if (val && mem_cfg_2lm) { 883 i10nm_printk(KERN_NOTICE, "Decoding errors via MCA banks for 2LM isn't supported yet\n"); 884 return -EIO; 885 } 886 887 ret = param_set_int(buf, kp); 888 889 return ret; 890 } 891 892 static const struct kernel_param_ops decoding_via_mca_param_ops = { 893 .set = set_decoding_via_mca, 894 .get = param_get_int, 895 }; 896 897 module_param_cb(decoding_via_mca, &decoding_via_mca_param_ops, &decoding_via_mca, 0644); 898 MODULE_PARM_DESC(decoding_via_mca, "decoding_via_mca: 0=off(default), 1=enable"); 899 900 module_param(retry_rd_err_log, int, 0444); 901 MODULE_PARM_DESC(retry_rd_err_log, "retry_rd_err_log: 0=off(default), 1=bios(Linux doesn't reset any control bits, but just reports values.), 2=linux(Linux tries to take control and resets mode bits, clear valid/UC bits after reading.)"); 902 903 MODULE_LICENSE("GPL v2"); 904 MODULE_DESCRIPTION("MC Driver for Intel 10nm server processors"); 905