xref: /openbmc/linux/drivers/edac/ghes_edac.c (revision 5085e036) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * GHES/EDAC Linux driver
4  *
5  * Copyright (c) 2013 by Mauro Carvalho Chehab
6  *
7  * Red Hat Inc. https://www.redhat.com
8  */
9 
10 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 
12 #include <acpi/ghes.h>
13 #include <linux/edac.h>
14 #include <linux/dmi.h>
15 #include "edac_module.h"
16 #include <ras/ras_event.h>
17 
18 #define OTHER_DETAIL_LEN	400
19 
20 struct ghes_pvt {
21 	struct mem_ctl_info *mci;
22 
23 	/* Buffers for the error handling routine */
24 	char other_detail[OTHER_DETAIL_LEN];
25 	char msg[80];
26 };
27 
28 static refcount_t ghes_refcount = REFCOUNT_INIT(0);
29 
30 /*
31  * Access to ghes_pvt must be protected by ghes_lock. The spinlock
32  * also provides the necessary (implicit) memory barrier for the SMP
33  * case to make the pointer visible on another CPU.
34  */
35 static struct ghes_pvt *ghes_pvt;
36 
37 /*
38  * This driver's representation of the system hardware, as collected
39  * from DMI.
40  */
41 static struct ghes_hw_desc {
42 	int num_dimms;
43 	struct dimm_info *dimms;
44 } ghes_hw;
45 
46 /* GHES registration mutex */
47 static DEFINE_MUTEX(ghes_reg_mutex);
48 
49 /*
50  * Sync with other, potentially concurrent callers of
51  * ghes_edac_report_mem_error(). We don't know what the
52  * "inventive" firmware would do.
53  */
54 static DEFINE_SPINLOCK(ghes_lock);
55 
56 /* "ghes_edac.force_load=1" skips the platform check */
57 static bool __read_mostly force_load;
58 module_param(force_load, bool, 0);
59 
60 static bool system_scanned;
61 
62 /* Memory Device - Type 17 of SMBIOS spec */
63 struct memdev_dmi_entry {
64 	u8 type;
65 	u8 length;
66 	u16 handle;
67 	u16 phys_mem_array_handle;
68 	u16 mem_err_info_handle;
69 	u16 total_width;
70 	u16 data_width;
71 	u16 size;
72 	u8 form_factor;
73 	u8 device_set;
74 	u8 device_locator;
75 	u8 bank_locator;
76 	u8 memory_type;
77 	u16 type_detail;
78 	u16 speed;
79 	u8 manufacturer;
80 	u8 serial_number;
81 	u8 asset_tag;
82 	u8 part_number;
83 	u8 attributes;
84 	u32 extended_size;
85 	u16 conf_mem_clk_speed;
86 } __attribute__((__packed__));
87 
88 static struct dimm_info *find_dimm_by_handle(struct mem_ctl_info *mci, u16 handle)
89 {
90 	struct dimm_info *dimm;
91 
92 	mci_for_each_dimm(mci, dimm) {
93 		if (dimm->smbios_handle == handle)
94 			return dimm;
95 	}
96 
97 	return NULL;
98 }
99 
100 static void dimm_setup_label(struct dimm_info *dimm, u16 handle)
101 {
102 	const char *bank = NULL, *device = NULL;
103 
104 	dmi_memdev_name(handle, &bank, &device);
105 
106 	/* both strings must be non-zero */
107 	if (bank && *bank && device && *device)
108 		snprintf(dimm->label, sizeof(dimm->label), "%s %s", bank, device);
109 }
110 
111 static void assign_dmi_dimm_info(struct dimm_info *dimm, struct memdev_dmi_entry *entry)
112 {
113 	u16 rdr_mask = BIT(7) | BIT(13);
114 
115 	if (entry->size == 0xffff) {
116 		pr_info("Can't get DIMM%i size\n", dimm->idx);
117 		dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
118 	} else if (entry->size == 0x7fff) {
119 		dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
120 	} else {
121 		if (entry->size & BIT(15))
122 			dimm->nr_pages = MiB_TO_PAGES((entry->size & 0x7fff) << 10);
123 		else
124 			dimm->nr_pages = MiB_TO_PAGES(entry->size);
125 	}
126 
127 	switch (entry->memory_type) {
128 	case 0x12:
129 		if (entry->type_detail & BIT(13))
130 			dimm->mtype = MEM_RDDR;
131 		else
132 			dimm->mtype = MEM_DDR;
133 		break;
134 	case 0x13:
135 		if (entry->type_detail & BIT(13))
136 			dimm->mtype = MEM_RDDR2;
137 		else
138 			dimm->mtype = MEM_DDR2;
139 		break;
140 	case 0x14:
141 		dimm->mtype = MEM_FB_DDR2;
142 		break;
143 	case 0x18:
144 		if (entry->type_detail & BIT(12))
145 			dimm->mtype = MEM_NVDIMM;
146 		else if (entry->type_detail & BIT(13))
147 			dimm->mtype = MEM_RDDR3;
148 		else
149 			dimm->mtype = MEM_DDR3;
150 		break;
151 	case 0x1a:
152 		if (entry->type_detail & BIT(12))
153 			dimm->mtype = MEM_NVDIMM;
154 		else if (entry->type_detail & BIT(13))
155 			dimm->mtype = MEM_RDDR4;
156 		else
157 			dimm->mtype = MEM_DDR4;
158 		break;
159 	default:
160 		if (entry->type_detail & BIT(6))
161 			dimm->mtype = MEM_RMBS;
162 		else if ((entry->type_detail & rdr_mask) == rdr_mask)
163 			dimm->mtype = MEM_RDR;
164 		else if (entry->type_detail & BIT(7))
165 			dimm->mtype = MEM_SDR;
166 		else if (entry->type_detail & BIT(9))
167 			dimm->mtype = MEM_EDO;
168 		else
169 			dimm->mtype = MEM_UNKNOWN;
170 	}
171 
172 	/*
173 	 * Actually, we can only detect if the memory has bits for
174 	 * checksum or not
175 	 */
176 	if (entry->total_width == entry->data_width)
177 		dimm->edac_mode = EDAC_NONE;
178 	else
179 		dimm->edac_mode = EDAC_SECDED;
180 
181 	dimm->dtype = DEV_UNKNOWN;
182 	dimm->grain = 128;		/* Likely, worse case */
183 
184 	dimm_setup_label(dimm, entry->handle);
185 
186 	if (dimm->nr_pages) {
187 		edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
188 			dimm->idx, edac_mem_types[dimm->mtype],
189 			PAGES_TO_MiB(dimm->nr_pages),
190 			(dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
191 		edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
192 			entry->memory_type, entry->type_detail,
193 			entry->total_width, entry->data_width);
194 	}
195 
196 	dimm->smbios_handle = entry->handle;
197 }
198 
199 static void enumerate_dimms(const struct dmi_header *dh, void *arg)
200 {
201 	struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
202 	struct ghes_hw_desc *hw = (struct ghes_hw_desc *)arg;
203 	struct dimm_info *d;
204 
205 	if (dh->type != DMI_ENTRY_MEM_DEVICE)
206 		return;
207 
208 	/* Enlarge the array with additional 16 */
209 	if (!hw->num_dimms || !(hw->num_dimms % 16)) {
210 		struct dimm_info *new;
211 
212 		new = krealloc_array(hw->dimms, hw->num_dimms + 16,
213 				     sizeof(struct dimm_info), GFP_KERNEL);
214 		if (!new) {
215 			WARN_ON_ONCE(1);
216 			return;
217 		}
218 
219 		hw->dimms = new;
220 	}
221 
222 	d = &hw->dimms[hw->num_dimms];
223 	d->idx = hw->num_dimms;
224 
225 	assign_dmi_dimm_info(d, entry);
226 
227 	hw->num_dimms++;
228 }
229 
230 static void ghes_scan_system(void)
231 {
232 	if (system_scanned)
233 		return;
234 
235 	dmi_walk(enumerate_dimms, &ghes_hw);
236 
237 	system_scanned = true;
238 }
239 
240 static int print_mem_error_other_detail(const struct cper_sec_mem_err *mem, char *msg,
241 					const char *location, unsigned int len)
242 {
243 	u32 n;
244 
245 	if (!msg)
246 		return 0;
247 
248 	n = 0;
249 	len -= 1;
250 
251 	n += scnprintf(msg + n, len - n, "APEI location: %s ", location);
252 
253 	if (!(mem->validation_bits & CPER_MEM_VALID_ERROR_STATUS))
254 		goto out;
255 
256 	n += scnprintf(msg + n, len - n, "status(0x%016llx): ", mem->error_status);
257 	n += scnprintf(msg + n, len - n, "%s ", cper_mem_err_status_str(mem->error_status));
258 
259 out:
260 	msg[n] = '\0';
261 
262 	return n;
263 }
264 
265 void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
266 {
267 	struct cper_mem_err_compact cmem;
268 	struct edac_raw_error_desc *e;
269 	struct mem_ctl_info *mci;
270 	struct ghes_pvt *pvt;
271 	unsigned long flags;
272 	char *p;
273 
274 	/*
275 	 * We can do the locking below because GHES defers error processing
276 	 * from NMI to IRQ context. Whenever that changes, we'd at least
277 	 * know.
278 	 */
279 	if (WARN_ON_ONCE(in_nmi()))
280 		return;
281 
282 	spin_lock_irqsave(&ghes_lock, flags);
283 
284 	pvt = ghes_pvt;
285 	if (!pvt)
286 		goto unlock;
287 
288 	mci = pvt->mci;
289 	e = &mci->error_desc;
290 
291 	/* Cleans the error report buffer */
292 	memset(e, 0, sizeof (*e));
293 	e->error_count = 1;
294 	e->grain = 1;
295 	e->msg = pvt->msg;
296 	e->other_detail = pvt->other_detail;
297 	e->top_layer = -1;
298 	e->mid_layer = -1;
299 	e->low_layer = -1;
300 	*pvt->other_detail = '\0';
301 	*pvt->msg = '\0';
302 
303 	switch (sev) {
304 	case GHES_SEV_CORRECTED:
305 		e->type = HW_EVENT_ERR_CORRECTED;
306 		break;
307 	case GHES_SEV_RECOVERABLE:
308 		e->type = HW_EVENT_ERR_UNCORRECTED;
309 		break;
310 	case GHES_SEV_PANIC:
311 		e->type = HW_EVENT_ERR_FATAL;
312 		break;
313 	default:
314 	case GHES_SEV_NO:
315 		e->type = HW_EVENT_ERR_INFO;
316 	}
317 
318 	edac_dbg(1, "error validation_bits: 0x%08llx\n",
319 		 (long long)mem_err->validation_bits);
320 
321 	/* Error type, mapped on e->msg */
322 	if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
323 		u8 etype = mem_err->error_type;
324 
325 		p = pvt->msg;
326 		p += snprintf(p, sizeof(pvt->msg), "%s", cper_mem_err_type_str(etype));
327 	} else {
328 		strcpy(pvt->msg, "unknown error");
329 	}
330 
331 	/* Error address */
332 	if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
333 		e->page_frame_number = PHYS_PFN(mem_err->physical_addr);
334 		e->offset_in_page = offset_in_page(mem_err->physical_addr);
335 	}
336 
337 	/* Error grain */
338 	if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
339 		e->grain = ~mem_err->physical_addr_mask + 1;
340 
341 	/* Memory error location, mapped on e->location */
342 	p = e->location;
343 	cper_mem_err_pack(mem_err, &cmem);
344 	p += cper_mem_err_location(&cmem, p);
345 
346 	if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
347 		struct dimm_info *dimm;
348 
349 		p += cper_dimm_err_location(&cmem, p);
350 		dimm = find_dimm_by_handle(mci, mem_err->mem_dev_handle);
351 		if (dimm) {
352 			e->top_layer = dimm->idx;
353 			strcpy(e->label, dimm->label);
354 		}
355 	}
356 	if (p > e->location)
357 		*(p - 1) = '\0';
358 
359 	if (!*e->label)
360 		strcpy(e->label, "unknown memory");
361 
362 	/* All other fields are mapped on e->other_detail */
363 	p = pvt->other_detail;
364 	p += print_mem_error_other_detail(mem_err, p, e->location, OTHER_DETAIL_LEN);
365 	if (p > pvt->other_detail)
366 		*(p - 1) = '\0';
367 
368 	edac_raw_mc_handle_error(e);
369 
370 unlock:
371 	spin_unlock_irqrestore(&ghes_lock, flags);
372 }
373 
374 /*
375  * Known systems that are safe to enable this module.
376  */
377 static struct acpi_platform_list plat_list[] = {
378 	{"HPE   ", "Server  ", 0, ACPI_SIG_FADT, all_versions},
379 	{ } /* End */
380 };
381 
382 int ghes_edac_register(struct ghes *ghes, struct device *dev)
383 {
384 	bool fake = false;
385 	struct mem_ctl_info *mci;
386 	struct ghes_pvt *pvt;
387 	struct edac_mc_layer layers[1];
388 	unsigned long flags;
389 	int idx = -1;
390 	int rc = 0;
391 
392 	if (IS_ENABLED(CONFIG_X86)) {
393 		/* Check if safe to enable on this system */
394 		idx = acpi_match_platform_list(plat_list);
395 		if (!force_load && idx < 0)
396 			return -ENODEV;
397 	} else {
398 		force_load = true;
399 		idx = 0;
400 	}
401 
402 	/* finish another registration/unregistration instance first */
403 	mutex_lock(&ghes_reg_mutex);
404 
405 	/*
406 	 * We have only one logical memory controller to which all DIMMs belong.
407 	 */
408 	if (refcount_inc_not_zero(&ghes_refcount))
409 		goto unlock;
410 
411 	ghes_scan_system();
412 
413 	/* Check if we've got a bogus BIOS */
414 	if (!ghes_hw.num_dimms) {
415 		fake = true;
416 		ghes_hw.num_dimms = 1;
417 	}
418 
419 	layers[0].type = EDAC_MC_LAYER_ALL_MEM;
420 	layers[0].size = ghes_hw.num_dimms;
421 	layers[0].is_virt_csrow = true;
422 
423 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_pvt));
424 	if (!mci) {
425 		pr_info("Can't allocate memory for EDAC data\n");
426 		rc = -ENOMEM;
427 		goto unlock;
428 	}
429 
430 	pvt		= mci->pvt_info;
431 	pvt->mci	= mci;
432 
433 	mci->pdev = dev;
434 	mci->mtype_cap = MEM_FLAG_EMPTY;
435 	mci->edac_ctl_cap = EDAC_FLAG_NONE;
436 	mci->edac_cap = EDAC_FLAG_NONE;
437 	mci->mod_name = "ghes_edac.c";
438 	mci->ctl_name = "ghes_edac";
439 	mci->dev_name = "ghes";
440 
441 	if (fake) {
442 		pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
443 		pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
444 		pr_info("work on such system. Use this driver with caution\n");
445 	} else if (idx < 0) {
446 		pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");
447 		pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");
448 		pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
449 		pr_info("If you find incorrect reports, please contact your hardware vendor\n");
450 		pr_info("to correct its BIOS.\n");
451 		pr_info("This system has %d DIMM sockets.\n", ghes_hw.num_dimms);
452 	}
453 
454 	if (!fake) {
455 		struct dimm_info *src, *dst;
456 		int i = 0;
457 
458 		mci_for_each_dimm(mci, dst) {
459 			src = &ghes_hw.dimms[i];
460 
461 			dst->idx	   = src->idx;
462 			dst->smbios_handle = src->smbios_handle;
463 			dst->nr_pages	   = src->nr_pages;
464 			dst->mtype	   = src->mtype;
465 			dst->edac_mode	   = src->edac_mode;
466 			dst->dtype	   = src->dtype;
467 			dst->grain	   = src->grain;
468 
469 			/*
470 			 * If no src->label, preserve default label assigned
471 			 * from EDAC core.
472 			 */
473 			if (strlen(src->label))
474 				memcpy(dst->label, src->label, sizeof(src->label));
475 
476 			i++;
477 		}
478 
479 	} else {
480 		struct dimm_info *dimm = edac_get_dimm(mci, 0, 0, 0);
481 
482 		dimm->nr_pages = 1;
483 		dimm->grain = 128;
484 		dimm->mtype = MEM_UNKNOWN;
485 		dimm->dtype = DEV_UNKNOWN;
486 		dimm->edac_mode = EDAC_SECDED;
487 	}
488 
489 	rc = edac_mc_add_mc(mci);
490 	if (rc < 0) {
491 		pr_info("Can't register with the EDAC core\n");
492 		edac_mc_free(mci);
493 		rc = -ENODEV;
494 		goto unlock;
495 	}
496 
497 	spin_lock_irqsave(&ghes_lock, flags);
498 	ghes_pvt = pvt;
499 	spin_unlock_irqrestore(&ghes_lock, flags);
500 
501 	/* only set on success */
502 	refcount_set(&ghes_refcount, 1);
503 
504 unlock:
505 
506 	/* Not needed anymore */
507 	kfree(ghes_hw.dimms);
508 	ghes_hw.dimms = NULL;
509 
510 	mutex_unlock(&ghes_reg_mutex);
511 
512 	return rc;
513 }
514 
515 void ghes_edac_unregister(struct ghes *ghes)
516 {
517 	struct mem_ctl_info *mci;
518 	unsigned long flags;
519 
520 	if (!force_load)
521 		return;
522 
523 	mutex_lock(&ghes_reg_mutex);
524 
525 	system_scanned = false;
526 	memset(&ghes_hw, 0, sizeof(struct ghes_hw_desc));
527 
528 	if (!refcount_dec_and_test(&ghes_refcount))
529 		goto unlock;
530 
531 	/*
532 	 * Wait for the irq handler being finished.
533 	 */
534 	spin_lock_irqsave(&ghes_lock, flags);
535 	mci = ghes_pvt ? ghes_pvt->mci : NULL;
536 	ghes_pvt = NULL;
537 	spin_unlock_irqrestore(&ghes_lock, flags);
538 
539 	if (!mci)
540 		goto unlock;
541 
542 	mci = edac_mc_del_mc(mci->pdev);
543 	if (mci)
544 		edac_mc_free(mci);
545 
546 unlock:
547 	mutex_unlock(&ghes_reg_mutex);
548 }
549