1 /* 2 * Intel e7xxx Memory Controller kernel module 3 * (C) 2003 Linux Networx (http://lnxi.com) 4 * This file may be distributed under the terms of the 5 * GNU General Public License. 6 * 7 * See "enum e7xxx_chips" below for supported chipsets 8 * 9 * Written by Thayne Harbaugh 10 * Based on work by Dan Hollis <goemon at anime dot net> and others. 11 * http://www.anime.net/~goemon/linux-ecc/ 12 * 13 * Contributors: 14 * Eric Biederman (Linux Networx) 15 * Tom Zimmerman (Linux Networx) 16 * Jim Garlick (Lawrence Livermore National Labs) 17 * Dave Peterson (Lawrence Livermore National Labs) 18 * That One Guy (Some other place) 19 * Wang Zhenyu (intel.com) 20 * 21 * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $ 22 * 23 */ 24 25 #include <linux/module.h> 26 #include <linux/init.h> 27 #include <linux/pci.h> 28 #include <linux/pci_ids.h> 29 #include <linux/edac.h> 30 #include "edac_core.h" 31 32 #define E7XXX_REVISION " Ver: 2.0.2" 33 #define EDAC_MOD_STR "e7xxx_edac" 34 35 #define e7xxx_printk(level, fmt, arg...) \ 36 edac_printk(level, "e7xxx", fmt, ##arg) 37 38 #define e7xxx_mc_printk(mci, level, fmt, arg...) \ 39 edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg) 40 41 #ifndef PCI_DEVICE_ID_INTEL_7205_0 42 #define PCI_DEVICE_ID_INTEL_7205_0 0x255d 43 #endif /* PCI_DEVICE_ID_INTEL_7205_0 */ 44 45 #ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR 46 #define PCI_DEVICE_ID_INTEL_7205_1_ERR 0x2551 47 #endif /* PCI_DEVICE_ID_INTEL_7205_1_ERR */ 48 49 #ifndef PCI_DEVICE_ID_INTEL_7500_0 50 #define PCI_DEVICE_ID_INTEL_7500_0 0x2540 51 #endif /* PCI_DEVICE_ID_INTEL_7500_0 */ 52 53 #ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR 54 #define PCI_DEVICE_ID_INTEL_7500_1_ERR 0x2541 55 #endif /* PCI_DEVICE_ID_INTEL_7500_1_ERR */ 56 57 #ifndef PCI_DEVICE_ID_INTEL_7501_0 58 #define PCI_DEVICE_ID_INTEL_7501_0 0x254c 59 #endif /* PCI_DEVICE_ID_INTEL_7501_0 */ 60 61 #ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR 62 #define PCI_DEVICE_ID_INTEL_7501_1_ERR 0x2541 63 #endif /* PCI_DEVICE_ID_INTEL_7501_1_ERR */ 64 65 #ifndef PCI_DEVICE_ID_INTEL_7505_0 66 #define PCI_DEVICE_ID_INTEL_7505_0 0x2550 67 #endif /* PCI_DEVICE_ID_INTEL_7505_0 */ 68 69 #ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR 70 #define PCI_DEVICE_ID_INTEL_7505_1_ERR 0x2551 71 #endif /* PCI_DEVICE_ID_INTEL_7505_1_ERR */ 72 73 #define E7XXX_NR_CSROWS 8 /* number of csrows */ 74 #define E7XXX_NR_DIMMS 8 /* FIXME - is this correct? */ 75 76 /* E7XXX register addresses - device 0 function 0 */ 77 #define E7XXX_DRB 0x60 /* DRAM row boundary register (8b) */ 78 #define E7XXX_DRA 0x70 /* DRAM row attribute register (8b) */ 79 /* 80 * 31 Device width row 7 0=x8 1=x4 81 * 27 Device width row 6 82 * 23 Device width row 5 83 * 19 Device width row 4 84 * 15 Device width row 3 85 * 11 Device width row 2 86 * 7 Device width row 1 87 * 3 Device width row 0 88 */ 89 #define E7XXX_DRC 0x7C /* DRAM controller mode reg (32b) */ 90 /* 91 * 22 Number channels 0=1,1=2 92 * 19:18 DRB Granularity 32/64MB 93 */ 94 #define E7XXX_TOLM 0xC4 /* DRAM top of low memory reg (16b) */ 95 #define E7XXX_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */ 96 #define E7XXX_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */ 97 98 /* E7XXX register addresses - device 0 function 1 */ 99 #define E7XXX_DRAM_FERR 0x80 /* DRAM first error register (8b) */ 100 #define E7XXX_DRAM_NERR 0x82 /* DRAM next error register (8b) */ 101 #define E7XXX_DRAM_CELOG_ADD 0xA0 /* DRAM first correctable memory */ 102 /* error address register (32b) */ 103 /* 104 * 31:28 Reserved 105 * 27:6 CE address (4k block 33:12) 106 * 5:0 Reserved 107 */ 108 #define E7XXX_DRAM_UELOG_ADD 0xB0 /* DRAM first uncorrectable memory */ 109 /* error address register (32b) */ 110 /* 111 * 31:28 Reserved 112 * 27:6 CE address (4k block 33:12) 113 * 5:0 Reserved 114 */ 115 #define E7XXX_DRAM_CELOG_SYNDROME 0xD0 /* DRAM first correctable memory */ 116 /* error syndrome register (16b) */ 117 118 enum e7xxx_chips { 119 E7500 = 0, 120 E7501, 121 E7505, 122 E7205, 123 }; 124 125 struct e7xxx_pvt { 126 struct pci_dev *bridge_ck; 127 u32 tolm; 128 u32 remapbase; 129 u32 remaplimit; 130 const struct e7xxx_dev_info *dev_info; 131 }; 132 133 struct e7xxx_dev_info { 134 u16 err_dev; 135 const char *ctl_name; 136 }; 137 138 struct e7xxx_error_info { 139 u8 dram_ferr; 140 u8 dram_nerr; 141 u32 dram_celog_add; 142 u16 dram_celog_syndrome; 143 u32 dram_uelog_add; 144 }; 145 146 static struct edac_pci_ctl_info *e7xxx_pci; 147 148 static const struct e7xxx_dev_info e7xxx_devs[] = { 149 [E7500] = { 150 .err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR, 151 .ctl_name = "E7500"}, 152 [E7501] = { 153 .err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR, 154 .ctl_name = "E7501"}, 155 [E7505] = { 156 .err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR, 157 .ctl_name = "E7505"}, 158 [E7205] = { 159 .err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR, 160 .ctl_name = "E7205"}, 161 }; 162 163 /* FIXME - is this valid for both SECDED and S4ECD4ED? */ 164 static inline int e7xxx_find_channel(u16 syndrome) 165 { 166 debugf3("%s()\n", __func__); 167 168 if ((syndrome & 0xff00) == 0) 169 return 0; 170 171 if ((syndrome & 0x00ff) == 0) 172 return 1; 173 174 if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0) 175 return 0; 176 177 return 1; 178 } 179 180 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci, 181 unsigned long page) 182 { 183 u32 remap; 184 struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info; 185 186 debugf3("%s()\n", __func__); 187 188 if ((page < pvt->tolm) || 189 ((page >= 0x100000) && (page < pvt->remapbase))) 190 return page; 191 192 remap = (page - pvt->tolm) + pvt->remapbase; 193 194 if (remap < pvt->remaplimit) 195 return remap; 196 197 e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page); 198 return pvt->tolm - 1; 199 } 200 201 static void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info) 202 { 203 u32 error_1b, page; 204 u16 syndrome; 205 int row; 206 int channel; 207 208 debugf3("%s()\n", __func__); 209 /* read the error address */ 210 error_1b = info->dram_celog_add; 211 /* FIXME - should use PAGE_SHIFT */ 212 page = error_1b >> 6; /* convert the address to 4k page */ 213 /* read the syndrome */ 214 syndrome = info->dram_celog_syndrome; 215 /* FIXME - check for -1 */ 216 row = edac_mc_find_csrow_by_page(mci, page); 217 /* convert syndrome to channel */ 218 channel = e7xxx_find_channel(syndrome); 219 edac_mc_handle_ce(mci, page, 0, syndrome, row, channel, "e7xxx CE"); 220 } 221 222 static void process_ce_no_info(struct mem_ctl_info *mci) 223 { 224 debugf3("%s()\n", __func__); 225 edac_mc_handle_ce_no_info(mci, "e7xxx CE log register overflow"); 226 } 227 228 static void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info) 229 { 230 u32 error_2b, block_page; 231 int row; 232 233 debugf3("%s()\n", __func__); 234 /* read the error address */ 235 error_2b = info->dram_uelog_add; 236 /* FIXME - should use PAGE_SHIFT */ 237 block_page = error_2b >> 6; /* convert to 4k address */ 238 row = edac_mc_find_csrow_by_page(mci, block_page); 239 edac_mc_handle_ue(mci, block_page, 0, row, "e7xxx UE"); 240 } 241 242 static void process_ue_no_info(struct mem_ctl_info *mci) 243 { 244 debugf3("%s()\n", __func__); 245 edac_mc_handle_ue_no_info(mci, "e7xxx UE log register overflow"); 246 } 247 248 static void e7xxx_get_error_info(struct mem_ctl_info *mci, 249 struct e7xxx_error_info *info) 250 { 251 struct e7xxx_pvt *pvt; 252 253 pvt = (struct e7xxx_pvt *)mci->pvt_info; 254 pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr); 255 pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr); 256 257 if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) { 258 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD, 259 &info->dram_celog_add); 260 pci_read_config_word(pvt->bridge_ck, 261 E7XXX_DRAM_CELOG_SYNDROME, 262 &info->dram_celog_syndrome); 263 } 264 265 if ((info->dram_ferr & 2) || (info->dram_nerr & 2)) 266 pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD, 267 &info->dram_uelog_add); 268 269 if (info->dram_ferr & 3) 270 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03); 271 272 if (info->dram_nerr & 3) 273 pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03); 274 } 275 276 static int e7xxx_process_error_info(struct mem_ctl_info *mci, 277 struct e7xxx_error_info *info, 278 int handle_errors) 279 { 280 int error_found; 281 282 error_found = 0; 283 284 /* decode and report errors */ 285 if (info->dram_ferr & 1) { /* check first error correctable */ 286 error_found = 1; 287 288 if (handle_errors) 289 process_ce(mci, info); 290 } 291 292 if (info->dram_ferr & 2) { /* check first error uncorrectable */ 293 error_found = 1; 294 295 if (handle_errors) 296 process_ue(mci, info); 297 } 298 299 if (info->dram_nerr & 1) { /* check next error correctable */ 300 error_found = 1; 301 302 if (handle_errors) { 303 if (info->dram_ferr & 1) 304 process_ce_no_info(mci); 305 else 306 process_ce(mci, info); 307 } 308 } 309 310 if (info->dram_nerr & 2) { /* check next error uncorrectable */ 311 error_found = 1; 312 313 if (handle_errors) { 314 if (info->dram_ferr & 2) 315 process_ue_no_info(mci); 316 else 317 process_ue(mci, info); 318 } 319 } 320 321 return error_found; 322 } 323 324 static void e7xxx_check(struct mem_ctl_info *mci) 325 { 326 struct e7xxx_error_info info; 327 328 debugf3("%s()\n", __func__); 329 e7xxx_get_error_info(mci, &info); 330 e7xxx_process_error_info(mci, &info, 1); 331 } 332 333 /* Return 1 if dual channel mode is active. Else return 0. */ 334 static inline int dual_channel_active(u32 drc, int dev_idx) 335 { 336 return (dev_idx == E7501) ? ((drc >> 22) & 0x1) : 1; 337 } 338 339 /* Return DRB granularity (0=32mb, 1=64mb). */ 340 static inline int drb_granularity(u32 drc, int dev_idx) 341 { 342 /* only e7501 can be single channel */ 343 return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1; 344 } 345 346 static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, 347 int dev_idx, u32 drc) 348 { 349 unsigned long last_cumul_size; 350 int index; 351 u8 value; 352 u32 dra, cumul_size; 353 int drc_chan, drc_drbg, drc_ddim, mem_dev; 354 struct csrow_info *csrow; 355 356 pci_read_config_dword(pdev, E7XXX_DRA, &dra); 357 drc_chan = dual_channel_active(drc, dev_idx); 358 drc_drbg = drb_granularity(drc, dev_idx); 359 drc_ddim = (drc >> 20) & 0x3; 360 last_cumul_size = 0; 361 362 /* The dram row boundary (DRB) reg values are boundary address 363 * for each DRAM row with a granularity of 32 or 64MB (single/dual 364 * channel operation). DRB regs are cumulative; therefore DRB7 will 365 * contain the total memory contained in all eight rows. 366 */ 367 for (index = 0; index < mci->nr_csrows; index++) { 368 /* mem_dev 0=x8, 1=x4 */ 369 mem_dev = (dra >> (index * 4 + 3)) & 0x1; 370 csrow = &mci->csrows[index]; 371 372 pci_read_config_byte(pdev, E7XXX_DRB + index, &value); 373 /* convert a 64 or 32 MiB DRB to a page size. */ 374 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT); 375 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index, 376 cumul_size); 377 if (cumul_size == last_cumul_size) 378 continue; /* not populated */ 379 380 csrow->first_page = last_cumul_size; 381 csrow->last_page = cumul_size - 1; 382 csrow->nr_pages = cumul_size - last_cumul_size; 383 last_cumul_size = cumul_size; 384 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */ 385 csrow->mtype = MEM_RDDR; /* only one type supported */ 386 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8; 387 388 /* 389 * if single channel or x8 devices then SECDED 390 * if dual channel and x4 then S4ECD4ED 391 */ 392 if (drc_ddim) { 393 if (drc_chan && mem_dev) { 394 csrow->edac_mode = EDAC_S4ECD4ED; 395 mci->edac_cap |= EDAC_FLAG_S4ECD4ED; 396 } else { 397 csrow->edac_mode = EDAC_SECDED; 398 mci->edac_cap |= EDAC_FLAG_SECDED; 399 } 400 } else 401 csrow->edac_mode = EDAC_NONE; 402 } 403 } 404 405 static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx) 406 { 407 u16 pci_data; 408 struct mem_ctl_info *mci = NULL; 409 struct e7xxx_pvt *pvt = NULL; 410 u32 drc; 411 int drc_chan; 412 struct e7xxx_error_info discard; 413 414 debugf0("%s(): mci\n", __func__); 415 416 pci_read_config_dword(pdev, E7XXX_DRC, &drc); 417 418 drc_chan = dual_channel_active(drc, dev_idx); 419 mci = edac_mc_alloc(sizeof(*pvt), E7XXX_NR_CSROWS, drc_chan + 1, 0); 420 421 if (mci == NULL) 422 return -ENOMEM; 423 424 debugf3("%s(): init mci\n", __func__); 425 mci->mtype_cap = MEM_FLAG_RDDR; 426 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED | 427 EDAC_FLAG_S4ECD4ED; 428 /* FIXME - what if different memory types are in different csrows? */ 429 mci->mod_name = EDAC_MOD_STR; 430 mci->mod_ver = E7XXX_REVISION; 431 mci->dev = &pdev->dev; 432 debugf3("%s(): init pvt\n", __func__); 433 pvt = (struct e7xxx_pvt *)mci->pvt_info; 434 pvt->dev_info = &e7xxx_devs[dev_idx]; 435 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL, 436 pvt->dev_info->err_dev, pvt->bridge_ck); 437 438 if (!pvt->bridge_ck) { 439 e7xxx_printk(KERN_ERR, "error reporting device not found:" 440 "vendor %x device 0x%x (broken BIOS?)\n", 441 PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev); 442 goto fail0; 443 } 444 445 debugf3("%s(): more mci init\n", __func__); 446 mci->ctl_name = pvt->dev_info->ctl_name; 447 mci->dev_name = pci_name(pdev); 448 mci->edac_check = e7xxx_check; 449 mci->ctl_page_to_phys = ctl_page_to_phys; 450 e7xxx_init_csrows(mci, pdev, dev_idx, drc); 451 mci->edac_cap |= EDAC_FLAG_NONE; 452 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__); 453 /* load the top of low memory, remap base, and remap limit vars */ 454 pci_read_config_word(pdev, E7XXX_TOLM, &pci_data); 455 pvt->tolm = ((u32) pci_data) << 4; 456 pci_read_config_word(pdev, E7XXX_REMAPBASE, &pci_data); 457 pvt->remapbase = ((u32) pci_data) << 14; 458 pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data); 459 pvt->remaplimit = ((u32) pci_data) << 14; 460 e7xxx_printk(KERN_INFO, 461 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm, 462 pvt->remapbase, pvt->remaplimit); 463 464 /* clear any pending errors, or initial state bits */ 465 e7xxx_get_error_info(mci, &discard); 466 467 /* Here we assume that we will never see multiple instances of this 468 * type of memory controller. The ID is therefore hardcoded to 0. 469 */ 470 if (edac_mc_add_mc(mci)) { 471 debugf3("%s(): failed edac_mc_add_mc()\n", __func__); 472 goto fail1; 473 } 474 475 /* allocating generic PCI control info */ 476 e7xxx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); 477 if (!e7xxx_pci) { 478 printk(KERN_WARNING 479 "%s(): Unable to create PCI control\n", 480 __func__); 481 printk(KERN_WARNING 482 "%s(): PCI error report via EDAC not setup\n", 483 __func__); 484 } 485 486 /* get this far and it's successful */ 487 debugf3("%s(): success\n", __func__); 488 return 0; 489 490 fail1: 491 pci_dev_put(pvt->bridge_ck); 492 493 fail0: 494 edac_mc_free(mci); 495 496 return -ENODEV; 497 } 498 499 /* returns count (>= 0), or negative on error */ 500 static int __devinit e7xxx_init_one(struct pci_dev *pdev, 501 const struct pci_device_id *ent) 502 { 503 debugf0("%s()\n", __func__); 504 505 /* wake up and enable device */ 506 return pci_enable_device(pdev) ? 507 -EIO : e7xxx_probe1(pdev, ent->driver_data); 508 } 509 510 static void __devexit e7xxx_remove_one(struct pci_dev *pdev) 511 { 512 struct mem_ctl_info *mci; 513 struct e7xxx_pvt *pvt; 514 515 debugf0("%s()\n", __func__); 516 517 if (e7xxx_pci) 518 edac_pci_release_generic_ctl(e7xxx_pci); 519 520 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) 521 return; 522 523 pvt = (struct e7xxx_pvt *)mci->pvt_info; 524 pci_dev_put(pvt->bridge_ck); 525 edac_mc_free(mci); 526 } 527 528 static DEFINE_PCI_DEVICE_TABLE(e7xxx_pci_tbl) = { 529 { 530 PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 531 E7205}, 532 { 533 PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 534 E7500}, 535 { 536 PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 537 E7501}, 538 { 539 PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 540 E7505}, 541 { 542 0, 543 } /* 0 terminated list. */ 544 }; 545 546 MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl); 547 548 static struct pci_driver e7xxx_driver = { 549 .name = EDAC_MOD_STR, 550 .probe = e7xxx_init_one, 551 .remove = __devexit_p(e7xxx_remove_one), 552 .id_table = e7xxx_pci_tbl, 553 }; 554 555 static int __init e7xxx_init(void) 556 { 557 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 558 opstate_init(); 559 560 return pci_register_driver(&e7xxx_driver); 561 } 562 563 static void __exit e7xxx_exit(void) 564 { 565 pci_unregister_driver(&e7xxx_driver); 566 } 567 568 module_init(e7xxx_init); 569 module_exit(e7xxx_exit); 570 571 MODULE_LICENSE("GPL"); 572 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n" 573 "Based on.work by Dan Hollis et al"); 574 MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers"); 575 module_param(edac_op_state, int, 0444); 576 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 577