xref: /openbmc/linux/drivers/edac/e752x_edac.c (revision 9ac8d3fb)
1 /*
2  * Intel e752x Memory Controller kernel module
3  * (C) 2004 Linux Networx (http://lnxi.com)
4  * This file may be distributed under the terms of the
5  * GNU General Public License.
6  *
7  * See "enum e752x_chips" below for supported chipsets
8  *
9  * Written by Tom Zimmerman
10  *
11  * Contributors:
12  * 	Thayne Harbaugh at realmsys.com (?)
13  * 	Wang Zhenyu at intel.com
14  * 	Dave Jiang at mvista.com
15  *
16  * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
17  *
18  */
19 
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
23 #include <linux/pci_ids.h>
24 #include <linux/slab.h>
25 #include <linux/edac.h>
26 #include "edac_core.h"
27 
28 #define E752X_REVISION	" Ver: 2.0.2 " __DATE__
29 #define EDAC_MOD_STR	"e752x_edac"
30 
31 static int report_non_memory_errors;
32 static int force_function_unhide;
33 static int sysbus_parity = -1;
34 
35 static struct edac_pci_ctl_info *e752x_pci;
36 
37 #define e752x_printk(level, fmt, arg...) \
38 	edac_printk(level, "e752x", fmt, ##arg)
39 
40 #define e752x_mc_printk(mci, level, fmt, arg...) \
41 	edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg)
42 
43 #ifndef PCI_DEVICE_ID_INTEL_7520_0
44 #define PCI_DEVICE_ID_INTEL_7520_0      0x3590
45 #endif				/* PCI_DEVICE_ID_INTEL_7520_0      */
46 
47 #ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR
48 #define PCI_DEVICE_ID_INTEL_7520_1_ERR  0x3591
49 #endif				/* PCI_DEVICE_ID_INTEL_7520_1_ERR  */
50 
51 #ifndef PCI_DEVICE_ID_INTEL_7525_0
52 #define PCI_DEVICE_ID_INTEL_7525_0      0x359E
53 #endif				/* PCI_DEVICE_ID_INTEL_7525_0      */
54 
55 #ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR
56 #define PCI_DEVICE_ID_INTEL_7525_1_ERR  0x3593
57 #endif				/* PCI_DEVICE_ID_INTEL_7525_1_ERR  */
58 
59 #ifndef PCI_DEVICE_ID_INTEL_7320_0
60 #define PCI_DEVICE_ID_INTEL_7320_0	0x3592
61 #endif				/* PCI_DEVICE_ID_INTEL_7320_0 */
62 
63 #ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR
64 #define PCI_DEVICE_ID_INTEL_7320_1_ERR	0x3593
65 #endif				/* PCI_DEVICE_ID_INTEL_7320_1_ERR */
66 
67 #ifndef PCI_DEVICE_ID_INTEL_3100_0
68 #define PCI_DEVICE_ID_INTEL_3100_0	0x35B0
69 #endif				/* PCI_DEVICE_ID_INTEL_3100_0 */
70 
71 #ifndef PCI_DEVICE_ID_INTEL_3100_1_ERR
72 #define PCI_DEVICE_ID_INTEL_3100_1_ERR	0x35B1
73 #endif				/* PCI_DEVICE_ID_INTEL_3100_1_ERR */
74 
75 #define E752X_NR_CSROWS		8	/* number of csrows */
76 
77 /* E752X register addresses - device 0 function 0 */
78 #define E752X_DRB		0x60	/* DRAM row boundary register (8b) */
79 #define E752X_DRA		0x70	/* DRAM row attribute register (8b) */
80 					/*
81 					 * 31:30   Device width row 7
82 					 *      01=x8 10=x4 11=x8 DDR2
83 					 * 27:26   Device width row 6
84 					 * 23:22   Device width row 5
85 					 * 19:20   Device width row 4
86 					 * 15:14   Device width row 3
87 					 * 11:10   Device width row 2
88 					 *  7:6    Device width row 1
89 					 *  3:2    Device width row 0
90 					 */
91 #define E752X_DRC		0x7C	/* DRAM controller mode reg (32b) */
92 					/* FIXME:IS THIS RIGHT? */
93 					/*
94 					 * 22    Number channels 0=1,1=2
95 					 * 19:18 DRB Granularity 32/64MB
96 					 */
97 #define E752X_DRM		0x80	/* Dimm mapping register */
98 #define E752X_DDRCSR		0x9A	/* DDR control and status reg (16b) */
99 					/*
100 					 * 14:12 1 single A, 2 single B, 3 dual
101 					 */
102 #define E752X_TOLM		0xC4	/* DRAM top of low memory reg (16b) */
103 #define E752X_REMAPBASE		0xC6	/* DRAM remap base address reg (16b) */
104 #define E752X_REMAPLIMIT	0xC8	/* DRAM remap limit address reg (16b) */
105 #define E752X_REMAPOFFSET	0xCA	/* DRAM remap limit offset reg (16b) */
106 
107 /* E752X register addresses - device 0 function 1 */
108 #define E752X_FERR_GLOBAL	0x40	/* Global first error register (32b) */
109 #define E752X_NERR_GLOBAL	0x44	/* Global next error register (32b) */
110 #define E752X_HI_FERR		0x50	/* Hub interface first error reg (8b) */
111 #define E752X_HI_NERR		0x52	/* Hub interface next error reg (8b) */
112 #define E752X_HI_ERRMASK	0x54	/* Hub interface error mask reg (8b) */
113 #define E752X_HI_SMICMD		0x5A	/* Hub interface SMI command reg (8b) */
114 #define E752X_SYSBUS_FERR	0x60	/* System buss first error reg (16b) */
115 #define E752X_SYSBUS_NERR	0x62	/* System buss next error reg (16b) */
116 #define E752X_SYSBUS_ERRMASK	0x64	/* System buss error mask reg (16b) */
117 #define E752X_SYSBUS_SMICMD	0x6A	/* System buss SMI command reg (16b) */
118 #define E752X_BUF_FERR		0x70	/* Memory buffer first error reg (8b) */
119 #define E752X_BUF_NERR		0x72	/* Memory buffer next error reg (8b) */
120 #define E752X_BUF_ERRMASK	0x74	/* Memory buffer error mask reg (8b) */
121 #define E752X_BUF_SMICMD	0x7A	/* Memory buffer SMI cmd reg (8b) */
122 #define E752X_DRAM_FERR		0x80	/* DRAM first error register (16b) */
123 #define E752X_DRAM_NERR		0x82	/* DRAM next error register (16b) */
124 #define E752X_DRAM_ERRMASK	0x84	/* DRAM error mask register (8b) */
125 #define E752X_DRAM_SMICMD	0x8A	/* DRAM SMI command register (8b) */
126 #define E752X_DRAM_RETR_ADD	0xAC	/* DRAM Retry address register (32b) */
127 #define E752X_DRAM_SEC1_ADD	0xA0	/* DRAM first correctable memory */
128 					/*     error address register (32b) */
129 					/*
130 					 * 31    Reserved
131 					 * 30:2  CE address (64 byte block 34:6
132 					 * 1     Reserved
133 					 * 0     HiLoCS
134 					 */
135 #define E752X_DRAM_SEC2_ADD	0xC8	/* DRAM first correctable memory */
136 					/*     error address register (32b) */
137 					/*
138 					 * 31    Reserved
139 					 * 30:2  CE address (64 byte block 34:6)
140 					 * 1     Reserved
141 					 * 0     HiLoCS
142 					 */
143 #define E752X_DRAM_DED_ADD	0xA4	/* DRAM first uncorrectable memory */
144 					/*     error address register (32b) */
145 					/*
146 					 * 31    Reserved
147 					 * 30:2  CE address (64 byte block 34:6)
148 					 * 1     Reserved
149 					 * 0     HiLoCS
150 					 */
151 #define E752X_DRAM_SCRB_ADD	0xA8	/* DRAM 1st uncorrectable scrub mem */
152 					/*     error address register (32b) */
153 					/*
154 					 * 31    Reserved
155 					 * 30:2  CE address (64 byte block 34:6
156 					 * 1     Reserved
157 					 * 0     HiLoCS
158 					 */
159 #define E752X_DRAM_SEC1_SYNDROME 0xC4	/* DRAM first correctable memory */
160 					/*     error syndrome register (16b) */
161 #define E752X_DRAM_SEC2_SYNDROME 0xC6	/* DRAM second correctable memory */
162 					/*     error syndrome register (16b) */
163 #define E752X_DEVPRES1		0xF4	/* Device Present 1 register (8b) */
164 
165 /* 3100 IMCH specific register addresses - device 0 function 1 */
166 #define I3100_NSI_FERR		0x48	/* NSI first error reg (32b) */
167 #define I3100_NSI_NERR		0x4C	/* NSI next error reg (32b) */
168 #define I3100_NSI_SMICMD	0x54	/* NSI SMI command register (32b) */
169 #define I3100_NSI_EMASK		0x90	/* NSI error mask register (32b) */
170 
171 /* ICH5R register addresses - device 30 function 0 */
172 #define ICH5R_PCI_STAT		0x06	/* PCI status register (16b) */
173 #define ICH5R_PCI_2ND_STAT	0x1E	/* PCI status secondary reg (16b) */
174 #define ICH5R_PCI_BRIDGE_CTL	0x3E	/* PCI bridge control register (16b) */
175 
176 enum e752x_chips {
177 	E7520 = 0,
178 	E7525 = 1,
179 	E7320 = 2,
180 	I3100 = 3
181 };
182 
183 struct e752x_pvt {
184 	struct pci_dev *bridge_ck;
185 	struct pci_dev *dev_d0f0;
186 	struct pci_dev *dev_d0f1;
187 	u32 tolm;
188 	u32 remapbase;
189 	u32 remaplimit;
190 	int mc_symmetric;
191 	u8 map[8];
192 	int map_type;
193 	const struct e752x_dev_info *dev_info;
194 };
195 
196 struct e752x_dev_info {
197 	u16 err_dev;
198 	u16 ctl_dev;
199 	const char *ctl_name;
200 };
201 
202 struct e752x_error_info {
203 	u32 ferr_global;
204 	u32 nerr_global;
205 	u32 nsi_ferr;	/* 3100 only */
206 	u32 nsi_nerr;	/* 3100 only */
207 	u8 hi_ferr;	/* all but 3100 */
208 	u8 hi_nerr;	/* all but 3100 */
209 	u16 sysbus_ferr;
210 	u16 sysbus_nerr;
211 	u8 buf_ferr;
212 	u8 buf_nerr;
213 	u16 dram_ferr;
214 	u16 dram_nerr;
215 	u32 dram_sec1_add;
216 	u32 dram_sec2_add;
217 	u16 dram_sec1_syndrome;
218 	u16 dram_sec2_syndrome;
219 	u32 dram_ded_add;
220 	u32 dram_scrb_add;
221 	u32 dram_retr_add;
222 };
223 
224 static const struct e752x_dev_info e752x_devs[] = {
225 	[E7520] = {
226 		.err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR,
227 		.ctl_dev = PCI_DEVICE_ID_INTEL_7520_0,
228 		.ctl_name = "E7520"},
229 	[E7525] = {
230 		.err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR,
231 		.ctl_dev = PCI_DEVICE_ID_INTEL_7525_0,
232 		.ctl_name = "E7525"},
233 	[E7320] = {
234 		.err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR,
235 		.ctl_dev = PCI_DEVICE_ID_INTEL_7320_0,
236 		.ctl_name = "E7320"},
237 	[I3100] = {
238 		.err_dev = PCI_DEVICE_ID_INTEL_3100_1_ERR,
239 		.ctl_dev = PCI_DEVICE_ID_INTEL_3100_0,
240 		.ctl_name = "3100"},
241 };
242 
243 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
244 				unsigned long page)
245 {
246 	u32 remap;
247 	struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
248 
249 	debugf3("%s()\n", __func__);
250 
251 	if (page < pvt->tolm)
252 		return page;
253 
254 	if ((page >= 0x100000) && (page < pvt->remapbase))
255 		return page;
256 
257 	remap = (page - pvt->tolm) + pvt->remapbase;
258 
259 	if (remap < pvt->remaplimit)
260 		return remap;
261 
262 	e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
263 	return pvt->tolm - 1;
264 }
265 
266 static void do_process_ce(struct mem_ctl_info *mci, u16 error_one,
267 			u32 sec1_add, u16 sec1_syndrome)
268 {
269 	u32 page;
270 	int row;
271 	int channel;
272 	int i;
273 	struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
274 
275 	debugf3("%s()\n", __func__);
276 
277 	/* convert the addr to 4k page */
278 	page = sec1_add >> (PAGE_SHIFT - 4);
279 
280 	/* FIXME - check for -1 */
281 	if (pvt->mc_symmetric) {
282 		/* chip select are bits 14 & 13 */
283 		row = ((page >> 1) & 3);
284 		e752x_printk(KERN_WARNING,
285 			"Test row %d Table %d %d %d %d %d %d %d %d\n", row,
286 			pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3],
287 			pvt->map[4], pvt->map[5], pvt->map[6],
288 			pvt->map[7]);
289 
290 		/* test for channel remapping */
291 		for (i = 0; i < 8; i++) {
292 			if (pvt->map[i] == row)
293 				break;
294 		}
295 
296 		e752x_printk(KERN_WARNING, "Test computed row %d\n", i);
297 
298 		if (i < 8)
299 			row = i;
300 		else
301 			e752x_mc_printk(mci, KERN_WARNING,
302 					"row %d not found in remap table\n",
303 					row);
304 	} else
305 		row = edac_mc_find_csrow_by_page(mci, page);
306 
307 	/* 0 = channel A, 1 = channel B */
308 	channel = !(error_one & 1);
309 
310 	/* e752x mc reads 34:6 of the DRAM linear address */
311 	edac_mc_handle_ce(mci, page, offset_in_page(sec1_add << 4),
312 			sec1_syndrome, row, channel, "e752x CE");
313 }
314 
315 static inline void process_ce(struct mem_ctl_info *mci, u16 error_one,
316 			u32 sec1_add, u16 sec1_syndrome, int *error_found,
317 			int handle_error)
318 {
319 	*error_found = 1;
320 
321 	if (handle_error)
322 		do_process_ce(mci, error_one, sec1_add, sec1_syndrome);
323 }
324 
325 static void do_process_ue(struct mem_ctl_info *mci, u16 error_one,
326 			u32 ded_add, u32 scrb_add)
327 {
328 	u32 error_2b, block_page;
329 	int row;
330 	struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
331 
332 	debugf3("%s()\n", __func__);
333 
334 	if (error_one & 0x0202) {
335 		error_2b = ded_add;
336 
337 		/* convert to 4k address */
338 		block_page = error_2b >> (PAGE_SHIFT - 4);
339 
340 		row = pvt->mc_symmetric ?
341 		/* chip select are bits 14 & 13 */
342 			((block_page >> 1) & 3) :
343 			edac_mc_find_csrow_by_page(mci, block_page);
344 
345 		/* e752x mc reads 34:6 of the DRAM linear address */
346 		edac_mc_handle_ue(mci, block_page,
347 				offset_in_page(error_2b << 4),
348 				row, "e752x UE from Read");
349 	}
350 	if (error_one & 0x0404) {
351 		error_2b = scrb_add;
352 
353 		/* convert to 4k address */
354 		block_page = error_2b >> (PAGE_SHIFT - 4);
355 
356 		row = pvt->mc_symmetric ?
357 		/* chip select are bits 14 & 13 */
358 			((block_page >> 1) & 3) :
359 			edac_mc_find_csrow_by_page(mci, block_page);
360 
361 		/* e752x mc reads 34:6 of the DRAM linear address */
362 		edac_mc_handle_ue(mci, block_page,
363 				offset_in_page(error_2b << 4),
364 				row, "e752x UE from Scruber");
365 	}
366 }
367 
368 static inline void process_ue(struct mem_ctl_info *mci, u16 error_one,
369 			u32 ded_add, u32 scrb_add, int *error_found,
370 			int handle_error)
371 {
372 	*error_found = 1;
373 
374 	if (handle_error)
375 		do_process_ue(mci, error_one, ded_add, scrb_add);
376 }
377 
378 static inline void process_ue_no_info_wr(struct mem_ctl_info *mci,
379 					 int *error_found, int handle_error)
380 {
381 	*error_found = 1;
382 
383 	if (!handle_error)
384 		return;
385 
386 	debugf3("%s()\n", __func__);
387 	edac_mc_handle_ue_no_info(mci, "e752x UE log memory write");
388 }
389 
390 static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error,
391 				 u32 retry_add)
392 {
393 	u32 error_1b, page;
394 	int row;
395 	struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
396 
397 	error_1b = retry_add;
398 	page = error_1b >> (PAGE_SHIFT - 4);  /* convert the addr to 4k page */
399 
400 	/* chip select are bits 14 & 13 */
401 	row = pvt->mc_symmetric ? ((page >> 1) & 3) :
402 		edac_mc_find_csrow_by_page(mci, page);
403 
404 	e752x_mc_printk(mci, KERN_WARNING,
405 			"CE page 0x%lx, row %d : Memory read retry\n",
406 			(long unsigned int)page, row);
407 }
408 
409 static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error,
410 				u32 retry_add, int *error_found,
411 				int handle_error)
412 {
413 	*error_found = 1;
414 
415 	if (handle_error)
416 		do_process_ded_retry(mci, error, retry_add);
417 }
418 
419 static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error,
420 					int *error_found, int handle_error)
421 {
422 	*error_found = 1;
423 
424 	if (handle_error)
425 		e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n");
426 }
427 
428 static char *global_message[11] = {
429 	"PCI Express C1",
430 	"PCI Express C",
431 	"PCI Express B1",
432 	"PCI Express B",
433 	"PCI Express A1",
434 	"PCI Express A",
435 	"DMA Controller",
436 	"HUB or NS Interface",
437 	"System Bus",
438 	"DRAM Controller",  /* 9th entry */
439 	"Internal Buffer"
440 };
441 
442 #define DRAM_ENTRY	9
443 
444 static char *fatal_message[2] = { "Non-Fatal ", "Fatal " };
445 
446 static void do_global_error(int fatal, u32 errors)
447 {
448 	int i;
449 
450 	for (i = 0; i < 11; i++) {
451 		if (errors & (1 << i)) {
452 			/* If the error is from DRAM Controller OR
453 			 * we are to report ALL errors, then
454 			 * report the error
455 			 */
456 			if ((i == DRAM_ENTRY) || report_non_memory_errors)
457 				e752x_printk(KERN_WARNING, "%sError %s\n",
458 					fatal_message[fatal],
459 					global_message[i]);
460 		}
461 	}
462 }
463 
464 static inline void global_error(int fatal, u32 errors, int *error_found,
465 				int handle_error)
466 {
467 	*error_found = 1;
468 
469 	if (handle_error)
470 		do_global_error(fatal, errors);
471 }
472 
473 static char *hub_message[7] = {
474 	"HI Address or Command Parity", "HI Illegal Access",
475 	"HI Internal Parity", "Out of Range Access",
476 	"HI Data Parity", "Enhanced Config Access",
477 	"Hub Interface Target Abort"
478 };
479 
480 static void do_hub_error(int fatal, u8 errors)
481 {
482 	int i;
483 
484 	for (i = 0; i < 7; i++) {
485 		if (errors & (1 << i))
486 			e752x_printk(KERN_WARNING, "%sError %s\n",
487 				fatal_message[fatal], hub_message[i]);
488 	}
489 }
490 
491 static inline void hub_error(int fatal, u8 errors, int *error_found,
492 			int handle_error)
493 {
494 	*error_found = 1;
495 
496 	if (handle_error)
497 		do_hub_error(fatal, errors);
498 }
499 
500 #define NSI_FATAL_MASK		0x0c080081
501 #define NSI_NON_FATAL_MASK	0x23a0ba64
502 #define NSI_ERR_MASK		(NSI_FATAL_MASK | NSI_NON_FATAL_MASK)
503 
504 static char *nsi_message[30] = {
505 	"NSI Link Down",	/* NSI_FERR/NSI_NERR bit 0, fatal error */
506 	"",						/* reserved */
507 	"NSI Parity Error",				/* bit 2, non-fatal */
508 	"",						/* reserved */
509 	"",						/* reserved */
510 	"Correctable Error Message",			/* bit 5, non-fatal */
511 	"Non-Fatal Error Message",			/* bit 6, non-fatal */
512 	"Fatal Error Message",				/* bit 7, fatal */
513 	"",						/* reserved */
514 	"Receiver Error",				/* bit 9, non-fatal */
515 	"",						/* reserved */
516 	"Bad TLP",					/* bit 11, non-fatal */
517 	"Bad DLLP",					/* bit 12, non-fatal */
518 	"REPLAY_NUM Rollover",				/* bit 13, non-fatal */
519 	"",						/* reserved */
520 	"Replay Timer Timeout",				/* bit 15, non-fatal */
521 	"",						/* reserved */
522 	"",						/* reserved */
523 	"",						/* reserved */
524 	"Data Link Protocol Error",			/* bit 19, fatal */
525 	"",						/* reserved */
526 	"Poisoned TLP",					/* bit 21, non-fatal */
527 	"",						/* reserved */
528 	"Completion Timeout",				/* bit 23, non-fatal */
529 	"Completer Abort",				/* bit 24, non-fatal */
530 	"Unexpected Completion",			/* bit 25, non-fatal */
531 	"Receiver Overflow",				/* bit 26, fatal */
532 	"Malformed TLP",				/* bit 27, fatal */
533 	"",						/* reserved */
534 	"Unsupported Request"				/* bit 29, non-fatal */
535 };
536 
537 static void do_nsi_error(int fatal, u32 errors)
538 {
539 	int i;
540 
541 	for (i = 0; i < 30; i++) {
542 		if (errors & (1 << i))
543 			printk(KERN_WARNING "%sError %s\n",
544 			       fatal_message[fatal], nsi_message[i]);
545 	}
546 }
547 
548 static inline void nsi_error(int fatal, u32 errors, int *error_found,
549 		int handle_error)
550 {
551 	*error_found = 1;
552 
553 	if (handle_error)
554 		do_nsi_error(fatal, errors);
555 }
556 
557 static char *membuf_message[4] = {
558 	"Internal PMWB to DRAM parity",
559 	"Internal PMWB to System Bus Parity",
560 	"Internal System Bus or IO to PMWB Parity",
561 	"Internal DRAM to PMWB Parity"
562 };
563 
564 static void do_membuf_error(u8 errors)
565 {
566 	int i;
567 
568 	for (i = 0; i < 4; i++) {
569 		if (errors & (1 << i))
570 			e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n",
571 				membuf_message[i]);
572 	}
573 }
574 
575 static inline void membuf_error(u8 errors, int *error_found, int handle_error)
576 {
577 	*error_found = 1;
578 
579 	if (handle_error)
580 		do_membuf_error(errors);
581 }
582 
583 static char *sysbus_message[10] = {
584 	"Addr or Request Parity",
585 	"Data Strobe Glitch",
586 	"Addr Strobe Glitch",
587 	"Data Parity",
588 	"Addr Above TOM",
589 	"Non DRAM Lock Error",
590 	"MCERR", "BINIT",
591 	"Memory Parity",
592 	"IO Subsystem Parity"
593 };
594 
595 static void do_sysbus_error(int fatal, u32 errors)
596 {
597 	int i;
598 
599 	for (i = 0; i < 10; i++) {
600 		if (errors & (1 << i))
601 			e752x_printk(KERN_WARNING, "%sError System Bus %s\n",
602 				fatal_message[fatal], sysbus_message[i]);
603 	}
604 }
605 
606 static inline void sysbus_error(int fatal, u32 errors, int *error_found,
607 				int handle_error)
608 {
609 	*error_found = 1;
610 
611 	if (handle_error)
612 		do_sysbus_error(fatal, errors);
613 }
614 
615 static void e752x_check_hub_interface(struct e752x_error_info *info,
616 				int *error_found, int handle_error)
617 {
618 	u8 stat8;
619 
620 	//pci_read_config_byte(dev,E752X_HI_FERR,&stat8);
621 
622 	stat8 = info->hi_ferr;
623 
624 	if (stat8 & 0x7f) {	/* Error, so process */
625 		stat8 &= 0x7f;
626 
627 		if (stat8 & 0x2b)
628 			hub_error(1, stat8 & 0x2b, error_found, handle_error);
629 
630 		if (stat8 & 0x54)
631 			hub_error(0, stat8 & 0x54, error_found, handle_error);
632 	}
633 	//pci_read_config_byte(dev,E752X_HI_NERR,&stat8);
634 
635 	stat8 = info->hi_nerr;
636 
637 	if (stat8 & 0x7f) {	/* Error, so process */
638 		stat8 &= 0x7f;
639 
640 		if (stat8 & 0x2b)
641 			hub_error(1, stat8 & 0x2b, error_found, handle_error);
642 
643 		if (stat8 & 0x54)
644 			hub_error(0, stat8 & 0x54, error_found, handle_error);
645 	}
646 }
647 
648 static void e752x_check_ns_interface(struct e752x_error_info *info,
649 				int *error_found, int handle_error)
650 {
651 	u32 stat32;
652 
653 	stat32 = info->nsi_ferr;
654 	if (stat32 & NSI_ERR_MASK) { /* Error, so process */
655 		if (stat32 & NSI_FATAL_MASK)	/* check for fatal errors */
656 			nsi_error(1, stat32 & NSI_FATAL_MASK, error_found,
657 				  handle_error);
658 		if (stat32 & NSI_NON_FATAL_MASK) /* check for non-fatal ones */
659 			nsi_error(0, stat32 & NSI_NON_FATAL_MASK, error_found,
660 				  handle_error);
661 	}
662 	stat32 = info->nsi_nerr;
663 	if (stat32 & NSI_ERR_MASK) {
664 		if (stat32 & NSI_FATAL_MASK)
665 			nsi_error(1, stat32 & NSI_FATAL_MASK, error_found,
666 				  handle_error);
667 		if (stat32 & NSI_NON_FATAL_MASK)
668 			nsi_error(0, stat32 & NSI_NON_FATAL_MASK, error_found,
669 				  handle_error);
670 	}
671 }
672 
673 static void e752x_check_sysbus(struct e752x_error_info *info,
674 			int *error_found, int handle_error)
675 {
676 	u32 stat32, error32;
677 
678 	//pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32);
679 	stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16);
680 
681 	if (stat32 == 0)
682 		return;		/* no errors */
683 
684 	error32 = (stat32 >> 16) & 0x3ff;
685 	stat32 = stat32 & 0x3ff;
686 
687 	if (stat32 & 0x087)
688 		sysbus_error(1, stat32 & 0x087, error_found, handle_error);
689 
690 	if (stat32 & 0x378)
691 		sysbus_error(0, stat32 & 0x378, error_found, handle_error);
692 
693 	if (error32 & 0x087)
694 		sysbus_error(1, error32 & 0x087, error_found, handle_error);
695 
696 	if (error32 & 0x378)
697 		sysbus_error(0, error32 & 0x378, error_found, handle_error);
698 }
699 
700 static void e752x_check_membuf(struct e752x_error_info *info,
701 			int *error_found, int handle_error)
702 {
703 	u8 stat8;
704 
705 	stat8 = info->buf_ferr;
706 
707 	if (stat8 & 0x0f) {	/* Error, so process */
708 		stat8 &= 0x0f;
709 		membuf_error(stat8, error_found, handle_error);
710 	}
711 
712 	stat8 = info->buf_nerr;
713 
714 	if (stat8 & 0x0f) {	/* Error, so process */
715 		stat8 &= 0x0f;
716 		membuf_error(stat8, error_found, handle_error);
717 	}
718 }
719 
720 static void e752x_check_dram(struct mem_ctl_info *mci,
721 			struct e752x_error_info *info, int *error_found,
722 			int handle_error)
723 {
724 	u16 error_one, error_next;
725 
726 	error_one = info->dram_ferr;
727 	error_next = info->dram_nerr;
728 
729 	/* decode and report errors */
730 	if (error_one & 0x0101)	/* check first error correctable */
731 		process_ce(mci, error_one, info->dram_sec1_add,
732 			info->dram_sec1_syndrome, error_found, handle_error);
733 
734 	if (error_next & 0x0101)	/* check next error correctable */
735 		process_ce(mci, error_next, info->dram_sec2_add,
736 			info->dram_sec2_syndrome, error_found, handle_error);
737 
738 	if (error_one & 0x4040)
739 		process_ue_no_info_wr(mci, error_found, handle_error);
740 
741 	if (error_next & 0x4040)
742 		process_ue_no_info_wr(mci, error_found, handle_error);
743 
744 	if (error_one & 0x2020)
745 		process_ded_retry(mci, error_one, info->dram_retr_add,
746 				error_found, handle_error);
747 
748 	if (error_next & 0x2020)
749 		process_ded_retry(mci, error_next, info->dram_retr_add,
750 				error_found, handle_error);
751 
752 	if (error_one & 0x0808)
753 		process_threshold_ce(mci, error_one, error_found, handle_error);
754 
755 	if (error_next & 0x0808)
756 		process_threshold_ce(mci, error_next, error_found,
757 				handle_error);
758 
759 	if (error_one & 0x0606)
760 		process_ue(mci, error_one, info->dram_ded_add,
761 			info->dram_scrb_add, error_found, handle_error);
762 
763 	if (error_next & 0x0606)
764 		process_ue(mci, error_next, info->dram_ded_add,
765 			info->dram_scrb_add, error_found, handle_error);
766 }
767 
768 static void e752x_get_error_info(struct mem_ctl_info *mci,
769 				 struct e752x_error_info *info)
770 {
771 	struct pci_dev *dev;
772 	struct e752x_pvt *pvt;
773 
774 	memset(info, 0, sizeof(*info));
775 	pvt = (struct e752x_pvt *)mci->pvt_info;
776 	dev = pvt->dev_d0f1;
777 	pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global);
778 
779 	if (info->ferr_global) {
780 		if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) {
781 			pci_read_config_dword(dev, I3100_NSI_FERR,
782 					     &info->nsi_ferr);
783 			info->hi_ferr = 0;
784 		} else {
785 			pci_read_config_byte(dev, E752X_HI_FERR,
786 					     &info->hi_ferr);
787 			info->nsi_ferr = 0;
788 		}
789 		pci_read_config_word(dev, E752X_SYSBUS_FERR,
790 				&info->sysbus_ferr);
791 		pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr);
792 		pci_read_config_word(dev, E752X_DRAM_FERR, &info->dram_ferr);
793 		pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD,
794 				&info->dram_sec1_add);
795 		pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME,
796 				&info->dram_sec1_syndrome);
797 		pci_read_config_dword(dev, E752X_DRAM_DED_ADD,
798 				&info->dram_ded_add);
799 		pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD,
800 				&info->dram_scrb_add);
801 		pci_read_config_dword(dev, E752X_DRAM_RETR_ADD,
802 				&info->dram_retr_add);
803 
804 		/* ignore the reserved bits just in case */
805 		if (info->hi_ferr & 0x7f)
806 			pci_write_config_byte(dev, E752X_HI_FERR,
807 					info->hi_ferr);
808 
809 		if (info->nsi_ferr & NSI_ERR_MASK)
810 			pci_write_config_dword(dev, I3100_NSI_FERR,
811 					info->nsi_ferr);
812 
813 		if (info->sysbus_ferr)
814 			pci_write_config_word(dev, E752X_SYSBUS_FERR,
815 					info->sysbus_ferr);
816 
817 		if (info->buf_ferr & 0x0f)
818 			pci_write_config_byte(dev, E752X_BUF_FERR,
819 					info->buf_ferr);
820 
821 		if (info->dram_ferr)
822 			pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR,
823 					 info->dram_ferr, info->dram_ferr);
824 
825 		pci_write_config_dword(dev, E752X_FERR_GLOBAL,
826 				info->ferr_global);
827 	}
828 
829 	pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global);
830 
831 	if (info->nerr_global) {
832 		if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) {
833 			pci_read_config_dword(dev, I3100_NSI_NERR,
834 					     &info->nsi_nerr);
835 			info->hi_nerr = 0;
836 		} else {
837 			pci_read_config_byte(dev, E752X_HI_NERR,
838 					     &info->hi_nerr);
839 			info->nsi_nerr = 0;
840 		}
841 		pci_read_config_word(dev, E752X_SYSBUS_NERR,
842 				&info->sysbus_nerr);
843 		pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr);
844 		pci_read_config_word(dev, E752X_DRAM_NERR, &info->dram_nerr);
845 		pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD,
846 				&info->dram_sec2_add);
847 		pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME,
848 				&info->dram_sec2_syndrome);
849 
850 		if (info->hi_nerr & 0x7f)
851 			pci_write_config_byte(dev, E752X_HI_NERR,
852 					info->hi_nerr);
853 
854 		if (info->nsi_nerr & NSI_ERR_MASK)
855 			pci_write_config_dword(dev, I3100_NSI_NERR,
856 					info->nsi_nerr);
857 
858 		if (info->sysbus_nerr)
859 			pci_write_config_word(dev, E752X_SYSBUS_NERR,
860 					info->sysbus_nerr);
861 
862 		if (info->buf_nerr & 0x0f)
863 			pci_write_config_byte(dev, E752X_BUF_NERR,
864 					info->buf_nerr);
865 
866 		if (info->dram_nerr)
867 			pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR,
868 					 info->dram_nerr, info->dram_nerr);
869 
870 		pci_write_config_dword(dev, E752X_NERR_GLOBAL,
871 				info->nerr_global);
872 	}
873 }
874 
875 static int e752x_process_error_info(struct mem_ctl_info *mci,
876 				struct e752x_error_info *info,
877 				int handle_errors)
878 {
879 	u32 error32, stat32;
880 	int error_found;
881 
882 	error_found = 0;
883 	error32 = (info->ferr_global >> 18) & 0x3ff;
884 	stat32 = (info->ferr_global >> 4) & 0x7ff;
885 
886 	if (error32)
887 		global_error(1, error32, &error_found, handle_errors);
888 
889 	if (stat32)
890 		global_error(0, stat32, &error_found, handle_errors);
891 
892 	error32 = (info->nerr_global >> 18) & 0x3ff;
893 	stat32 = (info->nerr_global >> 4) & 0x7ff;
894 
895 	if (error32)
896 		global_error(1, error32, &error_found, handle_errors);
897 
898 	if (stat32)
899 		global_error(0, stat32, &error_found, handle_errors);
900 
901 	e752x_check_hub_interface(info, &error_found, handle_errors);
902 	e752x_check_ns_interface(info, &error_found, handle_errors);
903 	e752x_check_sysbus(info, &error_found, handle_errors);
904 	e752x_check_membuf(info, &error_found, handle_errors);
905 	e752x_check_dram(mci, info, &error_found, handle_errors);
906 	return error_found;
907 }
908 
909 static void e752x_check(struct mem_ctl_info *mci)
910 {
911 	struct e752x_error_info info;
912 
913 	debugf3("%s()\n", __func__);
914 	e752x_get_error_info(mci, &info);
915 	e752x_process_error_info(mci, &info, 1);
916 }
917 
918 /* Return 1 if dual channel mode is active.  Else return 0. */
919 static inline int dual_channel_active(u16 ddrcsr)
920 {
921 	return (((ddrcsr >> 12) & 3) == 3);
922 }
923 
924 /* Remap csrow index numbers if map_type is "reverse"
925  */
926 static inline int remap_csrow_index(struct mem_ctl_info *mci, int index)
927 {
928 	struct e752x_pvt *pvt = mci->pvt_info;
929 
930 	if (!pvt->map_type)
931 		return (7 - index);
932 
933 	return (index);
934 }
935 
936 static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
937 			u16 ddrcsr)
938 {
939 	struct csrow_info *csrow;
940 	unsigned long last_cumul_size;
941 	int index, mem_dev, drc_chan;
942 	int drc_drbg;		/* DRB granularity 0=64mb, 1=128mb */
943 	int drc_ddim;		/* DRAM Data Integrity Mode 0=none, 2=edac */
944 	u8 value;
945 	u32 dra, drc, cumul_size;
946 
947 	dra = 0;
948 	for (index = 0; index < 4; index++) {
949 		u8 dra_reg;
950 		pci_read_config_byte(pdev, E752X_DRA + index, &dra_reg);
951 		dra |= dra_reg << (index * 8);
952 	}
953 	pci_read_config_dword(pdev, E752X_DRC, &drc);
954 	drc_chan = dual_channel_active(ddrcsr);
955 	drc_drbg = drc_chan + 1;	/* 128 in dual mode, 64 in single */
956 	drc_ddim = (drc >> 20) & 0x3;
957 
958 	/* The dram row boundary (DRB) reg values are boundary address for
959 	 * each DRAM row with a granularity of 64 or 128MB (single/dual
960 	 * channel operation).  DRB regs are cumulative; therefore DRB7 will
961 	 * contain the total memory contained in all eight rows.
962 	 */
963 	for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
964 		/* mem_dev 0=x8, 1=x4 */
965 		mem_dev = (dra >> (index * 4 + 2)) & 0x3;
966 		csrow = &mci->csrows[remap_csrow_index(mci, index)];
967 
968 		mem_dev = (mem_dev == 2);
969 		pci_read_config_byte(pdev, E752X_DRB + index, &value);
970 		/* convert a 128 or 64 MiB DRB to a page size. */
971 		cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
972 		debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
973 			cumul_size);
974 		if (cumul_size == last_cumul_size)
975 			continue;	/* not populated */
976 
977 		csrow->first_page = last_cumul_size;
978 		csrow->last_page = cumul_size - 1;
979 		csrow->nr_pages = cumul_size - last_cumul_size;
980 		last_cumul_size = cumul_size;
981 		csrow->grain = 1 << 12;	/* 4KiB - resolution of CELOG */
982 		csrow->mtype = MEM_RDDR;	/* only one type supported */
983 		csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
984 
985 		/*
986 		 * if single channel or x8 devices then SECDED
987 		 * if dual channel and x4 then S4ECD4ED
988 		 */
989 		if (drc_ddim) {
990 			if (drc_chan && mem_dev) {
991 				csrow->edac_mode = EDAC_S4ECD4ED;
992 				mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
993 			} else {
994 				csrow->edac_mode = EDAC_SECDED;
995 				mci->edac_cap |= EDAC_FLAG_SECDED;
996 			}
997 		} else
998 			csrow->edac_mode = EDAC_NONE;
999 	}
1000 }
1001 
1002 static void e752x_init_mem_map_table(struct pci_dev *pdev,
1003 				struct e752x_pvt *pvt)
1004 {
1005 	int index;
1006 	u8 value, last, row;
1007 
1008 	last = 0;
1009 	row = 0;
1010 
1011 	for (index = 0; index < 8; index += 2) {
1012 		pci_read_config_byte(pdev, E752X_DRB + index, &value);
1013 		/* test if there is a dimm in this slot */
1014 		if (value == last) {
1015 			/* no dimm in the slot, so flag it as empty */
1016 			pvt->map[index] = 0xff;
1017 			pvt->map[index + 1] = 0xff;
1018 		} else {	/* there is a dimm in the slot */
1019 			pvt->map[index] = row;
1020 			row++;
1021 			last = value;
1022 			/* test the next value to see if the dimm is double
1023 			 * sided
1024 			 */
1025 			pci_read_config_byte(pdev, E752X_DRB + index + 1,
1026 					&value);
1027 
1028 			/* the dimm is single sided, so flag as empty */
1029 			/* this is a double sided dimm to save the next row #*/
1030 			pvt->map[index + 1] = (value == last) ? 0xff :	row;
1031 			row++;
1032 			last = value;
1033 		}
1034 	}
1035 }
1036 
1037 /* Return 0 on success or 1 on failure. */
1038 static int e752x_get_devs(struct pci_dev *pdev, int dev_idx,
1039 			struct e752x_pvt *pvt)
1040 {
1041 	struct pci_dev *dev;
1042 
1043 	pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
1044 				pvt->dev_info->err_dev, pvt->bridge_ck);
1045 
1046 	if (pvt->bridge_ck == NULL)
1047 		pvt->bridge_ck = pci_scan_single_device(pdev->bus,
1048 							PCI_DEVFN(0, 1));
1049 
1050 	if (pvt->bridge_ck == NULL) {
1051 		e752x_printk(KERN_ERR, "error reporting device not found:"
1052 			"vendor %x device 0x%x (broken BIOS?)\n",
1053 			PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev);
1054 		return 1;
1055 	}
1056 
1057 	dev = pci_get_device(PCI_VENDOR_ID_INTEL,
1058 				e752x_devs[dev_idx].ctl_dev,
1059 				NULL);
1060 
1061 	if (dev == NULL)
1062 		goto fail;
1063 
1064 	pvt->dev_d0f0 = dev;
1065 	pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck);
1066 
1067 	return 0;
1068 
1069 fail:
1070 	pci_dev_put(pvt->bridge_ck);
1071 	return 1;
1072 }
1073 
1074 /* Setup system bus parity mask register.
1075  * Sysbus parity supported on:
1076  *   e7320/e7520/e7525 + Xeon
1077  *   i3100 + Xeon/Celeron
1078  * Sysbus parity not supported on:
1079  *   i3100 + Pentium M/Celeron M/Core Duo/Core2 Duo
1080  */
1081 static void e752x_init_sysbus_parity_mask(struct e752x_pvt *pvt)
1082 {
1083 	char *cpu_id = cpu_data(0).x86_model_id;
1084 	struct pci_dev *dev = pvt->dev_d0f1;
1085 	int enable = 1;
1086 
1087 	/* Allow module paramter override, else see if CPU supports parity */
1088 	if (sysbus_parity != -1) {
1089 		enable = sysbus_parity;
1090 	} else if (cpu_id[0] &&
1091 		   ((strstr(cpu_id, "Pentium") && strstr(cpu_id, " M ")) ||
1092 		    (strstr(cpu_id, "Celeron") && strstr(cpu_id, " M ")) ||
1093 		    (strstr(cpu_id, "Core") && strstr(cpu_id, "Duo")))) {
1094 		e752x_printk(KERN_INFO, "System Bus Parity not "
1095 			     "supported by CPU, disabling\n");
1096 		enable = 0;
1097 	}
1098 
1099 	if (enable)
1100 		pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x0000);
1101 	else
1102 		pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x0309);
1103 }
1104 
1105 static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt)
1106 {
1107 	struct pci_dev *dev;
1108 
1109 	dev = pvt->dev_d0f1;
1110 	/* Turn off error disable & SMI in case the BIOS turned it on */
1111 	if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) {
1112 		pci_write_config_dword(dev, I3100_NSI_EMASK, 0);
1113 		pci_write_config_dword(dev, I3100_NSI_SMICMD, 0);
1114 	} else {
1115 		pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00);
1116 		pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00);
1117 	}
1118 
1119 	e752x_init_sysbus_parity_mask(pvt);
1120 
1121 	pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00);
1122 	pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00);
1123 	pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00);
1124 	pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00);
1125 	pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00);
1126 }
1127 
1128 static int e752x_probe1(struct pci_dev *pdev, int dev_idx)
1129 {
1130 	u16 pci_data;
1131 	u8 stat8;
1132 	struct mem_ctl_info *mci;
1133 	struct e752x_pvt *pvt;
1134 	u16 ddrcsr;
1135 	int drc_chan;		/* Number of channels 0=1chan,1=2chan */
1136 	struct e752x_error_info discard;
1137 
1138 	debugf0("%s(): mci\n", __func__);
1139 	debugf0("Starting Probe1\n");
1140 
1141 	/* check to see if device 0 function 1 is enabled; if it isn't, we
1142 	 * assume the BIOS has reserved it for a reason and is expecting
1143 	 * exclusive access, we take care not to violate that assumption and
1144 	 * fail the probe. */
1145 	pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8);
1146 	if (!force_function_unhide && !(stat8 & (1 << 5))) {
1147 		printk(KERN_INFO "Contact your BIOS vendor to see if the "
1148 			"E752x error registers can be safely un-hidden\n");
1149 		return -ENODEV;
1150 	}
1151 	stat8 |= (1 << 5);
1152 	pci_write_config_byte(pdev, E752X_DEVPRES1, stat8);
1153 
1154 	pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr);
1155 	/* FIXME: should check >>12 or 0xf, true for all? */
1156 	/* Dual channel = 1, Single channel = 0 */
1157 	drc_chan = dual_channel_active(ddrcsr);
1158 
1159 	mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1, 0);
1160 
1161 	if (mci == NULL) {
1162 		return -ENOMEM;
1163 	}
1164 
1165 	debugf3("%s(): init mci\n", __func__);
1166 	mci->mtype_cap = MEM_FLAG_RDDR;
1167 	/* 3100 IMCH supports SECDEC only */
1168 	mci->edac_ctl_cap = (dev_idx == I3100) ? EDAC_FLAG_SECDED :
1169 		(EDAC_FLAG_NONE | EDAC_FLAG_SECDED | EDAC_FLAG_S4ECD4ED);
1170 	/* FIXME - what if different memory types are in different csrows? */
1171 	mci->mod_name = EDAC_MOD_STR;
1172 	mci->mod_ver = E752X_REVISION;
1173 	mci->dev = &pdev->dev;
1174 
1175 	debugf3("%s(): init pvt\n", __func__);
1176 	pvt = (struct e752x_pvt *)mci->pvt_info;
1177 	pvt->dev_info = &e752x_devs[dev_idx];
1178 	pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
1179 
1180 	if (e752x_get_devs(pdev, dev_idx, pvt)) {
1181 		edac_mc_free(mci);
1182 		return -ENODEV;
1183 	}
1184 
1185 	debugf3("%s(): more mci init\n", __func__);
1186 	mci->ctl_name = pvt->dev_info->ctl_name;
1187 	mci->dev_name = pci_name(pdev);
1188 	mci->edac_check = e752x_check;
1189 	mci->ctl_page_to_phys = ctl_page_to_phys;
1190 
1191 	/* set the map type.  1 = normal, 0 = reversed
1192 	 * Must be set before e752x_init_csrows in case csrow mapping
1193 	 * is reversed.
1194 	 */
1195 	pci_read_config_byte(pdev, E752X_DRM, &stat8);
1196 	pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
1197 
1198 	e752x_init_csrows(mci, pdev, ddrcsr);
1199 	e752x_init_mem_map_table(pdev, pvt);
1200 
1201 	if (dev_idx == I3100)
1202 		mci->edac_cap = EDAC_FLAG_SECDED; /* the only mode supported */
1203 	else
1204 		mci->edac_cap |= EDAC_FLAG_NONE;
1205 	debugf3("%s(): tolm, remapbase, remaplimit\n", __func__);
1206 
1207 	/* load the top of low memory, remap base, and remap limit vars */
1208 	pci_read_config_word(pdev, E752X_TOLM, &pci_data);
1209 	pvt->tolm = ((u32) pci_data) << 4;
1210 	pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data);
1211 	pvt->remapbase = ((u32) pci_data) << 14;
1212 	pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data);
1213 	pvt->remaplimit = ((u32) pci_data) << 14;
1214 	e752x_printk(KERN_INFO,
1215 			"tolm = %x, remapbase = %x, remaplimit = %x\n",
1216 			pvt->tolm, pvt->remapbase, pvt->remaplimit);
1217 
1218 	/* Here we assume that we will never see multiple instances of this
1219 	 * type of memory controller.  The ID is therefore hardcoded to 0.
1220 	 */
1221 	if (edac_mc_add_mc(mci)) {
1222 		debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
1223 		goto fail;
1224 	}
1225 
1226 	e752x_init_error_reporting_regs(pvt);
1227 	e752x_get_error_info(mci, &discard);	/* clear other MCH errors */
1228 
1229 	/* allocating generic PCI control info */
1230 	e752x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1231 	if (!e752x_pci) {
1232 		printk(KERN_WARNING
1233 			"%s(): Unable to create PCI control\n", __func__);
1234 		printk(KERN_WARNING
1235 			"%s(): PCI error report via EDAC not setup\n",
1236 			__func__);
1237 	}
1238 
1239 	/* get this far and it's successful */
1240 	debugf3("%s(): success\n", __func__);
1241 	return 0;
1242 
1243 fail:
1244 	pci_dev_put(pvt->dev_d0f0);
1245 	pci_dev_put(pvt->dev_d0f1);
1246 	pci_dev_put(pvt->bridge_ck);
1247 	edac_mc_free(mci);
1248 
1249 	return -ENODEV;
1250 }
1251 
1252 /* returns count (>= 0), or negative on error */
1253 static int __devinit e752x_init_one(struct pci_dev *pdev,
1254 				const struct pci_device_id *ent)
1255 {
1256 	debugf0("%s()\n", __func__);
1257 
1258 	/* wake up and enable device */
1259 	if (pci_enable_device(pdev) < 0)
1260 		return -EIO;
1261 
1262 	return e752x_probe1(pdev, ent->driver_data);
1263 }
1264 
1265 static void __devexit e752x_remove_one(struct pci_dev *pdev)
1266 {
1267 	struct mem_ctl_info *mci;
1268 	struct e752x_pvt *pvt;
1269 
1270 	debugf0("%s()\n", __func__);
1271 
1272 	if (e752x_pci)
1273 		edac_pci_release_generic_ctl(e752x_pci);
1274 
1275 	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
1276 		return;
1277 
1278 	pvt = (struct e752x_pvt *)mci->pvt_info;
1279 	pci_dev_put(pvt->dev_d0f0);
1280 	pci_dev_put(pvt->dev_d0f1);
1281 	pci_dev_put(pvt->bridge_ck);
1282 	edac_mc_free(mci);
1283 }
1284 
1285 static const struct pci_device_id e752x_pci_tbl[] __devinitdata = {
1286 	{
1287 	 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1288 	 E7520},
1289 	{
1290 	 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1291 	 E7525},
1292 	{
1293 	 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1294 	 E7320},
1295 	{
1296 	 PCI_VEND_DEV(INTEL, 3100_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1297 	 I3100},
1298 	{
1299 	 0,
1300 	 }			/* 0 terminated list. */
1301 };
1302 
1303 MODULE_DEVICE_TABLE(pci, e752x_pci_tbl);
1304 
1305 static struct pci_driver e752x_driver = {
1306 	.name = EDAC_MOD_STR,
1307 	.probe = e752x_init_one,
1308 	.remove = __devexit_p(e752x_remove_one),
1309 	.id_table = e752x_pci_tbl,
1310 };
1311 
1312 static int __init e752x_init(void)
1313 {
1314 	int pci_rc;
1315 
1316 	debugf3("%s()\n", __func__);
1317 
1318        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1319        opstate_init();
1320 
1321 	pci_rc = pci_register_driver(&e752x_driver);
1322 	return (pci_rc < 0) ? pci_rc : 0;
1323 }
1324 
1325 static void __exit e752x_exit(void)
1326 {
1327 	debugf3("%s()\n", __func__);
1328 	pci_unregister_driver(&e752x_driver);
1329 }
1330 
1331 module_init(e752x_init);
1332 module_exit(e752x_exit);
1333 
1334 MODULE_LICENSE("GPL");
1335 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n");
1336 MODULE_DESCRIPTION("MC support for Intel e752x/3100 memory controllers");
1337 
1338 module_param(force_function_unhide, int, 0444);
1339 MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:"
1340 		 " 1=force unhide and hope BIOS doesn't fight driver for "
1341 		"Dev0:Fun1 access");
1342 
1343 module_param(edac_op_state, int, 0444);
1344 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1345 
1346 module_param(sysbus_parity, int, 0444);
1347 MODULE_PARM_DESC(sysbus_parity, "0=disable system bus parity checking,"
1348 		" 1=enable system bus parity checking, default=auto-detect");
1349 module_param(report_non_memory_errors, int, 0644);
1350 MODULE_PARM_DESC(report_non_memory_errors, "0=disable non-memory error "
1351 		"reporting, 1=enable non-memory error reporting");
1352