1 /* 2 * Intel e752x Memory Controller kernel module 3 * (C) 2004 Linux Networx (http://lnxi.com) 4 * This file may be distributed under the terms of the 5 * GNU General Public License. 6 * 7 * See "enum e752x_chips" below for supported chipsets 8 * 9 * Written by Tom Zimmerman 10 * 11 * Contributors: 12 * Thayne Harbaugh at realmsys.com (?) 13 * Wang Zhenyu at intel.com 14 * Dave Jiang at mvista.com 15 * 16 * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $ 17 * 18 */ 19 20 #include <linux/module.h> 21 #include <linux/init.h> 22 #include <linux/pci.h> 23 #include <linux/pci_ids.h> 24 #include <linux/edac.h> 25 #include "edac_core.h" 26 27 #define E752X_REVISION " Ver: 2.0.2 " __DATE__ 28 #define EDAC_MOD_STR "e752x_edac" 29 30 static int report_non_memory_errors; 31 static int force_function_unhide; 32 static int sysbus_parity = -1; 33 34 static struct edac_pci_ctl_info *e752x_pci; 35 36 #define e752x_printk(level, fmt, arg...) \ 37 edac_printk(level, "e752x", fmt, ##arg) 38 39 #define e752x_mc_printk(mci, level, fmt, arg...) \ 40 edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg) 41 42 #ifndef PCI_DEVICE_ID_INTEL_7520_0 43 #define PCI_DEVICE_ID_INTEL_7520_0 0x3590 44 #endif /* PCI_DEVICE_ID_INTEL_7520_0 */ 45 46 #ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR 47 #define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591 48 #endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */ 49 50 #ifndef PCI_DEVICE_ID_INTEL_7525_0 51 #define PCI_DEVICE_ID_INTEL_7525_0 0x359E 52 #endif /* PCI_DEVICE_ID_INTEL_7525_0 */ 53 54 #ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR 55 #define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593 56 #endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */ 57 58 #ifndef PCI_DEVICE_ID_INTEL_7320_0 59 #define PCI_DEVICE_ID_INTEL_7320_0 0x3592 60 #endif /* PCI_DEVICE_ID_INTEL_7320_0 */ 61 62 #ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR 63 #define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593 64 #endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */ 65 66 #ifndef PCI_DEVICE_ID_INTEL_3100_0 67 #define PCI_DEVICE_ID_INTEL_3100_0 0x35B0 68 #endif /* PCI_DEVICE_ID_INTEL_3100_0 */ 69 70 #ifndef PCI_DEVICE_ID_INTEL_3100_1_ERR 71 #define PCI_DEVICE_ID_INTEL_3100_1_ERR 0x35B1 72 #endif /* PCI_DEVICE_ID_INTEL_3100_1_ERR */ 73 74 #define E752X_NR_CSROWS 8 /* number of csrows */ 75 76 /* E752X register addresses - device 0 function 0 */ 77 #define E752X_MCHSCRB 0x52 /* Memory Scrub register (16b) */ 78 /* 79 * 6:5 Scrub Completion Count 80 * 3:2 Scrub Rate (i3100 only) 81 * 01=fast 10=normal 82 * 1:0 Scrub Mode enable 83 * 00=off 10=on 84 */ 85 #define E752X_DRB 0x60 /* DRAM row boundary register (8b) */ 86 #define E752X_DRA 0x70 /* DRAM row attribute register (8b) */ 87 /* 88 * 31:30 Device width row 7 89 * 01=x8 10=x4 11=x8 DDR2 90 * 27:26 Device width row 6 91 * 23:22 Device width row 5 92 * 19:20 Device width row 4 93 * 15:14 Device width row 3 94 * 11:10 Device width row 2 95 * 7:6 Device width row 1 96 * 3:2 Device width row 0 97 */ 98 #define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */ 99 /* FIXME:IS THIS RIGHT? */ 100 /* 101 * 22 Number channels 0=1,1=2 102 * 19:18 DRB Granularity 32/64MB 103 */ 104 #define E752X_DRM 0x80 /* Dimm mapping register */ 105 #define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */ 106 /* 107 * 14:12 1 single A, 2 single B, 3 dual 108 */ 109 #define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */ 110 #define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */ 111 #define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */ 112 #define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */ 113 114 /* E752X register addresses - device 0 function 1 */ 115 #define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */ 116 #define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */ 117 #define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */ 118 #define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */ 119 #define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */ 120 #define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */ 121 #define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */ 122 #define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */ 123 #define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */ 124 #define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */ 125 #define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */ 126 #define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */ 127 #define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */ 128 #define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI cmd reg (8b) */ 129 #define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */ 130 #define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */ 131 #define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */ 132 #define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */ 133 #define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */ 134 #define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */ 135 /* error address register (32b) */ 136 /* 137 * 31 Reserved 138 * 30:2 CE address (64 byte block 34:6 139 * 1 Reserved 140 * 0 HiLoCS 141 */ 142 #define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */ 143 /* error address register (32b) */ 144 /* 145 * 31 Reserved 146 * 30:2 CE address (64 byte block 34:6) 147 * 1 Reserved 148 * 0 HiLoCS 149 */ 150 #define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */ 151 /* error address register (32b) */ 152 /* 153 * 31 Reserved 154 * 30:2 CE address (64 byte block 34:6) 155 * 1 Reserved 156 * 0 HiLoCS 157 */ 158 #define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM 1st uncorrectable scrub mem */ 159 /* error address register (32b) */ 160 /* 161 * 31 Reserved 162 * 30:2 CE address (64 byte block 34:6 163 * 1 Reserved 164 * 0 HiLoCS 165 */ 166 #define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */ 167 /* error syndrome register (16b) */ 168 #define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */ 169 /* error syndrome register (16b) */ 170 #define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */ 171 172 /* 3100 IMCH specific register addresses - device 0 function 1 */ 173 #define I3100_NSI_FERR 0x48 /* NSI first error reg (32b) */ 174 #define I3100_NSI_NERR 0x4C /* NSI next error reg (32b) */ 175 #define I3100_NSI_SMICMD 0x54 /* NSI SMI command register (32b) */ 176 #define I3100_NSI_EMASK 0x90 /* NSI error mask register (32b) */ 177 178 /* ICH5R register addresses - device 30 function 0 */ 179 #define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */ 180 #define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */ 181 #define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */ 182 183 enum e752x_chips { 184 E7520 = 0, 185 E7525 = 1, 186 E7320 = 2, 187 I3100 = 3 188 }; 189 190 struct e752x_pvt { 191 struct pci_dev *bridge_ck; 192 struct pci_dev *dev_d0f0; 193 struct pci_dev *dev_d0f1; 194 u32 tolm; 195 u32 remapbase; 196 u32 remaplimit; 197 int mc_symmetric; 198 u8 map[8]; 199 int map_type; 200 const struct e752x_dev_info *dev_info; 201 }; 202 203 struct e752x_dev_info { 204 u16 err_dev; 205 u16 ctl_dev; 206 const char *ctl_name; 207 }; 208 209 struct e752x_error_info { 210 u32 ferr_global; 211 u32 nerr_global; 212 u32 nsi_ferr; /* 3100 only */ 213 u32 nsi_nerr; /* 3100 only */ 214 u8 hi_ferr; /* all but 3100 */ 215 u8 hi_nerr; /* all but 3100 */ 216 u16 sysbus_ferr; 217 u16 sysbus_nerr; 218 u8 buf_ferr; 219 u8 buf_nerr; 220 u16 dram_ferr; 221 u16 dram_nerr; 222 u32 dram_sec1_add; 223 u32 dram_sec2_add; 224 u16 dram_sec1_syndrome; 225 u16 dram_sec2_syndrome; 226 u32 dram_ded_add; 227 u32 dram_scrb_add; 228 u32 dram_retr_add; 229 }; 230 231 static const struct e752x_dev_info e752x_devs[] = { 232 [E7520] = { 233 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR, 234 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0, 235 .ctl_name = "E7520"}, 236 [E7525] = { 237 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR, 238 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0, 239 .ctl_name = "E7525"}, 240 [E7320] = { 241 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR, 242 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0, 243 .ctl_name = "E7320"}, 244 [I3100] = { 245 .err_dev = PCI_DEVICE_ID_INTEL_3100_1_ERR, 246 .ctl_dev = PCI_DEVICE_ID_INTEL_3100_0, 247 .ctl_name = "3100"}, 248 }; 249 250 /* Valid scrub rates for the e752x/3100 hardware memory scrubber. We 251 * map the scrubbing bandwidth to a hardware register value. The 'set' 252 * operation finds the 'matching or higher value'. Note that scrubbing 253 * on the e752x can only be enabled/disabled. The 3100 supports 254 * a normal and fast mode. 255 */ 256 257 #define SDRATE_EOT 0xFFFFFFFF 258 259 struct scrubrate { 260 u32 bandwidth; /* bandwidth consumed by scrubbing in bytes/sec */ 261 u16 scrubval; /* register value for scrub rate */ 262 }; 263 264 /* Rate below assumes same performance as i3100 using PC3200 DDR2 in 265 * normal mode. e752x bridges don't support choosing normal or fast mode, 266 * so the scrubbing bandwidth value isn't all that important - scrubbing is 267 * either on or off. 268 */ 269 static const struct scrubrate scrubrates_e752x[] = { 270 {0, 0x00}, /* Scrubbing Off */ 271 {500000, 0x02}, /* Scrubbing On */ 272 {SDRATE_EOT, 0x00} /* End of Table */ 273 }; 274 275 /* Fast mode: 2 GByte PC3200 DDR2 scrubbed in 33s = 63161283 bytes/s 276 * Normal mode: 125 (32000 / 256) times slower than fast mode. 277 */ 278 static const struct scrubrate scrubrates_i3100[] = { 279 {0, 0x00}, /* Scrubbing Off */ 280 {500000, 0x0a}, /* Normal mode - 32k clocks */ 281 {62500000, 0x06}, /* Fast mode - 256 clocks */ 282 {SDRATE_EOT, 0x00} /* End of Table */ 283 }; 284 285 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci, 286 unsigned long page) 287 { 288 u32 remap; 289 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; 290 291 debugf3("%s()\n", __func__); 292 293 if (page < pvt->tolm) 294 return page; 295 296 if ((page >= 0x100000) && (page < pvt->remapbase)) 297 return page; 298 299 remap = (page - pvt->tolm) + pvt->remapbase; 300 301 if (remap < pvt->remaplimit) 302 return remap; 303 304 e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page); 305 return pvt->tolm - 1; 306 } 307 308 static void do_process_ce(struct mem_ctl_info *mci, u16 error_one, 309 u32 sec1_add, u16 sec1_syndrome) 310 { 311 u32 page; 312 int row; 313 int channel; 314 int i; 315 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; 316 317 debugf3("%s()\n", __func__); 318 319 /* convert the addr to 4k page */ 320 page = sec1_add >> (PAGE_SHIFT - 4); 321 322 /* FIXME - check for -1 */ 323 if (pvt->mc_symmetric) { 324 /* chip select are bits 14 & 13 */ 325 row = ((page >> 1) & 3); 326 e752x_printk(KERN_WARNING, 327 "Test row %d Table %d %d %d %d %d %d %d %d\n", row, 328 pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3], 329 pvt->map[4], pvt->map[5], pvt->map[6], 330 pvt->map[7]); 331 332 /* test for channel remapping */ 333 for (i = 0; i < 8; i++) { 334 if (pvt->map[i] == row) 335 break; 336 } 337 338 e752x_printk(KERN_WARNING, "Test computed row %d\n", i); 339 340 if (i < 8) 341 row = i; 342 else 343 e752x_mc_printk(mci, KERN_WARNING, 344 "row %d not found in remap table\n", 345 row); 346 } else 347 row = edac_mc_find_csrow_by_page(mci, page); 348 349 /* 0 = channel A, 1 = channel B */ 350 channel = !(error_one & 1); 351 352 /* e752x mc reads 34:6 of the DRAM linear address */ 353 edac_mc_handle_ce(mci, page, offset_in_page(sec1_add << 4), 354 sec1_syndrome, row, channel, "e752x CE"); 355 } 356 357 static inline void process_ce(struct mem_ctl_info *mci, u16 error_one, 358 u32 sec1_add, u16 sec1_syndrome, int *error_found, 359 int handle_error) 360 { 361 *error_found = 1; 362 363 if (handle_error) 364 do_process_ce(mci, error_one, sec1_add, sec1_syndrome); 365 } 366 367 static void do_process_ue(struct mem_ctl_info *mci, u16 error_one, 368 u32 ded_add, u32 scrb_add) 369 { 370 u32 error_2b, block_page; 371 int row; 372 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; 373 374 debugf3("%s()\n", __func__); 375 376 if (error_one & 0x0202) { 377 error_2b = ded_add; 378 379 /* convert to 4k address */ 380 block_page = error_2b >> (PAGE_SHIFT - 4); 381 382 row = pvt->mc_symmetric ? 383 /* chip select are bits 14 & 13 */ 384 ((block_page >> 1) & 3) : 385 edac_mc_find_csrow_by_page(mci, block_page); 386 387 /* e752x mc reads 34:6 of the DRAM linear address */ 388 edac_mc_handle_ue(mci, block_page, 389 offset_in_page(error_2b << 4), 390 row, "e752x UE from Read"); 391 } 392 if (error_one & 0x0404) { 393 error_2b = scrb_add; 394 395 /* convert to 4k address */ 396 block_page = error_2b >> (PAGE_SHIFT - 4); 397 398 row = pvt->mc_symmetric ? 399 /* chip select are bits 14 & 13 */ 400 ((block_page >> 1) & 3) : 401 edac_mc_find_csrow_by_page(mci, block_page); 402 403 /* e752x mc reads 34:6 of the DRAM linear address */ 404 edac_mc_handle_ue(mci, block_page, 405 offset_in_page(error_2b << 4), 406 row, "e752x UE from Scruber"); 407 } 408 } 409 410 static inline void process_ue(struct mem_ctl_info *mci, u16 error_one, 411 u32 ded_add, u32 scrb_add, int *error_found, 412 int handle_error) 413 { 414 *error_found = 1; 415 416 if (handle_error) 417 do_process_ue(mci, error_one, ded_add, scrb_add); 418 } 419 420 static inline void process_ue_no_info_wr(struct mem_ctl_info *mci, 421 int *error_found, int handle_error) 422 { 423 *error_found = 1; 424 425 if (!handle_error) 426 return; 427 428 debugf3("%s()\n", __func__); 429 edac_mc_handle_ue_no_info(mci, "e752x UE log memory write"); 430 } 431 432 static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error, 433 u32 retry_add) 434 { 435 u32 error_1b, page; 436 int row; 437 struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info; 438 439 error_1b = retry_add; 440 page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */ 441 442 /* chip select are bits 14 & 13 */ 443 row = pvt->mc_symmetric ? ((page >> 1) & 3) : 444 edac_mc_find_csrow_by_page(mci, page); 445 446 e752x_mc_printk(mci, KERN_WARNING, 447 "CE page 0x%lx, row %d : Memory read retry\n", 448 (long unsigned int)page, row); 449 } 450 451 static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error, 452 u32 retry_add, int *error_found, 453 int handle_error) 454 { 455 *error_found = 1; 456 457 if (handle_error) 458 do_process_ded_retry(mci, error, retry_add); 459 } 460 461 static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error, 462 int *error_found, int handle_error) 463 { 464 *error_found = 1; 465 466 if (handle_error) 467 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n"); 468 } 469 470 static char *global_message[11] = { 471 "PCI Express C1", 472 "PCI Express C", 473 "PCI Express B1", 474 "PCI Express B", 475 "PCI Express A1", 476 "PCI Express A", 477 "DMA Controller", 478 "HUB or NS Interface", 479 "System Bus", 480 "DRAM Controller", /* 9th entry */ 481 "Internal Buffer" 482 }; 483 484 #define DRAM_ENTRY 9 485 486 static char *fatal_message[2] = { "Non-Fatal ", "Fatal " }; 487 488 static void do_global_error(int fatal, u32 errors) 489 { 490 int i; 491 492 for (i = 0; i < 11; i++) { 493 if (errors & (1 << i)) { 494 /* If the error is from DRAM Controller OR 495 * we are to report ALL errors, then 496 * report the error 497 */ 498 if ((i == DRAM_ENTRY) || report_non_memory_errors) 499 e752x_printk(KERN_WARNING, "%sError %s\n", 500 fatal_message[fatal], 501 global_message[i]); 502 } 503 } 504 } 505 506 static inline void global_error(int fatal, u32 errors, int *error_found, 507 int handle_error) 508 { 509 *error_found = 1; 510 511 if (handle_error) 512 do_global_error(fatal, errors); 513 } 514 515 static char *hub_message[7] = { 516 "HI Address or Command Parity", "HI Illegal Access", 517 "HI Internal Parity", "Out of Range Access", 518 "HI Data Parity", "Enhanced Config Access", 519 "Hub Interface Target Abort" 520 }; 521 522 static void do_hub_error(int fatal, u8 errors) 523 { 524 int i; 525 526 for (i = 0; i < 7; i++) { 527 if (errors & (1 << i)) 528 e752x_printk(KERN_WARNING, "%sError %s\n", 529 fatal_message[fatal], hub_message[i]); 530 } 531 } 532 533 static inline void hub_error(int fatal, u8 errors, int *error_found, 534 int handle_error) 535 { 536 *error_found = 1; 537 538 if (handle_error) 539 do_hub_error(fatal, errors); 540 } 541 542 #define NSI_FATAL_MASK 0x0c080081 543 #define NSI_NON_FATAL_MASK 0x23a0ba64 544 #define NSI_ERR_MASK (NSI_FATAL_MASK | NSI_NON_FATAL_MASK) 545 546 static char *nsi_message[30] = { 547 "NSI Link Down", /* NSI_FERR/NSI_NERR bit 0, fatal error */ 548 "", /* reserved */ 549 "NSI Parity Error", /* bit 2, non-fatal */ 550 "", /* reserved */ 551 "", /* reserved */ 552 "Correctable Error Message", /* bit 5, non-fatal */ 553 "Non-Fatal Error Message", /* bit 6, non-fatal */ 554 "Fatal Error Message", /* bit 7, fatal */ 555 "", /* reserved */ 556 "Receiver Error", /* bit 9, non-fatal */ 557 "", /* reserved */ 558 "Bad TLP", /* bit 11, non-fatal */ 559 "Bad DLLP", /* bit 12, non-fatal */ 560 "REPLAY_NUM Rollover", /* bit 13, non-fatal */ 561 "", /* reserved */ 562 "Replay Timer Timeout", /* bit 15, non-fatal */ 563 "", /* reserved */ 564 "", /* reserved */ 565 "", /* reserved */ 566 "Data Link Protocol Error", /* bit 19, fatal */ 567 "", /* reserved */ 568 "Poisoned TLP", /* bit 21, non-fatal */ 569 "", /* reserved */ 570 "Completion Timeout", /* bit 23, non-fatal */ 571 "Completer Abort", /* bit 24, non-fatal */ 572 "Unexpected Completion", /* bit 25, non-fatal */ 573 "Receiver Overflow", /* bit 26, fatal */ 574 "Malformed TLP", /* bit 27, fatal */ 575 "", /* reserved */ 576 "Unsupported Request" /* bit 29, non-fatal */ 577 }; 578 579 static void do_nsi_error(int fatal, u32 errors) 580 { 581 int i; 582 583 for (i = 0; i < 30; i++) { 584 if (errors & (1 << i)) 585 printk(KERN_WARNING "%sError %s\n", 586 fatal_message[fatal], nsi_message[i]); 587 } 588 } 589 590 static inline void nsi_error(int fatal, u32 errors, int *error_found, 591 int handle_error) 592 { 593 *error_found = 1; 594 595 if (handle_error) 596 do_nsi_error(fatal, errors); 597 } 598 599 static char *membuf_message[4] = { 600 "Internal PMWB to DRAM parity", 601 "Internal PMWB to System Bus Parity", 602 "Internal System Bus or IO to PMWB Parity", 603 "Internal DRAM to PMWB Parity" 604 }; 605 606 static void do_membuf_error(u8 errors) 607 { 608 int i; 609 610 for (i = 0; i < 4; i++) { 611 if (errors & (1 << i)) 612 e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n", 613 membuf_message[i]); 614 } 615 } 616 617 static inline void membuf_error(u8 errors, int *error_found, int handle_error) 618 { 619 *error_found = 1; 620 621 if (handle_error) 622 do_membuf_error(errors); 623 } 624 625 static char *sysbus_message[10] = { 626 "Addr or Request Parity", 627 "Data Strobe Glitch", 628 "Addr Strobe Glitch", 629 "Data Parity", 630 "Addr Above TOM", 631 "Non DRAM Lock Error", 632 "MCERR", "BINIT", 633 "Memory Parity", 634 "IO Subsystem Parity" 635 }; 636 637 static void do_sysbus_error(int fatal, u32 errors) 638 { 639 int i; 640 641 for (i = 0; i < 10; i++) { 642 if (errors & (1 << i)) 643 e752x_printk(KERN_WARNING, "%sError System Bus %s\n", 644 fatal_message[fatal], sysbus_message[i]); 645 } 646 } 647 648 static inline void sysbus_error(int fatal, u32 errors, int *error_found, 649 int handle_error) 650 { 651 *error_found = 1; 652 653 if (handle_error) 654 do_sysbus_error(fatal, errors); 655 } 656 657 static void e752x_check_hub_interface(struct e752x_error_info *info, 658 int *error_found, int handle_error) 659 { 660 u8 stat8; 661 662 //pci_read_config_byte(dev,E752X_HI_FERR,&stat8); 663 664 stat8 = info->hi_ferr; 665 666 if (stat8 & 0x7f) { /* Error, so process */ 667 stat8 &= 0x7f; 668 669 if (stat8 & 0x2b) 670 hub_error(1, stat8 & 0x2b, error_found, handle_error); 671 672 if (stat8 & 0x54) 673 hub_error(0, stat8 & 0x54, error_found, handle_error); 674 } 675 //pci_read_config_byte(dev,E752X_HI_NERR,&stat8); 676 677 stat8 = info->hi_nerr; 678 679 if (stat8 & 0x7f) { /* Error, so process */ 680 stat8 &= 0x7f; 681 682 if (stat8 & 0x2b) 683 hub_error(1, stat8 & 0x2b, error_found, handle_error); 684 685 if (stat8 & 0x54) 686 hub_error(0, stat8 & 0x54, error_found, handle_error); 687 } 688 } 689 690 static void e752x_check_ns_interface(struct e752x_error_info *info, 691 int *error_found, int handle_error) 692 { 693 u32 stat32; 694 695 stat32 = info->nsi_ferr; 696 if (stat32 & NSI_ERR_MASK) { /* Error, so process */ 697 if (stat32 & NSI_FATAL_MASK) /* check for fatal errors */ 698 nsi_error(1, stat32 & NSI_FATAL_MASK, error_found, 699 handle_error); 700 if (stat32 & NSI_NON_FATAL_MASK) /* check for non-fatal ones */ 701 nsi_error(0, stat32 & NSI_NON_FATAL_MASK, error_found, 702 handle_error); 703 } 704 stat32 = info->nsi_nerr; 705 if (stat32 & NSI_ERR_MASK) { 706 if (stat32 & NSI_FATAL_MASK) 707 nsi_error(1, stat32 & NSI_FATAL_MASK, error_found, 708 handle_error); 709 if (stat32 & NSI_NON_FATAL_MASK) 710 nsi_error(0, stat32 & NSI_NON_FATAL_MASK, error_found, 711 handle_error); 712 } 713 } 714 715 static void e752x_check_sysbus(struct e752x_error_info *info, 716 int *error_found, int handle_error) 717 { 718 u32 stat32, error32; 719 720 //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32); 721 stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16); 722 723 if (stat32 == 0) 724 return; /* no errors */ 725 726 error32 = (stat32 >> 16) & 0x3ff; 727 stat32 = stat32 & 0x3ff; 728 729 if (stat32 & 0x087) 730 sysbus_error(1, stat32 & 0x087, error_found, handle_error); 731 732 if (stat32 & 0x378) 733 sysbus_error(0, stat32 & 0x378, error_found, handle_error); 734 735 if (error32 & 0x087) 736 sysbus_error(1, error32 & 0x087, error_found, handle_error); 737 738 if (error32 & 0x378) 739 sysbus_error(0, error32 & 0x378, error_found, handle_error); 740 } 741 742 static void e752x_check_membuf(struct e752x_error_info *info, 743 int *error_found, int handle_error) 744 { 745 u8 stat8; 746 747 stat8 = info->buf_ferr; 748 749 if (stat8 & 0x0f) { /* Error, so process */ 750 stat8 &= 0x0f; 751 membuf_error(stat8, error_found, handle_error); 752 } 753 754 stat8 = info->buf_nerr; 755 756 if (stat8 & 0x0f) { /* Error, so process */ 757 stat8 &= 0x0f; 758 membuf_error(stat8, error_found, handle_error); 759 } 760 } 761 762 static void e752x_check_dram(struct mem_ctl_info *mci, 763 struct e752x_error_info *info, int *error_found, 764 int handle_error) 765 { 766 u16 error_one, error_next; 767 768 error_one = info->dram_ferr; 769 error_next = info->dram_nerr; 770 771 /* decode and report errors */ 772 if (error_one & 0x0101) /* check first error correctable */ 773 process_ce(mci, error_one, info->dram_sec1_add, 774 info->dram_sec1_syndrome, error_found, handle_error); 775 776 if (error_next & 0x0101) /* check next error correctable */ 777 process_ce(mci, error_next, info->dram_sec2_add, 778 info->dram_sec2_syndrome, error_found, handle_error); 779 780 if (error_one & 0x4040) 781 process_ue_no_info_wr(mci, error_found, handle_error); 782 783 if (error_next & 0x4040) 784 process_ue_no_info_wr(mci, error_found, handle_error); 785 786 if (error_one & 0x2020) 787 process_ded_retry(mci, error_one, info->dram_retr_add, 788 error_found, handle_error); 789 790 if (error_next & 0x2020) 791 process_ded_retry(mci, error_next, info->dram_retr_add, 792 error_found, handle_error); 793 794 if (error_one & 0x0808) 795 process_threshold_ce(mci, error_one, error_found, handle_error); 796 797 if (error_next & 0x0808) 798 process_threshold_ce(mci, error_next, error_found, 799 handle_error); 800 801 if (error_one & 0x0606) 802 process_ue(mci, error_one, info->dram_ded_add, 803 info->dram_scrb_add, error_found, handle_error); 804 805 if (error_next & 0x0606) 806 process_ue(mci, error_next, info->dram_ded_add, 807 info->dram_scrb_add, error_found, handle_error); 808 } 809 810 static void e752x_get_error_info(struct mem_ctl_info *mci, 811 struct e752x_error_info *info) 812 { 813 struct pci_dev *dev; 814 struct e752x_pvt *pvt; 815 816 memset(info, 0, sizeof(*info)); 817 pvt = (struct e752x_pvt *)mci->pvt_info; 818 dev = pvt->dev_d0f1; 819 pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global); 820 821 if (info->ferr_global) { 822 if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) { 823 pci_read_config_dword(dev, I3100_NSI_FERR, 824 &info->nsi_ferr); 825 info->hi_ferr = 0; 826 } else { 827 pci_read_config_byte(dev, E752X_HI_FERR, 828 &info->hi_ferr); 829 info->nsi_ferr = 0; 830 } 831 pci_read_config_word(dev, E752X_SYSBUS_FERR, 832 &info->sysbus_ferr); 833 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr); 834 pci_read_config_word(dev, E752X_DRAM_FERR, &info->dram_ferr); 835 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD, 836 &info->dram_sec1_add); 837 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME, 838 &info->dram_sec1_syndrome); 839 pci_read_config_dword(dev, E752X_DRAM_DED_ADD, 840 &info->dram_ded_add); 841 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD, 842 &info->dram_scrb_add); 843 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD, 844 &info->dram_retr_add); 845 846 /* ignore the reserved bits just in case */ 847 if (info->hi_ferr & 0x7f) 848 pci_write_config_byte(dev, E752X_HI_FERR, 849 info->hi_ferr); 850 851 if (info->nsi_ferr & NSI_ERR_MASK) 852 pci_write_config_dword(dev, I3100_NSI_FERR, 853 info->nsi_ferr); 854 855 if (info->sysbus_ferr) 856 pci_write_config_word(dev, E752X_SYSBUS_FERR, 857 info->sysbus_ferr); 858 859 if (info->buf_ferr & 0x0f) 860 pci_write_config_byte(dev, E752X_BUF_FERR, 861 info->buf_ferr); 862 863 if (info->dram_ferr) 864 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR, 865 info->dram_ferr, info->dram_ferr); 866 867 pci_write_config_dword(dev, E752X_FERR_GLOBAL, 868 info->ferr_global); 869 } 870 871 pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global); 872 873 if (info->nerr_global) { 874 if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) { 875 pci_read_config_dword(dev, I3100_NSI_NERR, 876 &info->nsi_nerr); 877 info->hi_nerr = 0; 878 } else { 879 pci_read_config_byte(dev, E752X_HI_NERR, 880 &info->hi_nerr); 881 info->nsi_nerr = 0; 882 } 883 pci_read_config_word(dev, E752X_SYSBUS_NERR, 884 &info->sysbus_nerr); 885 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr); 886 pci_read_config_word(dev, E752X_DRAM_NERR, &info->dram_nerr); 887 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD, 888 &info->dram_sec2_add); 889 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME, 890 &info->dram_sec2_syndrome); 891 892 if (info->hi_nerr & 0x7f) 893 pci_write_config_byte(dev, E752X_HI_NERR, 894 info->hi_nerr); 895 896 if (info->nsi_nerr & NSI_ERR_MASK) 897 pci_write_config_dword(dev, I3100_NSI_NERR, 898 info->nsi_nerr); 899 900 if (info->sysbus_nerr) 901 pci_write_config_word(dev, E752X_SYSBUS_NERR, 902 info->sysbus_nerr); 903 904 if (info->buf_nerr & 0x0f) 905 pci_write_config_byte(dev, E752X_BUF_NERR, 906 info->buf_nerr); 907 908 if (info->dram_nerr) 909 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR, 910 info->dram_nerr, info->dram_nerr); 911 912 pci_write_config_dword(dev, E752X_NERR_GLOBAL, 913 info->nerr_global); 914 } 915 } 916 917 static int e752x_process_error_info(struct mem_ctl_info *mci, 918 struct e752x_error_info *info, 919 int handle_errors) 920 { 921 u32 error32, stat32; 922 int error_found; 923 924 error_found = 0; 925 error32 = (info->ferr_global >> 18) & 0x3ff; 926 stat32 = (info->ferr_global >> 4) & 0x7ff; 927 928 if (error32) 929 global_error(1, error32, &error_found, handle_errors); 930 931 if (stat32) 932 global_error(0, stat32, &error_found, handle_errors); 933 934 error32 = (info->nerr_global >> 18) & 0x3ff; 935 stat32 = (info->nerr_global >> 4) & 0x7ff; 936 937 if (error32) 938 global_error(1, error32, &error_found, handle_errors); 939 940 if (stat32) 941 global_error(0, stat32, &error_found, handle_errors); 942 943 e752x_check_hub_interface(info, &error_found, handle_errors); 944 e752x_check_ns_interface(info, &error_found, handle_errors); 945 e752x_check_sysbus(info, &error_found, handle_errors); 946 e752x_check_membuf(info, &error_found, handle_errors); 947 e752x_check_dram(mci, info, &error_found, handle_errors); 948 return error_found; 949 } 950 951 static void e752x_check(struct mem_ctl_info *mci) 952 { 953 struct e752x_error_info info; 954 955 debugf3("%s()\n", __func__); 956 e752x_get_error_info(mci, &info); 957 e752x_process_error_info(mci, &info, 1); 958 } 959 960 /* Program byte/sec bandwidth scrub rate to hardware */ 961 static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 *new_bw) 962 { 963 const struct scrubrate *scrubrates; 964 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info; 965 struct pci_dev *pdev = pvt->dev_d0f0; 966 int i; 967 968 if (pvt->dev_info->ctl_dev == PCI_DEVICE_ID_INTEL_3100_0) 969 scrubrates = scrubrates_i3100; 970 else 971 scrubrates = scrubrates_e752x; 972 973 /* Translate the desired scrub rate to a e752x/3100 register value. 974 * Search for the bandwidth that is equal or greater than the 975 * desired rate and program the cooresponding register value. 976 */ 977 for (i = 0; scrubrates[i].bandwidth != SDRATE_EOT; i++) 978 if (scrubrates[i].bandwidth >= *new_bw) 979 break; 980 981 if (scrubrates[i].bandwidth == SDRATE_EOT) 982 return -1; 983 984 pci_write_config_word(pdev, E752X_MCHSCRB, scrubrates[i].scrubval); 985 986 return 0; 987 } 988 989 /* Convert current scrub rate value into byte/sec bandwidth */ 990 static int get_sdram_scrub_rate(struct mem_ctl_info *mci, u32 *bw) 991 { 992 const struct scrubrate *scrubrates; 993 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info; 994 struct pci_dev *pdev = pvt->dev_d0f0; 995 u16 scrubval; 996 int i; 997 998 if (pvt->dev_info->ctl_dev == PCI_DEVICE_ID_INTEL_3100_0) 999 scrubrates = scrubrates_i3100; 1000 else 1001 scrubrates = scrubrates_e752x; 1002 1003 /* Find the bandwidth matching the memory scrubber configuration */ 1004 pci_read_config_word(pdev, E752X_MCHSCRB, &scrubval); 1005 scrubval = scrubval & 0x0f; 1006 1007 for (i = 0; scrubrates[i].bandwidth != SDRATE_EOT; i++) 1008 if (scrubrates[i].scrubval == scrubval) 1009 break; 1010 1011 if (scrubrates[i].bandwidth == SDRATE_EOT) { 1012 e752x_printk(KERN_WARNING, 1013 "Invalid sdram scrub control value: 0x%x\n", scrubval); 1014 return -1; 1015 } 1016 1017 *bw = scrubrates[i].bandwidth; 1018 1019 return 0; 1020 } 1021 1022 /* Return 1 if dual channel mode is active. Else return 0. */ 1023 static inline int dual_channel_active(u16 ddrcsr) 1024 { 1025 return (((ddrcsr >> 12) & 3) == 3); 1026 } 1027 1028 /* Remap csrow index numbers if map_type is "reverse" 1029 */ 1030 static inline int remap_csrow_index(struct mem_ctl_info *mci, int index) 1031 { 1032 struct e752x_pvt *pvt = mci->pvt_info; 1033 1034 if (!pvt->map_type) 1035 return (7 - index); 1036 1037 return (index); 1038 } 1039 1040 static void e752x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, 1041 u16 ddrcsr) 1042 { 1043 struct csrow_info *csrow; 1044 unsigned long last_cumul_size; 1045 int index, mem_dev, drc_chan; 1046 int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */ 1047 int drc_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */ 1048 u8 value; 1049 u32 dra, drc, cumul_size; 1050 1051 dra = 0; 1052 for (index = 0; index < 4; index++) { 1053 u8 dra_reg; 1054 pci_read_config_byte(pdev, E752X_DRA + index, &dra_reg); 1055 dra |= dra_reg << (index * 8); 1056 } 1057 pci_read_config_dword(pdev, E752X_DRC, &drc); 1058 drc_chan = dual_channel_active(ddrcsr); 1059 drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */ 1060 drc_ddim = (drc >> 20) & 0x3; 1061 1062 /* The dram row boundary (DRB) reg values are boundary address for 1063 * each DRAM row with a granularity of 64 or 128MB (single/dual 1064 * channel operation). DRB regs are cumulative; therefore DRB7 will 1065 * contain the total memory contained in all eight rows. 1066 */ 1067 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) { 1068 /* mem_dev 0=x8, 1=x4 */ 1069 mem_dev = (dra >> (index * 4 + 2)) & 0x3; 1070 csrow = &mci->csrows[remap_csrow_index(mci, index)]; 1071 1072 mem_dev = (mem_dev == 2); 1073 pci_read_config_byte(pdev, E752X_DRB + index, &value); 1074 /* convert a 128 or 64 MiB DRB to a page size. */ 1075 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT); 1076 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index, 1077 cumul_size); 1078 if (cumul_size == last_cumul_size) 1079 continue; /* not populated */ 1080 1081 csrow->first_page = last_cumul_size; 1082 csrow->last_page = cumul_size - 1; 1083 csrow->nr_pages = cumul_size - last_cumul_size; 1084 last_cumul_size = cumul_size; 1085 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */ 1086 csrow->mtype = MEM_RDDR; /* only one type supported */ 1087 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8; 1088 1089 /* 1090 * if single channel or x8 devices then SECDED 1091 * if dual channel and x4 then S4ECD4ED 1092 */ 1093 if (drc_ddim) { 1094 if (drc_chan && mem_dev) { 1095 csrow->edac_mode = EDAC_S4ECD4ED; 1096 mci->edac_cap |= EDAC_FLAG_S4ECD4ED; 1097 } else { 1098 csrow->edac_mode = EDAC_SECDED; 1099 mci->edac_cap |= EDAC_FLAG_SECDED; 1100 } 1101 } else 1102 csrow->edac_mode = EDAC_NONE; 1103 } 1104 } 1105 1106 static void e752x_init_mem_map_table(struct pci_dev *pdev, 1107 struct e752x_pvt *pvt) 1108 { 1109 int index; 1110 u8 value, last, row; 1111 1112 last = 0; 1113 row = 0; 1114 1115 for (index = 0; index < 8; index += 2) { 1116 pci_read_config_byte(pdev, E752X_DRB + index, &value); 1117 /* test if there is a dimm in this slot */ 1118 if (value == last) { 1119 /* no dimm in the slot, so flag it as empty */ 1120 pvt->map[index] = 0xff; 1121 pvt->map[index + 1] = 0xff; 1122 } else { /* there is a dimm in the slot */ 1123 pvt->map[index] = row; 1124 row++; 1125 last = value; 1126 /* test the next value to see if the dimm is double 1127 * sided 1128 */ 1129 pci_read_config_byte(pdev, E752X_DRB + index + 1, 1130 &value); 1131 1132 /* the dimm is single sided, so flag as empty */ 1133 /* this is a double sided dimm to save the next row #*/ 1134 pvt->map[index + 1] = (value == last) ? 0xff : row; 1135 row++; 1136 last = value; 1137 } 1138 } 1139 } 1140 1141 /* Return 0 on success or 1 on failure. */ 1142 static int e752x_get_devs(struct pci_dev *pdev, int dev_idx, 1143 struct e752x_pvt *pvt) 1144 { 1145 struct pci_dev *dev; 1146 1147 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL, 1148 pvt->dev_info->err_dev, pvt->bridge_ck); 1149 1150 if (pvt->bridge_ck == NULL) 1151 pvt->bridge_ck = pci_scan_single_device(pdev->bus, 1152 PCI_DEVFN(0, 1)); 1153 1154 if (pvt->bridge_ck == NULL) { 1155 e752x_printk(KERN_ERR, "error reporting device not found:" 1156 "vendor %x device 0x%x (broken BIOS?)\n", 1157 PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev); 1158 return 1; 1159 } 1160 1161 dev = pci_get_device(PCI_VENDOR_ID_INTEL, 1162 e752x_devs[dev_idx].ctl_dev, 1163 NULL); 1164 1165 if (dev == NULL) 1166 goto fail; 1167 1168 pvt->dev_d0f0 = dev; 1169 pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck); 1170 1171 return 0; 1172 1173 fail: 1174 pci_dev_put(pvt->bridge_ck); 1175 return 1; 1176 } 1177 1178 /* Setup system bus parity mask register. 1179 * Sysbus parity supported on: 1180 * e7320/e7520/e7525 + Xeon 1181 */ 1182 static void e752x_init_sysbus_parity_mask(struct e752x_pvt *pvt) 1183 { 1184 char *cpu_id = cpu_data(0).x86_model_id; 1185 struct pci_dev *dev = pvt->dev_d0f1; 1186 int enable = 1; 1187 1188 /* Allow module parameter override, else see if CPU supports parity */ 1189 if (sysbus_parity != -1) { 1190 enable = sysbus_parity; 1191 } else if (cpu_id[0] && !strstr(cpu_id, "Xeon")) { 1192 e752x_printk(KERN_INFO, "System Bus Parity not " 1193 "supported by CPU, disabling\n"); 1194 enable = 0; 1195 } 1196 1197 if (enable) 1198 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x0000); 1199 else 1200 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x0309); 1201 } 1202 1203 static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt) 1204 { 1205 struct pci_dev *dev; 1206 1207 dev = pvt->dev_d0f1; 1208 /* Turn off error disable & SMI in case the BIOS turned it on */ 1209 if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) { 1210 pci_write_config_dword(dev, I3100_NSI_EMASK, 0); 1211 pci_write_config_dword(dev, I3100_NSI_SMICMD, 0); 1212 } else { 1213 pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00); 1214 pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00); 1215 } 1216 1217 e752x_init_sysbus_parity_mask(pvt); 1218 1219 pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00); 1220 pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00); 1221 pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00); 1222 pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00); 1223 pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00); 1224 } 1225 1226 static int e752x_probe1(struct pci_dev *pdev, int dev_idx) 1227 { 1228 u16 pci_data; 1229 u8 stat8; 1230 struct mem_ctl_info *mci; 1231 struct e752x_pvt *pvt; 1232 u16 ddrcsr; 1233 int drc_chan; /* Number of channels 0=1chan,1=2chan */ 1234 struct e752x_error_info discard; 1235 1236 debugf0("%s(): mci\n", __func__); 1237 debugf0("Starting Probe1\n"); 1238 1239 /* check to see if device 0 function 1 is enabled; if it isn't, we 1240 * assume the BIOS has reserved it for a reason and is expecting 1241 * exclusive access, we take care not to violate that assumption and 1242 * fail the probe. */ 1243 pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8); 1244 if (!force_function_unhide && !(stat8 & (1 << 5))) { 1245 printk(KERN_INFO "Contact your BIOS vendor to see if the " 1246 "E752x error registers can be safely un-hidden\n"); 1247 return -ENODEV; 1248 } 1249 stat8 |= (1 << 5); 1250 pci_write_config_byte(pdev, E752X_DEVPRES1, stat8); 1251 1252 pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr); 1253 /* FIXME: should check >>12 or 0xf, true for all? */ 1254 /* Dual channel = 1, Single channel = 0 */ 1255 drc_chan = dual_channel_active(ddrcsr); 1256 1257 mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1, 0); 1258 1259 if (mci == NULL) { 1260 return -ENOMEM; 1261 } 1262 1263 debugf3("%s(): init mci\n", __func__); 1264 mci->mtype_cap = MEM_FLAG_RDDR; 1265 /* 3100 IMCH supports SECDEC only */ 1266 mci->edac_ctl_cap = (dev_idx == I3100) ? EDAC_FLAG_SECDED : 1267 (EDAC_FLAG_NONE | EDAC_FLAG_SECDED | EDAC_FLAG_S4ECD4ED); 1268 /* FIXME - what if different memory types are in different csrows? */ 1269 mci->mod_name = EDAC_MOD_STR; 1270 mci->mod_ver = E752X_REVISION; 1271 mci->dev = &pdev->dev; 1272 1273 debugf3("%s(): init pvt\n", __func__); 1274 pvt = (struct e752x_pvt *)mci->pvt_info; 1275 pvt->dev_info = &e752x_devs[dev_idx]; 1276 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0); 1277 1278 if (e752x_get_devs(pdev, dev_idx, pvt)) { 1279 edac_mc_free(mci); 1280 return -ENODEV; 1281 } 1282 1283 debugf3("%s(): more mci init\n", __func__); 1284 mci->ctl_name = pvt->dev_info->ctl_name; 1285 mci->dev_name = pci_name(pdev); 1286 mci->edac_check = e752x_check; 1287 mci->ctl_page_to_phys = ctl_page_to_phys; 1288 mci->set_sdram_scrub_rate = set_sdram_scrub_rate; 1289 mci->get_sdram_scrub_rate = get_sdram_scrub_rate; 1290 1291 /* set the map type. 1 = normal, 0 = reversed 1292 * Must be set before e752x_init_csrows in case csrow mapping 1293 * is reversed. 1294 */ 1295 pci_read_config_byte(pdev, E752X_DRM, &stat8); 1296 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f)); 1297 1298 e752x_init_csrows(mci, pdev, ddrcsr); 1299 e752x_init_mem_map_table(pdev, pvt); 1300 1301 if (dev_idx == I3100) 1302 mci->edac_cap = EDAC_FLAG_SECDED; /* the only mode supported */ 1303 else 1304 mci->edac_cap |= EDAC_FLAG_NONE; 1305 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__); 1306 1307 /* load the top of low memory, remap base, and remap limit vars */ 1308 pci_read_config_word(pdev, E752X_TOLM, &pci_data); 1309 pvt->tolm = ((u32) pci_data) << 4; 1310 pci_read_config_word(pdev, E752X_REMAPBASE, &pci_data); 1311 pvt->remapbase = ((u32) pci_data) << 14; 1312 pci_read_config_word(pdev, E752X_REMAPLIMIT, &pci_data); 1313 pvt->remaplimit = ((u32) pci_data) << 14; 1314 e752x_printk(KERN_INFO, 1315 "tolm = %x, remapbase = %x, remaplimit = %x\n", 1316 pvt->tolm, pvt->remapbase, pvt->remaplimit); 1317 1318 /* Here we assume that we will never see multiple instances of this 1319 * type of memory controller. The ID is therefore hardcoded to 0. 1320 */ 1321 if (edac_mc_add_mc(mci)) { 1322 debugf3("%s(): failed edac_mc_add_mc()\n", __func__); 1323 goto fail; 1324 } 1325 1326 e752x_init_error_reporting_regs(pvt); 1327 e752x_get_error_info(mci, &discard); /* clear other MCH errors */ 1328 1329 /* allocating generic PCI control info */ 1330 e752x_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); 1331 if (!e752x_pci) { 1332 printk(KERN_WARNING 1333 "%s(): Unable to create PCI control\n", __func__); 1334 printk(KERN_WARNING 1335 "%s(): PCI error report via EDAC not setup\n", 1336 __func__); 1337 } 1338 1339 /* get this far and it's successful */ 1340 debugf3("%s(): success\n", __func__); 1341 return 0; 1342 1343 fail: 1344 pci_dev_put(pvt->dev_d0f0); 1345 pci_dev_put(pvt->dev_d0f1); 1346 pci_dev_put(pvt->bridge_ck); 1347 edac_mc_free(mci); 1348 1349 return -ENODEV; 1350 } 1351 1352 /* returns count (>= 0), or negative on error */ 1353 static int __devinit e752x_init_one(struct pci_dev *pdev, 1354 const struct pci_device_id *ent) 1355 { 1356 debugf0("%s()\n", __func__); 1357 1358 /* wake up and enable device */ 1359 if (pci_enable_device(pdev) < 0) 1360 return -EIO; 1361 1362 return e752x_probe1(pdev, ent->driver_data); 1363 } 1364 1365 static void __devexit e752x_remove_one(struct pci_dev *pdev) 1366 { 1367 struct mem_ctl_info *mci; 1368 struct e752x_pvt *pvt; 1369 1370 debugf0("%s()\n", __func__); 1371 1372 if (e752x_pci) 1373 edac_pci_release_generic_ctl(e752x_pci); 1374 1375 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) 1376 return; 1377 1378 pvt = (struct e752x_pvt *)mci->pvt_info; 1379 pci_dev_put(pvt->dev_d0f0); 1380 pci_dev_put(pvt->dev_d0f1); 1381 pci_dev_put(pvt->bridge_ck); 1382 edac_mc_free(mci); 1383 } 1384 1385 static const struct pci_device_id e752x_pci_tbl[] __devinitdata = { 1386 { 1387 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1388 E7520}, 1389 { 1390 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1391 E7525}, 1392 { 1393 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1394 E7320}, 1395 { 1396 PCI_VEND_DEV(INTEL, 3100_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1397 I3100}, 1398 { 1399 0, 1400 } /* 0 terminated list. */ 1401 }; 1402 1403 MODULE_DEVICE_TABLE(pci, e752x_pci_tbl); 1404 1405 static struct pci_driver e752x_driver = { 1406 .name = EDAC_MOD_STR, 1407 .probe = e752x_init_one, 1408 .remove = __devexit_p(e752x_remove_one), 1409 .id_table = e752x_pci_tbl, 1410 }; 1411 1412 static int __init e752x_init(void) 1413 { 1414 int pci_rc; 1415 1416 debugf3("%s()\n", __func__); 1417 1418 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 1419 opstate_init(); 1420 1421 pci_rc = pci_register_driver(&e752x_driver); 1422 return (pci_rc < 0) ? pci_rc : 0; 1423 } 1424 1425 static void __exit e752x_exit(void) 1426 { 1427 debugf3("%s()\n", __func__); 1428 pci_unregister_driver(&e752x_driver); 1429 } 1430 1431 module_init(e752x_init); 1432 module_exit(e752x_exit); 1433 1434 MODULE_LICENSE("GPL"); 1435 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n"); 1436 MODULE_DESCRIPTION("MC support for Intel e752x/3100 memory controllers"); 1437 1438 module_param(force_function_unhide, int, 0444); 1439 MODULE_PARM_DESC(force_function_unhide, "if BIOS sets Dev0:Fun1 up as hidden:" 1440 " 1=force unhide and hope BIOS doesn't fight driver for " 1441 "Dev0:Fun1 access"); 1442 1443 module_param(edac_op_state, int, 0444); 1444 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 1445 1446 module_param(sysbus_parity, int, 0444); 1447 MODULE_PARM_DESC(sysbus_parity, "0=disable system bus parity checking," 1448 " 1=enable system bus parity checking, default=auto-detect"); 1449 module_param(report_non_memory_errors, int, 0644); 1450 MODULE_PARM_DESC(report_non_memory_errors, "0=disable non-memory error " 1451 "reporting, 1=enable non-memory error reporting"); 1452