1 /* 2 * cpc925_edac.c, EDAC driver for IBM CPC925 Bridge and Memory Controller. 3 * 4 * Copyright (c) 2008 Wind River Systems, Inc. 5 * 6 * Authors: Cao Qingtao <qingtao.cao@windriver.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 15 * See the GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 22 #include <linux/module.h> 23 #include <linux/init.h> 24 #include <linux/io.h> 25 #include <linux/edac.h> 26 #include <linux/of.h> 27 #include <linux/platform_device.h> 28 #include <linux/gfp.h> 29 30 #include "edac_core.h" 31 #include "edac_module.h" 32 33 #define CPC925_EDAC_REVISION " Ver: 1.0.0 " __DATE__ 34 #define CPC925_EDAC_MOD_STR "cpc925_edac" 35 36 #define cpc925_printk(level, fmt, arg...) \ 37 edac_printk(level, "CPC925", fmt, ##arg) 38 39 #define cpc925_mc_printk(mci, level, fmt, arg...) \ 40 edac_mc_chipset_printk(mci, level, "CPC925", fmt, ##arg) 41 42 /* 43 * CPC925 registers are of 32 bits with bit0 defined at the 44 * most significant bit and bit31 at that of least significant. 45 */ 46 #define CPC925_BITS_PER_REG 32 47 #define CPC925_BIT(nr) (1UL << (CPC925_BITS_PER_REG - 1 - nr)) 48 49 /* 50 * EDAC device names for the error detections of 51 * CPU Interface and Hypertransport Link. 52 */ 53 #define CPC925_CPU_ERR_DEV "cpu" 54 #define CPC925_HT_LINK_DEV "htlink" 55 56 /* Suppose DDR Refresh cycle is 15.6 microsecond */ 57 #define CPC925_REF_FREQ 0xFA69 58 #define CPC925_SCRUB_BLOCK_SIZE 64 /* bytes */ 59 #define CPC925_NR_CSROWS 8 60 61 /* 62 * All registers and bits definitions are taken from 63 * "CPC925 Bridge and Memory Controller User Manual, SA14-2761-02". 64 */ 65 66 /* 67 * CPU and Memory Controller Registers 68 */ 69 /************************************************************ 70 * Processor Interface Exception Mask Register (APIMASK) 71 ************************************************************/ 72 #define REG_APIMASK_OFFSET 0x30070 73 enum apimask_bits { 74 APIMASK_DART = CPC925_BIT(0), /* DART Exception */ 75 APIMASK_ADI0 = CPC925_BIT(1), /* Handshake Error on PI0_ADI */ 76 APIMASK_ADI1 = CPC925_BIT(2), /* Handshake Error on PI1_ADI */ 77 APIMASK_STAT = CPC925_BIT(3), /* Status Exception */ 78 APIMASK_DERR = CPC925_BIT(4), /* Data Error Exception */ 79 APIMASK_ADRS0 = CPC925_BIT(5), /* Addressing Exception on PI0 */ 80 APIMASK_ADRS1 = CPC925_BIT(6), /* Addressing Exception on PI1 */ 81 /* BIT(7) Reserved */ 82 APIMASK_ECC_UE_H = CPC925_BIT(8), /* UECC upper */ 83 APIMASK_ECC_CE_H = CPC925_BIT(9), /* CECC upper */ 84 APIMASK_ECC_UE_L = CPC925_BIT(10), /* UECC lower */ 85 APIMASK_ECC_CE_L = CPC925_BIT(11), /* CECC lower */ 86 87 CPU_MASK_ENABLE = (APIMASK_DART | APIMASK_ADI0 | APIMASK_ADI1 | 88 APIMASK_STAT | APIMASK_DERR | APIMASK_ADRS0 | 89 APIMASK_ADRS1), 90 ECC_MASK_ENABLE = (APIMASK_ECC_UE_H | APIMASK_ECC_CE_H | 91 APIMASK_ECC_UE_L | APIMASK_ECC_CE_L), 92 }; 93 94 /************************************************************ 95 * Processor Interface Exception Register (APIEXCP) 96 ************************************************************/ 97 #define REG_APIEXCP_OFFSET 0x30060 98 enum apiexcp_bits { 99 APIEXCP_DART = CPC925_BIT(0), /* DART Exception */ 100 APIEXCP_ADI0 = CPC925_BIT(1), /* Handshake Error on PI0_ADI */ 101 APIEXCP_ADI1 = CPC925_BIT(2), /* Handshake Error on PI1_ADI */ 102 APIEXCP_STAT = CPC925_BIT(3), /* Status Exception */ 103 APIEXCP_DERR = CPC925_BIT(4), /* Data Error Exception */ 104 APIEXCP_ADRS0 = CPC925_BIT(5), /* Addressing Exception on PI0 */ 105 APIEXCP_ADRS1 = CPC925_BIT(6), /* Addressing Exception on PI1 */ 106 /* BIT(7) Reserved */ 107 APIEXCP_ECC_UE_H = CPC925_BIT(8), /* UECC upper */ 108 APIEXCP_ECC_CE_H = CPC925_BIT(9), /* CECC upper */ 109 APIEXCP_ECC_UE_L = CPC925_BIT(10), /* UECC lower */ 110 APIEXCP_ECC_CE_L = CPC925_BIT(11), /* CECC lower */ 111 112 CPU_EXCP_DETECTED = (APIEXCP_DART | APIEXCP_ADI0 | APIEXCP_ADI1 | 113 APIEXCP_STAT | APIEXCP_DERR | APIEXCP_ADRS0 | 114 APIEXCP_ADRS1), 115 UECC_EXCP_DETECTED = (APIEXCP_ECC_UE_H | APIEXCP_ECC_UE_L), 116 CECC_EXCP_DETECTED = (APIEXCP_ECC_CE_H | APIEXCP_ECC_CE_L), 117 ECC_EXCP_DETECTED = (UECC_EXCP_DETECTED | CECC_EXCP_DETECTED), 118 }; 119 120 /************************************************************ 121 * Memory Bus Configuration Register (MBCR) 122 ************************************************************/ 123 #define REG_MBCR_OFFSET 0x2190 124 #define MBCR_64BITCFG_SHIFT 23 125 #define MBCR_64BITCFG_MASK (1UL << MBCR_64BITCFG_SHIFT) 126 #define MBCR_64BITBUS_SHIFT 22 127 #define MBCR_64BITBUS_MASK (1UL << MBCR_64BITBUS_SHIFT) 128 129 /************************************************************ 130 * Memory Bank Mode Register (MBMR) 131 ************************************************************/ 132 #define REG_MBMR_OFFSET 0x21C0 133 #define MBMR_MODE_MAX_VALUE 0xF 134 #define MBMR_MODE_SHIFT 25 135 #define MBMR_MODE_MASK (MBMR_MODE_MAX_VALUE << MBMR_MODE_SHIFT) 136 #define MBMR_BBA_SHIFT 24 137 #define MBMR_BBA_MASK (1UL << MBMR_BBA_SHIFT) 138 139 /************************************************************ 140 * Memory Bank Boundary Address Register (MBBAR) 141 ************************************************************/ 142 #define REG_MBBAR_OFFSET 0x21D0 143 #define MBBAR_BBA_MAX_VALUE 0xFF 144 #define MBBAR_BBA_SHIFT 24 145 #define MBBAR_BBA_MASK (MBBAR_BBA_MAX_VALUE << MBBAR_BBA_SHIFT) 146 147 /************************************************************ 148 * Memory Scrub Control Register (MSCR) 149 ************************************************************/ 150 #define REG_MSCR_OFFSET 0x2400 151 #define MSCR_SCRUB_MOD_MASK 0xC0000000 /* scrub_mod - bit0:1*/ 152 #define MSCR_BACKGR_SCRUB 0x40000000 /* 01 */ 153 #define MSCR_SI_SHIFT 16 /* si - bit8:15*/ 154 #define MSCR_SI_MAX_VALUE 0xFF 155 #define MSCR_SI_MASK (MSCR_SI_MAX_VALUE << MSCR_SI_SHIFT) 156 157 /************************************************************ 158 * Memory Scrub Range Start Register (MSRSR) 159 ************************************************************/ 160 #define REG_MSRSR_OFFSET 0x2410 161 162 /************************************************************ 163 * Memory Scrub Range End Register (MSRER) 164 ************************************************************/ 165 #define REG_MSRER_OFFSET 0x2420 166 167 /************************************************************ 168 * Memory Scrub Pattern Register (MSPR) 169 ************************************************************/ 170 #define REG_MSPR_OFFSET 0x2430 171 172 /************************************************************ 173 * Memory Check Control Register (MCCR) 174 ************************************************************/ 175 #define REG_MCCR_OFFSET 0x2440 176 enum mccr_bits { 177 MCCR_ECC_EN = CPC925_BIT(0), /* ECC high and low check */ 178 }; 179 180 /************************************************************ 181 * Memory Check Range End Register (MCRER) 182 ************************************************************/ 183 #define REG_MCRER_OFFSET 0x2450 184 185 /************************************************************ 186 * Memory Error Address Register (MEAR) 187 ************************************************************/ 188 #define REG_MEAR_OFFSET 0x2460 189 #define MEAR_BCNT_MAX_VALUE 0x3 190 #define MEAR_BCNT_SHIFT 30 191 #define MEAR_BCNT_MASK (MEAR_BCNT_MAX_VALUE << MEAR_BCNT_SHIFT) 192 #define MEAR_RANK_MAX_VALUE 0x7 193 #define MEAR_RANK_SHIFT 27 194 #define MEAR_RANK_MASK (MEAR_RANK_MAX_VALUE << MEAR_RANK_SHIFT) 195 #define MEAR_COL_MAX_VALUE 0x7FF 196 #define MEAR_COL_SHIFT 16 197 #define MEAR_COL_MASK (MEAR_COL_MAX_VALUE << MEAR_COL_SHIFT) 198 #define MEAR_BANK_MAX_VALUE 0x3 199 #define MEAR_BANK_SHIFT 14 200 #define MEAR_BANK_MASK (MEAR_BANK_MAX_VALUE << MEAR_BANK_SHIFT) 201 #define MEAR_ROW_MASK 0x00003FFF 202 203 /************************************************************ 204 * Memory Error Syndrome Register (MESR) 205 ************************************************************/ 206 #define REG_MESR_OFFSET 0x2470 207 #define MESR_ECC_SYN_H_MASK 0xFF00 208 #define MESR_ECC_SYN_L_MASK 0x00FF 209 210 /************************************************************ 211 * Memory Mode Control Register (MMCR) 212 ************************************************************/ 213 #define REG_MMCR_OFFSET 0x2500 214 enum mmcr_bits { 215 MMCR_REG_DIMM_MODE = CPC925_BIT(3), 216 }; 217 218 /* 219 * HyperTransport Link Registers 220 */ 221 /************************************************************ 222 * Error Handling/Enumeration Scratch Pad Register (ERRCTRL) 223 ************************************************************/ 224 #define REG_ERRCTRL_OFFSET 0x70140 225 enum errctrl_bits { /* nonfatal interrupts for */ 226 ERRCTRL_SERR_NF = CPC925_BIT(0), /* system error */ 227 ERRCTRL_CRC_NF = CPC925_BIT(1), /* CRC error */ 228 ERRCTRL_RSP_NF = CPC925_BIT(2), /* Response error */ 229 ERRCTRL_EOC_NF = CPC925_BIT(3), /* End-Of-Chain error */ 230 ERRCTRL_OVF_NF = CPC925_BIT(4), /* Overflow error */ 231 ERRCTRL_PROT_NF = CPC925_BIT(5), /* Protocol error */ 232 233 ERRCTRL_RSP_ERR = CPC925_BIT(6), /* Response error received */ 234 ERRCTRL_CHN_FAL = CPC925_BIT(7), /* Sync flooding detected */ 235 236 HT_ERRCTRL_ENABLE = (ERRCTRL_SERR_NF | ERRCTRL_CRC_NF | 237 ERRCTRL_RSP_NF | ERRCTRL_EOC_NF | 238 ERRCTRL_OVF_NF | ERRCTRL_PROT_NF), 239 HT_ERRCTRL_DETECTED = (ERRCTRL_RSP_ERR | ERRCTRL_CHN_FAL), 240 }; 241 242 /************************************************************ 243 * Link Configuration and Link Control Register (LINKCTRL) 244 ************************************************************/ 245 #define REG_LINKCTRL_OFFSET 0x70110 246 enum linkctrl_bits { 247 LINKCTRL_CRC_ERR = (CPC925_BIT(22) | CPC925_BIT(23)), 248 LINKCTRL_LINK_FAIL = CPC925_BIT(27), 249 250 HT_LINKCTRL_DETECTED = (LINKCTRL_CRC_ERR | LINKCTRL_LINK_FAIL), 251 }; 252 253 /************************************************************ 254 * Link FreqCap/Error/Freq/Revision ID Register (LINKERR) 255 ************************************************************/ 256 #define REG_LINKERR_OFFSET 0x70120 257 enum linkerr_bits { 258 LINKERR_EOC_ERR = CPC925_BIT(17), /* End-Of-Chain error */ 259 LINKERR_OVF_ERR = CPC925_BIT(18), /* Receive Buffer Overflow */ 260 LINKERR_PROT_ERR = CPC925_BIT(19), /* Protocol error */ 261 262 HT_LINKERR_DETECTED = (LINKERR_EOC_ERR | LINKERR_OVF_ERR | 263 LINKERR_PROT_ERR), 264 }; 265 266 /************************************************************ 267 * Bridge Control Register (BRGCTRL) 268 ************************************************************/ 269 #define REG_BRGCTRL_OFFSET 0x70300 270 enum brgctrl_bits { 271 BRGCTRL_DETSERR = CPC925_BIT(0), /* SERR on Secondary Bus */ 272 BRGCTRL_SECBUSRESET = CPC925_BIT(9), /* Secondary Bus Reset */ 273 }; 274 275 /* Private structure for edac memory controller */ 276 struct cpc925_mc_pdata { 277 void __iomem *vbase; 278 unsigned long total_mem; 279 const char *name; 280 int edac_idx; 281 }; 282 283 /* Private structure for common edac device */ 284 struct cpc925_dev_info { 285 void __iomem *vbase; 286 struct platform_device *pdev; 287 char *ctl_name; 288 int edac_idx; 289 struct edac_device_ctl_info *edac_dev; 290 void (*init)(struct cpc925_dev_info *dev_info); 291 void (*exit)(struct cpc925_dev_info *dev_info); 292 void (*check)(struct edac_device_ctl_info *edac_dev); 293 }; 294 295 /* Get total memory size from Open Firmware DTB */ 296 static void get_total_mem(struct cpc925_mc_pdata *pdata) 297 { 298 struct device_node *np = NULL; 299 const unsigned int *reg, *reg_end; 300 int len, sw, aw; 301 unsigned long start, size; 302 303 np = of_find_node_by_type(NULL, "memory"); 304 if (!np) 305 return; 306 307 aw = of_n_addr_cells(np); 308 sw = of_n_size_cells(np); 309 reg = (const unsigned int *)of_get_property(np, "reg", &len); 310 reg_end = reg + len/4; 311 312 pdata->total_mem = 0; 313 do { 314 start = of_read_number(reg, aw); 315 reg += aw; 316 size = of_read_number(reg, sw); 317 reg += sw; 318 debugf1("%s: start 0x%lx, size 0x%lx\n", __func__, 319 start, size); 320 pdata->total_mem += size; 321 } while (reg < reg_end); 322 323 of_node_put(np); 324 debugf0("%s: total_mem 0x%lx\n", __func__, pdata->total_mem); 325 } 326 327 static void cpc925_init_csrows(struct mem_ctl_info *mci) 328 { 329 struct cpc925_mc_pdata *pdata = mci->pvt_info; 330 struct csrow_info *csrow; 331 int index; 332 u32 mbmr, mbbar, bba; 333 unsigned long row_size, last_nr_pages = 0; 334 335 get_total_mem(pdata); 336 337 for (index = 0; index < mci->nr_csrows; index++) { 338 mbmr = __raw_readl(pdata->vbase + REG_MBMR_OFFSET + 339 0x20 * index); 340 mbbar = __raw_readl(pdata->vbase + REG_MBBAR_OFFSET + 341 0x20 + index); 342 bba = (((mbmr & MBMR_BBA_MASK) >> MBMR_BBA_SHIFT) << 8) | 343 ((mbbar & MBBAR_BBA_MASK) >> MBBAR_BBA_SHIFT); 344 345 if (bba == 0) 346 continue; /* not populated */ 347 348 csrow = &mci->csrows[index]; 349 350 row_size = bba * (1UL << 28); /* 256M */ 351 csrow->first_page = last_nr_pages; 352 csrow->nr_pages = row_size >> PAGE_SHIFT; 353 csrow->last_page = csrow->first_page + csrow->nr_pages - 1; 354 last_nr_pages = csrow->last_page + 1; 355 356 csrow->mtype = MEM_RDDR; 357 csrow->edac_mode = EDAC_SECDED; 358 359 switch (csrow->nr_channels) { 360 case 1: /* Single channel */ 361 csrow->grain = 32; /* four-beat burst of 32 bytes */ 362 break; 363 case 2: /* Dual channel */ 364 default: 365 csrow->grain = 64; /* four-beat burst of 64 bytes */ 366 break; 367 } 368 369 switch ((mbmr & MBMR_MODE_MASK) >> MBMR_MODE_SHIFT) { 370 case 6: /* 0110, no way to differentiate X8 VS X16 */ 371 case 5: /* 0101 */ 372 case 8: /* 1000 */ 373 csrow->dtype = DEV_X16; 374 break; 375 case 7: /* 0111 */ 376 case 9: /* 1001 */ 377 csrow->dtype = DEV_X8; 378 break; 379 default: 380 csrow->dtype = DEV_UNKNOWN; 381 break; 382 } 383 } 384 } 385 386 /* Enable memory controller ECC detection */ 387 static void cpc925_mc_init(struct mem_ctl_info *mci) 388 { 389 struct cpc925_mc_pdata *pdata = mci->pvt_info; 390 u32 apimask; 391 u32 mccr; 392 393 /* Enable various ECC error exceptions */ 394 apimask = __raw_readl(pdata->vbase + REG_APIMASK_OFFSET); 395 if ((apimask & ECC_MASK_ENABLE) == 0) { 396 apimask |= ECC_MASK_ENABLE; 397 __raw_writel(apimask, pdata->vbase + REG_APIMASK_OFFSET); 398 } 399 400 /* Enable ECC detection */ 401 mccr = __raw_readl(pdata->vbase + REG_MCCR_OFFSET); 402 if ((mccr & MCCR_ECC_EN) == 0) { 403 mccr |= MCCR_ECC_EN; 404 __raw_writel(mccr, pdata->vbase + REG_MCCR_OFFSET); 405 } 406 } 407 408 /* Disable memory controller ECC detection */ 409 static void cpc925_mc_exit(struct mem_ctl_info *mci) 410 { 411 /* 412 * WARNING: 413 * We are supposed to clear the ECC error detection bits, 414 * and it will be no problem to do so. However, once they 415 * are cleared here if we want to re-install CPC925 EDAC 416 * module later, setting them up in cpc925_mc_init() will 417 * trigger machine check exception. 418 * Also, it's ok to leave ECC error detection bits enabled, 419 * since they are reset to 1 by default or by boot loader. 420 */ 421 422 return; 423 } 424 425 /* 426 * Revert DDR column/row/bank addresses into page frame number and 427 * offset in page. 428 * 429 * Suppose memory mode is 0x0111(128-bit mode, identical DIMM pairs), 430 * physical address(PA) bits to column address(CA) bits mappings are: 431 * CA 0 1 2 3 4 5 6 7 8 9 10 432 * PA 59 58 57 56 55 54 53 52 51 50 49 433 * 434 * physical address(PA) bits to bank address(BA) bits mappings are: 435 * BA 0 1 436 * PA 43 44 437 * 438 * physical address(PA) bits to row address(RA) bits mappings are: 439 * RA 0 1 2 3 4 5 6 7 8 9 10 11 12 440 * PA 36 35 34 48 47 46 45 40 41 42 39 38 37 441 */ 442 static void cpc925_mc_get_pfn(struct mem_ctl_info *mci, u32 mear, 443 unsigned long *pfn, unsigned long *offset, int *csrow) 444 { 445 u32 bcnt, rank, col, bank, row; 446 u32 c; 447 unsigned long pa; 448 int i; 449 450 bcnt = (mear & MEAR_BCNT_MASK) >> MEAR_BCNT_SHIFT; 451 rank = (mear & MEAR_RANK_MASK) >> MEAR_RANK_SHIFT; 452 col = (mear & MEAR_COL_MASK) >> MEAR_COL_SHIFT; 453 bank = (mear & MEAR_BANK_MASK) >> MEAR_BANK_SHIFT; 454 row = mear & MEAR_ROW_MASK; 455 456 *csrow = rank; 457 458 #ifdef CONFIG_EDAC_DEBUG 459 if (mci->csrows[rank].first_page == 0) { 460 cpc925_mc_printk(mci, KERN_ERR, "ECC occurs in a " 461 "non-populated csrow, broken hardware?\n"); 462 return; 463 } 464 #endif 465 466 /* Revert csrow number */ 467 pa = mci->csrows[rank].first_page << PAGE_SHIFT; 468 469 /* Revert column address */ 470 col += bcnt; 471 for (i = 0; i < 11; i++) { 472 c = col & 0x1; 473 col >>= 1; 474 pa |= c << (14 - i); 475 } 476 477 /* Revert bank address */ 478 pa |= bank << 19; 479 480 /* Revert row address, in 4 steps */ 481 for (i = 0; i < 3; i++) { 482 c = row & 0x1; 483 row >>= 1; 484 pa |= c << (26 - i); 485 } 486 487 for (i = 0; i < 3; i++) { 488 c = row & 0x1; 489 row >>= 1; 490 pa |= c << (21 + i); 491 } 492 493 for (i = 0; i < 4; i++) { 494 c = row & 0x1; 495 row >>= 1; 496 pa |= c << (18 - i); 497 } 498 499 for (i = 0; i < 3; i++) { 500 c = row & 0x1; 501 row >>= 1; 502 pa |= c << (29 - i); 503 } 504 505 *offset = pa & (PAGE_SIZE - 1); 506 *pfn = pa >> PAGE_SHIFT; 507 508 debugf0("%s: ECC physical address 0x%lx\n", __func__, pa); 509 } 510 511 static int cpc925_mc_find_channel(struct mem_ctl_info *mci, u16 syndrome) 512 { 513 if ((syndrome & MESR_ECC_SYN_H_MASK) == 0) 514 return 0; 515 516 if ((syndrome & MESR_ECC_SYN_L_MASK) == 0) 517 return 1; 518 519 cpc925_mc_printk(mci, KERN_INFO, "Unexpected syndrome value: 0x%x\n", 520 syndrome); 521 return 1; 522 } 523 524 /* Check memory controller registers for ECC errors */ 525 static void cpc925_mc_check(struct mem_ctl_info *mci) 526 { 527 struct cpc925_mc_pdata *pdata = mci->pvt_info; 528 u32 apiexcp; 529 u32 mear; 530 u32 mesr; 531 u16 syndrome; 532 unsigned long pfn = 0, offset = 0; 533 int csrow = 0, channel = 0; 534 535 /* APIEXCP is cleared when read */ 536 apiexcp = __raw_readl(pdata->vbase + REG_APIEXCP_OFFSET); 537 if ((apiexcp & ECC_EXCP_DETECTED) == 0) 538 return; 539 540 mesr = __raw_readl(pdata->vbase + REG_MESR_OFFSET); 541 syndrome = mesr | (MESR_ECC_SYN_H_MASK | MESR_ECC_SYN_L_MASK); 542 543 mear = __raw_readl(pdata->vbase + REG_MEAR_OFFSET); 544 545 /* Revert column/row addresses into page frame number, etc */ 546 cpc925_mc_get_pfn(mci, mear, &pfn, &offset, &csrow); 547 548 if (apiexcp & CECC_EXCP_DETECTED) { 549 cpc925_mc_printk(mci, KERN_INFO, "DRAM CECC Fault\n"); 550 channel = cpc925_mc_find_channel(mci, syndrome); 551 edac_mc_handle_ce(mci, pfn, offset, syndrome, 552 csrow, channel, mci->ctl_name); 553 } 554 555 if (apiexcp & UECC_EXCP_DETECTED) { 556 cpc925_mc_printk(mci, KERN_INFO, "DRAM UECC Fault\n"); 557 edac_mc_handle_ue(mci, pfn, offset, csrow, mci->ctl_name); 558 } 559 560 cpc925_mc_printk(mci, KERN_INFO, "Dump registers:\n"); 561 cpc925_mc_printk(mci, KERN_INFO, "APIMASK 0x%08x\n", 562 __raw_readl(pdata->vbase + REG_APIMASK_OFFSET)); 563 cpc925_mc_printk(mci, KERN_INFO, "APIEXCP 0x%08x\n", 564 apiexcp); 565 cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Ctrl 0x%08x\n", 566 __raw_readl(pdata->vbase + REG_MSCR_OFFSET)); 567 cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Rge Start 0x%08x\n", 568 __raw_readl(pdata->vbase + REG_MSRSR_OFFSET)); 569 cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Rge End 0x%08x\n", 570 __raw_readl(pdata->vbase + REG_MSRER_OFFSET)); 571 cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Pattern 0x%08x\n", 572 __raw_readl(pdata->vbase + REG_MSPR_OFFSET)); 573 cpc925_mc_printk(mci, KERN_INFO, "Mem Chk Ctrl 0x%08x\n", 574 __raw_readl(pdata->vbase + REG_MCCR_OFFSET)); 575 cpc925_mc_printk(mci, KERN_INFO, "Mem Chk Rge End 0x%08x\n", 576 __raw_readl(pdata->vbase + REG_MCRER_OFFSET)); 577 cpc925_mc_printk(mci, KERN_INFO, "Mem Err Address 0x%08x\n", 578 mesr); 579 cpc925_mc_printk(mci, KERN_INFO, "Mem Err Syndrome 0x%08x\n", 580 syndrome); 581 } 582 583 /******************** CPU err device********************************/ 584 /* Enable CPU Errors detection */ 585 static void cpc925_cpu_init(struct cpc925_dev_info *dev_info) 586 { 587 u32 apimask; 588 589 apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET); 590 if ((apimask & CPU_MASK_ENABLE) == 0) { 591 apimask |= CPU_MASK_ENABLE; 592 __raw_writel(apimask, dev_info->vbase + REG_APIMASK_OFFSET); 593 } 594 } 595 596 /* Disable CPU Errors detection */ 597 static void cpc925_cpu_exit(struct cpc925_dev_info *dev_info) 598 { 599 /* 600 * WARNING: 601 * We are supposed to clear the CPU error detection bits, 602 * and it will be no problem to do so. However, once they 603 * are cleared here if we want to re-install CPC925 EDAC 604 * module later, setting them up in cpc925_cpu_init() will 605 * trigger machine check exception. 606 * Also, it's ok to leave CPU error detection bits enabled, 607 * since they are reset to 1 by default. 608 */ 609 610 return; 611 } 612 613 /* Check for CPU Errors */ 614 static void cpc925_cpu_check(struct edac_device_ctl_info *edac_dev) 615 { 616 struct cpc925_dev_info *dev_info = edac_dev->pvt_info; 617 u32 apiexcp; 618 u32 apimask; 619 620 /* APIEXCP is cleared when read */ 621 apiexcp = __raw_readl(dev_info->vbase + REG_APIEXCP_OFFSET); 622 if ((apiexcp & CPU_EXCP_DETECTED) == 0) 623 return; 624 625 apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET); 626 cpc925_printk(KERN_INFO, "Processor Interface Fault\n" 627 "Processor Interface register dump:\n"); 628 cpc925_printk(KERN_INFO, "APIMASK 0x%08x\n", apimask); 629 cpc925_printk(KERN_INFO, "APIEXCP 0x%08x\n", apiexcp); 630 631 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); 632 } 633 634 /******************** HT Link err device****************************/ 635 /* Enable HyperTransport Link Error detection */ 636 static void cpc925_htlink_init(struct cpc925_dev_info *dev_info) 637 { 638 u32 ht_errctrl; 639 640 ht_errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET); 641 if ((ht_errctrl & HT_ERRCTRL_ENABLE) == 0) { 642 ht_errctrl |= HT_ERRCTRL_ENABLE; 643 __raw_writel(ht_errctrl, dev_info->vbase + REG_ERRCTRL_OFFSET); 644 } 645 } 646 647 /* Disable HyperTransport Link Error detection */ 648 static void cpc925_htlink_exit(struct cpc925_dev_info *dev_info) 649 { 650 u32 ht_errctrl; 651 652 ht_errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET); 653 ht_errctrl &= ~HT_ERRCTRL_ENABLE; 654 __raw_writel(ht_errctrl, dev_info->vbase + REG_ERRCTRL_OFFSET); 655 } 656 657 /* Check for HyperTransport Link errors */ 658 static void cpc925_htlink_check(struct edac_device_ctl_info *edac_dev) 659 { 660 struct cpc925_dev_info *dev_info = edac_dev->pvt_info; 661 u32 brgctrl = __raw_readl(dev_info->vbase + REG_BRGCTRL_OFFSET); 662 u32 linkctrl = __raw_readl(dev_info->vbase + REG_LINKCTRL_OFFSET); 663 u32 errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET); 664 u32 linkerr = __raw_readl(dev_info->vbase + REG_LINKERR_OFFSET); 665 666 if (!((brgctrl & BRGCTRL_DETSERR) || 667 (linkctrl & HT_LINKCTRL_DETECTED) || 668 (errctrl & HT_ERRCTRL_DETECTED) || 669 (linkerr & HT_LINKERR_DETECTED))) 670 return; 671 672 cpc925_printk(KERN_INFO, "HT Link Fault\n" 673 "HT register dump:\n"); 674 cpc925_printk(KERN_INFO, "Bridge Ctrl 0x%08x\n", 675 brgctrl); 676 cpc925_printk(KERN_INFO, "Link Config Ctrl 0x%08x\n", 677 linkctrl); 678 cpc925_printk(KERN_INFO, "Error Enum and Ctrl 0x%08x\n", 679 errctrl); 680 cpc925_printk(KERN_INFO, "Link Error 0x%08x\n", 681 linkerr); 682 683 /* Clear by write 1 */ 684 if (brgctrl & BRGCTRL_DETSERR) 685 __raw_writel(BRGCTRL_DETSERR, 686 dev_info->vbase + REG_BRGCTRL_OFFSET); 687 688 if (linkctrl & HT_LINKCTRL_DETECTED) 689 __raw_writel(HT_LINKCTRL_DETECTED, 690 dev_info->vbase + REG_LINKCTRL_OFFSET); 691 692 /* Initiate Secondary Bus Reset to clear the chain failure */ 693 if (errctrl & ERRCTRL_CHN_FAL) 694 __raw_writel(BRGCTRL_SECBUSRESET, 695 dev_info->vbase + REG_BRGCTRL_OFFSET); 696 697 if (errctrl & ERRCTRL_RSP_ERR) 698 __raw_writel(ERRCTRL_RSP_ERR, 699 dev_info->vbase + REG_ERRCTRL_OFFSET); 700 701 if (linkerr & HT_LINKERR_DETECTED) 702 __raw_writel(HT_LINKERR_DETECTED, 703 dev_info->vbase + REG_LINKERR_OFFSET); 704 705 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); 706 } 707 708 static struct cpc925_dev_info cpc925_devs[] = { 709 { 710 .ctl_name = CPC925_CPU_ERR_DEV, 711 .init = cpc925_cpu_init, 712 .exit = cpc925_cpu_exit, 713 .check = cpc925_cpu_check, 714 }, 715 { 716 .ctl_name = CPC925_HT_LINK_DEV, 717 .init = cpc925_htlink_init, 718 .exit = cpc925_htlink_exit, 719 .check = cpc925_htlink_check, 720 }, 721 {0}, /* Terminated by NULL */ 722 }; 723 724 /* 725 * Add CPU Err detection and HyperTransport Link Err detection 726 * as common "edac_device", they have no corresponding device 727 * nodes in the Open Firmware DTB and we have to add platform 728 * devices for them. Also, they will share the MMIO with that 729 * of memory controller. 730 */ 731 static void cpc925_add_edac_devices(void __iomem *vbase) 732 { 733 struct cpc925_dev_info *dev_info; 734 735 if (!vbase) { 736 cpc925_printk(KERN_ERR, "MMIO not established yet\n"); 737 return; 738 } 739 740 for (dev_info = &cpc925_devs[0]; dev_info->init; dev_info++) { 741 dev_info->vbase = vbase; 742 dev_info->pdev = platform_device_register_simple( 743 dev_info->ctl_name, 0, NULL, 0); 744 if (IS_ERR(dev_info->pdev)) { 745 cpc925_printk(KERN_ERR, 746 "Can't register platform device for %s\n", 747 dev_info->ctl_name); 748 continue; 749 } 750 751 /* 752 * Don't have to allocate private structure but 753 * make use of cpc925_devs[] instead. 754 */ 755 dev_info->edac_idx = edac_device_alloc_index(); 756 dev_info->edac_dev = 757 edac_device_alloc_ctl_info(0, dev_info->ctl_name, 758 1, NULL, 0, 0, NULL, 0, dev_info->edac_idx); 759 if (!dev_info->edac_dev) { 760 cpc925_printk(KERN_ERR, "No memory for edac device\n"); 761 goto err1; 762 } 763 764 dev_info->edac_dev->pvt_info = dev_info; 765 dev_info->edac_dev->dev = &dev_info->pdev->dev; 766 dev_info->edac_dev->ctl_name = dev_info->ctl_name; 767 dev_info->edac_dev->mod_name = CPC925_EDAC_MOD_STR; 768 dev_info->edac_dev->dev_name = dev_name(&dev_info->pdev->dev); 769 770 if (edac_op_state == EDAC_OPSTATE_POLL) 771 dev_info->edac_dev->edac_check = dev_info->check; 772 773 if (dev_info->init) 774 dev_info->init(dev_info); 775 776 if (edac_device_add_device(dev_info->edac_dev) > 0) { 777 cpc925_printk(KERN_ERR, 778 "Unable to add edac device for %s\n", 779 dev_info->ctl_name); 780 goto err2; 781 } 782 783 debugf0("%s: Successfully added edac device for %s\n", 784 __func__, dev_info->ctl_name); 785 786 continue; 787 788 err2: 789 if (dev_info->exit) 790 dev_info->exit(dev_info); 791 edac_device_free_ctl_info(dev_info->edac_dev); 792 err1: 793 platform_device_unregister(dev_info->pdev); 794 } 795 } 796 797 /* 798 * Delete the common "edac_device" for CPU Err Detection 799 * and HyperTransport Link Err Detection 800 */ 801 static void cpc925_del_edac_devices(void) 802 { 803 struct cpc925_dev_info *dev_info; 804 805 for (dev_info = &cpc925_devs[0]; dev_info->init; dev_info++) { 806 if (dev_info->edac_dev) { 807 edac_device_del_device(dev_info->edac_dev->dev); 808 edac_device_free_ctl_info(dev_info->edac_dev); 809 platform_device_unregister(dev_info->pdev); 810 } 811 812 if (dev_info->exit) 813 dev_info->exit(dev_info); 814 815 debugf0("%s: Successfully deleted edac device for %s\n", 816 __func__, dev_info->ctl_name); 817 } 818 } 819 820 /* Convert current back-ground scrub rate into byte/sec bandwith */ 821 static int cpc925_get_sdram_scrub_rate(struct mem_ctl_info *mci) 822 { 823 struct cpc925_mc_pdata *pdata = mci->pvt_info; 824 int bw; 825 u32 mscr; 826 u8 si; 827 828 mscr = __raw_readl(pdata->vbase + REG_MSCR_OFFSET); 829 si = (mscr & MSCR_SI_MASK) >> MSCR_SI_SHIFT; 830 831 debugf0("%s, Mem Scrub Ctrl Register 0x%x\n", __func__, mscr); 832 833 if (((mscr & MSCR_SCRUB_MOD_MASK) != MSCR_BACKGR_SCRUB) || 834 (si == 0)) { 835 cpc925_mc_printk(mci, KERN_INFO, "Scrub mode not enabled\n"); 836 bw = 0; 837 } else 838 bw = CPC925_SCRUB_BLOCK_SIZE * 0xFA67 / si; 839 840 return bw; 841 } 842 843 /* Return 0 for single channel; 1 for dual channel */ 844 static int cpc925_mc_get_channels(void __iomem *vbase) 845 { 846 int dual = 0; 847 u32 mbcr; 848 849 mbcr = __raw_readl(vbase + REG_MBCR_OFFSET); 850 851 /* 852 * Dual channel only when 128-bit wide physical bus 853 * and 128-bit configuration. 854 */ 855 if (((mbcr & MBCR_64BITCFG_MASK) == 0) && 856 ((mbcr & MBCR_64BITBUS_MASK) == 0)) 857 dual = 1; 858 859 debugf0("%s: %s channel\n", __func__, 860 (dual > 0) ? "Dual" : "Single"); 861 862 return dual; 863 } 864 865 static int __devinit cpc925_probe(struct platform_device *pdev) 866 { 867 static int edac_mc_idx; 868 struct mem_ctl_info *mci; 869 void __iomem *vbase; 870 struct cpc925_mc_pdata *pdata; 871 struct resource *r; 872 int res = 0, nr_channels; 873 874 debugf0("%s: %s platform device found!\n", __func__, pdev->name); 875 876 if (!devres_open_group(&pdev->dev, cpc925_probe, GFP_KERNEL)) { 877 res = -ENOMEM; 878 goto out; 879 } 880 881 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 882 if (!r) { 883 cpc925_printk(KERN_ERR, "Unable to get resource\n"); 884 res = -ENOENT; 885 goto err1; 886 } 887 888 if (!devm_request_mem_region(&pdev->dev, 889 r->start, 890 resource_size(r), 891 pdev->name)) { 892 cpc925_printk(KERN_ERR, "Unable to request mem region\n"); 893 res = -EBUSY; 894 goto err1; 895 } 896 897 vbase = devm_ioremap(&pdev->dev, r->start, resource_size(r)); 898 if (!vbase) { 899 cpc925_printk(KERN_ERR, "Unable to ioremap device\n"); 900 res = -ENOMEM; 901 goto err2; 902 } 903 904 nr_channels = cpc925_mc_get_channels(vbase); 905 mci = edac_mc_alloc(sizeof(struct cpc925_mc_pdata), 906 CPC925_NR_CSROWS, nr_channels + 1, edac_mc_idx); 907 if (!mci) { 908 cpc925_printk(KERN_ERR, "No memory for mem_ctl_info\n"); 909 res = -ENOMEM; 910 goto err2; 911 } 912 913 pdata = mci->pvt_info; 914 pdata->vbase = vbase; 915 pdata->edac_idx = edac_mc_idx++; 916 pdata->name = pdev->name; 917 918 mci->dev = &pdev->dev; 919 platform_set_drvdata(pdev, mci); 920 mci->dev_name = dev_name(&pdev->dev); 921 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR; 922 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 923 mci->edac_cap = EDAC_FLAG_SECDED; 924 mci->mod_name = CPC925_EDAC_MOD_STR; 925 mci->mod_ver = CPC925_EDAC_REVISION; 926 mci->ctl_name = pdev->name; 927 928 if (edac_op_state == EDAC_OPSTATE_POLL) 929 mci->edac_check = cpc925_mc_check; 930 931 mci->ctl_page_to_phys = NULL; 932 mci->scrub_mode = SCRUB_SW_SRC; 933 mci->set_sdram_scrub_rate = NULL; 934 mci->get_sdram_scrub_rate = cpc925_get_sdram_scrub_rate; 935 936 cpc925_init_csrows(mci); 937 938 /* Setup memory controller registers */ 939 cpc925_mc_init(mci); 940 941 if (edac_mc_add_mc(mci) > 0) { 942 cpc925_mc_printk(mci, KERN_ERR, "Failed edac_mc_add_mc()\n"); 943 goto err3; 944 } 945 946 cpc925_add_edac_devices(vbase); 947 948 /* get this far and it's successful */ 949 debugf0("%s: success\n", __func__); 950 951 res = 0; 952 goto out; 953 954 err3: 955 cpc925_mc_exit(mci); 956 edac_mc_free(mci); 957 err2: 958 devm_release_mem_region(&pdev->dev, r->start, resource_size(r)); 959 err1: 960 devres_release_group(&pdev->dev, cpc925_probe); 961 out: 962 return res; 963 } 964 965 static int cpc925_remove(struct platform_device *pdev) 966 { 967 struct mem_ctl_info *mci = platform_get_drvdata(pdev); 968 969 /* 970 * Delete common edac devices before edac mc, because 971 * the former share the MMIO of the latter. 972 */ 973 cpc925_del_edac_devices(); 974 cpc925_mc_exit(mci); 975 976 edac_mc_del_mc(&pdev->dev); 977 edac_mc_free(mci); 978 979 return 0; 980 } 981 982 static struct platform_driver cpc925_edac_driver = { 983 .probe = cpc925_probe, 984 .remove = cpc925_remove, 985 .driver = { 986 .name = "cpc925_edac", 987 } 988 }; 989 990 static int __init cpc925_edac_init(void) 991 { 992 int ret = 0; 993 994 printk(KERN_INFO "IBM CPC925 EDAC driver " CPC925_EDAC_REVISION "\n"); 995 printk(KERN_INFO "\t(c) 2008 Wind River Systems, Inc\n"); 996 997 /* Only support POLL mode so far */ 998 edac_op_state = EDAC_OPSTATE_POLL; 999 1000 ret = platform_driver_register(&cpc925_edac_driver); 1001 if (ret) { 1002 printk(KERN_WARNING "Failed to register %s\n", 1003 CPC925_EDAC_MOD_STR); 1004 } 1005 1006 return ret; 1007 } 1008 1009 static void __exit cpc925_edac_exit(void) 1010 { 1011 platform_driver_unregister(&cpc925_edac_driver); 1012 } 1013 1014 module_init(cpc925_edac_init); 1015 module_exit(cpc925_edac_exit); 1016 1017 MODULE_LICENSE("GPL"); 1018 MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>"); 1019 MODULE_DESCRIPTION("IBM CPC925 Bridge and MC EDAC kernel module"); 1020