1 /* 2 * cpc925_edac.c, EDAC driver for IBM CPC925 Bridge and Memory Controller. 3 * 4 * Copyright (c) 2008 Wind River Systems, Inc. 5 * 6 * Authors: Cao Qingtao <qingtao.cao@windriver.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 15 * See the GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 */ 21 22 #include <linux/module.h> 23 #include <linux/init.h> 24 #include <linux/io.h> 25 #include <linux/edac.h> 26 #include <linux/of.h> 27 #include <linux/platform_device.h> 28 #include <linux/gfp.h> 29 30 #include "edac_module.h" 31 32 #define CPC925_EDAC_REVISION " Ver: 1.0.0" 33 #define CPC925_EDAC_MOD_STR "cpc925_edac" 34 35 #define cpc925_printk(level, fmt, arg...) \ 36 edac_printk(level, "CPC925", fmt, ##arg) 37 38 #define cpc925_mc_printk(mci, level, fmt, arg...) \ 39 edac_mc_chipset_printk(mci, level, "CPC925", fmt, ##arg) 40 41 /* 42 * CPC925 registers are of 32 bits with bit0 defined at the 43 * most significant bit and bit31 at that of least significant. 44 */ 45 #define CPC925_BITS_PER_REG 32 46 #define CPC925_BIT(nr) (1UL << (CPC925_BITS_PER_REG - 1 - nr)) 47 48 /* 49 * EDAC device names for the error detections of 50 * CPU Interface and Hypertransport Link. 51 */ 52 #define CPC925_CPU_ERR_DEV "cpu" 53 #define CPC925_HT_LINK_DEV "htlink" 54 55 /* Suppose DDR Refresh cycle is 15.6 microsecond */ 56 #define CPC925_REF_FREQ 0xFA69 57 #define CPC925_SCRUB_BLOCK_SIZE 64 /* bytes */ 58 #define CPC925_NR_CSROWS 8 59 60 /* 61 * All registers and bits definitions are taken from 62 * "CPC925 Bridge and Memory Controller User Manual, SA14-2761-02". 63 */ 64 65 /* 66 * CPU and Memory Controller Registers 67 */ 68 /************************************************************ 69 * Processor Interface Exception Mask Register (APIMASK) 70 ************************************************************/ 71 #define REG_APIMASK_OFFSET 0x30070 72 enum apimask_bits { 73 APIMASK_DART = CPC925_BIT(0), /* DART Exception */ 74 APIMASK_ADI0 = CPC925_BIT(1), /* Handshake Error on PI0_ADI */ 75 APIMASK_ADI1 = CPC925_BIT(2), /* Handshake Error on PI1_ADI */ 76 APIMASK_STAT = CPC925_BIT(3), /* Status Exception */ 77 APIMASK_DERR = CPC925_BIT(4), /* Data Error Exception */ 78 APIMASK_ADRS0 = CPC925_BIT(5), /* Addressing Exception on PI0 */ 79 APIMASK_ADRS1 = CPC925_BIT(6), /* Addressing Exception on PI1 */ 80 /* BIT(7) Reserved */ 81 APIMASK_ECC_UE_H = CPC925_BIT(8), /* UECC upper */ 82 APIMASK_ECC_CE_H = CPC925_BIT(9), /* CECC upper */ 83 APIMASK_ECC_UE_L = CPC925_BIT(10), /* UECC lower */ 84 APIMASK_ECC_CE_L = CPC925_BIT(11), /* CECC lower */ 85 86 CPU_MASK_ENABLE = (APIMASK_DART | APIMASK_ADI0 | APIMASK_ADI1 | 87 APIMASK_STAT | APIMASK_DERR | APIMASK_ADRS0 | 88 APIMASK_ADRS1), 89 ECC_MASK_ENABLE = (APIMASK_ECC_UE_H | APIMASK_ECC_CE_H | 90 APIMASK_ECC_UE_L | APIMASK_ECC_CE_L), 91 }; 92 #define APIMASK_ADI(n) CPC925_BIT(((n)+1)) 93 94 /************************************************************ 95 * Processor Interface Exception Register (APIEXCP) 96 ************************************************************/ 97 #define REG_APIEXCP_OFFSET 0x30060 98 enum apiexcp_bits { 99 APIEXCP_DART = CPC925_BIT(0), /* DART Exception */ 100 APIEXCP_ADI0 = CPC925_BIT(1), /* Handshake Error on PI0_ADI */ 101 APIEXCP_ADI1 = CPC925_BIT(2), /* Handshake Error on PI1_ADI */ 102 APIEXCP_STAT = CPC925_BIT(3), /* Status Exception */ 103 APIEXCP_DERR = CPC925_BIT(4), /* Data Error Exception */ 104 APIEXCP_ADRS0 = CPC925_BIT(5), /* Addressing Exception on PI0 */ 105 APIEXCP_ADRS1 = CPC925_BIT(6), /* Addressing Exception on PI1 */ 106 /* BIT(7) Reserved */ 107 APIEXCP_ECC_UE_H = CPC925_BIT(8), /* UECC upper */ 108 APIEXCP_ECC_CE_H = CPC925_BIT(9), /* CECC upper */ 109 APIEXCP_ECC_UE_L = CPC925_BIT(10), /* UECC lower */ 110 APIEXCP_ECC_CE_L = CPC925_BIT(11), /* CECC lower */ 111 112 CPU_EXCP_DETECTED = (APIEXCP_DART | APIEXCP_ADI0 | APIEXCP_ADI1 | 113 APIEXCP_STAT | APIEXCP_DERR | APIEXCP_ADRS0 | 114 APIEXCP_ADRS1), 115 UECC_EXCP_DETECTED = (APIEXCP_ECC_UE_H | APIEXCP_ECC_UE_L), 116 CECC_EXCP_DETECTED = (APIEXCP_ECC_CE_H | APIEXCP_ECC_CE_L), 117 ECC_EXCP_DETECTED = (UECC_EXCP_DETECTED | CECC_EXCP_DETECTED), 118 }; 119 120 /************************************************************ 121 * Memory Bus Configuration Register (MBCR) 122 ************************************************************/ 123 #define REG_MBCR_OFFSET 0x2190 124 #define MBCR_64BITCFG_SHIFT 23 125 #define MBCR_64BITCFG_MASK (1UL << MBCR_64BITCFG_SHIFT) 126 #define MBCR_64BITBUS_SHIFT 22 127 #define MBCR_64BITBUS_MASK (1UL << MBCR_64BITBUS_SHIFT) 128 129 /************************************************************ 130 * Memory Bank Mode Register (MBMR) 131 ************************************************************/ 132 #define REG_MBMR_OFFSET 0x21C0 133 #define MBMR_MODE_MAX_VALUE 0xF 134 #define MBMR_MODE_SHIFT 25 135 #define MBMR_MODE_MASK (MBMR_MODE_MAX_VALUE << MBMR_MODE_SHIFT) 136 #define MBMR_BBA_SHIFT 24 137 #define MBMR_BBA_MASK (1UL << MBMR_BBA_SHIFT) 138 139 /************************************************************ 140 * Memory Bank Boundary Address Register (MBBAR) 141 ************************************************************/ 142 #define REG_MBBAR_OFFSET 0x21D0 143 #define MBBAR_BBA_MAX_VALUE 0xFF 144 #define MBBAR_BBA_SHIFT 24 145 #define MBBAR_BBA_MASK (MBBAR_BBA_MAX_VALUE << MBBAR_BBA_SHIFT) 146 147 /************************************************************ 148 * Memory Scrub Control Register (MSCR) 149 ************************************************************/ 150 #define REG_MSCR_OFFSET 0x2400 151 #define MSCR_SCRUB_MOD_MASK 0xC0000000 /* scrub_mod - bit0:1*/ 152 #define MSCR_BACKGR_SCRUB 0x40000000 /* 01 */ 153 #define MSCR_SI_SHIFT 16 /* si - bit8:15*/ 154 #define MSCR_SI_MAX_VALUE 0xFF 155 #define MSCR_SI_MASK (MSCR_SI_MAX_VALUE << MSCR_SI_SHIFT) 156 157 /************************************************************ 158 * Memory Scrub Range Start Register (MSRSR) 159 ************************************************************/ 160 #define REG_MSRSR_OFFSET 0x2410 161 162 /************************************************************ 163 * Memory Scrub Range End Register (MSRER) 164 ************************************************************/ 165 #define REG_MSRER_OFFSET 0x2420 166 167 /************************************************************ 168 * Memory Scrub Pattern Register (MSPR) 169 ************************************************************/ 170 #define REG_MSPR_OFFSET 0x2430 171 172 /************************************************************ 173 * Memory Check Control Register (MCCR) 174 ************************************************************/ 175 #define REG_MCCR_OFFSET 0x2440 176 enum mccr_bits { 177 MCCR_ECC_EN = CPC925_BIT(0), /* ECC high and low check */ 178 }; 179 180 /************************************************************ 181 * Memory Check Range End Register (MCRER) 182 ************************************************************/ 183 #define REG_MCRER_OFFSET 0x2450 184 185 /************************************************************ 186 * Memory Error Address Register (MEAR) 187 ************************************************************/ 188 #define REG_MEAR_OFFSET 0x2460 189 #define MEAR_BCNT_MAX_VALUE 0x3 190 #define MEAR_BCNT_SHIFT 30 191 #define MEAR_BCNT_MASK (MEAR_BCNT_MAX_VALUE << MEAR_BCNT_SHIFT) 192 #define MEAR_RANK_MAX_VALUE 0x7 193 #define MEAR_RANK_SHIFT 27 194 #define MEAR_RANK_MASK (MEAR_RANK_MAX_VALUE << MEAR_RANK_SHIFT) 195 #define MEAR_COL_MAX_VALUE 0x7FF 196 #define MEAR_COL_SHIFT 16 197 #define MEAR_COL_MASK (MEAR_COL_MAX_VALUE << MEAR_COL_SHIFT) 198 #define MEAR_BANK_MAX_VALUE 0x3 199 #define MEAR_BANK_SHIFT 14 200 #define MEAR_BANK_MASK (MEAR_BANK_MAX_VALUE << MEAR_BANK_SHIFT) 201 #define MEAR_ROW_MASK 0x00003FFF 202 203 /************************************************************ 204 * Memory Error Syndrome Register (MESR) 205 ************************************************************/ 206 #define REG_MESR_OFFSET 0x2470 207 #define MESR_ECC_SYN_H_MASK 0xFF00 208 #define MESR_ECC_SYN_L_MASK 0x00FF 209 210 /************************************************************ 211 * Memory Mode Control Register (MMCR) 212 ************************************************************/ 213 #define REG_MMCR_OFFSET 0x2500 214 enum mmcr_bits { 215 MMCR_REG_DIMM_MODE = CPC925_BIT(3), 216 }; 217 218 /* 219 * HyperTransport Link Registers 220 */ 221 /************************************************************ 222 * Error Handling/Enumeration Scratch Pad Register (ERRCTRL) 223 ************************************************************/ 224 #define REG_ERRCTRL_OFFSET 0x70140 225 enum errctrl_bits { /* nonfatal interrupts for */ 226 ERRCTRL_SERR_NF = CPC925_BIT(0), /* system error */ 227 ERRCTRL_CRC_NF = CPC925_BIT(1), /* CRC error */ 228 ERRCTRL_RSP_NF = CPC925_BIT(2), /* Response error */ 229 ERRCTRL_EOC_NF = CPC925_BIT(3), /* End-Of-Chain error */ 230 ERRCTRL_OVF_NF = CPC925_BIT(4), /* Overflow error */ 231 ERRCTRL_PROT_NF = CPC925_BIT(5), /* Protocol error */ 232 233 ERRCTRL_RSP_ERR = CPC925_BIT(6), /* Response error received */ 234 ERRCTRL_CHN_FAL = CPC925_BIT(7), /* Sync flooding detected */ 235 236 HT_ERRCTRL_ENABLE = (ERRCTRL_SERR_NF | ERRCTRL_CRC_NF | 237 ERRCTRL_RSP_NF | ERRCTRL_EOC_NF | 238 ERRCTRL_OVF_NF | ERRCTRL_PROT_NF), 239 HT_ERRCTRL_DETECTED = (ERRCTRL_RSP_ERR | ERRCTRL_CHN_FAL), 240 }; 241 242 /************************************************************ 243 * Link Configuration and Link Control Register (LINKCTRL) 244 ************************************************************/ 245 #define REG_LINKCTRL_OFFSET 0x70110 246 enum linkctrl_bits { 247 LINKCTRL_CRC_ERR = (CPC925_BIT(22) | CPC925_BIT(23)), 248 LINKCTRL_LINK_FAIL = CPC925_BIT(27), 249 250 HT_LINKCTRL_DETECTED = (LINKCTRL_CRC_ERR | LINKCTRL_LINK_FAIL), 251 }; 252 253 /************************************************************ 254 * Link FreqCap/Error/Freq/Revision ID Register (LINKERR) 255 ************************************************************/ 256 #define REG_LINKERR_OFFSET 0x70120 257 enum linkerr_bits { 258 LINKERR_EOC_ERR = CPC925_BIT(17), /* End-Of-Chain error */ 259 LINKERR_OVF_ERR = CPC925_BIT(18), /* Receive Buffer Overflow */ 260 LINKERR_PROT_ERR = CPC925_BIT(19), /* Protocol error */ 261 262 HT_LINKERR_DETECTED = (LINKERR_EOC_ERR | LINKERR_OVF_ERR | 263 LINKERR_PROT_ERR), 264 }; 265 266 /************************************************************ 267 * Bridge Control Register (BRGCTRL) 268 ************************************************************/ 269 #define REG_BRGCTRL_OFFSET 0x70300 270 enum brgctrl_bits { 271 BRGCTRL_DETSERR = CPC925_BIT(0), /* SERR on Secondary Bus */ 272 BRGCTRL_SECBUSRESET = CPC925_BIT(9), /* Secondary Bus Reset */ 273 }; 274 275 /* Private structure for edac memory controller */ 276 struct cpc925_mc_pdata { 277 void __iomem *vbase; 278 unsigned long total_mem; 279 const char *name; 280 int edac_idx; 281 }; 282 283 /* Private structure for common edac device */ 284 struct cpc925_dev_info { 285 void __iomem *vbase; 286 struct platform_device *pdev; 287 char *ctl_name; 288 int edac_idx; 289 struct edac_device_ctl_info *edac_dev; 290 void (*init)(struct cpc925_dev_info *dev_info); 291 void (*exit)(struct cpc925_dev_info *dev_info); 292 void (*check)(struct edac_device_ctl_info *edac_dev); 293 }; 294 295 /* Get total memory size from Open Firmware DTB */ 296 static void get_total_mem(struct cpc925_mc_pdata *pdata) 297 { 298 struct device_node *np = NULL; 299 const unsigned int *reg, *reg_end; 300 int len, sw, aw; 301 unsigned long start, size; 302 303 np = of_find_node_by_type(NULL, "memory"); 304 if (!np) 305 return; 306 307 aw = of_n_addr_cells(np); 308 sw = of_n_size_cells(np); 309 reg = (const unsigned int *)of_get_property(np, "reg", &len); 310 reg_end = reg + len/4; 311 312 pdata->total_mem = 0; 313 do { 314 start = of_read_number(reg, aw); 315 reg += aw; 316 size = of_read_number(reg, sw); 317 reg += sw; 318 edac_dbg(1, "start 0x%lx, size 0x%lx\n", start, size); 319 pdata->total_mem += size; 320 } while (reg < reg_end); 321 322 of_node_put(np); 323 edac_dbg(0, "total_mem 0x%lx\n", pdata->total_mem); 324 } 325 326 static void cpc925_init_csrows(struct mem_ctl_info *mci) 327 { 328 struct cpc925_mc_pdata *pdata = mci->pvt_info; 329 struct csrow_info *csrow; 330 struct dimm_info *dimm; 331 enum dev_type dtype; 332 int index, j; 333 u32 mbmr, mbbar, bba, grain; 334 unsigned long row_size, nr_pages, last_nr_pages = 0; 335 336 get_total_mem(pdata); 337 338 for (index = 0; index < mci->nr_csrows; index++) { 339 mbmr = __raw_readl(pdata->vbase + REG_MBMR_OFFSET + 340 0x20 * index); 341 mbbar = __raw_readl(pdata->vbase + REG_MBBAR_OFFSET + 342 0x20 + index); 343 bba = (((mbmr & MBMR_BBA_MASK) >> MBMR_BBA_SHIFT) << 8) | 344 ((mbbar & MBBAR_BBA_MASK) >> MBBAR_BBA_SHIFT); 345 346 if (bba == 0) 347 continue; /* not populated */ 348 349 csrow = mci->csrows[index]; 350 351 row_size = bba * (1UL << 28); /* 256M */ 352 csrow->first_page = last_nr_pages; 353 nr_pages = row_size >> PAGE_SHIFT; 354 csrow->last_page = csrow->first_page + nr_pages - 1; 355 last_nr_pages = csrow->last_page + 1; 356 357 switch (csrow->nr_channels) { 358 case 1: /* Single channel */ 359 grain = 32; /* four-beat burst of 32 bytes */ 360 break; 361 case 2: /* Dual channel */ 362 default: 363 grain = 64; /* four-beat burst of 64 bytes */ 364 break; 365 } 366 switch ((mbmr & MBMR_MODE_MASK) >> MBMR_MODE_SHIFT) { 367 case 6: /* 0110, no way to differentiate X8 VS X16 */ 368 case 5: /* 0101 */ 369 case 8: /* 1000 */ 370 dtype = DEV_X16; 371 break; 372 case 7: /* 0111 */ 373 case 9: /* 1001 */ 374 dtype = DEV_X8; 375 break; 376 default: 377 dtype = DEV_UNKNOWN; 378 break; 379 } 380 for (j = 0; j < csrow->nr_channels; j++) { 381 dimm = csrow->channels[j]->dimm; 382 dimm->nr_pages = nr_pages / csrow->nr_channels; 383 dimm->mtype = MEM_RDDR; 384 dimm->edac_mode = EDAC_SECDED; 385 dimm->grain = grain; 386 dimm->dtype = dtype; 387 } 388 } 389 } 390 391 /* Enable memory controller ECC detection */ 392 static void cpc925_mc_init(struct mem_ctl_info *mci) 393 { 394 struct cpc925_mc_pdata *pdata = mci->pvt_info; 395 u32 apimask; 396 u32 mccr; 397 398 /* Enable various ECC error exceptions */ 399 apimask = __raw_readl(pdata->vbase + REG_APIMASK_OFFSET); 400 if ((apimask & ECC_MASK_ENABLE) == 0) { 401 apimask |= ECC_MASK_ENABLE; 402 __raw_writel(apimask, pdata->vbase + REG_APIMASK_OFFSET); 403 } 404 405 /* Enable ECC detection */ 406 mccr = __raw_readl(pdata->vbase + REG_MCCR_OFFSET); 407 if ((mccr & MCCR_ECC_EN) == 0) { 408 mccr |= MCCR_ECC_EN; 409 __raw_writel(mccr, pdata->vbase + REG_MCCR_OFFSET); 410 } 411 } 412 413 /* Disable memory controller ECC detection */ 414 static void cpc925_mc_exit(struct mem_ctl_info *mci) 415 { 416 /* 417 * WARNING: 418 * We are supposed to clear the ECC error detection bits, 419 * and it will be no problem to do so. However, once they 420 * are cleared here if we want to re-install CPC925 EDAC 421 * module later, setting them up in cpc925_mc_init() will 422 * trigger machine check exception. 423 * Also, it's ok to leave ECC error detection bits enabled, 424 * since they are reset to 1 by default or by boot loader. 425 */ 426 427 return; 428 } 429 430 /* 431 * Revert DDR column/row/bank addresses into page frame number and 432 * offset in page. 433 * 434 * Suppose memory mode is 0x0111(128-bit mode, identical DIMM pairs), 435 * physical address(PA) bits to column address(CA) bits mappings are: 436 * CA 0 1 2 3 4 5 6 7 8 9 10 437 * PA 59 58 57 56 55 54 53 52 51 50 49 438 * 439 * physical address(PA) bits to bank address(BA) bits mappings are: 440 * BA 0 1 441 * PA 43 44 442 * 443 * physical address(PA) bits to row address(RA) bits mappings are: 444 * RA 0 1 2 3 4 5 6 7 8 9 10 11 12 445 * PA 36 35 34 48 47 46 45 40 41 42 39 38 37 446 */ 447 static void cpc925_mc_get_pfn(struct mem_ctl_info *mci, u32 mear, 448 unsigned long *pfn, unsigned long *offset, int *csrow) 449 { 450 u32 bcnt, rank, col, bank, row; 451 u32 c; 452 unsigned long pa; 453 int i; 454 455 bcnt = (mear & MEAR_BCNT_MASK) >> MEAR_BCNT_SHIFT; 456 rank = (mear & MEAR_RANK_MASK) >> MEAR_RANK_SHIFT; 457 col = (mear & MEAR_COL_MASK) >> MEAR_COL_SHIFT; 458 bank = (mear & MEAR_BANK_MASK) >> MEAR_BANK_SHIFT; 459 row = mear & MEAR_ROW_MASK; 460 461 *csrow = rank; 462 463 #ifdef CONFIG_EDAC_DEBUG 464 if (mci->csrows[rank]->first_page == 0) { 465 cpc925_mc_printk(mci, KERN_ERR, "ECC occurs in a " 466 "non-populated csrow, broken hardware?\n"); 467 return; 468 } 469 #endif 470 471 /* Revert csrow number */ 472 pa = mci->csrows[rank]->first_page << PAGE_SHIFT; 473 474 /* Revert column address */ 475 col += bcnt; 476 for (i = 0; i < 11; i++) { 477 c = col & 0x1; 478 col >>= 1; 479 pa |= c << (14 - i); 480 } 481 482 /* Revert bank address */ 483 pa |= bank << 19; 484 485 /* Revert row address, in 4 steps */ 486 for (i = 0; i < 3; i++) { 487 c = row & 0x1; 488 row >>= 1; 489 pa |= c << (26 - i); 490 } 491 492 for (i = 0; i < 3; i++) { 493 c = row & 0x1; 494 row >>= 1; 495 pa |= c << (21 + i); 496 } 497 498 for (i = 0; i < 4; i++) { 499 c = row & 0x1; 500 row >>= 1; 501 pa |= c << (18 - i); 502 } 503 504 for (i = 0; i < 3; i++) { 505 c = row & 0x1; 506 row >>= 1; 507 pa |= c << (29 - i); 508 } 509 510 *offset = pa & (PAGE_SIZE - 1); 511 *pfn = pa >> PAGE_SHIFT; 512 513 edac_dbg(0, "ECC physical address 0x%lx\n", pa); 514 } 515 516 static int cpc925_mc_find_channel(struct mem_ctl_info *mci, u16 syndrome) 517 { 518 if ((syndrome & MESR_ECC_SYN_H_MASK) == 0) 519 return 0; 520 521 if ((syndrome & MESR_ECC_SYN_L_MASK) == 0) 522 return 1; 523 524 cpc925_mc_printk(mci, KERN_INFO, "Unexpected syndrome value: 0x%x\n", 525 syndrome); 526 return 1; 527 } 528 529 /* Check memory controller registers for ECC errors */ 530 static void cpc925_mc_check(struct mem_ctl_info *mci) 531 { 532 struct cpc925_mc_pdata *pdata = mci->pvt_info; 533 u32 apiexcp; 534 u32 mear; 535 u32 mesr; 536 u16 syndrome; 537 unsigned long pfn = 0, offset = 0; 538 int csrow = 0, channel = 0; 539 540 /* APIEXCP is cleared when read */ 541 apiexcp = __raw_readl(pdata->vbase + REG_APIEXCP_OFFSET); 542 if ((apiexcp & ECC_EXCP_DETECTED) == 0) 543 return; 544 545 mesr = __raw_readl(pdata->vbase + REG_MESR_OFFSET); 546 syndrome = mesr | (MESR_ECC_SYN_H_MASK | MESR_ECC_SYN_L_MASK); 547 548 mear = __raw_readl(pdata->vbase + REG_MEAR_OFFSET); 549 550 /* Revert column/row addresses into page frame number, etc */ 551 cpc925_mc_get_pfn(mci, mear, &pfn, &offset, &csrow); 552 553 if (apiexcp & CECC_EXCP_DETECTED) { 554 cpc925_mc_printk(mci, KERN_INFO, "DRAM CECC Fault\n"); 555 channel = cpc925_mc_find_channel(mci, syndrome); 556 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 557 pfn, offset, syndrome, 558 csrow, channel, -1, 559 mci->ctl_name, ""); 560 } 561 562 if (apiexcp & UECC_EXCP_DETECTED) { 563 cpc925_mc_printk(mci, KERN_INFO, "DRAM UECC Fault\n"); 564 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 565 pfn, offset, 0, 566 csrow, -1, -1, 567 mci->ctl_name, ""); 568 } 569 570 cpc925_mc_printk(mci, KERN_INFO, "Dump registers:\n"); 571 cpc925_mc_printk(mci, KERN_INFO, "APIMASK 0x%08x\n", 572 __raw_readl(pdata->vbase + REG_APIMASK_OFFSET)); 573 cpc925_mc_printk(mci, KERN_INFO, "APIEXCP 0x%08x\n", 574 apiexcp); 575 cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Ctrl 0x%08x\n", 576 __raw_readl(pdata->vbase + REG_MSCR_OFFSET)); 577 cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Rge Start 0x%08x\n", 578 __raw_readl(pdata->vbase + REG_MSRSR_OFFSET)); 579 cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Rge End 0x%08x\n", 580 __raw_readl(pdata->vbase + REG_MSRER_OFFSET)); 581 cpc925_mc_printk(mci, KERN_INFO, "Mem Scrub Pattern 0x%08x\n", 582 __raw_readl(pdata->vbase + REG_MSPR_OFFSET)); 583 cpc925_mc_printk(mci, KERN_INFO, "Mem Chk Ctrl 0x%08x\n", 584 __raw_readl(pdata->vbase + REG_MCCR_OFFSET)); 585 cpc925_mc_printk(mci, KERN_INFO, "Mem Chk Rge End 0x%08x\n", 586 __raw_readl(pdata->vbase + REG_MCRER_OFFSET)); 587 cpc925_mc_printk(mci, KERN_INFO, "Mem Err Address 0x%08x\n", 588 mesr); 589 cpc925_mc_printk(mci, KERN_INFO, "Mem Err Syndrome 0x%08x\n", 590 syndrome); 591 } 592 593 /******************** CPU err device********************************/ 594 static u32 cpc925_cpu_mask_disabled(void) 595 { 596 struct device_node *cpunode; 597 static u32 mask = 0; 598 599 /* use cached value if available */ 600 if (mask != 0) 601 return mask; 602 603 mask = APIMASK_ADI0 | APIMASK_ADI1; 604 605 for_each_of_cpu_node(cpunode) { 606 const u32 *reg = of_get_property(cpunode, "reg", NULL); 607 if (reg == NULL || *reg > 2) { 608 cpc925_printk(KERN_ERR, "Bad reg value at %pOF\n", cpunode); 609 continue; 610 } 611 612 mask &= ~APIMASK_ADI(*reg); 613 } 614 615 if (mask != (APIMASK_ADI0 | APIMASK_ADI1)) { 616 /* We assume that each CPU sits on it's own PI and that 617 * for present CPUs the reg property equals to the PI 618 * interface id */ 619 cpc925_printk(KERN_WARNING, 620 "Assuming PI id is equal to CPU MPIC id!\n"); 621 } 622 623 return mask; 624 } 625 626 /* Enable CPU Errors detection */ 627 static void cpc925_cpu_init(struct cpc925_dev_info *dev_info) 628 { 629 u32 apimask; 630 u32 cpumask; 631 632 apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET); 633 634 cpumask = cpc925_cpu_mask_disabled(); 635 if (apimask & cpumask) { 636 cpc925_printk(KERN_WARNING, "CPU(s) not present, " 637 "but enabled in APIMASK, disabling\n"); 638 apimask &= ~cpumask; 639 } 640 641 if ((apimask & CPU_MASK_ENABLE) == 0) 642 apimask |= CPU_MASK_ENABLE; 643 644 __raw_writel(apimask, dev_info->vbase + REG_APIMASK_OFFSET); 645 } 646 647 /* Disable CPU Errors detection */ 648 static void cpc925_cpu_exit(struct cpc925_dev_info *dev_info) 649 { 650 /* 651 * WARNING: 652 * We are supposed to clear the CPU error detection bits, 653 * and it will be no problem to do so. However, once they 654 * are cleared here if we want to re-install CPC925 EDAC 655 * module later, setting them up in cpc925_cpu_init() will 656 * trigger machine check exception. 657 * Also, it's ok to leave CPU error detection bits enabled, 658 * since they are reset to 1 by default. 659 */ 660 661 return; 662 } 663 664 /* Check for CPU Errors */ 665 static void cpc925_cpu_check(struct edac_device_ctl_info *edac_dev) 666 { 667 struct cpc925_dev_info *dev_info = edac_dev->pvt_info; 668 u32 apiexcp; 669 u32 apimask; 670 671 /* APIEXCP is cleared when read */ 672 apiexcp = __raw_readl(dev_info->vbase + REG_APIEXCP_OFFSET); 673 if ((apiexcp & CPU_EXCP_DETECTED) == 0) 674 return; 675 676 if ((apiexcp & ~cpc925_cpu_mask_disabled()) == 0) 677 return; 678 679 apimask = __raw_readl(dev_info->vbase + REG_APIMASK_OFFSET); 680 cpc925_printk(KERN_INFO, "Processor Interface Fault\n" 681 "Processor Interface register dump:\n"); 682 cpc925_printk(KERN_INFO, "APIMASK 0x%08x\n", apimask); 683 cpc925_printk(KERN_INFO, "APIEXCP 0x%08x\n", apiexcp); 684 685 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); 686 } 687 688 /******************** HT Link err device****************************/ 689 /* Enable HyperTransport Link Error detection */ 690 static void cpc925_htlink_init(struct cpc925_dev_info *dev_info) 691 { 692 u32 ht_errctrl; 693 694 ht_errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET); 695 if ((ht_errctrl & HT_ERRCTRL_ENABLE) == 0) { 696 ht_errctrl |= HT_ERRCTRL_ENABLE; 697 __raw_writel(ht_errctrl, dev_info->vbase + REG_ERRCTRL_OFFSET); 698 } 699 } 700 701 /* Disable HyperTransport Link Error detection */ 702 static void cpc925_htlink_exit(struct cpc925_dev_info *dev_info) 703 { 704 u32 ht_errctrl; 705 706 ht_errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET); 707 ht_errctrl &= ~HT_ERRCTRL_ENABLE; 708 __raw_writel(ht_errctrl, dev_info->vbase + REG_ERRCTRL_OFFSET); 709 } 710 711 /* Check for HyperTransport Link errors */ 712 static void cpc925_htlink_check(struct edac_device_ctl_info *edac_dev) 713 { 714 struct cpc925_dev_info *dev_info = edac_dev->pvt_info; 715 u32 brgctrl = __raw_readl(dev_info->vbase + REG_BRGCTRL_OFFSET); 716 u32 linkctrl = __raw_readl(dev_info->vbase + REG_LINKCTRL_OFFSET); 717 u32 errctrl = __raw_readl(dev_info->vbase + REG_ERRCTRL_OFFSET); 718 u32 linkerr = __raw_readl(dev_info->vbase + REG_LINKERR_OFFSET); 719 720 if (!((brgctrl & BRGCTRL_DETSERR) || 721 (linkctrl & HT_LINKCTRL_DETECTED) || 722 (errctrl & HT_ERRCTRL_DETECTED) || 723 (linkerr & HT_LINKERR_DETECTED))) 724 return; 725 726 cpc925_printk(KERN_INFO, "HT Link Fault\n" 727 "HT register dump:\n"); 728 cpc925_printk(KERN_INFO, "Bridge Ctrl 0x%08x\n", 729 brgctrl); 730 cpc925_printk(KERN_INFO, "Link Config Ctrl 0x%08x\n", 731 linkctrl); 732 cpc925_printk(KERN_INFO, "Error Enum and Ctrl 0x%08x\n", 733 errctrl); 734 cpc925_printk(KERN_INFO, "Link Error 0x%08x\n", 735 linkerr); 736 737 /* Clear by write 1 */ 738 if (brgctrl & BRGCTRL_DETSERR) 739 __raw_writel(BRGCTRL_DETSERR, 740 dev_info->vbase + REG_BRGCTRL_OFFSET); 741 742 if (linkctrl & HT_LINKCTRL_DETECTED) 743 __raw_writel(HT_LINKCTRL_DETECTED, 744 dev_info->vbase + REG_LINKCTRL_OFFSET); 745 746 /* Initiate Secondary Bus Reset to clear the chain failure */ 747 if (errctrl & ERRCTRL_CHN_FAL) 748 __raw_writel(BRGCTRL_SECBUSRESET, 749 dev_info->vbase + REG_BRGCTRL_OFFSET); 750 751 if (errctrl & ERRCTRL_RSP_ERR) 752 __raw_writel(ERRCTRL_RSP_ERR, 753 dev_info->vbase + REG_ERRCTRL_OFFSET); 754 755 if (linkerr & HT_LINKERR_DETECTED) 756 __raw_writel(HT_LINKERR_DETECTED, 757 dev_info->vbase + REG_LINKERR_OFFSET); 758 759 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); 760 } 761 762 static struct cpc925_dev_info cpc925_devs[] = { 763 { 764 .ctl_name = CPC925_CPU_ERR_DEV, 765 .init = cpc925_cpu_init, 766 .exit = cpc925_cpu_exit, 767 .check = cpc925_cpu_check, 768 }, 769 { 770 .ctl_name = CPC925_HT_LINK_DEV, 771 .init = cpc925_htlink_init, 772 .exit = cpc925_htlink_exit, 773 .check = cpc925_htlink_check, 774 }, 775 { } 776 }; 777 778 /* 779 * Add CPU Err detection and HyperTransport Link Err detection 780 * as common "edac_device", they have no corresponding device 781 * nodes in the Open Firmware DTB and we have to add platform 782 * devices for them. Also, they will share the MMIO with that 783 * of memory controller. 784 */ 785 static void cpc925_add_edac_devices(void __iomem *vbase) 786 { 787 struct cpc925_dev_info *dev_info; 788 789 if (!vbase) { 790 cpc925_printk(KERN_ERR, "MMIO not established yet\n"); 791 return; 792 } 793 794 for (dev_info = &cpc925_devs[0]; dev_info->init; dev_info++) { 795 dev_info->vbase = vbase; 796 dev_info->pdev = platform_device_register_simple( 797 dev_info->ctl_name, 0, NULL, 0); 798 if (IS_ERR(dev_info->pdev)) { 799 cpc925_printk(KERN_ERR, 800 "Can't register platform device for %s\n", 801 dev_info->ctl_name); 802 continue; 803 } 804 805 /* 806 * Don't have to allocate private structure but 807 * make use of cpc925_devs[] instead. 808 */ 809 dev_info->edac_idx = edac_device_alloc_index(); 810 dev_info->edac_dev = 811 edac_device_alloc_ctl_info(0, dev_info->ctl_name, 812 1, NULL, 0, 0, NULL, 0, dev_info->edac_idx); 813 if (!dev_info->edac_dev) { 814 cpc925_printk(KERN_ERR, "No memory for edac device\n"); 815 goto err1; 816 } 817 818 dev_info->edac_dev->pvt_info = dev_info; 819 dev_info->edac_dev->dev = &dev_info->pdev->dev; 820 dev_info->edac_dev->ctl_name = dev_info->ctl_name; 821 dev_info->edac_dev->mod_name = CPC925_EDAC_MOD_STR; 822 dev_info->edac_dev->dev_name = dev_name(&dev_info->pdev->dev); 823 824 if (edac_op_state == EDAC_OPSTATE_POLL) 825 dev_info->edac_dev->edac_check = dev_info->check; 826 827 if (dev_info->init) 828 dev_info->init(dev_info); 829 830 if (edac_device_add_device(dev_info->edac_dev) > 0) { 831 cpc925_printk(KERN_ERR, 832 "Unable to add edac device for %s\n", 833 dev_info->ctl_name); 834 goto err2; 835 } 836 837 edac_dbg(0, "Successfully added edac device for %s\n", 838 dev_info->ctl_name); 839 840 continue; 841 842 err2: 843 if (dev_info->exit) 844 dev_info->exit(dev_info); 845 edac_device_free_ctl_info(dev_info->edac_dev); 846 err1: 847 platform_device_unregister(dev_info->pdev); 848 } 849 } 850 851 /* 852 * Delete the common "edac_device" for CPU Err Detection 853 * and HyperTransport Link Err Detection 854 */ 855 static void cpc925_del_edac_devices(void) 856 { 857 struct cpc925_dev_info *dev_info; 858 859 for (dev_info = &cpc925_devs[0]; dev_info->init; dev_info++) { 860 if (dev_info->edac_dev) { 861 edac_device_del_device(dev_info->edac_dev->dev); 862 edac_device_free_ctl_info(dev_info->edac_dev); 863 platform_device_unregister(dev_info->pdev); 864 } 865 866 if (dev_info->exit) 867 dev_info->exit(dev_info); 868 869 edac_dbg(0, "Successfully deleted edac device for %s\n", 870 dev_info->ctl_name); 871 } 872 } 873 874 /* Convert current back-ground scrub rate into byte/sec bandwidth */ 875 static int cpc925_get_sdram_scrub_rate(struct mem_ctl_info *mci) 876 { 877 struct cpc925_mc_pdata *pdata = mci->pvt_info; 878 int bw; 879 u32 mscr; 880 u8 si; 881 882 mscr = __raw_readl(pdata->vbase + REG_MSCR_OFFSET); 883 si = (mscr & MSCR_SI_MASK) >> MSCR_SI_SHIFT; 884 885 edac_dbg(0, "Mem Scrub Ctrl Register 0x%x\n", mscr); 886 887 if (((mscr & MSCR_SCRUB_MOD_MASK) != MSCR_BACKGR_SCRUB) || 888 (si == 0)) { 889 cpc925_mc_printk(mci, KERN_INFO, "Scrub mode not enabled\n"); 890 bw = 0; 891 } else 892 bw = CPC925_SCRUB_BLOCK_SIZE * 0xFA67 / si; 893 894 return bw; 895 } 896 897 /* Return 0 for single channel; 1 for dual channel */ 898 static int cpc925_mc_get_channels(void __iomem *vbase) 899 { 900 int dual = 0; 901 u32 mbcr; 902 903 mbcr = __raw_readl(vbase + REG_MBCR_OFFSET); 904 905 /* 906 * Dual channel only when 128-bit wide physical bus 907 * and 128-bit configuration. 908 */ 909 if (((mbcr & MBCR_64BITCFG_MASK) == 0) && 910 ((mbcr & MBCR_64BITBUS_MASK) == 0)) 911 dual = 1; 912 913 edac_dbg(0, "%s channel\n", (dual > 0) ? "Dual" : "Single"); 914 915 return dual; 916 } 917 918 static int cpc925_probe(struct platform_device *pdev) 919 { 920 static int edac_mc_idx; 921 struct mem_ctl_info *mci; 922 struct edac_mc_layer layers[2]; 923 void __iomem *vbase; 924 struct cpc925_mc_pdata *pdata; 925 struct resource *r; 926 int res = 0, nr_channels; 927 928 edac_dbg(0, "%s platform device found!\n", pdev->name); 929 930 if (!devres_open_group(&pdev->dev, cpc925_probe, GFP_KERNEL)) { 931 res = -ENOMEM; 932 goto out; 933 } 934 935 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 936 if (!r) { 937 cpc925_printk(KERN_ERR, "Unable to get resource\n"); 938 res = -ENOENT; 939 goto err1; 940 } 941 942 if (!devm_request_mem_region(&pdev->dev, 943 r->start, 944 resource_size(r), 945 pdev->name)) { 946 cpc925_printk(KERN_ERR, "Unable to request mem region\n"); 947 res = -EBUSY; 948 goto err1; 949 } 950 951 vbase = devm_ioremap(&pdev->dev, r->start, resource_size(r)); 952 if (!vbase) { 953 cpc925_printk(KERN_ERR, "Unable to ioremap device\n"); 954 res = -ENOMEM; 955 goto err2; 956 } 957 958 nr_channels = cpc925_mc_get_channels(vbase) + 1; 959 960 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 961 layers[0].size = CPC925_NR_CSROWS; 962 layers[0].is_virt_csrow = true; 963 layers[1].type = EDAC_MC_LAYER_CHANNEL; 964 layers[1].size = nr_channels; 965 layers[1].is_virt_csrow = false; 966 mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, 967 sizeof(struct cpc925_mc_pdata)); 968 if (!mci) { 969 cpc925_printk(KERN_ERR, "No memory for mem_ctl_info\n"); 970 res = -ENOMEM; 971 goto err2; 972 } 973 974 pdata = mci->pvt_info; 975 pdata->vbase = vbase; 976 pdata->edac_idx = edac_mc_idx++; 977 pdata->name = pdev->name; 978 979 mci->pdev = &pdev->dev; 980 platform_set_drvdata(pdev, mci); 981 mci->dev_name = dev_name(&pdev->dev); 982 mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR; 983 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 984 mci->edac_cap = EDAC_FLAG_SECDED; 985 mci->mod_name = CPC925_EDAC_MOD_STR; 986 mci->ctl_name = pdev->name; 987 988 if (edac_op_state == EDAC_OPSTATE_POLL) 989 mci->edac_check = cpc925_mc_check; 990 991 mci->ctl_page_to_phys = NULL; 992 mci->scrub_mode = SCRUB_SW_SRC; 993 mci->set_sdram_scrub_rate = NULL; 994 mci->get_sdram_scrub_rate = cpc925_get_sdram_scrub_rate; 995 996 cpc925_init_csrows(mci); 997 998 /* Setup memory controller registers */ 999 cpc925_mc_init(mci); 1000 1001 if (edac_mc_add_mc(mci) > 0) { 1002 cpc925_mc_printk(mci, KERN_ERR, "Failed edac_mc_add_mc()\n"); 1003 goto err3; 1004 } 1005 1006 cpc925_add_edac_devices(vbase); 1007 1008 /* get this far and it's successful */ 1009 edac_dbg(0, "success\n"); 1010 1011 res = 0; 1012 goto out; 1013 1014 err3: 1015 cpc925_mc_exit(mci); 1016 edac_mc_free(mci); 1017 err2: 1018 devm_release_mem_region(&pdev->dev, r->start, resource_size(r)); 1019 err1: 1020 devres_release_group(&pdev->dev, cpc925_probe); 1021 out: 1022 return res; 1023 } 1024 1025 static int cpc925_remove(struct platform_device *pdev) 1026 { 1027 struct mem_ctl_info *mci = platform_get_drvdata(pdev); 1028 1029 /* 1030 * Delete common edac devices before edac mc, because 1031 * the former share the MMIO of the latter. 1032 */ 1033 cpc925_del_edac_devices(); 1034 cpc925_mc_exit(mci); 1035 1036 edac_mc_del_mc(&pdev->dev); 1037 edac_mc_free(mci); 1038 1039 return 0; 1040 } 1041 1042 static struct platform_driver cpc925_edac_driver = { 1043 .probe = cpc925_probe, 1044 .remove = cpc925_remove, 1045 .driver = { 1046 .name = "cpc925_edac", 1047 } 1048 }; 1049 1050 static int __init cpc925_edac_init(void) 1051 { 1052 int ret = 0; 1053 1054 printk(KERN_INFO "IBM CPC925 EDAC driver " CPC925_EDAC_REVISION "\n"); 1055 printk(KERN_INFO "\t(c) 2008 Wind River Systems, Inc\n"); 1056 1057 /* Only support POLL mode so far */ 1058 edac_op_state = EDAC_OPSTATE_POLL; 1059 1060 ret = platform_driver_register(&cpc925_edac_driver); 1061 if (ret) { 1062 printk(KERN_WARNING "Failed to register %s\n", 1063 CPC925_EDAC_MOD_STR); 1064 } 1065 1066 return ret; 1067 } 1068 1069 static void __exit cpc925_edac_exit(void) 1070 { 1071 platform_driver_unregister(&cpc925_edac_driver); 1072 } 1073 1074 module_init(cpc925_edac_init); 1075 module_exit(cpc925_edac_exit); 1076 1077 MODULE_LICENSE("GPL"); 1078 MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>"); 1079 MODULE_DESCRIPTION("IBM CPC925 Bridge and MC EDAC kernel module"); 1080