1 /* 2 * Cell MIC driver for ECC counting 3 * 4 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp. 5 * <benh@kernel.crashing.org> 6 * 7 * This file may be distributed under the terms of the 8 * GNU General Public License. 9 */ 10 #undef DEBUG 11 12 #include <linux/module.h> 13 #include <linux/init.h> 14 #include <linux/platform_device.h> 15 #include <linux/stop_machine.h> 16 #include <linux/io.h> 17 #include <asm/machdep.h> 18 #include <asm/cell-regs.h> 19 20 #include "edac_core.h" 21 22 struct cell_edac_priv 23 { 24 struct cbe_mic_tm_regs __iomem *regs; 25 int node; 26 int chanmask; 27 #ifdef DEBUG 28 u64 prev_fir; 29 #endif 30 }; 31 32 static void cell_edac_count_ce(struct mem_ctl_info *mci, int chan, u64 ar) 33 { 34 struct cell_edac_priv *priv = mci->pvt_info; 35 struct csrow_info *csrow = &mci->csrows[0]; 36 unsigned long address, pfn, offset, syndrome; 37 38 dev_dbg(mci->dev, "ECC CE err on node %d, channel %d, ar = 0x%016lx\n", 39 priv->node, chan, ar); 40 41 /* Address decoding is likely a bit bogus, to dbl check */ 42 address = (ar & 0xffffffffe0000000ul) >> 29; 43 if (priv->chanmask == 0x3) 44 address = (address << 1) | chan; 45 pfn = address >> PAGE_SHIFT; 46 offset = address & ~PAGE_MASK; 47 syndrome = (ar & 0x000000001fe00000ul) >> 21; 48 49 /* TODO: Decoding of the error addresss */ 50 edac_mc_handle_ce(mci, csrow->first_page + pfn, offset, 51 syndrome, 0, chan, ""); 52 } 53 54 static void cell_edac_count_ue(struct mem_ctl_info *mci, int chan, u64 ar) 55 { 56 struct cell_edac_priv *priv = mci->pvt_info; 57 struct csrow_info *csrow = &mci->csrows[0]; 58 unsigned long address, pfn, offset; 59 60 dev_dbg(mci->dev, "ECC UE err on node %d, channel %d, ar = 0x%016lx\n", 61 priv->node, chan, ar); 62 63 /* Address decoding is likely a bit bogus, to dbl check */ 64 address = (ar & 0xffffffffe0000000ul) >> 29; 65 if (priv->chanmask == 0x3) 66 address = (address << 1) | chan; 67 pfn = address >> PAGE_SHIFT; 68 offset = address & ~PAGE_MASK; 69 70 /* TODO: Decoding of the error addresss */ 71 edac_mc_handle_ue(mci, csrow->first_page + pfn, offset, 0, ""); 72 } 73 74 static void cell_edac_check(struct mem_ctl_info *mci) 75 { 76 struct cell_edac_priv *priv = mci->pvt_info; 77 u64 fir, addreg, clear = 0; 78 79 fir = in_be64(&priv->regs->mic_fir); 80 #ifdef DEBUG 81 if (fir != priv->prev_fir) { 82 dev_dbg(mci->dev, "fir change : 0x%016lx\n", fir); 83 priv->prev_fir = fir; 84 } 85 #endif 86 if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_SINGLE_0_ERR)) { 87 addreg = in_be64(&priv->regs->mic_df_ecc_address_0); 88 clear |= CBE_MIC_FIR_ECC_SINGLE_0_RESET; 89 cell_edac_count_ce(mci, 0, addreg); 90 } 91 if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_SINGLE_1_ERR)) { 92 addreg = in_be64(&priv->regs->mic_df_ecc_address_1); 93 clear |= CBE_MIC_FIR_ECC_SINGLE_1_RESET; 94 cell_edac_count_ce(mci, 1, addreg); 95 } 96 if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_MULTI_0_ERR)) { 97 addreg = in_be64(&priv->regs->mic_df_ecc_address_0); 98 clear |= CBE_MIC_FIR_ECC_MULTI_0_RESET; 99 cell_edac_count_ue(mci, 0, addreg); 100 } 101 if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_MULTI_1_ERR)) { 102 addreg = in_be64(&priv->regs->mic_df_ecc_address_1); 103 clear |= CBE_MIC_FIR_ECC_MULTI_1_RESET; 104 cell_edac_count_ue(mci, 1, addreg); 105 } 106 107 /* The procedure for clearing FIR bits is a bit ... weird */ 108 if (clear) { 109 fir &= ~(CBE_MIC_FIR_ECC_ERR_MASK | CBE_MIC_FIR_ECC_SET_MASK); 110 fir |= CBE_MIC_FIR_ECC_RESET_MASK; 111 fir &= ~clear; 112 out_be64(&priv->regs->mic_fir, fir); 113 (void)in_be64(&priv->regs->mic_fir); 114 115 mb(); /* sync up */ 116 #ifdef DEBUG 117 fir = in_be64(&priv->regs->mic_fir); 118 dev_dbg(mci->dev, "fir clear : 0x%016lx\n", fir); 119 #endif 120 } 121 } 122 123 static void __devinit cell_edac_init_csrows(struct mem_ctl_info *mci) 124 { 125 struct csrow_info *csrow = &mci->csrows[0]; 126 struct cell_edac_priv *priv = mci->pvt_info; 127 struct device_node *np; 128 129 for (np = NULL; 130 (np = of_find_node_by_name(np, "memory")) != NULL;) { 131 struct resource r; 132 133 /* We "know" that the Cell firmware only creates one entry 134 * in the "memory" nodes. If that changes, this code will 135 * need to be adapted. 136 */ 137 if (of_address_to_resource(np, 0, &r)) 138 continue; 139 if (of_node_to_nid(np) != priv->node) 140 continue; 141 csrow->first_page = r.start >> PAGE_SHIFT; 142 csrow->nr_pages = (r.end - r.start + 1) >> PAGE_SHIFT; 143 csrow->last_page = csrow->first_page + csrow->nr_pages - 1; 144 csrow->mtype = MEM_XDR; 145 csrow->edac_mode = EDAC_FLAG_EC | EDAC_FLAG_SECDED; 146 dev_dbg(mci->dev, 147 "Initialized on node %d, chanmask=0x%x," 148 " first_page=0x%lx, nr_pages=0x%x\n", 149 priv->node, priv->chanmask, 150 csrow->first_page, csrow->nr_pages); 151 break; 152 } 153 } 154 155 static int __devinit cell_edac_probe(struct platform_device *pdev) 156 { 157 struct cbe_mic_tm_regs __iomem *regs; 158 struct mem_ctl_info *mci; 159 struct cell_edac_priv *priv; 160 u64 reg; 161 int rc, chanmask; 162 163 regs = cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(pdev->id)); 164 if (regs == NULL) 165 return -ENODEV; 166 167 /* Get channel population */ 168 reg = in_be64(®s->mic_mnt_cfg); 169 dev_dbg(&pdev->dev, "MIC_MNT_CFG = 0x%016lx\n", reg); 170 chanmask = 0; 171 if (reg & CBE_MIC_MNT_CFG_CHAN_0_POP) 172 chanmask |= 0x1; 173 if (reg & CBE_MIC_MNT_CFG_CHAN_1_POP) 174 chanmask |= 0x2; 175 if (chanmask == 0) { 176 dev_warn(&pdev->dev, 177 "Yuck ! No channel populated ? Aborting !\n"); 178 return -ENODEV; 179 } 180 dev_dbg(&pdev->dev, "Initial FIR = 0x%016lx\n", 181 in_be64(®s->mic_fir)); 182 183 /* Allocate & init EDAC MC data structure */ 184 mci = edac_mc_alloc(sizeof(struct cell_edac_priv), 1, 185 chanmask == 3 ? 2 : 1, pdev->id); 186 if (mci == NULL) 187 return -ENOMEM; 188 priv = mci->pvt_info; 189 priv->regs = regs; 190 priv->node = pdev->id; 191 priv->chanmask = chanmask; 192 mci->dev = &pdev->dev; 193 mci->mtype_cap = MEM_FLAG_XDR; 194 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED; 195 mci->edac_cap = EDAC_FLAG_EC | EDAC_FLAG_SECDED; 196 mci->mod_name = "cell_edac"; 197 mci->ctl_name = "MIC"; 198 mci->dev_name = pdev->dev.bus_id; 199 mci->edac_check = cell_edac_check; 200 cell_edac_init_csrows(mci); 201 202 /* Register with EDAC core */ 203 rc = edac_mc_add_mc(mci); 204 if (rc) { 205 dev_err(&pdev->dev, "failed to register with EDAC core\n"); 206 edac_mc_free(mci); 207 return rc; 208 } 209 210 return 0; 211 } 212 213 static int __devexit cell_edac_remove(struct platform_device *pdev) 214 { 215 struct mem_ctl_info *mci = edac_mc_del_mc(&pdev->dev); 216 if (mci) 217 edac_mc_free(mci); 218 return 0; 219 } 220 221 static struct platform_driver cell_edac_driver = { 222 .driver = { 223 .name = "cbe-mic", 224 .owner = THIS_MODULE, 225 }, 226 .probe = cell_edac_probe, 227 .remove = cell_edac_remove, 228 }; 229 230 static int __init cell_edac_init(void) 231 { 232 /* Sanity check registers data structure */ 233 BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs, 234 mic_df_ecc_address_0) != 0xf8); 235 BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs, 236 mic_df_ecc_address_1) != 0x1b8); 237 BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs, 238 mic_df_config) != 0x218); 239 BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs, 240 mic_fir) != 0x230); 241 BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs, 242 mic_mnt_cfg) != 0x210); 243 BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs, 244 mic_exc) != 0x208); 245 246 return platform_driver_register(&cell_edac_driver); 247 } 248 249 static void __exit cell_edac_exit(void) 250 { 251 platform_driver_unregister(&cell_edac_driver); 252 } 253 254 module_init(cell_edac_init); 255 module_exit(cell_edac_exit); 256 257 MODULE_LICENSE("GPL"); 258 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>"); 259 MODULE_DESCRIPTION("ECC counting for Cell MIC"); 260