1 /* 2 * AMD64 class Memory Controller kernel module 3 * 4 * Copyright (c) 2009 SoftwareBitMaker. 5 * Copyright (c) 2009-15 Advanced Micro Devices, Inc. 6 * 7 * This file may be distributed under the terms of the 8 * GNU General Public License. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/ctype.h> 13 #include <linux/init.h> 14 #include <linux/pci.h> 15 #include <linux/pci_ids.h> 16 #include <linux/slab.h> 17 #include <linux/mmzone.h> 18 #include <linux/edac.h> 19 #include <asm/cpu_device_id.h> 20 #include <asm/msr.h> 21 #include "edac_module.h" 22 #include "mce_amd.h" 23 24 #define amd64_info(fmt, arg...) \ 25 edac_printk(KERN_INFO, "amd64", fmt, ##arg) 26 27 #define amd64_warn(fmt, arg...) \ 28 edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg) 29 30 #define amd64_err(fmt, arg...) \ 31 edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg) 32 33 #define amd64_mc_warn(mci, fmt, arg...) \ 34 edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg) 35 36 #define amd64_mc_err(mci, fmt, arg...) \ 37 edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg) 38 39 /* 40 * Throughout the comments in this code, the following terms are used: 41 * 42 * SysAddr, DramAddr, and InputAddr 43 * 44 * These terms come directly from the amd64 documentation 45 * (AMD publication #26094). They are defined as follows: 46 * 47 * SysAddr: 48 * This is a physical address generated by a CPU core or a device 49 * doing DMA. If generated by a CPU core, a SysAddr is the result of 50 * a virtual to physical address translation by the CPU core's address 51 * translation mechanism (MMU). 52 * 53 * DramAddr: 54 * A DramAddr is derived from a SysAddr by subtracting an offset that 55 * depends on which node the SysAddr maps to and whether the SysAddr 56 * is within a range affected by memory hoisting. The DRAM Base 57 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers 58 * determine which node a SysAddr maps to. 59 * 60 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr 61 * is within the range of addresses specified by this register, then 62 * a value x from the DHAR is subtracted from the SysAddr to produce a 63 * DramAddr. Here, x represents the base address for the node that 64 * the SysAddr maps to plus an offset due to memory hoisting. See 65 * section 3.4.8 and the comments in amd64_get_dram_hole_info() and 66 * sys_addr_to_dram_addr() below for more information. 67 * 68 * If the SysAddr is not affected by the DHAR then a value y is 69 * subtracted from the SysAddr to produce a DramAddr. Here, y is the 70 * base address for the node that the SysAddr maps to. See section 71 * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more 72 * information. 73 * 74 * InputAddr: 75 * A DramAddr is translated to an InputAddr before being passed to the 76 * memory controller for the node that the DramAddr is associated 77 * with. The memory controller then maps the InputAddr to a csrow. 78 * If node interleaving is not in use, then the InputAddr has the same 79 * value as the DramAddr. Otherwise, the InputAddr is produced by 80 * discarding the bits used for node interleaving from the DramAddr. 81 * See section 3.4.4 for more information. 82 * 83 * The memory controller for a given node uses its DRAM CS Base and 84 * DRAM CS Mask registers to map an InputAddr to a csrow. See 85 * sections 3.5.4 and 3.5.5 for more information. 86 */ 87 88 #define EDAC_AMD64_VERSION "3.5.0" 89 #define EDAC_MOD_STR "amd64_edac" 90 91 /* Extended Model from CPUID, for CPU Revision numbers */ 92 #define K8_REV_D 1 93 #define K8_REV_E 2 94 #define K8_REV_F 4 95 96 /* Hardware limit on ChipSelect rows per MC and processors per system */ 97 #define NUM_CHIPSELECTS 8 98 #define DRAM_RANGES 8 99 100 #define ON true 101 #define OFF false 102 103 /* 104 * PCI-defined configuration space registers 105 */ 106 #define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601 107 #define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602 108 #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b 109 #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c 110 #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571 111 #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572 112 #define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531 113 #define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532 114 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581 115 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582 116 #define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460 117 #define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466 118 119 /* 120 * Function 1 - Address Map 121 */ 122 #define DRAM_BASE_LO 0x40 123 #define DRAM_LIMIT_LO 0x44 124 125 /* 126 * F15 M30h D18F1x2[1C:00] 127 */ 128 #define DRAM_CONT_BASE 0x200 129 #define DRAM_CONT_LIMIT 0x204 130 131 /* 132 * F15 M30h D18F1x2[4C:40] 133 */ 134 #define DRAM_CONT_HIGH_OFF 0x240 135 136 #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3)) 137 #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7)) 138 #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7)) 139 140 #define DHAR 0xf0 141 #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1)) 142 #define dhar_base(pvt) ((pvt)->dhar & 0xff000000) 143 #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16) 144 145 /* NOTE: Extra mask bit vs K8 */ 146 #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16) 147 148 #define DCT_CFG_SEL 0x10C 149 150 #define DRAM_LOCAL_NODE_BASE 0x120 151 #define DRAM_LOCAL_NODE_LIM 0x124 152 153 #define DRAM_BASE_HI 0x140 154 #define DRAM_LIMIT_HI 0x144 155 156 157 /* 158 * Function 2 - DRAM controller 159 */ 160 #define DCSB0 0x40 161 #define DCSB1 0x140 162 #define DCSB_CS_ENABLE BIT(0) 163 164 #define DCSM0 0x60 165 #define DCSM1 0x160 166 167 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE) 168 169 #define DRAM_CONTROL 0x78 170 171 #define DBAM0 0x80 172 #define DBAM1 0x180 173 174 /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */ 175 #define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF) 176 177 #define DBAM_MAX_VALUE 11 178 179 #define DCLR0 0x90 180 #define DCLR1 0x190 181 #define REVE_WIDTH_128 BIT(16) 182 #define WIDTH_128 BIT(11) 183 184 #define DCHR0 0x94 185 #define DCHR1 0x194 186 #define DDR3_MODE BIT(8) 187 188 #define DCT_SEL_LO 0x110 189 #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0)) 190 #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2)) 191 192 #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4))) 193 194 #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5)) 195 #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10)) 196 197 #define SWAP_INTLV_REG 0x10c 198 199 #define DCT_SEL_HI 0x114 200 201 #define F15H_M60H_SCRCTRL 0x1C8 202 #define F17H_SCR_BASE_ADDR 0x48 203 #define F17H_SCR_LIMIT_ADDR 0x4C 204 205 /* 206 * Function 3 - Misc Control 207 */ 208 #define NBCTL 0x40 209 210 #define NBCFG 0x44 211 #define NBCFG_CHIPKILL BIT(23) 212 #define NBCFG_ECC_ENABLE BIT(22) 213 214 /* F3x48: NBSL */ 215 #define F10_NBSL_EXT_ERR_ECC 0x8 216 #define NBSL_PP_OBS 0x2 217 218 #define SCRCTRL 0x58 219 220 #define F10_ONLINE_SPARE 0xB0 221 #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1) 222 #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7) 223 224 #define F10_NB_ARRAY_ADDR 0xB8 225 #define F10_NB_ARRAY_DRAM BIT(31) 226 227 /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ 228 #define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1) 229 230 #define F10_NB_ARRAY_DATA 0xBC 231 #define F10_NB_ARR_ECC_WR_REQ BIT(17) 232 #define SET_NB_DRAM_INJECTION_WRITE(inj) \ 233 (BIT(((inj.word) & 0xF) + 20) | \ 234 F10_NB_ARR_ECC_WR_REQ | inj.bit_map) 235 #define SET_NB_DRAM_INJECTION_READ(inj) \ 236 (BIT(((inj.word) & 0xF) + 20) | \ 237 BIT(16) | inj.bit_map) 238 239 240 #define NBCAP 0xE8 241 #define NBCAP_CHIPKILL BIT(4) 242 #define NBCAP_SECDED BIT(3) 243 #define NBCAP_DCT_DUAL BIT(0) 244 245 #define EXT_NB_MCA_CFG 0x180 246 247 /* MSRs */ 248 #define MSR_MCGCTL_NBE BIT(4) 249 250 /* F17h */ 251 252 /* F0: */ 253 #define DF_DHAR 0x104 254 255 /* UMC CH register offsets */ 256 #define UMCCH_BASE_ADDR 0x0 257 #define UMCCH_ADDR_MASK 0x20 258 #define UMCCH_ADDR_CFG 0x30 259 #define UMCCH_DIMM_CFG 0x80 260 #define UMCCH_UMC_CFG 0x100 261 #define UMCCH_SDP_CTRL 0x104 262 #define UMCCH_ECC_CTRL 0x14C 263 #define UMCCH_ECC_BAD_SYMBOL 0xD90 264 #define UMCCH_UMC_CAP 0xDF0 265 #define UMCCH_UMC_CAP_HI 0xDF4 266 267 /* UMC CH bitfields */ 268 #define UMC_ECC_CHIPKILL_CAP BIT(31) 269 #define UMC_ECC_ENABLED BIT(30) 270 271 #define UMC_SDP_INIT BIT(31) 272 273 #define NUM_UMCS 2 274 275 enum amd_families { 276 K8_CPUS = 0, 277 F10_CPUS, 278 F15_CPUS, 279 F15_M30H_CPUS, 280 F15_M60H_CPUS, 281 F16_CPUS, 282 F16_M30H_CPUS, 283 F17_CPUS, 284 NUM_FAMILIES, 285 }; 286 287 /* Error injection control structure */ 288 struct error_injection { 289 u32 section; 290 u32 word; 291 u32 bit_map; 292 }; 293 294 /* low and high part of PCI config space regs */ 295 struct reg_pair { 296 u32 lo, hi; 297 }; 298 299 /* 300 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers 301 */ 302 struct dram_range { 303 struct reg_pair base; 304 struct reg_pair lim; 305 }; 306 307 /* A DCT chip selects collection */ 308 struct chip_select { 309 u32 csbases[NUM_CHIPSELECTS]; 310 u8 b_cnt; 311 312 u32 csmasks[NUM_CHIPSELECTS]; 313 u8 m_cnt; 314 }; 315 316 struct amd64_umc { 317 u32 dimm_cfg; /* DIMM Configuration reg */ 318 u32 umc_cfg; /* Configuration reg */ 319 u32 sdp_ctrl; /* SDP Control reg */ 320 u32 ecc_ctrl; /* DRAM ECC Control reg */ 321 u32 umc_cap_hi; /* Capabilities High reg */ 322 }; 323 324 struct amd64_pvt { 325 struct low_ops *ops; 326 327 /* pci_device handles which we utilize */ 328 struct pci_dev *F0, *F1, *F2, *F3, *F6; 329 330 u16 mc_node_id; /* MC index of this MC node */ 331 u8 fam; /* CPU family */ 332 u8 model; /* ... model */ 333 u8 stepping; /* ... stepping */ 334 335 int ext_model; /* extended model value of this node */ 336 int channel_count; 337 338 /* Raw registers */ 339 u32 dclr0; /* DRAM Configuration Low DCT0 reg */ 340 u32 dclr1; /* DRAM Configuration Low DCT1 reg */ 341 u32 dchr0; /* DRAM Configuration High DCT0 reg */ 342 u32 dchr1; /* DRAM Configuration High DCT1 reg */ 343 u32 nbcap; /* North Bridge Capabilities */ 344 u32 nbcfg; /* F10 North Bridge Configuration */ 345 u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */ 346 u32 dhar; /* DRAM Hoist reg */ 347 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */ 348 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ 349 350 /* one for each DCT */ 351 struct chip_select csels[2]; 352 353 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */ 354 struct dram_range ranges[DRAM_RANGES]; 355 356 u64 top_mem; /* top of memory below 4GB */ 357 u64 top_mem2; /* top of memory above 4GB */ 358 359 u32 dct_sel_lo; /* DRAM Controller Select Low */ 360 u32 dct_sel_hi; /* DRAM Controller Select High */ 361 u32 online_spare; /* On-Line spare Reg */ 362 363 /* x4 or x8 syndromes in use */ 364 u8 ecc_sym_sz; 365 366 /* place to store error injection parameters prior to issue */ 367 struct error_injection injection; 368 369 /* cache the dram_type */ 370 enum mem_type dram_type; 371 372 struct amd64_umc *umc; /* UMC registers */ 373 }; 374 375 enum err_codes { 376 DECODE_OK = 0, 377 ERR_NODE = -1, 378 ERR_CSROW = -2, 379 ERR_CHANNEL = -3, 380 ERR_SYND = -4, 381 ERR_NORM_ADDR = -5, 382 }; 383 384 struct err_info { 385 int err_code; 386 struct mem_ctl_info *src_mci; 387 int csrow; 388 int channel; 389 u16 syndrome; 390 u32 page; 391 u32 offset; 392 }; 393 394 static inline u32 get_umc_base(u8 channel) 395 { 396 /* ch0: 0x50000, ch1: 0x150000 */ 397 return 0x50000 + (!!channel << 20); 398 } 399 400 static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i) 401 { 402 u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8; 403 404 if (boot_cpu_data.x86 == 0xf) 405 return addr; 406 407 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr; 408 } 409 410 static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i) 411 { 412 u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff; 413 414 if (boot_cpu_data.x86 == 0xf) 415 return lim; 416 417 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim; 418 } 419 420 static inline u16 extract_syndrome(u64 status) 421 { 422 return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00); 423 } 424 425 static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt) 426 { 427 if (pvt->fam == 0x15 && pvt->model >= 0x30) 428 return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) | 429 ((pvt->dct_sel_lo >> 6) & 0x3); 430 431 return ((pvt)->dct_sel_lo >> 6) & 0x3; 432 } 433 /* 434 * per-node ECC settings descriptor 435 */ 436 struct ecc_settings { 437 u32 old_nbctl; 438 bool nbctl_valid; 439 440 struct flags { 441 unsigned long nb_mce_enable:1; 442 unsigned long nb_ecc_prev:1; 443 } flags; 444 }; 445 446 #ifdef CONFIG_EDAC_DEBUG 447 extern const struct attribute_group amd64_edac_dbg_group; 448 #endif 449 450 #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION 451 extern const struct attribute_group amd64_edac_inj_group; 452 #endif 453 454 /* 455 * Each of the PCI Device IDs types have their own set of hardware accessor 456 * functions and per device encoding/decoding logic. 457 */ 458 struct low_ops { 459 int (*early_channel_count) (struct amd64_pvt *pvt); 460 void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr, 461 struct err_info *); 462 int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, 463 unsigned cs_mode, int cs_mask_nr); 464 }; 465 466 struct amd64_family_type { 467 const char *ctl_name; 468 u16 f0_id, f1_id, f2_id, f6_id; 469 struct low_ops ops; 470 }; 471 472 int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, 473 u32 *val, const char *func); 474 int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, 475 u32 val, const char *func); 476 477 #define amd64_read_pci_cfg(pdev, offset, val) \ 478 __amd64_read_pci_cfg_dword(pdev, offset, val, __func__) 479 480 #define amd64_write_pci_cfg(pdev, offset, val) \ 481 __amd64_write_pci_cfg_dword(pdev, offset, val, __func__) 482 483 int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, 484 u64 *hole_offset, u64 *hole_size); 485 486 #define to_mci(k) container_of(k, struct mem_ctl_info, dev) 487 488 /* Injection helpers */ 489 static inline void disable_caches(void *dummy) 490 { 491 write_cr0(read_cr0() | X86_CR0_CD); 492 wbinvd(); 493 } 494 495 static inline void enable_caches(void *dummy) 496 { 497 write_cr0(read_cr0() & ~X86_CR0_CD); 498 } 499 500 static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i) 501 { 502 if (pvt->fam == 0x15 && pvt->model >= 0x30) { 503 u32 tmp; 504 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp); 505 return (u8) tmp & 0xF; 506 } 507 return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7; 508 } 509 510 static inline u8 dhar_valid(struct amd64_pvt *pvt) 511 { 512 if (pvt->fam == 0x15 && pvt->model >= 0x30) { 513 u32 tmp; 514 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); 515 return (tmp >> 1) & BIT(0); 516 } 517 return (pvt)->dhar & BIT(0); 518 } 519 520 static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt) 521 { 522 if (pvt->fam == 0x15 && pvt->model >= 0x30) { 523 u32 tmp; 524 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); 525 return (tmp >> 11) & 0x1FFF; 526 } 527 return (pvt)->dct_sel_lo & 0xFFFFF800; 528 } 529