1 /* 2 * AMD64 class Memory Controller kernel module 3 * 4 * Copyright (c) 2009 SoftwareBitMaker. 5 * Copyright (c) 2009-15 Advanced Micro Devices, Inc. 6 * 7 * This file may be distributed under the terms of the 8 * GNU General Public License. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/ctype.h> 13 #include <linux/init.h> 14 #include <linux/pci.h> 15 #include <linux/pci_ids.h> 16 #include <linux/slab.h> 17 #include <linux/mmzone.h> 18 #include <linux/edac.h> 19 #include <asm/cpu_device_id.h> 20 #include <asm/msr.h> 21 #include "edac_module.h" 22 #include "mce_amd.h" 23 24 #define amd64_info(fmt, arg...) \ 25 edac_printk(KERN_INFO, "amd64", fmt, ##arg) 26 27 #define amd64_warn(fmt, arg...) \ 28 edac_printk(KERN_WARNING, "amd64", "Warning: " fmt, ##arg) 29 30 #define amd64_err(fmt, arg...) \ 31 edac_printk(KERN_ERR, "amd64", "Error: " fmt, ##arg) 32 33 #define amd64_mc_warn(mci, fmt, arg...) \ 34 edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg) 35 36 #define amd64_mc_err(mci, fmt, arg...) \ 37 edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg) 38 39 /* 40 * Throughout the comments in this code, the following terms are used: 41 * 42 * SysAddr, DramAddr, and InputAddr 43 * 44 * These terms come directly from the amd64 documentation 45 * (AMD publication #26094). They are defined as follows: 46 * 47 * SysAddr: 48 * This is a physical address generated by a CPU core or a device 49 * doing DMA. If generated by a CPU core, a SysAddr is the result of 50 * a virtual to physical address translation by the CPU core's address 51 * translation mechanism (MMU). 52 * 53 * DramAddr: 54 * A DramAddr is derived from a SysAddr by subtracting an offset that 55 * depends on which node the SysAddr maps to and whether the SysAddr 56 * is within a range affected by memory hoisting. The DRAM Base 57 * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers 58 * determine which node a SysAddr maps to. 59 * 60 * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr 61 * is within the range of addresses specified by this register, then 62 * a value x from the DHAR is subtracted from the SysAddr to produce a 63 * DramAddr. Here, x represents the base address for the node that 64 * the SysAddr maps to plus an offset due to memory hoisting. See 65 * section 3.4.8 and the comments in amd64_get_dram_hole_info() and 66 * sys_addr_to_dram_addr() below for more information. 67 * 68 * If the SysAddr is not affected by the DHAR then a value y is 69 * subtracted from the SysAddr to produce a DramAddr. Here, y is the 70 * base address for the node that the SysAddr maps to. See section 71 * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more 72 * information. 73 * 74 * InputAddr: 75 * A DramAddr is translated to an InputAddr before being passed to the 76 * memory controller for the node that the DramAddr is associated 77 * with. The memory controller then maps the InputAddr to a csrow. 78 * If node interleaving is not in use, then the InputAddr has the same 79 * value as the DramAddr. Otherwise, the InputAddr is produced by 80 * discarding the bits used for node interleaving from the DramAddr. 81 * See section 3.4.4 for more information. 82 * 83 * The memory controller for a given node uses its DRAM CS Base and 84 * DRAM CS Mask registers to map an InputAddr to a csrow. See 85 * sections 3.5.4 and 3.5.5 for more information. 86 */ 87 88 #define EDAC_AMD64_VERSION "3.5.0" 89 #define EDAC_MOD_STR "amd64_edac" 90 91 /* Extended Model from CPUID, for CPU Revision numbers */ 92 #define K8_REV_D 1 93 #define K8_REV_E 2 94 #define K8_REV_F 4 95 96 /* Hardware limit on ChipSelect rows per MC and processors per system */ 97 #define NUM_CHIPSELECTS 8 98 #define DRAM_RANGES 8 99 #define NUM_CONTROLLERS 8 100 101 #define ON true 102 #define OFF false 103 104 /* 105 * PCI-defined configuration space registers 106 */ 107 #define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601 108 #define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602 109 #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F1 0x141b 110 #define PCI_DEVICE_ID_AMD_15H_M30H_NB_F2 0x141c 111 #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F1 0x1571 112 #define PCI_DEVICE_ID_AMD_15H_M60H_NB_F2 0x1572 113 #define PCI_DEVICE_ID_AMD_16H_NB_F1 0x1531 114 #define PCI_DEVICE_ID_AMD_16H_NB_F2 0x1532 115 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F1 0x1581 116 #define PCI_DEVICE_ID_AMD_16H_M30H_NB_F2 0x1582 117 #define PCI_DEVICE_ID_AMD_17H_DF_F0 0x1460 118 #define PCI_DEVICE_ID_AMD_17H_DF_F6 0x1466 119 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F0 0x15e8 120 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F6 0x15ee 121 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F0 0x1490 122 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F6 0x1496 123 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F0 0x1440 124 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446 125 #define PCI_DEVICE_ID_AMD_19H_DF_F0 0x1650 126 #define PCI_DEVICE_ID_AMD_19H_DF_F6 0x1656 127 128 /* 129 * Function 1 - Address Map 130 */ 131 #define DRAM_BASE_LO 0x40 132 #define DRAM_LIMIT_LO 0x44 133 134 /* 135 * F15 M30h D18F1x2[1C:00] 136 */ 137 #define DRAM_CONT_BASE 0x200 138 #define DRAM_CONT_LIMIT 0x204 139 140 /* 141 * F15 M30h D18F1x2[4C:40] 142 */ 143 #define DRAM_CONT_HIGH_OFF 0x240 144 145 #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3)) 146 #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7)) 147 #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7)) 148 149 #define DHAR 0xf0 150 #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1)) 151 #define dhar_base(pvt) ((pvt)->dhar & 0xff000000) 152 #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16) 153 154 /* NOTE: Extra mask bit vs K8 */ 155 #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16) 156 157 #define DCT_CFG_SEL 0x10C 158 159 #define DRAM_LOCAL_NODE_BASE 0x120 160 #define DRAM_LOCAL_NODE_LIM 0x124 161 162 #define DRAM_BASE_HI 0x140 163 #define DRAM_LIMIT_HI 0x144 164 165 166 /* 167 * Function 2 - DRAM controller 168 */ 169 #define DCSB0 0x40 170 #define DCSB1 0x140 171 #define DCSB_CS_ENABLE BIT(0) 172 173 #define DCSM0 0x60 174 #define DCSM1 0x160 175 176 #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE) 177 #define csrow_sec_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE) 178 179 #define DRAM_CONTROL 0x78 180 181 #define DBAM0 0x80 182 #define DBAM1 0x180 183 184 /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */ 185 #define DBAM_DIMM(i, reg) ((((reg) >> (4*(i)))) & 0xF) 186 187 #define DBAM_MAX_VALUE 11 188 189 #define DCLR0 0x90 190 #define DCLR1 0x190 191 #define REVE_WIDTH_128 BIT(16) 192 #define WIDTH_128 BIT(11) 193 194 #define DCHR0 0x94 195 #define DCHR1 0x194 196 #define DDR3_MODE BIT(8) 197 198 #define DCT_SEL_LO 0x110 199 #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0)) 200 #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2)) 201 202 #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4))) 203 204 #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5)) 205 #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10)) 206 207 #define SWAP_INTLV_REG 0x10c 208 209 #define DCT_SEL_HI 0x114 210 211 #define F15H_M60H_SCRCTRL 0x1C8 212 #define F17H_SCR_BASE_ADDR 0x48 213 #define F17H_SCR_LIMIT_ADDR 0x4C 214 215 /* 216 * Function 3 - Misc Control 217 */ 218 #define NBCTL 0x40 219 220 #define NBCFG 0x44 221 #define NBCFG_CHIPKILL BIT(23) 222 #define NBCFG_ECC_ENABLE BIT(22) 223 224 /* F3x48: NBSL */ 225 #define F10_NBSL_EXT_ERR_ECC 0x8 226 #define NBSL_PP_OBS 0x2 227 228 #define SCRCTRL 0x58 229 230 #define F10_ONLINE_SPARE 0xB0 231 #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1) 232 #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7) 233 234 #define F10_NB_ARRAY_ADDR 0xB8 235 #define F10_NB_ARRAY_DRAM BIT(31) 236 237 /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ 238 #define SET_NB_ARRAY_ADDR(section) (((section) & 0x3) << 1) 239 240 #define F10_NB_ARRAY_DATA 0xBC 241 #define F10_NB_ARR_ECC_WR_REQ BIT(17) 242 #define SET_NB_DRAM_INJECTION_WRITE(inj) \ 243 (BIT(((inj.word) & 0xF) + 20) | \ 244 F10_NB_ARR_ECC_WR_REQ | inj.bit_map) 245 #define SET_NB_DRAM_INJECTION_READ(inj) \ 246 (BIT(((inj.word) & 0xF) + 20) | \ 247 BIT(16) | inj.bit_map) 248 249 250 #define NBCAP 0xE8 251 #define NBCAP_CHIPKILL BIT(4) 252 #define NBCAP_SECDED BIT(3) 253 #define NBCAP_DCT_DUAL BIT(0) 254 255 #define EXT_NB_MCA_CFG 0x180 256 257 /* MSRs */ 258 #define MSR_MCGCTL_NBE BIT(4) 259 260 /* F17h */ 261 262 /* F0: */ 263 #define DF_DHAR 0x104 264 265 /* UMC CH register offsets */ 266 #define UMCCH_BASE_ADDR 0x0 267 #define UMCCH_BASE_ADDR_SEC 0x10 268 #define UMCCH_ADDR_MASK 0x20 269 #define UMCCH_ADDR_MASK_SEC 0x28 270 #define UMCCH_ADDR_CFG 0x30 271 #define UMCCH_DIMM_CFG 0x80 272 #define UMCCH_UMC_CFG 0x100 273 #define UMCCH_SDP_CTRL 0x104 274 #define UMCCH_ECC_CTRL 0x14C 275 #define UMCCH_ECC_BAD_SYMBOL 0xD90 276 #define UMCCH_UMC_CAP 0xDF0 277 #define UMCCH_UMC_CAP_HI 0xDF4 278 279 /* UMC CH bitfields */ 280 #define UMC_ECC_CHIPKILL_CAP BIT(31) 281 #define UMC_ECC_ENABLED BIT(30) 282 283 #define UMC_SDP_INIT BIT(31) 284 285 enum amd_families { 286 K8_CPUS = 0, 287 F10_CPUS, 288 F15_CPUS, 289 F15_M30H_CPUS, 290 F15_M60H_CPUS, 291 F16_CPUS, 292 F16_M30H_CPUS, 293 F17_CPUS, 294 F17_M10H_CPUS, 295 F17_M30H_CPUS, 296 F17_M70H_CPUS, 297 F19_CPUS, 298 NUM_FAMILIES, 299 }; 300 301 /* Error injection control structure */ 302 struct error_injection { 303 u32 section; 304 u32 word; 305 u32 bit_map; 306 }; 307 308 /* low and high part of PCI config space regs */ 309 struct reg_pair { 310 u32 lo, hi; 311 }; 312 313 /* 314 * See F1x[1, 0][7C:40] DRAM Base/Limit Registers 315 */ 316 struct dram_range { 317 struct reg_pair base; 318 struct reg_pair lim; 319 }; 320 321 /* A DCT chip selects collection */ 322 struct chip_select { 323 u32 csbases[NUM_CHIPSELECTS]; 324 u32 csbases_sec[NUM_CHIPSELECTS]; 325 u8 b_cnt; 326 327 u32 csmasks[NUM_CHIPSELECTS]; 328 u32 csmasks_sec[NUM_CHIPSELECTS]; 329 u8 m_cnt; 330 }; 331 332 struct amd64_umc { 333 u32 dimm_cfg; /* DIMM Configuration reg */ 334 u32 umc_cfg; /* Configuration reg */ 335 u32 sdp_ctrl; /* SDP Control reg */ 336 u32 ecc_ctrl; /* DRAM ECC Control reg */ 337 u32 umc_cap_hi; /* Capabilities High reg */ 338 }; 339 340 struct amd64_pvt { 341 struct low_ops *ops; 342 343 /* pci_device handles which we utilize */ 344 struct pci_dev *F0, *F1, *F2, *F3, *F6; 345 346 u16 mc_node_id; /* MC index of this MC node */ 347 u8 fam; /* CPU family */ 348 u8 model; /* ... model */ 349 u8 stepping; /* ... stepping */ 350 351 int ext_model; /* extended model value of this node */ 352 int channel_count; 353 354 /* Raw registers */ 355 u32 dclr0; /* DRAM Configuration Low DCT0 reg */ 356 u32 dclr1; /* DRAM Configuration Low DCT1 reg */ 357 u32 dchr0; /* DRAM Configuration High DCT0 reg */ 358 u32 dchr1; /* DRAM Configuration High DCT1 reg */ 359 u32 nbcap; /* North Bridge Capabilities */ 360 u32 nbcfg; /* F10 North Bridge Configuration */ 361 u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */ 362 u32 dhar; /* DRAM Hoist reg */ 363 u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */ 364 u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ 365 366 /* one for each DCT/UMC */ 367 struct chip_select csels[NUM_CONTROLLERS]; 368 369 /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */ 370 struct dram_range ranges[DRAM_RANGES]; 371 372 u64 top_mem; /* top of memory below 4GB */ 373 u64 top_mem2; /* top of memory above 4GB */ 374 375 u32 dct_sel_lo; /* DRAM Controller Select Low */ 376 u32 dct_sel_hi; /* DRAM Controller Select High */ 377 u32 online_spare; /* On-Line spare Reg */ 378 379 /* x4, x8, or x16 syndromes in use */ 380 u8 ecc_sym_sz; 381 382 /* place to store error injection parameters prior to issue */ 383 struct error_injection injection; 384 385 /* cache the dram_type */ 386 enum mem_type dram_type; 387 388 struct amd64_umc *umc; /* UMC registers */ 389 }; 390 391 enum err_codes { 392 DECODE_OK = 0, 393 ERR_NODE = -1, 394 ERR_CSROW = -2, 395 ERR_CHANNEL = -3, 396 ERR_SYND = -4, 397 ERR_NORM_ADDR = -5, 398 }; 399 400 struct err_info { 401 int err_code; 402 struct mem_ctl_info *src_mci; 403 int csrow; 404 int channel; 405 u16 syndrome; 406 u32 page; 407 u32 offset; 408 }; 409 410 static inline u32 get_umc_base(u8 channel) 411 { 412 /* chY: 0xY50000 */ 413 return 0x50000 + (channel << 20); 414 } 415 416 static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i) 417 { 418 u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8; 419 420 if (boot_cpu_data.x86 == 0xf) 421 return addr; 422 423 return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr; 424 } 425 426 static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i) 427 { 428 u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff; 429 430 if (boot_cpu_data.x86 == 0xf) 431 return lim; 432 433 return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim; 434 } 435 436 static inline u16 extract_syndrome(u64 status) 437 { 438 return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00); 439 } 440 441 static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt) 442 { 443 if (pvt->fam == 0x15 && pvt->model >= 0x30) 444 return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) | 445 ((pvt->dct_sel_lo >> 6) & 0x3); 446 447 return ((pvt)->dct_sel_lo >> 6) & 0x3; 448 } 449 /* 450 * per-node ECC settings descriptor 451 */ 452 struct ecc_settings { 453 u32 old_nbctl; 454 bool nbctl_valid; 455 456 struct flags { 457 unsigned long nb_mce_enable:1; 458 unsigned long nb_ecc_prev:1; 459 } flags; 460 }; 461 462 #ifdef CONFIG_EDAC_DEBUG 463 extern const struct attribute_group amd64_edac_dbg_group; 464 #endif 465 466 #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION 467 extern const struct attribute_group amd64_edac_inj_group; 468 #endif 469 470 /* 471 * Each of the PCI Device IDs types have their own set of hardware accessor 472 * functions and per device encoding/decoding logic. 473 */ 474 struct low_ops { 475 int (*early_channel_count) (struct amd64_pvt *pvt); 476 void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr, 477 struct err_info *); 478 int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, 479 unsigned cs_mode, int cs_mask_nr); 480 }; 481 482 struct amd64_family_type { 483 const char *ctl_name; 484 u16 f0_id, f1_id, f2_id, f6_id; 485 /* Maximum number of memory controllers per die/node. */ 486 u8 max_mcs; 487 struct low_ops ops; 488 }; 489 490 int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset, 491 u32 *val, const char *func); 492 int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, 493 u32 val, const char *func); 494 495 #define amd64_read_pci_cfg(pdev, offset, val) \ 496 __amd64_read_pci_cfg_dword(pdev, offset, val, __func__) 497 498 #define amd64_write_pci_cfg(pdev, offset, val) \ 499 __amd64_write_pci_cfg_dword(pdev, offset, val, __func__) 500 501 int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, 502 u64 *hole_offset, u64 *hole_size); 503 504 #define to_mci(k) container_of(k, struct mem_ctl_info, dev) 505 506 /* Injection helpers */ 507 static inline void disable_caches(void *dummy) 508 { 509 write_cr0(read_cr0() | X86_CR0_CD); 510 wbinvd(); 511 } 512 513 static inline void enable_caches(void *dummy) 514 { 515 write_cr0(read_cr0() & ~X86_CR0_CD); 516 } 517 518 static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i) 519 { 520 if (pvt->fam == 0x15 && pvt->model >= 0x30) { 521 u32 tmp; 522 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp); 523 return (u8) tmp & 0xF; 524 } 525 return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7; 526 } 527 528 static inline u8 dhar_valid(struct amd64_pvt *pvt) 529 { 530 if (pvt->fam == 0x15 && pvt->model >= 0x30) { 531 u32 tmp; 532 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); 533 return (tmp >> 1) & BIT(0); 534 } 535 return (pvt)->dhar & BIT(0); 536 } 537 538 static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt) 539 { 540 if (pvt->fam == 0x15 && pvt->model >= 0x30) { 541 u32 tmp; 542 amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp); 543 return (tmp >> 11) & 0x1FFF; 544 } 545 return (pvt)->dct_sel_lo & 0xFFFFF800; 546 } 547