12bc65418SDoug Thompson #include "amd64_edac.h" 22bc65418SDoug Thompson 32bc65418SDoug Thompson static struct edac_pci_ctl_info *amd64_ctl_pci; 42bc65418SDoug Thompson 52bc65418SDoug Thompson static int report_gart_errors; 62bc65418SDoug Thompson module_param(report_gart_errors, int, 0644); 72bc65418SDoug Thompson 82bc65418SDoug Thompson /* 92bc65418SDoug Thompson * Set by command line parameter. If BIOS has enabled the ECC, this override is 102bc65418SDoug Thompson * cleared to prevent re-enabling the hardware by this driver. 112bc65418SDoug Thompson */ 122bc65418SDoug Thompson static int ecc_enable_override; 132bc65418SDoug Thompson module_param(ecc_enable_override, int, 0644); 142bc65418SDoug Thompson 152bc65418SDoug Thompson /* Lookup table for all possible MC control instances */ 162bc65418SDoug Thompson struct amd64_pvt; 172bc65418SDoug Thompson static struct mem_ctl_info *mci_lookup[MAX_NUMNODES]; 182bc65418SDoug Thompson static struct amd64_pvt *pvt_lookup[MAX_NUMNODES]; 192bc65418SDoug Thompson 202bc65418SDoug Thompson /* 212bc65418SDoug Thompson * Memory scrubber control interface. For K8, memory scrubbing is handled by 222bc65418SDoug Thompson * hardware and can involve L2 cache, dcache as well as the main memory. With 232bc65418SDoug Thompson * F10, this is extended to L3 cache scrubbing on CPU models sporting that 242bc65418SDoug Thompson * functionality. 252bc65418SDoug Thompson * 262bc65418SDoug Thompson * This causes the "units" for the scrubbing speed to vary from 64 byte blocks 272bc65418SDoug Thompson * (dram) over to cache lines. This is nasty, so we will use bandwidth in 282bc65418SDoug Thompson * bytes/sec for the setting. 292bc65418SDoug Thompson * 302bc65418SDoug Thompson * Currently, we only do dram scrubbing. If the scrubbing is done in software on 312bc65418SDoug Thompson * other archs, we might not have access to the caches directly. 322bc65418SDoug Thompson */ 332bc65418SDoug Thompson 342bc65418SDoug Thompson /* 352bc65418SDoug Thompson * scan the scrub rate mapping table for a close or matching bandwidth value to 362bc65418SDoug Thompson * issue. If requested is too big, then use last maximum value found. 372bc65418SDoug Thompson */ 382bc65418SDoug Thompson static int amd64_search_set_scrub_rate(struct pci_dev *ctl, u32 new_bw, 392bc65418SDoug Thompson u32 min_scrubrate) 402bc65418SDoug Thompson { 412bc65418SDoug Thompson u32 scrubval; 422bc65418SDoug Thompson int i; 432bc65418SDoug Thompson 442bc65418SDoug Thompson /* 452bc65418SDoug Thompson * map the configured rate (new_bw) to a value specific to the AMD64 462bc65418SDoug Thompson * memory controller and apply to register. Search for the first 472bc65418SDoug Thompson * bandwidth entry that is greater or equal than the setting requested 482bc65418SDoug Thompson * and program that. If at last entry, turn off DRAM scrubbing. 492bc65418SDoug Thompson */ 502bc65418SDoug Thompson for (i = 0; i < ARRAY_SIZE(scrubrates); i++) { 512bc65418SDoug Thompson /* 522bc65418SDoug Thompson * skip scrub rates which aren't recommended 532bc65418SDoug Thompson * (see F10 BKDG, F3x58) 542bc65418SDoug Thompson */ 552bc65418SDoug Thompson if (scrubrates[i].scrubval < min_scrubrate) 562bc65418SDoug Thompson continue; 572bc65418SDoug Thompson 582bc65418SDoug Thompson if (scrubrates[i].bandwidth <= new_bw) 592bc65418SDoug Thompson break; 602bc65418SDoug Thompson 612bc65418SDoug Thompson /* 622bc65418SDoug Thompson * if no suitable bandwidth found, turn off DRAM scrubbing 632bc65418SDoug Thompson * entirely by falling back to the last element in the 642bc65418SDoug Thompson * scrubrates array. 652bc65418SDoug Thompson */ 662bc65418SDoug Thompson } 672bc65418SDoug Thompson 682bc65418SDoug Thompson scrubval = scrubrates[i].scrubval; 692bc65418SDoug Thompson if (scrubval) 702bc65418SDoug Thompson edac_printk(KERN_DEBUG, EDAC_MC, 712bc65418SDoug Thompson "Setting scrub rate bandwidth: %u\n", 722bc65418SDoug Thompson scrubrates[i].bandwidth); 732bc65418SDoug Thompson else 742bc65418SDoug Thompson edac_printk(KERN_DEBUG, EDAC_MC, "Turning scrubbing off.\n"); 752bc65418SDoug Thompson 762bc65418SDoug Thompson pci_write_bits32(ctl, K8_SCRCTRL, scrubval, 0x001F); 772bc65418SDoug Thompson 782bc65418SDoug Thompson return 0; 792bc65418SDoug Thompson } 802bc65418SDoug Thompson 812bc65418SDoug Thompson static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 *bandwidth) 822bc65418SDoug Thompson { 832bc65418SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 842bc65418SDoug Thompson u32 min_scrubrate = 0x0; 852bc65418SDoug Thompson 862bc65418SDoug Thompson switch (boot_cpu_data.x86) { 872bc65418SDoug Thompson case 0xf: 882bc65418SDoug Thompson min_scrubrate = K8_MIN_SCRUB_RATE_BITS; 892bc65418SDoug Thompson break; 902bc65418SDoug Thompson case 0x10: 912bc65418SDoug Thompson min_scrubrate = F10_MIN_SCRUB_RATE_BITS; 922bc65418SDoug Thompson break; 932bc65418SDoug Thompson case 0x11: 942bc65418SDoug Thompson min_scrubrate = F11_MIN_SCRUB_RATE_BITS; 952bc65418SDoug Thompson break; 962bc65418SDoug Thompson 972bc65418SDoug Thompson default: 982bc65418SDoug Thompson amd64_printk(KERN_ERR, "Unsupported family!\n"); 992bc65418SDoug Thompson break; 1002bc65418SDoug Thompson } 1012bc65418SDoug Thompson return amd64_search_set_scrub_rate(pvt->misc_f3_ctl, *bandwidth, 1022bc65418SDoug Thompson min_scrubrate); 1032bc65418SDoug Thompson } 1042bc65418SDoug Thompson 1052bc65418SDoug Thompson static int amd64_get_scrub_rate(struct mem_ctl_info *mci, u32 *bw) 1062bc65418SDoug Thompson { 1072bc65418SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 1082bc65418SDoug Thompson u32 scrubval = 0; 1092bc65418SDoug Thompson int status = -1, i, ret = 0; 1102bc65418SDoug Thompson 1112bc65418SDoug Thompson ret = pci_read_config_dword(pvt->misc_f3_ctl, K8_SCRCTRL, &scrubval); 1122bc65418SDoug Thompson if (ret) 1132bc65418SDoug Thompson debugf0("Reading K8_SCRCTRL failed\n"); 1142bc65418SDoug Thompson 1152bc65418SDoug Thompson scrubval = scrubval & 0x001F; 1162bc65418SDoug Thompson 1172bc65418SDoug Thompson edac_printk(KERN_DEBUG, EDAC_MC, 1182bc65418SDoug Thompson "pci-read, sdram scrub control value: %d \n", scrubval); 1192bc65418SDoug Thompson 1202bc65418SDoug Thompson for (i = 0; ARRAY_SIZE(scrubrates); i++) { 1212bc65418SDoug Thompson if (scrubrates[i].scrubval == scrubval) { 1222bc65418SDoug Thompson *bw = scrubrates[i].bandwidth; 1232bc65418SDoug Thompson status = 0; 1242bc65418SDoug Thompson break; 1252bc65418SDoug Thompson } 1262bc65418SDoug Thompson } 1272bc65418SDoug Thompson 1282bc65418SDoug Thompson return status; 1292bc65418SDoug Thompson } 1302bc65418SDoug Thompson 1316775763aSDoug Thompson /* Map from a CSROW entry to the mask entry that operates on it */ 1326775763aSDoug Thompson static inline u32 amd64_map_to_dcs_mask(struct amd64_pvt *pvt, int csrow) 1336775763aSDoug Thompson { 1346775763aSDoug Thompson return csrow >> (pvt->num_dcsm >> 3); 1356775763aSDoug Thompson } 1366775763aSDoug Thompson 1376775763aSDoug Thompson /* return the 'base' address the i'th CS entry of the 'dct' DRAM controller */ 1386775763aSDoug Thompson static u32 amd64_get_dct_base(struct amd64_pvt *pvt, int dct, int csrow) 1396775763aSDoug Thompson { 1406775763aSDoug Thompson if (dct == 0) 1416775763aSDoug Thompson return pvt->dcsb0[csrow]; 1426775763aSDoug Thompson else 1436775763aSDoug Thompson return pvt->dcsb1[csrow]; 1446775763aSDoug Thompson } 1456775763aSDoug Thompson 1466775763aSDoug Thompson /* 1476775763aSDoug Thompson * Return the 'mask' address the i'th CS entry. This function is needed because 1486775763aSDoug Thompson * there number of DCSM registers on Rev E and prior vs Rev F and later is 1496775763aSDoug Thompson * different. 1506775763aSDoug Thompson */ 1516775763aSDoug Thompson static u32 amd64_get_dct_mask(struct amd64_pvt *pvt, int dct, int csrow) 1526775763aSDoug Thompson { 1536775763aSDoug Thompson if (dct == 0) 1546775763aSDoug Thompson return pvt->dcsm0[amd64_map_to_dcs_mask(pvt, csrow)]; 1556775763aSDoug Thompson else 1566775763aSDoug Thompson return pvt->dcsm1[amd64_map_to_dcs_mask(pvt, csrow)]; 1576775763aSDoug Thompson } 1586775763aSDoug Thompson 1596775763aSDoug Thompson 1606775763aSDoug Thompson /* 1616775763aSDoug Thompson * In *base and *limit, pass back the full 40-bit base and limit physical 1626775763aSDoug Thompson * addresses for the node given by node_id. This information is obtained from 1636775763aSDoug Thompson * DRAM Base (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers. The 1646775763aSDoug Thompson * base and limit addresses are of type SysAddr, as defined at the start of 1656775763aSDoug Thompson * section 3.4.4 (p. 70). They are the lowest and highest physical addresses 1666775763aSDoug Thompson * in the address range they represent. 1676775763aSDoug Thompson */ 1686775763aSDoug Thompson static void amd64_get_base_and_limit(struct amd64_pvt *pvt, int node_id, 1696775763aSDoug Thompson u64 *base, u64 *limit) 1706775763aSDoug Thompson { 1716775763aSDoug Thompson *base = pvt->dram_base[node_id]; 1726775763aSDoug Thompson *limit = pvt->dram_limit[node_id]; 1736775763aSDoug Thompson } 1746775763aSDoug Thompson 1756775763aSDoug Thompson /* 1766775763aSDoug Thompson * Return 1 if the SysAddr given by sys_addr matches the base/limit associated 1776775763aSDoug Thompson * with node_id 1786775763aSDoug Thompson */ 1796775763aSDoug Thompson static int amd64_base_limit_match(struct amd64_pvt *pvt, 1806775763aSDoug Thompson u64 sys_addr, int node_id) 1816775763aSDoug Thompson { 1826775763aSDoug Thompson u64 base, limit, addr; 1836775763aSDoug Thompson 1846775763aSDoug Thompson amd64_get_base_and_limit(pvt, node_id, &base, &limit); 1856775763aSDoug Thompson 1866775763aSDoug Thompson /* The K8 treats this as a 40-bit value. However, bits 63-40 will be 1876775763aSDoug Thompson * all ones if the most significant implemented address bit is 1. 1886775763aSDoug Thompson * Here we discard bits 63-40. See section 3.4.2 of AMD publication 1896775763aSDoug Thompson * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1 1906775763aSDoug Thompson * Application Programming. 1916775763aSDoug Thompson */ 1926775763aSDoug Thompson addr = sys_addr & 0x000000ffffffffffull; 1936775763aSDoug Thompson 1946775763aSDoug Thompson return (addr >= base) && (addr <= limit); 1956775763aSDoug Thompson } 1966775763aSDoug Thompson 1976775763aSDoug Thompson /* 1986775763aSDoug Thompson * Attempt to map a SysAddr to a node. On success, return a pointer to the 1996775763aSDoug Thompson * mem_ctl_info structure for the node that the SysAddr maps to. 2006775763aSDoug Thompson * 2016775763aSDoug Thompson * On failure, return NULL. 2026775763aSDoug Thompson */ 2036775763aSDoug Thompson static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci, 2046775763aSDoug Thompson u64 sys_addr) 2056775763aSDoug Thompson { 2066775763aSDoug Thompson struct amd64_pvt *pvt; 2076775763aSDoug Thompson int node_id; 2086775763aSDoug Thompson u32 intlv_en, bits; 2096775763aSDoug Thompson 2106775763aSDoug Thompson /* 2116775763aSDoug Thompson * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section 2126775763aSDoug Thompson * 3.4.4.2) registers to map the SysAddr to a node ID. 2136775763aSDoug Thompson */ 2146775763aSDoug Thompson pvt = mci->pvt_info; 2156775763aSDoug Thompson 2166775763aSDoug Thompson /* 2176775763aSDoug Thompson * The value of this field should be the same for all DRAM Base 2186775763aSDoug Thompson * registers. Therefore we arbitrarily choose to read it from the 2196775763aSDoug Thompson * register for node 0. 2206775763aSDoug Thompson */ 2216775763aSDoug Thompson intlv_en = pvt->dram_IntlvEn[0]; 2226775763aSDoug Thompson 2236775763aSDoug Thompson if (intlv_en == 0) { 2246775763aSDoug Thompson for (node_id = 0; ; ) { 2256775763aSDoug Thompson if (amd64_base_limit_match(pvt, sys_addr, node_id)) 2266775763aSDoug Thompson break; 2276775763aSDoug Thompson 2286775763aSDoug Thompson if (++node_id >= DRAM_REG_COUNT) 2296775763aSDoug Thompson goto err_no_match; 2306775763aSDoug Thompson } 2316775763aSDoug Thompson goto found; 2326775763aSDoug Thompson } 2336775763aSDoug Thompson 2346775763aSDoug Thompson if (unlikely((intlv_en != (0x01 << 8)) && 2356775763aSDoug Thompson (intlv_en != (0x03 << 8)) && 2366775763aSDoug Thompson (intlv_en != (0x07 << 8)))) { 2376775763aSDoug Thompson amd64_printk(KERN_WARNING, "junk value of 0x%x extracted from " 2386775763aSDoug Thompson "IntlvEn field of DRAM Base Register for node 0: " 2396775763aSDoug Thompson "This probably indicates a BIOS bug.\n", intlv_en); 2406775763aSDoug Thompson return NULL; 2416775763aSDoug Thompson } 2426775763aSDoug Thompson 2436775763aSDoug Thompson bits = (((u32) sys_addr) >> 12) & intlv_en; 2446775763aSDoug Thompson 2456775763aSDoug Thompson for (node_id = 0; ; ) { 2466775763aSDoug Thompson if ((pvt->dram_limit[node_id] & intlv_en) == bits) 2476775763aSDoug Thompson break; /* intlv_sel field matches */ 2486775763aSDoug Thompson 2496775763aSDoug Thompson if (++node_id >= DRAM_REG_COUNT) 2506775763aSDoug Thompson goto err_no_match; 2516775763aSDoug Thompson } 2526775763aSDoug Thompson 2536775763aSDoug Thompson /* sanity test for sys_addr */ 2546775763aSDoug Thompson if (unlikely(!amd64_base_limit_match(pvt, sys_addr, node_id))) { 2556775763aSDoug Thompson amd64_printk(KERN_WARNING, 2566775763aSDoug Thompson "%s(): sys_addr 0x%lx falls outside base/limit " 2576775763aSDoug Thompson "address range for node %d with node interleaving " 2586775763aSDoug Thompson "enabled.\n", __func__, (unsigned long)sys_addr, 2596775763aSDoug Thompson node_id); 2606775763aSDoug Thompson return NULL; 2616775763aSDoug Thompson } 2626775763aSDoug Thompson 2636775763aSDoug Thompson found: 2646775763aSDoug Thompson return edac_mc_find(node_id); 2656775763aSDoug Thompson 2666775763aSDoug Thompson err_no_match: 2676775763aSDoug Thompson debugf2("sys_addr 0x%lx doesn't match any node\n", 2686775763aSDoug Thompson (unsigned long)sys_addr); 2696775763aSDoug Thompson 2706775763aSDoug Thompson return NULL; 2716775763aSDoug Thompson } 272e2ce7255SDoug Thompson 273e2ce7255SDoug Thompson /* 274e2ce7255SDoug Thompson * Extract the DRAM CS base address from selected csrow register. 275e2ce7255SDoug Thompson */ 276e2ce7255SDoug Thompson static u64 base_from_dct_base(struct amd64_pvt *pvt, int csrow) 277e2ce7255SDoug Thompson { 278e2ce7255SDoug Thompson return ((u64) (amd64_get_dct_base(pvt, 0, csrow) & pvt->dcsb_base)) << 279e2ce7255SDoug Thompson pvt->dcs_shift; 280e2ce7255SDoug Thompson } 281e2ce7255SDoug Thompson 282e2ce7255SDoug Thompson /* 283e2ce7255SDoug Thompson * Extract the mask from the dcsb0[csrow] entry in a CPU revision-specific way. 284e2ce7255SDoug Thompson */ 285e2ce7255SDoug Thompson static u64 mask_from_dct_mask(struct amd64_pvt *pvt, int csrow) 286e2ce7255SDoug Thompson { 287e2ce7255SDoug Thompson u64 dcsm_bits, other_bits; 288e2ce7255SDoug Thompson u64 mask; 289e2ce7255SDoug Thompson 290e2ce7255SDoug Thompson /* Extract bits from DRAM CS Mask. */ 291e2ce7255SDoug Thompson dcsm_bits = amd64_get_dct_mask(pvt, 0, csrow) & pvt->dcsm_mask; 292e2ce7255SDoug Thompson 293e2ce7255SDoug Thompson other_bits = pvt->dcsm_mask; 294e2ce7255SDoug Thompson other_bits = ~(other_bits << pvt->dcs_shift); 295e2ce7255SDoug Thompson 296e2ce7255SDoug Thompson /* 297e2ce7255SDoug Thompson * The extracted bits from DCSM belong in the spaces represented by 298e2ce7255SDoug Thompson * the cleared bits in other_bits. 299e2ce7255SDoug Thompson */ 300e2ce7255SDoug Thompson mask = (dcsm_bits << pvt->dcs_shift) | other_bits; 301e2ce7255SDoug Thompson 302e2ce7255SDoug Thompson return mask; 303e2ce7255SDoug Thompson } 304e2ce7255SDoug Thompson 305e2ce7255SDoug Thompson /* 306e2ce7255SDoug Thompson * @input_addr is an InputAddr associated with the node given by mci. Return the 307e2ce7255SDoug Thompson * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr). 308e2ce7255SDoug Thompson */ 309e2ce7255SDoug Thompson static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr) 310e2ce7255SDoug Thompson { 311e2ce7255SDoug Thompson struct amd64_pvt *pvt; 312e2ce7255SDoug Thompson int csrow; 313e2ce7255SDoug Thompson u64 base, mask; 314e2ce7255SDoug Thompson 315e2ce7255SDoug Thompson pvt = mci->pvt_info; 316e2ce7255SDoug Thompson 317e2ce7255SDoug Thompson /* 318e2ce7255SDoug Thompson * Here we use the DRAM CS Base and DRAM CS Mask registers. For each CS 319e2ce7255SDoug Thompson * base/mask register pair, test the condition shown near the start of 320e2ce7255SDoug Thompson * section 3.5.4 (p. 84, BKDG #26094, K8, revA-E). 321e2ce7255SDoug Thompson */ 322e2ce7255SDoug Thompson for (csrow = 0; csrow < CHIPSELECT_COUNT; csrow++) { 323e2ce7255SDoug Thompson 324e2ce7255SDoug Thompson /* This DRAM chip select is disabled on this node */ 325e2ce7255SDoug Thompson if ((pvt->dcsb0[csrow] & K8_DCSB_CS_ENABLE) == 0) 326e2ce7255SDoug Thompson continue; 327e2ce7255SDoug Thompson 328e2ce7255SDoug Thompson base = base_from_dct_base(pvt, csrow); 329e2ce7255SDoug Thompson mask = ~mask_from_dct_mask(pvt, csrow); 330e2ce7255SDoug Thompson 331e2ce7255SDoug Thompson if ((input_addr & mask) == (base & mask)) { 332e2ce7255SDoug Thompson debugf2("InputAddr 0x%lx matches csrow %d (node %d)\n", 333e2ce7255SDoug Thompson (unsigned long)input_addr, csrow, 334e2ce7255SDoug Thompson pvt->mc_node_id); 335e2ce7255SDoug Thompson 336e2ce7255SDoug Thompson return csrow; 337e2ce7255SDoug Thompson } 338e2ce7255SDoug Thompson } 339e2ce7255SDoug Thompson 340e2ce7255SDoug Thompson debugf2("no matching csrow for InputAddr 0x%lx (MC node %d)\n", 341e2ce7255SDoug Thompson (unsigned long)input_addr, pvt->mc_node_id); 342e2ce7255SDoug Thompson 343e2ce7255SDoug Thompson return -1; 344e2ce7255SDoug Thompson } 345e2ce7255SDoug Thompson 346e2ce7255SDoug Thompson /* 347e2ce7255SDoug Thompson * Return the base value defined by the DRAM Base register for the node 348e2ce7255SDoug Thompson * represented by mci. This function returns the full 40-bit value despite the 349e2ce7255SDoug Thompson * fact that the register only stores bits 39-24 of the value. See section 350e2ce7255SDoug Thompson * 3.4.4.1 (BKDG #26094, K8, revA-E) 351e2ce7255SDoug Thompson */ 352e2ce7255SDoug Thompson static inline u64 get_dram_base(struct mem_ctl_info *mci) 353e2ce7255SDoug Thompson { 354e2ce7255SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 355e2ce7255SDoug Thompson 356e2ce7255SDoug Thompson return pvt->dram_base[pvt->mc_node_id]; 357e2ce7255SDoug Thompson } 358e2ce7255SDoug Thompson 359e2ce7255SDoug Thompson /* 360e2ce7255SDoug Thompson * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094) 361e2ce7255SDoug Thompson * for the node represented by mci. Info is passed back in *hole_base, 362e2ce7255SDoug Thompson * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if 363e2ce7255SDoug Thompson * info is invalid. Info may be invalid for either of the following reasons: 364e2ce7255SDoug Thompson * 365e2ce7255SDoug Thompson * - The revision of the node is not E or greater. In this case, the DRAM Hole 366e2ce7255SDoug Thompson * Address Register does not exist. 367e2ce7255SDoug Thompson * 368e2ce7255SDoug Thompson * - The DramHoleValid bit is cleared in the DRAM Hole Address Register, 369e2ce7255SDoug Thompson * indicating that its contents are not valid. 370e2ce7255SDoug Thompson * 371e2ce7255SDoug Thompson * The values passed back in *hole_base, *hole_offset, and *hole_size are 372e2ce7255SDoug Thompson * complete 32-bit values despite the fact that the bitfields in the DHAR 373e2ce7255SDoug Thompson * only represent bits 31-24 of the base and offset values. 374e2ce7255SDoug Thompson */ 375e2ce7255SDoug Thompson int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, 376e2ce7255SDoug Thompson u64 *hole_offset, u64 *hole_size) 377e2ce7255SDoug Thompson { 378e2ce7255SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 379e2ce7255SDoug Thompson u64 base; 380e2ce7255SDoug Thompson 381e2ce7255SDoug Thompson /* only revE and later have the DRAM Hole Address Register */ 382e2ce7255SDoug Thompson if (boot_cpu_data.x86 == 0xf && pvt->ext_model < OPTERON_CPU_REV_E) { 383e2ce7255SDoug Thompson debugf1(" revision %d for node %d does not support DHAR\n", 384e2ce7255SDoug Thompson pvt->ext_model, pvt->mc_node_id); 385e2ce7255SDoug Thompson return 1; 386e2ce7255SDoug Thompson } 387e2ce7255SDoug Thompson 388e2ce7255SDoug Thompson /* only valid for Fam10h */ 389e2ce7255SDoug Thompson if (boot_cpu_data.x86 == 0x10 && 390e2ce7255SDoug Thompson (pvt->dhar & F10_DRAM_MEM_HOIST_VALID) == 0) { 391e2ce7255SDoug Thompson debugf1(" Dram Memory Hoisting is DISABLED on this system\n"); 392e2ce7255SDoug Thompson return 1; 393e2ce7255SDoug Thompson } 394e2ce7255SDoug Thompson 395e2ce7255SDoug Thompson if ((pvt->dhar & DHAR_VALID) == 0) { 396e2ce7255SDoug Thompson debugf1(" Dram Memory Hoisting is DISABLED on this node %d\n", 397e2ce7255SDoug Thompson pvt->mc_node_id); 398e2ce7255SDoug Thompson return 1; 399e2ce7255SDoug Thompson } 400e2ce7255SDoug Thompson 401e2ce7255SDoug Thompson /* This node has Memory Hoisting */ 402e2ce7255SDoug Thompson 403e2ce7255SDoug Thompson /* +------------------+--------------------+--------------------+----- 404e2ce7255SDoug Thompson * | memory | DRAM hole | relocated | 405e2ce7255SDoug Thompson * | [0, (x - 1)] | [x, 0xffffffff] | addresses from | 406e2ce7255SDoug Thompson * | | | DRAM hole | 407e2ce7255SDoug Thompson * | | | [0x100000000, | 408e2ce7255SDoug Thompson * | | | (0x100000000+ | 409e2ce7255SDoug Thompson * | | | (0xffffffff-x))] | 410e2ce7255SDoug Thompson * +------------------+--------------------+--------------------+----- 411e2ce7255SDoug Thompson * 412e2ce7255SDoug Thompson * Above is a diagram of physical memory showing the DRAM hole and the 413e2ce7255SDoug Thompson * relocated addresses from the DRAM hole. As shown, the DRAM hole 414e2ce7255SDoug Thompson * starts at address x (the base address) and extends through address 415e2ce7255SDoug Thompson * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the 416e2ce7255SDoug Thompson * addresses in the hole so that they start at 0x100000000. 417e2ce7255SDoug Thompson */ 418e2ce7255SDoug Thompson 419e2ce7255SDoug Thompson base = dhar_base(pvt->dhar); 420e2ce7255SDoug Thompson 421e2ce7255SDoug Thompson *hole_base = base; 422e2ce7255SDoug Thompson *hole_size = (0x1ull << 32) - base; 423e2ce7255SDoug Thompson 424e2ce7255SDoug Thompson if (boot_cpu_data.x86 > 0xf) 425e2ce7255SDoug Thompson *hole_offset = f10_dhar_offset(pvt->dhar); 426e2ce7255SDoug Thompson else 427e2ce7255SDoug Thompson *hole_offset = k8_dhar_offset(pvt->dhar); 428e2ce7255SDoug Thompson 429e2ce7255SDoug Thompson debugf1(" DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n", 430e2ce7255SDoug Thompson pvt->mc_node_id, (unsigned long)*hole_base, 431e2ce7255SDoug Thompson (unsigned long)*hole_offset, (unsigned long)*hole_size); 432e2ce7255SDoug Thompson 433e2ce7255SDoug Thompson return 0; 434e2ce7255SDoug Thompson } 435e2ce7255SDoug Thompson EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info); 436e2ce7255SDoug Thompson 43793c2df58SDoug Thompson /* 43893c2df58SDoug Thompson * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is 43993c2df58SDoug Thompson * assumed that sys_addr maps to the node given by mci. 44093c2df58SDoug Thompson * 44193c2df58SDoug Thompson * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section 44293c2df58SDoug Thompson * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a 44393c2df58SDoug Thompson * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled, 44493c2df58SDoug Thompson * then it is also involved in translating a SysAddr to a DramAddr. Sections 44593c2df58SDoug Thompson * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting. 44693c2df58SDoug Thompson * These parts of the documentation are unclear. I interpret them as follows: 44793c2df58SDoug Thompson * 44893c2df58SDoug Thompson * When node n receives a SysAddr, it processes the SysAddr as follows: 44993c2df58SDoug Thompson * 45093c2df58SDoug Thompson * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM 45193c2df58SDoug Thompson * Limit registers for node n. If the SysAddr is not within the range 45293c2df58SDoug Thompson * specified by the base and limit values, then node n ignores the Sysaddr 45393c2df58SDoug Thompson * (since it does not map to node n). Otherwise continue to step 2 below. 45493c2df58SDoug Thompson * 45593c2df58SDoug Thompson * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is 45693c2df58SDoug Thompson * disabled so skip to step 3 below. Otherwise see if the SysAddr is within 45793c2df58SDoug Thompson * the range of relocated addresses (starting at 0x100000000) from the DRAM 45893c2df58SDoug Thompson * hole. If not, skip to step 3 below. Else get the value of the 45993c2df58SDoug Thompson * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the 46093c2df58SDoug Thompson * offset defined by this value from the SysAddr. 46193c2df58SDoug Thompson * 46293c2df58SDoug Thompson * 3. Obtain the base address for node n from the DRAMBase field of the DRAM 46393c2df58SDoug Thompson * Base register for node n. To obtain the DramAddr, subtract the base 46493c2df58SDoug Thompson * address from the SysAddr, as shown near the start of section 3.4.4 (p.70). 46593c2df58SDoug Thompson */ 46693c2df58SDoug Thompson static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr) 46793c2df58SDoug Thompson { 46893c2df58SDoug Thompson u64 dram_base, hole_base, hole_offset, hole_size, dram_addr; 46993c2df58SDoug Thompson int ret = 0; 47093c2df58SDoug Thompson 47193c2df58SDoug Thompson dram_base = get_dram_base(mci); 47293c2df58SDoug Thompson 47393c2df58SDoug Thompson ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, 47493c2df58SDoug Thompson &hole_size); 47593c2df58SDoug Thompson if (!ret) { 47693c2df58SDoug Thompson if ((sys_addr >= (1ull << 32)) && 47793c2df58SDoug Thompson (sys_addr < ((1ull << 32) + hole_size))) { 47893c2df58SDoug Thompson /* use DHAR to translate SysAddr to DramAddr */ 47993c2df58SDoug Thompson dram_addr = sys_addr - hole_offset; 48093c2df58SDoug Thompson 48193c2df58SDoug Thompson debugf2("using DHAR to translate SysAddr 0x%lx to " 48293c2df58SDoug Thompson "DramAddr 0x%lx\n", 48393c2df58SDoug Thompson (unsigned long)sys_addr, 48493c2df58SDoug Thompson (unsigned long)dram_addr); 48593c2df58SDoug Thompson 48693c2df58SDoug Thompson return dram_addr; 48793c2df58SDoug Thompson } 48893c2df58SDoug Thompson } 48993c2df58SDoug Thompson 49093c2df58SDoug Thompson /* 49193c2df58SDoug Thompson * Translate the SysAddr to a DramAddr as shown near the start of 49293c2df58SDoug Thompson * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8 49393c2df58SDoug Thompson * only deals with 40-bit values. Therefore we discard bits 63-40 of 49493c2df58SDoug Thompson * sys_addr below. If bit 39 of sys_addr is 1 then the bits we 49593c2df58SDoug Thompson * discard are all 1s. Otherwise the bits we discard are all 0s. See 49693c2df58SDoug Thompson * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture 49793c2df58SDoug Thompson * Programmer's Manual Volume 1 Application Programming. 49893c2df58SDoug Thompson */ 49993c2df58SDoug Thompson dram_addr = (sys_addr & 0xffffffffffull) - dram_base; 50093c2df58SDoug Thompson 50193c2df58SDoug Thompson debugf2("using DRAM Base register to translate SysAddr 0x%lx to " 50293c2df58SDoug Thompson "DramAddr 0x%lx\n", (unsigned long)sys_addr, 50393c2df58SDoug Thompson (unsigned long)dram_addr); 50493c2df58SDoug Thompson return dram_addr; 50593c2df58SDoug Thompson } 50693c2df58SDoug Thompson 50793c2df58SDoug Thompson /* 50893c2df58SDoug Thompson * @intlv_en is the value of the IntlvEn field from a DRAM Base register 50993c2df58SDoug Thompson * (section 3.4.4.1). Return the number of bits from a SysAddr that are used 51093c2df58SDoug Thompson * for node interleaving. 51193c2df58SDoug Thompson */ 51293c2df58SDoug Thompson static int num_node_interleave_bits(unsigned intlv_en) 51393c2df58SDoug Thompson { 51493c2df58SDoug Thompson static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 }; 51593c2df58SDoug Thompson int n; 51693c2df58SDoug Thompson 51793c2df58SDoug Thompson BUG_ON(intlv_en > 7); 51893c2df58SDoug Thompson n = intlv_shift_table[intlv_en]; 51993c2df58SDoug Thompson return n; 52093c2df58SDoug Thompson } 52193c2df58SDoug Thompson 52293c2df58SDoug Thompson /* Translate the DramAddr given by @dram_addr to an InputAddr. */ 52393c2df58SDoug Thompson static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr) 52493c2df58SDoug Thompson { 52593c2df58SDoug Thompson struct amd64_pvt *pvt; 52693c2df58SDoug Thompson int intlv_shift; 52793c2df58SDoug Thompson u64 input_addr; 52893c2df58SDoug Thompson 52993c2df58SDoug Thompson pvt = mci->pvt_info; 53093c2df58SDoug Thompson 53193c2df58SDoug Thompson /* 53293c2df58SDoug Thompson * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) 53393c2df58SDoug Thompson * concerning translating a DramAddr to an InputAddr. 53493c2df58SDoug Thompson */ 53593c2df58SDoug Thompson intlv_shift = num_node_interleave_bits(pvt->dram_IntlvEn[0]); 53693c2df58SDoug Thompson input_addr = ((dram_addr >> intlv_shift) & 0xffffff000ull) + 53793c2df58SDoug Thompson (dram_addr & 0xfff); 53893c2df58SDoug Thompson 53993c2df58SDoug Thompson debugf2(" Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n", 54093c2df58SDoug Thompson intlv_shift, (unsigned long)dram_addr, 54193c2df58SDoug Thompson (unsigned long)input_addr); 54293c2df58SDoug Thompson 54393c2df58SDoug Thompson return input_addr; 54493c2df58SDoug Thompson } 54593c2df58SDoug Thompson 54693c2df58SDoug Thompson /* 54793c2df58SDoug Thompson * Translate the SysAddr represented by @sys_addr to an InputAddr. It is 54893c2df58SDoug Thompson * assumed that @sys_addr maps to the node given by mci. 54993c2df58SDoug Thompson */ 55093c2df58SDoug Thompson static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr) 55193c2df58SDoug Thompson { 55293c2df58SDoug Thompson u64 input_addr; 55393c2df58SDoug Thompson 55493c2df58SDoug Thompson input_addr = 55593c2df58SDoug Thompson dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr)); 55693c2df58SDoug Thompson 55793c2df58SDoug Thompson debugf2("SysAdddr 0x%lx translates to InputAddr 0x%lx\n", 55893c2df58SDoug Thompson (unsigned long)sys_addr, (unsigned long)input_addr); 55993c2df58SDoug Thompson 56093c2df58SDoug Thompson return input_addr; 56193c2df58SDoug Thompson } 56293c2df58SDoug Thompson 56393c2df58SDoug Thompson 56493c2df58SDoug Thompson /* 56593c2df58SDoug Thompson * @input_addr is an InputAddr associated with the node represented by mci. 56693c2df58SDoug Thompson * Translate @input_addr to a DramAddr and return the result. 56793c2df58SDoug Thompson */ 56893c2df58SDoug Thompson static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr) 56993c2df58SDoug Thompson { 57093c2df58SDoug Thompson struct amd64_pvt *pvt; 57193c2df58SDoug Thompson int node_id, intlv_shift; 57293c2df58SDoug Thompson u64 bits, dram_addr; 57393c2df58SDoug Thompson u32 intlv_sel; 57493c2df58SDoug Thompson 57593c2df58SDoug Thompson /* 57693c2df58SDoug Thompson * Near the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) 57793c2df58SDoug Thompson * shows how to translate a DramAddr to an InputAddr. Here we reverse 57893c2df58SDoug Thompson * this procedure. When translating from a DramAddr to an InputAddr, the 57993c2df58SDoug Thompson * bits used for node interleaving are discarded. Here we recover these 58093c2df58SDoug Thompson * bits from the IntlvSel field of the DRAM Limit register (section 58193c2df58SDoug Thompson * 3.4.4.2) for the node that input_addr is associated with. 58293c2df58SDoug Thompson */ 58393c2df58SDoug Thompson pvt = mci->pvt_info; 58493c2df58SDoug Thompson node_id = pvt->mc_node_id; 58593c2df58SDoug Thompson BUG_ON((node_id < 0) || (node_id > 7)); 58693c2df58SDoug Thompson 58793c2df58SDoug Thompson intlv_shift = num_node_interleave_bits(pvt->dram_IntlvEn[0]); 58893c2df58SDoug Thompson 58993c2df58SDoug Thompson if (intlv_shift == 0) { 59093c2df58SDoug Thompson debugf1(" InputAddr 0x%lx translates to DramAddr of " 59193c2df58SDoug Thompson "same value\n", (unsigned long)input_addr); 59293c2df58SDoug Thompson 59393c2df58SDoug Thompson return input_addr; 59493c2df58SDoug Thompson } 59593c2df58SDoug Thompson 59693c2df58SDoug Thompson bits = ((input_addr & 0xffffff000ull) << intlv_shift) + 59793c2df58SDoug Thompson (input_addr & 0xfff); 59893c2df58SDoug Thompson 59993c2df58SDoug Thompson intlv_sel = pvt->dram_IntlvSel[node_id] & ((1 << intlv_shift) - 1); 60093c2df58SDoug Thompson dram_addr = bits + (intlv_sel << 12); 60193c2df58SDoug Thompson 60293c2df58SDoug Thompson debugf1("InputAddr 0x%lx translates to DramAddr 0x%lx " 60393c2df58SDoug Thompson "(%d node interleave bits)\n", (unsigned long)input_addr, 60493c2df58SDoug Thompson (unsigned long)dram_addr, intlv_shift); 60593c2df58SDoug Thompson 60693c2df58SDoug Thompson return dram_addr; 60793c2df58SDoug Thompson } 60893c2df58SDoug Thompson 60993c2df58SDoug Thompson /* 61093c2df58SDoug Thompson * @dram_addr is a DramAddr that maps to the node represented by mci. Convert 61193c2df58SDoug Thompson * @dram_addr to a SysAddr. 61293c2df58SDoug Thompson */ 61393c2df58SDoug Thompson static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr) 61493c2df58SDoug Thompson { 61593c2df58SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 61693c2df58SDoug Thompson u64 hole_base, hole_offset, hole_size, base, limit, sys_addr; 61793c2df58SDoug Thompson int ret = 0; 61893c2df58SDoug Thompson 61993c2df58SDoug Thompson ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, 62093c2df58SDoug Thompson &hole_size); 62193c2df58SDoug Thompson if (!ret) { 62293c2df58SDoug Thompson if ((dram_addr >= hole_base) && 62393c2df58SDoug Thompson (dram_addr < (hole_base + hole_size))) { 62493c2df58SDoug Thompson sys_addr = dram_addr + hole_offset; 62593c2df58SDoug Thompson 62693c2df58SDoug Thompson debugf1("using DHAR to translate DramAddr 0x%lx to " 62793c2df58SDoug Thompson "SysAddr 0x%lx\n", (unsigned long)dram_addr, 62893c2df58SDoug Thompson (unsigned long)sys_addr); 62993c2df58SDoug Thompson 63093c2df58SDoug Thompson return sys_addr; 63193c2df58SDoug Thompson } 63293c2df58SDoug Thompson } 63393c2df58SDoug Thompson 63493c2df58SDoug Thompson amd64_get_base_and_limit(pvt, pvt->mc_node_id, &base, &limit); 63593c2df58SDoug Thompson sys_addr = dram_addr + base; 63693c2df58SDoug Thompson 63793c2df58SDoug Thompson /* 63893c2df58SDoug Thompson * The sys_addr we have computed up to this point is a 40-bit value 63993c2df58SDoug Thompson * because the k8 deals with 40-bit values. However, the value we are 64093c2df58SDoug Thompson * supposed to return is a full 64-bit physical address. The AMD 64193c2df58SDoug Thompson * x86-64 architecture specifies that the most significant implemented 64293c2df58SDoug Thompson * address bit through bit 63 of a physical address must be either all 64393c2df58SDoug Thompson * 0s or all 1s. Therefore we sign-extend the 40-bit sys_addr to a 64493c2df58SDoug Thompson * 64-bit value below. See section 3.4.2 of AMD publication 24592: 64593c2df58SDoug Thompson * AMD x86-64 Architecture Programmer's Manual Volume 1 Application 64693c2df58SDoug Thompson * Programming. 64793c2df58SDoug Thompson */ 64893c2df58SDoug Thompson sys_addr |= ~((sys_addr & (1ull << 39)) - 1); 64993c2df58SDoug Thompson 65093c2df58SDoug Thompson debugf1(" Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n", 65193c2df58SDoug Thompson pvt->mc_node_id, (unsigned long)dram_addr, 65293c2df58SDoug Thompson (unsigned long)sys_addr); 65393c2df58SDoug Thompson 65493c2df58SDoug Thompson return sys_addr; 65593c2df58SDoug Thompson } 65693c2df58SDoug Thompson 65793c2df58SDoug Thompson /* 65893c2df58SDoug Thompson * @input_addr is an InputAddr associated with the node given by mci. Translate 65993c2df58SDoug Thompson * @input_addr to a SysAddr. 66093c2df58SDoug Thompson */ 66193c2df58SDoug Thompson static inline u64 input_addr_to_sys_addr(struct mem_ctl_info *mci, 66293c2df58SDoug Thompson u64 input_addr) 66393c2df58SDoug Thompson { 66493c2df58SDoug Thompson return dram_addr_to_sys_addr(mci, 66593c2df58SDoug Thompson input_addr_to_dram_addr(mci, input_addr)); 66693c2df58SDoug Thompson } 66793c2df58SDoug Thompson 66893c2df58SDoug Thompson /* 66993c2df58SDoug Thompson * Find the minimum and maximum InputAddr values that map to the given @csrow. 67093c2df58SDoug Thompson * Pass back these values in *input_addr_min and *input_addr_max. 67193c2df58SDoug Thompson */ 67293c2df58SDoug Thompson static void find_csrow_limits(struct mem_ctl_info *mci, int csrow, 67393c2df58SDoug Thompson u64 *input_addr_min, u64 *input_addr_max) 67493c2df58SDoug Thompson { 67593c2df58SDoug Thompson struct amd64_pvt *pvt; 67693c2df58SDoug Thompson u64 base, mask; 67793c2df58SDoug Thompson 67893c2df58SDoug Thompson pvt = mci->pvt_info; 67993c2df58SDoug Thompson BUG_ON((csrow < 0) || (csrow >= CHIPSELECT_COUNT)); 68093c2df58SDoug Thompson 68193c2df58SDoug Thompson base = base_from_dct_base(pvt, csrow); 68293c2df58SDoug Thompson mask = mask_from_dct_mask(pvt, csrow); 68393c2df58SDoug Thompson 68493c2df58SDoug Thompson *input_addr_min = base & ~mask; 68593c2df58SDoug Thompson *input_addr_max = base | mask | pvt->dcs_mask_notused; 68693c2df58SDoug Thompson } 68793c2df58SDoug Thompson 68893c2df58SDoug Thompson /* 68993c2df58SDoug Thompson * Extract error address from MCA NB Address Low (section 3.6.4.5) and MCA NB 69093c2df58SDoug Thompson * Address High (section 3.6.4.6) register values and return the result. Address 69193c2df58SDoug Thompson * is located in the info structure (nbeah and nbeal), the encoding is device 69293c2df58SDoug Thompson * specific. 69393c2df58SDoug Thompson */ 69493c2df58SDoug Thompson static u64 extract_error_address(struct mem_ctl_info *mci, 69593c2df58SDoug Thompson struct amd64_error_info_regs *info) 69693c2df58SDoug Thompson { 69793c2df58SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 69893c2df58SDoug Thompson 69993c2df58SDoug Thompson return pvt->ops->get_error_address(mci, info); 70093c2df58SDoug Thompson } 70193c2df58SDoug Thompson 70293c2df58SDoug Thompson 70393c2df58SDoug Thompson /* Map the Error address to a PAGE and PAGE OFFSET. */ 70493c2df58SDoug Thompson static inline void error_address_to_page_and_offset(u64 error_address, 70593c2df58SDoug Thompson u32 *page, u32 *offset) 70693c2df58SDoug Thompson { 70793c2df58SDoug Thompson *page = (u32) (error_address >> PAGE_SHIFT); 70893c2df58SDoug Thompson *offset = ((u32) error_address) & ~PAGE_MASK; 70993c2df58SDoug Thompson } 71093c2df58SDoug Thompson 71193c2df58SDoug Thompson /* 71293c2df58SDoug Thompson * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address 71393c2df58SDoug Thompson * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers 71493c2df58SDoug Thompson * of a node that detected an ECC memory error. mci represents the node that 71593c2df58SDoug Thompson * the error address maps to (possibly different from the node that detected 71693c2df58SDoug Thompson * the error). Return the number of the csrow that sys_addr maps to, or -1 on 71793c2df58SDoug Thompson * error. 71893c2df58SDoug Thompson */ 71993c2df58SDoug Thompson static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) 72093c2df58SDoug Thompson { 72193c2df58SDoug Thompson int csrow; 72293c2df58SDoug Thompson 72393c2df58SDoug Thompson csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr)); 72493c2df58SDoug Thompson 72593c2df58SDoug Thompson if (csrow == -1) 72693c2df58SDoug Thompson amd64_mc_printk(mci, KERN_ERR, 72793c2df58SDoug Thompson "Failed to translate InputAddr to csrow for " 72893c2df58SDoug Thompson "address 0x%lx\n", (unsigned long)sys_addr); 72993c2df58SDoug Thompson return csrow; 73093c2df58SDoug Thompson } 731e2ce7255SDoug Thompson 7322da11654SDoug Thompson static int get_channel_from_ecc_syndrome(unsigned short syndrome); 7332da11654SDoug Thompson 7342da11654SDoug Thompson static void amd64_cpu_display_info(struct amd64_pvt *pvt) 7352da11654SDoug Thompson { 7362da11654SDoug Thompson if (boot_cpu_data.x86 == 0x11) 7372da11654SDoug Thompson edac_printk(KERN_DEBUG, EDAC_MC, "F11h CPU detected\n"); 7382da11654SDoug Thompson else if (boot_cpu_data.x86 == 0x10) 7392da11654SDoug Thompson edac_printk(KERN_DEBUG, EDAC_MC, "F10h CPU detected\n"); 7402da11654SDoug Thompson else if (boot_cpu_data.x86 == 0xf) 7412da11654SDoug Thompson edac_printk(KERN_DEBUG, EDAC_MC, "%s detected\n", 7422da11654SDoug Thompson (pvt->ext_model >= OPTERON_CPU_REV_F) ? 7432da11654SDoug Thompson "Rev F or later" : "Rev E or earlier"); 7442da11654SDoug Thompson else 7452da11654SDoug Thompson /* we'll hardly ever ever get here */ 7462da11654SDoug Thompson edac_printk(KERN_ERR, EDAC_MC, "Unknown cpu!\n"); 7472da11654SDoug Thompson } 7482da11654SDoug Thompson 7492da11654SDoug Thompson /* 7502da11654SDoug Thompson * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs 7512da11654SDoug Thompson * are ECC capable. 7522da11654SDoug Thompson */ 7532da11654SDoug Thompson static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt) 7542da11654SDoug Thompson { 7552da11654SDoug Thompson int bit; 7562da11654SDoug Thompson enum dev_type edac_cap = EDAC_NONE; 7572da11654SDoug Thompson 7582da11654SDoug Thompson bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= OPTERON_CPU_REV_F) 7592da11654SDoug Thompson ? 19 7602da11654SDoug Thompson : 17; 7612da11654SDoug Thompson 7622da11654SDoug Thompson if (pvt->dclr0 >> BIT(bit)) 7632da11654SDoug Thompson edac_cap = EDAC_FLAG_SECDED; 7642da11654SDoug Thompson 7652da11654SDoug Thompson return edac_cap; 7662da11654SDoug Thompson } 7672da11654SDoug Thompson 7682da11654SDoug Thompson 7692da11654SDoug Thompson static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt, 7702da11654SDoug Thompson int ganged); 7712da11654SDoug Thompson 7722da11654SDoug Thompson /* Display and decode various NB registers for debug purposes. */ 7732da11654SDoug Thompson static void amd64_dump_misc_regs(struct amd64_pvt *pvt) 7742da11654SDoug Thompson { 7752da11654SDoug Thompson int ganged; 7762da11654SDoug Thompson 7772da11654SDoug Thompson debugf1(" nbcap:0x%8.08x DctDualCap=%s DualNode=%s 8-Node=%s\n", 7782da11654SDoug Thompson pvt->nbcap, 7792da11654SDoug Thompson (pvt->nbcap & K8_NBCAP_DCT_DUAL) ? "True" : "False", 7802da11654SDoug Thompson (pvt->nbcap & K8_NBCAP_DUAL_NODE) ? "True" : "False", 7812da11654SDoug Thompson (pvt->nbcap & K8_NBCAP_8_NODE) ? "True" : "False"); 7822da11654SDoug Thompson debugf1(" ECC Capable=%s ChipKill Capable=%s\n", 7832da11654SDoug Thompson (pvt->nbcap & K8_NBCAP_SECDED) ? "True" : "False", 7842da11654SDoug Thompson (pvt->nbcap & K8_NBCAP_CHIPKILL) ? "True" : "False"); 7852da11654SDoug Thompson debugf1(" DramCfg0-low=0x%08x DIMM-ECC=%s Parity=%s Width=%s\n", 7862da11654SDoug Thompson pvt->dclr0, 7872da11654SDoug Thompson (pvt->dclr0 & BIT(19)) ? "Enabled" : "Disabled", 7882da11654SDoug Thompson (pvt->dclr0 & BIT(8)) ? "Enabled" : "Disabled", 7892da11654SDoug Thompson (pvt->dclr0 & BIT(11)) ? "128b" : "64b"); 7902da11654SDoug Thompson debugf1(" DIMM x4 Present: L0=%s L1=%s L2=%s L3=%s DIMM Type=%s\n", 7912da11654SDoug Thompson (pvt->dclr0 & BIT(12)) ? "Y" : "N", 7922da11654SDoug Thompson (pvt->dclr0 & BIT(13)) ? "Y" : "N", 7932da11654SDoug Thompson (pvt->dclr0 & BIT(14)) ? "Y" : "N", 7942da11654SDoug Thompson (pvt->dclr0 & BIT(15)) ? "Y" : "N", 7952da11654SDoug Thompson (pvt->dclr0 & BIT(16)) ? "UN-Buffered" : "Buffered"); 7962da11654SDoug Thompson 7972da11654SDoug Thompson 7982da11654SDoug Thompson debugf1(" online-spare: 0x%8.08x\n", pvt->online_spare); 7992da11654SDoug Thompson 8002da11654SDoug Thompson if (boot_cpu_data.x86 == 0xf) { 8012da11654SDoug Thompson debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n", 8022da11654SDoug Thompson pvt->dhar, dhar_base(pvt->dhar), 8032da11654SDoug Thompson k8_dhar_offset(pvt->dhar)); 8042da11654SDoug Thompson debugf1(" DramHoleValid=%s\n", 8052da11654SDoug Thompson (pvt->dhar & DHAR_VALID) ? "True" : "False"); 8062da11654SDoug Thompson 8072da11654SDoug Thompson debugf1(" dbam-dkt: 0x%8.08x\n", pvt->dbam0); 8082da11654SDoug Thompson 8092da11654SDoug Thompson /* everything below this point is Fam10h and above */ 8102da11654SDoug Thompson return; 8112da11654SDoug Thompson 8122da11654SDoug Thompson } else { 8132da11654SDoug Thompson debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n", 8142da11654SDoug Thompson pvt->dhar, dhar_base(pvt->dhar), 8152da11654SDoug Thompson f10_dhar_offset(pvt->dhar)); 8162da11654SDoug Thompson debugf1(" DramMemHoistValid=%s DramHoleValid=%s\n", 8172da11654SDoug Thompson (pvt->dhar & F10_DRAM_MEM_HOIST_VALID) ? 8182da11654SDoug Thompson "True" : "False", 8192da11654SDoug Thompson (pvt->dhar & DHAR_VALID) ? 8202da11654SDoug Thompson "True" : "False"); 8212da11654SDoug Thompson } 8222da11654SDoug Thompson 8232da11654SDoug Thompson /* Only if NOT ganged does dcl1 have valid info */ 8242da11654SDoug Thompson if (!dct_ganging_enabled(pvt)) { 8252da11654SDoug Thompson debugf1(" DramCfg1-low=0x%08x DIMM-ECC=%s Parity=%s " 8262da11654SDoug Thompson "Width=%s\n", pvt->dclr1, 8272da11654SDoug Thompson (pvt->dclr1 & BIT(19)) ? "Enabled" : "Disabled", 8282da11654SDoug Thompson (pvt->dclr1 & BIT(8)) ? "Enabled" : "Disabled", 8292da11654SDoug Thompson (pvt->dclr1 & BIT(11)) ? "128b" : "64b"); 8302da11654SDoug Thompson debugf1(" DIMM x4 Present: L0=%s L1=%s L2=%s L3=%s " 8312da11654SDoug Thompson "DIMM Type=%s\n", 8322da11654SDoug Thompson (pvt->dclr1 & BIT(12)) ? "Y" : "N", 8332da11654SDoug Thompson (pvt->dclr1 & BIT(13)) ? "Y" : "N", 8342da11654SDoug Thompson (pvt->dclr1 & BIT(14)) ? "Y" : "N", 8352da11654SDoug Thompson (pvt->dclr1 & BIT(15)) ? "Y" : "N", 8362da11654SDoug Thompson (pvt->dclr1 & BIT(16)) ? "UN-Buffered" : "Buffered"); 8372da11654SDoug Thompson } 8382da11654SDoug Thompson 8392da11654SDoug Thompson /* 8402da11654SDoug Thompson * Determine if ganged and then dump memory sizes for first controller, 8412da11654SDoug Thompson * and if NOT ganged dump info for 2nd controller. 8422da11654SDoug Thompson */ 8432da11654SDoug Thompson ganged = dct_ganging_enabled(pvt); 8442da11654SDoug Thompson 8452da11654SDoug Thompson f10_debug_display_dimm_sizes(0, pvt, ganged); 8462da11654SDoug Thompson 8472da11654SDoug Thompson if (!ganged) 8482da11654SDoug Thompson f10_debug_display_dimm_sizes(1, pvt, ganged); 8492da11654SDoug Thompson } 8502da11654SDoug Thompson 8512da11654SDoug Thompson /* Read in both of DBAM registers */ 8522da11654SDoug Thompson static void amd64_read_dbam_reg(struct amd64_pvt *pvt) 8532da11654SDoug Thompson { 8542da11654SDoug Thompson int err = 0; 8552da11654SDoug Thompson unsigned int reg; 8562da11654SDoug Thompson 8572da11654SDoug Thompson reg = DBAM0; 8582da11654SDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, reg, &pvt->dbam0); 8592da11654SDoug Thompson if (err) 8602da11654SDoug Thompson goto err_reg; 8612da11654SDoug Thompson 8622da11654SDoug Thompson if (boot_cpu_data.x86 >= 0x10) { 8632da11654SDoug Thompson reg = DBAM1; 8642da11654SDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, reg, &pvt->dbam1); 8652da11654SDoug Thompson 8662da11654SDoug Thompson if (err) 8672da11654SDoug Thompson goto err_reg; 8682da11654SDoug Thompson } 8692da11654SDoug Thompson 8702da11654SDoug Thompson err_reg: 8712da11654SDoug Thompson debugf0("Error reading F2x%03x.\n", reg); 8722da11654SDoug Thompson } 8732da11654SDoug Thompson 87494be4bffSDoug Thompson /* 87594be4bffSDoug Thompson * NOTE: CPU Revision Dependent code: Rev E and Rev F 87694be4bffSDoug Thompson * 87794be4bffSDoug Thompson * Set the DCSB and DCSM mask values depending on the CPU revision value. Also 87894be4bffSDoug Thompson * set the shift factor for the DCSB and DCSM values. 87994be4bffSDoug Thompson * 88094be4bffSDoug Thompson * ->dcs_mask_notused, RevE: 88194be4bffSDoug Thompson * 88294be4bffSDoug Thompson * To find the max InputAddr for the csrow, start with the base address and set 88394be4bffSDoug Thompson * all bits that are "don't care" bits in the test at the start of section 88494be4bffSDoug Thompson * 3.5.4 (p. 84). 88594be4bffSDoug Thompson * 88694be4bffSDoug Thompson * The "don't care" bits are all set bits in the mask and all bits in the gaps 88794be4bffSDoug Thompson * between bit ranges [35:25] and [19:13]. The value REV_E_DCS_NOTUSED_BITS 88894be4bffSDoug Thompson * represents bits [24:20] and [12:0], which are all bits in the above-mentioned 88994be4bffSDoug Thompson * gaps. 89094be4bffSDoug Thompson * 89194be4bffSDoug Thompson * ->dcs_mask_notused, RevF and later: 89294be4bffSDoug Thompson * 89394be4bffSDoug Thompson * To find the max InputAddr for the csrow, start with the base address and set 89494be4bffSDoug Thompson * all bits that are "don't care" bits in the test at the start of NPT section 89594be4bffSDoug Thompson * 4.5.4 (p. 87). 89694be4bffSDoug Thompson * 89794be4bffSDoug Thompson * The "don't care" bits are all set bits in the mask and all bits in the gaps 89894be4bffSDoug Thompson * between bit ranges [36:27] and [21:13]. 89994be4bffSDoug Thompson * 90094be4bffSDoug Thompson * The value REV_F_F1Xh_DCS_NOTUSED_BITS represents bits [26:22] and [12:0], 90194be4bffSDoug Thompson * which are all bits in the above-mentioned gaps. 90294be4bffSDoug Thompson */ 90394be4bffSDoug Thompson static void amd64_set_dct_base_and_mask(struct amd64_pvt *pvt) 90494be4bffSDoug Thompson { 90594be4bffSDoug Thompson if (pvt->ext_model >= OPTERON_CPU_REV_F) { 90694be4bffSDoug Thompson pvt->dcsb_base = REV_F_F1Xh_DCSB_BASE_BITS; 90794be4bffSDoug Thompson pvt->dcsm_mask = REV_F_F1Xh_DCSM_MASK_BITS; 90894be4bffSDoug Thompson pvt->dcs_mask_notused = REV_F_F1Xh_DCS_NOTUSED_BITS; 90994be4bffSDoug Thompson pvt->dcs_shift = REV_F_F1Xh_DCS_SHIFT; 91094be4bffSDoug Thompson 91194be4bffSDoug Thompson switch (boot_cpu_data.x86) { 91294be4bffSDoug Thompson case 0xf: 91394be4bffSDoug Thompson pvt->num_dcsm = REV_F_DCSM_COUNT; 91494be4bffSDoug Thompson break; 91594be4bffSDoug Thompson 91694be4bffSDoug Thompson case 0x10: 91794be4bffSDoug Thompson pvt->num_dcsm = F10_DCSM_COUNT; 91894be4bffSDoug Thompson break; 91994be4bffSDoug Thompson 92094be4bffSDoug Thompson case 0x11: 92194be4bffSDoug Thompson pvt->num_dcsm = F11_DCSM_COUNT; 92294be4bffSDoug Thompson break; 92394be4bffSDoug Thompson 92494be4bffSDoug Thompson default: 92594be4bffSDoug Thompson amd64_printk(KERN_ERR, "Unsupported family!\n"); 92694be4bffSDoug Thompson break; 92794be4bffSDoug Thompson } 92894be4bffSDoug Thompson } else { 92994be4bffSDoug Thompson pvt->dcsb_base = REV_E_DCSB_BASE_BITS; 93094be4bffSDoug Thompson pvt->dcsm_mask = REV_E_DCSM_MASK_BITS; 93194be4bffSDoug Thompson pvt->dcs_mask_notused = REV_E_DCS_NOTUSED_BITS; 93294be4bffSDoug Thompson pvt->dcs_shift = REV_E_DCS_SHIFT; 93394be4bffSDoug Thompson pvt->num_dcsm = REV_E_DCSM_COUNT; 93494be4bffSDoug Thompson } 93594be4bffSDoug Thompson } 93694be4bffSDoug Thompson 93794be4bffSDoug Thompson /* 93894be4bffSDoug Thompson * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask hw registers 93994be4bffSDoug Thompson */ 94094be4bffSDoug Thompson static void amd64_read_dct_base_mask(struct amd64_pvt *pvt) 94194be4bffSDoug Thompson { 94294be4bffSDoug Thompson int cs, reg, err = 0; 94394be4bffSDoug Thompson 94494be4bffSDoug Thompson amd64_set_dct_base_and_mask(pvt); 94594be4bffSDoug Thompson 94694be4bffSDoug Thompson for (cs = 0; cs < CHIPSELECT_COUNT; cs++) { 94794be4bffSDoug Thompson reg = K8_DCSB0 + (cs * 4); 94894be4bffSDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, reg, 94994be4bffSDoug Thompson &pvt->dcsb0[cs]); 95094be4bffSDoug Thompson if (unlikely(err)) 95194be4bffSDoug Thompson debugf0("Reading K8_DCSB0[%d] failed\n", cs); 95294be4bffSDoug Thompson else 95394be4bffSDoug Thompson debugf0(" DCSB0[%d]=0x%08x reg: F2x%x\n", 95494be4bffSDoug Thompson cs, pvt->dcsb0[cs], reg); 95594be4bffSDoug Thompson 95694be4bffSDoug Thompson /* If DCT are NOT ganged, then read in DCT1's base */ 95794be4bffSDoug Thompson if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) { 95894be4bffSDoug Thompson reg = F10_DCSB1 + (cs * 4); 95994be4bffSDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, reg, 96094be4bffSDoug Thompson &pvt->dcsb1[cs]); 96194be4bffSDoug Thompson if (unlikely(err)) 96294be4bffSDoug Thompson debugf0("Reading F10_DCSB1[%d] failed\n", cs); 96394be4bffSDoug Thompson else 96494be4bffSDoug Thompson debugf0(" DCSB1[%d]=0x%08x reg: F2x%x\n", 96594be4bffSDoug Thompson cs, pvt->dcsb1[cs], reg); 96694be4bffSDoug Thompson } else { 96794be4bffSDoug Thompson pvt->dcsb1[cs] = 0; 96894be4bffSDoug Thompson } 96994be4bffSDoug Thompson } 97094be4bffSDoug Thompson 97194be4bffSDoug Thompson for (cs = 0; cs < pvt->num_dcsm; cs++) { 97294be4bffSDoug Thompson reg = K8_DCSB0 + (cs * 4); 97394be4bffSDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, reg, 97494be4bffSDoug Thompson &pvt->dcsm0[cs]); 97594be4bffSDoug Thompson if (unlikely(err)) 97694be4bffSDoug Thompson debugf0("Reading K8_DCSM0 failed\n"); 97794be4bffSDoug Thompson else 97894be4bffSDoug Thompson debugf0(" DCSM0[%d]=0x%08x reg: F2x%x\n", 97994be4bffSDoug Thompson cs, pvt->dcsm0[cs], reg); 98094be4bffSDoug Thompson 98194be4bffSDoug Thompson /* If DCT are NOT ganged, then read in DCT1's mask */ 98294be4bffSDoug Thompson if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) { 98394be4bffSDoug Thompson reg = F10_DCSM1 + (cs * 4); 98494be4bffSDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, reg, 98594be4bffSDoug Thompson &pvt->dcsm1[cs]); 98694be4bffSDoug Thompson if (unlikely(err)) 98794be4bffSDoug Thompson debugf0("Reading F10_DCSM1[%d] failed\n", cs); 98894be4bffSDoug Thompson else 98994be4bffSDoug Thompson debugf0(" DCSM1[%d]=0x%08x reg: F2x%x\n", 99094be4bffSDoug Thompson cs, pvt->dcsm1[cs], reg); 99194be4bffSDoug Thompson } else 99294be4bffSDoug Thompson pvt->dcsm1[cs] = 0; 99394be4bffSDoug Thompson } 99494be4bffSDoug Thompson } 99594be4bffSDoug Thompson 99694be4bffSDoug Thompson static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt) 99794be4bffSDoug Thompson { 99894be4bffSDoug Thompson enum mem_type type; 99994be4bffSDoug Thompson 100094be4bffSDoug Thompson if (boot_cpu_data.x86 >= 0x10 || pvt->ext_model >= OPTERON_CPU_REV_F) { 100194be4bffSDoug Thompson /* Rev F and later */ 100294be4bffSDoug Thompson type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; 100394be4bffSDoug Thompson } else { 100494be4bffSDoug Thompson /* Rev E and earlier */ 100594be4bffSDoug Thompson type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; 100694be4bffSDoug Thompson } 100794be4bffSDoug Thompson 100894be4bffSDoug Thompson debugf1(" Memory type is: %s\n", 100994be4bffSDoug Thompson (type == MEM_DDR2) ? "MEM_DDR2" : 101094be4bffSDoug Thompson (type == MEM_RDDR2) ? "MEM_RDDR2" : 101194be4bffSDoug Thompson (type == MEM_DDR) ? "MEM_DDR" : "MEM_RDDR"); 101294be4bffSDoug Thompson 101394be4bffSDoug Thompson return type; 101494be4bffSDoug Thompson } 101594be4bffSDoug Thompson 1016ddff876dSDoug Thompson /* 1017ddff876dSDoug Thompson * Read the DRAM Configuration Low register. It differs between CG, D & E revs 1018ddff876dSDoug Thompson * and the later RevF memory controllers (DDR vs DDR2) 1019ddff876dSDoug Thompson * 1020ddff876dSDoug Thompson * Return: 1021ddff876dSDoug Thompson * number of memory channels in operation 1022ddff876dSDoug Thompson * Pass back: 1023ddff876dSDoug Thompson * contents of the DCL0_LOW register 1024ddff876dSDoug Thompson */ 1025ddff876dSDoug Thompson static int k8_early_channel_count(struct amd64_pvt *pvt) 1026ddff876dSDoug Thompson { 1027ddff876dSDoug Thompson int flag, err = 0; 1028ddff876dSDoug Thompson 1029ddff876dSDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0); 1030ddff876dSDoug Thompson if (err) 1031ddff876dSDoug Thompson return err; 1032ddff876dSDoug Thompson 1033ddff876dSDoug Thompson if ((boot_cpu_data.x86_model >> 4) >= OPTERON_CPU_REV_F) { 1034ddff876dSDoug Thompson /* RevF (NPT) and later */ 1035ddff876dSDoug Thompson flag = pvt->dclr0 & F10_WIDTH_128; 1036ddff876dSDoug Thompson } else { 1037ddff876dSDoug Thompson /* RevE and earlier */ 1038ddff876dSDoug Thompson flag = pvt->dclr0 & REVE_WIDTH_128; 1039ddff876dSDoug Thompson } 1040ddff876dSDoug Thompson 1041ddff876dSDoug Thompson /* not used */ 1042ddff876dSDoug Thompson pvt->dclr1 = 0; 1043ddff876dSDoug Thompson 1044ddff876dSDoug Thompson return (flag) ? 2 : 1; 1045ddff876dSDoug Thompson } 1046ddff876dSDoug Thompson 1047ddff876dSDoug Thompson /* extract the ERROR ADDRESS for the K8 CPUs */ 1048ddff876dSDoug Thompson static u64 k8_get_error_address(struct mem_ctl_info *mci, 1049ddff876dSDoug Thompson struct amd64_error_info_regs *info) 1050ddff876dSDoug Thompson { 1051ddff876dSDoug Thompson return (((u64) (info->nbeah & 0xff)) << 32) + 1052ddff876dSDoug Thompson (info->nbeal & ~0x03); 1053ddff876dSDoug Thompson } 1054ddff876dSDoug Thompson 1055ddff876dSDoug Thompson /* 1056ddff876dSDoug Thompson * Read the Base and Limit registers for K8 based Memory controllers; extract 1057ddff876dSDoug Thompson * fields from the 'raw' reg into separate data fields 1058ddff876dSDoug Thompson * 1059ddff876dSDoug Thompson * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN 1060ddff876dSDoug Thompson */ 1061ddff876dSDoug Thompson static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram) 1062ddff876dSDoug Thompson { 1063ddff876dSDoug Thompson u32 low; 1064ddff876dSDoug Thompson u32 off = dram << 3; /* 8 bytes between DRAM entries */ 1065ddff876dSDoug Thompson int err; 1066ddff876dSDoug Thompson 1067ddff876dSDoug Thompson err = pci_read_config_dword(pvt->addr_f1_ctl, 1068ddff876dSDoug Thompson K8_DRAM_BASE_LOW + off, &low); 1069ddff876dSDoug Thompson if (err) 1070ddff876dSDoug Thompson debugf0("Reading K8_DRAM_BASE_LOW failed\n"); 1071ddff876dSDoug Thompson 1072ddff876dSDoug Thompson /* Extract parts into separate data entries */ 1073ddff876dSDoug Thompson pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 8; 1074ddff876dSDoug Thompson pvt->dram_IntlvEn[dram] = (low >> 8) & 0x7; 1075ddff876dSDoug Thompson pvt->dram_rw_en[dram] = (low & 0x3); 1076ddff876dSDoug Thompson 1077ddff876dSDoug Thompson err = pci_read_config_dword(pvt->addr_f1_ctl, 1078ddff876dSDoug Thompson K8_DRAM_LIMIT_LOW + off, &low); 1079ddff876dSDoug Thompson if (err) 1080ddff876dSDoug Thompson debugf0("Reading K8_DRAM_LIMIT_LOW failed\n"); 1081ddff876dSDoug Thompson 1082ddff876dSDoug Thompson /* 1083ddff876dSDoug Thompson * Extract parts into separate data entries. Limit is the HIGHEST memory 1084ddff876dSDoug Thompson * location of the region, so lower 24 bits need to be all ones 1085ddff876dSDoug Thompson */ 1086ddff876dSDoug Thompson pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 8) | 0x00FFFFFF; 1087ddff876dSDoug Thompson pvt->dram_IntlvSel[dram] = (low >> 8) & 0x7; 1088ddff876dSDoug Thompson pvt->dram_DstNode[dram] = (low & 0x7); 1089ddff876dSDoug Thompson } 1090ddff876dSDoug Thompson 1091ddff876dSDoug Thompson static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, 1092ddff876dSDoug Thompson struct amd64_error_info_regs *info, 1093ddff876dSDoug Thompson u64 SystemAddress) 1094ddff876dSDoug Thompson { 1095ddff876dSDoug Thompson struct mem_ctl_info *src_mci; 1096ddff876dSDoug Thompson unsigned short syndrome; 1097ddff876dSDoug Thompson int channel, csrow; 1098ddff876dSDoug Thompson u32 page, offset; 1099ddff876dSDoug Thompson 1100ddff876dSDoug Thompson /* Extract the syndrome parts and form a 16-bit syndrome */ 1101ddff876dSDoug Thompson syndrome = EXTRACT_HIGH_SYNDROME(info->nbsl) << 8; 1102ddff876dSDoug Thompson syndrome |= EXTRACT_LOW_SYNDROME(info->nbsh); 1103ddff876dSDoug Thompson 1104ddff876dSDoug Thompson /* CHIPKILL enabled */ 1105ddff876dSDoug Thompson if (info->nbcfg & K8_NBCFG_CHIPKILL) { 1106ddff876dSDoug Thompson channel = get_channel_from_ecc_syndrome(syndrome); 1107ddff876dSDoug Thompson if (channel < 0) { 1108ddff876dSDoug Thompson /* 1109ddff876dSDoug Thompson * Syndrome didn't map, so we don't know which of the 1110ddff876dSDoug Thompson * 2 DIMMs is in error. So we need to ID 'both' of them 1111ddff876dSDoug Thompson * as suspect. 1112ddff876dSDoug Thompson */ 1113ddff876dSDoug Thompson amd64_mc_printk(mci, KERN_WARNING, 1114ddff876dSDoug Thompson "unknown syndrome 0x%x - possible error " 1115ddff876dSDoug Thompson "reporting race\n", syndrome); 1116ddff876dSDoug Thompson edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); 1117ddff876dSDoug Thompson return; 1118ddff876dSDoug Thompson } 1119ddff876dSDoug Thompson } else { 1120ddff876dSDoug Thompson /* 1121ddff876dSDoug Thompson * non-chipkill ecc mode 1122ddff876dSDoug Thompson * 1123ddff876dSDoug Thompson * The k8 documentation is unclear about how to determine the 1124ddff876dSDoug Thompson * channel number when using non-chipkill memory. This method 1125ddff876dSDoug Thompson * was obtained from email communication with someone at AMD. 1126ddff876dSDoug Thompson * (Wish the email was placed in this comment - norsk) 1127ddff876dSDoug Thompson */ 1128ddff876dSDoug Thompson channel = ((SystemAddress & BIT(3)) != 0); 1129ddff876dSDoug Thompson } 1130ddff876dSDoug Thompson 1131ddff876dSDoug Thompson /* 1132ddff876dSDoug Thompson * Find out which node the error address belongs to. This may be 1133ddff876dSDoug Thompson * different from the node that detected the error. 1134ddff876dSDoug Thompson */ 1135ddff876dSDoug Thompson src_mci = find_mc_by_sys_addr(mci, SystemAddress); 1136ddff876dSDoug Thompson if (src_mci) { 1137ddff876dSDoug Thompson amd64_mc_printk(mci, KERN_ERR, 1138ddff876dSDoug Thompson "failed to map error address 0x%lx to a node\n", 1139ddff876dSDoug Thompson (unsigned long)SystemAddress); 1140ddff876dSDoug Thompson edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); 1141ddff876dSDoug Thompson return; 1142ddff876dSDoug Thompson } 1143ddff876dSDoug Thompson 1144ddff876dSDoug Thompson /* Now map the SystemAddress to a CSROW */ 1145ddff876dSDoug Thompson csrow = sys_addr_to_csrow(src_mci, SystemAddress); 1146ddff876dSDoug Thompson if (csrow < 0) { 1147ddff876dSDoug Thompson edac_mc_handle_ce_no_info(src_mci, EDAC_MOD_STR); 1148ddff876dSDoug Thompson } else { 1149ddff876dSDoug Thompson error_address_to_page_and_offset(SystemAddress, &page, &offset); 1150ddff876dSDoug Thompson 1151ddff876dSDoug Thompson edac_mc_handle_ce(src_mci, page, offset, syndrome, csrow, 1152ddff876dSDoug Thompson channel, EDAC_MOD_STR); 1153ddff876dSDoug Thompson } 1154ddff876dSDoug Thompson } 1155ddff876dSDoug Thompson 1156ddff876dSDoug Thompson /* 1157ddff876dSDoug Thompson * determrine the number of PAGES in for this DIMM's size based on its DRAM 1158ddff876dSDoug Thompson * Address Mapping. 1159ddff876dSDoug Thompson * 1160ddff876dSDoug Thompson * First step is to calc the number of bits to shift a value of 1 left to 1161ddff876dSDoug Thompson * indicate show many pages. Start with the DBAM value as the starting bits, 1162ddff876dSDoug Thompson * then proceed to adjust those shift bits, based on CPU rev and the table. 1163ddff876dSDoug Thompson * See BKDG on the DBAM 1164ddff876dSDoug Thompson */ 1165ddff876dSDoug Thompson static int k8_dbam_map_to_pages(struct amd64_pvt *pvt, int dram_map) 1166ddff876dSDoug Thompson { 1167ddff876dSDoug Thompson int nr_pages; 1168ddff876dSDoug Thompson 1169ddff876dSDoug Thompson if (pvt->ext_model >= OPTERON_CPU_REV_F) { 1170ddff876dSDoug Thompson nr_pages = 1 << (revf_quad_ddr2_shift[dram_map] - PAGE_SHIFT); 1171ddff876dSDoug Thompson } else { 1172ddff876dSDoug Thompson /* 1173ddff876dSDoug Thompson * RevE and less section; this line is tricky. It collapses the 1174ddff876dSDoug Thompson * table used by RevD and later to one that matches revisions CG 1175ddff876dSDoug Thompson * and earlier. 1176ddff876dSDoug Thompson */ 1177ddff876dSDoug Thompson dram_map -= (pvt->ext_model >= OPTERON_CPU_REV_D) ? 1178ddff876dSDoug Thompson (dram_map > 8 ? 4 : (dram_map > 5 ? 1179ddff876dSDoug Thompson 3 : (dram_map > 2 ? 1 : 0))) : 0; 1180ddff876dSDoug Thompson 1181ddff876dSDoug Thompson /* 25 shift is 32MiB minimum DIMM size in RevE and prior */ 1182ddff876dSDoug Thompson nr_pages = 1 << (dram_map + 25 - PAGE_SHIFT); 1183ddff876dSDoug Thompson } 1184ddff876dSDoug Thompson 1185ddff876dSDoug Thompson return nr_pages; 1186ddff876dSDoug Thompson } 1187ddff876dSDoug Thompson 11881afd3c98SDoug Thompson /* 11891afd3c98SDoug Thompson * Get the number of DCT channels in use. 11901afd3c98SDoug Thompson * 11911afd3c98SDoug Thompson * Return: 11921afd3c98SDoug Thompson * number of Memory Channels in operation 11931afd3c98SDoug Thompson * Pass back: 11941afd3c98SDoug Thompson * contents of the DCL0_LOW register 11951afd3c98SDoug Thompson */ 11961afd3c98SDoug Thompson static int f10_early_channel_count(struct amd64_pvt *pvt) 11971afd3c98SDoug Thompson { 11981afd3c98SDoug Thompson int err = 0, channels = 0; 11991afd3c98SDoug Thompson u32 dbam; 1200ddff876dSDoug Thompson 12011afd3c98SDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0); 12021afd3c98SDoug Thompson if (err) 12031afd3c98SDoug Thompson goto err_reg; 12041afd3c98SDoug Thompson 12051afd3c98SDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_1, &pvt->dclr1); 12061afd3c98SDoug Thompson if (err) 12071afd3c98SDoug Thompson goto err_reg; 12081afd3c98SDoug Thompson 12091afd3c98SDoug Thompson /* If we are in 128 bit mode, then we are using 2 channels */ 12101afd3c98SDoug Thompson if (pvt->dclr0 & F10_WIDTH_128) { 12111afd3c98SDoug Thompson debugf0("Data WIDTH is 128 bits - 2 channels\n"); 12121afd3c98SDoug Thompson channels = 2; 12131afd3c98SDoug Thompson return channels; 12141afd3c98SDoug Thompson } 12151afd3c98SDoug Thompson 12161afd3c98SDoug Thompson /* 12171afd3c98SDoug Thompson * Need to check if in UN-ganged mode: In such, there are 2 channels, 12181afd3c98SDoug Thompson * but they are NOT in 128 bit mode and thus the above 'dcl0' status bit 12191afd3c98SDoug Thompson * will be OFF. 12201afd3c98SDoug Thompson * 12211afd3c98SDoug Thompson * Need to check DCT0[0] and DCT1[0] to see if only one of them has 12221afd3c98SDoug Thompson * their CSEnable bit on. If so, then SINGLE DIMM case. 12231afd3c98SDoug Thompson */ 12241afd3c98SDoug Thompson debugf0("Data WIDTH is NOT 128 bits - need more decoding\n"); 12251afd3c98SDoug Thompson 12261afd3c98SDoug Thompson /* 12271afd3c98SDoug Thompson * Check DRAM Bank Address Mapping values for each DIMM to see if there 12281afd3c98SDoug Thompson * is more than just one DIMM present in unganged mode. Need to check 12291afd3c98SDoug Thompson * both controllers since DIMMs can be placed in either one. 12301afd3c98SDoug Thompson */ 12311afd3c98SDoug Thompson channels = 0; 12321afd3c98SDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, DBAM0, &dbam); 12331afd3c98SDoug Thompson if (err) 12341afd3c98SDoug Thompson goto err_reg; 12351afd3c98SDoug Thompson 12361afd3c98SDoug Thompson if (DBAM_DIMM(0, dbam) > 0) 12371afd3c98SDoug Thompson channels++; 12381afd3c98SDoug Thompson if (DBAM_DIMM(1, dbam) > 0) 12391afd3c98SDoug Thompson channels++; 12401afd3c98SDoug Thompson if (DBAM_DIMM(2, dbam) > 0) 12411afd3c98SDoug Thompson channels++; 12421afd3c98SDoug Thompson if (DBAM_DIMM(3, dbam) > 0) 12431afd3c98SDoug Thompson channels++; 12441afd3c98SDoug Thompson 12451afd3c98SDoug Thompson /* If more than 2 DIMMs are present, then we have 2 channels */ 12461afd3c98SDoug Thompson if (channels > 2) 12471afd3c98SDoug Thompson channels = 2; 12481afd3c98SDoug Thompson else if (channels == 0) { 12491afd3c98SDoug Thompson /* No DIMMs on DCT0, so look at DCT1 */ 12501afd3c98SDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, DBAM1, &dbam); 12511afd3c98SDoug Thompson if (err) 12521afd3c98SDoug Thompson goto err_reg; 12531afd3c98SDoug Thompson 12541afd3c98SDoug Thompson if (DBAM_DIMM(0, dbam) > 0) 12551afd3c98SDoug Thompson channels++; 12561afd3c98SDoug Thompson if (DBAM_DIMM(1, dbam) > 0) 12571afd3c98SDoug Thompson channels++; 12581afd3c98SDoug Thompson if (DBAM_DIMM(2, dbam) > 0) 12591afd3c98SDoug Thompson channels++; 12601afd3c98SDoug Thompson if (DBAM_DIMM(3, dbam) > 0) 12611afd3c98SDoug Thompson channels++; 12621afd3c98SDoug Thompson 12631afd3c98SDoug Thompson if (channels > 2) 12641afd3c98SDoug Thompson channels = 2; 12651afd3c98SDoug Thompson } 12661afd3c98SDoug Thompson 12671afd3c98SDoug Thompson /* If we found ALL 0 values, then assume just ONE DIMM-ONE Channel */ 12681afd3c98SDoug Thompson if (channels == 0) 12691afd3c98SDoug Thompson channels = 1; 12701afd3c98SDoug Thompson 12711afd3c98SDoug Thompson debugf0("DIMM count= %d\n", channels); 12721afd3c98SDoug Thompson 12731afd3c98SDoug Thompson return channels; 12741afd3c98SDoug Thompson 12751afd3c98SDoug Thompson err_reg: 12761afd3c98SDoug Thompson return -1; 12771afd3c98SDoug Thompson 12781afd3c98SDoug Thompson } 12791afd3c98SDoug Thompson 12801afd3c98SDoug Thompson static int f10_dbam_map_to_pages(struct amd64_pvt *pvt, int dram_map) 12811afd3c98SDoug Thompson { 12821afd3c98SDoug Thompson return 1 << (revf_quad_ddr2_shift[dram_map] - PAGE_SHIFT); 12831afd3c98SDoug Thompson } 12841afd3c98SDoug Thompson 12851afd3c98SDoug Thompson /* Enable extended configuration access via 0xCF8 feature */ 12861afd3c98SDoug Thompson static void amd64_setup(struct amd64_pvt *pvt) 12871afd3c98SDoug Thompson { 12881afd3c98SDoug Thompson u32 reg; 12891afd3c98SDoug Thompson 12901afd3c98SDoug Thompson pci_read_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, ®); 12911afd3c98SDoug Thompson 12921afd3c98SDoug Thompson pvt->flags.cf8_extcfg = !!(reg & F10_NB_CFG_LOW_ENABLE_EXT_CFG); 12931afd3c98SDoug Thompson reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG; 12941afd3c98SDoug Thompson pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg); 12951afd3c98SDoug Thompson } 12961afd3c98SDoug Thompson 12971afd3c98SDoug Thompson /* Restore the extended configuration access via 0xCF8 feature */ 12981afd3c98SDoug Thompson static void amd64_teardown(struct amd64_pvt *pvt) 12991afd3c98SDoug Thompson { 13001afd3c98SDoug Thompson u32 reg; 13011afd3c98SDoug Thompson 13021afd3c98SDoug Thompson pci_read_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, ®); 13031afd3c98SDoug Thompson 13041afd3c98SDoug Thompson reg &= ~F10_NB_CFG_LOW_ENABLE_EXT_CFG; 13051afd3c98SDoug Thompson if (pvt->flags.cf8_extcfg) 13061afd3c98SDoug Thompson reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG; 13071afd3c98SDoug Thompson pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg); 13081afd3c98SDoug Thompson } 13091afd3c98SDoug Thompson 13101afd3c98SDoug Thompson static u64 f10_get_error_address(struct mem_ctl_info *mci, 13111afd3c98SDoug Thompson struct amd64_error_info_regs *info) 13121afd3c98SDoug Thompson { 13131afd3c98SDoug Thompson return (((u64) (info->nbeah & 0xffff)) << 32) + 13141afd3c98SDoug Thompson (info->nbeal & ~0x01); 13151afd3c98SDoug Thompson } 13161afd3c98SDoug Thompson 13171afd3c98SDoug Thompson /* 13181afd3c98SDoug Thompson * Read the Base and Limit registers for F10 based Memory controllers. Extract 13191afd3c98SDoug Thompson * fields from the 'raw' reg into separate data fields. 13201afd3c98SDoug Thompson * 13211afd3c98SDoug Thompson * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN. 13221afd3c98SDoug Thompson */ 13231afd3c98SDoug Thompson static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram) 13241afd3c98SDoug Thompson { 13251afd3c98SDoug Thompson u32 high_offset, low_offset, high_base, low_base, high_limit, low_limit; 13261afd3c98SDoug Thompson 13271afd3c98SDoug Thompson low_offset = K8_DRAM_BASE_LOW + (dram << 3); 13281afd3c98SDoug Thompson high_offset = F10_DRAM_BASE_HIGH + (dram << 3); 13291afd3c98SDoug Thompson 13301afd3c98SDoug Thompson /* read the 'raw' DRAM BASE Address register */ 13311afd3c98SDoug Thompson pci_read_config_dword(pvt->addr_f1_ctl, low_offset, &low_base); 13321afd3c98SDoug Thompson 13331afd3c98SDoug Thompson /* Read from the ECS data register */ 13341afd3c98SDoug Thompson pci_read_config_dword(pvt->addr_f1_ctl, high_offset, &high_base); 13351afd3c98SDoug Thompson 13361afd3c98SDoug Thompson /* Extract parts into separate data entries */ 13371afd3c98SDoug Thompson pvt->dram_rw_en[dram] = (low_base & 0x3); 13381afd3c98SDoug Thompson 13391afd3c98SDoug Thompson if (pvt->dram_rw_en[dram] == 0) 13401afd3c98SDoug Thompson return; 13411afd3c98SDoug Thompson 13421afd3c98SDoug Thompson pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7; 13431afd3c98SDoug Thompson 13441afd3c98SDoug Thompson pvt->dram_base[dram] = (((((u64) high_base & 0x000000FF) << 32) | 13451afd3c98SDoug Thompson ((u64) low_base & 0xFFFF0000))) << 8; 13461afd3c98SDoug Thompson 13471afd3c98SDoug Thompson low_offset = K8_DRAM_LIMIT_LOW + (dram << 3); 13481afd3c98SDoug Thompson high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3); 13491afd3c98SDoug Thompson 13501afd3c98SDoug Thompson /* read the 'raw' LIMIT registers */ 13511afd3c98SDoug Thompson pci_read_config_dword(pvt->addr_f1_ctl, low_offset, &low_limit); 13521afd3c98SDoug Thompson 13531afd3c98SDoug Thompson /* Read from the ECS data register for the HIGH portion */ 13541afd3c98SDoug Thompson pci_read_config_dword(pvt->addr_f1_ctl, high_offset, &high_limit); 13551afd3c98SDoug Thompson 13561afd3c98SDoug Thompson debugf0(" HW Regs: BASE=0x%08x-%08x LIMIT= 0x%08x-%08x\n", 13571afd3c98SDoug Thompson high_base, low_base, high_limit, low_limit); 13581afd3c98SDoug Thompson 13591afd3c98SDoug Thompson pvt->dram_DstNode[dram] = (low_limit & 0x7); 13601afd3c98SDoug Thompson pvt->dram_IntlvSel[dram] = (low_limit >> 8) & 0x7; 13611afd3c98SDoug Thompson 13621afd3c98SDoug Thompson /* 13631afd3c98SDoug Thompson * Extract address values and form a LIMIT address. Limit is the HIGHEST 13641afd3c98SDoug Thompson * memory location of the region, so low 24 bits need to be all ones. 13651afd3c98SDoug Thompson */ 13661afd3c98SDoug Thompson low_limit |= 0x0000FFFF; 13671afd3c98SDoug Thompson pvt->dram_limit[dram] = 13681afd3c98SDoug Thompson ((((u64) high_limit << 32) + (u64) low_limit) << 8) | (0xFF); 13691afd3c98SDoug Thompson } 13706163b5d4SDoug Thompson 13716163b5d4SDoug Thompson static void f10_read_dram_ctl_register(struct amd64_pvt *pvt) 13726163b5d4SDoug Thompson { 13736163b5d4SDoug Thompson int err = 0; 13746163b5d4SDoug Thompson 13756163b5d4SDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCTL_SEL_LOW, 13766163b5d4SDoug Thompson &pvt->dram_ctl_select_low); 13776163b5d4SDoug Thompson if (err) { 13786163b5d4SDoug Thompson debugf0("Reading F10_DCTL_SEL_LOW failed\n"); 13796163b5d4SDoug Thompson } else { 13806163b5d4SDoug Thompson debugf0("DRAM_DCTL_SEL_LOW=0x%x DctSelBaseAddr=0x%x\n", 13816163b5d4SDoug Thompson pvt->dram_ctl_select_low, dct_sel_baseaddr(pvt)); 13826163b5d4SDoug Thompson 13836163b5d4SDoug Thompson debugf0(" DRAM DCTs are=%s DRAM Is=%s DRAM-Ctl-" 13846163b5d4SDoug Thompson "sel-hi-range=%s\n", 13856163b5d4SDoug Thompson (dct_ganging_enabled(pvt) ? "GANGED" : "NOT GANGED"), 13866163b5d4SDoug Thompson (dct_dram_enabled(pvt) ? "Enabled" : "Disabled"), 13876163b5d4SDoug Thompson (dct_high_range_enabled(pvt) ? "Enabled" : "Disabled")); 13886163b5d4SDoug Thompson 13896163b5d4SDoug Thompson debugf0(" DctDatIntLv=%s MemCleared=%s DctSelIntLvAddr=0x%x\n", 13906163b5d4SDoug Thompson (dct_data_intlv_enabled(pvt) ? "Enabled" : "Disabled"), 13916163b5d4SDoug Thompson (dct_memory_cleared(pvt) ? "True " : "False "), 13926163b5d4SDoug Thompson dct_sel_interleave_addr(pvt)); 13936163b5d4SDoug Thompson } 13946163b5d4SDoug Thompson 13956163b5d4SDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCTL_SEL_HIGH, 13966163b5d4SDoug Thompson &pvt->dram_ctl_select_high); 13976163b5d4SDoug Thompson if (err) 13986163b5d4SDoug Thompson debugf0("Reading F10_DCTL_SEL_HIGH failed\n"); 13996163b5d4SDoug Thompson } 14006163b5d4SDoug Thompson 1401f71d0a05SDoug Thompson /* 1402f71d0a05SDoug Thompson * determine channel based on the interleaving mode: F10h BKDG, 2.8.9 Memory 1403f71d0a05SDoug Thompson * Interleaving Modes. 1404f71d0a05SDoug Thompson */ 14056163b5d4SDoug Thompson static u32 f10_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, 14066163b5d4SDoug Thompson int hi_range_sel, u32 intlv_en) 14076163b5d4SDoug Thompson { 14086163b5d4SDoug Thompson u32 cs, temp, dct_sel_high = (pvt->dram_ctl_select_low >> 1) & 1; 14096163b5d4SDoug Thompson 14106163b5d4SDoug Thompson if (dct_ganging_enabled(pvt)) 14116163b5d4SDoug Thompson cs = 0; 14126163b5d4SDoug Thompson else if (hi_range_sel) 14136163b5d4SDoug Thompson cs = dct_sel_high; 14146163b5d4SDoug Thompson else if (dct_interleave_enabled(pvt)) { 1415f71d0a05SDoug Thompson /* 1416f71d0a05SDoug Thompson * see F2x110[DctSelIntLvAddr] - channel interleave mode 1417f71d0a05SDoug Thompson */ 14186163b5d4SDoug Thompson if (dct_sel_interleave_addr(pvt) == 0) 14196163b5d4SDoug Thompson cs = sys_addr >> 6 & 1; 14206163b5d4SDoug Thompson else if ((dct_sel_interleave_addr(pvt) >> 1) & 1) { 14216163b5d4SDoug Thompson temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2; 14226163b5d4SDoug Thompson 14236163b5d4SDoug Thompson if (dct_sel_interleave_addr(pvt) & 1) 14246163b5d4SDoug Thompson cs = (sys_addr >> 9 & 1) ^ temp; 14256163b5d4SDoug Thompson else 14266163b5d4SDoug Thompson cs = (sys_addr >> 6 & 1) ^ temp; 14276163b5d4SDoug Thompson } else if (intlv_en & 4) 14286163b5d4SDoug Thompson cs = sys_addr >> 15 & 1; 14296163b5d4SDoug Thompson else if (intlv_en & 2) 14306163b5d4SDoug Thompson cs = sys_addr >> 14 & 1; 14316163b5d4SDoug Thompson else if (intlv_en & 1) 14326163b5d4SDoug Thompson cs = sys_addr >> 13 & 1; 14336163b5d4SDoug Thompson else 14346163b5d4SDoug Thompson cs = sys_addr >> 12 & 1; 14356163b5d4SDoug Thompson } else if (dct_high_range_enabled(pvt) && !dct_ganging_enabled(pvt)) 14366163b5d4SDoug Thompson cs = ~dct_sel_high & 1; 14376163b5d4SDoug Thompson else 14386163b5d4SDoug Thompson cs = 0; 14396163b5d4SDoug Thompson 14406163b5d4SDoug Thompson return cs; 14416163b5d4SDoug Thompson } 14426163b5d4SDoug Thompson 14436163b5d4SDoug Thompson static inline u32 f10_map_intlv_en_to_shift(u32 intlv_en) 14446163b5d4SDoug Thompson { 14456163b5d4SDoug Thompson if (intlv_en == 1) 14466163b5d4SDoug Thompson return 1; 14476163b5d4SDoug Thompson else if (intlv_en == 3) 14486163b5d4SDoug Thompson return 2; 14496163b5d4SDoug Thompson else if (intlv_en == 7) 14506163b5d4SDoug Thompson return 3; 14516163b5d4SDoug Thompson 14526163b5d4SDoug Thompson return 0; 14536163b5d4SDoug Thompson } 14546163b5d4SDoug Thompson 1455f71d0a05SDoug Thompson /* See F10h BKDG, 2.8.10.2 DctSelBaseOffset Programming */ 1456f71d0a05SDoug Thompson static inline u64 f10_get_base_addr_offset(u64 sys_addr, int hi_range_sel, 14576163b5d4SDoug Thompson u32 dct_sel_base_addr, 14586163b5d4SDoug Thompson u64 dct_sel_base_off, 1459f71d0a05SDoug Thompson u32 hole_valid, u32 hole_off, 14606163b5d4SDoug Thompson u64 dram_base) 14616163b5d4SDoug Thompson { 14626163b5d4SDoug Thompson u64 chan_off; 14636163b5d4SDoug Thompson 14646163b5d4SDoug Thompson if (hi_range_sel) { 14656163b5d4SDoug Thompson if (!(dct_sel_base_addr & 0xFFFFF800) && 1466f71d0a05SDoug Thompson hole_valid && (sys_addr >= 0x100000000ULL)) 14676163b5d4SDoug Thompson chan_off = hole_off << 16; 14686163b5d4SDoug Thompson else 14696163b5d4SDoug Thompson chan_off = dct_sel_base_off; 14706163b5d4SDoug Thompson } else { 1471f71d0a05SDoug Thompson if (hole_valid && (sys_addr >= 0x100000000ULL)) 14726163b5d4SDoug Thompson chan_off = hole_off << 16; 14736163b5d4SDoug Thompson else 14746163b5d4SDoug Thompson chan_off = dram_base & 0xFFFFF8000000ULL; 14756163b5d4SDoug Thompson } 14766163b5d4SDoug Thompson 14776163b5d4SDoug Thompson return (sys_addr & 0x0000FFFFFFFFFFC0ULL) - 14786163b5d4SDoug Thompson (chan_off & 0x0000FFFFFF800000ULL); 14796163b5d4SDoug Thompson } 14806163b5d4SDoug Thompson 14816163b5d4SDoug Thompson /* Hack for the time being - Can we get this from BIOS?? */ 14826163b5d4SDoug Thompson #define CH0SPARE_RANK 0 14836163b5d4SDoug Thompson #define CH1SPARE_RANK 1 14846163b5d4SDoug Thompson 14856163b5d4SDoug Thompson /* 14866163b5d4SDoug Thompson * checks if the csrow passed in is marked as SPARED, if so returns the new 14876163b5d4SDoug Thompson * spare row 14886163b5d4SDoug Thompson */ 14896163b5d4SDoug Thompson static inline int f10_process_possible_spare(int csrow, 14906163b5d4SDoug Thompson u32 cs, struct amd64_pvt *pvt) 14916163b5d4SDoug Thompson { 14926163b5d4SDoug Thompson u32 swap_done; 14936163b5d4SDoug Thompson u32 bad_dram_cs; 14946163b5d4SDoug Thompson 14956163b5d4SDoug Thompson /* Depending on channel, isolate respective SPARING info */ 14966163b5d4SDoug Thompson if (cs) { 14976163b5d4SDoug Thompson swap_done = F10_ONLINE_SPARE_SWAPDONE1(pvt->online_spare); 14986163b5d4SDoug Thompson bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS1(pvt->online_spare); 14996163b5d4SDoug Thompson if (swap_done && (csrow == bad_dram_cs)) 15006163b5d4SDoug Thompson csrow = CH1SPARE_RANK; 15016163b5d4SDoug Thompson } else { 15026163b5d4SDoug Thompson swap_done = F10_ONLINE_SPARE_SWAPDONE0(pvt->online_spare); 15036163b5d4SDoug Thompson bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS0(pvt->online_spare); 15046163b5d4SDoug Thompson if (swap_done && (csrow == bad_dram_cs)) 15056163b5d4SDoug Thompson csrow = CH0SPARE_RANK; 15066163b5d4SDoug Thompson } 15076163b5d4SDoug Thompson return csrow; 15086163b5d4SDoug Thompson } 15096163b5d4SDoug Thompson 15106163b5d4SDoug Thompson /* 15116163b5d4SDoug Thompson * Iterate over the DRAM DCT "base" and "mask" registers looking for a 15126163b5d4SDoug Thompson * SystemAddr match on the specified 'ChannelSelect' and 'NodeID' 15136163b5d4SDoug Thompson * 15146163b5d4SDoug Thompson * Return: 15156163b5d4SDoug Thompson * -EINVAL: NOT FOUND 15166163b5d4SDoug Thompson * 0..csrow = Chip-Select Row 15176163b5d4SDoug Thompson */ 15186163b5d4SDoug Thompson static int f10_lookup_addr_in_dct(u32 in_addr, u32 nid, u32 cs) 15196163b5d4SDoug Thompson { 15206163b5d4SDoug Thompson struct mem_ctl_info *mci; 15216163b5d4SDoug Thompson struct amd64_pvt *pvt; 15226163b5d4SDoug Thompson u32 cs_base, cs_mask; 15236163b5d4SDoug Thompson int cs_found = -EINVAL; 15246163b5d4SDoug Thompson int csrow; 15256163b5d4SDoug Thompson 15266163b5d4SDoug Thompson mci = mci_lookup[nid]; 15276163b5d4SDoug Thompson if (!mci) 15286163b5d4SDoug Thompson return cs_found; 15296163b5d4SDoug Thompson 15306163b5d4SDoug Thompson pvt = mci->pvt_info; 15316163b5d4SDoug Thompson 15326163b5d4SDoug Thompson debugf1("InputAddr=0x%x channelselect=%d\n", in_addr, cs); 15336163b5d4SDoug Thompson 15346163b5d4SDoug Thompson for (csrow = 0; csrow < CHIPSELECT_COUNT; csrow++) { 15356163b5d4SDoug Thompson 15366163b5d4SDoug Thompson cs_base = amd64_get_dct_base(pvt, cs, csrow); 15376163b5d4SDoug Thompson if (!(cs_base & K8_DCSB_CS_ENABLE)) 15386163b5d4SDoug Thompson continue; 15396163b5d4SDoug Thompson 15406163b5d4SDoug Thompson /* 15416163b5d4SDoug Thompson * We have an ENABLED CSROW, Isolate just the MASK bits of the 15426163b5d4SDoug Thompson * target: [28:19] and [13:5], which map to [36:27] and [21:13] 15436163b5d4SDoug Thompson * of the actual address. 15446163b5d4SDoug Thompson */ 15456163b5d4SDoug Thompson cs_base &= REV_F_F1Xh_DCSB_BASE_BITS; 15466163b5d4SDoug Thompson 15476163b5d4SDoug Thompson /* 15486163b5d4SDoug Thompson * Get the DCT Mask, and ENABLE the reserved bits: [18:16] and 15496163b5d4SDoug Thompson * [4:0] to become ON. Then mask off bits [28:0] ([36:8]) 15506163b5d4SDoug Thompson */ 15516163b5d4SDoug Thompson cs_mask = amd64_get_dct_mask(pvt, cs, csrow); 15526163b5d4SDoug Thompson 15536163b5d4SDoug Thompson debugf1(" CSROW=%d CSBase=0x%x RAW CSMask=0x%x\n", 15546163b5d4SDoug Thompson csrow, cs_base, cs_mask); 15556163b5d4SDoug Thompson 15566163b5d4SDoug Thompson cs_mask = (cs_mask | 0x0007C01F) & 0x1FFFFFFF; 15576163b5d4SDoug Thompson 15586163b5d4SDoug Thompson debugf1(" Final CSMask=0x%x\n", cs_mask); 15596163b5d4SDoug Thompson debugf1(" (InputAddr & ~CSMask)=0x%x " 15606163b5d4SDoug Thompson "(CSBase & ~CSMask)=0x%x\n", 15616163b5d4SDoug Thompson (in_addr & ~cs_mask), (cs_base & ~cs_mask)); 15626163b5d4SDoug Thompson 15636163b5d4SDoug Thompson if ((in_addr & ~cs_mask) == (cs_base & ~cs_mask)) { 15646163b5d4SDoug Thompson cs_found = f10_process_possible_spare(csrow, cs, pvt); 15656163b5d4SDoug Thompson 15666163b5d4SDoug Thompson debugf1(" MATCH csrow=%d\n", cs_found); 15676163b5d4SDoug Thompson break; 15686163b5d4SDoug Thompson } 15696163b5d4SDoug Thompson } 15706163b5d4SDoug Thompson return cs_found; 15716163b5d4SDoug Thompson } 15726163b5d4SDoug Thompson 1573f71d0a05SDoug Thompson /* For a given @dram_range, check if @sys_addr falls within it. */ 1574f71d0a05SDoug Thompson static int f10_match_to_this_node(struct amd64_pvt *pvt, int dram_range, 1575f71d0a05SDoug Thompson u64 sys_addr, int *nid, int *chan_sel) 1576f71d0a05SDoug Thompson { 1577f71d0a05SDoug Thompson int node_id, cs_found = -EINVAL, high_range = 0; 1578f71d0a05SDoug Thompson u32 intlv_en, intlv_sel, intlv_shift, hole_off; 1579f71d0a05SDoug Thompson u32 hole_valid, tmp, dct_sel_base, channel; 1580f71d0a05SDoug Thompson u64 dram_base, chan_addr, dct_sel_base_off; 1581f71d0a05SDoug Thompson 1582f71d0a05SDoug Thompson dram_base = pvt->dram_base[dram_range]; 1583f71d0a05SDoug Thompson intlv_en = pvt->dram_IntlvEn[dram_range]; 1584f71d0a05SDoug Thompson 1585f71d0a05SDoug Thompson node_id = pvt->dram_DstNode[dram_range]; 1586f71d0a05SDoug Thompson intlv_sel = pvt->dram_IntlvSel[dram_range]; 1587f71d0a05SDoug Thompson 1588f71d0a05SDoug Thompson debugf1("(dram=%d) Base=0x%llx SystemAddr= 0x%llx Limit=0x%llx\n", 1589f71d0a05SDoug Thompson dram_range, dram_base, sys_addr, pvt->dram_limit[dram_range]); 1590f71d0a05SDoug Thompson 1591f71d0a05SDoug Thompson /* 1592f71d0a05SDoug Thompson * This assumes that one node's DHAR is the same as all the other 1593f71d0a05SDoug Thompson * nodes' DHAR. 1594f71d0a05SDoug Thompson */ 1595f71d0a05SDoug Thompson hole_off = (pvt->dhar & 0x0000FF80); 1596f71d0a05SDoug Thompson hole_valid = (pvt->dhar & 0x1); 1597f71d0a05SDoug Thompson dct_sel_base_off = (pvt->dram_ctl_select_high & 0xFFFFFC00) << 16; 1598f71d0a05SDoug Thompson 1599f71d0a05SDoug Thompson debugf1(" HoleOffset=0x%x HoleValid=0x%x IntlvSel=0x%x\n", 1600f71d0a05SDoug Thompson hole_off, hole_valid, intlv_sel); 1601f71d0a05SDoug Thompson 1602f71d0a05SDoug Thompson if (intlv_en || 1603f71d0a05SDoug Thompson (intlv_sel != ((sys_addr >> 12) & intlv_en))) 1604f71d0a05SDoug Thompson return -EINVAL; 1605f71d0a05SDoug Thompson 1606f71d0a05SDoug Thompson dct_sel_base = dct_sel_baseaddr(pvt); 1607f71d0a05SDoug Thompson 1608f71d0a05SDoug Thompson /* 1609f71d0a05SDoug Thompson * check whether addresses >= DctSelBaseAddr[47:27] are to be used to 1610f71d0a05SDoug Thompson * select between DCT0 and DCT1. 1611f71d0a05SDoug Thompson */ 1612f71d0a05SDoug Thompson if (dct_high_range_enabled(pvt) && 1613f71d0a05SDoug Thompson !dct_ganging_enabled(pvt) && 1614f71d0a05SDoug Thompson ((sys_addr >> 27) >= (dct_sel_base >> 11))) 1615f71d0a05SDoug Thompson high_range = 1; 1616f71d0a05SDoug Thompson 1617f71d0a05SDoug Thompson channel = f10_determine_channel(pvt, sys_addr, high_range, intlv_en); 1618f71d0a05SDoug Thompson 1619f71d0a05SDoug Thompson chan_addr = f10_get_base_addr_offset(sys_addr, high_range, dct_sel_base, 1620f71d0a05SDoug Thompson dct_sel_base_off, hole_valid, 1621f71d0a05SDoug Thompson hole_off, dram_base); 1622f71d0a05SDoug Thompson 1623f71d0a05SDoug Thompson intlv_shift = f10_map_intlv_en_to_shift(intlv_en); 1624f71d0a05SDoug Thompson 1625f71d0a05SDoug Thompson /* remove Node ID (in case of memory interleaving) */ 1626f71d0a05SDoug Thompson tmp = chan_addr & 0xFC0; 1627f71d0a05SDoug Thompson 1628f71d0a05SDoug Thompson chan_addr = ((chan_addr >> intlv_shift) & 0xFFFFFFFFF000ULL) | tmp; 1629f71d0a05SDoug Thompson 1630f71d0a05SDoug Thompson /* remove channel interleave and hash */ 1631f71d0a05SDoug Thompson if (dct_interleave_enabled(pvt) && 1632f71d0a05SDoug Thompson !dct_high_range_enabled(pvt) && 1633f71d0a05SDoug Thompson !dct_ganging_enabled(pvt)) { 1634f71d0a05SDoug Thompson if (dct_sel_interleave_addr(pvt) != 1) 1635f71d0a05SDoug Thompson chan_addr = (chan_addr >> 1) & 0xFFFFFFFFFFFFFFC0ULL; 1636f71d0a05SDoug Thompson else { 1637f71d0a05SDoug Thompson tmp = chan_addr & 0xFC0; 1638f71d0a05SDoug Thompson chan_addr = ((chan_addr & 0xFFFFFFFFFFFFC000ULL) >> 1) 1639f71d0a05SDoug Thompson | tmp; 1640f71d0a05SDoug Thompson } 1641f71d0a05SDoug Thompson } 1642f71d0a05SDoug Thompson 1643f71d0a05SDoug Thompson debugf1(" (ChannelAddrLong=0x%llx) >> 8 becomes InputAddr=0x%x\n", 1644f71d0a05SDoug Thompson chan_addr, (u32)(chan_addr >> 8)); 1645f71d0a05SDoug Thompson 1646f71d0a05SDoug Thompson cs_found = f10_lookup_addr_in_dct(chan_addr >> 8, node_id, channel); 1647f71d0a05SDoug Thompson 1648f71d0a05SDoug Thompson if (cs_found >= 0) { 1649f71d0a05SDoug Thompson *nid = node_id; 1650f71d0a05SDoug Thompson *chan_sel = channel; 1651f71d0a05SDoug Thompson } 1652f71d0a05SDoug Thompson return cs_found; 1653f71d0a05SDoug Thompson } 1654f71d0a05SDoug Thompson 1655f71d0a05SDoug Thompson static int f10_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr, 1656f71d0a05SDoug Thompson int *node, int *chan_sel) 1657f71d0a05SDoug Thompson { 1658f71d0a05SDoug Thompson int dram_range, cs_found = -EINVAL; 1659f71d0a05SDoug Thompson u64 dram_base, dram_limit; 1660f71d0a05SDoug Thompson 1661f71d0a05SDoug Thompson for (dram_range = 0; dram_range < DRAM_REG_COUNT; dram_range++) { 1662f71d0a05SDoug Thompson 1663f71d0a05SDoug Thompson if (!pvt->dram_rw_en[dram_range]) 1664f71d0a05SDoug Thompson continue; 1665f71d0a05SDoug Thompson 1666f71d0a05SDoug Thompson dram_base = pvt->dram_base[dram_range]; 1667f71d0a05SDoug Thompson dram_limit = pvt->dram_limit[dram_range]; 1668f71d0a05SDoug Thompson 1669f71d0a05SDoug Thompson if ((dram_base <= sys_addr) && (sys_addr <= dram_limit)) { 1670f71d0a05SDoug Thompson 1671f71d0a05SDoug Thompson cs_found = f10_match_to_this_node(pvt, dram_range, 1672f71d0a05SDoug Thompson sys_addr, node, 1673f71d0a05SDoug Thompson chan_sel); 1674f71d0a05SDoug Thompson if (cs_found >= 0) 1675f71d0a05SDoug Thompson break; 1676f71d0a05SDoug Thompson } 1677f71d0a05SDoug Thompson } 1678f71d0a05SDoug Thompson return cs_found; 1679f71d0a05SDoug Thompson } 1680f71d0a05SDoug Thompson 1681f71d0a05SDoug Thompson /* 1682f71d0a05SDoug Thompson * This the F10h reference code from AMD to map a @sys_addr to NodeID, 1683f71d0a05SDoug Thompson * CSROW, Channel. 1684f71d0a05SDoug Thompson * 1685f71d0a05SDoug Thompson * The @sys_addr is usually an error address received from the hardware. 1686f71d0a05SDoug Thompson */ 1687f71d0a05SDoug Thompson static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci, 1688f71d0a05SDoug Thompson struct amd64_error_info_regs *info, 1689f71d0a05SDoug Thompson u64 sys_addr) 1690f71d0a05SDoug Thompson { 1691f71d0a05SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 1692f71d0a05SDoug Thompson u32 page, offset; 1693f71d0a05SDoug Thompson unsigned short syndrome; 1694f71d0a05SDoug Thompson int nid, csrow, chan = 0; 1695f71d0a05SDoug Thompson 1696f71d0a05SDoug Thompson csrow = f10_translate_sysaddr_to_cs(pvt, sys_addr, &nid, &chan); 1697f71d0a05SDoug Thompson 1698f71d0a05SDoug Thompson if (csrow >= 0) { 1699f71d0a05SDoug Thompson error_address_to_page_and_offset(sys_addr, &page, &offset); 1700f71d0a05SDoug Thompson 1701f71d0a05SDoug Thompson syndrome = EXTRACT_HIGH_SYNDROME(info->nbsl) << 8; 1702f71d0a05SDoug Thompson syndrome |= EXTRACT_LOW_SYNDROME(info->nbsh); 1703f71d0a05SDoug Thompson 1704f71d0a05SDoug Thompson /* 1705f71d0a05SDoug Thompson * Is CHIPKILL on? If so, then we can attempt to use the 1706f71d0a05SDoug Thompson * syndrome to isolate which channel the error was on. 1707f71d0a05SDoug Thompson */ 1708f71d0a05SDoug Thompson if (pvt->nbcfg & K8_NBCFG_CHIPKILL) 1709f71d0a05SDoug Thompson chan = get_channel_from_ecc_syndrome(syndrome); 1710f71d0a05SDoug Thompson 1711f71d0a05SDoug Thompson if (chan >= 0) { 1712f71d0a05SDoug Thompson edac_mc_handle_ce(mci, page, offset, syndrome, 1713f71d0a05SDoug Thompson csrow, chan, EDAC_MOD_STR); 1714f71d0a05SDoug Thompson } else { 1715f71d0a05SDoug Thompson /* 1716f71d0a05SDoug Thompson * Channel unknown, report all channels on this 1717f71d0a05SDoug Thompson * CSROW as failed. 1718f71d0a05SDoug Thompson */ 1719f71d0a05SDoug Thompson for (chan = 0; chan < mci->csrows[csrow].nr_channels; 1720f71d0a05SDoug Thompson chan++) { 1721f71d0a05SDoug Thompson edac_mc_handle_ce(mci, page, offset, 1722f71d0a05SDoug Thompson syndrome, 1723f71d0a05SDoug Thompson csrow, chan, 1724f71d0a05SDoug Thompson EDAC_MOD_STR); 1725f71d0a05SDoug Thompson } 1726f71d0a05SDoug Thompson } 1727f71d0a05SDoug Thompson 1728f71d0a05SDoug Thompson } else { 1729f71d0a05SDoug Thompson edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); 1730f71d0a05SDoug Thompson } 1731f71d0a05SDoug Thompson } 1732f71d0a05SDoug Thompson 1733f71d0a05SDoug Thompson /* 1734f71d0a05SDoug Thompson * Input (@index) is the DBAM DIMM value (1 of 4) used as an index into a shift 1735f71d0a05SDoug Thompson * table (revf_quad_ddr2_shift) which starts at 128MB DIMM size. Index of 0 1736f71d0a05SDoug Thompson * indicates an empty DIMM slot, as reported by Hardware on empty slots. 1737f71d0a05SDoug Thompson * 1738f71d0a05SDoug Thompson * Normalize to 128MB by subracting 27 bit shift. 1739f71d0a05SDoug Thompson */ 1740f71d0a05SDoug Thompson static int map_dbam_to_csrow_size(int index) 1741f71d0a05SDoug Thompson { 1742f71d0a05SDoug Thompson int mega_bytes = 0; 1743f71d0a05SDoug Thompson 1744f71d0a05SDoug Thompson if (index > 0 && index <= DBAM_MAX_VALUE) 1745f71d0a05SDoug Thompson mega_bytes = ((128 << (revf_quad_ddr2_shift[index]-27))); 1746f71d0a05SDoug Thompson 1747f71d0a05SDoug Thompson return mega_bytes; 1748f71d0a05SDoug Thompson } 1749f71d0a05SDoug Thompson 1750f71d0a05SDoug Thompson /* 1751f71d0a05SDoug Thompson * debug routine to display the memory sizes of a DIMM (ganged or not) and it 1752f71d0a05SDoug Thompson * CSROWs as well 1753f71d0a05SDoug Thompson */ 1754f71d0a05SDoug Thompson static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt, 1755f71d0a05SDoug Thompson int ganged) 1756f71d0a05SDoug Thompson { 1757f71d0a05SDoug Thompson int dimm, size0, size1; 1758f71d0a05SDoug Thompson u32 dbam; 1759f71d0a05SDoug Thompson u32 *dcsb; 1760f71d0a05SDoug Thompson 1761f71d0a05SDoug Thompson debugf1(" dbam%d: 0x%8.08x CSROW is %s\n", ctrl, 1762f71d0a05SDoug Thompson ctrl ? pvt->dbam1 : pvt->dbam0, 1763f71d0a05SDoug Thompson ganged ? "GANGED - dbam1 not used" : "NON-GANGED"); 1764f71d0a05SDoug Thompson 1765f71d0a05SDoug Thompson dbam = ctrl ? pvt->dbam1 : pvt->dbam0; 1766f71d0a05SDoug Thompson dcsb = ctrl ? pvt->dcsb1 : pvt->dcsb0; 1767f71d0a05SDoug Thompson 1768f71d0a05SDoug Thompson /* Dump memory sizes for DIMM and its CSROWs */ 1769f71d0a05SDoug Thompson for (dimm = 0; dimm < 4; dimm++) { 1770f71d0a05SDoug Thompson 1771f71d0a05SDoug Thompson size0 = 0; 1772f71d0a05SDoug Thompson if (dcsb[dimm*2] & K8_DCSB_CS_ENABLE) 1773f71d0a05SDoug Thompson size0 = map_dbam_to_csrow_size(DBAM_DIMM(dimm, dbam)); 1774f71d0a05SDoug Thompson 1775f71d0a05SDoug Thompson size1 = 0; 1776f71d0a05SDoug Thompson if (dcsb[dimm*2 + 1] & K8_DCSB_CS_ENABLE) 1777f71d0a05SDoug Thompson size1 = map_dbam_to_csrow_size(DBAM_DIMM(dimm, dbam)); 1778f71d0a05SDoug Thompson 1779f71d0a05SDoug Thompson debugf1(" CTRL-%d DIMM-%d=%5dMB CSROW-%d=%5dMB " 1780f71d0a05SDoug Thompson "CSROW-%d=%5dMB\n", 1781f71d0a05SDoug Thompson ctrl, 1782f71d0a05SDoug Thompson dimm, 1783f71d0a05SDoug Thompson size0 + size1, 1784f71d0a05SDoug Thompson dimm * 2, 1785f71d0a05SDoug Thompson size0, 1786f71d0a05SDoug Thompson dimm * 2 + 1, 1787f71d0a05SDoug Thompson size1); 1788f71d0a05SDoug Thompson } 1789f71d0a05SDoug Thompson } 1790f71d0a05SDoug Thompson 1791f71d0a05SDoug Thompson /* 1792f71d0a05SDoug Thompson * Very early hardware probe on pci_probe thread to determine if this module 1793f71d0a05SDoug Thompson * supports the hardware. 1794f71d0a05SDoug Thompson * 1795f71d0a05SDoug Thompson * Return: 1796f71d0a05SDoug Thompson * 0 for OK 1797f71d0a05SDoug Thompson * 1 for error 1798f71d0a05SDoug Thompson */ 1799f71d0a05SDoug Thompson static int f10_probe_valid_hardware(struct amd64_pvt *pvt) 1800f71d0a05SDoug Thompson { 1801f71d0a05SDoug Thompson int ret = 0; 1802f71d0a05SDoug Thompson 1803f71d0a05SDoug Thompson /* 1804f71d0a05SDoug Thompson * If we are on a DDR3 machine, we don't know yet if 1805f71d0a05SDoug Thompson * we support that properly at this time 1806f71d0a05SDoug Thompson */ 1807f71d0a05SDoug Thompson if ((pvt->dchr0 & F10_DCHR_Ddr3Mode) || 1808f71d0a05SDoug Thompson (pvt->dchr1 & F10_DCHR_Ddr3Mode)) { 1809f71d0a05SDoug Thompson 1810f71d0a05SDoug Thompson amd64_printk(KERN_WARNING, 1811f71d0a05SDoug Thompson "%s() This machine is running with DDR3 memory. " 1812f71d0a05SDoug Thompson "This is not currently supported. " 1813f71d0a05SDoug Thompson "DCHR0=0x%x DCHR1=0x%x\n", 1814f71d0a05SDoug Thompson __func__, pvt->dchr0, pvt->dchr1); 1815f71d0a05SDoug Thompson 1816f71d0a05SDoug Thompson amd64_printk(KERN_WARNING, 1817f71d0a05SDoug Thompson " Contact '%s' module MAINTAINER to help add" 1818f71d0a05SDoug Thompson " support.\n", 1819f71d0a05SDoug Thompson EDAC_MOD_STR); 1820f71d0a05SDoug Thompson 1821f71d0a05SDoug Thompson ret = 1; 1822f71d0a05SDoug Thompson 1823f71d0a05SDoug Thompson } 1824f71d0a05SDoug Thompson return ret; 1825f71d0a05SDoug Thompson } 18266163b5d4SDoug Thompson 18274d37607aSDoug Thompson /* 18284d37607aSDoug Thompson * There currently are 3 types type of MC devices for AMD Athlon/Opterons 18294d37607aSDoug Thompson * (as per PCI DEVICE_IDs): 18304d37607aSDoug Thompson * 18314d37607aSDoug Thompson * Family K8: That is the Athlon64 and Opteron CPUs. They all have the same PCI 18324d37607aSDoug Thompson * DEVICE ID, even though there is differences between the different Revisions 18334d37607aSDoug Thompson * (CG,D,E,F). 18344d37607aSDoug Thompson * 18354d37607aSDoug Thompson * Family F10h and F11h. 18364d37607aSDoug Thompson * 18374d37607aSDoug Thompson */ 18384d37607aSDoug Thompson static struct amd64_family_type amd64_family_types[] = { 18394d37607aSDoug Thompson [K8_CPUS] = { 18404d37607aSDoug Thompson .ctl_name = "RevF", 18414d37607aSDoug Thompson .addr_f1_ctl = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP, 18424d37607aSDoug Thompson .misc_f3_ctl = PCI_DEVICE_ID_AMD_K8_NB_MISC, 18434d37607aSDoug Thompson .ops = { 18444d37607aSDoug Thompson .early_channel_count = k8_early_channel_count, 18454d37607aSDoug Thompson .get_error_address = k8_get_error_address, 18464d37607aSDoug Thompson .read_dram_base_limit = k8_read_dram_base_limit, 18474d37607aSDoug Thompson .map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow, 18484d37607aSDoug Thompson .dbam_map_to_pages = k8_dbam_map_to_pages, 18494d37607aSDoug Thompson } 18504d37607aSDoug Thompson }, 18514d37607aSDoug Thompson [F10_CPUS] = { 18524d37607aSDoug Thompson .ctl_name = "Family 10h", 18534d37607aSDoug Thompson .addr_f1_ctl = PCI_DEVICE_ID_AMD_10H_NB_MAP, 18544d37607aSDoug Thompson .misc_f3_ctl = PCI_DEVICE_ID_AMD_10H_NB_MISC, 18554d37607aSDoug Thompson .ops = { 18564d37607aSDoug Thompson .probe_valid_hardware = f10_probe_valid_hardware, 18574d37607aSDoug Thompson .early_channel_count = f10_early_channel_count, 18584d37607aSDoug Thompson .get_error_address = f10_get_error_address, 18594d37607aSDoug Thompson .read_dram_base_limit = f10_read_dram_base_limit, 18604d37607aSDoug Thompson .read_dram_ctl_register = f10_read_dram_ctl_register, 18614d37607aSDoug Thompson .map_sysaddr_to_csrow = f10_map_sysaddr_to_csrow, 18624d37607aSDoug Thompson .dbam_map_to_pages = f10_dbam_map_to_pages, 18634d37607aSDoug Thompson } 18644d37607aSDoug Thompson }, 18654d37607aSDoug Thompson [F11_CPUS] = { 18664d37607aSDoug Thompson .ctl_name = "Family 11h", 18674d37607aSDoug Thompson .addr_f1_ctl = PCI_DEVICE_ID_AMD_11H_NB_MAP, 18684d37607aSDoug Thompson .misc_f3_ctl = PCI_DEVICE_ID_AMD_11H_NB_MISC, 18694d37607aSDoug Thompson .ops = { 18704d37607aSDoug Thompson .probe_valid_hardware = f10_probe_valid_hardware, 18714d37607aSDoug Thompson .early_channel_count = f10_early_channel_count, 18724d37607aSDoug Thompson .get_error_address = f10_get_error_address, 18734d37607aSDoug Thompson .read_dram_base_limit = f10_read_dram_base_limit, 18744d37607aSDoug Thompson .read_dram_ctl_register = f10_read_dram_ctl_register, 18754d37607aSDoug Thompson .map_sysaddr_to_csrow = f10_map_sysaddr_to_csrow, 18764d37607aSDoug Thompson .dbam_map_to_pages = f10_dbam_map_to_pages, 18774d37607aSDoug Thompson } 18784d37607aSDoug Thompson }, 18794d37607aSDoug Thompson }; 18804d37607aSDoug Thompson 18814d37607aSDoug Thompson static struct pci_dev *pci_get_related_function(unsigned int vendor, 18824d37607aSDoug Thompson unsigned int device, 18834d37607aSDoug Thompson struct pci_dev *related) 18844d37607aSDoug Thompson { 18854d37607aSDoug Thompson struct pci_dev *dev = NULL; 18864d37607aSDoug Thompson 18874d37607aSDoug Thompson dev = pci_get_device(vendor, device, dev); 18884d37607aSDoug Thompson while (dev) { 18894d37607aSDoug Thompson if ((dev->bus->number == related->bus->number) && 18904d37607aSDoug Thompson (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn))) 18914d37607aSDoug Thompson break; 18924d37607aSDoug Thompson dev = pci_get_device(vendor, device, dev); 18934d37607aSDoug Thompson } 18944d37607aSDoug Thompson 18954d37607aSDoug Thompson return dev; 18964d37607aSDoug Thompson } 18974d37607aSDoug Thompson 1898b1289d6fSDoug Thompson /* 1899b1289d6fSDoug Thompson * syndrome mapping table for ECC ChipKill devices 1900b1289d6fSDoug Thompson * 1901b1289d6fSDoug Thompson * The comment in each row is the token (nibble) number that is in error. 1902b1289d6fSDoug Thompson * The least significant nibble of the syndrome is the mask for the bits 1903b1289d6fSDoug Thompson * that are in error (need to be toggled) for the particular nibble. 1904b1289d6fSDoug Thompson * 1905b1289d6fSDoug Thompson * Each row contains 16 entries. 1906b1289d6fSDoug Thompson * The first entry (0th) is the channel number for that row of syndromes. 1907b1289d6fSDoug Thompson * The remaining 15 entries are the syndromes for the respective Error 1908b1289d6fSDoug Thompson * bit mask index. 1909b1289d6fSDoug Thompson * 1910b1289d6fSDoug Thompson * 1st index entry is 0x0001 mask, indicating that the rightmost bit is the 1911b1289d6fSDoug Thompson * bit in error. 1912b1289d6fSDoug Thompson * The 2nd index entry is 0x0010 that the second bit is damaged. 1913b1289d6fSDoug Thompson * The 3rd index entry is 0x0011 indicating that the rightmost 2 bits 1914b1289d6fSDoug Thompson * are damaged. 1915b1289d6fSDoug Thompson * Thus so on until index 15, 0x1111, whose entry has the syndrome 1916b1289d6fSDoug Thompson * indicating that all 4 bits are damaged. 1917b1289d6fSDoug Thompson * 1918b1289d6fSDoug Thompson * A search is performed on this table looking for a given syndrome. 1919b1289d6fSDoug Thompson * 1920b1289d6fSDoug Thompson * See the AMD documentation for ECC syndromes. This ECC table is valid 1921b1289d6fSDoug Thompson * across all the versions of the AMD64 processors. 1922b1289d6fSDoug Thompson * 1923b1289d6fSDoug Thompson * A fast lookup is to use the LAST four bits of the 16-bit syndrome as a 1924b1289d6fSDoug Thompson * COLUMN index, then search all ROWS of that column, looking for a match 1925b1289d6fSDoug Thompson * with the input syndrome. The ROW value will be the token number. 1926b1289d6fSDoug Thompson * 1927b1289d6fSDoug Thompson * The 0'th entry on that row, can be returned as the CHANNEL (0 or 1) of this 1928b1289d6fSDoug Thompson * error. 1929b1289d6fSDoug Thompson */ 1930b1289d6fSDoug Thompson #define NUMBER_ECC_ROWS 36 1931b1289d6fSDoug Thompson static const unsigned short ecc_chipkill_syndromes[NUMBER_ECC_ROWS][16] = { 1932b1289d6fSDoug Thompson /* Channel 0 syndromes */ 1933b1289d6fSDoug Thompson {/*0*/ 0, 0xe821, 0x7c32, 0x9413, 0xbb44, 0x5365, 0xc776, 0x2f57, 1934b1289d6fSDoug Thompson 0xdd88, 0x35a9, 0xa1ba, 0x499b, 0x66cc, 0x8eed, 0x1afe, 0xf2df }, 1935b1289d6fSDoug Thompson {/*1*/ 0, 0x5d31, 0xa612, 0xfb23, 0x9584, 0xc8b5, 0x3396, 0x6ea7, 1936b1289d6fSDoug Thompson 0xeac8, 0xb7f9, 0x4cda, 0x11eb, 0x7f4c, 0x227d, 0xd95e, 0x846f }, 1937b1289d6fSDoug Thompson {/*2*/ 0, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007, 1938b1289d6fSDoug Thompson 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f }, 1939b1289d6fSDoug Thompson {/*3*/ 0, 0x2021, 0x3032, 0x1013, 0x4044, 0x6065, 0x7076, 0x5057, 1940b1289d6fSDoug Thompson 0x8088, 0xa0a9, 0xb0ba, 0x909b, 0xc0cc, 0xe0ed, 0xf0fe, 0xd0df }, 1941b1289d6fSDoug Thompson {/*4*/ 0, 0x5041, 0xa082, 0xf0c3, 0x9054, 0xc015, 0x30d6, 0x6097, 1942b1289d6fSDoug Thompson 0xe0a8, 0xb0e9, 0x402a, 0x106b, 0x70fc, 0x20bd, 0xd07e, 0x803f }, 1943b1289d6fSDoug Thompson {/*5*/ 0, 0xbe21, 0xd732, 0x6913, 0x2144, 0x9f65, 0xf676, 0x4857, 1944b1289d6fSDoug Thompson 0x3288, 0x8ca9, 0xe5ba, 0x5b9b, 0x13cc, 0xaded, 0xc4fe, 0x7adf }, 1945b1289d6fSDoug Thompson {/*6*/ 0, 0x4951, 0x8ea2, 0xc7f3, 0x5394, 0x1ac5, 0xdd36, 0x9467, 1946b1289d6fSDoug Thompson 0xa1e8, 0xe8b9, 0x2f4a, 0x661b, 0xf27c, 0xbb2d, 0x7cde, 0x358f }, 1947b1289d6fSDoug Thompson {/*7*/ 0, 0x74e1, 0x9872, 0xec93, 0xd6b4, 0xa255, 0x4ec6, 0x3a27, 1948b1289d6fSDoug Thompson 0x6bd8, 0x1f39, 0xf3aa, 0x874b, 0xbd6c, 0xc98d, 0x251e, 0x51ff }, 1949b1289d6fSDoug Thompson {/*8*/ 0, 0x15c1, 0x2a42, 0x3f83, 0xcef4, 0xdb35, 0xe4b6, 0xf177, 1950b1289d6fSDoug Thompson 0x4758, 0x5299, 0x6d1a, 0x78db, 0x89ac, 0x9c6d, 0xa3ee, 0xb62f }, 1951b1289d6fSDoug Thompson {/*9*/ 0, 0x3d01, 0x1602, 0x2b03, 0x8504, 0xb805, 0x9306, 0xae07, 1952b1289d6fSDoug Thompson 0xca08, 0xf709, 0xdc0a, 0xe10b, 0x4f0c, 0x720d, 0x590e, 0x640f }, 1953b1289d6fSDoug Thompson {/*a*/ 0, 0x9801, 0xec02, 0x7403, 0x6b04, 0xf305, 0x8706, 0x1f07, 1954b1289d6fSDoug Thompson 0xbd08, 0x2509, 0x510a, 0xc90b, 0xd60c, 0x4e0d, 0x3a0e, 0xa20f }, 1955b1289d6fSDoug Thompson {/*b*/ 0, 0xd131, 0x6212, 0xb323, 0x3884, 0xe9b5, 0x5a96, 0x8ba7, 1956b1289d6fSDoug Thompson 0x1cc8, 0xcdf9, 0x7eda, 0xafeb, 0x244c, 0xf57d, 0x465e, 0x976f }, 1957b1289d6fSDoug Thompson {/*c*/ 0, 0xe1d1, 0x7262, 0x93b3, 0xb834, 0x59e5, 0xca56, 0x2b87, 1958b1289d6fSDoug Thompson 0xdc18, 0x3dc9, 0xae7a, 0x4fab, 0x542c, 0x85fd, 0x164e, 0xf79f }, 1959b1289d6fSDoug Thompson {/*d*/ 0, 0x6051, 0xb0a2, 0xd0f3, 0x1094, 0x70c5, 0xa036, 0xc067, 1960b1289d6fSDoug Thompson 0x20e8, 0x40b9, 0x904a, 0x601b, 0x307c, 0x502d, 0x80de, 0xe08f }, 1961b1289d6fSDoug Thompson {/*e*/ 0, 0xa4c1, 0xf842, 0x5c83, 0xe6f4, 0x4235, 0x1eb6, 0xba77, 1962b1289d6fSDoug Thompson 0x7b58, 0xdf99, 0x831a, 0x27db, 0x9dac, 0x396d, 0x65ee, 0xc12f }, 1963b1289d6fSDoug Thompson {/*f*/ 0, 0x11c1, 0x2242, 0x3383, 0xc8f4, 0xd935, 0xeab6, 0xfb77, 1964b1289d6fSDoug Thompson 0x4c58, 0x5d99, 0x6e1a, 0x7fdb, 0x84ac, 0x956d, 0xa6ee, 0xb72f }, 19654d37607aSDoug Thompson 1966b1289d6fSDoug Thompson /* Channel 1 syndromes */ 1967b1289d6fSDoug Thompson {/*10*/ 1, 0x45d1, 0x8a62, 0xcfb3, 0x5e34, 0x1be5, 0xd456, 0x9187, 1968b1289d6fSDoug Thompson 0xa718, 0xe2c9, 0x2d7a, 0x68ab, 0xf92c, 0xbcfd, 0x734e, 0x369f }, 1969b1289d6fSDoug Thompson {/*11*/ 1, 0x63e1, 0xb172, 0xd293, 0x14b4, 0x7755, 0xa5c6, 0xc627, 1970b1289d6fSDoug Thompson 0x28d8, 0x4b39, 0x99aa, 0xfa4b, 0x3c6c, 0x5f8d, 0x8d1e, 0xeeff }, 1971b1289d6fSDoug Thompson {/*12*/ 1, 0xb741, 0xd982, 0x6ec3, 0x2254, 0x9515, 0xfbd6, 0x4c97, 1972b1289d6fSDoug Thompson 0x33a8, 0x84e9, 0xea2a, 0x5d6b, 0x11fc, 0xa6bd, 0xc87e, 0x7f3f }, 1973b1289d6fSDoug Thompson {/*13*/ 1, 0xdd41, 0x6682, 0xbbc3, 0x3554, 0xe815, 0x53d6, 0xce97, 1974b1289d6fSDoug Thompson 0x1aa8, 0xc7e9, 0x7c2a, 0xa1fb, 0x2ffc, 0xf2bd, 0x497e, 0x943f }, 1975b1289d6fSDoug Thompson {/*14*/ 1, 0x2bd1, 0x3d62, 0x16b3, 0x4f34, 0x64e5, 0x7256, 0x5987, 1976b1289d6fSDoug Thompson 0x8518, 0xaec9, 0xb87a, 0x93ab, 0xca2c, 0xe1fd, 0xf74e, 0xdc9f }, 1977b1289d6fSDoug Thompson {/*15*/ 1, 0x83c1, 0xc142, 0x4283, 0xa4f4, 0x2735, 0x65b6, 0xe677, 1978b1289d6fSDoug Thompson 0xf858, 0x7b99, 0x391a, 0xbadb, 0x5cac, 0xdf6d, 0x9dee, 0x1e2f }, 1979b1289d6fSDoug Thompson {/*16*/ 1, 0x8fd1, 0xc562, 0x4ab3, 0xa934, 0x26e5, 0x6c56, 0xe387, 1980b1289d6fSDoug Thompson 0xfe18, 0x71c9, 0x3b7a, 0xb4ab, 0x572c, 0xd8fd, 0x924e, 0x1d9f }, 1981b1289d6fSDoug Thompson {/*17*/ 1, 0x4791, 0x89e2, 0xce73, 0x5264, 0x15f5, 0xdb86, 0x9c17, 1982b1289d6fSDoug Thompson 0xa3b8, 0xe429, 0x2a5a, 0x6dcb, 0xf1dc, 0xb64d, 0x783e, 0x3faf }, 1983b1289d6fSDoug Thompson {/*18*/ 1, 0x5781, 0xa9c2, 0xfe43, 0x92a4, 0xc525, 0x3b66, 0x6ce7, 1984b1289d6fSDoug Thompson 0xe3f8, 0xb479, 0x4a3a, 0x1dbb, 0x715c, 0x26dd, 0xd89e, 0x8f1f }, 1985b1289d6fSDoug Thompson {/*19*/ 1, 0xbf41, 0xd582, 0x6ac3, 0x2954, 0x9615, 0xfcd6, 0x4397, 1986b1289d6fSDoug Thompson 0x3ea8, 0x81e9, 0xeb2a, 0x546b, 0x17fc, 0xa8bd, 0xc27e, 0x7d3f }, 1987b1289d6fSDoug Thompson {/*1a*/ 1, 0x9891, 0xe1e2, 0x7273, 0x6464, 0xf7f5, 0x8586, 0x1617, 1988b1289d6fSDoug Thompson 0xb8b8, 0x2b29, 0x595a, 0xcacb, 0xdcdc, 0x4f4d, 0x3d3e, 0xaeaf }, 1989b1289d6fSDoug Thompson {/*1b*/ 1, 0xcce1, 0x4472, 0x8893, 0xfdb4, 0x3f55, 0xb9c6, 0x7527, 1990b1289d6fSDoug Thompson 0x56d8, 0x9a39, 0x12aa, 0xde4b, 0xab6c, 0x678d, 0xef1e, 0x23ff }, 1991b1289d6fSDoug Thompson {/*1c*/ 1, 0xa761, 0xf9b2, 0x5ed3, 0xe214, 0x4575, 0x1ba6, 0xbcc7, 1992b1289d6fSDoug Thompson 0x7328, 0xd449, 0x8a9a, 0x2dfb, 0x913c, 0x365d, 0x688e, 0xcfef }, 1993b1289d6fSDoug Thompson {/*1d*/ 1, 0xff61, 0x55b2, 0xaad3, 0x7914, 0x8675, 0x2ca6, 0xd3c7, 1994b1289d6fSDoug Thompson 0x9e28, 0x6149, 0xcb9a, 0x34fb, 0xe73c, 0x185d, 0xb28e, 0x4def }, 1995b1289d6fSDoug Thompson {/*1e*/ 1, 0x5451, 0xa8a2, 0xfcf3, 0x9694, 0xc2c5, 0x3e36, 0x6a67, 1996b1289d6fSDoug Thompson 0xebe8, 0xbfb9, 0x434a, 0x171b, 0x7d7c, 0x292d, 0xd5de, 0x818f }, 1997b1289d6fSDoug Thompson {/*1f*/ 1, 0x6fc1, 0xb542, 0xda83, 0x19f4, 0x7635, 0xacb6, 0xc377, 1998b1289d6fSDoug Thompson 0x2e58, 0x4199, 0x9b1a, 0xf4db, 0x37ac, 0x586d, 0x82ee, 0xed2f }, 1999b1289d6fSDoug Thompson 2000b1289d6fSDoug Thompson /* ECC bits are also in the set of tokens and they too can go bad 2001b1289d6fSDoug Thompson * first 2 cover channel 0, while the second 2 cover channel 1 2002b1289d6fSDoug Thompson */ 2003b1289d6fSDoug Thompson {/*20*/ 0, 0xbe01, 0xd702, 0x6903, 0x2104, 0x9f05, 0xf606, 0x4807, 2004b1289d6fSDoug Thompson 0x3208, 0x8c09, 0xe50a, 0x5b0b, 0x130c, 0xad0d, 0xc40e, 0x7a0f }, 2005b1289d6fSDoug Thompson {/*21*/ 0, 0x4101, 0x8202, 0xc303, 0x5804, 0x1905, 0xda06, 0x9b07, 2006b1289d6fSDoug Thompson 0xac08, 0xed09, 0x2e0a, 0x6f0b, 0x640c, 0xb50d, 0x760e, 0x370f }, 2007b1289d6fSDoug Thompson {/*22*/ 1, 0xc441, 0x4882, 0x8cc3, 0xf654, 0x3215, 0xbed6, 0x7a97, 2008b1289d6fSDoug Thompson 0x5ba8, 0x9fe9, 0x132a, 0xd76b, 0xadfc, 0x69bd, 0xe57e, 0x213f }, 2009b1289d6fSDoug Thompson {/*23*/ 1, 0x7621, 0x9b32, 0xed13, 0xda44, 0xac65, 0x4176, 0x3757, 2010b1289d6fSDoug Thompson 0x6f88, 0x19a9, 0xf4ba, 0x829b, 0xb5cc, 0xc3ed, 0x2efe, 0x58df } 2011b1289d6fSDoug Thompson }; 2012b1289d6fSDoug Thompson 2013b1289d6fSDoug Thompson /* 2014b1289d6fSDoug Thompson * Given the syndrome argument, scan each of the channel tables for a syndrome 2015b1289d6fSDoug Thompson * match. Depending on which table it is found, return the channel number. 2016b1289d6fSDoug Thompson */ 2017b1289d6fSDoug Thompson static int get_channel_from_ecc_syndrome(unsigned short syndrome) 2018b1289d6fSDoug Thompson { 2019b1289d6fSDoug Thompson int row; 2020b1289d6fSDoug Thompson int column; 2021b1289d6fSDoug Thompson 2022b1289d6fSDoug Thompson /* Determine column to scan */ 2023b1289d6fSDoug Thompson column = syndrome & 0xF; 2024b1289d6fSDoug Thompson 2025b1289d6fSDoug Thompson /* Scan all rows, looking for syndrome, or end of table */ 2026b1289d6fSDoug Thompson for (row = 0; row < NUMBER_ECC_ROWS; row++) { 2027b1289d6fSDoug Thompson if (ecc_chipkill_syndromes[row][column] == syndrome) 2028b1289d6fSDoug Thompson return ecc_chipkill_syndromes[row][0]; 2029b1289d6fSDoug Thompson } 2030b1289d6fSDoug Thompson 2031b1289d6fSDoug Thompson debugf0("syndrome(%x) not found\n", syndrome); 2032b1289d6fSDoug Thompson return -1; 2033b1289d6fSDoug Thompson } 2034d27bf6faSDoug Thompson 2035d27bf6faSDoug Thompson /* 2036d27bf6faSDoug Thompson * Check for valid error in the NB Status High register. If so, proceed to read 2037d27bf6faSDoug Thompson * NB Status Low, NB Address Low and NB Address High registers and store data 2038d27bf6faSDoug Thompson * into error structure. 2039d27bf6faSDoug Thompson * 2040d27bf6faSDoug Thompson * Returns: 2041d27bf6faSDoug Thompson * - 1: if hardware regs contains valid error info 2042d27bf6faSDoug Thompson * - 0: if no valid error is indicated 2043d27bf6faSDoug Thompson */ 2044d27bf6faSDoug Thompson static int amd64_get_error_info_regs(struct mem_ctl_info *mci, 2045d27bf6faSDoug Thompson struct amd64_error_info_regs *regs) 2046d27bf6faSDoug Thompson { 2047d27bf6faSDoug Thompson struct amd64_pvt *pvt; 2048d27bf6faSDoug Thompson struct pci_dev *misc_f3_ctl; 2049d27bf6faSDoug Thompson int err = 0; 2050d27bf6faSDoug Thompson 2051d27bf6faSDoug Thompson pvt = mci->pvt_info; 2052d27bf6faSDoug Thompson misc_f3_ctl = pvt->misc_f3_ctl; 2053d27bf6faSDoug Thompson 2054d27bf6faSDoug Thompson err = pci_read_config_dword(misc_f3_ctl, K8_NBSH, ®s->nbsh); 2055d27bf6faSDoug Thompson if (err) 2056d27bf6faSDoug Thompson goto err_reg; 2057d27bf6faSDoug Thompson 2058d27bf6faSDoug Thompson if (!(regs->nbsh & K8_NBSH_VALID_BIT)) 2059d27bf6faSDoug Thompson return 0; 2060d27bf6faSDoug Thompson 2061d27bf6faSDoug Thompson /* valid error, read remaining error information registers */ 2062d27bf6faSDoug Thompson err = pci_read_config_dword(misc_f3_ctl, K8_NBSL, ®s->nbsl); 2063d27bf6faSDoug Thompson if (err) 2064d27bf6faSDoug Thompson goto err_reg; 2065d27bf6faSDoug Thompson 2066d27bf6faSDoug Thompson err = pci_read_config_dword(misc_f3_ctl, K8_NBEAL, ®s->nbeal); 2067d27bf6faSDoug Thompson if (err) 2068d27bf6faSDoug Thompson goto err_reg; 2069d27bf6faSDoug Thompson 2070d27bf6faSDoug Thompson err = pci_read_config_dword(misc_f3_ctl, K8_NBEAH, ®s->nbeah); 2071d27bf6faSDoug Thompson if (err) 2072d27bf6faSDoug Thompson goto err_reg; 2073d27bf6faSDoug Thompson 2074d27bf6faSDoug Thompson err = pci_read_config_dword(misc_f3_ctl, K8_NBCFG, ®s->nbcfg); 2075d27bf6faSDoug Thompson if (err) 2076d27bf6faSDoug Thompson goto err_reg; 2077d27bf6faSDoug Thompson 2078d27bf6faSDoug Thompson return 1; 2079d27bf6faSDoug Thompson 2080d27bf6faSDoug Thompson err_reg: 2081d27bf6faSDoug Thompson debugf0("Reading error info register failed\n"); 2082d27bf6faSDoug Thompson return 0; 2083d27bf6faSDoug Thompson } 2084d27bf6faSDoug Thompson 2085d27bf6faSDoug Thompson /* 2086d27bf6faSDoug Thompson * This function is called to retrieve the error data from hardware and store it 2087d27bf6faSDoug Thompson * in the info structure. 2088d27bf6faSDoug Thompson * 2089d27bf6faSDoug Thompson * Returns: 2090d27bf6faSDoug Thompson * - 1: if a valid error is found 2091d27bf6faSDoug Thompson * - 0: if no error is found 2092d27bf6faSDoug Thompson */ 2093d27bf6faSDoug Thompson static int amd64_get_error_info(struct mem_ctl_info *mci, 2094d27bf6faSDoug Thompson struct amd64_error_info_regs *info) 2095d27bf6faSDoug Thompson { 2096d27bf6faSDoug Thompson struct amd64_pvt *pvt; 2097d27bf6faSDoug Thompson struct amd64_error_info_regs regs; 2098d27bf6faSDoug Thompson 2099d27bf6faSDoug Thompson pvt = mci->pvt_info; 2100d27bf6faSDoug Thompson 2101d27bf6faSDoug Thompson if (!amd64_get_error_info_regs(mci, info)) 2102d27bf6faSDoug Thompson return 0; 2103d27bf6faSDoug Thompson 2104d27bf6faSDoug Thompson /* 2105d27bf6faSDoug Thompson * Here's the problem with the K8's EDAC reporting: There are four 2106d27bf6faSDoug Thompson * registers which report pieces of error information. They are shared 2107d27bf6faSDoug Thompson * between CEs and UEs. Furthermore, contrary to what is stated in the 2108d27bf6faSDoug Thompson * BKDG, the overflow bit is never used! Every error always updates the 2109d27bf6faSDoug Thompson * reporting registers. 2110d27bf6faSDoug Thompson * 2111d27bf6faSDoug Thompson * Can you see the race condition? All four error reporting registers 2112d27bf6faSDoug Thompson * must be read before a new error updates them! There is no way to read 2113d27bf6faSDoug Thompson * all four registers atomically. The best than can be done is to detect 2114d27bf6faSDoug Thompson * that a race has occured and then report the error without any kind of 2115d27bf6faSDoug Thompson * precision. 2116d27bf6faSDoug Thompson * 2117d27bf6faSDoug Thompson * What is still positive is that errors are still reported and thus 2118d27bf6faSDoug Thompson * problems can still be detected - just not localized because the 2119d27bf6faSDoug Thompson * syndrome and address are spread out across registers. 2120d27bf6faSDoug Thompson * 2121d27bf6faSDoug Thompson * Grrrrr!!!!! Here's hoping that AMD fixes this in some future K8 rev. 2122d27bf6faSDoug Thompson * UEs and CEs should have separate register sets with proper overflow 2123d27bf6faSDoug Thompson * bits that are used! At very least the problem can be fixed by 2124d27bf6faSDoug Thompson * honoring the ErrValid bit in 'nbsh' and not updating registers - just 2125d27bf6faSDoug Thompson * set the overflow bit - unless the current error is CE and the new 2126d27bf6faSDoug Thompson * error is UE which would be the only situation for overwriting the 2127d27bf6faSDoug Thompson * current values. 2128d27bf6faSDoug Thompson */ 2129d27bf6faSDoug Thompson 2130d27bf6faSDoug Thompson regs = *info; 2131d27bf6faSDoug Thompson 2132d27bf6faSDoug Thompson /* Use info from the second read - most current */ 2133d27bf6faSDoug Thompson if (unlikely(!amd64_get_error_info_regs(mci, info))) 2134d27bf6faSDoug Thompson return 0; 2135d27bf6faSDoug Thompson 2136d27bf6faSDoug Thompson /* clear the error bits in hardware */ 2137d27bf6faSDoug Thompson pci_write_bits32(pvt->misc_f3_ctl, K8_NBSH, 0, K8_NBSH_VALID_BIT); 2138d27bf6faSDoug Thompson 2139d27bf6faSDoug Thompson /* Check for the possible race condition */ 2140d27bf6faSDoug Thompson if ((regs.nbsh != info->nbsh) || 2141d27bf6faSDoug Thompson (regs.nbsl != info->nbsl) || 2142d27bf6faSDoug Thompson (regs.nbeah != info->nbeah) || 2143d27bf6faSDoug Thompson (regs.nbeal != info->nbeal)) { 2144d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_WARNING, 2145d27bf6faSDoug Thompson "hardware STATUS read access race condition " 2146d27bf6faSDoug Thompson "detected!\n"); 2147d27bf6faSDoug Thompson return 0; 2148d27bf6faSDoug Thompson } 2149d27bf6faSDoug Thompson return 1; 2150d27bf6faSDoug Thompson } 2151d27bf6faSDoug Thompson 2152d27bf6faSDoug Thompson static inline void amd64_decode_gart_tlb_error(struct mem_ctl_info *mci, 2153d27bf6faSDoug Thompson struct amd64_error_info_regs *info) 2154d27bf6faSDoug Thompson { 2155d27bf6faSDoug Thompson u32 err_code; 2156d27bf6faSDoug Thompson u32 ec_tt; /* error code transaction type (2b) */ 2157d27bf6faSDoug Thompson u32 ec_ll; /* error code cache level (2b) */ 2158d27bf6faSDoug Thompson 2159d27bf6faSDoug Thompson err_code = EXTRACT_ERROR_CODE(info->nbsl); 2160d27bf6faSDoug Thompson ec_ll = EXTRACT_LL_CODE(err_code); 2161d27bf6faSDoug Thompson ec_tt = EXTRACT_TT_CODE(err_code); 2162d27bf6faSDoug Thompson 2163d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_ERR, 2164d27bf6faSDoug Thompson "GART TLB event: transaction type(%s), " 2165d27bf6faSDoug Thompson "cache level(%s)\n", tt_msgs[ec_tt], ll_msgs[ec_ll]); 2166d27bf6faSDoug Thompson } 2167d27bf6faSDoug Thompson 2168d27bf6faSDoug Thompson static inline void amd64_decode_mem_cache_error(struct mem_ctl_info *mci, 2169d27bf6faSDoug Thompson struct amd64_error_info_regs *info) 2170d27bf6faSDoug Thompson { 2171d27bf6faSDoug Thompson u32 err_code; 2172d27bf6faSDoug Thompson u32 ec_rrrr; /* error code memory transaction (4b) */ 2173d27bf6faSDoug Thompson u32 ec_tt; /* error code transaction type (2b) */ 2174d27bf6faSDoug Thompson u32 ec_ll; /* error code cache level (2b) */ 2175d27bf6faSDoug Thompson 2176d27bf6faSDoug Thompson err_code = EXTRACT_ERROR_CODE(info->nbsl); 2177d27bf6faSDoug Thompson ec_ll = EXTRACT_LL_CODE(err_code); 2178d27bf6faSDoug Thompson ec_tt = EXTRACT_TT_CODE(err_code); 2179d27bf6faSDoug Thompson ec_rrrr = EXTRACT_RRRR_CODE(err_code); 2180d27bf6faSDoug Thompson 2181d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_ERR, 2182d27bf6faSDoug Thompson "cache hierarchy error: memory transaction type(%s), " 2183d27bf6faSDoug Thompson "transaction type(%s), cache level(%s)\n", 2184d27bf6faSDoug Thompson rrrr_msgs[ec_rrrr], tt_msgs[ec_tt], ll_msgs[ec_ll]); 2185d27bf6faSDoug Thompson } 2186d27bf6faSDoug Thompson 2187d27bf6faSDoug Thompson 2188d27bf6faSDoug Thompson /* 2189d27bf6faSDoug Thompson * Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR 2190d27bf6faSDoug Thompson * ADDRESS and process. 2191d27bf6faSDoug Thompson */ 2192d27bf6faSDoug Thompson static void amd64_handle_ce(struct mem_ctl_info *mci, 2193d27bf6faSDoug Thompson struct amd64_error_info_regs *info) 2194d27bf6faSDoug Thompson { 2195d27bf6faSDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 2196d27bf6faSDoug Thompson u64 SystemAddress; 2197d27bf6faSDoug Thompson 2198d27bf6faSDoug Thompson /* Ensure that the Error Address is VALID */ 2199d27bf6faSDoug Thompson if ((info->nbsh & K8_NBSH_VALID_ERROR_ADDR) == 0) { 2200d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_ERR, 2201d27bf6faSDoug Thompson "HW has no ERROR_ADDRESS available\n"); 2202d27bf6faSDoug Thompson edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); 2203d27bf6faSDoug Thompson return; 2204d27bf6faSDoug Thompson } 2205d27bf6faSDoug Thompson 2206d27bf6faSDoug Thompson SystemAddress = extract_error_address(mci, info); 2207d27bf6faSDoug Thompson 2208d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_ERR, 2209d27bf6faSDoug Thompson "CE ERROR_ADDRESS= 0x%llx\n", SystemAddress); 2210d27bf6faSDoug Thompson 2211d27bf6faSDoug Thompson pvt->ops->map_sysaddr_to_csrow(mci, info, SystemAddress); 2212d27bf6faSDoug Thompson } 2213d27bf6faSDoug Thompson 2214d27bf6faSDoug Thompson /* Handle any Un-correctable Errors (UEs) */ 2215d27bf6faSDoug Thompson static void amd64_handle_ue(struct mem_ctl_info *mci, 2216d27bf6faSDoug Thompson struct amd64_error_info_regs *info) 2217d27bf6faSDoug Thompson { 2218d27bf6faSDoug Thompson int csrow; 2219d27bf6faSDoug Thompson u64 SystemAddress; 2220d27bf6faSDoug Thompson u32 page, offset; 2221d27bf6faSDoug Thompson struct mem_ctl_info *log_mci, *src_mci = NULL; 2222d27bf6faSDoug Thompson 2223d27bf6faSDoug Thompson log_mci = mci; 2224d27bf6faSDoug Thompson 2225d27bf6faSDoug Thompson if ((info->nbsh & K8_NBSH_VALID_ERROR_ADDR) == 0) { 2226d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_CRIT, 2227d27bf6faSDoug Thompson "HW has no ERROR_ADDRESS available\n"); 2228d27bf6faSDoug Thompson edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); 2229d27bf6faSDoug Thompson return; 2230d27bf6faSDoug Thompson } 2231d27bf6faSDoug Thompson 2232d27bf6faSDoug Thompson SystemAddress = extract_error_address(mci, info); 2233d27bf6faSDoug Thompson 2234d27bf6faSDoug Thompson /* 2235d27bf6faSDoug Thompson * Find out which node the error address belongs to. This may be 2236d27bf6faSDoug Thompson * different from the node that detected the error. 2237d27bf6faSDoug Thompson */ 2238d27bf6faSDoug Thompson src_mci = find_mc_by_sys_addr(mci, SystemAddress); 2239d27bf6faSDoug Thompson if (!src_mci) { 2240d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_CRIT, 2241d27bf6faSDoug Thompson "ERROR ADDRESS (0x%lx) value NOT mapped to a MC\n", 2242d27bf6faSDoug Thompson (unsigned long)SystemAddress); 2243d27bf6faSDoug Thompson edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); 2244d27bf6faSDoug Thompson return; 2245d27bf6faSDoug Thompson } 2246d27bf6faSDoug Thompson 2247d27bf6faSDoug Thompson log_mci = src_mci; 2248d27bf6faSDoug Thompson 2249d27bf6faSDoug Thompson csrow = sys_addr_to_csrow(log_mci, SystemAddress); 2250d27bf6faSDoug Thompson if (csrow < 0) { 2251d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_CRIT, 2252d27bf6faSDoug Thompson "ERROR_ADDRESS (0x%lx) value NOT mapped to 'csrow'\n", 2253d27bf6faSDoug Thompson (unsigned long)SystemAddress); 2254d27bf6faSDoug Thompson edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); 2255d27bf6faSDoug Thompson } else { 2256d27bf6faSDoug Thompson error_address_to_page_and_offset(SystemAddress, &page, &offset); 2257d27bf6faSDoug Thompson edac_mc_handle_ue(log_mci, page, offset, csrow, EDAC_MOD_STR); 2258d27bf6faSDoug Thompson } 2259d27bf6faSDoug Thompson } 2260d27bf6faSDoug Thompson 2261d27bf6faSDoug Thompson static void amd64_decode_bus_error(struct mem_ctl_info *mci, 2262d27bf6faSDoug Thompson struct amd64_error_info_regs *info) 2263d27bf6faSDoug Thompson { 2264d27bf6faSDoug Thompson u32 err_code, ext_ec; 2265d27bf6faSDoug Thompson u32 ec_pp; /* error code participating processor (2p) */ 2266d27bf6faSDoug Thompson u32 ec_to; /* error code timed out (1b) */ 2267d27bf6faSDoug Thompson u32 ec_rrrr; /* error code memory transaction (4b) */ 2268d27bf6faSDoug Thompson u32 ec_ii; /* error code memory or I/O (2b) */ 2269d27bf6faSDoug Thompson u32 ec_ll; /* error code cache level (2b) */ 2270d27bf6faSDoug Thompson 2271d27bf6faSDoug Thompson ext_ec = EXTRACT_EXT_ERROR_CODE(info->nbsl); 2272d27bf6faSDoug Thompson err_code = EXTRACT_ERROR_CODE(info->nbsl); 2273d27bf6faSDoug Thompson 2274d27bf6faSDoug Thompson ec_ll = EXTRACT_LL_CODE(err_code); 2275d27bf6faSDoug Thompson ec_ii = EXTRACT_II_CODE(err_code); 2276d27bf6faSDoug Thompson ec_rrrr = EXTRACT_RRRR_CODE(err_code); 2277d27bf6faSDoug Thompson ec_to = EXTRACT_TO_CODE(err_code); 2278d27bf6faSDoug Thompson ec_pp = EXTRACT_PP_CODE(err_code); 2279d27bf6faSDoug Thompson 2280d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_ERR, 2281d27bf6faSDoug Thompson "BUS ERROR:\n" 2282d27bf6faSDoug Thompson " time-out(%s) mem or i/o(%s)\n" 2283d27bf6faSDoug Thompson " participating processor(%s)\n" 2284d27bf6faSDoug Thompson " memory transaction type(%s)\n" 2285d27bf6faSDoug Thompson " cache level(%s) Error Found by: %s\n", 2286d27bf6faSDoug Thompson to_msgs[ec_to], 2287d27bf6faSDoug Thompson ii_msgs[ec_ii], 2288d27bf6faSDoug Thompson pp_msgs[ec_pp], 2289d27bf6faSDoug Thompson rrrr_msgs[ec_rrrr], 2290d27bf6faSDoug Thompson ll_msgs[ec_ll], 2291d27bf6faSDoug Thompson (info->nbsh & K8_NBSH_ERR_SCRUBER) ? 2292d27bf6faSDoug Thompson "Scrubber" : "Normal Operation"); 2293d27bf6faSDoug Thompson 2294d27bf6faSDoug Thompson /* If this was an 'observed' error, early out */ 2295d27bf6faSDoug Thompson if (ec_pp == K8_NBSL_PP_OBS) 2296d27bf6faSDoug Thompson return; /* We aren't the node involved */ 2297d27bf6faSDoug Thompson 2298d27bf6faSDoug Thompson /* Parse out the extended error code for ECC events */ 2299d27bf6faSDoug Thompson switch (ext_ec) { 2300d27bf6faSDoug Thompson /* F10 changed to one Extended ECC error code */ 2301d27bf6faSDoug Thompson case F10_NBSL_EXT_ERR_RES: /* Reserved field */ 2302d27bf6faSDoug Thompson case F10_NBSL_EXT_ERR_ECC: /* F10 ECC ext err code */ 2303d27bf6faSDoug Thompson break; 2304d27bf6faSDoug Thompson 2305d27bf6faSDoug Thompson default: 2306d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_ERR, "NOT ECC: no special error " 2307d27bf6faSDoug Thompson "handling for this error\n"); 2308d27bf6faSDoug Thompson return; 2309d27bf6faSDoug Thompson } 2310d27bf6faSDoug Thompson 2311d27bf6faSDoug Thompson if (info->nbsh & K8_NBSH_CECC) 2312d27bf6faSDoug Thompson amd64_handle_ce(mci, info); 2313d27bf6faSDoug Thompson else if (info->nbsh & K8_NBSH_UECC) 2314d27bf6faSDoug Thompson amd64_handle_ue(mci, info); 2315d27bf6faSDoug Thompson 2316d27bf6faSDoug Thompson /* 2317d27bf6faSDoug Thompson * If main error is CE then overflow must be CE. If main error is UE 2318d27bf6faSDoug Thompson * then overflow is unknown. We'll call the overflow a CE - if 2319d27bf6faSDoug Thompson * panic_on_ue is set then we're already panic'ed and won't arrive 2320d27bf6faSDoug Thompson * here. Else, then apparently someone doesn't think that UE's are 2321d27bf6faSDoug Thompson * catastrophic. 2322d27bf6faSDoug Thompson */ 2323d27bf6faSDoug Thompson if (info->nbsh & K8_NBSH_OVERFLOW) 2324d27bf6faSDoug Thompson edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR 2325d27bf6faSDoug Thompson "Error Overflow set"); 2326d27bf6faSDoug Thompson } 2327d27bf6faSDoug Thompson 2328d27bf6faSDoug Thompson int amd64_process_error_info(struct mem_ctl_info *mci, 2329d27bf6faSDoug Thompson struct amd64_error_info_regs *info, 2330d27bf6faSDoug Thompson int handle_errors) 2331d27bf6faSDoug Thompson { 2332d27bf6faSDoug Thompson struct amd64_pvt *pvt; 2333d27bf6faSDoug Thompson struct amd64_error_info_regs *regs; 2334d27bf6faSDoug Thompson u32 err_code, ext_ec; 2335d27bf6faSDoug Thompson int gart_tlb_error = 0; 2336d27bf6faSDoug Thompson 2337d27bf6faSDoug Thompson pvt = mci->pvt_info; 2338d27bf6faSDoug Thompson 2339d27bf6faSDoug Thompson /* If caller doesn't want us to process the error, return */ 2340d27bf6faSDoug Thompson if (!handle_errors) 2341d27bf6faSDoug Thompson return 1; 2342d27bf6faSDoug Thompson 2343d27bf6faSDoug Thompson regs = info; 2344d27bf6faSDoug Thompson 2345d27bf6faSDoug Thompson debugf1("NorthBridge ERROR: mci(0x%p)\n", mci); 2346d27bf6faSDoug Thompson debugf1(" MC node(%d) Error-Address(0x%.8x-%.8x)\n", 2347d27bf6faSDoug Thompson pvt->mc_node_id, regs->nbeah, regs->nbeal); 2348d27bf6faSDoug Thompson debugf1(" nbsh(0x%.8x) nbsl(0x%.8x)\n", 2349d27bf6faSDoug Thompson regs->nbsh, regs->nbsl); 2350d27bf6faSDoug Thompson debugf1(" Valid Error=%s Overflow=%s\n", 2351d27bf6faSDoug Thompson (regs->nbsh & K8_NBSH_VALID_BIT) ? "True" : "False", 2352d27bf6faSDoug Thompson (regs->nbsh & K8_NBSH_OVERFLOW) ? "True" : "False"); 2353d27bf6faSDoug Thompson debugf1(" Err Uncorrected=%s MCA Error Reporting=%s\n", 2354d27bf6faSDoug Thompson (regs->nbsh & K8_NBSH_UNCORRECTED_ERR) ? 2355d27bf6faSDoug Thompson "True" : "False", 2356d27bf6faSDoug Thompson (regs->nbsh & K8_NBSH_ERR_ENABLE) ? 2357d27bf6faSDoug Thompson "True" : "False"); 2358d27bf6faSDoug Thompson debugf1(" MiscErr Valid=%s ErrAddr Valid=%s PCC=%s\n", 2359d27bf6faSDoug Thompson (regs->nbsh & K8_NBSH_MISC_ERR_VALID) ? 2360d27bf6faSDoug Thompson "True" : "False", 2361d27bf6faSDoug Thompson (regs->nbsh & K8_NBSH_VALID_ERROR_ADDR) ? 2362d27bf6faSDoug Thompson "True" : "False", 2363d27bf6faSDoug Thompson (regs->nbsh & K8_NBSH_PCC) ? 2364d27bf6faSDoug Thompson "True" : "False"); 2365d27bf6faSDoug Thompson debugf1(" CECC=%s UECC=%s Found by Scruber=%s\n", 2366d27bf6faSDoug Thompson (regs->nbsh & K8_NBSH_CECC) ? 2367d27bf6faSDoug Thompson "True" : "False", 2368d27bf6faSDoug Thompson (regs->nbsh & K8_NBSH_UECC) ? 2369d27bf6faSDoug Thompson "True" : "False", 2370d27bf6faSDoug Thompson (regs->nbsh & K8_NBSH_ERR_SCRUBER) ? 2371d27bf6faSDoug Thompson "True" : "False"); 2372d27bf6faSDoug Thompson debugf1(" CORE0=%s CORE1=%s CORE2=%s CORE3=%s\n", 2373d27bf6faSDoug Thompson (regs->nbsh & K8_NBSH_CORE0) ? "True" : "False", 2374d27bf6faSDoug Thompson (regs->nbsh & K8_NBSH_CORE1) ? "True" : "False", 2375d27bf6faSDoug Thompson (regs->nbsh & K8_NBSH_CORE2) ? "True" : "False", 2376d27bf6faSDoug Thompson (regs->nbsh & K8_NBSH_CORE3) ? "True" : "False"); 2377d27bf6faSDoug Thompson 2378d27bf6faSDoug Thompson 2379d27bf6faSDoug Thompson err_code = EXTRACT_ERROR_CODE(regs->nbsl); 2380d27bf6faSDoug Thompson 2381d27bf6faSDoug Thompson /* Determine which error type: 2382d27bf6faSDoug Thompson * 1) GART errors - non-fatal, developmental events 2383d27bf6faSDoug Thompson * 2) MEMORY errors 2384d27bf6faSDoug Thompson * 3) BUS errors 2385d27bf6faSDoug Thompson * 4) Unknown error 2386d27bf6faSDoug Thompson */ 2387d27bf6faSDoug Thompson if (TEST_TLB_ERROR(err_code)) { 2388d27bf6faSDoug Thompson /* 2389d27bf6faSDoug Thompson * GART errors are intended to help graphics driver developers 2390d27bf6faSDoug Thompson * to detect bad GART PTEs. It is recommended by AMD to disable 2391d27bf6faSDoug Thompson * GART table walk error reporting by default[1] (currently 2392d27bf6faSDoug Thompson * being disabled in mce_cpu_quirks()) and according to the 2393d27bf6faSDoug Thompson * comment in mce_cpu_quirks(), such GART errors can be 2394d27bf6faSDoug Thompson * incorrectly triggered. We may see these errors anyway and 2395d27bf6faSDoug Thompson * unless requested by the user, they won't be reported. 2396d27bf6faSDoug Thompson * 2397d27bf6faSDoug Thompson * [1] section 13.10.1 on BIOS and Kernel Developers Guide for 2398d27bf6faSDoug Thompson * AMD NPT family 0Fh processors 2399d27bf6faSDoug Thompson */ 2400d27bf6faSDoug Thompson if (report_gart_errors == 0) 2401d27bf6faSDoug Thompson return 1; 2402d27bf6faSDoug Thompson 2403d27bf6faSDoug Thompson /* 2404d27bf6faSDoug Thompson * Only if GART error reporting is requested should we generate 2405d27bf6faSDoug Thompson * any logs. 2406d27bf6faSDoug Thompson */ 2407d27bf6faSDoug Thompson gart_tlb_error = 1; 2408d27bf6faSDoug Thompson 2409d27bf6faSDoug Thompson debugf1("GART TLB error\n"); 2410d27bf6faSDoug Thompson amd64_decode_gart_tlb_error(mci, info); 2411d27bf6faSDoug Thompson } else if (TEST_MEM_ERROR(err_code)) { 2412d27bf6faSDoug Thompson debugf1("Memory/Cache error\n"); 2413d27bf6faSDoug Thompson amd64_decode_mem_cache_error(mci, info); 2414d27bf6faSDoug Thompson } else if (TEST_BUS_ERROR(err_code)) { 2415d27bf6faSDoug Thompson debugf1("Bus (Link/DRAM) error\n"); 2416d27bf6faSDoug Thompson amd64_decode_bus_error(mci, info); 2417d27bf6faSDoug Thompson } else { 2418d27bf6faSDoug Thompson /* shouldn't reach here! */ 2419d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_WARNING, 2420d27bf6faSDoug Thompson "%s(): unknown MCE error 0x%x\n", __func__, 2421d27bf6faSDoug Thompson err_code); 2422d27bf6faSDoug Thompson } 2423d27bf6faSDoug Thompson 2424d27bf6faSDoug Thompson ext_ec = EXTRACT_EXT_ERROR_CODE(regs->nbsl); 2425d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_ERR, 2426d27bf6faSDoug Thompson "ExtErr=(0x%x) %s\n", ext_ec, ext_msgs[ext_ec]); 2427d27bf6faSDoug Thompson 2428d27bf6faSDoug Thompson if (((ext_ec >= F10_NBSL_EXT_ERR_CRC && 2429d27bf6faSDoug Thompson ext_ec <= F10_NBSL_EXT_ERR_TGT) || 2430d27bf6faSDoug Thompson (ext_ec == F10_NBSL_EXT_ERR_RMW)) && 2431d27bf6faSDoug Thompson EXTRACT_LDT_LINK(info->nbsh)) { 2432d27bf6faSDoug Thompson 2433d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_ERR, 2434d27bf6faSDoug Thompson "Error on hypertransport link: %s\n", 2435d27bf6faSDoug Thompson htlink_msgs[ 2436d27bf6faSDoug Thompson EXTRACT_LDT_LINK(info->nbsh)]); 2437d27bf6faSDoug Thompson } 2438d27bf6faSDoug Thompson 2439d27bf6faSDoug Thompson /* 2440d27bf6faSDoug Thompson * Check the UE bit of the NB status high register, if set generate some 2441d27bf6faSDoug Thompson * logs. If NOT a GART error, then process the event as a NO-INFO event. 2442d27bf6faSDoug Thompson * If it was a GART error, skip that process. 2443d27bf6faSDoug Thompson */ 2444d27bf6faSDoug Thompson if (regs->nbsh & K8_NBSH_UNCORRECTED_ERR) { 2445d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_CRIT, "uncorrected error\n"); 2446d27bf6faSDoug Thompson if (!gart_tlb_error) 2447d27bf6faSDoug Thompson edac_mc_handle_ue_no_info(mci, "UE bit is set\n"); 2448d27bf6faSDoug Thompson } 2449d27bf6faSDoug Thompson 2450d27bf6faSDoug Thompson if (regs->nbsh & K8_NBSH_PCC) 2451d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_CRIT, 2452d27bf6faSDoug Thompson "PCC (processor context corrupt) set\n"); 2453d27bf6faSDoug Thompson 2454d27bf6faSDoug Thompson return 1; 2455d27bf6faSDoug Thompson } 2456d27bf6faSDoug Thompson EXPORT_SYMBOL_GPL(amd64_process_error_info); 2457d27bf6faSDoug Thompson 2458d27bf6faSDoug Thompson 2459