12bc65418SDoug Thompson #include "amd64_edac.h" 27d6034d3SDoug Thompson #include <asm/k8.h> 32bc65418SDoug Thompson 42bc65418SDoug Thompson static struct edac_pci_ctl_info *amd64_ctl_pci; 52bc65418SDoug Thompson 62bc65418SDoug Thompson static int report_gart_errors; 72bc65418SDoug Thompson module_param(report_gart_errors, int, 0644); 82bc65418SDoug Thompson 92bc65418SDoug Thompson /* 102bc65418SDoug Thompson * Set by command line parameter. If BIOS has enabled the ECC, this override is 112bc65418SDoug Thompson * cleared to prevent re-enabling the hardware by this driver. 122bc65418SDoug Thompson */ 132bc65418SDoug Thompson static int ecc_enable_override; 142bc65418SDoug Thompson module_param(ecc_enable_override, int, 0644); 152bc65418SDoug Thompson 162bc65418SDoug Thompson /* Lookup table for all possible MC control instances */ 172bc65418SDoug Thompson struct amd64_pvt; 183011b20dSBorislav Petkov static struct mem_ctl_info *mci_lookup[EDAC_MAX_NUMNODES]; 193011b20dSBorislav Petkov static struct amd64_pvt *pvt_lookup[EDAC_MAX_NUMNODES]; 202bc65418SDoug Thompson 212bc65418SDoug Thompson /* 22b70ef010SBorislav Petkov * See F2x80 for K8 and F2x[1,0]80 for Fam10 and later. The table below is only 23b70ef010SBorislav Petkov * for DDR2 DRAM mapping. 24b70ef010SBorislav Petkov */ 25b70ef010SBorislav Petkov u32 revf_quad_ddr2_shift[] = { 26b70ef010SBorislav Petkov 0, /* 0000b NULL DIMM (128mb) */ 27b70ef010SBorislav Petkov 28, /* 0001b 256mb */ 28b70ef010SBorislav Petkov 29, /* 0010b 512mb */ 29b70ef010SBorislav Petkov 29, /* 0011b 512mb */ 30b70ef010SBorislav Petkov 29, /* 0100b 512mb */ 31b70ef010SBorislav Petkov 30, /* 0101b 1gb */ 32b70ef010SBorislav Petkov 30, /* 0110b 1gb */ 33b70ef010SBorislav Petkov 31, /* 0111b 2gb */ 34b70ef010SBorislav Petkov 31, /* 1000b 2gb */ 35b70ef010SBorislav Petkov 32, /* 1001b 4gb */ 36b70ef010SBorislav Petkov 32, /* 1010b 4gb */ 37b70ef010SBorislav Petkov 33, /* 1011b 8gb */ 38b70ef010SBorislav Petkov 0, /* 1100b future */ 39b70ef010SBorislav Petkov 0, /* 1101b future */ 40b70ef010SBorislav Petkov 0, /* 1110b future */ 41b70ef010SBorislav Petkov 0 /* 1111b future */ 42b70ef010SBorislav Petkov }; 43b70ef010SBorislav Petkov 44b70ef010SBorislav Petkov /* 45b70ef010SBorislav Petkov * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing 46b70ef010SBorislav Petkov * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching- 47b70ef010SBorislav Petkov * or higher value'. 48b70ef010SBorislav Petkov * 49b70ef010SBorislav Petkov *FIXME: Produce a better mapping/linearisation. 50b70ef010SBorislav Petkov */ 51b70ef010SBorislav Petkov 52b70ef010SBorislav Petkov struct scrubrate scrubrates[] = { 53b70ef010SBorislav Petkov { 0x01, 1600000000UL}, 54b70ef010SBorislav Petkov { 0x02, 800000000UL}, 55b70ef010SBorislav Petkov { 0x03, 400000000UL}, 56b70ef010SBorislav Petkov { 0x04, 200000000UL}, 57b70ef010SBorislav Petkov { 0x05, 100000000UL}, 58b70ef010SBorislav Petkov { 0x06, 50000000UL}, 59b70ef010SBorislav Petkov { 0x07, 25000000UL}, 60b70ef010SBorislav Petkov { 0x08, 12284069UL}, 61b70ef010SBorislav Petkov { 0x09, 6274509UL}, 62b70ef010SBorislav Petkov { 0x0A, 3121951UL}, 63b70ef010SBorislav Petkov { 0x0B, 1560975UL}, 64b70ef010SBorislav Petkov { 0x0C, 781440UL}, 65b70ef010SBorislav Petkov { 0x0D, 390720UL}, 66b70ef010SBorislav Petkov { 0x0E, 195300UL}, 67b70ef010SBorislav Petkov { 0x0F, 97650UL}, 68b70ef010SBorislav Petkov { 0x10, 48854UL}, 69b70ef010SBorislav Petkov { 0x11, 24427UL}, 70b70ef010SBorislav Petkov { 0x12, 12213UL}, 71b70ef010SBorislav Petkov { 0x13, 6101UL}, 72b70ef010SBorislav Petkov { 0x14, 3051UL}, 73b70ef010SBorislav Petkov { 0x15, 1523UL}, 74b70ef010SBorislav Petkov { 0x16, 761UL}, 75b70ef010SBorislav Petkov { 0x00, 0UL}, /* scrubbing off */ 76b70ef010SBorislav Petkov }; 77b70ef010SBorislav Petkov 78b70ef010SBorislav Petkov /* 792bc65418SDoug Thompson * Memory scrubber control interface. For K8, memory scrubbing is handled by 802bc65418SDoug Thompson * hardware and can involve L2 cache, dcache as well as the main memory. With 812bc65418SDoug Thompson * F10, this is extended to L3 cache scrubbing on CPU models sporting that 822bc65418SDoug Thompson * functionality. 832bc65418SDoug Thompson * 842bc65418SDoug Thompson * This causes the "units" for the scrubbing speed to vary from 64 byte blocks 852bc65418SDoug Thompson * (dram) over to cache lines. This is nasty, so we will use bandwidth in 862bc65418SDoug Thompson * bytes/sec for the setting. 872bc65418SDoug Thompson * 882bc65418SDoug Thompson * Currently, we only do dram scrubbing. If the scrubbing is done in software on 892bc65418SDoug Thompson * other archs, we might not have access to the caches directly. 902bc65418SDoug Thompson */ 912bc65418SDoug Thompson 922bc65418SDoug Thompson /* 932bc65418SDoug Thompson * scan the scrub rate mapping table for a close or matching bandwidth value to 942bc65418SDoug Thompson * issue. If requested is too big, then use last maximum value found. 952bc65418SDoug Thompson */ 962bc65418SDoug Thompson static int amd64_search_set_scrub_rate(struct pci_dev *ctl, u32 new_bw, 972bc65418SDoug Thompson u32 min_scrubrate) 982bc65418SDoug Thompson { 992bc65418SDoug Thompson u32 scrubval; 1002bc65418SDoug Thompson int i; 1012bc65418SDoug Thompson 1022bc65418SDoug Thompson /* 1032bc65418SDoug Thompson * map the configured rate (new_bw) to a value specific to the AMD64 1042bc65418SDoug Thompson * memory controller and apply to register. Search for the first 1052bc65418SDoug Thompson * bandwidth entry that is greater or equal than the setting requested 1062bc65418SDoug Thompson * and program that. If at last entry, turn off DRAM scrubbing. 1072bc65418SDoug Thompson */ 1082bc65418SDoug Thompson for (i = 0; i < ARRAY_SIZE(scrubrates); i++) { 1092bc65418SDoug Thompson /* 1102bc65418SDoug Thompson * skip scrub rates which aren't recommended 1112bc65418SDoug Thompson * (see F10 BKDG, F3x58) 1122bc65418SDoug Thompson */ 1132bc65418SDoug Thompson if (scrubrates[i].scrubval < min_scrubrate) 1142bc65418SDoug Thompson continue; 1152bc65418SDoug Thompson 1162bc65418SDoug Thompson if (scrubrates[i].bandwidth <= new_bw) 1172bc65418SDoug Thompson break; 1182bc65418SDoug Thompson 1192bc65418SDoug Thompson /* 1202bc65418SDoug Thompson * if no suitable bandwidth found, turn off DRAM scrubbing 1212bc65418SDoug Thompson * entirely by falling back to the last element in the 1222bc65418SDoug Thompson * scrubrates array. 1232bc65418SDoug Thompson */ 1242bc65418SDoug Thompson } 1252bc65418SDoug Thompson 1262bc65418SDoug Thompson scrubval = scrubrates[i].scrubval; 1272bc65418SDoug Thompson if (scrubval) 1282bc65418SDoug Thompson edac_printk(KERN_DEBUG, EDAC_MC, 1292bc65418SDoug Thompson "Setting scrub rate bandwidth: %u\n", 1302bc65418SDoug Thompson scrubrates[i].bandwidth); 1312bc65418SDoug Thompson else 1322bc65418SDoug Thompson edac_printk(KERN_DEBUG, EDAC_MC, "Turning scrubbing off.\n"); 1332bc65418SDoug Thompson 1342bc65418SDoug Thompson pci_write_bits32(ctl, K8_SCRCTRL, scrubval, 0x001F); 1352bc65418SDoug Thompson 1362bc65418SDoug Thompson return 0; 1372bc65418SDoug Thompson } 1382bc65418SDoug Thompson 1392bc65418SDoug Thompson static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 *bandwidth) 1402bc65418SDoug Thompson { 1412bc65418SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 1422bc65418SDoug Thompson u32 min_scrubrate = 0x0; 1432bc65418SDoug Thompson 1442bc65418SDoug Thompson switch (boot_cpu_data.x86) { 1452bc65418SDoug Thompson case 0xf: 1462bc65418SDoug Thompson min_scrubrate = K8_MIN_SCRUB_RATE_BITS; 1472bc65418SDoug Thompson break; 1482bc65418SDoug Thompson case 0x10: 1492bc65418SDoug Thompson min_scrubrate = F10_MIN_SCRUB_RATE_BITS; 1502bc65418SDoug Thompson break; 1512bc65418SDoug Thompson case 0x11: 1522bc65418SDoug Thompson min_scrubrate = F11_MIN_SCRUB_RATE_BITS; 1532bc65418SDoug Thompson break; 1542bc65418SDoug Thompson 1552bc65418SDoug Thompson default: 1562bc65418SDoug Thompson amd64_printk(KERN_ERR, "Unsupported family!\n"); 1572bc65418SDoug Thompson break; 1582bc65418SDoug Thompson } 1592bc65418SDoug Thompson return amd64_search_set_scrub_rate(pvt->misc_f3_ctl, *bandwidth, 1602bc65418SDoug Thompson min_scrubrate); 1612bc65418SDoug Thompson } 1622bc65418SDoug Thompson 1632bc65418SDoug Thompson static int amd64_get_scrub_rate(struct mem_ctl_info *mci, u32 *bw) 1642bc65418SDoug Thompson { 1652bc65418SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 1662bc65418SDoug Thompson u32 scrubval = 0; 1676ba5dcdcSBorislav Petkov int status = -1, i; 1682bc65418SDoug Thompson 1696ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_SCRCTRL, &scrubval); 1702bc65418SDoug Thompson 1712bc65418SDoug Thompson scrubval = scrubval & 0x001F; 1722bc65418SDoug Thompson 1732bc65418SDoug Thompson edac_printk(KERN_DEBUG, EDAC_MC, 1742bc65418SDoug Thompson "pci-read, sdram scrub control value: %d \n", scrubval); 1752bc65418SDoug Thompson 1762bc65418SDoug Thompson for (i = 0; ARRAY_SIZE(scrubrates); i++) { 1772bc65418SDoug Thompson if (scrubrates[i].scrubval == scrubval) { 1782bc65418SDoug Thompson *bw = scrubrates[i].bandwidth; 1792bc65418SDoug Thompson status = 0; 1802bc65418SDoug Thompson break; 1812bc65418SDoug Thompson } 1822bc65418SDoug Thompson } 1832bc65418SDoug Thompson 1842bc65418SDoug Thompson return status; 1852bc65418SDoug Thompson } 1862bc65418SDoug Thompson 1876775763aSDoug Thompson /* Map from a CSROW entry to the mask entry that operates on it */ 1886775763aSDoug Thompson static inline u32 amd64_map_to_dcs_mask(struct amd64_pvt *pvt, int csrow) 1896775763aSDoug Thompson { 1909d858bb1SBorislav Petkov if (boot_cpu_data.x86 == 0xf && pvt->ext_model < OPTERON_CPU_REV_F) 1919d858bb1SBorislav Petkov return csrow; 1929d858bb1SBorislav Petkov else 1939d858bb1SBorislav Petkov return csrow >> 1; 1946775763aSDoug Thompson } 1956775763aSDoug Thompson 1966775763aSDoug Thompson /* return the 'base' address the i'th CS entry of the 'dct' DRAM controller */ 1976775763aSDoug Thompson static u32 amd64_get_dct_base(struct amd64_pvt *pvt, int dct, int csrow) 1986775763aSDoug Thompson { 1996775763aSDoug Thompson if (dct == 0) 2006775763aSDoug Thompson return pvt->dcsb0[csrow]; 2016775763aSDoug Thompson else 2026775763aSDoug Thompson return pvt->dcsb1[csrow]; 2036775763aSDoug Thompson } 2046775763aSDoug Thompson 2056775763aSDoug Thompson /* 2066775763aSDoug Thompson * Return the 'mask' address the i'th CS entry. This function is needed because 2076775763aSDoug Thompson * there number of DCSM registers on Rev E and prior vs Rev F and later is 2086775763aSDoug Thompson * different. 2096775763aSDoug Thompson */ 2106775763aSDoug Thompson static u32 amd64_get_dct_mask(struct amd64_pvt *pvt, int dct, int csrow) 2116775763aSDoug Thompson { 2126775763aSDoug Thompson if (dct == 0) 2136775763aSDoug Thompson return pvt->dcsm0[amd64_map_to_dcs_mask(pvt, csrow)]; 2146775763aSDoug Thompson else 2156775763aSDoug Thompson return pvt->dcsm1[amd64_map_to_dcs_mask(pvt, csrow)]; 2166775763aSDoug Thompson } 2176775763aSDoug Thompson 2186775763aSDoug Thompson 2196775763aSDoug Thompson /* 2206775763aSDoug Thompson * In *base and *limit, pass back the full 40-bit base and limit physical 2216775763aSDoug Thompson * addresses for the node given by node_id. This information is obtained from 2226775763aSDoug Thompson * DRAM Base (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers. The 2236775763aSDoug Thompson * base and limit addresses are of type SysAddr, as defined at the start of 2246775763aSDoug Thompson * section 3.4.4 (p. 70). They are the lowest and highest physical addresses 2256775763aSDoug Thompson * in the address range they represent. 2266775763aSDoug Thompson */ 2276775763aSDoug Thompson static void amd64_get_base_and_limit(struct amd64_pvt *pvt, int node_id, 2286775763aSDoug Thompson u64 *base, u64 *limit) 2296775763aSDoug Thompson { 2306775763aSDoug Thompson *base = pvt->dram_base[node_id]; 2316775763aSDoug Thompson *limit = pvt->dram_limit[node_id]; 2326775763aSDoug Thompson } 2336775763aSDoug Thompson 2346775763aSDoug Thompson /* 2356775763aSDoug Thompson * Return 1 if the SysAddr given by sys_addr matches the base/limit associated 2366775763aSDoug Thompson * with node_id 2376775763aSDoug Thompson */ 2386775763aSDoug Thompson static int amd64_base_limit_match(struct amd64_pvt *pvt, 2396775763aSDoug Thompson u64 sys_addr, int node_id) 2406775763aSDoug Thompson { 2416775763aSDoug Thompson u64 base, limit, addr; 2426775763aSDoug Thompson 2436775763aSDoug Thompson amd64_get_base_and_limit(pvt, node_id, &base, &limit); 2446775763aSDoug Thompson 2456775763aSDoug Thompson /* The K8 treats this as a 40-bit value. However, bits 63-40 will be 2466775763aSDoug Thompson * all ones if the most significant implemented address bit is 1. 2476775763aSDoug Thompson * Here we discard bits 63-40. See section 3.4.2 of AMD publication 2486775763aSDoug Thompson * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1 2496775763aSDoug Thompson * Application Programming. 2506775763aSDoug Thompson */ 2516775763aSDoug Thompson addr = sys_addr & 0x000000ffffffffffull; 2526775763aSDoug Thompson 2536775763aSDoug Thompson return (addr >= base) && (addr <= limit); 2546775763aSDoug Thompson } 2556775763aSDoug Thompson 2566775763aSDoug Thompson /* 2576775763aSDoug Thompson * Attempt to map a SysAddr to a node. On success, return a pointer to the 2586775763aSDoug Thompson * mem_ctl_info structure for the node that the SysAddr maps to. 2596775763aSDoug Thompson * 2606775763aSDoug Thompson * On failure, return NULL. 2616775763aSDoug Thompson */ 2626775763aSDoug Thompson static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci, 2636775763aSDoug Thompson u64 sys_addr) 2646775763aSDoug Thompson { 2656775763aSDoug Thompson struct amd64_pvt *pvt; 2666775763aSDoug Thompson int node_id; 2676775763aSDoug Thompson u32 intlv_en, bits; 2686775763aSDoug Thompson 2696775763aSDoug Thompson /* 2706775763aSDoug Thompson * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section 2716775763aSDoug Thompson * 3.4.4.2) registers to map the SysAddr to a node ID. 2726775763aSDoug Thompson */ 2736775763aSDoug Thompson pvt = mci->pvt_info; 2746775763aSDoug Thompson 2756775763aSDoug Thompson /* 2766775763aSDoug Thompson * The value of this field should be the same for all DRAM Base 2776775763aSDoug Thompson * registers. Therefore we arbitrarily choose to read it from the 2786775763aSDoug Thompson * register for node 0. 2796775763aSDoug Thompson */ 2806775763aSDoug Thompson intlv_en = pvt->dram_IntlvEn[0]; 2816775763aSDoug Thompson 2826775763aSDoug Thompson if (intlv_en == 0) { 2838edc5445SBorislav Petkov for (node_id = 0; node_id < DRAM_REG_COUNT; node_id++) { 2846775763aSDoug Thompson if (amd64_base_limit_match(pvt, sys_addr, node_id)) 2856775763aSDoug Thompson goto found; 2866775763aSDoug Thompson } 2878edc5445SBorislav Petkov goto err_no_match; 2888edc5445SBorislav Petkov } 2896775763aSDoug Thompson 29072f158feSBorislav Petkov if (unlikely((intlv_en != 0x01) && 29172f158feSBorislav Petkov (intlv_en != 0x03) && 29272f158feSBorislav Petkov (intlv_en != 0x07))) { 2936775763aSDoug Thompson amd64_printk(KERN_WARNING, "junk value of 0x%x extracted from " 2946775763aSDoug Thompson "IntlvEn field of DRAM Base Register for node 0: " 29572f158feSBorislav Petkov "this probably indicates a BIOS bug.\n", intlv_en); 2966775763aSDoug Thompson return NULL; 2976775763aSDoug Thompson } 2986775763aSDoug Thompson 2996775763aSDoug Thompson bits = (((u32) sys_addr) >> 12) & intlv_en; 3006775763aSDoug Thompson 3016775763aSDoug Thompson for (node_id = 0; ; ) { 3028edc5445SBorislav Petkov if ((pvt->dram_IntlvSel[node_id] & intlv_en) == bits) 3036775763aSDoug Thompson break; /* intlv_sel field matches */ 3046775763aSDoug Thompson 3056775763aSDoug Thompson if (++node_id >= DRAM_REG_COUNT) 3066775763aSDoug Thompson goto err_no_match; 3076775763aSDoug Thompson } 3086775763aSDoug Thompson 3096775763aSDoug Thompson /* sanity test for sys_addr */ 3106775763aSDoug Thompson if (unlikely(!amd64_base_limit_match(pvt, sys_addr, node_id))) { 3116775763aSDoug Thompson amd64_printk(KERN_WARNING, 3128edc5445SBorislav Petkov "%s(): sys_addr 0x%llx falls outside base/limit " 3136775763aSDoug Thompson "address range for node %d with node interleaving " 3148edc5445SBorislav Petkov "enabled.\n", 3158edc5445SBorislav Petkov __func__, sys_addr, node_id); 3166775763aSDoug Thompson return NULL; 3176775763aSDoug Thompson } 3186775763aSDoug Thompson 3196775763aSDoug Thompson found: 3206775763aSDoug Thompson return edac_mc_find(node_id); 3216775763aSDoug Thompson 3226775763aSDoug Thompson err_no_match: 3236775763aSDoug Thompson debugf2("sys_addr 0x%lx doesn't match any node\n", 3246775763aSDoug Thompson (unsigned long)sys_addr); 3256775763aSDoug Thompson 3266775763aSDoug Thompson return NULL; 3276775763aSDoug Thompson } 328e2ce7255SDoug Thompson 329e2ce7255SDoug Thompson /* 330e2ce7255SDoug Thompson * Extract the DRAM CS base address from selected csrow register. 331e2ce7255SDoug Thompson */ 332e2ce7255SDoug Thompson static u64 base_from_dct_base(struct amd64_pvt *pvt, int csrow) 333e2ce7255SDoug Thompson { 334e2ce7255SDoug Thompson return ((u64) (amd64_get_dct_base(pvt, 0, csrow) & pvt->dcsb_base)) << 335e2ce7255SDoug Thompson pvt->dcs_shift; 336e2ce7255SDoug Thompson } 337e2ce7255SDoug Thompson 338e2ce7255SDoug Thompson /* 339e2ce7255SDoug Thompson * Extract the mask from the dcsb0[csrow] entry in a CPU revision-specific way. 340e2ce7255SDoug Thompson */ 341e2ce7255SDoug Thompson static u64 mask_from_dct_mask(struct amd64_pvt *pvt, int csrow) 342e2ce7255SDoug Thompson { 343e2ce7255SDoug Thompson u64 dcsm_bits, other_bits; 344e2ce7255SDoug Thompson u64 mask; 345e2ce7255SDoug Thompson 346e2ce7255SDoug Thompson /* Extract bits from DRAM CS Mask. */ 347e2ce7255SDoug Thompson dcsm_bits = amd64_get_dct_mask(pvt, 0, csrow) & pvt->dcsm_mask; 348e2ce7255SDoug Thompson 349e2ce7255SDoug Thompson other_bits = pvt->dcsm_mask; 350e2ce7255SDoug Thompson other_bits = ~(other_bits << pvt->dcs_shift); 351e2ce7255SDoug Thompson 352e2ce7255SDoug Thompson /* 353e2ce7255SDoug Thompson * The extracted bits from DCSM belong in the spaces represented by 354e2ce7255SDoug Thompson * the cleared bits in other_bits. 355e2ce7255SDoug Thompson */ 356e2ce7255SDoug Thompson mask = (dcsm_bits << pvt->dcs_shift) | other_bits; 357e2ce7255SDoug Thompson 358e2ce7255SDoug Thompson return mask; 359e2ce7255SDoug Thompson } 360e2ce7255SDoug Thompson 361e2ce7255SDoug Thompson /* 362e2ce7255SDoug Thompson * @input_addr is an InputAddr associated with the node given by mci. Return the 363e2ce7255SDoug Thompson * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr). 364e2ce7255SDoug Thompson */ 365e2ce7255SDoug Thompson static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr) 366e2ce7255SDoug Thompson { 367e2ce7255SDoug Thompson struct amd64_pvt *pvt; 368e2ce7255SDoug Thompson int csrow; 369e2ce7255SDoug Thompson u64 base, mask; 370e2ce7255SDoug Thompson 371e2ce7255SDoug Thompson pvt = mci->pvt_info; 372e2ce7255SDoug Thompson 373e2ce7255SDoug Thompson /* 374e2ce7255SDoug Thompson * Here we use the DRAM CS Base and DRAM CS Mask registers. For each CS 375e2ce7255SDoug Thompson * base/mask register pair, test the condition shown near the start of 376e2ce7255SDoug Thompson * section 3.5.4 (p. 84, BKDG #26094, K8, revA-E). 377e2ce7255SDoug Thompson */ 3789d858bb1SBorislav Petkov for (csrow = 0; csrow < pvt->cs_count; csrow++) { 379e2ce7255SDoug Thompson 380e2ce7255SDoug Thompson /* This DRAM chip select is disabled on this node */ 381e2ce7255SDoug Thompson if ((pvt->dcsb0[csrow] & K8_DCSB_CS_ENABLE) == 0) 382e2ce7255SDoug Thompson continue; 383e2ce7255SDoug Thompson 384e2ce7255SDoug Thompson base = base_from_dct_base(pvt, csrow); 385e2ce7255SDoug Thompson mask = ~mask_from_dct_mask(pvt, csrow); 386e2ce7255SDoug Thompson 387e2ce7255SDoug Thompson if ((input_addr & mask) == (base & mask)) { 388e2ce7255SDoug Thompson debugf2("InputAddr 0x%lx matches csrow %d (node %d)\n", 389e2ce7255SDoug Thompson (unsigned long)input_addr, csrow, 390e2ce7255SDoug Thompson pvt->mc_node_id); 391e2ce7255SDoug Thompson 392e2ce7255SDoug Thompson return csrow; 393e2ce7255SDoug Thompson } 394e2ce7255SDoug Thompson } 395e2ce7255SDoug Thompson 396e2ce7255SDoug Thompson debugf2("no matching csrow for InputAddr 0x%lx (MC node %d)\n", 397e2ce7255SDoug Thompson (unsigned long)input_addr, pvt->mc_node_id); 398e2ce7255SDoug Thompson 399e2ce7255SDoug Thompson return -1; 400e2ce7255SDoug Thompson } 401e2ce7255SDoug Thompson 402e2ce7255SDoug Thompson /* 403e2ce7255SDoug Thompson * Return the base value defined by the DRAM Base register for the node 404e2ce7255SDoug Thompson * represented by mci. This function returns the full 40-bit value despite the 405e2ce7255SDoug Thompson * fact that the register only stores bits 39-24 of the value. See section 406e2ce7255SDoug Thompson * 3.4.4.1 (BKDG #26094, K8, revA-E) 407e2ce7255SDoug Thompson */ 408e2ce7255SDoug Thompson static inline u64 get_dram_base(struct mem_ctl_info *mci) 409e2ce7255SDoug Thompson { 410e2ce7255SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 411e2ce7255SDoug Thompson 412e2ce7255SDoug Thompson return pvt->dram_base[pvt->mc_node_id]; 413e2ce7255SDoug Thompson } 414e2ce7255SDoug Thompson 415e2ce7255SDoug Thompson /* 416e2ce7255SDoug Thompson * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094) 417e2ce7255SDoug Thompson * for the node represented by mci. Info is passed back in *hole_base, 418e2ce7255SDoug Thompson * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if 419e2ce7255SDoug Thompson * info is invalid. Info may be invalid for either of the following reasons: 420e2ce7255SDoug Thompson * 421e2ce7255SDoug Thompson * - The revision of the node is not E or greater. In this case, the DRAM Hole 422e2ce7255SDoug Thompson * Address Register does not exist. 423e2ce7255SDoug Thompson * 424e2ce7255SDoug Thompson * - The DramHoleValid bit is cleared in the DRAM Hole Address Register, 425e2ce7255SDoug Thompson * indicating that its contents are not valid. 426e2ce7255SDoug Thompson * 427e2ce7255SDoug Thompson * The values passed back in *hole_base, *hole_offset, and *hole_size are 428e2ce7255SDoug Thompson * complete 32-bit values despite the fact that the bitfields in the DHAR 429e2ce7255SDoug Thompson * only represent bits 31-24 of the base and offset values. 430e2ce7255SDoug Thompson */ 431e2ce7255SDoug Thompson int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, 432e2ce7255SDoug Thompson u64 *hole_offset, u64 *hole_size) 433e2ce7255SDoug Thompson { 434e2ce7255SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 435e2ce7255SDoug Thompson u64 base; 436e2ce7255SDoug Thompson 437e2ce7255SDoug Thompson /* only revE and later have the DRAM Hole Address Register */ 438e2ce7255SDoug Thompson if (boot_cpu_data.x86 == 0xf && pvt->ext_model < OPTERON_CPU_REV_E) { 439e2ce7255SDoug Thompson debugf1(" revision %d for node %d does not support DHAR\n", 440e2ce7255SDoug Thompson pvt->ext_model, pvt->mc_node_id); 441e2ce7255SDoug Thompson return 1; 442e2ce7255SDoug Thompson } 443e2ce7255SDoug Thompson 444e2ce7255SDoug Thompson /* only valid for Fam10h */ 445e2ce7255SDoug Thompson if (boot_cpu_data.x86 == 0x10 && 446e2ce7255SDoug Thompson (pvt->dhar & F10_DRAM_MEM_HOIST_VALID) == 0) { 447e2ce7255SDoug Thompson debugf1(" Dram Memory Hoisting is DISABLED on this system\n"); 448e2ce7255SDoug Thompson return 1; 449e2ce7255SDoug Thompson } 450e2ce7255SDoug Thompson 451e2ce7255SDoug Thompson if ((pvt->dhar & DHAR_VALID) == 0) { 452e2ce7255SDoug Thompson debugf1(" Dram Memory Hoisting is DISABLED on this node %d\n", 453e2ce7255SDoug Thompson pvt->mc_node_id); 454e2ce7255SDoug Thompson return 1; 455e2ce7255SDoug Thompson } 456e2ce7255SDoug Thompson 457e2ce7255SDoug Thompson /* This node has Memory Hoisting */ 458e2ce7255SDoug Thompson 459e2ce7255SDoug Thompson /* +------------------+--------------------+--------------------+----- 460e2ce7255SDoug Thompson * | memory | DRAM hole | relocated | 461e2ce7255SDoug Thompson * | [0, (x - 1)] | [x, 0xffffffff] | addresses from | 462e2ce7255SDoug Thompson * | | | DRAM hole | 463e2ce7255SDoug Thompson * | | | [0x100000000, | 464e2ce7255SDoug Thompson * | | | (0x100000000+ | 465e2ce7255SDoug Thompson * | | | (0xffffffff-x))] | 466e2ce7255SDoug Thompson * +------------------+--------------------+--------------------+----- 467e2ce7255SDoug Thompson * 468e2ce7255SDoug Thompson * Above is a diagram of physical memory showing the DRAM hole and the 469e2ce7255SDoug Thompson * relocated addresses from the DRAM hole. As shown, the DRAM hole 470e2ce7255SDoug Thompson * starts at address x (the base address) and extends through address 471e2ce7255SDoug Thompson * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the 472e2ce7255SDoug Thompson * addresses in the hole so that they start at 0x100000000. 473e2ce7255SDoug Thompson */ 474e2ce7255SDoug Thompson 475e2ce7255SDoug Thompson base = dhar_base(pvt->dhar); 476e2ce7255SDoug Thompson 477e2ce7255SDoug Thompson *hole_base = base; 478e2ce7255SDoug Thompson *hole_size = (0x1ull << 32) - base; 479e2ce7255SDoug Thompson 480e2ce7255SDoug Thompson if (boot_cpu_data.x86 > 0xf) 481e2ce7255SDoug Thompson *hole_offset = f10_dhar_offset(pvt->dhar); 482e2ce7255SDoug Thompson else 483e2ce7255SDoug Thompson *hole_offset = k8_dhar_offset(pvt->dhar); 484e2ce7255SDoug Thompson 485e2ce7255SDoug Thompson debugf1(" DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n", 486e2ce7255SDoug Thompson pvt->mc_node_id, (unsigned long)*hole_base, 487e2ce7255SDoug Thompson (unsigned long)*hole_offset, (unsigned long)*hole_size); 488e2ce7255SDoug Thompson 489e2ce7255SDoug Thompson return 0; 490e2ce7255SDoug Thompson } 491e2ce7255SDoug Thompson EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info); 492e2ce7255SDoug Thompson 49393c2df58SDoug Thompson /* 49493c2df58SDoug Thompson * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is 49593c2df58SDoug Thompson * assumed that sys_addr maps to the node given by mci. 49693c2df58SDoug Thompson * 49793c2df58SDoug Thompson * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section 49893c2df58SDoug Thompson * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a 49993c2df58SDoug Thompson * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled, 50093c2df58SDoug Thompson * then it is also involved in translating a SysAddr to a DramAddr. Sections 50193c2df58SDoug Thompson * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting. 50293c2df58SDoug Thompson * These parts of the documentation are unclear. I interpret them as follows: 50393c2df58SDoug Thompson * 50493c2df58SDoug Thompson * When node n receives a SysAddr, it processes the SysAddr as follows: 50593c2df58SDoug Thompson * 50693c2df58SDoug Thompson * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM 50793c2df58SDoug Thompson * Limit registers for node n. If the SysAddr is not within the range 50893c2df58SDoug Thompson * specified by the base and limit values, then node n ignores the Sysaddr 50993c2df58SDoug Thompson * (since it does not map to node n). Otherwise continue to step 2 below. 51093c2df58SDoug Thompson * 51193c2df58SDoug Thompson * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is 51293c2df58SDoug Thompson * disabled so skip to step 3 below. Otherwise see if the SysAddr is within 51393c2df58SDoug Thompson * the range of relocated addresses (starting at 0x100000000) from the DRAM 51493c2df58SDoug Thompson * hole. If not, skip to step 3 below. Else get the value of the 51593c2df58SDoug Thompson * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the 51693c2df58SDoug Thompson * offset defined by this value from the SysAddr. 51793c2df58SDoug Thompson * 51893c2df58SDoug Thompson * 3. Obtain the base address for node n from the DRAMBase field of the DRAM 51993c2df58SDoug Thompson * Base register for node n. To obtain the DramAddr, subtract the base 52093c2df58SDoug Thompson * address from the SysAddr, as shown near the start of section 3.4.4 (p.70). 52193c2df58SDoug Thompson */ 52293c2df58SDoug Thompson static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr) 52393c2df58SDoug Thompson { 52493c2df58SDoug Thompson u64 dram_base, hole_base, hole_offset, hole_size, dram_addr; 52593c2df58SDoug Thompson int ret = 0; 52693c2df58SDoug Thompson 52793c2df58SDoug Thompson dram_base = get_dram_base(mci); 52893c2df58SDoug Thompson 52993c2df58SDoug Thompson ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, 53093c2df58SDoug Thompson &hole_size); 53193c2df58SDoug Thompson if (!ret) { 53293c2df58SDoug Thompson if ((sys_addr >= (1ull << 32)) && 53393c2df58SDoug Thompson (sys_addr < ((1ull << 32) + hole_size))) { 53493c2df58SDoug Thompson /* use DHAR to translate SysAddr to DramAddr */ 53593c2df58SDoug Thompson dram_addr = sys_addr - hole_offset; 53693c2df58SDoug Thompson 53793c2df58SDoug Thompson debugf2("using DHAR to translate SysAddr 0x%lx to " 53893c2df58SDoug Thompson "DramAddr 0x%lx\n", 53993c2df58SDoug Thompson (unsigned long)sys_addr, 54093c2df58SDoug Thompson (unsigned long)dram_addr); 54193c2df58SDoug Thompson 54293c2df58SDoug Thompson return dram_addr; 54393c2df58SDoug Thompson } 54493c2df58SDoug Thompson } 54593c2df58SDoug Thompson 54693c2df58SDoug Thompson /* 54793c2df58SDoug Thompson * Translate the SysAddr to a DramAddr as shown near the start of 54893c2df58SDoug Thompson * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8 54993c2df58SDoug Thompson * only deals with 40-bit values. Therefore we discard bits 63-40 of 55093c2df58SDoug Thompson * sys_addr below. If bit 39 of sys_addr is 1 then the bits we 55193c2df58SDoug Thompson * discard are all 1s. Otherwise the bits we discard are all 0s. See 55293c2df58SDoug Thompson * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture 55393c2df58SDoug Thompson * Programmer's Manual Volume 1 Application Programming. 55493c2df58SDoug Thompson */ 55593c2df58SDoug Thompson dram_addr = (sys_addr & 0xffffffffffull) - dram_base; 55693c2df58SDoug Thompson 55793c2df58SDoug Thompson debugf2("using DRAM Base register to translate SysAddr 0x%lx to " 55893c2df58SDoug Thompson "DramAddr 0x%lx\n", (unsigned long)sys_addr, 55993c2df58SDoug Thompson (unsigned long)dram_addr); 56093c2df58SDoug Thompson return dram_addr; 56193c2df58SDoug Thompson } 56293c2df58SDoug Thompson 56393c2df58SDoug Thompson /* 56493c2df58SDoug Thompson * @intlv_en is the value of the IntlvEn field from a DRAM Base register 56593c2df58SDoug Thompson * (section 3.4.4.1). Return the number of bits from a SysAddr that are used 56693c2df58SDoug Thompson * for node interleaving. 56793c2df58SDoug Thompson */ 56893c2df58SDoug Thompson static int num_node_interleave_bits(unsigned intlv_en) 56993c2df58SDoug Thompson { 57093c2df58SDoug Thompson static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 }; 57193c2df58SDoug Thompson int n; 57293c2df58SDoug Thompson 57393c2df58SDoug Thompson BUG_ON(intlv_en > 7); 57493c2df58SDoug Thompson n = intlv_shift_table[intlv_en]; 57593c2df58SDoug Thompson return n; 57693c2df58SDoug Thompson } 57793c2df58SDoug Thompson 57893c2df58SDoug Thompson /* Translate the DramAddr given by @dram_addr to an InputAddr. */ 57993c2df58SDoug Thompson static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr) 58093c2df58SDoug Thompson { 58193c2df58SDoug Thompson struct amd64_pvt *pvt; 58293c2df58SDoug Thompson int intlv_shift; 58393c2df58SDoug Thompson u64 input_addr; 58493c2df58SDoug Thompson 58593c2df58SDoug Thompson pvt = mci->pvt_info; 58693c2df58SDoug Thompson 58793c2df58SDoug Thompson /* 58893c2df58SDoug Thompson * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) 58993c2df58SDoug Thompson * concerning translating a DramAddr to an InputAddr. 59093c2df58SDoug Thompson */ 59193c2df58SDoug Thompson intlv_shift = num_node_interleave_bits(pvt->dram_IntlvEn[0]); 59293c2df58SDoug Thompson input_addr = ((dram_addr >> intlv_shift) & 0xffffff000ull) + 59393c2df58SDoug Thompson (dram_addr & 0xfff); 59493c2df58SDoug Thompson 59593c2df58SDoug Thompson debugf2(" Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n", 59693c2df58SDoug Thompson intlv_shift, (unsigned long)dram_addr, 59793c2df58SDoug Thompson (unsigned long)input_addr); 59893c2df58SDoug Thompson 59993c2df58SDoug Thompson return input_addr; 60093c2df58SDoug Thompson } 60193c2df58SDoug Thompson 60293c2df58SDoug Thompson /* 60393c2df58SDoug Thompson * Translate the SysAddr represented by @sys_addr to an InputAddr. It is 60493c2df58SDoug Thompson * assumed that @sys_addr maps to the node given by mci. 60593c2df58SDoug Thompson */ 60693c2df58SDoug Thompson static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr) 60793c2df58SDoug Thompson { 60893c2df58SDoug Thompson u64 input_addr; 60993c2df58SDoug Thompson 61093c2df58SDoug Thompson input_addr = 61193c2df58SDoug Thompson dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr)); 61293c2df58SDoug Thompson 61393c2df58SDoug Thompson debugf2("SysAdddr 0x%lx translates to InputAddr 0x%lx\n", 61493c2df58SDoug Thompson (unsigned long)sys_addr, (unsigned long)input_addr); 61593c2df58SDoug Thompson 61693c2df58SDoug Thompson return input_addr; 61793c2df58SDoug Thompson } 61893c2df58SDoug Thompson 61993c2df58SDoug Thompson 62093c2df58SDoug Thompson /* 62193c2df58SDoug Thompson * @input_addr is an InputAddr associated with the node represented by mci. 62293c2df58SDoug Thompson * Translate @input_addr to a DramAddr and return the result. 62393c2df58SDoug Thompson */ 62493c2df58SDoug Thompson static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr) 62593c2df58SDoug Thompson { 62693c2df58SDoug Thompson struct amd64_pvt *pvt; 62793c2df58SDoug Thompson int node_id, intlv_shift; 62893c2df58SDoug Thompson u64 bits, dram_addr; 62993c2df58SDoug Thompson u32 intlv_sel; 63093c2df58SDoug Thompson 63193c2df58SDoug Thompson /* 63293c2df58SDoug Thompson * Near the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) 63393c2df58SDoug Thompson * shows how to translate a DramAddr to an InputAddr. Here we reverse 63493c2df58SDoug Thompson * this procedure. When translating from a DramAddr to an InputAddr, the 63593c2df58SDoug Thompson * bits used for node interleaving are discarded. Here we recover these 63693c2df58SDoug Thompson * bits from the IntlvSel field of the DRAM Limit register (section 63793c2df58SDoug Thompson * 3.4.4.2) for the node that input_addr is associated with. 63893c2df58SDoug Thompson */ 63993c2df58SDoug Thompson pvt = mci->pvt_info; 64093c2df58SDoug Thompson node_id = pvt->mc_node_id; 64193c2df58SDoug Thompson BUG_ON((node_id < 0) || (node_id > 7)); 64293c2df58SDoug Thompson 64393c2df58SDoug Thompson intlv_shift = num_node_interleave_bits(pvt->dram_IntlvEn[0]); 64493c2df58SDoug Thompson 64593c2df58SDoug Thompson if (intlv_shift == 0) { 64693c2df58SDoug Thompson debugf1(" InputAddr 0x%lx translates to DramAddr of " 64793c2df58SDoug Thompson "same value\n", (unsigned long)input_addr); 64893c2df58SDoug Thompson 64993c2df58SDoug Thompson return input_addr; 65093c2df58SDoug Thompson } 65193c2df58SDoug Thompson 65293c2df58SDoug Thompson bits = ((input_addr & 0xffffff000ull) << intlv_shift) + 65393c2df58SDoug Thompson (input_addr & 0xfff); 65493c2df58SDoug Thompson 65593c2df58SDoug Thompson intlv_sel = pvt->dram_IntlvSel[node_id] & ((1 << intlv_shift) - 1); 65693c2df58SDoug Thompson dram_addr = bits + (intlv_sel << 12); 65793c2df58SDoug Thompson 65893c2df58SDoug Thompson debugf1("InputAddr 0x%lx translates to DramAddr 0x%lx " 65993c2df58SDoug Thompson "(%d node interleave bits)\n", (unsigned long)input_addr, 66093c2df58SDoug Thompson (unsigned long)dram_addr, intlv_shift); 66193c2df58SDoug Thompson 66293c2df58SDoug Thompson return dram_addr; 66393c2df58SDoug Thompson } 66493c2df58SDoug Thompson 66593c2df58SDoug Thompson /* 66693c2df58SDoug Thompson * @dram_addr is a DramAddr that maps to the node represented by mci. Convert 66793c2df58SDoug Thompson * @dram_addr to a SysAddr. 66893c2df58SDoug Thompson */ 66993c2df58SDoug Thompson static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr) 67093c2df58SDoug Thompson { 67193c2df58SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 67293c2df58SDoug Thompson u64 hole_base, hole_offset, hole_size, base, limit, sys_addr; 67393c2df58SDoug Thompson int ret = 0; 67493c2df58SDoug Thompson 67593c2df58SDoug Thompson ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, 67693c2df58SDoug Thompson &hole_size); 67793c2df58SDoug Thompson if (!ret) { 67893c2df58SDoug Thompson if ((dram_addr >= hole_base) && 67993c2df58SDoug Thompson (dram_addr < (hole_base + hole_size))) { 68093c2df58SDoug Thompson sys_addr = dram_addr + hole_offset; 68193c2df58SDoug Thompson 68293c2df58SDoug Thompson debugf1("using DHAR to translate DramAddr 0x%lx to " 68393c2df58SDoug Thompson "SysAddr 0x%lx\n", (unsigned long)dram_addr, 68493c2df58SDoug Thompson (unsigned long)sys_addr); 68593c2df58SDoug Thompson 68693c2df58SDoug Thompson return sys_addr; 68793c2df58SDoug Thompson } 68893c2df58SDoug Thompson } 68993c2df58SDoug Thompson 69093c2df58SDoug Thompson amd64_get_base_and_limit(pvt, pvt->mc_node_id, &base, &limit); 69193c2df58SDoug Thompson sys_addr = dram_addr + base; 69293c2df58SDoug Thompson 69393c2df58SDoug Thompson /* 69493c2df58SDoug Thompson * The sys_addr we have computed up to this point is a 40-bit value 69593c2df58SDoug Thompson * because the k8 deals with 40-bit values. However, the value we are 69693c2df58SDoug Thompson * supposed to return is a full 64-bit physical address. The AMD 69793c2df58SDoug Thompson * x86-64 architecture specifies that the most significant implemented 69893c2df58SDoug Thompson * address bit through bit 63 of a physical address must be either all 69993c2df58SDoug Thompson * 0s or all 1s. Therefore we sign-extend the 40-bit sys_addr to a 70093c2df58SDoug Thompson * 64-bit value below. See section 3.4.2 of AMD publication 24592: 70193c2df58SDoug Thompson * AMD x86-64 Architecture Programmer's Manual Volume 1 Application 70293c2df58SDoug Thompson * Programming. 70393c2df58SDoug Thompson */ 70493c2df58SDoug Thompson sys_addr |= ~((sys_addr & (1ull << 39)) - 1); 70593c2df58SDoug Thompson 70693c2df58SDoug Thompson debugf1(" Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n", 70793c2df58SDoug Thompson pvt->mc_node_id, (unsigned long)dram_addr, 70893c2df58SDoug Thompson (unsigned long)sys_addr); 70993c2df58SDoug Thompson 71093c2df58SDoug Thompson return sys_addr; 71193c2df58SDoug Thompson } 71293c2df58SDoug Thompson 71393c2df58SDoug Thompson /* 71493c2df58SDoug Thompson * @input_addr is an InputAddr associated with the node given by mci. Translate 71593c2df58SDoug Thompson * @input_addr to a SysAddr. 71693c2df58SDoug Thompson */ 71793c2df58SDoug Thompson static inline u64 input_addr_to_sys_addr(struct mem_ctl_info *mci, 71893c2df58SDoug Thompson u64 input_addr) 71993c2df58SDoug Thompson { 72093c2df58SDoug Thompson return dram_addr_to_sys_addr(mci, 72193c2df58SDoug Thompson input_addr_to_dram_addr(mci, input_addr)); 72293c2df58SDoug Thompson } 72393c2df58SDoug Thompson 72493c2df58SDoug Thompson /* 72593c2df58SDoug Thompson * Find the minimum and maximum InputAddr values that map to the given @csrow. 72693c2df58SDoug Thompson * Pass back these values in *input_addr_min and *input_addr_max. 72793c2df58SDoug Thompson */ 72893c2df58SDoug Thompson static void find_csrow_limits(struct mem_ctl_info *mci, int csrow, 72993c2df58SDoug Thompson u64 *input_addr_min, u64 *input_addr_max) 73093c2df58SDoug Thompson { 73193c2df58SDoug Thompson struct amd64_pvt *pvt; 73293c2df58SDoug Thompson u64 base, mask; 73393c2df58SDoug Thompson 73493c2df58SDoug Thompson pvt = mci->pvt_info; 7359d858bb1SBorislav Petkov BUG_ON((csrow < 0) || (csrow >= pvt->cs_count)); 73693c2df58SDoug Thompson 73793c2df58SDoug Thompson base = base_from_dct_base(pvt, csrow); 73893c2df58SDoug Thompson mask = mask_from_dct_mask(pvt, csrow); 73993c2df58SDoug Thompson 74093c2df58SDoug Thompson *input_addr_min = base & ~mask; 74193c2df58SDoug Thompson *input_addr_max = base | mask | pvt->dcs_mask_notused; 74293c2df58SDoug Thompson } 74393c2df58SDoug Thompson 74493c2df58SDoug Thompson /* 74593c2df58SDoug Thompson * Extract error address from MCA NB Address Low (section 3.6.4.5) and MCA NB 74693c2df58SDoug Thompson * Address High (section 3.6.4.6) register values and return the result. Address 74793c2df58SDoug Thompson * is located in the info structure (nbeah and nbeal), the encoding is device 74893c2df58SDoug Thompson * specific. 74993c2df58SDoug Thompson */ 75093c2df58SDoug Thompson static u64 extract_error_address(struct mem_ctl_info *mci, 751ef44cc4cSBorislav Petkov struct err_regs *info) 75293c2df58SDoug Thompson { 75393c2df58SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 75493c2df58SDoug Thompson 75593c2df58SDoug Thompson return pvt->ops->get_error_address(mci, info); 75693c2df58SDoug Thompson } 75793c2df58SDoug Thompson 75893c2df58SDoug Thompson 75993c2df58SDoug Thompson /* Map the Error address to a PAGE and PAGE OFFSET. */ 76093c2df58SDoug Thompson static inline void error_address_to_page_and_offset(u64 error_address, 76193c2df58SDoug Thompson u32 *page, u32 *offset) 76293c2df58SDoug Thompson { 76393c2df58SDoug Thompson *page = (u32) (error_address >> PAGE_SHIFT); 76493c2df58SDoug Thompson *offset = ((u32) error_address) & ~PAGE_MASK; 76593c2df58SDoug Thompson } 76693c2df58SDoug Thompson 76793c2df58SDoug Thompson /* 76893c2df58SDoug Thompson * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address 76993c2df58SDoug Thompson * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers 77093c2df58SDoug Thompson * of a node that detected an ECC memory error. mci represents the node that 77193c2df58SDoug Thompson * the error address maps to (possibly different from the node that detected 77293c2df58SDoug Thompson * the error). Return the number of the csrow that sys_addr maps to, or -1 on 77393c2df58SDoug Thompson * error. 77493c2df58SDoug Thompson */ 77593c2df58SDoug Thompson static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) 77693c2df58SDoug Thompson { 77793c2df58SDoug Thompson int csrow; 77893c2df58SDoug Thompson 77993c2df58SDoug Thompson csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr)); 78093c2df58SDoug Thompson 78193c2df58SDoug Thompson if (csrow == -1) 78293c2df58SDoug Thompson amd64_mc_printk(mci, KERN_ERR, 78393c2df58SDoug Thompson "Failed to translate InputAddr to csrow for " 78493c2df58SDoug Thompson "address 0x%lx\n", (unsigned long)sys_addr); 78593c2df58SDoug Thompson return csrow; 78693c2df58SDoug Thompson } 787e2ce7255SDoug Thompson 7882da11654SDoug Thompson static int get_channel_from_ecc_syndrome(unsigned short syndrome); 7892da11654SDoug Thompson 7902da11654SDoug Thompson static void amd64_cpu_display_info(struct amd64_pvt *pvt) 7912da11654SDoug Thompson { 7922da11654SDoug Thompson if (boot_cpu_data.x86 == 0x11) 7932da11654SDoug Thompson edac_printk(KERN_DEBUG, EDAC_MC, "F11h CPU detected\n"); 7942da11654SDoug Thompson else if (boot_cpu_data.x86 == 0x10) 7952da11654SDoug Thompson edac_printk(KERN_DEBUG, EDAC_MC, "F10h CPU detected\n"); 7962da11654SDoug Thompson else if (boot_cpu_data.x86 == 0xf) 7972da11654SDoug Thompson edac_printk(KERN_DEBUG, EDAC_MC, "%s detected\n", 7982da11654SDoug Thompson (pvt->ext_model >= OPTERON_CPU_REV_F) ? 7992da11654SDoug Thompson "Rev F or later" : "Rev E or earlier"); 8002da11654SDoug Thompson else 8012da11654SDoug Thompson /* we'll hardly ever ever get here */ 8022da11654SDoug Thompson edac_printk(KERN_ERR, EDAC_MC, "Unknown cpu!\n"); 8032da11654SDoug Thompson } 8042da11654SDoug Thompson 8052da11654SDoug Thompson /* 8062da11654SDoug Thompson * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs 8072da11654SDoug Thompson * are ECC capable. 8082da11654SDoug Thompson */ 8092da11654SDoug Thompson static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt) 8102da11654SDoug Thompson { 8112da11654SDoug Thompson int bit; 812584fcff4SBorislav Petkov enum dev_type edac_cap = EDAC_FLAG_NONE; 8132da11654SDoug Thompson 8142da11654SDoug Thompson bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= OPTERON_CPU_REV_F) 8152da11654SDoug Thompson ? 19 8162da11654SDoug Thompson : 17; 8172da11654SDoug Thompson 818584fcff4SBorislav Petkov if (pvt->dclr0 & BIT(bit)) 8192da11654SDoug Thompson edac_cap = EDAC_FLAG_SECDED; 8202da11654SDoug Thompson 8212da11654SDoug Thompson return edac_cap; 8222da11654SDoug Thompson } 8232da11654SDoug Thompson 8242da11654SDoug Thompson 8258566c4dfSBorislav Petkov static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt); 8262da11654SDoug Thompson 82768798e17SBorislav Petkov static void amd64_dump_dramcfg_low(u32 dclr, int chan) 82868798e17SBorislav Petkov { 82968798e17SBorislav Petkov debugf1("F2x%d90 (DRAM Cfg Low): 0x%08x\n", chan, dclr); 83068798e17SBorislav Petkov 83168798e17SBorislav Petkov debugf1(" DIMM type: %sbuffered; all DIMMs support ECC: %s\n", 83268798e17SBorislav Petkov (dclr & BIT(16)) ? "un" : "", 83368798e17SBorislav Petkov (dclr & BIT(19)) ? "yes" : "no"); 83468798e17SBorislav Petkov 83568798e17SBorislav Petkov debugf1(" PAR/ERR parity: %s\n", 83668798e17SBorislav Petkov (dclr & BIT(8)) ? "enabled" : "disabled"); 83768798e17SBorislav Petkov 83868798e17SBorislav Petkov debugf1(" DCT 128bit mode width: %s\n", 83968798e17SBorislav Petkov (dclr & BIT(11)) ? "128b" : "64b"); 84068798e17SBorislav Petkov 84168798e17SBorislav Petkov debugf1(" x4 logical DIMMs present: L0: %s L1: %s L2: %s L3: %s\n", 84268798e17SBorislav Petkov (dclr & BIT(12)) ? "yes" : "no", 84368798e17SBorislav Petkov (dclr & BIT(13)) ? "yes" : "no", 84468798e17SBorislav Petkov (dclr & BIT(14)) ? "yes" : "no", 84568798e17SBorislav Petkov (dclr & BIT(15)) ? "yes" : "no"); 84668798e17SBorislav Petkov } 84768798e17SBorislav Petkov 8482da11654SDoug Thompson /* Display and decode various NB registers for debug purposes. */ 8492da11654SDoug Thompson static void amd64_dump_misc_regs(struct amd64_pvt *pvt) 8502da11654SDoug Thompson { 8512da11654SDoug Thompson int ganged; 8522da11654SDoug Thompson 85368798e17SBorislav Petkov debugf1("F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); 8542da11654SDoug Thompson 85568798e17SBorislav Petkov debugf1(" NB two channel DRAM capable: %s\n", 85668798e17SBorislav Petkov (pvt->nbcap & K8_NBCAP_DCT_DUAL) ? "yes" : "no"); 85768798e17SBorislav Petkov 85868798e17SBorislav Petkov debugf1(" ECC capable: %s, ChipKill ECC capable: %s\n", 85968798e17SBorislav Petkov (pvt->nbcap & K8_NBCAP_SECDED) ? "yes" : "no", 86068798e17SBorislav Petkov (pvt->nbcap & K8_NBCAP_CHIPKILL) ? "yes" : "no"); 86168798e17SBorislav Petkov 86268798e17SBorislav Petkov amd64_dump_dramcfg_low(pvt->dclr0, 0); 8632da11654SDoug Thompson 8648de1d91eSBorislav Petkov debugf1("F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare); 8652da11654SDoug Thompson 8668de1d91eSBorislav Petkov debugf1("F1xF0 (DRAM Hole Address): 0x%08x, base: 0x%08x, " 8678de1d91eSBorislav Petkov "offset: 0x%08x\n", 8688de1d91eSBorislav Petkov pvt->dhar, 8698de1d91eSBorislav Petkov dhar_base(pvt->dhar), 8708de1d91eSBorislav Petkov (boot_cpu_data.x86 == 0xf) ? k8_dhar_offset(pvt->dhar) 8718de1d91eSBorislav Petkov : f10_dhar_offset(pvt->dhar)); 8722da11654SDoug Thompson 8738de1d91eSBorislav Petkov debugf1(" DramHoleValid: %s\n", 8748de1d91eSBorislav Petkov (pvt->dhar & DHAR_VALID) ? "yes" : "no"); 8752da11654SDoug Thompson 8762da11654SDoug Thompson /* everything below this point is Fam10h and above */ 8778566c4dfSBorislav Petkov if (boot_cpu_data.x86 == 0xf) { 8788566c4dfSBorislav Petkov amd64_debug_display_dimm_sizes(0, pvt); 8792da11654SDoug Thompson return; 8808566c4dfSBorislav Petkov } 8812da11654SDoug Thompson 8828de1d91eSBorislav Petkov /* Only if NOT ganged does dclr1 have valid info */ 88368798e17SBorislav Petkov if (!dct_ganging_enabled(pvt)) 88468798e17SBorislav Petkov amd64_dump_dramcfg_low(pvt->dclr1, 1); 8852da11654SDoug Thompson 8862da11654SDoug Thompson /* 8872da11654SDoug Thompson * Determine if ganged and then dump memory sizes for first controller, 8882da11654SDoug Thompson * and if NOT ganged dump info for 2nd controller. 8892da11654SDoug Thompson */ 8902da11654SDoug Thompson ganged = dct_ganging_enabled(pvt); 8912da11654SDoug Thompson 8928566c4dfSBorislav Petkov amd64_debug_display_dimm_sizes(0, pvt); 8932da11654SDoug Thompson 8942da11654SDoug Thompson if (!ganged) 8958566c4dfSBorislav Petkov amd64_debug_display_dimm_sizes(1, pvt); 8962da11654SDoug Thompson } 8972da11654SDoug Thompson 8982da11654SDoug Thompson /* Read in both of DBAM registers */ 8992da11654SDoug Thompson static void amd64_read_dbam_reg(struct amd64_pvt *pvt) 9002da11654SDoug Thompson { 9016ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->dram_f2_ctl, DBAM0, &pvt->dbam0); 9022da11654SDoug Thompson 9036ba5dcdcSBorislav Petkov if (boot_cpu_data.x86 >= 0x10) 9046ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->dram_f2_ctl, DBAM1, &pvt->dbam1); 9052da11654SDoug Thompson } 9062da11654SDoug Thompson 90794be4bffSDoug Thompson /* 90894be4bffSDoug Thompson * NOTE: CPU Revision Dependent code: Rev E and Rev F 90994be4bffSDoug Thompson * 91094be4bffSDoug Thompson * Set the DCSB and DCSM mask values depending on the CPU revision value. Also 91194be4bffSDoug Thompson * set the shift factor for the DCSB and DCSM values. 91294be4bffSDoug Thompson * 91394be4bffSDoug Thompson * ->dcs_mask_notused, RevE: 91494be4bffSDoug Thompson * 91594be4bffSDoug Thompson * To find the max InputAddr for the csrow, start with the base address and set 91694be4bffSDoug Thompson * all bits that are "don't care" bits in the test at the start of section 91794be4bffSDoug Thompson * 3.5.4 (p. 84). 91894be4bffSDoug Thompson * 91994be4bffSDoug Thompson * The "don't care" bits are all set bits in the mask and all bits in the gaps 92094be4bffSDoug Thompson * between bit ranges [35:25] and [19:13]. The value REV_E_DCS_NOTUSED_BITS 92194be4bffSDoug Thompson * represents bits [24:20] and [12:0], which are all bits in the above-mentioned 92294be4bffSDoug Thompson * gaps. 92394be4bffSDoug Thompson * 92494be4bffSDoug Thompson * ->dcs_mask_notused, RevF and later: 92594be4bffSDoug Thompson * 92694be4bffSDoug Thompson * To find the max InputAddr for the csrow, start with the base address and set 92794be4bffSDoug Thompson * all bits that are "don't care" bits in the test at the start of NPT section 92894be4bffSDoug Thompson * 4.5.4 (p. 87). 92994be4bffSDoug Thompson * 93094be4bffSDoug Thompson * The "don't care" bits are all set bits in the mask and all bits in the gaps 93194be4bffSDoug Thompson * between bit ranges [36:27] and [21:13]. 93294be4bffSDoug Thompson * 93394be4bffSDoug Thompson * The value REV_F_F1Xh_DCS_NOTUSED_BITS represents bits [26:22] and [12:0], 93494be4bffSDoug Thompson * which are all bits in the above-mentioned gaps. 93594be4bffSDoug Thompson */ 93694be4bffSDoug Thompson static void amd64_set_dct_base_and_mask(struct amd64_pvt *pvt) 93794be4bffSDoug Thompson { 9389d858bb1SBorislav Petkov 9399d858bb1SBorislav Petkov if (boot_cpu_data.x86 == 0xf && pvt->ext_model < OPTERON_CPU_REV_F) { 9409d858bb1SBorislav Petkov pvt->dcsb_base = REV_E_DCSB_BASE_BITS; 9419d858bb1SBorislav Petkov pvt->dcsm_mask = REV_E_DCSM_MASK_BITS; 9429d858bb1SBorislav Petkov pvt->dcs_mask_notused = REV_E_DCS_NOTUSED_BITS; 9439d858bb1SBorislav Petkov pvt->dcs_shift = REV_E_DCS_SHIFT; 9449d858bb1SBorislav Petkov pvt->cs_count = 8; 9459d858bb1SBorislav Petkov pvt->num_dcsm = 8; 9469d858bb1SBorislav Petkov } else { 94794be4bffSDoug Thompson pvt->dcsb_base = REV_F_F1Xh_DCSB_BASE_BITS; 94894be4bffSDoug Thompson pvt->dcsm_mask = REV_F_F1Xh_DCSM_MASK_BITS; 94994be4bffSDoug Thompson pvt->dcs_mask_notused = REV_F_F1Xh_DCS_NOTUSED_BITS; 95094be4bffSDoug Thompson pvt->dcs_shift = REV_F_F1Xh_DCS_SHIFT; 95194be4bffSDoug Thompson 9529d858bb1SBorislav Petkov if (boot_cpu_data.x86 == 0x11) { 9539d858bb1SBorislav Petkov pvt->cs_count = 4; 9549d858bb1SBorislav Petkov pvt->num_dcsm = 2; 95594be4bffSDoug Thompson } else { 9569d858bb1SBorislav Petkov pvt->cs_count = 8; 9579d858bb1SBorislav Petkov pvt->num_dcsm = 4; 9589d858bb1SBorislav Petkov } 95994be4bffSDoug Thompson } 96094be4bffSDoug Thompson } 96194be4bffSDoug Thompson 96294be4bffSDoug Thompson /* 96394be4bffSDoug Thompson * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask hw registers 96494be4bffSDoug Thompson */ 96594be4bffSDoug Thompson static void amd64_read_dct_base_mask(struct amd64_pvt *pvt) 96694be4bffSDoug Thompson { 9676ba5dcdcSBorislav Petkov int cs, reg; 96894be4bffSDoug Thompson 96994be4bffSDoug Thompson amd64_set_dct_base_and_mask(pvt); 97094be4bffSDoug Thompson 9719d858bb1SBorislav Petkov for (cs = 0; cs < pvt->cs_count; cs++) { 97294be4bffSDoug Thompson reg = K8_DCSB0 + (cs * 4); 9736ba5dcdcSBorislav Petkov if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg, &pvt->dcsb0[cs])) 97494be4bffSDoug Thompson debugf0(" DCSB0[%d]=0x%08x reg: F2x%x\n", 97594be4bffSDoug Thompson cs, pvt->dcsb0[cs], reg); 97694be4bffSDoug Thompson 97794be4bffSDoug Thompson /* If DCT are NOT ganged, then read in DCT1's base */ 97894be4bffSDoug Thompson if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) { 97994be4bffSDoug Thompson reg = F10_DCSB1 + (cs * 4); 9806ba5dcdcSBorislav Petkov if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg, 9816ba5dcdcSBorislav Petkov &pvt->dcsb1[cs])) 98294be4bffSDoug Thompson debugf0(" DCSB1[%d]=0x%08x reg: F2x%x\n", 98394be4bffSDoug Thompson cs, pvt->dcsb1[cs], reg); 98494be4bffSDoug Thompson } else { 98594be4bffSDoug Thompson pvt->dcsb1[cs] = 0; 98694be4bffSDoug Thompson } 98794be4bffSDoug Thompson } 98894be4bffSDoug Thompson 98994be4bffSDoug Thompson for (cs = 0; cs < pvt->num_dcsm; cs++) { 9904afcd2dcSWan Wei reg = K8_DCSM0 + (cs * 4); 9916ba5dcdcSBorislav Petkov if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg, &pvt->dcsm0[cs])) 99294be4bffSDoug Thompson debugf0(" DCSM0[%d]=0x%08x reg: F2x%x\n", 99394be4bffSDoug Thompson cs, pvt->dcsm0[cs], reg); 99494be4bffSDoug Thompson 99594be4bffSDoug Thompson /* If DCT are NOT ganged, then read in DCT1's mask */ 99694be4bffSDoug Thompson if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) { 99794be4bffSDoug Thompson reg = F10_DCSM1 + (cs * 4); 9986ba5dcdcSBorislav Petkov if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, reg, 9996ba5dcdcSBorislav Petkov &pvt->dcsm1[cs])) 100094be4bffSDoug Thompson debugf0(" DCSM1[%d]=0x%08x reg: F2x%x\n", 100194be4bffSDoug Thompson cs, pvt->dcsm1[cs], reg); 10026ba5dcdcSBorislav Petkov } else { 100394be4bffSDoug Thompson pvt->dcsm1[cs] = 0; 100494be4bffSDoug Thompson } 100594be4bffSDoug Thompson } 10066ba5dcdcSBorislav Petkov } 100794be4bffSDoug Thompson 100894be4bffSDoug Thompson static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt) 100994be4bffSDoug Thompson { 101094be4bffSDoug Thompson enum mem_type type; 101194be4bffSDoug Thompson 101294be4bffSDoug Thompson if (boot_cpu_data.x86 >= 0x10 || pvt->ext_model >= OPTERON_CPU_REV_F) { 101394be4bffSDoug Thompson /* Rev F and later */ 101494be4bffSDoug Thompson type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; 101594be4bffSDoug Thompson } else { 101694be4bffSDoug Thompson /* Rev E and earlier */ 101794be4bffSDoug Thompson type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; 101894be4bffSDoug Thompson } 101994be4bffSDoug Thompson 102094be4bffSDoug Thompson debugf1(" Memory type is: %s\n", 102194be4bffSDoug Thompson (type == MEM_DDR2) ? "MEM_DDR2" : 102294be4bffSDoug Thompson (type == MEM_RDDR2) ? "MEM_RDDR2" : 102394be4bffSDoug Thompson (type == MEM_DDR) ? "MEM_DDR" : "MEM_RDDR"); 102494be4bffSDoug Thompson 102594be4bffSDoug Thompson return type; 102694be4bffSDoug Thompson } 102794be4bffSDoug Thompson 1028ddff876dSDoug Thompson /* 1029ddff876dSDoug Thompson * Read the DRAM Configuration Low register. It differs between CG, D & E revs 1030ddff876dSDoug Thompson * and the later RevF memory controllers (DDR vs DDR2) 1031ddff876dSDoug Thompson * 1032ddff876dSDoug Thompson * Return: 1033ddff876dSDoug Thompson * number of memory channels in operation 1034ddff876dSDoug Thompson * Pass back: 1035ddff876dSDoug Thompson * contents of the DCL0_LOW register 1036ddff876dSDoug Thompson */ 1037ddff876dSDoug Thompson static int k8_early_channel_count(struct amd64_pvt *pvt) 1038ddff876dSDoug Thompson { 1039ddff876dSDoug Thompson int flag, err = 0; 1040ddff876dSDoug Thompson 10416ba5dcdcSBorislav Petkov err = amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0); 1042ddff876dSDoug Thompson if (err) 1043ddff876dSDoug Thompson return err; 1044ddff876dSDoug Thompson 1045ddff876dSDoug Thompson if ((boot_cpu_data.x86_model >> 4) >= OPTERON_CPU_REV_F) { 1046ddff876dSDoug Thompson /* RevF (NPT) and later */ 1047ddff876dSDoug Thompson flag = pvt->dclr0 & F10_WIDTH_128; 1048ddff876dSDoug Thompson } else { 1049ddff876dSDoug Thompson /* RevE and earlier */ 1050ddff876dSDoug Thompson flag = pvt->dclr0 & REVE_WIDTH_128; 1051ddff876dSDoug Thompson } 1052ddff876dSDoug Thompson 1053ddff876dSDoug Thompson /* not used */ 1054ddff876dSDoug Thompson pvt->dclr1 = 0; 1055ddff876dSDoug Thompson 1056ddff876dSDoug Thompson return (flag) ? 2 : 1; 1057ddff876dSDoug Thompson } 1058ddff876dSDoug Thompson 1059ddff876dSDoug Thompson /* extract the ERROR ADDRESS for the K8 CPUs */ 1060ddff876dSDoug Thompson static u64 k8_get_error_address(struct mem_ctl_info *mci, 1061ef44cc4cSBorislav Petkov struct err_regs *info) 1062ddff876dSDoug Thompson { 1063ddff876dSDoug Thompson return (((u64) (info->nbeah & 0xff)) << 32) + 1064ddff876dSDoug Thompson (info->nbeal & ~0x03); 1065ddff876dSDoug Thompson } 1066ddff876dSDoug Thompson 1067ddff876dSDoug Thompson /* 1068ddff876dSDoug Thompson * Read the Base and Limit registers for K8 based Memory controllers; extract 1069ddff876dSDoug Thompson * fields from the 'raw' reg into separate data fields 1070ddff876dSDoug Thompson * 1071ddff876dSDoug Thompson * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN 1072ddff876dSDoug Thompson */ 1073ddff876dSDoug Thompson static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram) 1074ddff876dSDoug Thompson { 1075ddff876dSDoug Thompson u32 low; 1076ddff876dSDoug Thompson u32 off = dram << 3; /* 8 bytes between DRAM entries */ 1077ddff876dSDoug Thompson 10786ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->addr_f1_ctl, K8_DRAM_BASE_LOW + off, &low); 1079ddff876dSDoug Thompson 1080ddff876dSDoug Thompson /* Extract parts into separate data entries */ 10814997811eSBorislav Petkov pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 8; 1082ddff876dSDoug Thompson pvt->dram_IntlvEn[dram] = (low >> 8) & 0x7; 1083ddff876dSDoug Thompson pvt->dram_rw_en[dram] = (low & 0x3); 1084ddff876dSDoug Thompson 10856ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->addr_f1_ctl, K8_DRAM_LIMIT_LOW + off, &low); 1086ddff876dSDoug Thompson 1087ddff876dSDoug Thompson /* 1088ddff876dSDoug Thompson * Extract parts into separate data entries. Limit is the HIGHEST memory 1089ddff876dSDoug Thompson * location of the region, so lower 24 bits need to be all ones 1090ddff876dSDoug Thompson */ 10914997811eSBorislav Petkov pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 8) | 0x00FFFFFF; 1092ddff876dSDoug Thompson pvt->dram_IntlvSel[dram] = (low >> 8) & 0x7; 1093ddff876dSDoug Thompson pvt->dram_DstNode[dram] = (low & 0x7); 1094ddff876dSDoug Thompson } 1095ddff876dSDoug Thompson 1096ddff876dSDoug Thompson static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, 1097ef44cc4cSBorislav Petkov struct err_regs *info, 1098ddff876dSDoug Thompson u64 SystemAddress) 1099ddff876dSDoug Thompson { 1100ddff876dSDoug Thompson struct mem_ctl_info *src_mci; 1101ddff876dSDoug Thompson unsigned short syndrome; 1102ddff876dSDoug Thompson int channel, csrow; 1103ddff876dSDoug Thompson u32 page, offset; 1104ddff876dSDoug Thompson 1105ddff876dSDoug Thompson /* Extract the syndrome parts and form a 16-bit syndrome */ 1106b70ef010SBorislav Petkov syndrome = HIGH_SYNDROME(info->nbsl) << 8; 1107b70ef010SBorislav Petkov syndrome |= LOW_SYNDROME(info->nbsh); 1108ddff876dSDoug Thompson 1109ddff876dSDoug Thompson /* CHIPKILL enabled */ 1110ddff876dSDoug Thompson if (info->nbcfg & K8_NBCFG_CHIPKILL) { 1111ddff876dSDoug Thompson channel = get_channel_from_ecc_syndrome(syndrome); 1112ddff876dSDoug Thompson if (channel < 0) { 1113ddff876dSDoug Thompson /* 1114ddff876dSDoug Thompson * Syndrome didn't map, so we don't know which of the 1115ddff876dSDoug Thompson * 2 DIMMs is in error. So we need to ID 'both' of them 1116ddff876dSDoug Thompson * as suspect. 1117ddff876dSDoug Thompson */ 1118ddff876dSDoug Thompson amd64_mc_printk(mci, KERN_WARNING, 1119ddff876dSDoug Thompson "unknown syndrome 0x%x - possible error " 1120ddff876dSDoug Thompson "reporting race\n", syndrome); 1121ddff876dSDoug Thompson edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); 1122ddff876dSDoug Thompson return; 1123ddff876dSDoug Thompson } 1124ddff876dSDoug Thompson } else { 1125ddff876dSDoug Thompson /* 1126ddff876dSDoug Thompson * non-chipkill ecc mode 1127ddff876dSDoug Thompson * 1128ddff876dSDoug Thompson * The k8 documentation is unclear about how to determine the 1129ddff876dSDoug Thompson * channel number when using non-chipkill memory. This method 1130ddff876dSDoug Thompson * was obtained from email communication with someone at AMD. 1131ddff876dSDoug Thompson * (Wish the email was placed in this comment - norsk) 1132ddff876dSDoug Thompson */ 1133ddff876dSDoug Thompson channel = ((SystemAddress & BIT(3)) != 0); 1134ddff876dSDoug Thompson } 1135ddff876dSDoug Thompson 1136ddff876dSDoug Thompson /* 1137ddff876dSDoug Thompson * Find out which node the error address belongs to. This may be 1138ddff876dSDoug Thompson * different from the node that detected the error. 1139ddff876dSDoug Thompson */ 1140ddff876dSDoug Thompson src_mci = find_mc_by_sys_addr(mci, SystemAddress); 11412cff18c2SKeith Mannthey if (!src_mci) { 1142ddff876dSDoug Thompson amd64_mc_printk(mci, KERN_ERR, 1143ddff876dSDoug Thompson "failed to map error address 0x%lx to a node\n", 1144ddff876dSDoug Thompson (unsigned long)SystemAddress); 1145ddff876dSDoug Thompson edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); 1146ddff876dSDoug Thompson return; 1147ddff876dSDoug Thompson } 1148ddff876dSDoug Thompson 1149ddff876dSDoug Thompson /* Now map the SystemAddress to a CSROW */ 1150ddff876dSDoug Thompson csrow = sys_addr_to_csrow(src_mci, SystemAddress); 1151ddff876dSDoug Thompson if (csrow < 0) { 1152ddff876dSDoug Thompson edac_mc_handle_ce_no_info(src_mci, EDAC_MOD_STR); 1153ddff876dSDoug Thompson } else { 1154ddff876dSDoug Thompson error_address_to_page_and_offset(SystemAddress, &page, &offset); 1155ddff876dSDoug Thompson 1156ddff876dSDoug Thompson edac_mc_handle_ce(src_mci, page, offset, syndrome, csrow, 1157ddff876dSDoug Thompson channel, EDAC_MOD_STR); 1158ddff876dSDoug Thompson } 1159ddff876dSDoug Thompson } 1160ddff876dSDoug Thompson 1161ddff876dSDoug Thompson /* 1162ddff876dSDoug Thompson * determrine the number of PAGES in for this DIMM's size based on its DRAM 1163ddff876dSDoug Thompson * Address Mapping. 1164ddff876dSDoug Thompson * 1165ddff876dSDoug Thompson * First step is to calc the number of bits to shift a value of 1 left to 1166ddff876dSDoug Thompson * indicate show many pages. Start with the DBAM value as the starting bits, 1167ddff876dSDoug Thompson * then proceed to adjust those shift bits, based on CPU rev and the table. 1168ddff876dSDoug Thompson * See BKDG on the DBAM 1169ddff876dSDoug Thompson */ 1170ddff876dSDoug Thompson static int k8_dbam_map_to_pages(struct amd64_pvt *pvt, int dram_map) 1171ddff876dSDoug Thompson { 1172ddff876dSDoug Thompson int nr_pages; 1173ddff876dSDoug Thompson 1174ddff876dSDoug Thompson if (pvt->ext_model >= OPTERON_CPU_REV_F) { 1175ddff876dSDoug Thompson nr_pages = 1 << (revf_quad_ddr2_shift[dram_map] - PAGE_SHIFT); 1176ddff876dSDoug Thompson } else { 1177ddff876dSDoug Thompson /* 1178ddff876dSDoug Thompson * RevE and less section; this line is tricky. It collapses the 1179ddff876dSDoug Thompson * table used by RevD and later to one that matches revisions CG 1180ddff876dSDoug Thompson * and earlier. 1181ddff876dSDoug Thompson */ 1182ddff876dSDoug Thompson dram_map -= (pvt->ext_model >= OPTERON_CPU_REV_D) ? 1183ddff876dSDoug Thompson (dram_map > 8 ? 4 : (dram_map > 5 ? 1184ddff876dSDoug Thompson 3 : (dram_map > 2 ? 1 : 0))) : 0; 1185ddff876dSDoug Thompson 1186ddff876dSDoug Thompson /* 25 shift is 32MiB minimum DIMM size in RevE and prior */ 1187ddff876dSDoug Thompson nr_pages = 1 << (dram_map + 25 - PAGE_SHIFT); 1188ddff876dSDoug Thompson } 1189ddff876dSDoug Thompson 1190ddff876dSDoug Thompson return nr_pages; 1191ddff876dSDoug Thompson } 1192ddff876dSDoug Thompson 11931afd3c98SDoug Thompson /* 11941afd3c98SDoug Thompson * Get the number of DCT channels in use. 11951afd3c98SDoug Thompson * 11961afd3c98SDoug Thompson * Return: 11971afd3c98SDoug Thompson * number of Memory Channels in operation 11981afd3c98SDoug Thompson * Pass back: 11991afd3c98SDoug Thompson * contents of the DCL0_LOW register 12001afd3c98SDoug Thompson */ 12011afd3c98SDoug Thompson static int f10_early_channel_count(struct amd64_pvt *pvt) 12021afd3c98SDoug Thompson { 120357a30854SWan Wei int dbams[] = { DBAM0, DBAM1 }; 12046ba5dcdcSBorislav Petkov int i, j, channels = 0; 12051afd3c98SDoug Thompson u32 dbam; 1206ddff876dSDoug Thompson 12071afd3c98SDoug Thompson /* If we are in 128 bit mode, then we are using 2 channels */ 12081afd3c98SDoug Thompson if (pvt->dclr0 & F10_WIDTH_128) { 12091afd3c98SDoug Thompson channels = 2; 12101afd3c98SDoug Thompson return channels; 12111afd3c98SDoug Thompson } 12121afd3c98SDoug Thompson 12131afd3c98SDoug Thompson /* 1214d16149e8SBorislav Petkov * Need to check if in unganged mode: In such, there are 2 channels, 1215d16149e8SBorislav Petkov * but they are not in 128 bit mode and thus the above 'dclr0' status 1216d16149e8SBorislav Petkov * bit will be OFF. 12171afd3c98SDoug Thompson * 12181afd3c98SDoug Thompson * Need to check DCT0[0] and DCT1[0] to see if only one of them has 12191afd3c98SDoug Thompson * their CSEnable bit on. If so, then SINGLE DIMM case. 12201afd3c98SDoug Thompson */ 1221d16149e8SBorislav Petkov debugf0("Data width is not 128 bits - need more decoding\n"); 12221afd3c98SDoug Thompson 12231afd3c98SDoug Thompson /* 12241afd3c98SDoug Thompson * Check DRAM Bank Address Mapping values for each DIMM to see if there 12251afd3c98SDoug Thompson * is more than just one DIMM present in unganged mode. Need to check 12261afd3c98SDoug Thompson * both controllers since DIMMs can be placed in either one. 12271afd3c98SDoug Thompson */ 122857a30854SWan Wei for (i = 0; i < ARRAY_SIZE(dbams); i++) { 12296ba5dcdcSBorislav Petkov if (amd64_read_pci_cfg(pvt->dram_f2_ctl, dbams[i], &dbam)) 12301afd3c98SDoug Thompson goto err_reg; 12311afd3c98SDoug Thompson 123257a30854SWan Wei for (j = 0; j < 4; j++) { 123357a30854SWan Wei if (DBAM_DIMM(j, dbam) > 0) { 12341afd3c98SDoug Thompson channels++; 123557a30854SWan Wei break; 12361afd3c98SDoug Thompson } 123757a30854SWan Wei } 123857a30854SWan Wei } 12391afd3c98SDoug Thompson 1240d16149e8SBorislav Petkov if (channels > 2) 1241d16149e8SBorislav Petkov channels = 2; 1242d16149e8SBorislav Petkov 124337da0450SBorislav Petkov debugf0("MCT channel count: %d\n", channels); 12441afd3c98SDoug Thompson 12451afd3c98SDoug Thompson return channels; 12461afd3c98SDoug Thompson 12471afd3c98SDoug Thompson err_reg: 12481afd3c98SDoug Thompson return -1; 12491afd3c98SDoug Thompson 12501afd3c98SDoug Thompson } 12511afd3c98SDoug Thompson 12521afd3c98SDoug Thompson static int f10_dbam_map_to_pages(struct amd64_pvt *pvt, int dram_map) 12531afd3c98SDoug Thompson { 12541afd3c98SDoug Thompson return 1 << (revf_quad_ddr2_shift[dram_map] - PAGE_SHIFT); 12551afd3c98SDoug Thompson } 12561afd3c98SDoug Thompson 12571afd3c98SDoug Thompson /* Enable extended configuration access via 0xCF8 feature */ 12581afd3c98SDoug Thompson static void amd64_setup(struct amd64_pvt *pvt) 12591afd3c98SDoug Thompson { 12601afd3c98SDoug Thompson u32 reg; 12611afd3c98SDoug Thompson 12626ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, ®); 12631afd3c98SDoug Thompson 12641afd3c98SDoug Thompson pvt->flags.cf8_extcfg = !!(reg & F10_NB_CFG_LOW_ENABLE_EXT_CFG); 12651afd3c98SDoug Thompson reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG; 12661afd3c98SDoug Thompson pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg); 12671afd3c98SDoug Thompson } 12681afd3c98SDoug Thompson 12691afd3c98SDoug Thompson /* Restore the extended configuration access via 0xCF8 feature */ 12701afd3c98SDoug Thompson static void amd64_teardown(struct amd64_pvt *pvt) 12711afd3c98SDoug Thompson { 12721afd3c98SDoug Thompson u32 reg; 12731afd3c98SDoug Thompson 12746ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, ®); 12751afd3c98SDoug Thompson 12761afd3c98SDoug Thompson reg &= ~F10_NB_CFG_LOW_ENABLE_EXT_CFG; 12771afd3c98SDoug Thompson if (pvt->flags.cf8_extcfg) 12781afd3c98SDoug Thompson reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG; 12791afd3c98SDoug Thompson pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg); 12801afd3c98SDoug Thompson } 12811afd3c98SDoug Thompson 12821afd3c98SDoug Thompson static u64 f10_get_error_address(struct mem_ctl_info *mci, 1283ef44cc4cSBorislav Petkov struct err_regs *info) 12841afd3c98SDoug Thompson { 12851afd3c98SDoug Thompson return (((u64) (info->nbeah & 0xffff)) << 32) + 12861afd3c98SDoug Thompson (info->nbeal & ~0x01); 12871afd3c98SDoug Thompson } 12881afd3c98SDoug Thompson 12891afd3c98SDoug Thompson /* 12901afd3c98SDoug Thompson * Read the Base and Limit registers for F10 based Memory controllers. Extract 12911afd3c98SDoug Thompson * fields from the 'raw' reg into separate data fields. 12921afd3c98SDoug Thompson * 12931afd3c98SDoug Thompson * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN. 12941afd3c98SDoug Thompson */ 12951afd3c98SDoug Thompson static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram) 12961afd3c98SDoug Thompson { 12971afd3c98SDoug Thompson u32 high_offset, low_offset, high_base, low_base, high_limit, low_limit; 12981afd3c98SDoug Thompson 12991afd3c98SDoug Thompson low_offset = K8_DRAM_BASE_LOW + (dram << 3); 13001afd3c98SDoug Thompson high_offset = F10_DRAM_BASE_HIGH + (dram << 3); 13011afd3c98SDoug Thompson 13021afd3c98SDoug Thompson /* read the 'raw' DRAM BASE Address register */ 13036ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->addr_f1_ctl, low_offset, &low_base); 13041afd3c98SDoug Thompson 13051afd3c98SDoug Thompson /* Read from the ECS data register */ 13066ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->addr_f1_ctl, high_offset, &high_base); 13071afd3c98SDoug Thompson 13081afd3c98SDoug Thompson /* Extract parts into separate data entries */ 13091afd3c98SDoug Thompson pvt->dram_rw_en[dram] = (low_base & 0x3); 13101afd3c98SDoug Thompson 13111afd3c98SDoug Thompson if (pvt->dram_rw_en[dram] == 0) 13121afd3c98SDoug Thompson return; 13131afd3c98SDoug Thompson 13141afd3c98SDoug Thompson pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7; 13151afd3c98SDoug Thompson 131666216a7aSBorislav Petkov pvt->dram_base[dram] = (((u64)high_base & 0x000000FF) << 40) | 13174997811eSBorislav Petkov (((u64)low_base & 0xFFFF0000) << 8); 13181afd3c98SDoug Thompson 13191afd3c98SDoug Thompson low_offset = K8_DRAM_LIMIT_LOW + (dram << 3); 13201afd3c98SDoug Thompson high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3); 13211afd3c98SDoug Thompson 13221afd3c98SDoug Thompson /* read the 'raw' LIMIT registers */ 13236ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->addr_f1_ctl, low_offset, &low_limit); 13241afd3c98SDoug Thompson 13251afd3c98SDoug Thompson /* Read from the ECS data register for the HIGH portion */ 13266ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->addr_f1_ctl, high_offset, &high_limit); 13271afd3c98SDoug Thompson 13281afd3c98SDoug Thompson debugf0(" HW Regs: BASE=0x%08x-%08x LIMIT= 0x%08x-%08x\n", 13291afd3c98SDoug Thompson high_base, low_base, high_limit, low_limit); 13301afd3c98SDoug Thompson 13311afd3c98SDoug Thompson pvt->dram_DstNode[dram] = (low_limit & 0x7); 13321afd3c98SDoug Thompson pvt->dram_IntlvSel[dram] = (low_limit >> 8) & 0x7; 13331afd3c98SDoug Thompson 13341afd3c98SDoug Thompson /* 13351afd3c98SDoug Thompson * Extract address values and form a LIMIT address. Limit is the HIGHEST 13361afd3c98SDoug Thompson * memory location of the region, so low 24 bits need to be all ones. 13371afd3c98SDoug Thompson */ 133866216a7aSBorislav Petkov pvt->dram_limit[dram] = (((u64)high_limit & 0x000000FF) << 40) | 13394997811eSBorislav Petkov (((u64) low_limit & 0xFFFF0000) << 8) | 134066216a7aSBorislav Petkov 0x00FFFFFF; 13411afd3c98SDoug Thompson } 13426163b5d4SDoug Thompson 13436163b5d4SDoug Thompson static void f10_read_dram_ctl_register(struct amd64_pvt *pvt) 13446163b5d4SDoug Thompson { 13456163b5d4SDoug Thompson 13466ba5dcdcSBorislav Petkov if (!amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCTL_SEL_LOW, 13476ba5dcdcSBorislav Petkov &pvt->dram_ctl_select_low)) { 134872381bd5SBorislav Petkov debugf0("F2x110 (DCTL Sel. Low): 0x%08x, " 134972381bd5SBorislav Petkov "High range addresses at: 0x%x\n", 135072381bd5SBorislav Petkov pvt->dram_ctl_select_low, 135172381bd5SBorislav Petkov dct_sel_baseaddr(pvt)); 13526163b5d4SDoug Thompson 135372381bd5SBorislav Petkov debugf0(" DCT mode: %s, All DCTs on: %s\n", 135472381bd5SBorislav Petkov (dct_ganging_enabled(pvt) ? "ganged" : "unganged"), 135572381bd5SBorislav Petkov (dct_dram_enabled(pvt) ? "yes" : "no")); 13566163b5d4SDoug Thompson 135772381bd5SBorislav Petkov if (!dct_ganging_enabled(pvt)) 135872381bd5SBorislav Petkov debugf0(" Address range split per DCT: %s\n", 135972381bd5SBorislav Petkov (dct_high_range_enabled(pvt) ? "yes" : "no")); 136072381bd5SBorislav Petkov 136172381bd5SBorislav Petkov debugf0(" DCT data interleave for ECC: %s, " 136272381bd5SBorislav Petkov "DRAM cleared since last warm reset: %s\n", 136372381bd5SBorislav Petkov (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"), 136472381bd5SBorislav Petkov (dct_memory_cleared(pvt) ? "yes" : "no")); 136572381bd5SBorislav Petkov 136672381bd5SBorislav Petkov debugf0(" DCT channel interleave: %s, " 136772381bd5SBorislav Petkov "DCT interleave bits selector: 0x%x\n", 136872381bd5SBorislav Petkov (dct_interleave_enabled(pvt) ? "enabled" : "disabled"), 13696163b5d4SDoug Thompson dct_sel_interleave_addr(pvt)); 13706163b5d4SDoug Thompson } 13716163b5d4SDoug Thompson 13726ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCTL_SEL_HIGH, 13736163b5d4SDoug Thompson &pvt->dram_ctl_select_high); 13746163b5d4SDoug Thompson } 13756163b5d4SDoug Thompson 1376f71d0a05SDoug Thompson /* 1377f71d0a05SDoug Thompson * determine channel based on the interleaving mode: F10h BKDG, 2.8.9 Memory 1378f71d0a05SDoug Thompson * Interleaving Modes. 1379f71d0a05SDoug Thompson */ 13806163b5d4SDoug Thompson static u32 f10_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, 13816163b5d4SDoug Thompson int hi_range_sel, u32 intlv_en) 13826163b5d4SDoug Thompson { 13836163b5d4SDoug Thompson u32 cs, temp, dct_sel_high = (pvt->dram_ctl_select_low >> 1) & 1; 13846163b5d4SDoug Thompson 13856163b5d4SDoug Thompson if (dct_ganging_enabled(pvt)) 13866163b5d4SDoug Thompson cs = 0; 13876163b5d4SDoug Thompson else if (hi_range_sel) 13886163b5d4SDoug Thompson cs = dct_sel_high; 13896163b5d4SDoug Thompson else if (dct_interleave_enabled(pvt)) { 1390f71d0a05SDoug Thompson /* 1391f71d0a05SDoug Thompson * see F2x110[DctSelIntLvAddr] - channel interleave mode 1392f71d0a05SDoug Thompson */ 13936163b5d4SDoug Thompson if (dct_sel_interleave_addr(pvt) == 0) 13946163b5d4SDoug Thompson cs = sys_addr >> 6 & 1; 13956163b5d4SDoug Thompson else if ((dct_sel_interleave_addr(pvt) >> 1) & 1) { 13966163b5d4SDoug Thompson temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2; 13976163b5d4SDoug Thompson 13986163b5d4SDoug Thompson if (dct_sel_interleave_addr(pvt) & 1) 13996163b5d4SDoug Thompson cs = (sys_addr >> 9 & 1) ^ temp; 14006163b5d4SDoug Thompson else 14016163b5d4SDoug Thompson cs = (sys_addr >> 6 & 1) ^ temp; 14026163b5d4SDoug Thompson } else if (intlv_en & 4) 14036163b5d4SDoug Thompson cs = sys_addr >> 15 & 1; 14046163b5d4SDoug Thompson else if (intlv_en & 2) 14056163b5d4SDoug Thompson cs = sys_addr >> 14 & 1; 14066163b5d4SDoug Thompson else if (intlv_en & 1) 14076163b5d4SDoug Thompson cs = sys_addr >> 13 & 1; 14086163b5d4SDoug Thompson else 14096163b5d4SDoug Thompson cs = sys_addr >> 12 & 1; 14106163b5d4SDoug Thompson } else if (dct_high_range_enabled(pvt) && !dct_ganging_enabled(pvt)) 14116163b5d4SDoug Thompson cs = ~dct_sel_high & 1; 14126163b5d4SDoug Thompson else 14136163b5d4SDoug Thompson cs = 0; 14146163b5d4SDoug Thompson 14156163b5d4SDoug Thompson return cs; 14166163b5d4SDoug Thompson } 14176163b5d4SDoug Thompson 14186163b5d4SDoug Thompson static inline u32 f10_map_intlv_en_to_shift(u32 intlv_en) 14196163b5d4SDoug Thompson { 14206163b5d4SDoug Thompson if (intlv_en == 1) 14216163b5d4SDoug Thompson return 1; 14226163b5d4SDoug Thompson else if (intlv_en == 3) 14236163b5d4SDoug Thompson return 2; 14246163b5d4SDoug Thompson else if (intlv_en == 7) 14256163b5d4SDoug Thompson return 3; 14266163b5d4SDoug Thompson 14276163b5d4SDoug Thompson return 0; 14286163b5d4SDoug Thompson } 14296163b5d4SDoug Thompson 1430f71d0a05SDoug Thompson /* See F10h BKDG, 2.8.10.2 DctSelBaseOffset Programming */ 1431f71d0a05SDoug Thompson static inline u64 f10_get_base_addr_offset(u64 sys_addr, int hi_range_sel, 14326163b5d4SDoug Thompson u32 dct_sel_base_addr, 14336163b5d4SDoug Thompson u64 dct_sel_base_off, 1434f71d0a05SDoug Thompson u32 hole_valid, u32 hole_off, 14356163b5d4SDoug Thompson u64 dram_base) 14366163b5d4SDoug Thompson { 14376163b5d4SDoug Thompson u64 chan_off; 14386163b5d4SDoug Thompson 14396163b5d4SDoug Thompson if (hi_range_sel) { 14406163b5d4SDoug Thompson if (!(dct_sel_base_addr & 0xFFFFF800) && 1441f71d0a05SDoug Thompson hole_valid && (sys_addr >= 0x100000000ULL)) 14426163b5d4SDoug Thompson chan_off = hole_off << 16; 14436163b5d4SDoug Thompson else 14446163b5d4SDoug Thompson chan_off = dct_sel_base_off; 14456163b5d4SDoug Thompson } else { 1446f71d0a05SDoug Thompson if (hole_valid && (sys_addr >= 0x100000000ULL)) 14476163b5d4SDoug Thompson chan_off = hole_off << 16; 14486163b5d4SDoug Thompson else 14496163b5d4SDoug Thompson chan_off = dram_base & 0xFFFFF8000000ULL; 14506163b5d4SDoug Thompson } 14516163b5d4SDoug Thompson 14526163b5d4SDoug Thompson return (sys_addr & 0x0000FFFFFFFFFFC0ULL) - 14536163b5d4SDoug Thompson (chan_off & 0x0000FFFFFF800000ULL); 14546163b5d4SDoug Thompson } 14556163b5d4SDoug Thompson 14566163b5d4SDoug Thompson /* Hack for the time being - Can we get this from BIOS?? */ 14576163b5d4SDoug Thompson #define CH0SPARE_RANK 0 14586163b5d4SDoug Thompson #define CH1SPARE_RANK 1 14596163b5d4SDoug Thompson 14606163b5d4SDoug Thompson /* 14616163b5d4SDoug Thompson * checks if the csrow passed in is marked as SPARED, if so returns the new 14626163b5d4SDoug Thompson * spare row 14636163b5d4SDoug Thompson */ 14646163b5d4SDoug Thompson static inline int f10_process_possible_spare(int csrow, 14656163b5d4SDoug Thompson u32 cs, struct amd64_pvt *pvt) 14666163b5d4SDoug Thompson { 14676163b5d4SDoug Thompson u32 swap_done; 14686163b5d4SDoug Thompson u32 bad_dram_cs; 14696163b5d4SDoug Thompson 14706163b5d4SDoug Thompson /* Depending on channel, isolate respective SPARING info */ 14716163b5d4SDoug Thompson if (cs) { 14726163b5d4SDoug Thompson swap_done = F10_ONLINE_SPARE_SWAPDONE1(pvt->online_spare); 14736163b5d4SDoug Thompson bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS1(pvt->online_spare); 14746163b5d4SDoug Thompson if (swap_done && (csrow == bad_dram_cs)) 14756163b5d4SDoug Thompson csrow = CH1SPARE_RANK; 14766163b5d4SDoug Thompson } else { 14776163b5d4SDoug Thompson swap_done = F10_ONLINE_SPARE_SWAPDONE0(pvt->online_spare); 14786163b5d4SDoug Thompson bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS0(pvt->online_spare); 14796163b5d4SDoug Thompson if (swap_done && (csrow == bad_dram_cs)) 14806163b5d4SDoug Thompson csrow = CH0SPARE_RANK; 14816163b5d4SDoug Thompson } 14826163b5d4SDoug Thompson return csrow; 14836163b5d4SDoug Thompson } 14846163b5d4SDoug Thompson 14856163b5d4SDoug Thompson /* 14866163b5d4SDoug Thompson * Iterate over the DRAM DCT "base" and "mask" registers looking for a 14876163b5d4SDoug Thompson * SystemAddr match on the specified 'ChannelSelect' and 'NodeID' 14886163b5d4SDoug Thompson * 14896163b5d4SDoug Thompson * Return: 14906163b5d4SDoug Thompson * -EINVAL: NOT FOUND 14916163b5d4SDoug Thompson * 0..csrow = Chip-Select Row 14926163b5d4SDoug Thompson */ 14936163b5d4SDoug Thompson static int f10_lookup_addr_in_dct(u32 in_addr, u32 nid, u32 cs) 14946163b5d4SDoug Thompson { 14956163b5d4SDoug Thompson struct mem_ctl_info *mci; 14966163b5d4SDoug Thompson struct amd64_pvt *pvt; 14976163b5d4SDoug Thompson u32 cs_base, cs_mask; 14986163b5d4SDoug Thompson int cs_found = -EINVAL; 14996163b5d4SDoug Thompson int csrow; 15006163b5d4SDoug Thompson 15016163b5d4SDoug Thompson mci = mci_lookup[nid]; 15026163b5d4SDoug Thompson if (!mci) 15036163b5d4SDoug Thompson return cs_found; 15046163b5d4SDoug Thompson 15056163b5d4SDoug Thompson pvt = mci->pvt_info; 15066163b5d4SDoug Thompson 15076163b5d4SDoug Thompson debugf1("InputAddr=0x%x channelselect=%d\n", in_addr, cs); 15086163b5d4SDoug Thompson 15099d858bb1SBorislav Petkov for (csrow = 0; csrow < pvt->cs_count; csrow++) { 15106163b5d4SDoug Thompson 15116163b5d4SDoug Thompson cs_base = amd64_get_dct_base(pvt, cs, csrow); 15126163b5d4SDoug Thompson if (!(cs_base & K8_DCSB_CS_ENABLE)) 15136163b5d4SDoug Thompson continue; 15146163b5d4SDoug Thompson 15156163b5d4SDoug Thompson /* 15166163b5d4SDoug Thompson * We have an ENABLED CSROW, Isolate just the MASK bits of the 15176163b5d4SDoug Thompson * target: [28:19] and [13:5], which map to [36:27] and [21:13] 15186163b5d4SDoug Thompson * of the actual address. 15196163b5d4SDoug Thompson */ 15206163b5d4SDoug Thompson cs_base &= REV_F_F1Xh_DCSB_BASE_BITS; 15216163b5d4SDoug Thompson 15226163b5d4SDoug Thompson /* 15236163b5d4SDoug Thompson * Get the DCT Mask, and ENABLE the reserved bits: [18:16] and 15246163b5d4SDoug Thompson * [4:0] to become ON. Then mask off bits [28:0] ([36:8]) 15256163b5d4SDoug Thompson */ 15266163b5d4SDoug Thompson cs_mask = amd64_get_dct_mask(pvt, cs, csrow); 15276163b5d4SDoug Thompson 15286163b5d4SDoug Thompson debugf1(" CSROW=%d CSBase=0x%x RAW CSMask=0x%x\n", 15296163b5d4SDoug Thompson csrow, cs_base, cs_mask); 15306163b5d4SDoug Thompson 15316163b5d4SDoug Thompson cs_mask = (cs_mask | 0x0007C01F) & 0x1FFFFFFF; 15326163b5d4SDoug Thompson 15336163b5d4SDoug Thompson debugf1(" Final CSMask=0x%x\n", cs_mask); 15346163b5d4SDoug Thompson debugf1(" (InputAddr & ~CSMask)=0x%x " 15356163b5d4SDoug Thompson "(CSBase & ~CSMask)=0x%x\n", 15366163b5d4SDoug Thompson (in_addr & ~cs_mask), (cs_base & ~cs_mask)); 15376163b5d4SDoug Thompson 15386163b5d4SDoug Thompson if ((in_addr & ~cs_mask) == (cs_base & ~cs_mask)) { 15396163b5d4SDoug Thompson cs_found = f10_process_possible_spare(csrow, cs, pvt); 15406163b5d4SDoug Thompson 15416163b5d4SDoug Thompson debugf1(" MATCH csrow=%d\n", cs_found); 15426163b5d4SDoug Thompson break; 15436163b5d4SDoug Thompson } 15446163b5d4SDoug Thompson } 15456163b5d4SDoug Thompson return cs_found; 15466163b5d4SDoug Thompson } 15476163b5d4SDoug Thompson 1548f71d0a05SDoug Thompson /* For a given @dram_range, check if @sys_addr falls within it. */ 1549f71d0a05SDoug Thompson static int f10_match_to_this_node(struct amd64_pvt *pvt, int dram_range, 1550f71d0a05SDoug Thompson u64 sys_addr, int *nid, int *chan_sel) 1551f71d0a05SDoug Thompson { 1552f71d0a05SDoug Thompson int node_id, cs_found = -EINVAL, high_range = 0; 1553f71d0a05SDoug Thompson u32 intlv_en, intlv_sel, intlv_shift, hole_off; 1554f71d0a05SDoug Thompson u32 hole_valid, tmp, dct_sel_base, channel; 1555f71d0a05SDoug Thompson u64 dram_base, chan_addr, dct_sel_base_off; 1556f71d0a05SDoug Thompson 1557f71d0a05SDoug Thompson dram_base = pvt->dram_base[dram_range]; 1558f71d0a05SDoug Thompson intlv_en = pvt->dram_IntlvEn[dram_range]; 1559f71d0a05SDoug Thompson 1560f71d0a05SDoug Thompson node_id = pvt->dram_DstNode[dram_range]; 1561f71d0a05SDoug Thompson intlv_sel = pvt->dram_IntlvSel[dram_range]; 1562f71d0a05SDoug Thompson 1563f71d0a05SDoug Thompson debugf1("(dram=%d) Base=0x%llx SystemAddr= 0x%llx Limit=0x%llx\n", 1564f71d0a05SDoug Thompson dram_range, dram_base, sys_addr, pvt->dram_limit[dram_range]); 1565f71d0a05SDoug Thompson 1566f71d0a05SDoug Thompson /* 1567f71d0a05SDoug Thompson * This assumes that one node's DHAR is the same as all the other 1568f71d0a05SDoug Thompson * nodes' DHAR. 1569f71d0a05SDoug Thompson */ 1570f71d0a05SDoug Thompson hole_off = (pvt->dhar & 0x0000FF80); 1571f71d0a05SDoug Thompson hole_valid = (pvt->dhar & 0x1); 1572f71d0a05SDoug Thompson dct_sel_base_off = (pvt->dram_ctl_select_high & 0xFFFFFC00) << 16; 1573f71d0a05SDoug Thompson 1574f71d0a05SDoug Thompson debugf1(" HoleOffset=0x%x HoleValid=0x%x IntlvSel=0x%x\n", 1575f71d0a05SDoug Thompson hole_off, hole_valid, intlv_sel); 1576f71d0a05SDoug Thompson 1577f71d0a05SDoug Thompson if (intlv_en || 1578f71d0a05SDoug Thompson (intlv_sel != ((sys_addr >> 12) & intlv_en))) 1579f71d0a05SDoug Thompson return -EINVAL; 1580f71d0a05SDoug Thompson 1581f71d0a05SDoug Thompson dct_sel_base = dct_sel_baseaddr(pvt); 1582f71d0a05SDoug Thompson 1583f71d0a05SDoug Thompson /* 1584f71d0a05SDoug Thompson * check whether addresses >= DctSelBaseAddr[47:27] are to be used to 1585f71d0a05SDoug Thompson * select between DCT0 and DCT1. 1586f71d0a05SDoug Thompson */ 1587f71d0a05SDoug Thompson if (dct_high_range_enabled(pvt) && 1588f71d0a05SDoug Thompson !dct_ganging_enabled(pvt) && 1589f71d0a05SDoug Thompson ((sys_addr >> 27) >= (dct_sel_base >> 11))) 1590f71d0a05SDoug Thompson high_range = 1; 1591f71d0a05SDoug Thompson 1592f71d0a05SDoug Thompson channel = f10_determine_channel(pvt, sys_addr, high_range, intlv_en); 1593f71d0a05SDoug Thompson 1594f71d0a05SDoug Thompson chan_addr = f10_get_base_addr_offset(sys_addr, high_range, dct_sel_base, 1595f71d0a05SDoug Thompson dct_sel_base_off, hole_valid, 1596f71d0a05SDoug Thompson hole_off, dram_base); 1597f71d0a05SDoug Thompson 1598f71d0a05SDoug Thompson intlv_shift = f10_map_intlv_en_to_shift(intlv_en); 1599f71d0a05SDoug Thompson 1600f71d0a05SDoug Thompson /* remove Node ID (in case of memory interleaving) */ 1601f71d0a05SDoug Thompson tmp = chan_addr & 0xFC0; 1602f71d0a05SDoug Thompson 1603f71d0a05SDoug Thompson chan_addr = ((chan_addr >> intlv_shift) & 0xFFFFFFFFF000ULL) | tmp; 1604f71d0a05SDoug Thompson 1605f71d0a05SDoug Thompson /* remove channel interleave and hash */ 1606f71d0a05SDoug Thompson if (dct_interleave_enabled(pvt) && 1607f71d0a05SDoug Thompson !dct_high_range_enabled(pvt) && 1608f71d0a05SDoug Thompson !dct_ganging_enabled(pvt)) { 1609f71d0a05SDoug Thompson if (dct_sel_interleave_addr(pvt) != 1) 1610f71d0a05SDoug Thompson chan_addr = (chan_addr >> 1) & 0xFFFFFFFFFFFFFFC0ULL; 1611f71d0a05SDoug Thompson else { 1612f71d0a05SDoug Thompson tmp = chan_addr & 0xFC0; 1613f71d0a05SDoug Thompson chan_addr = ((chan_addr & 0xFFFFFFFFFFFFC000ULL) >> 1) 1614f71d0a05SDoug Thompson | tmp; 1615f71d0a05SDoug Thompson } 1616f71d0a05SDoug Thompson } 1617f71d0a05SDoug Thompson 1618f71d0a05SDoug Thompson debugf1(" (ChannelAddrLong=0x%llx) >> 8 becomes InputAddr=0x%x\n", 1619f71d0a05SDoug Thompson chan_addr, (u32)(chan_addr >> 8)); 1620f71d0a05SDoug Thompson 1621f71d0a05SDoug Thompson cs_found = f10_lookup_addr_in_dct(chan_addr >> 8, node_id, channel); 1622f71d0a05SDoug Thompson 1623f71d0a05SDoug Thompson if (cs_found >= 0) { 1624f71d0a05SDoug Thompson *nid = node_id; 1625f71d0a05SDoug Thompson *chan_sel = channel; 1626f71d0a05SDoug Thompson } 1627f71d0a05SDoug Thompson return cs_found; 1628f71d0a05SDoug Thompson } 1629f71d0a05SDoug Thompson 1630f71d0a05SDoug Thompson static int f10_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr, 1631f71d0a05SDoug Thompson int *node, int *chan_sel) 1632f71d0a05SDoug Thompson { 1633f71d0a05SDoug Thompson int dram_range, cs_found = -EINVAL; 1634f71d0a05SDoug Thompson u64 dram_base, dram_limit; 1635f71d0a05SDoug Thompson 1636f71d0a05SDoug Thompson for (dram_range = 0; dram_range < DRAM_REG_COUNT; dram_range++) { 1637f71d0a05SDoug Thompson 1638f71d0a05SDoug Thompson if (!pvt->dram_rw_en[dram_range]) 1639f71d0a05SDoug Thompson continue; 1640f71d0a05SDoug Thompson 1641f71d0a05SDoug Thompson dram_base = pvt->dram_base[dram_range]; 1642f71d0a05SDoug Thompson dram_limit = pvt->dram_limit[dram_range]; 1643f71d0a05SDoug Thompson 1644f71d0a05SDoug Thompson if ((dram_base <= sys_addr) && (sys_addr <= dram_limit)) { 1645f71d0a05SDoug Thompson 1646f71d0a05SDoug Thompson cs_found = f10_match_to_this_node(pvt, dram_range, 1647f71d0a05SDoug Thompson sys_addr, node, 1648f71d0a05SDoug Thompson chan_sel); 1649f71d0a05SDoug Thompson if (cs_found >= 0) 1650f71d0a05SDoug Thompson break; 1651f71d0a05SDoug Thompson } 1652f71d0a05SDoug Thompson } 1653f71d0a05SDoug Thompson return cs_found; 1654f71d0a05SDoug Thompson } 1655f71d0a05SDoug Thompson 1656f71d0a05SDoug Thompson /* 1657f71d0a05SDoug Thompson * This the F10h reference code from AMD to map a @sys_addr to NodeID, 1658f71d0a05SDoug Thompson * CSROW, Channel. 1659f71d0a05SDoug Thompson * 1660f71d0a05SDoug Thompson * The @sys_addr is usually an error address received from the hardware. 1661f71d0a05SDoug Thompson */ 1662f71d0a05SDoug Thompson static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci, 1663ef44cc4cSBorislav Petkov struct err_regs *info, 1664f71d0a05SDoug Thompson u64 sys_addr) 1665f71d0a05SDoug Thompson { 1666f71d0a05SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 1667f71d0a05SDoug Thompson u32 page, offset; 1668f71d0a05SDoug Thompson unsigned short syndrome; 1669f71d0a05SDoug Thompson int nid, csrow, chan = 0; 1670f71d0a05SDoug Thompson 1671f71d0a05SDoug Thompson csrow = f10_translate_sysaddr_to_cs(pvt, sys_addr, &nid, &chan); 1672f71d0a05SDoug Thompson 1673f71d0a05SDoug Thompson if (csrow >= 0) { 1674f71d0a05SDoug Thompson error_address_to_page_and_offset(sys_addr, &page, &offset); 1675f71d0a05SDoug Thompson 1676b70ef010SBorislav Petkov syndrome = HIGH_SYNDROME(info->nbsl) << 8; 1677b70ef010SBorislav Petkov syndrome |= LOW_SYNDROME(info->nbsh); 1678f71d0a05SDoug Thompson 1679f71d0a05SDoug Thompson /* 1680f71d0a05SDoug Thompson * Is CHIPKILL on? If so, then we can attempt to use the 1681f71d0a05SDoug Thompson * syndrome to isolate which channel the error was on. 1682f71d0a05SDoug Thompson */ 1683f71d0a05SDoug Thompson if (pvt->nbcfg & K8_NBCFG_CHIPKILL) 1684f71d0a05SDoug Thompson chan = get_channel_from_ecc_syndrome(syndrome); 1685f71d0a05SDoug Thompson 1686f71d0a05SDoug Thompson if (chan >= 0) { 1687f71d0a05SDoug Thompson edac_mc_handle_ce(mci, page, offset, syndrome, 1688f71d0a05SDoug Thompson csrow, chan, EDAC_MOD_STR); 1689f71d0a05SDoug Thompson } else { 1690f71d0a05SDoug Thompson /* 1691f71d0a05SDoug Thompson * Channel unknown, report all channels on this 1692f71d0a05SDoug Thompson * CSROW as failed. 1693f71d0a05SDoug Thompson */ 1694f71d0a05SDoug Thompson for (chan = 0; chan < mci->csrows[csrow].nr_channels; 1695f71d0a05SDoug Thompson chan++) { 1696f71d0a05SDoug Thompson edac_mc_handle_ce(mci, page, offset, 1697f71d0a05SDoug Thompson syndrome, 1698f71d0a05SDoug Thompson csrow, chan, 1699f71d0a05SDoug Thompson EDAC_MOD_STR); 1700f71d0a05SDoug Thompson } 1701f71d0a05SDoug Thompson } 1702f71d0a05SDoug Thompson 1703f71d0a05SDoug Thompson } else { 1704f71d0a05SDoug Thompson edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); 1705f71d0a05SDoug Thompson } 1706f71d0a05SDoug Thompson } 1707f71d0a05SDoug Thompson 1708f71d0a05SDoug Thompson /* 1709f71d0a05SDoug Thompson * Input (@index) is the DBAM DIMM value (1 of 4) used as an index into a shift 1710f71d0a05SDoug Thompson * table (revf_quad_ddr2_shift) which starts at 128MB DIMM size. Index of 0 1711f71d0a05SDoug Thompson * indicates an empty DIMM slot, as reported by Hardware on empty slots. 1712f71d0a05SDoug Thompson * 1713f71d0a05SDoug Thompson * Normalize to 128MB by subracting 27 bit shift. 1714f71d0a05SDoug Thompson */ 1715f71d0a05SDoug Thompson static int map_dbam_to_csrow_size(int index) 1716f71d0a05SDoug Thompson { 1717f71d0a05SDoug Thompson int mega_bytes = 0; 1718f71d0a05SDoug Thompson 1719f71d0a05SDoug Thompson if (index > 0 && index <= DBAM_MAX_VALUE) 1720f71d0a05SDoug Thompson mega_bytes = ((128 << (revf_quad_ddr2_shift[index]-27))); 1721f71d0a05SDoug Thompson 1722f71d0a05SDoug Thompson return mega_bytes; 1723f71d0a05SDoug Thompson } 1724f71d0a05SDoug Thompson 1725f71d0a05SDoug Thompson /* 17268566c4dfSBorislav Petkov * debug routine to display the memory sizes of all logical DIMMs and its 1727f71d0a05SDoug Thompson * CSROWs as well 1728f71d0a05SDoug Thompson */ 17298566c4dfSBorislav Petkov static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt) 1730f71d0a05SDoug Thompson { 1731f71d0a05SDoug Thompson int dimm, size0, size1; 1732f71d0a05SDoug Thompson u32 dbam; 1733f71d0a05SDoug Thompson u32 *dcsb; 1734f71d0a05SDoug Thompson 17358566c4dfSBorislav Petkov if (boot_cpu_data.x86 == 0xf) { 17368566c4dfSBorislav Petkov /* K8 families < revF not supported yet */ 17378566c4dfSBorislav Petkov if (pvt->ext_model < OPTERON_CPU_REV_F) 17388566c4dfSBorislav Petkov return; 17398566c4dfSBorislav Petkov else 17408566c4dfSBorislav Petkov WARN_ON(ctrl != 0); 17418566c4dfSBorislav Petkov } 17428566c4dfSBorislav Petkov 17438566c4dfSBorislav Petkov debugf1("F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n", 17448566c4dfSBorislav Petkov ctrl, ctrl ? pvt->dbam1 : pvt->dbam0); 1745f71d0a05SDoug Thompson 1746f71d0a05SDoug Thompson dbam = ctrl ? pvt->dbam1 : pvt->dbam0; 1747f71d0a05SDoug Thompson dcsb = ctrl ? pvt->dcsb1 : pvt->dcsb0; 1748f71d0a05SDoug Thompson 17498566c4dfSBorislav Petkov edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl); 17508566c4dfSBorislav Petkov 1751f71d0a05SDoug Thompson /* Dump memory sizes for DIMM and its CSROWs */ 1752f71d0a05SDoug Thompson for (dimm = 0; dimm < 4; dimm++) { 1753f71d0a05SDoug Thompson 1754f71d0a05SDoug Thompson size0 = 0; 1755f71d0a05SDoug Thompson if (dcsb[dimm*2] & K8_DCSB_CS_ENABLE) 1756f71d0a05SDoug Thompson size0 = map_dbam_to_csrow_size(DBAM_DIMM(dimm, dbam)); 1757f71d0a05SDoug Thompson 1758f71d0a05SDoug Thompson size1 = 0; 1759f71d0a05SDoug Thompson if (dcsb[dimm*2 + 1] & K8_DCSB_CS_ENABLE) 1760f71d0a05SDoug Thompson size1 = map_dbam_to_csrow_size(DBAM_DIMM(dimm, dbam)); 1761f71d0a05SDoug Thompson 17628566c4dfSBorislav Petkov edac_printk(KERN_DEBUG, EDAC_MC, " %d: %5dMB %d: %5dMB\n", 17638566c4dfSBorislav Petkov dimm * 2, size0, dimm * 2 + 1, size1); 1764f71d0a05SDoug Thompson } 1765f71d0a05SDoug Thompson } 1766f71d0a05SDoug Thompson 1767f71d0a05SDoug Thompson /* 1768f71d0a05SDoug Thompson * Very early hardware probe on pci_probe thread to determine if this module 1769f71d0a05SDoug Thompson * supports the hardware. 1770f71d0a05SDoug Thompson * 1771f71d0a05SDoug Thompson * Return: 1772f71d0a05SDoug Thompson * 0 for OK 1773f71d0a05SDoug Thompson * 1 for error 1774f71d0a05SDoug Thompson */ 1775f71d0a05SDoug Thompson static int f10_probe_valid_hardware(struct amd64_pvt *pvt) 1776f71d0a05SDoug Thompson { 1777f71d0a05SDoug Thompson int ret = 0; 1778f71d0a05SDoug Thompson 1779f71d0a05SDoug Thompson /* 1780f71d0a05SDoug Thompson * If we are on a DDR3 machine, we don't know yet if 1781f71d0a05SDoug Thompson * we support that properly at this time 1782f71d0a05SDoug Thompson */ 1783f71d0a05SDoug Thompson if ((pvt->dchr0 & F10_DCHR_Ddr3Mode) || 1784f71d0a05SDoug Thompson (pvt->dchr1 & F10_DCHR_Ddr3Mode)) { 1785f71d0a05SDoug Thompson 1786f71d0a05SDoug Thompson amd64_printk(KERN_WARNING, 1787f71d0a05SDoug Thompson "%s() This machine is running with DDR3 memory. " 1788f71d0a05SDoug Thompson "This is not currently supported. " 1789f71d0a05SDoug Thompson "DCHR0=0x%x DCHR1=0x%x\n", 1790f71d0a05SDoug Thompson __func__, pvt->dchr0, pvt->dchr1); 1791f71d0a05SDoug Thompson 1792f71d0a05SDoug Thompson amd64_printk(KERN_WARNING, 1793f71d0a05SDoug Thompson " Contact '%s' module MAINTAINER to help add" 1794f71d0a05SDoug Thompson " support.\n", 1795f71d0a05SDoug Thompson EDAC_MOD_STR); 1796f71d0a05SDoug Thompson 1797f71d0a05SDoug Thompson ret = 1; 1798f71d0a05SDoug Thompson 1799f71d0a05SDoug Thompson } 1800f71d0a05SDoug Thompson return ret; 1801f71d0a05SDoug Thompson } 18026163b5d4SDoug Thompson 18034d37607aSDoug Thompson /* 18044d37607aSDoug Thompson * There currently are 3 types type of MC devices for AMD Athlon/Opterons 18054d37607aSDoug Thompson * (as per PCI DEVICE_IDs): 18064d37607aSDoug Thompson * 18074d37607aSDoug Thompson * Family K8: That is the Athlon64 and Opteron CPUs. They all have the same PCI 18084d37607aSDoug Thompson * DEVICE ID, even though there is differences between the different Revisions 18094d37607aSDoug Thompson * (CG,D,E,F). 18104d37607aSDoug Thompson * 18114d37607aSDoug Thompson * Family F10h and F11h. 18124d37607aSDoug Thompson * 18134d37607aSDoug Thompson */ 18144d37607aSDoug Thompson static struct amd64_family_type amd64_family_types[] = { 18154d37607aSDoug Thompson [K8_CPUS] = { 18164d37607aSDoug Thompson .ctl_name = "RevF", 18174d37607aSDoug Thompson .addr_f1_ctl = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP, 18184d37607aSDoug Thompson .misc_f3_ctl = PCI_DEVICE_ID_AMD_K8_NB_MISC, 18194d37607aSDoug Thompson .ops = { 18204d37607aSDoug Thompson .early_channel_count = k8_early_channel_count, 18214d37607aSDoug Thompson .get_error_address = k8_get_error_address, 18224d37607aSDoug Thompson .read_dram_base_limit = k8_read_dram_base_limit, 18234d37607aSDoug Thompson .map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow, 18244d37607aSDoug Thompson .dbam_map_to_pages = k8_dbam_map_to_pages, 18254d37607aSDoug Thompson } 18264d37607aSDoug Thompson }, 18274d37607aSDoug Thompson [F10_CPUS] = { 18284d37607aSDoug Thompson .ctl_name = "Family 10h", 18294d37607aSDoug Thompson .addr_f1_ctl = PCI_DEVICE_ID_AMD_10H_NB_MAP, 18304d37607aSDoug Thompson .misc_f3_ctl = PCI_DEVICE_ID_AMD_10H_NB_MISC, 18314d37607aSDoug Thompson .ops = { 18324d37607aSDoug Thompson .probe_valid_hardware = f10_probe_valid_hardware, 18334d37607aSDoug Thompson .early_channel_count = f10_early_channel_count, 18344d37607aSDoug Thompson .get_error_address = f10_get_error_address, 18354d37607aSDoug Thompson .read_dram_base_limit = f10_read_dram_base_limit, 18364d37607aSDoug Thompson .read_dram_ctl_register = f10_read_dram_ctl_register, 18374d37607aSDoug Thompson .map_sysaddr_to_csrow = f10_map_sysaddr_to_csrow, 18384d37607aSDoug Thompson .dbam_map_to_pages = f10_dbam_map_to_pages, 18394d37607aSDoug Thompson } 18404d37607aSDoug Thompson }, 18414d37607aSDoug Thompson [F11_CPUS] = { 18424d37607aSDoug Thompson .ctl_name = "Family 11h", 18434d37607aSDoug Thompson .addr_f1_ctl = PCI_DEVICE_ID_AMD_11H_NB_MAP, 18444d37607aSDoug Thompson .misc_f3_ctl = PCI_DEVICE_ID_AMD_11H_NB_MISC, 18454d37607aSDoug Thompson .ops = { 18464d37607aSDoug Thompson .probe_valid_hardware = f10_probe_valid_hardware, 18474d37607aSDoug Thompson .early_channel_count = f10_early_channel_count, 18484d37607aSDoug Thompson .get_error_address = f10_get_error_address, 18494d37607aSDoug Thompson .read_dram_base_limit = f10_read_dram_base_limit, 18504d37607aSDoug Thompson .read_dram_ctl_register = f10_read_dram_ctl_register, 18514d37607aSDoug Thompson .map_sysaddr_to_csrow = f10_map_sysaddr_to_csrow, 18524d37607aSDoug Thompson .dbam_map_to_pages = f10_dbam_map_to_pages, 18534d37607aSDoug Thompson } 18544d37607aSDoug Thompson }, 18554d37607aSDoug Thompson }; 18564d37607aSDoug Thompson 18574d37607aSDoug Thompson static struct pci_dev *pci_get_related_function(unsigned int vendor, 18584d37607aSDoug Thompson unsigned int device, 18594d37607aSDoug Thompson struct pci_dev *related) 18604d37607aSDoug Thompson { 18614d37607aSDoug Thompson struct pci_dev *dev = NULL; 18624d37607aSDoug Thompson 18634d37607aSDoug Thompson dev = pci_get_device(vendor, device, dev); 18644d37607aSDoug Thompson while (dev) { 18654d37607aSDoug Thompson if ((dev->bus->number == related->bus->number) && 18664d37607aSDoug Thompson (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn))) 18674d37607aSDoug Thompson break; 18684d37607aSDoug Thompson dev = pci_get_device(vendor, device, dev); 18694d37607aSDoug Thompson } 18704d37607aSDoug Thompson 18714d37607aSDoug Thompson return dev; 18724d37607aSDoug Thompson } 18734d37607aSDoug Thompson 1874b1289d6fSDoug Thompson /* 1875b1289d6fSDoug Thompson * syndrome mapping table for ECC ChipKill devices 1876b1289d6fSDoug Thompson * 1877b1289d6fSDoug Thompson * The comment in each row is the token (nibble) number that is in error. 1878b1289d6fSDoug Thompson * The least significant nibble of the syndrome is the mask for the bits 1879b1289d6fSDoug Thompson * that are in error (need to be toggled) for the particular nibble. 1880b1289d6fSDoug Thompson * 1881b1289d6fSDoug Thompson * Each row contains 16 entries. 1882b1289d6fSDoug Thompson * The first entry (0th) is the channel number for that row of syndromes. 1883b1289d6fSDoug Thompson * The remaining 15 entries are the syndromes for the respective Error 1884b1289d6fSDoug Thompson * bit mask index. 1885b1289d6fSDoug Thompson * 1886b1289d6fSDoug Thompson * 1st index entry is 0x0001 mask, indicating that the rightmost bit is the 1887b1289d6fSDoug Thompson * bit in error. 1888b1289d6fSDoug Thompson * The 2nd index entry is 0x0010 that the second bit is damaged. 1889b1289d6fSDoug Thompson * The 3rd index entry is 0x0011 indicating that the rightmost 2 bits 1890b1289d6fSDoug Thompson * are damaged. 1891b1289d6fSDoug Thompson * Thus so on until index 15, 0x1111, whose entry has the syndrome 1892b1289d6fSDoug Thompson * indicating that all 4 bits are damaged. 1893b1289d6fSDoug Thompson * 1894b1289d6fSDoug Thompson * A search is performed on this table looking for a given syndrome. 1895b1289d6fSDoug Thompson * 1896b1289d6fSDoug Thompson * See the AMD documentation for ECC syndromes. This ECC table is valid 1897b1289d6fSDoug Thompson * across all the versions of the AMD64 processors. 1898b1289d6fSDoug Thompson * 1899b1289d6fSDoug Thompson * A fast lookup is to use the LAST four bits of the 16-bit syndrome as a 1900b1289d6fSDoug Thompson * COLUMN index, then search all ROWS of that column, looking for a match 1901b1289d6fSDoug Thompson * with the input syndrome. The ROW value will be the token number. 1902b1289d6fSDoug Thompson * 1903b1289d6fSDoug Thompson * The 0'th entry on that row, can be returned as the CHANNEL (0 or 1) of this 1904b1289d6fSDoug Thompson * error. 1905b1289d6fSDoug Thompson */ 1906b1289d6fSDoug Thompson #define NUMBER_ECC_ROWS 36 1907b1289d6fSDoug Thompson static const unsigned short ecc_chipkill_syndromes[NUMBER_ECC_ROWS][16] = { 1908b1289d6fSDoug Thompson /* Channel 0 syndromes */ 1909b1289d6fSDoug Thompson {/*0*/ 0, 0xe821, 0x7c32, 0x9413, 0xbb44, 0x5365, 0xc776, 0x2f57, 1910b1289d6fSDoug Thompson 0xdd88, 0x35a9, 0xa1ba, 0x499b, 0x66cc, 0x8eed, 0x1afe, 0xf2df }, 1911b1289d6fSDoug Thompson {/*1*/ 0, 0x5d31, 0xa612, 0xfb23, 0x9584, 0xc8b5, 0x3396, 0x6ea7, 1912b1289d6fSDoug Thompson 0xeac8, 0xb7f9, 0x4cda, 0x11eb, 0x7f4c, 0x227d, 0xd95e, 0x846f }, 1913b1289d6fSDoug Thompson {/*2*/ 0, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007, 1914b1289d6fSDoug Thompson 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f }, 1915b1289d6fSDoug Thompson {/*3*/ 0, 0x2021, 0x3032, 0x1013, 0x4044, 0x6065, 0x7076, 0x5057, 1916b1289d6fSDoug Thompson 0x8088, 0xa0a9, 0xb0ba, 0x909b, 0xc0cc, 0xe0ed, 0xf0fe, 0xd0df }, 1917b1289d6fSDoug Thompson {/*4*/ 0, 0x5041, 0xa082, 0xf0c3, 0x9054, 0xc015, 0x30d6, 0x6097, 1918b1289d6fSDoug Thompson 0xe0a8, 0xb0e9, 0x402a, 0x106b, 0x70fc, 0x20bd, 0xd07e, 0x803f }, 1919b1289d6fSDoug Thompson {/*5*/ 0, 0xbe21, 0xd732, 0x6913, 0x2144, 0x9f65, 0xf676, 0x4857, 1920b1289d6fSDoug Thompson 0x3288, 0x8ca9, 0xe5ba, 0x5b9b, 0x13cc, 0xaded, 0xc4fe, 0x7adf }, 1921b1289d6fSDoug Thompson {/*6*/ 0, 0x4951, 0x8ea2, 0xc7f3, 0x5394, 0x1ac5, 0xdd36, 0x9467, 1922b1289d6fSDoug Thompson 0xa1e8, 0xe8b9, 0x2f4a, 0x661b, 0xf27c, 0xbb2d, 0x7cde, 0x358f }, 1923b1289d6fSDoug Thompson {/*7*/ 0, 0x74e1, 0x9872, 0xec93, 0xd6b4, 0xa255, 0x4ec6, 0x3a27, 1924b1289d6fSDoug Thompson 0x6bd8, 0x1f39, 0xf3aa, 0x874b, 0xbd6c, 0xc98d, 0x251e, 0x51ff }, 1925b1289d6fSDoug Thompson {/*8*/ 0, 0x15c1, 0x2a42, 0x3f83, 0xcef4, 0xdb35, 0xe4b6, 0xf177, 1926b1289d6fSDoug Thompson 0x4758, 0x5299, 0x6d1a, 0x78db, 0x89ac, 0x9c6d, 0xa3ee, 0xb62f }, 1927b1289d6fSDoug Thompson {/*9*/ 0, 0x3d01, 0x1602, 0x2b03, 0x8504, 0xb805, 0x9306, 0xae07, 1928b1289d6fSDoug Thompson 0xca08, 0xf709, 0xdc0a, 0xe10b, 0x4f0c, 0x720d, 0x590e, 0x640f }, 1929b1289d6fSDoug Thompson {/*a*/ 0, 0x9801, 0xec02, 0x7403, 0x6b04, 0xf305, 0x8706, 0x1f07, 1930b1289d6fSDoug Thompson 0xbd08, 0x2509, 0x510a, 0xc90b, 0xd60c, 0x4e0d, 0x3a0e, 0xa20f }, 1931b1289d6fSDoug Thompson {/*b*/ 0, 0xd131, 0x6212, 0xb323, 0x3884, 0xe9b5, 0x5a96, 0x8ba7, 1932b1289d6fSDoug Thompson 0x1cc8, 0xcdf9, 0x7eda, 0xafeb, 0x244c, 0xf57d, 0x465e, 0x976f }, 1933b1289d6fSDoug Thompson {/*c*/ 0, 0xe1d1, 0x7262, 0x93b3, 0xb834, 0x59e5, 0xca56, 0x2b87, 1934b1289d6fSDoug Thompson 0xdc18, 0x3dc9, 0xae7a, 0x4fab, 0x542c, 0x85fd, 0x164e, 0xf79f }, 1935b1289d6fSDoug Thompson {/*d*/ 0, 0x6051, 0xb0a2, 0xd0f3, 0x1094, 0x70c5, 0xa036, 0xc067, 1936b1289d6fSDoug Thompson 0x20e8, 0x40b9, 0x904a, 0x601b, 0x307c, 0x502d, 0x80de, 0xe08f }, 1937b1289d6fSDoug Thompson {/*e*/ 0, 0xa4c1, 0xf842, 0x5c83, 0xe6f4, 0x4235, 0x1eb6, 0xba77, 1938b1289d6fSDoug Thompson 0x7b58, 0xdf99, 0x831a, 0x27db, 0x9dac, 0x396d, 0x65ee, 0xc12f }, 1939b1289d6fSDoug Thompson {/*f*/ 0, 0x11c1, 0x2242, 0x3383, 0xc8f4, 0xd935, 0xeab6, 0xfb77, 1940b1289d6fSDoug Thompson 0x4c58, 0x5d99, 0x6e1a, 0x7fdb, 0x84ac, 0x956d, 0xa6ee, 0xb72f }, 19414d37607aSDoug Thompson 1942b1289d6fSDoug Thompson /* Channel 1 syndromes */ 1943b1289d6fSDoug Thompson {/*10*/ 1, 0x45d1, 0x8a62, 0xcfb3, 0x5e34, 0x1be5, 0xd456, 0x9187, 1944b1289d6fSDoug Thompson 0xa718, 0xe2c9, 0x2d7a, 0x68ab, 0xf92c, 0xbcfd, 0x734e, 0x369f }, 1945b1289d6fSDoug Thompson {/*11*/ 1, 0x63e1, 0xb172, 0xd293, 0x14b4, 0x7755, 0xa5c6, 0xc627, 1946b1289d6fSDoug Thompson 0x28d8, 0x4b39, 0x99aa, 0xfa4b, 0x3c6c, 0x5f8d, 0x8d1e, 0xeeff }, 1947b1289d6fSDoug Thompson {/*12*/ 1, 0xb741, 0xd982, 0x6ec3, 0x2254, 0x9515, 0xfbd6, 0x4c97, 1948b1289d6fSDoug Thompson 0x33a8, 0x84e9, 0xea2a, 0x5d6b, 0x11fc, 0xa6bd, 0xc87e, 0x7f3f }, 1949b1289d6fSDoug Thompson {/*13*/ 1, 0xdd41, 0x6682, 0xbbc3, 0x3554, 0xe815, 0x53d6, 0xce97, 1950b1289d6fSDoug Thompson 0x1aa8, 0xc7e9, 0x7c2a, 0xa1fb, 0x2ffc, 0xf2bd, 0x497e, 0x943f }, 1951b1289d6fSDoug Thompson {/*14*/ 1, 0x2bd1, 0x3d62, 0x16b3, 0x4f34, 0x64e5, 0x7256, 0x5987, 1952b1289d6fSDoug Thompson 0x8518, 0xaec9, 0xb87a, 0x93ab, 0xca2c, 0xe1fd, 0xf74e, 0xdc9f }, 1953b1289d6fSDoug Thompson {/*15*/ 1, 0x83c1, 0xc142, 0x4283, 0xa4f4, 0x2735, 0x65b6, 0xe677, 1954b1289d6fSDoug Thompson 0xf858, 0x7b99, 0x391a, 0xbadb, 0x5cac, 0xdf6d, 0x9dee, 0x1e2f }, 1955b1289d6fSDoug Thompson {/*16*/ 1, 0x8fd1, 0xc562, 0x4ab3, 0xa934, 0x26e5, 0x6c56, 0xe387, 1956b1289d6fSDoug Thompson 0xfe18, 0x71c9, 0x3b7a, 0xb4ab, 0x572c, 0xd8fd, 0x924e, 0x1d9f }, 1957b1289d6fSDoug Thompson {/*17*/ 1, 0x4791, 0x89e2, 0xce73, 0x5264, 0x15f5, 0xdb86, 0x9c17, 1958b1289d6fSDoug Thompson 0xa3b8, 0xe429, 0x2a5a, 0x6dcb, 0xf1dc, 0xb64d, 0x783e, 0x3faf }, 1959b1289d6fSDoug Thompson {/*18*/ 1, 0x5781, 0xa9c2, 0xfe43, 0x92a4, 0xc525, 0x3b66, 0x6ce7, 1960b1289d6fSDoug Thompson 0xe3f8, 0xb479, 0x4a3a, 0x1dbb, 0x715c, 0x26dd, 0xd89e, 0x8f1f }, 1961b1289d6fSDoug Thompson {/*19*/ 1, 0xbf41, 0xd582, 0x6ac3, 0x2954, 0x9615, 0xfcd6, 0x4397, 1962b1289d6fSDoug Thompson 0x3ea8, 0x81e9, 0xeb2a, 0x546b, 0x17fc, 0xa8bd, 0xc27e, 0x7d3f }, 1963b1289d6fSDoug Thompson {/*1a*/ 1, 0x9891, 0xe1e2, 0x7273, 0x6464, 0xf7f5, 0x8586, 0x1617, 1964b1289d6fSDoug Thompson 0xb8b8, 0x2b29, 0x595a, 0xcacb, 0xdcdc, 0x4f4d, 0x3d3e, 0xaeaf }, 1965b1289d6fSDoug Thompson {/*1b*/ 1, 0xcce1, 0x4472, 0x8893, 0xfdb4, 0x3f55, 0xb9c6, 0x7527, 1966b1289d6fSDoug Thompson 0x56d8, 0x9a39, 0x12aa, 0xde4b, 0xab6c, 0x678d, 0xef1e, 0x23ff }, 1967b1289d6fSDoug Thompson {/*1c*/ 1, 0xa761, 0xf9b2, 0x5ed3, 0xe214, 0x4575, 0x1ba6, 0xbcc7, 1968b1289d6fSDoug Thompson 0x7328, 0xd449, 0x8a9a, 0x2dfb, 0x913c, 0x365d, 0x688e, 0xcfef }, 1969b1289d6fSDoug Thompson {/*1d*/ 1, 0xff61, 0x55b2, 0xaad3, 0x7914, 0x8675, 0x2ca6, 0xd3c7, 1970b1289d6fSDoug Thompson 0x9e28, 0x6149, 0xcb9a, 0x34fb, 0xe73c, 0x185d, 0xb28e, 0x4def }, 1971b1289d6fSDoug Thompson {/*1e*/ 1, 0x5451, 0xa8a2, 0xfcf3, 0x9694, 0xc2c5, 0x3e36, 0x6a67, 1972b1289d6fSDoug Thompson 0xebe8, 0xbfb9, 0x434a, 0x171b, 0x7d7c, 0x292d, 0xd5de, 0x818f }, 1973b1289d6fSDoug Thompson {/*1f*/ 1, 0x6fc1, 0xb542, 0xda83, 0x19f4, 0x7635, 0xacb6, 0xc377, 1974b1289d6fSDoug Thompson 0x2e58, 0x4199, 0x9b1a, 0xf4db, 0x37ac, 0x586d, 0x82ee, 0xed2f }, 1975b1289d6fSDoug Thompson 1976b1289d6fSDoug Thompson /* ECC bits are also in the set of tokens and they too can go bad 1977b1289d6fSDoug Thompson * first 2 cover channel 0, while the second 2 cover channel 1 1978b1289d6fSDoug Thompson */ 1979b1289d6fSDoug Thompson {/*20*/ 0, 0xbe01, 0xd702, 0x6903, 0x2104, 0x9f05, 0xf606, 0x4807, 1980b1289d6fSDoug Thompson 0x3208, 0x8c09, 0xe50a, 0x5b0b, 0x130c, 0xad0d, 0xc40e, 0x7a0f }, 1981b1289d6fSDoug Thompson {/*21*/ 0, 0x4101, 0x8202, 0xc303, 0x5804, 0x1905, 0xda06, 0x9b07, 1982b1289d6fSDoug Thompson 0xac08, 0xed09, 0x2e0a, 0x6f0b, 0x640c, 0xb50d, 0x760e, 0x370f }, 1983b1289d6fSDoug Thompson {/*22*/ 1, 0xc441, 0x4882, 0x8cc3, 0xf654, 0x3215, 0xbed6, 0x7a97, 1984b1289d6fSDoug Thompson 0x5ba8, 0x9fe9, 0x132a, 0xd76b, 0xadfc, 0x69bd, 0xe57e, 0x213f }, 1985b1289d6fSDoug Thompson {/*23*/ 1, 0x7621, 0x9b32, 0xed13, 0xda44, 0xac65, 0x4176, 0x3757, 1986b1289d6fSDoug Thompson 0x6f88, 0x19a9, 0xf4ba, 0x829b, 0xb5cc, 0xc3ed, 0x2efe, 0x58df } 1987b1289d6fSDoug Thompson }; 1988b1289d6fSDoug Thompson 1989b1289d6fSDoug Thompson /* 1990b1289d6fSDoug Thompson * Given the syndrome argument, scan each of the channel tables for a syndrome 1991b1289d6fSDoug Thompson * match. Depending on which table it is found, return the channel number. 1992b1289d6fSDoug Thompson */ 1993b1289d6fSDoug Thompson static int get_channel_from_ecc_syndrome(unsigned short syndrome) 1994b1289d6fSDoug Thompson { 1995b1289d6fSDoug Thompson int row; 1996b1289d6fSDoug Thompson int column; 1997b1289d6fSDoug Thompson 1998b1289d6fSDoug Thompson /* Determine column to scan */ 1999b1289d6fSDoug Thompson column = syndrome & 0xF; 2000b1289d6fSDoug Thompson 2001b1289d6fSDoug Thompson /* Scan all rows, looking for syndrome, or end of table */ 2002b1289d6fSDoug Thompson for (row = 0; row < NUMBER_ECC_ROWS; row++) { 2003b1289d6fSDoug Thompson if (ecc_chipkill_syndromes[row][column] == syndrome) 2004b1289d6fSDoug Thompson return ecc_chipkill_syndromes[row][0]; 2005b1289d6fSDoug Thompson } 2006b1289d6fSDoug Thompson 2007b1289d6fSDoug Thompson debugf0("syndrome(%x) not found\n", syndrome); 2008b1289d6fSDoug Thompson return -1; 2009b1289d6fSDoug Thompson } 2010d27bf6faSDoug Thompson 2011d27bf6faSDoug Thompson /* 2012d27bf6faSDoug Thompson * Check for valid error in the NB Status High register. If so, proceed to read 2013d27bf6faSDoug Thompson * NB Status Low, NB Address Low and NB Address High registers and store data 2014d27bf6faSDoug Thompson * into error structure. 2015d27bf6faSDoug Thompson * 2016d27bf6faSDoug Thompson * Returns: 2017d27bf6faSDoug Thompson * - 1: if hardware regs contains valid error info 2018d27bf6faSDoug Thompson * - 0: if no valid error is indicated 2019d27bf6faSDoug Thompson */ 2020d27bf6faSDoug Thompson static int amd64_get_error_info_regs(struct mem_ctl_info *mci, 2021ef44cc4cSBorislav Petkov struct err_regs *regs) 2022d27bf6faSDoug Thompson { 2023d27bf6faSDoug Thompson struct amd64_pvt *pvt; 2024d27bf6faSDoug Thompson struct pci_dev *misc_f3_ctl; 2025d27bf6faSDoug Thompson 2026d27bf6faSDoug Thompson pvt = mci->pvt_info; 2027d27bf6faSDoug Thompson misc_f3_ctl = pvt->misc_f3_ctl; 2028d27bf6faSDoug Thompson 20296ba5dcdcSBorislav Petkov if (amd64_read_pci_cfg(misc_f3_ctl, K8_NBSH, ®s->nbsh)) 20306ba5dcdcSBorislav Petkov return 0; 2031d27bf6faSDoug Thompson 2032d27bf6faSDoug Thompson if (!(regs->nbsh & K8_NBSH_VALID_BIT)) 2033d27bf6faSDoug Thompson return 0; 2034d27bf6faSDoug Thompson 2035d27bf6faSDoug Thompson /* valid error, read remaining error information registers */ 20366ba5dcdcSBorislav Petkov if (amd64_read_pci_cfg(misc_f3_ctl, K8_NBSL, ®s->nbsl) || 20376ba5dcdcSBorislav Petkov amd64_read_pci_cfg(misc_f3_ctl, K8_NBEAL, ®s->nbeal) || 20386ba5dcdcSBorislav Petkov amd64_read_pci_cfg(misc_f3_ctl, K8_NBEAH, ®s->nbeah) || 20396ba5dcdcSBorislav Petkov amd64_read_pci_cfg(misc_f3_ctl, K8_NBCFG, ®s->nbcfg)) 20406ba5dcdcSBorislav Petkov return 0; 2041d27bf6faSDoug Thompson 2042d27bf6faSDoug Thompson return 1; 2043d27bf6faSDoug Thompson } 2044d27bf6faSDoug Thompson 2045d27bf6faSDoug Thompson /* 2046d27bf6faSDoug Thompson * This function is called to retrieve the error data from hardware and store it 2047d27bf6faSDoug Thompson * in the info structure. 2048d27bf6faSDoug Thompson * 2049d27bf6faSDoug Thompson * Returns: 2050d27bf6faSDoug Thompson * - 1: if a valid error is found 2051d27bf6faSDoug Thompson * - 0: if no error is found 2052d27bf6faSDoug Thompson */ 2053d27bf6faSDoug Thompson static int amd64_get_error_info(struct mem_ctl_info *mci, 2054ef44cc4cSBorislav Petkov struct err_regs *info) 2055d27bf6faSDoug Thompson { 2056d27bf6faSDoug Thompson struct amd64_pvt *pvt; 2057ef44cc4cSBorislav Petkov struct err_regs regs; 2058d27bf6faSDoug Thompson 2059d27bf6faSDoug Thompson pvt = mci->pvt_info; 2060d27bf6faSDoug Thompson 2061d27bf6faSDoug Thompson if (!amd64_get_error_info_regs(mci, info)) 2062d27bf6faSDoug Thompson return 0; 2063d27bf6faSDoug Thompson 2064d27bf6faSDoug Thompson /* 2065d27bf6faSDoug Thompson * Here's the problem with the K8's EDAC reporting: There are four 2066d27bf6faSDoug Thompson * registers which report pieces of error information. They are shared 2067d27bf6faSDoug Thompson * between CEs and UEs. Furthermore, contrary to what is stated in the 2068d27bf6faSDoug Thompson * BKDG, the overflow bit is never used! Every error always updates the 2069d27bf6faSDoug Thompson * reporting registers. 2070d27bf6faSDoug Thompson * 2071d27bf6faSDoug Thompson * Can you see the race condition? All four error reporting registers 2072d27bf6faSDoug Thompson * must be read before a new error updates them! There is no way to read 2073d27bf6faSDoug Thompson * all four registers atomically. The best than can be done is to detect 2074d27bf6faSDoug Thompson * that a race has occured and then report the error without any kind of 2075d27bf6faSDoug Thompson * precision. 2076d27bf6faSDoug Thompson * 2077d27bf6faSDoug Thompson * What is still positive is that errors are still reported and thus 2078d27bf6faSDoug Thompson * problems can still be detected - just not localized because the 2079d27bf6faSDoug Thompson * syndrome and address are spread out across registers. 2080d27bf6faSDoug Thompson * 2081d27bf6faSDoug Thompson * Grrrrr!!!!! Here's hoping that AMD fixes this in some future K8 rev. 2082d27bf6faSDoug Thompson * UEs and CEs should have separate register sets with proper overflow 2083d27bf6faSDoug Thompson * bits that are used! At very least the problem can be fixed by 2084d27bf6faSDoug Thompson * honoring the ErrValid bit in 'nbsh' and not updating registers - just 2085d27bf6faSDoug Thompson * set the overflow bit - unless the current error is CE and the new 2086d27bf6faSDoug Thompson * error is UE which would be the only situation for overwriting the 2087d27bf6faSDoug Thompson * current values. 2088d27bf6faSDoug Thompson */ 2089d27bf6faSDoug Thompson 2090d27bf6faSDoug Thompson regs = *info; 2091d27bf6faSDoug Thompson 2092d27bf6faSDoug Thompson /* Use info from the second read - most current */ 2093d27bf6faSDoug Thompson if (unlikely(!amd64_get_error_info_regs(mci, info))) 2094d27bf6faSDoug Thompson return 0; 2095d27bf6faSDoug Thompson 2096d27bf6faSDoug Thompson /* clear the error bits in hardware */ 2097d27bf6faSDoug Thompson pci_write_bits32(pvt->misc_f3_ctl, K8_NBSH, 0, K8_NBSH_VALID_BIT); 2098d27bf6faSDoug Thompson 2099d27bf6faSDoug Thompson /* Check for the possible race condition */ 2100d27bf6faSDoug Thompson if ((regs.nbsh != info->nbsh) || 2101d27bf6faSDoug Thompson (regs.nbsl != info->nbsl) || 2102d27bf6faSDoug Thompson (regs.nbeah != info->nbeah) || 2103d27bf6faSDoug Thompson (regs.nbeal != info->nbeal)) { 2104d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_WARNING, 2105d27bf6faSDoug Thompson "hardware STATUS read access race condition " 2106d27bf6faSDoug Thompson "detected!\n"); 2107d27bf6faSDoug Thompson return 0; 2108d27bf6faSDoug Thompson } 2109d27bf6faSDoug Thompson return 1; 2110d27bf6faSDoug Thompson } 2111d27bf6faSDoug Thompson 2112d27bf6faSDoug Thompson /* 2113d27bf6faSDoug Thompson * Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR 2114d27bf6faSDoug Thompson * ADDRESS and process. 2115d27bf6faSDoug Thompson */ 2116d27bf6faSDoug Thompson static void amd64_handle_ce(struct mem_ctl_info *mci, 2117ef44cc4cSBorislav Petkov struct err_regs *info) 2118d27bf6faSDoug Thompson { 2119d27bf6faSDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 2120d27bf6faSDoug Thompson u64 SystemAddress; 2121d27bf6faSDoug Thompson 2122d27bf6faSDoug Thompson /* Ensure that the Error Address is VALID */ 2123d27bf6faSDoug Thompson if ((info->nbsh & K8_NBSH_VALID_ERROR_ADDR) == 0) { 2124d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_ERR, 2125d27bf6faSDoug Thompson "HW has no ERROR_ADDRESS available\n"); 2126d27bf6faSDoug Thompson edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); 2127d27bf6faSDoug Thompson return; 2128d27bf6faSDoug Thompson } 2129d27bf6faSDoug Thompson 2130d27bf6faSDoug Thompson SystemAddress = extract_error_address(mci, info); 2131d27bf6faSDoug Thompson 2132d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_ERR, 2133d27bf6faSDoug Thompson "CE ERROR_ADDRESS= 0x%llx\n", SystemAddress); 2134d27bf6faSDoug Thompson 2135d27bf6faSDoug Thompson pvt->ops->map_sysaddr_to_csrow(mci, info, SystemAddress); 2136d27bf6faSDoug Thompson } 2137d27bf6faSDoug Thompson 2138d27bf6faSDoug Thompson /* Handle any Un-correctable Errors (UEs) */ 2139d27bf6faSDoug Thompson static void amd64_handle_ue(struct mem_ctl_info *mci, 2140ef44cc4cSBorislav Petkov struct err_regs *info) 2141d27bf6faSDoug Thompson { 2142d27bf6faSDoug Thompson int csrow; 2143d27bf6faSDoug Thompson u64 SystemAddress; 2144d27bf6faSDoug Thompson u32 page, offset; 2145d27bf6faSDoug Thompson struct mem_ctl_info *log_mci, *src_mci = NULL; 2146d27bf6faSDoug Thompson 2147d27bf6faSDoug Thompson log_mci = mci; 2148d27bf6faSDoug Thompson 2149d27bf6faSDoug Thompson if ((info->nbsh & K8_NBSH_VALID_ERROR_ADDR) == 0) { 2150d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_CRIT, 2151d27bf6faSDoug Thompson "HW has no ERROR_ADDRESS available\n"); 2152d27bf6faSDoug Thompson edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); 2153d27bf6faSDoug Thompson return; 2154d27bf6faSDoug Thompson } 2155d27bf6faSDoug Thompson 2156d27bf6faSDoug Thompson SystemAddress = extract_error_address(mci, info); 2157d27bf6faSDoug Thompson 2158d27bf6faSDoug Thompson /* 2159d27bf6faSDoug Thompson * Find out which node the error address belongs to. This may be 2160d27bf6faSDoug Thompson * different from the node that detected the error. 2161d27bf6faSDoug Thompson */ 2162d27bf6faSDoug Thompson src_mci = find_mc_by_sys_addr(mci, SystemAddress); 2163d27bf6faSDoug Thompson if (!src_mci) { 2164d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_CRIT, 2165d27bf6faSDoug Thompson "ERROR ADDRESS (0x%lx) value NOT mapped to a MC\n", 2166d27bf6faSDoug Thompson (unsigned long)SystemAddress); 2167d27bf6faSDoug Thompson edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); 2168d27bf6faSDoug Thompson return; 2169d27bf6faSDoug Thompson } 2170d27bf6faSDoug Thompson 2171d27bf6faSDoug Thompson log_mci = src_mci; 2172d27bf6faSDoug Thompson 2173d27bf6faSDoug Thompson csrow = sys_addr_to_csrow(log_mci, SystemAddress); 2174d27bf6faSDoug Thompson if (csrow < 0) { 2175d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_CRIT, 2176d27bf6faSDoug Thompson "ERROR_ADDRESS (0x%lx) value NOT mapped to 'csrow'\n", 2177d27bf6faSDoug Thompson (unsigned long)SystemAddress); 2178d27bf6faSDoug Thompson edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); 2179d27bf6faSDoug Thompson } else { 2180d27bf6faSDoug Thompson error_address_to_page_and_offset(SystemAddress, &page, &offset); 2181d27bf6faSDoug Thompson edac_mc_handle_ue(log_mci, page, offset, csrow, EDAC_MOD_STR); 2182d27bf6faSDoug Thompson } 2183d27bf6faSDoug Thompson } 2184d27bf6faSDoug Thompson 2185549d042dSBorislav Petkov static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci, 2186b69b29deSBorislav Petkov struct err_regs *info) 2187d27bf6faSDoug Thompson { 2188b70ef010SBorislav Petkov u32 ec = ERROR_CODE(info->nbsl); 2189b70ef010SBorislav Petkov u32 xec = EXT_ERROR_CODE(info->nbsl); 219017adea01SBorislav Petkov int ecc_type = (info->nbsh >> 13) & 0x3; 2191d27bf6faSDoug Thompson 2192b70ef010SBorislav Petkov /* Bail early out if this was an 'observed' error */ 2193b70ef010SBorislav Petkov if (PP(ec) == K8_NBSL_PP_OBS) 2194b70ef010SBorislav Petkov return; 2195d27bf6faSDoug Thompson 2196ecaf5606SBorislav Petkov /* Do only ECC errors */ 2197ecaf5606SBorislav Petkov if (xec && xec != F10_NBSL_EXT_ERR_ECC) 2198d27bf6faSDoug Thompson return; 2199d27bf6faSDoug Thompson 2200ecaf5606SBorislav Petkov if (ecc_type == 2) 2201d27bf6faSDoug Thompson amd64_handle_ce(mci, info); 2202ecaf5606SBorislav Petkov else if (ecc_type == 1) 2203d27bf6faSDoug Thompson amd64_handle_ue(mci, info); 2204d27bf6faSDoug Thompson 2205d27bf6faSDoug Thompson /* 2206d27bf6faSDoug Thompson * If main error is CE then overflow must be CE. If main error is UE 2207d27bf6faSDoug Thompson * then overflow is unknown. We'll call the overflow a CE - if 2208d27bf6faSDoug Thompson * panic_on_ue is set then we're already panic'ed and won't arrive 2209d27bf6faSDoug Thompson * here. Else, then apparently someone doesn't think that UE's are 2210d27bf6faSDoug Thompson * catastrophic. 2211d27bf6faSDoug Thompson */ 2212d27bf6faSDoug Thompson if (info->nbsh & K8_NBSH_OVERFLOW) 2213ecaf5606SBorislav Petkov edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR "Error Overflow"); 2214d27bf6faSDoug Thompson } 2215d27bf6faSDoug Thompson 2216b69b29deSBorislav Petkov void amd64_decode_bus_error(int node_id, struct err_regs *regs) 2217d27bf6faSDoug Thompson { 2218549d042dSBorislav Petkov struct mem_ctl_info *mci = mci_lookup[node_id]; 2219d27bf6faSDoug Thompson 2220b69b29deSBorislav Petkov __amd64_decode_bus_error(mci, regs); 2221d27bf6faSDoug Thompson 2222d27bf6faSDoug Thompson /* 2223d27bf6faSDoug Thompson * Check the UE bit of the NB status high register, if set generate some 2224d27bf6faSDoug Thompson * logs. If NOT a GART error, then process the event as a NO-INFO event. 2225d27bf6faSDoug Thompson * If it was a GART error, skip that process. 2226549d042dSBorislav Petkov * 2227549d042dSBorislav Petkov * FIXME: this should go somewhere else, if at all. 2228d27bf6faSDoug Thompson */ 22295110dbdeSBorislav Petkov if (regs->nbsh & K8_NBSH_UC_ERR && !report_gart_errors) 22305110dbdeSBorislav Petkov edac_mc_handle_ue_no_info(mci, "UE bit is set"); 2231549d042dSBorislav Petkov 2232d27bf6faSDoug Thompson } 2233d27bf6faSDoug Thompson 22340ec449eeSDoug Thompson /* 22350ec449eeSDoug Thompson * The main polling 'check' function, called FROM the edac core to perform the 22360ec449eeSDoug Thompson * error checking and if an error is encountered, error processing. 22370ec449eeSDoug Thompson */ 22380ec449eeSDoug Thompson static void amd64_check(struct mem_ctl_info *mci) 22390ec449eeSDoug Thompson { 2240ef44cc4cSBorislav Petkov struct err_regs regs; 22410ec449eeSDoug Thompson 2242549d042dSBorislav Petkov if (amd64_get_error_info(mci, ®s)) { 2243549d042dSBorislav Petkov struct amd64_pvt *pvt = mci->pvt_info; 2244549d042dSBorislav Petkov amd_decode_nb_mce(pvt->mc_node_id, ®s, 1); 2245549d042dSBorislav Petkov } 22460ec449eeSDoug Thompson } 22470ec449eeSDoug Thompson 22480ec449eeSDoug Thompson /* 22490ec449eeSDoug Thompson * Input: 22500ec449eeSDoug Thompson * 1) struct amd64_pvt which contains pvt->dram_f2_ctl pointer 22510ec449eeSDoug Thompson * 2) AMD Family index value 22520ec449eeSDoug Thompson * 22530ec449eeSDoug Thompson * Ouput: 22540ec449eeSDoug Thompson * Upon return of 0, the following filled in: 22550ec449eeSDoug Thompson * 22560ec449eeSDoug Thompson * struct pvt->addr_f1_ctl 22570ec449eeSDoug Thompson * struct pvt->misc_f3_ctl 22580ec449eeSDoug Thompson * 22590ec449eeSDoug Thompson * Filled in with related device funcitions of 'dram_f2_ctl' 22600ec449eeSDoug Thompson * These devices are "reserved" via the pci_get_device() 22610ec449eeSDoug Thompson * 22620ec449eeSDoug Thompson * Upon return of 1 (error status): 22630ec449eeSDoug Thompson * 22640ec449eeSDoug Thompson * Nothing reserved 22650ec449eeSDoug Thompson */ 22660ec449eeSDoug Thompson static int amd64_reserve_mc_sibling_devices(struct amd64_pvt *pvt, int mc_idx) 22670ec449eeSDoug Thompson { 22680ec449eeSDoug Thompson const struct amd64_family_type *amd64_dev = &amd64_family_types[mc_idx]; 22690ec449eeSDoug Thompson 22700ec449eeSDoug Thompson /* Reserve the ADDRESS MAP Device */ 22710ec449eeSDoug Thompson pvt->addr_f1_ctl = pci_get_related_function(pvt->dram_f2_ctl->vendor, 22720ec449eeSDoug Thompson amd64_dev->addr_f1_ctl, 22730ec449eeSDoug Thompson pvt->dram_f2_ctl); 22740ec449eeSDoug Thompson 22750ec449eeSDoug Thompson if (!pvt->addr_f1_ctl) { 22760ec449eeSDoug Thompson amd64_printk(KERN_ERR, "error address map device not found: " 22770ec449eeSDoug Thompson "vendor %x device 0x%x (broken BIOS?)\n", 22780ec449eeSDoug Thompson PCI_VENDOR_ID_AMD, amd64_dev->addr_f1_ctl); 22790ec449eeSDoug Thompson return 1; 22800ec449eeSDoug Thompson } 22810ec449eeSDoug Thompson 22820ec449eeSDoug Thompson /* Reserve the MISC Device */ 22830ec449eeSDoug Thompson pvt->misc_f3_ctl = pci_get_related_function(pvt->dram_f2_ctl->vendor, 22840ec449eeSDoug Thompson amd64_dev->misc_f3_ctl, 22850ec449eeSDoug Thompson pvt->dram_f2_ctl); 22860ec449eeSDoug Thompson 22870ec449eeSDoug Thompson if (!pvt->misc_f3_ctl) { 22880ec449eeSDoug Thompson pci_dev_put(pvt->addr_f1_ctl); 22890ec449eeSDoug Thompson pvt->addr_f1_ctl = NULL; 22900ec449eeSDoug Thompson 22910ec449eeSDoug Thompson amd64_printk(KERN_ERR, "error miscellaneous device not found: " 22920ec449eeSDoug Thompson "vendor %x device 0x%x (broken BIOS?)\n", 22930ec449eeSDoug Thompson PCI_VENDOR_ID_AMD, amd64_dev->misc_f3_ctl); 22940ec449eeSDoug Thompson return 1; 22950ec449eeSDoug Thompson } 22960ec449eeSDoug Thompson 22970ec449eeSDoug Thompson debugf1(" Addr Map device PCI Bus ID:\t%s\n", 22980ec449eeSDoug Thompson pci_name(pvt->addr_f1_ctl)); 22990ec449eeSDoug Thompson debugf1(" DRAM MEM-CTL PCI Bus ID:\t%s\n", 23000ec449eeSDoug Thompson pci_name(pvt->dram_f2_ctl)); 23010ec449eeSDoug Thompson debugf1(" Misc device PCI Bus ID:\t%s\n", 23020ec449eeSDoug Thompson pci_name(pvt->misc_f3_ctl)); 23030ec449eeSDoug Thompson 23040ec449eeSDoug Thompson return 0; 23050ec449eeSDoug Thompson } 23060ec449eeSDoug Thompson 23070ec449eeSDoug Thompson static void amd64_free_mc_sibling_devices(struct amd64_pvt *pvt) 23080ec449eeSDoug Thompson { 23090ec449eeSDoug Thompson pci_dev_put(pvt->addr_f1_ctl); 23100ec449eeSDoug Thompson pci_dev_put(pvt->misc_f3_ctl); 23110ec449eeSDoug Thompson } 23120ec449eeSDoug Thompson 23130ec449eeSDoug Thompson /* 23140ec449eeSDoug Thompson * Retrieve the hardware registers of the memory controller (this includes the 23150ec449eeSDoug Thompson * 'Address Map' and 'Misc' device regs) 23160ec449eeSDoug Thompson */ 23170ec449eeSDoug Thompson static void amd64_read_mc_registers(struct amd64_pvt *pvt) 23180ec449eeSDoug Thompson { 23190ec449eeSDoug Thompson u64 msr_val; 23206ba5dcdcSBorislav Petkov int dram; 23210ec449eeSDoug Thompson 23220ec449eeSDoug Thompson /* 23230ec449eeSDoug Thompson * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since 23240ec449eeSDoug Thompson * those are Read-As-Zero 23250ec449eeSDoug Thompson */ 2326e97f8bb8SBorislav Petkov rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem); 2327e97f8bb8SBorislav Petkov debugf0(" TOP_MEM: 0x%016llx\n", pvt->top_mem); 23280ec449eeSDoug Thompson 23290ec449eeSDoug Thompson /* check first whether TOP_MEM2 is enabled */ 23300ec449eeSDoug Thompson rdmsrl(MSR_K8_SYSCFG, msr_val); 23310ec449eeSDoug Thompson if (msr_val & (1U << 21)) { 2332e97f8bb8SBorislav Petkov rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2); 2333e97f8bb8SBorislav Petkov debugf0(" TOP_MEM2: 0x%016llx\n", pvt->top_mem2); 23340ec449eeSDoug Thompson } else 23350ec449eeSDoug Thompson debugf0(" TOP_MEM2 disabled.\n"); 23360ec449eeSDoug Thompson 23370ec449eeSDoug Thompson amd64_cpu_display_info(pvt); 23380ec449eeSDoug Thompson 23396ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCAP, &pvt->nbcap); 23400ec449eeSDoug Thompson 23410ec449eeSDoug Thompson if (pvt->ops->read_dram_ctl_register) 23420ec449eeSDoug Thompson pvt->ops->read_dram_ctl_register(pvt); 23430ec449eeSDoug Thompson 23440ec449eeSDoug Thompson for (dram = 0; dram < DRAM_REG_COUNT; dram++) { 23450ec449eeSDoug Thompson /* 23460ec449eeSDoug Thompson * Call CPU specific READ function to get the DRAM Base and 23470ec449eeSDoug Thompson * Limit values from the DCT. 23480ec449eeSDoug Thompson */ 23490ec449eeSDoug Thompson pvt->ops->read_dram_base_limit(pvt, dram); 23500ec449eeSDoug Thompson 23510ec449eeSDoug Thompson /* 23520ec449eeSDoug Thompson * Only print out debug info on rows with both R and W Enabled. 23530ec449eeSDoug Thompson * Normal processing, compiler should optimize this whole 'if' 23540ec449eeSDoug Thompson * debug output block away. 23550ec449eeSDoug Thompson */ 23560ec449eeSDoug Thompson if (pvt->dram_rw_en[dram] != 0) { 2357e97f8bb8SBorislav Petkov debugf1(" DRAM-BASE[%d]: 0x%016llx " 2358e97f8bb8SBorislav Petkov "DRAM-LIMIT: 0x%016llx\n", 23590ec449eeSDoug Thompson dram, 2360e97f8bb8SBorislav Petkov pvt->dram_base[dram], 2361e97f8bb8SBorislav Petkov pvt->dram_limit[dram]); 2362e97f8bb8SBorislav Petkov 23630ec449eeSDoug Thompson debugf1(" IntlvEn=%s %s %s " 23640ec449eeSDoug Thompson "IntlvSel=%d DstNode=%d\n", 23650ec449eeSDoug Thompson pvt->dram_IntlvEn[dram] ? 23660ec449eeSDoug Thompson "Enabled" : "Disabled", 23670ec449eeSDoug Thompson (pvt->dram_rw_en[dram] & 0x2) ? "W" : "!W", 23680ec449eeSDoug Thompson (pvt->dram_rw_en[dram] & 0x1) ? "R" : "!R", 23690ec449eeSDoug Thompson pvt->dram_IntlvSel[dram], 23700ec449eeSDoug Thompson pvt->dram_DstNode[dram]); 23710ec449eeSDoug Thompson } 23720ec449eeSDoug Thompson } 23730ec449eeSDoug Thompson 23740ec449eeSDoug Thompson amd64_read_dct_base_mask(pvt); 23750ec449eeSDoug Thompson 23766ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->addr_f1_ctl, K8_DHAR, &pvt->dhar); 23770ec449eeSDoug Thompson amd64_read_dbam_reg(pvt); 23780ec449eeSDoug Thompson 23796ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->misc_f3_ctl, 23800ec449eeSDoug Thompson F10_ONLINE_SPARE, &pvt->online_spare); 23810ec449eeSDoug Thompson 23826ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0); 23836ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCHR_0, &pvt->dchr0); 23840ec449eeSDoug Thompson 23850ec449eeSDoug Thompson if (!dct_ganging_enabled(pvt)) { 23866ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCLR_1, &pvt->dclr1); 23876ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->dram_f2_ctl, F10_DCHR_1, &pvt->dchr1); 23880ec449eeSDoug Thompson } 23890ec449eeSDoug Thompson amd64_dump_misc_regs(pvt); 23900ec449eeSDoug Thompson } 23910ec449eeSDoug Thompson 23920ec449eeSDoug Thompson /* 23930ec449eeSDoug Thompson * NOTE: CPU Revision Dependent code 23940ec449eeSDoug Thompson * 23950ec449eeSDoug Thompson * Input: 23969d858bb1SBorislav Petkov * @csrow_nr ChipSelect Row Number (0..pvt->cs_count-1) 23970ec449eeSDoug Thompson * k8 private pointer to --> 23980ec449eeSDoug Thompson * DRAM Bank Address mapping register 23990ec449eeSDoug Thompson * node_id 24000ec449eeSDoug Thompson * DCL register where dual_channel_active is 24010ec449eeSDoug Thompson * 24020ec449eeSDoug Thompson * The DBAM register consists of 4 sets of 4 bits each definitions: 24030ec449eeSDoug Thompson * 24040ec449eeSDoug Thompson * Bits: CSROWs 24050ec449eeSDoug Thompson * 0-3 CSROWs 0 and 1 24060ec449eeSDoug Thompson * 4-7 CSROWs 2 and 3 24070ec449eeSDoug Thompson * 8-11 CSROWs 4 and 5 24080ec449eeSDoug Thompson * 12-15 CSROWs 6 and 7 24090ec449eeSDoug Thompson * 24100ec449eeSDoug Thompson * Values range from: 0 to 15 24110ec449eeSDoug Thompson * The meaning of the values depends on CPU revision and dual-channel state, 24120ec449eeSDoug Thompson * see relevant BKDG more info. 24130ec449eeSDoug Thompson * 24140ec449eeSDoug Thompson * The memory controller provides for total of only 8 CSROWs in its current 24150ec449eeSDoug Thompson * architecture. Each "pair" of CSROWs normally represents just one DIMM in 24160ec449eeSDoug Thompson * single channel or two (2) DIMMs in dual channel mode. 24170ec449eeSDoug Thompson * 24180ec449eeSDoug Thompson * The following code logic collapses the various tables for CSROW based on CPU 24190ec449eeSDoug Thompson * revision. 24200ec449eeSDoug Thompson * 24210ec449eeSDoug Thompson * Returns: 24220ec449eeSDoug Thompson * The number of PAGE_SIZE pages on the specified CSROW number it 24230ec449eeSDoug Thompson * encompasses 24240ec449eeSDoug Thompson * 24250ec449eeSDoug Thompson */ 24260ec449eeSDoug Thompson static u32 amd64_csrow_nr_pages(int csrow_nr, struct amd64_pvt *pvt) 24270ec449eeSDoug Thompson { 24280ec449eeSDoug Thompson u32 dram_map, nr_pages; 24290ec449eeSDoug Thompson 24300ec449eeSDoug Thompson /* 24310ec449eeSDoug Thompson * The math on this doesn't look right on the surface because x/2*4 can 24320ec449eeSDoug Thompson * be simplified to x*2 but this expression makes use of the fact that 24330ec449eeSDoug Thompson * it is integral math where 1/2=0. This intermediate value becomes the 24340ec449eeSDoug Thompson * number of bits to shift the DBAM register to extract the proper CSROW 24350ec449eeSDoug Thompson * field. 24360ec449eeSDoug Thompson */ 24370ec449eeSDoug Thompson dram_map = (pvt->dbam0 >> ((csrow_nr / 2) * 4)) & 0xF; 24380ec449eeSDoug Thompson 24390ec449eeSDoug Thompson nr_pages = pvt->ops->dbam_map_to_pages(pvt, dram_map); 24400ec449eeSDoug Thompson 24410ec449eeSDoug Thompson /* 24420ec449eeSDoug Thompson * If dual channel then double the memory size of single channel. 24430ec449eeSDoug Thompson * Channel count is 1 or 2 24440ec449eeSDoug Thompson */ 24450ec449eeSDoug Thompson nr_pages <<= (pvt->channel_count - 1); 24460ec449eeSDoug Thompson 24470ec449eeSDoug Thompson debugf0(" (csrow=%d) DBAM map index= %d\n", csrow_nr, dram_map); 24480ec449eeSDoug Thompson debugf0(" nr_pages= %u channel-count = %d\n", 24490ec449eeSDoug Thompson nr_pages, pvt->channel_count); 24500ec449eeSDoug Thompson 24510ec449eeSDoug Thompson return nr_pages; 24520ec449eeSDoug Thompson } 24530ec449eeSDoug Thompson 24540ec449eeSDoug Thompson /* 24550ec449eeSDoug Thompson * Initialize the array of csrow attribute instances, based on the values 24560ec449eeSDoug Thompson * from pci config hardware registers. 24570ec449eeSDoug Thompson */ 24580ec449eeSDoug Thompson static int amd64_init_csrows(struct mem_ctl_info *mci) 24590ec449eeSDoug Thompson { 24600ec449eeSDoug Thompson struct csrow_info *csrow; 24610ec449eeSDoug Thompson struct amd64_pvt *pvt; 24620ec449eeSDoug Thompson u64 input_addr_min, input_addr_max, sys_addr; 24636ba5dcdcSBorislav Petkov int i, empty = 1; 24640ec449eeSDoug Thompson 24650ec449eeSDoug Thompson pvt = mci->pvt_info; 24660ec449eeSDoug Thompson 24676ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &pvt->nbcfg); 24680ec449eeSDoug Thompson 24690ec449eeSDoug Thompson debugf0("NBCFG= 0x%x CHIPKILL= %s DRAM ECC= %s\n", pvt->nbcfg, 24700ec449eeSDoug Thompson (pvt->nbcfg & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled", 24710ec449eeSDoug Thompson (pvt->nbcfg & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled" 24720ec449eeSDoug Thompson ); 24730ec449eeSDoug Thompson 24749d858bb1SBorislav Petkov for (i = 0; i < pvt->cs_count; i++) { 24750ec449eeSDoug Thompson csrow = &mci->csrows[i]; 24760ec449eeSDoug Thompson 24770ec449eeSDoug Thompson if ((pvt->dcsb0[i] & K8_DCSB_CS_ENABLE) == 0) { 24780ec449eeSDoug Thompson debugf1("----CSROW %d EMPTY for node %d\n", i, 24790ec449eeSDoug Thompson pvt->mc_node_id); 24800ec449eeSDoug Thompson continue; 24810ec449eeSDoug Thompson } 24820ec449eeSDoug Thompson 24830ec449eeSDoug Thompson debugf1("----CSROW %d VALID for MC node %d\n", 24840ec449eeSDoug Thompson i, pvt->mc_node_id); 24850ec449eeSDoug Thompson 24860ec449eeSDoug Thompson empty = 0; 24870ec449eeSDoug Thompson csrow->nr_pages = amd64_csrow_nr_pages(i, pvt); 24880ec449eeSDoug Thompson find_csrow_limits(mci, i, &input_addr_min, &input_addr_max); 24890ec449eeSDoug Thompson sys_addr = input_addr_to_sys_addr(mci, input_addr_min); 24900ec449eeSDoug Thompson csrow->first_page = (u32) (sys_addr >> PAGE_SHIFT); 24910ec449eeSDoug Thompson sys_addr = input_addr_to_sys_addr(mci, input_addr_max); 24920ec449eeSDoug Thompson csrow->last_page = (u32) (sys_addr >> PAGE_SHIFT); 24930ec449eeSDoug Thompson csrow->page_mask = ~mask_from_dct_mask(pvt, i); 24940ec449eeSDoug Thompson /* 8 bytes of resolution */ 24950ec449eeSDoug Thompson 24960ec449eeSDoug Thompson csrow->mtype = amd64_determine_memory_type(pvt); 24970ec449eeSDoug Thompson 24980ec449eeSDoug Thompson debugf1(" for MC node %d csrow %d:\n", pvt->mc_node_id, i); 24990ec449eeSDoug Thompson debugf1(" input_addr_min: 0x%lx input_addr_max: 0x%lx\n", 25000ec449eeSDoug Thompson (unsigned long)input_addr_min, 25010ec449eeSDoug Thompson (unsigned long)input_addr_max); 25020ec449eeSDoug Thompson debugf1(" sys_addr: 0x%lx page_mask: 0x%lx\n", 25030ec449eeSDoug Thompson (unsigned long)sys_addr, csrow->page_mask); 25040ec449eeSDoug Thompson debugf1(" nr_pages: %u first_page: 0x%lx " 25050ec449eeSDoug Thompson "last_page: 0x%lx\n", 25060ec449eeSDoug Thompson (unsigned)csrow->nr_pages, 25070ec449eeSDoug Thompson csrow->first_page, csrow->last_page); 25080ec449eeSDoug Thompson 25090ec449eeSDoug Thompson /* 25100ec449eeSDoug Thompson * determine whether CHIPKILL or JUST ECC or NO ECC is operating 25110ec449eeSDoug Thompson */ 25120ec449eeSDoug Thompson if (pvt->nbcfg & K8_NBCFG_ECC_ENABLE) 25130ec449eeSDoug Thompson csrow->edac_mode = 25140ec449eeSDoug Thompson (pvt->nbcfg & K8_NBCFG_CHIPKILL) ? 25150ec449eeSDoug Thompson EDAC_S4ECD4ED : EDAC_SECDED; 25160ec449eeSDoug Thompson else 25170ec449eeSDoug Thompson csrow->edac_mode = EDAC_NONE; 25180ec449eeSDoug Thompson } 25190ec449eeSDoug Thompson 25200ec449eeSDoug Thompson return empty; 25210ec449eeSDoug Thompson } 2522d27bf6faSDoug Thompson 252306724535SBorislav Petkov /* get all cores on this DCT */ 2524ba578cb3SRusty Russell static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, int nid) 2525f9431992SDoug Thompson { 252606724535SBorislav Petkov int cpu; 2527f9431992SDoug Thompson 252806724535SBorislav Petkov for_each_online_cpu(cpu) 252906724535SBorislav Petkov if (amd_get_nb_id(cpu) == nid) 253006724535SBorislav Petkov cpumask_set_cpu(cpu, mask); 2531f9431992SDoug Thompson } 2532f9431992SDoug Thompson 2533f9431992SDoug Thompson /* check MCG_CTL on all the cpus on this node */ 253406724535SBorislav Petkov static bool amd64_nb_mce_bank_enabled_on_node(int nid) 2535f9431992SDoug Thompson { 2536ba578cb3SRusty Russell cpumask_var_t mask; 253706724535SBorislav Petkov struct msr *msrs; 253806724535SBorislav Petkov int cpu, nbe, idx = 0; 253906724535SBorislav Petkov bool ret = false; 2540f9431992SDoug Thompson 2541ba578cb3SRusty Russell if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) { 2542ba578cb3SRusty Russell amd64_printk(KERN_WARNING, "%s: error allocating mask\n", 254306724535SBorislav Petkov __func__); 254406724535SBorislav Petkov return false; 254506724535SBorislav Petkov } 254606724535SBorislav Petkov 2547ba578cb3SRusty Russell get_cpus_on_this_dct_cpumask(mask, nid); 254806724535SBorislav Petkov 2549ba578cb3SRusty Russell msrs = kzalloc(sizeof(struct msr) * cpumask_weight(mask), GFP_KERNEL); 2550ba578cb3SRusty Russell if (!msrs) { 2551ba578cb3SRusty Russell amd64_printk(KERN_WARNING, "%s: error allocating msrs\n", 2552ba578cb3SRusty Russell __func__); 2553ba578cb3SRusty Russell free_cpumask_var(mask); 2554ba578cb3SRusty Russell return false; 2555ba578cb3SRusty Russell } 2556ba578cb3SRusty Russell 2557ba578cb3SRusty Russell rdmsr_on_cpus(mask, MSR_IA32_MCG_CTL, msrs); 2558ba578cb3SRusty Russell 2559ba578cb3SRusty Russell for_each_cpu(cpu, mask) { 256006724535SBorislav Petkov nbe = msrs[idx].l & K8_MSR_MCGCTL_NBE; 256106724535SBorislav Petkov 256206724535SBorislav Petkov debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n", 256306724535SBorislav Petkov cpu, msrs[idx].q, 256406724535SBorislav Petkov (nbe ? "enabled" : "disabled")); 256506724535SBorislav Petkov 256606724535SBorislav Petkov if (!nbe) 256706724535SBorislav Petkov goto out; 256806724535SBorislav Petkov 256906724535SBorislav Petkov idx++; 257006724535SBorislav Petkov } 257106724535SBorislav Petkov ret = true; 257206724535SBorislav Petkov 257306724535SBorislav Petkov out: 257406724535SBorislav Petkov kfree(msrs); 2575ba578cb3SRusty Russell free_cpumask_var(mask); 2576f9431992SDoug Thompson return ret; 2577f9431992SDoug Thompson } 2578f9431992SDoug Thompson 2579f6d6ae96SBorislav Petkov static int amd64_toggle_ecc_err_reporting(struct amd64_pvt *pvt, bool on) 2580f6d6ae96SBorislav Petkov { 2581f6d6ae96SBorislav Petkov cpumask_var_t cmask; 2582f6d6ae96SBorislav Petkov struct msr *msrs = NULL; 2583f6d6ae96SBorislav Petkov int cpu, idx = 0; 2584f6d6ae96SBorislav Petkov 2585f6d6ae96SBorislav Petkov if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) { 2586f6d6ae96SBorislav Petkov amd64_printk(KERN_WARNING, "%s: error allocating mask\n", 2587f6d6ae96SBorislav Petkov __func__); 2588f6d6ae96SBorislav Petkov return false; 2589f6d6ae96SBorislav Petkov } 2590f6d6ae96SBorislav Petkov 2591f6d6ae96SBorislav Petkov get_cpus_on_this_dct_cpumask(cmask, pvt->mc_node_id); 2592f6d6ae96SBorislav Petkov 2593f6d6ae96SBorislav Petkov msrs = kzalloc(sizeof(struct msr) * cpumask_weight(cmask), GFP_KERNEL); 2594f6d6ae96SBorislav Petkov if (!msrs) { 2595f6d6ae96SBorislav Petkov amd64_printk(KERN_WARNING, "%s: error allocating msrs\n", 2596f6d6ae96SBorislav Petkov __func__); 2597f6d6ae96SBorislav Petkov return -ENOMEM; 2598f6d6ae96SBorislav Petkov } 2599f6d6ae96SBorislav Petkov 2600f6d6ae96SBorislav Petkov rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs); 2601f6d6ae96SBorislav Petkov 2602f6d6ae96SBorislav Petkov for_each_cpu(cpu, cmask) { 2603f6d6ae96SBorislav Petkov 2604f6d6ae96SBorislav Petkov if (on) { 2605f6d6ae96SBorislav Petkov if (msrs[idx].l & K8_MSR_MCGCTL_NBE) 2606f6d6ae96SBorislav Petkov pvt->flags.ecc_report = 1; 2607f6d6ae96SBorislav Petkov 2608f6d6ae96SBorislav Petkov msrs[idx].l |= K8_MSR_MCGCTL_NBE; 2609f6d6ae96SBorislav Petkov } else { 2610f6d6ae96SBorislav Petkov /* 2611f6d6ae96SBorislav Petkov * Turn off ECC reporting only when it was off before 2612f6d6ae96SBorislav Petkov */ 2613f6d6ae96SBorislav Petkov if (!pvt->flags.ecc_report) 2614f6d6ae96SBorislav Petkov msrs[idx].l &= ~K8_MSR_MCGCTL_NBE; 2615f6d6ae96SBorislav Petkov } 2616f6d6ae96SBorislav Petkov idx++; 2617f6d6ae96SBorislav Petkov } 2618f6d6ae96SBorislav Petkov wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs); 2619f6d6ae96SBorislav Petkov 2620f6d6ae96SBorislav Petkov kfree(msrs); 2621f6d6ae96SBorislav Petkov free_cpumask_var(cmask); 2622f6d6ae96SBorislav Petkov 2623f6d6ae96SBorislav Petkov return 0; 2624f6d6ae96SBorislav Petkov } 2625f6d6ae96SBorislav Petkov 2626f6d6ae96SBorislav Petkov /* 2627f6d6ae96SBorislav Petkov * Only if 'ecc_enable_override' is set AND BIOS had ECC disabled, do "we" 2628f6d6ae96SBorislav Petkov * enable it. 2629f6d6ae96SBorislav Petkov */ 2630f6d6ae96SBorislav Petkov static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci) 2631f6d6ae96SBorislav Petkov { 2632f6d6ae96SBorislav Petkov struct amd64_pvt *pvt = mci->pvt_info; 2633f6d6ae96SBorislav Petkov u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn; 2634f6d6ae96SBorislav Petkov 2635f6d6ae96SBorislav Petkov if (!ecc_enable_override) 2636f6d6ae96SBorislav Petkov return; 2637f6d6ae96SBorislav Petkov 2638f6d6ae96SBorislav Petkov amd64_printk(KERN_WARNING, 2639f6d6ae96SBorislav Petkov "'ecc_enable_override' parameter is active, " 2640f6d6ae96SBorislav Petkov "Enabling AMD ECC hardware now: CAUTION\n"); 2641f6d6ae96SBorislav Petkov 26426ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCTL, &value); 2643f6d6ae96SBorislav Petkov 2644f6d6ae96SBorislav Petkov /* turn on UECCn and CECCEn bits */ 2645f6d6ae96SBorislav Petkov pvt->old_nbctl = value & mask; 2646f6d6ae96SBorislav Petkov pvt->nbctl_mcgctl_saved = 1; 2647f6d6ae96SBorislav Petkov 2648f6d6ae96SBorislav Petkov value |= mask; 2649f6d6ae96SBorislav Petkov pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value); 2650f6d6ae96SBorislav Petkov 2651f6d6ae96SBorislav Petkov if (amd64_toggle_ecc_err_reporting(pvt, ON)) 2652f6d6ae96SBorislav Petkov amd64_printk(KERN_WARNING, "Error enabling ECC reporting over " 2653f6d6ae96SBorislav Petkov "MCGCTL!\n"); 2654f6d6ae96SBorislav Petkov 26556ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &value); 2656f6d6ae96SBorislav Petkov 2657f6d6ae96SBorislav Petkov debugf0("NBCFG(1)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value, 2658f6d6ae96SBorislav Petkov (value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled", 2659f6d6ae96SBorislav Petkov (value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled"); 2660f6d6ae96SBorislav Petkov 2661f6d6ae96SBorislav Petkov if (!(value & K8_NBCFG_ECC_ENABLE)) { 2662f6d6ae96SBorislav Petkov amd64_printk(KERN_WARNING, 2663f6d6ae96SBorislav Petkov "This node reports that DRAM ECC is " 2664f6d6ae96SBorislav Petkov "currently Disabled; ENABLING now\n"); 2665f6d6ae96SBorislav Petkov 2666f6d6ae96SBorislav Petkov /* Attempt to turn on DRAM ECC Enable */ 2667f6d6ae96SBorislav Petkov value |= K8_NBCFG_ECC_ENABLE; 2668f6d6ae96SBorislav Petkov pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCFG, value); 2669f6d6ae96SBorislav Petkov 26706ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &value); 2671f6d6ae96SBorislav Petkov 2672f6d6ae96SBorislav Petkov if (!(value & K8_NBCFG_ECC_ENABLE)) { 2673f6d6ae96SBorislav Petkov amd64_printk(KERN_WARNING, 2674f6d6ae96SBorislav Petkov "Hardware rejects Enabling DRAM ECC checking\n" 2675f6d6ae96SBorislav Petkov "Check memory DIMM configuration\n"); 2676f6d6ae96SBorislav Petkov } else { 2677f6d6ae96SBorislav Petkov amd64_printk(KERN_DEBUG, 2678f6d6ae96SBorislav Petkov "Hardware accepted DRAM ECC Enable\n"); 2679f6d6ae96SBorislav Petkov } 2680f6d6ae96SBorislav Petkov } 2681f6d6ae96SBorislav Petkov debugf0("NBCFG(2)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value, 2682f6d6ae96SBorislav Petkov (value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled", 2683f6d6ae96SBorislav Petkov (value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled"); 2684f6d6ae96SBorislav Petkov 2685f6d6ae96SBorislav Petkov pvt->ctl_error_info.nbcfg = value; 2686f6d6ae96SBorislav Petkov } 2687f6d6ae96SBorislav Petkov 2688f6d6ae96SBorislav Petkov static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt) 2689f6d6ae96SBorislav Petkov { 2690f6d6ae96SBorislav Petkov u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn; 2691f6d6ae96SBorislav Petkov 2692f6d6ae96SBorislav Petkov if (!pvt->nbctl_mcgctl_saved) 2693f6d6ae96SBorislav Petkov return; 2694f6d6ae96SBorislav Petkov 26956ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCTL, &value); 2696f6d6ae96SBorislav Petkov value &= ~mask; 2697f6d6ae96SBorislav Petkov value |= pvt->old_nbctl; 2698f6d6ae96SBorislav Petkov 2699f6d6ae96SBorislav Petkov /* restore the NB Enable MCGCTL bit */ 2700f6d6ae96SBorislav Petkov pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value); 2701f6d6ae96SBorislav Petkov 2702f6d6ae96SBorislav Petkov if (amd64_toggle_ecc_err_reporting(pvt, OFF)) 2703f6d6ae96SBorislav Petkov amd64_printk(KERN_WARNING, "Error restoring ECC reporting over " 2704f6d6ae96SBorislav Petkov "MCGCTL!\n"); 2705f6d6ae96SBorislav Petkov } 2706f6d6ae96SBorislav Petkov 2707f9431992SDoug Thompson /* 2708f9431992SDoug Thompson * EDAC requires that the BIOS have ECC enabled before taking over the 2709f9431992SDoug Thompson * processing of ECC errors. This is because the BIOS can properly initialize 2710f9431992SDoug Thompson * the memory system completely. A command line option allows to force-enable 2711f9431992SDoug Thompson * hardware ECC later in amd64_enable_ecc_error_reporting(). 2712f9431992SDoug Thompson */ 2713be3468e8SBorislav Petkov static const char *ecc_warning = 2714be3468e8SBorislav Petkov "WARNING: ECC is disabled by BIOS. Module will NOT be loaded.\n" 2715be3468e8SBorislav Petkov " Either Enable ECC in the BIOS, or set 'ecc_enable_override'.\n" 2716be3468e8SBorislav Petkov " Also, use of the override can cause unknown side effects.\n"; 2717be3468e8SBorislav Petkov 2718f9431992SDoug Thompson static int amd64_check_ecc_enabled(struct amd64_pvt *pvt) 2719f9431992SDoug Thompson { 2720f9431992SDoug Thompson u32 value; 272106724535SBorislav Petkov u8 ecc_enabled = 0; 272206724535SBorislav Petkov bool nb_mce_en = false; 2723f9431992SDoug Thompson 27246ba5dcdcSBorislav Petkov amd64_read_pci_cfg(pvt->misc_f3_ctl, K8_NBCFG, &value); 2725f9431992SDoug Thompson 2726f9431992SDoug Thompson ecc_enabled = !!(value & K8_NBCFG_ECC_ENABLE); 2727be3468e8SBorislav Petkov if (!ecc_enabled) 2728be3468e8SBorislav Petkov amd64_printk(KERN_WARNING, "This node reports that Memory ECC " 2729be3468e8SBorislav Petkov "is currently disabled, set F3x%x[22] (%s).\n", 2730f9431992SDoug Thompson K8_NBCFG, pci_name(pvt->misc_f3_ctl)); 2731be3468e8SBorislav Petkov else 2732be3468e8SBorislav Petkov amd64_printk(KERN_INFO, "ECC is enabled by BIOS.\n"); 2733be3468e8SBorislav Petkov 273406724535SBorislav Petkov nb_mce_en = amd64_nb_mce_bank_enabled_on_node(pvt->mc_node_id); 273506724535SBorislav Petkov if (!nb_mce_en) 2736be3468e8SBorislav Petkov amd64_printk(KERN_WARNING, "NB MCE bank disabled, set MSR " 2737be3468e8SBorislav Petkov "0x%08x[4] on node %d to enable.\n", 2738be3468e8SBorislav Petkov MSR_IA32_MCG_CTL, pvt->mc_node_id); 2739be3468e8SBorislav Petkov 274006724535SBorislav Petkov if (!ecc_enabled || !nb_mce_en) { 2741f9431992SDoug Thompson if (!ecc_enable_override) { 2742be3468e8SBorislav Petkov amd64_printk(KERN_WARNING, "%s", ecc_warning); 2743be3468e8SBorislav Petkov return -ENODEV; 2744be3468e8SBorislav Petkov } 274530c875cbSBorislav Petkov } else 2746f9431992SDoug Thompson /* CLEAR the override, since BIOS controlled it */ 2747f9431992SDoug Thompson ecc_enable_override = 0; 2748f9431992SDoug Thompson 2749be3468e8SBorislav Petkov return 0; 2750f9431992SDoug Thompson } 2751f9431992SDoug Thompson 27527d6034d3SDoug Thompson struct mcidev_sysfs_attribute sysfs_attrs[ARRAY_SIZE(amd64_dbg_attrs) + 27537d6034d3SDoug Thompson ARRAY_SIZE(amd64_inj_attrs) + 27547d6034d3SDoug Thompson 1]; 27557d6034d3SDoug Thompson 27567d6034d3SDoug Thompson struct mcidev_sysfs_attribute terminator = { .attr = { .name = NULL } }; 27577d6034d3SDoug Thompson 27587d6034d3SDoug Thompson static void amd64_set_mc_sysfs_attributes(struct mem_ctl_info *mci) 27597d6034d3SDoug Thompson { 27607d6034d3SDoug Thompson unsigned int i = 0, j = 0; 27617d6034d3SDoug Thompson 27627d6034d3SDoug Thompson for (; i < ARRAY_SIZE(amd64_dbg_attrs); i++) 27637d6034d3SDoug Thompson sysfs_attrs[i] = amd64_dbg_attrs[i]; 27647d6034d3SDoug Thompson 27657d6034d3SDoug Thompson for (j = 0; j < ARRAY_SIZE(amd64_inj_attrs); j++, i++) 27667d6034d3SDoug Thompson sysfs_attrs[i] = amd64_inj_attrs[j]; 27677d6034d3SDoug Thompson 27687d6034d3SDoug Thompson sysfs_attrs[i] = terminator; 27697d6034d3SDoug Thompson 27707d6034d3SDoug Thompson mci->mc_driver_sysfs_attributes = sysfs_attrs; 27717d6034d3SDoug Thompson } 27727d6034d3SDoug Thompson 27737d6034d3SDoug Thompson static void amd64_setup_mci_misc_attributes(struct mem_ctl_info *mci) 27747d6034d3SDoug Thompson { 27757d6034d3SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 27767d6034d3SDoug Thompson 27777d6034d3SDoug Thompson mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; 27787d6034d3SDoug Thompson mci->edac_ctl_cap = EDAC_FLAG_NONE; 27797d6034d3SDoug Thompson 27807d6034d3SDoug Thompson if (pvt->nbcap & K8_NBCAP_SECDED) 27817d6034d3SDoug Thompson mci->edac_ctl_cap |= EDAC_FLAG_SECDED; 27827d6034d3SDoug Thompson 27837d6034d3SDoug Thompson if (pvt->nbcap & K8_NBCAP_CHIPKILL) 27847d6034d3SDoug Thompson mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; 27857d6034d3SDoug Thompson 27867d6034d3SDoug Thompson mci->edac_cap = amd64_determine_edac_cap(pvt); 27877d6034d3SDoug Thompson mci->mod_name = EDAC_MOD_STR; 27887d6034d3SDoug Thompson mci->mod_ver = EDAC_AMD64_VERSION; 27897d6034d3SDoug Thompson mci->ctl_name = get_amd_family_name(pvt->mc_type_index); 27907d6034d3SDoug Thompson mci->dev_name = pci_name(pvt->dram_f2_ctl); 27917d6034d3SDoug Thompson mci->ctl_page_to_phys = NULL; 27927d6034d3SDoug Thompson 27937d6034d3SDoug Thompson /* IMPORTANT: Set the polling 'check' function in this module */ 27947d6034d3SDoug Thompson mci->edac_check = amd64_check; 27957d6034d3SDoug Thompson 27967d6034d3SDoug Thompson /* memory scrubber interface */ 27977d6034d3SDoug Thompson mci->set_sdram_scrub_rate = amd64_set_scrub_rate; 27987d6034d3SDoug Thompson mci->get_sdram_scrub_rate = amd64_get_scrub_rate; 27997d6034d3SDoug Thompson } 28007d6034d3SDoug Thompson 28017d6034d3SDoug Thompson /* 28027d6034d3SDoug Thompson * Init stuff for this DRAM Controller device. 28037d6034d3SDoug Thompson * 28047d6034d3SDoug Thompson * Due to a hardware feature on Fam10h CPUs, the Enable Extended Configuration 28057d6034d3SDoug Thompson * Space feature MUST be enabled on ALL Processors prior to actually reading 28067d6034d3SDoug Thompson * from the ECS registers. Since the loading of the module can occur on any 28077d6034d3SDoug Thompson * 'core', and cores don't 'see' all the other processors ECS data when the 28087d6034d3SDoug Thompson * others are NOT enabled. Our solution is to first enable ECS access in this 28097d6034d3SDoug Thompson * routine on all processors, gather some data in a amd64_pvt structure and 28107d6034d3SDoug Thompson * later come back in a finish-setup function to perform that final 28117d6034d3SDoug Thompson * initialization. See also amd64_init_2nd_stage() for that. 28127d6034d3SDoug Thompson */ 28137d6034d3SDoug Thompson static int amd64_probe_one_instance(struct pci_dev *dram_f2_ctl, 28147d6034d3SDoug Thompson int mc_type_index) 28157d6034d3SDoug Thompson { 28167d6034d3SDoug Thompson struct amd64_pvt *pvt = NULL; 28177d6034d3SDoug Thompson int err = 0, ret; 28187d6034d3SDoug Thompson 28197d6034d3SDoug Thompson ret = -ENOMEM; 28207d6034d3SDoug Thompson pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL); 28217d6034d3SDoug Thompson if (!pvt) 28227d6034d3SDoug Thompson goto err_exit; 28237d6034d3SDoug Thompson 282437da0450SBorislav Petkov pvt->mc_node_id = get_node_id(dram_f2_ctl); 28257d6034d3SDoug Thompson 28267d6034d3SDoug Thompson pvt->dram_f2_ctl = dram_f2_ctl; 28277d6034d3SDoug Thompson pvt->ext_model = boot_cpu_data.x86_model >> 4; 28287d6034d3SDoug Thompson pvt->mc_type_index = mc_type_index; 28297d6034d3SDoug Thompson pvt->ops = family_ops(mc_type_index); 28307d6034d3SDoug Thompson 28317d6034d3SDoug Thompson /* 28327d6034d3SDoug Thompson * We have the dram_f2_ctl device as an argument, now go reserve its 28337d6034d3SDoug Thompson * sibling devices from the PCI system. 28347d6034d3SDoug Thompson */ 28357d6034d3SDoug Thompson ret = -ENODEV; 28367d6034d3SDoug Thompson err = amd64_reserve_mc_sibling_devices(pvt, mc_type_index); 28377d6034d3SDoug Thompson if (err) 28387d6034d3SDoug Thompson goto err_free; 28397d6034d3SDoug Thompson 28407d6034d3SDoug Thompson ret = -EINVAL; 28417d6034d3SDoug Thompson err = amd64_check_ecc_enabled(pvt); 28427d6034d3SDoug Thompson if (err) 28437d6034d3SDoug Thompson goto err_put; 28447d6034d3SDoug Thompson 28457d6034d3SDoug Thompson /* 28467d6034d3SDoug Thompson * Key operation here: setup of HW prior to performing ops on it. Some 28477d6034d3SDoug Thompson * setup is required to access ECS data. After this is performed, the 28487d6034d3SDoug Thompson * 'teardown' function must be called upon error and normal exit paths. 28497d6034d3SDoug Thompson */ 28507d6034d3SDoug Thompson if (boot_cpu_data.x86 >= 0x10) 28517d6034d3SDoug Thompson amd64_setup(pvt); 28527d6034d3SDoug Thompson 28537d6034d3SDoug Thompson /* 28547d6034d3SDoug Thompson * Save the pointer to the private data for use in 2nd initialization 28557d6034d3SDoug Thompson * stage 28567d6034d3SDoug Thompson */ 28577d6034d3SDoug Thompson pvt_lookup[pvt->mc_node_id] = pvt; 28587d6034d3SDoug Thompson 28597d6034d3SDoug Thompson return 0; 28607d6034d3SDoug Thompson 28617d6034d3SDoug Thompson err_put: 28627d6034d3SDoug Thompson amd64_free_mc_sibling_devices(pvt); 28637d6034d3SDoug Thompson 28647d6034d3SDoug Thompson err_free: 28657d6034d3SDoug Thompson kfree(pvt); 28667d6034d3SDoug Thompson 28677d6034d3SDoug Thompson err_exit: 28687d6034d3SDoug Thompson return ret; 28697d6034d3SDoug Thompson } 28707d6034d3SDoug Thompson 28717d6034d3SDoug Thompson /* 28727d6034d3SDoug Thompson * This is the finishing stage of the init code. Needs to be performed after all 28737d6034d3SDoug Thompson * MCs' hardware have been prepped for accessing extended config space. 28747d6034d3SDoug Thompson */ 28757d6034d3SDoug Thompson static int amd64_init_2nd_stage(struct amd64_pvt *pvt) 28767d6034d3SDoug Thompson { 28777d6034d3SDoug Thompson int node_id = pvt->mc_node_id; 28787d6034d3SDoug Thompson struct mem_ctl_info *mci; 28797d6034d3SDoug Thompson int ret, err = 0; 28807d6034d3SDoug Thompson 28817d6034d3SDoug Thompson amd64_read_mc_registers(pvt); 28827d6034d3SDoug Thompson 28837d6034d3SDoug Thompson ret = -ENODEV; 28847d6034d3SDoug Thompson if (pvt->ops->probe_valid_hardware) { 28857d6034d3SDoug Thompson err = pvt->ops->probe_valid_hardware(pvt); 28867d6034d3SDoug Thompson if (err) 28877d6034d3SDoug Thompson goto err_exit; 28887d6034d3SDoug Thompson } 28897d6034d3SDoug Thompson 28907d6034d3SDoug Thompson /* 28917d6034d3SDoug Thompson * We need to determine how many memory channels there are. Then use 28927d6034d3SDoug Thompson * that information for calculating the size of the dynamic instance 28937d6034d3SDoug Thompson * tables in the 'mci' structure 28947d6034d3SDoug Thompson */ 28957d6034d3SDoug Thompson pvt->channel_count = pvt->ops->early_channel_count(pvt); 28967d6034d3SDoug Thompson if (pvt->channel_count < 0) 28977d6034d3SDoug Thompson goto err_exit; 28987d6034d3SDoug Thompson 28997d6034d3SDoug Thompson ret = -ENOMEM; 29009d858bb1SBorislav Petkov mci = edac_mc_alloc(0, pvt->cs_count, pvt->channel_count, node_id); 29017d6034d3SDoug Thompson if (!mci) 29027d6034d3SDoug Thompson goto err_exit; 29037d6034d3SDoug Thompson 29047d6034d3SDoug Thompson mci->pvt_info = pvt; 29057d6034d3SDoug Thompson 29067d6034d3SDoug Thompson mci->dev = &pvt->dram_f2_ctl->dev; 29077d6034d3SDoug Thompson amd64_setup_mci_misc_attributes(mci); 29087d6034d3SDoug Thompson 29097d6034d3SDoug Thompson if (amd64_init_csrows(mci)) 29107d6034d3SDoug Thompson mci->edac_cap = EDAC_FLAG_NONE; 29117d6034d3SDoug Thompson 29127d6034d3SDoug Thompson amd64_enable_ecc_error_reporting(mci); 29137d6034d3SDoug Thompson amd64_set_mc_sysfs_attributes(mci); 29147d6034d3SDoug Thompson 29157d6034d3SDoug Thompson ret = -ENODEV; 29167d6034d3SDoug Thompson if (edac_mc_add_mc(mci)) { 29177d6034d3SDoug Thompson debugf1("failed edac_mc_add_mc()\n"); 29187d6034d3SDoug Thompson goto err_add_mc; 29197d6034d3SDoug Thompson } 29207d6034d3SDoug Thompson 29217d6034d3SDoug Thompson mci_lookup[node_id] = mci; 29227d6034d3SDoug Thompson pvt_lookup[node_id] = NULL; 2923549d042dSBorislav Petkov 2924549d042dSBorislav Petkov /* register stuff with EDAC MCE */ 2925549d042dSBorislav Petkov if (report_gart_errors) 2926549d042dSBorislav Petkov amd_report_gart_errors(true); 2927549d042dSBorislav Petkov 2928549d042dSBorislav Petkov amd_register_ecc_decoder(amd64_decode_bus_error); 2929549d042dSBorislav Petkov 29307d6034d3SDoug Thompson return 0; 29317d6034d3SDoug Thompson 29327d6034d3SDoug Thompson err_add_mc: 29337d6034d3SDoug Thompson edac_mc_free(mci); 29347d6034d3SDoug Thompson 29357d6034d3SDoug Thompson err_exit: 29367d6034d3SDoug Thompson debugf0("failure to init 2nd stage: ret=%d\n", ret); 29377d6034d3SDoug Thompson 29387d6034d3SDoug Thompson amd64_restore_ecc_error_reporting(pvt); 29397d6034d3SDoug Thompson 29407d6034d3SDoug Thompson if (boot_cpu_data.x86 > 0xf) 29417d6034d3SDoug Thompson amd64_teardown(pvt); 29427d6034d3SDoug Thompson 29437d6034d3SDoug Thompson amd64_free_mc_sibling_devices(pvt); 29447d6034d3SDoug Thompson 29457d6034d3SDoug Thompson kfree(pvt_lookup[pvt->mc_node_id]); 29467d6034d3SDoug Thompson pvt_lookup[node_id] = NULL; 29477d6034d3SDoug Thompson 29487d6034d3SDoug Thompson return ret; 29497d6034d3SDoug Thompson } 29507d6034d3SDoug Thompson 29517d6034d3SDoug Thompson 29527d6034d3SDoug Thompson static int __devinit amd64_init_one_instance(struct pci_dev *pdev, 29537d6034d3SDoug Thompson const struct pci_device_id *mc_type) 29547d6034d3SDoug Thompson { 29557d6034d3SDoug Thompson int ret = 0; 29567d6034d3SDoug Thompson 295737da0450SBorislav Petkov debugf0("(MC node=%d,mc_type='%s')\n", get_node_id(pdev), 29587d6034d3SDoug Thompson get_amd_family_name(mc_type->driver_data)); 29597d6034d3SDoug Thompson 29607d6034d3SDoug Thompson ret = pci_enable_device(pdev); 29617d6034d3SDoug Thompson if (ret < 0) 29627d6034d3SDoug Thompson ret = -EIO; 29637d6034d3SDoug Thompson else 29647d6034d3SDoug Thompson ret = amd64_probe_one_instance(pdev, mc_type->driver_data); 29657d6034d3SDoug Thompson 29667d6034d3SDoug Thompson if (ret < 0) 29677d6034d3SDoug Thompson debugf0("ret=%d\n", ret); 29687d6034d3SDoug Thompson 29697d6034d3SDoug Thompson return ret; 29707d6034d3SDoug Thompson } 29717d6034d3SDoug Thompson 29727d6034d3SDoug Thompson static void __devexit amd64_remove_one_instance(struct pci_dev *pdev) 29737d6034d3SDoug Thompson { 29747d6034d3SDoug Thompson struct mem_ctl_info *mci; 29757d6034d3SDoug Thompson struct amd64_pvt *pvt; 29767d6034d3SDoug Thompson 29777d6034d3SDoug Thompson /* Remove from EDAC CORE tracking list */ 29787d6034d3SDoug Thompson mci = edac_mc_del_mc(&pdev->dev); 29797d6034d3SDoug Thompson if (!mci) 29807d6034d3SDoug Thompson return; 29817d6034d3SDoug Thompson 29827d6034d3SDoug Thompson pvt = mci->pvt_info; 29837d6034d3SDoug Thompson 29847d6034d3SDoug Thompson amd64_restore_ecc_error_reporting(pvt); 29857d6034d3SDoug Thompson 29867d6034d3SDoug Thompson if (boot_cpu_data.x86 > 0xf) 29877d6034d3SDoug Thompson amd64_teardown(pvt); 29887d6034d3SDoug Thompson 29897d6034d3SDoug Thompson amd64_free_mc_sibling_devices(pvt); 29907d6034d3SDoug Thompson 29917d6034d3SDoug Thompson kfree(pvt); 29927d6034d3SDoug Thompson mci->pvt_info = NULL; 29937d6034d3SDoug Thompson 29947d6034d3SDoug Thompson mci_lookup[pvt->mc_node_id] = NULL; 29957d6034d3SDoug Thompson 2996549d042dSBorislav Petkov /* unregister from EDAC MCE */ 2997549d042dSBorislav Petkov amd_report_gart_errors(false); 2998549d042dSBorislav Petkov amd_unregister_ecc_decoder(amd64_decode_bus_error); 2999549d042dSBorislav Petkov 30007d6034d3SDoug Thompson /* Free the EDAC CORE resources */ 30017d6034d3SDoug Thompson edac_mc_free(mci); 30027d6034d3SDoug Thompson } 30037d6034d3SDoug Thompson 30047d6034d3SDoug Thompson /* 30057d6034d3SDoug Thompson * This table is part of the interface for loading drivers for PCI devices. The 30067d6034d3SDoug Thompson * PCI core identifies what devices are on a system during boot, and then 30077d6034d3SDoug Thompson * inquiry this table to see if this driver is for a given device found. 30087d6034d3SDoug Thompson */ 30097d6034d3SDoug Thompson static const struct pci_device_id amd64_pci_table[] __devinitdata = { 30107d6034d3SDoug Thompson { 30117d6034d3SDoug Thompson .vendor = PCI_VENDOR_ID_AMD, 30127d6034d3SDoug Thompson .device = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL, 30137d6034d3SDoug Thompson .subvendor = PCI_ANY_ID, 30147d6034d3SDoug Thompson .subdevice = PCI_ANY_ID, 30157d6034d3SDoug Thompson .class = 0, 30167d6034d3SDoug Thompson .class_mask = 0, 30177d6034d3SDoug Thompson .driver_data = K8_CPUS 30187d6034d3SDoug Thompson }, 30197d6034d3SDoug Thompson { 30207d6034d3SDoug Thompson .vendor = PCI_VENDOR_ID_AMD, 30217d6034d3SDoug Thompson .device = PCI_DEVICE_ID_AMD_10H_NB_DRAM, 30227d6034d3SDoug Thompson .subvendor = PCI_ANY_ID, 30237d6034d3SDoug Thompson .subdevice = PCI_ANY_ID, 30247d6034d3SDoug Thompson .class = 0, 30257d6034d3SDoug Thompson .class_mask = 0, 30267d6034d3SDoug Thompson .driver_data = F10_CPUS 30277d6034d3SDoug Thompson }, 30287d6034d3SDoug Thompson { 30297d6034d3SDoug Thompson .vendor = PCI_VENDOR_ID_AMD, 30307d6034d3SDoug Thompson .device = PCI_DEVICE_ID_AMD_11H_NB_DRAM, 30317d6034d3SDoug Thompson .subvendor = PCI_ANY_ID, 30327d6034d3SDoug Thompson .subdevice = PCI_ANY_ID, 30337d6034d3SDoug Thompson .class = 0, 30347d6034d3SDoug Thompson .class_mask = 0, 30357d6034d3SDoug Thompson .driver_data = F11_CPUS 30367d6034d3SDoug Thompson }, 30377d6034d3SDoug Thompson {0, } 30387d6034d3SDoug Thompson }; 30397d6034d3SDoug Thompson MODULE_DEVICE_TABLE(pci, amd64_pci_table); 30407d6034d3SDoug Thompson 30417d6034d3SDoug Thompson static struct pci_driver amd64_pci_driver = { 30427d6034d3SDoug Thompson .name = EDAC_MOD_STR, 30437d6034d3SDoug Thompson .probe = amd64_init_one_instance, 30447d6034d3SDoug Thompson .remove = __devexit_p(amd64_remove_one_instance), 30457d6034d3SDoug Thompson .id_table = amd64_pci_table, 30467d6034d3SDoug Thompson }; 30477d6034d3SDoug Thompson 30487d6034d3SDoug Thompson static void amd64_setup_pci_device(void) 30497d6034d3SDoug Thompson { 30507d6034d3SDoug Thompson struct mem_ctl_info *mci; 30517d6034d3SDoug Thompson struct amd64_pvt *pvt; 30527d6034d3SDoug Thompson 30537d6034d3SDoug Thompson if (amd64_ctl_pci) 30547d6034d3SDoug Thompson return; 30557d6034d3SDoug Thompson 30567d6034d3SDoug Thompson mci = mci_lookup[0]; 30577d6034d3SDoug Thompson if (mci) { 30587d6034d3SDoug Thompson 30597d6034d3SDoug Thompson pvt = mci->pvt_info; 30607d6034d3SDoug Thompson amd64_ctl_pci = 30617d6034d3SDoug Thompson edac_pci_create_generic_ctl(&pvt->dram_f2_ctl->dev, 30627d6034d3SDoug Thompson EDAC_MOD_STR); 30637d6034d3SDoug Thompson 30647d6034d3SDoug Thompson if (!amd64_ctl_pci) { 30657d6034d3SDoug Thompson pr_warning("%s(): Unable to create PCI control\n", 30667d6034d3SDoug Thompson __func__); 30677d6034d3SDoug Thompson 30687d6034d3SDoug Thompson pr_warning("%s(): PCI error report via EDAC not set\n", 30697d6034d3SDoug Thompson __func__); 30707d6034d3SDoug Thompson } 30717d6034d3SDoug Thompson } 30727d6034d3SDoug Thompson } 30737d6034d3SDoug Thompson 30747d6034d3SDoug Thompson static int __init amd64_edac_init(void) 30757d6034d3SDoug Thompson { 30767d6034d3SDoug Thompson int nb, err = -ENODEV; 30777d6034d3SDoug Thompson 30787d6034d3SDoug Thompson edac_printk(KERN_INFO, EDAC_MOD_STR, EDAC_AMD64_VERSION "\n"); 30797d6034d3SDoug Thompson 30807d6034d3SDoug Thompson opstate_init(); 30817d6034d3SDoug Thompson 30827d6034d3SDoug Thompson if (cache_k8_northbridges() < 0) 3083a3c4c580SLi Hong return err; 30847d6034d3SDoug Thompson 30857d6034d3SDoug Thompson err = pci_register_driver(&amd64_pci_driver); 30867d6034d3SDoug Thompson if (err) 30877d6034d3SDoug Thompson return err; 30887d6034d3SDoug Thompson 30897d6034d3SDoug Thompson /* 30907d6034d3SDoug Thompson * At this point, the array 'pvt_lookup[]' contains pointers to alloc'd 30917d6034d3SDoug Thompson * amd64_pvt structs. These will be used in the 2nd stage init function 30927d6034d3SDoug Thompson * to finish initialization of the MC instances. 30937d6034d3SDoug Thompson */ 30947d6034d3SDoug Thompson for (nb = 0; nb < num_k8_northbridges; nb++) { 30957d6034d3SDoug Thompson if (!pvt_lookup[nb]) 30967d6034d3SDoug Thompson continue; 30977d6034d3SDoug Thompson 30987d6034d3SDoug Thompson err = amd64_init_2nd_stage(pvt_lookup[nb]); 30997d6034d3SDoug Thompson if (err) 310037da0450SBorislav Petkov goto err_2nd_stage; 31017d6034d3SDoug Thompson } 31027d6034d3SDoug Thompson 31037d6034d3SDoug Thompson amd64_setup_pci_device(); 31047d6034d3SDoug Thompson 31057d6034d3SDoug Thompson return 0; 31067d6034d3SDoug Thompson 310737da0450SBorislav Petkov err_2nd_stage: 310837da0450SBorislav Petkov debugf0("2nd stage failed\n"); 31097d6034d3SDoug Thompson pci_unregister_driver(&amd64_pci_driver); 31107d6034d3SDoug Thompson 31117d6034d3SDoug Thompson return err; 31127d6034d3SDoug Thompson } 31137d6034d3SDoug Thompson 31147d6034d3SDoug Thompson static void __exit amd64_edac_exit(void) 31157d6034d3SDoug Thompson { 31167d6034d3SDoug Thompson if (amd64_ctl_pci) 31177d6034d3SDoug Thompson edac_pci_release_generic_ctl(amd64_ctl_pci); 31187d6034d3SDoug Thompson 31197d6034d3SDoug Thompson pci_unregister_driver(&amd64_pci_driver); 31207d6034d3SDoug Thompson } 31217d6034d3SDoug Thompson 31227d6034d3SDoug Thompson module_init(amd64_edac_init); 31237d6034d3SDoug Thompson module_exit(amd64_edac_exit); 31247d6034d3SDoug Thompson 31257d6034d3SDoug Thompson MODULE_LICENSE("GPL"); 31267d6034d3SDoug Thompson MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, " 31277d6034d3SDoug Thompson "Dave Peterson, Thayne Harbaugh"); 31287d6034d3SDoug Thompson MODULE_DESCRIPTION("MC support for AMD64 memory controllers - " 31297d6034d3SDoug Thompson EDAC_AMD64_VERSION); 31307d6034d3SDoug Thompson 31317d6034d3SDoug Thompson module_param(edac_op_state, int, 0444); 31327d6034d3SDoug Thompson MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 3133