12bc65418SDoug Thompson #include "amd64_edac.h" 27d6034d3SDoug Thompson #include <asm/k8.h> 32bc65418SDoug Thompson 42bc65418SDoug Thompson static struct edac_pci_ctl_info *amd64_ctl_pci; 52bc65418SDoug Thompson 62bc65418SDoug Thompson static int report_gart_errors; 72bc65418SDoug Thompson module_param(report_gart_errors, int, 0644); 82bc65418SDoug Thompson 92bc65418SDoug Thompson /* 102bc65418SDoug Thompson * Set by command line parameter. If BIOS has enabled the ECC, this override is 112bc65418SDoug Thompson * cleared to prevent re-enabling the hardware by this driver. 122bc65418SDoug Thompson */ 132bc65418SDoug Thompson static int ecc_enable_override; 142bc65418SDoug Thompson module_param(ecc_enable_override, int, 0644); 152bc65418SDoug Thompson 162bc65418SDoug Thompson /* Lookup table for all possible MC control instances */ 172bc65418SDoug Thompson struct amd64_pvt; 182bc65418SDoug Thompson static struct mem_ctl_info *mci_lookup[MAX_NUMNODES]; 192bc65418SDoug Thompson static struct amd64_pvt *pvt_lookup[MAX_NUMNODES]; 202bc65418SDoug Thompson 212bc65418SDoug Thompson /* 22b70ef010SBorislav Petkov * See F2x80 for K8 and F2x[1,0]80 for Fam10 and later. The table below is only 23b70ef010SBorislav Petkov * for DDR2 DRAM mapping. 24b70ef010SBorislav Petkov */ 25b70ef010SBorislav Petkov u32 revf_quad_ddr2_shift[] = { 26b70ef010SBorislav Petkov 0, /* 0000b NULL DIMM (128mb) */ 27b70ef010SBorislav Petkov 28, /* 0001b 256mb */ 28b70ef010SBorislav Petkov 29, /* 0010b 512mb */ 29b70ef010SBorislav Petkov 29, /* 0011b 512mb */ 30b70ef010SBorislav Petkov 29, /* 0100b 512mb */ 31b70ef010SBorislav Petkov 30, /* 0101b 1gb */ 32b70ef010SBorislav Petkov 30, /* 0110b 1gb */ 33b70ef010SBorislav Petkov 31, /* 0111b 2gb */ 34b70ef010SBorislav Petkov 31, /* 1000b 2gb */ 35b70ef010SBorislav Petkov 32, /* 1001b 4gb */ 36b70ef010SBorislav Petkov 32, /* 1010b 4gb */ 37b70ef010SBorislav Petkov 33, /* 1011b 8gb */ 38b70ef010SBorislav Petkov 0, /* 1100b future */ 39b70ef010SBorislav Petkov 0, /* 1101b future */ 40b70ef010SBorislav Petkov 0, /* 1110b future */ 41b70ef010SBorislav Petkov 0 /* 1111b future */ 42b70ef010SBorislav Petkov }; 43b70ef010SBorislav Petkov 44b70ef010SBorislav Petkov /* 45b70ef010SBorislav Petkov * Valid scrub rates for the K8 hardware memory scrubber. We map the scrubbing 46b70ef010SBorislav Petkov * bandwidth to a valid bit pattern. The 'set' operation finds the 'matching- 47b70ef010SBorislav Petkov * or higher value'. 48b70ef010SBorislav Petkov * 49b70ef010SBorislav Petkov *FIXME: Produce a better mapping/linearisation. 50b70ef010SBorislav Petkov */ 51b70ef010SBorislav Petkov 52b70ef010SBorislav Petkov struct scrubrate scrubrates[] = { 53b70ef010SBorislav Petkov { 0x01, 1600000000UL}, 54b70ef010SBorislav Petkov { 0x02, 800000000UL}, 55b70ef010SBorislav Petkov { 0x03, 400000000UL}, 56b70ef010SBorislav Petkov { 0x04, 200000000UL}, 57b70ef010SBorislav Petkov { 0x05, 100000000UL}, 58b70ef010SBorislav Petkov { 0x06, 50000000UL}, 59b70ef010SBorislav Petkov { 0x07, 25000000UL}, 60b70ef010SBorislav Petkov { 0x08, 12284069UL}, 61b70ef010SBorislav Petkov { 0x09, 6274509UL}, 62b70ef010SBorislav Petkov { 0x0A, 3121951UL}, 63b70ef010SBorislav Petkov { 0x0B, 1560975UL}, 64b70ef010SBorislav Petkov { 0x0C, 781440UL}, 65b70ef010SBorislav Petkov { 0x0D, 390720UL}, 66b70ef010SBorislav Petkov { 0x0E, 195300UL}, 67b70ef010SBorislav Petkov { 0x0F, 97650UL}, 68b70ef010SBorislav Petkov { 0x10, 48854UL}, 69b70ef010SBorislav Petkov { 0x11, 24427UL}, 70b70ef010SBorislav Petkov { 0x12, 12213UL}, 71b70ef010SBorislav Petkov { 0x13, 6101UL}, 72b70ef010SBorislav Petkov { 0x14, 3051UL}, 73b70ef010SBorislav Petkov { 0x15, 1523UL}, 74b70ef010SBorislav Petkov { 0x16, 761UL}, 75b70ef010SBorislav Petkov { 0x00, 0UL}, /* scrubbing off */ 76b70ef010SBorislav Petkov }; 77b70ef010SBorislav Petkov 78b70ef010SBorislav Petkov /* 792bc65418SDoug Thompson * Memory scrubber control interface. For K8, memory scrubbing is handled by 802bc65418SDoug Thompson * hardware and can involve L2 cache, dcache as well as the main memory. With 812bc65418SDoug Thompson * F10, this is extended to L3 cache scrubbing on CPU models sporting that 822bc65418SDoug Thompson * functionality. 832bc65418SDoug Thompson * 842bc65418SDoug Thompson * This causes the "units" for the scrubbing speed to vary from 64 byte blocks 852bc65418SDoug Thompson * (dram) over to cache lines. This is nasty, so we will use bandwidth in 862bc65418SDoug Thompson * bytes/sec for the setting. 872bc65418SDoug Thompson * 882bc65418SDoug Thompson * Currently, we only do dram scrubbing. If the scrubbing is done in software on 892bc65418SDoug Thompson * other archs, we might not have access to the caches directly. 902bc65418SDoug Thompson */ 912bc65418SDoug Thompson 922bc65418SDoug Thompson /* 932bc65418SDoug Thompson * scan the scrub rate mapping table for a close or matching bandwidth value to 942bc65418SDoug Thompson * issue. If requested is too big, then use last maximum value found. 952bc65418SDoug Thompson */ 962bc65418SDoug Thompson static int amd64_search_set_scrub_rate(struct pci_dev *ctl, u32 new_bw, 972bc65418SDoug Thompson u32 min_scrubrate) 982bc65418SDoug Thompson { 992bc65418SDoug Thompson u32 scrubval; 1002bc65418SDoug Thompson int i; 1012bc65418SDoug Thompson 1022bc65418SDoug Thompson /* 1032bc65418SDoug Thompson * map the configured rate (new_bw) to a value specific to the AMD64 1042bc65418SDoug Thompson * memory controller and apply to register. Search for the first 1052bc65418SDoug Thompson * bandwidth entry that is greater or equal than the setting requested 1062bc65418SDoug Thompson * and program that. If at last entry, turn off DRAM scrubbing. 1072bc65418SDoug Thompson */ 1082bc65418SDoug Thompson for (i = 0; i < ARRAY_SIZE(scrubrates); i++) { 1092bc65418SDoug Thompson /* 1102bc65418SDoug Thompson * skip scrub rates which aren't recommended 1112bc65418SDoug Thompson * (see F10 BKDG, F3x58) 1122bc65418SDoug Thompson */ 1132bc65418SDoug Thompson if (scrubrates[i].scrubval < min_scrubrate) 1142bc65418SDoug Thompson continue; 1152bc65418SDoug Thompson 1162bc65418SDoug Thompson if (scrubrates[i].bandwidth <= new_bw) 1172bc65418SDoug Thompson break; 1182bc65418SDoug Thompson 1192bc65418SDoug Thompson /* 1202bc65418SDoug Thompson * if no suitable bandwidth found, turn off DRAM scrubbing 1212bc65418SDoug Thompson * entirely by falling back to the last element in the 1222bc65418SDoug Thompson * scrubrates array. 1232bc65418SDoug Thompson */ 1242bc65418SDoug Thompson } 1252bc65418SDoug Thompson 1262bc65418SDoug Thompson scrubval = scrubrates[i].scrubval; 1272bc65418SDoug Thompson if (scrubval) 1282bc65418SDoug Thompson edac_printk(KERN_DEBUG, EDAC_MC, 1292bc65418SDoug Thompson "Setting scrub rate bandwidth: %u\n", 1302bc65418SDoug Thompson scrubrates[i].bandwidth); 1312bc65418SDoug Thompson else 1322bc65418SDoug Thompson edac_printk(KERN_DEBUG, EDAC_MC, "Turning scrubbing off.\n"); 1332bc65418SDoug Thompson 1342bc65418SDoug Thompson pci_write_bits32(ctl, K8_SCRCTRL, scrubval, 0x001F); 1352bc65418SDoug Thompson 1362bc65418SDoug Thompson return 0; 1372bc65418SDoug Thompson } 1382bc65418SDoug Thompson 1392bc65418SDoug Thompson static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 *bandwidth) 1402bc65418SDoug Thompson { 1412bc65418SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 1422bc65418SDoug Thompson u32 min_scrubrate = 0x0; 1432bc65418SDoug Thompson 1442bc65418SDoug Thompson switch (boot_cpu_data.x86) { 1452bc65418SDoug Thompson case 0xf: 1462bc65418SDoug Thompson min_scrubrate = K8_MIN_SCRUB_RATE_BITS; 1472bc65418SDoug Thompson break; 1482bc65418SDoug Thompson case 0x10: 1492bc65418SDoug Thompson min_scrubrate = F10_MIN_SCRUB_RATE_BITS; 1502bc65418SDoug Thompson break; 1512bc65418SDoug Thompson case 0x11: 1522bc65418SDoug Thompson min_scrubrate = F11_MIN_SCRUB_RATE_BITS; 1532bc65418SDoug Thompson break; 1542bc65418SDoug Thompson 1552bc65418SDoug Thompson default: 1562bc65418SDoug Thompson amd64_printk(KERN_ERR, "Unsupported family!\n"); 1572bc65418SDoug Thompson break; 1582bc65418SDoug Thompson } 1592bc65418SDoug Thompson return amd64_search_set_scrub_rate(pvt->misc_f3_ctl, *bandwidth, 1602bc65418SDoug Thompson min_scrubrate); 1612bc65418SDoug Thompson } 1622bc65418SDoug Thompson 1632bc65418SDoug Thompson static int amd64_get_scrub_rate(struct mem_ctl_info *mci, u32 *bw) 1642bc65418SDoug Thompson { 1652bc65418SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 1662bc65418SDoug Thompson u32 scrubval = 0; 1672bc65418SDoug Thompson int status = -1, i, ret = 0; 1682bc65418SDoug Thompson 1692bc65418SDoug Thompson ret = pci_read_config_dword(pvt->misc_f3_ctl, K8_SCRCTRL, &scrubval); 1702bc65418SDoug Thompson if (ret) 1712bc65418SDoug Thompson debugf0("Reading K8_SCRCTRL failed\n"); 1722bc65418SDoug Thompson 1732bc65418SDoug Thompson scrubval = scrubval & 0x001F; 1742bc65418SDoug Thompson 1752bc65418SDoug Thompson edac_printk(KERN_DEBUG, EDAC_MC, 1762bc65418SDoug Thompson "pci-read, sdram scrub control value: %d \n", scrubval); 1772bc65418SDoug Thompson 1782bc65418SDoug Thompson for (i = 0; ARRAY_SIZE(scrubrates); i++) { 1792bc65418SDoug Thompson if (scrubrates[i].scrubval == scrubval) { 1802bc65418SDoug Thompson *bw = scrubrates[i].bandwidth; 1812bc65418SDoug Thompson status = 0; 1822bc65418SDoug Thompson break; 1832bc65418SDoug Thompson } 1842bc65418SDoug Thompson } 1852bc65418SDoug Thompson 1862bc65418SDoug Thompson return status; 1872bc65418SDoug Thompson } 1882bc65418SDoug Thompson 1896775763aSDoug Thompson /* Map from a CSROW entry to the mask entry that operates on it */ 1906775763aSDoug Thompson static inline u32 amd64_map_to_dcs_mask(struct amd64_pvt *pvt, int csrow) 1916775763aSDoug Thompson { 1926775763aSDoug Thompson return csrow >> (pvt->num_dcsm >> 3); 1936775763aSDoug Thompson } 1946775763aSDoug Thompson 1956775763aSDoug Thompson /* return the 'base' address the i'th CS entry of the 'dct' DRAM controller */ 1966775763aSDoug Thompson static u32 amd64_get_dct_base(struct amd64_pvt *pvt, int dct, int csrow) 1976775763aSDoug Thompson { 1986775763aSDoug Thompson if (dct == 0) 1996775763aSDoug Thompson return pvt->dcsb0[csrow]; 2006775763aSDoug Thompson else 2016775763aSDoug Thompson return pvt->dcsb1[csrow]; 2026775763aSDoug Thompson } 2036775763aSDoug Thompson 2046775763aSDoug Thompson /* 2056775763aSDoug Thompson * Return the 'mask' address the i'th CS entry. This function is needed because 2066775763aSDoug Thompson * there number of DCSM registers on Rev E and prior vs Rev F and later is 2076775763aSDoug Thompson * different. 2086775763aSDoug Thompson */ 2096775763aSDoug Thompson static u32 amd64_get_dct_mask(struct amd64_pvt *pvt, int dct, int csrow) 2106775763aSDoug Thompson { 2116775763aSDoug Thompson if (dct == 0) 2126775763aSDoug Thompson return pvt->dcsm0[amd64_map_to_dcs_mask(pvt, csrow)]; 2136775763aSDoug Thompson else 2146775763aSDoug Thompson return pvt->dcsm1[amd64_map_to_dcs_mask(pvt, csrow)]; 2156775763aSDoug Thompson } 2166775763aSDoug Thompson 2176775763aSDoug Thompson 2186775763aSDoug Thompson /* 2196775763aSDoug Thompson * In *base and *limit, pass back the full 40-bit base and limit physical 2206775763aSDoug Thompson * addresses for the node given by node_id. This information is obtained from 2216775763aSDoug Thompson * DRAM Base (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers. The 2226775763aSDoug Thompson * base and limit addresses are of type SysAddr, as defined at the start of 2236775763aSDoug Thompson * section 3.4.4 (p. 70). They are the lowest and highest physical addresses 2246775763aSDoug Thompson * in the address range they represent. 2256775763aSDoug Thompson */ 2266775763aSDoug Thompson static void amd64_get_base_and_limit(struct amd64_pvt *pvt, int node_id, 2276775763aSDoug Thompson u64 *base, u64 *limit) 2286775763aSDoug Thompson { 2296775763aSDoug Thompson *base = pvt->dram_base[node_id]; 2306775763aSDoug Thompson *limit = pvt->dram_limit[node_id]; 2316775763aSDoug Thompson } 2326775763aSDoug Thompson 2336775763aSDoug Thompson /* 2346775763aSDoug Thompson * Return 1 if the SysAddr given by sys_addr matches the base/limit associated 2356775763aSDoug Thompson * with node_id 2366775763aSDoug Thompson */ 2376775763aSDoug Thompson static int amd64_base_limit_match(struct amd64_pvt *pvt, 2386775763aSDoug Thompson u64 sys_addr, int node_id) 2396775763aSDoug Thompson { 2406775763aSDoug Thompson u64 base, limit, addr; 2416775763aSDoug Thompson 2426775763aSDoug Thompson amd64_get_base_and_limit(pvt, node_id, &base, &limit); 2436775763aSDoug Thompson 2446775763aSDoug Thompson /* The K8 treats this as a 40-bit value. However, bits 63-40 will be 2456775763aSDoug Thompson * all ones if the most significant implemented address bit is 1. 2466775763aSDoug Thompson * Here we discard bits 63-40. See section 3.4.2 of AMD publication 2476775763aSDoug Thompson * 24592: AMD x86-64 Architecture Programmer's Manual Volume 1 2486775763aSDoug Thompson * Application Programming. 2496775763aSDoug Thompson */ 2506775763aSDoug Thompson addr = sys_addr & 0x000000ffffffffffull; 2516775763aSDoug Thompson 2526775763aSDoug Thompson return (addr >= base) && (addr <= limit); 2536775763aSDoug Thompson } 2546775763aSDoug Thompson 2556775763aSDoug Thompson /* 2566775763aSDoug Thompson * Attempt to map a SysAddr to a node. On success, return a pointer to the 2576775763aSDoug Thompson * mem_ctl_info structure for the node that the SysAddr maps to. 2586775763aSDoug Thompson * 2596775763aSDoug Thompson * On failure, return NULL. 2606775763aSDoug Thompson */ 2616775763aSDoug Thompson static struct mem_ctl_info *find_mc_by_sys_addr(struct mem_ctl_info *mci, 2626775763aSDoug Thompson u64 sys_addr) 2636775763aSDoug Thompson { 2646775763aSDoug Thompson struct amd64_pvt *pvt; 2656775763aSDoug Thompson int node_id; 2666775763aSDoug Thompson u32 intlv_en, bits; 2676775763aSDoug Thompson 2686775763aSDoug Thompson /* 2696775763aSDoug Thompson * Here we use the DRAM Base (section 3.4.4.1) and DRAM Limit (section 2706775763aSDoug Thompson * 3.4.4.2) registers to map the SysAddr to a node ID. 2716775763aSDoug Thompson */ 2726775763aSDoug Thompson pvt = mci->pvt_info; 2736775763aSDoug Thompson 2746775763aSDoug Thompson /* 2756775763aSDoug Thompson * The value of this field should be the same for all DRAM Base 2766775763aSDoug Thompson * registers. Therefore we arbitrarily choose to read it from the 2776775763aSDoug Thompson * register for node 0. 2786775763aSDoug Thompson */ 2796775763aSDoug Thompson intlv_en = pvt->dram_IntlvEn[0]; 2806775763aSDoug Thompson 2816775763aSDoug Thompson if (intlv_en == 0) { 2826775763aSDoug Thompson for (node_id = 0; ; ) { 2836775763aSDoug Thompson if (amd64_base_limit_match(pvt, sys_addr, node_id)) 2846775763aSDoug Thompson break; 2856775763aSDoug Thompson 2866775763aSDoug Thompson if (++node_id >= DRAM_REG_COUNT) 2876775763aSDoug Thompson goto err_no_match; 2886775763aSDoug Thompson } 2896775763aSDoug Thompson goto found; 2906775763aSDoug Thompson } 2916775763aSDoug Thompson 2926775763aSDoug Thompson if (unlikely((intlv_en != (0x01 << 8)) && 2936775763aSDoug Thompson (intlv_en != (0x03 << 8)) && 2946775763aSDoug Thompson (intlv_en != (0x07 << 8)))) { 2956775763aSDoug Thompson amd64_printk(KERN_WARNING, "junk value of 0x%x extracted from " 2966775763aSDoug Thompson "IntlvEn field of DRAM Base Register for node 0: " 2976775763aSDoug Thompson "This probably indicates a BIOS bug.\n", intlv_en); 2986775763aSDoug Thompson return NULL; 2996775763aSDoug Thompson } 3006775763aSDoug Thompson 3016775763aSDoug Thompson bits = (((u32) sys_addr) >> 12) & intlv_en; 3026775763aSDoug Thompson 3036775763aSDoug Thompson for (node_id = 0; ; ) { 3046775763aSDoug Thompson if ((pvt->dram_limit[node_id] & intlv_en) == bits) 3056775763aSDoug Thompson break; /* intlv_sel field matches */ 3066775763aSDoug Thompson 3076775763aSDoug Thompson if (++node_id >= DRAM_REG_COUNT) 3086775763aSDoug Thompson goto err_no_match; 3096775763aSDoug Thompson } 3106775763aSDoug Thompson 3116775763aSDoug Thompson /* sanity test for sys_addr */ 3126775763aSDoug Thompson if (unlikely(!amd64_base_limit_match(pvt, sys_addr, node_id))) { 3136775763aSDoug Thompson amd64_printk(KERN_WARNING, 3146775763aSDoug Thompson "%s(): sys_addr 0x%lx falls outside base/limit " 3156775763aSDoug Thompson "address range for node %d with node interleaving " 3166775763aSDoug Thompson "enabled.\n", __func__, (unsigned long)sys_addr, 3176775763aSDoug Thompson node_id); 3186775763aSDoug Thompson return NULL; 3196775763aSDoug Thompson } 3206775763aSDoug Thompson 3216775763aSDoug Thompson found: 3226775763aSDoug Thompson return edac_mc_find(node_id); 3236775763aSDoug Thompson 3246775763aSDoug Thompson err_no_match: 3256775763aSDoug Thompson debugf2("sys_addr 0x%lx doesn't match any node\n", 3266775763aSDoug Thompson (unsigned long)sys_addr); 3276775763aSDoug Thompson 3286775763aSDoug Thompson return NULL; 3296775763aSDoug Thompson } 330e2ce7255SDoug Thompson 331e2ce7255SDoug Thompson /* 332e2ce7255SDoug Thompson * Extract the DRAM CS base address from selected csrow register. 333e2ce7255SDoug Thompson */ 334e2ce7255SDoug Thompson static u64 base_from_dct_base(struct amd64_pvt *pvt, int csrow) 335e2ce7255SDoug Thompson { 336e2ce7255SDoug Thompson return ((u64) (amd64_get_dct_base(pvt, 0, csrow) & pvt->dcsb_base)) << 337e2ce7255SDoug Thompson pvt->dcs_shift; 338e2ce7255SDoug Thompson } 339e2ce7255SDoug Thompson 340e2ce7255SDoug Thompson /* 341e2ce7255SDoug Thompson * Extract the mask from the dcsb0[csrow] entry in a CPU revision-specific way. 342e2ce7255SDoug Thompson */ 343e2ce7255SDoug Thompson static u64 mask_from_dct_mask(struct amd64_pvt *pvt, int csrow) 344e2ce7255SDoug Thompson { 345e2ce7255SDoug Thompson u64 dcsm_bits, other_bits; 346e2ce7255SDoug Thompson u64 mask; 347e2ce7255SDoug Thompson 348e2ce7255SDoug Thompson /* Extract bits from DRAM CS Mask. */ 349e2ce7255SDoug Thompson dcsm_bits = amd64_get_dct_mask(pvt, 0, csrow) & pvt->dcsm_mask; 350e2ce7255SDoug Thompson 351e2ce7255SDoug Thompson other_bits = pvt->dcsm_mask; 352e2ce7255SDoug Thompson other_bits = ~(other_bits << pvt->dcs_shift); 353e2ce7255SDoug Thompson 354e2ce7255SDoug Thompson /* 355e2ce7255SDoug Thompson * The extracted bits from DCSM belong in the spaces represented by 356e2ce7255SDoug Thompson * the cleared bits in other_bits. 357e2ce7255SDoug Thompson */ 358e2ce7255SDoug Thompson mask = (dcsm_bits << pvt->dcs_shift) | other_bits; 359e2ce7255SDoug Thompson 360e2ce7255SDoug Thompson return mask; 361e2ce7255SDoug Thompson } 362e2ce7255SDoug Thompson 363e2ce7255SDoug Thompson /* 364e2ce7255SDoug Thompson * @input_addr is an InputAddr associated with the node given by mci. Return the 365e2ce7255SDoug Thompson * csrow that input_addr maps to, or -1 on failure (no csrow claims input_addr). 366e2ce7255SDoug Thompson */ 367e2ce7255SDoug Thompson static int input_addr_to_csrow(struct mem_ctl_info *mci, u64 input_addr) 368e2ce7255SDoug Thompson { 369e2ce7255SDoug Thompson struct amd64_pvt *pvt; 370e2ce7255SDoug Thompson int csrow; 371e2ce7255SDoug Thompson u64 base, mask; 372e2ce7255SDoug Thompson 373e2ce7255SDoug Thompson pvt = mci->pvt_info; 374e2ce7255SDoug Thompson 375e2ce7255SDoug Thompson /* 376e2ce7255SDoug Thompson * Here we use the DRAM CS Base and DRAM CS Mask registers. For each CS 377e2ce7255SDoug Thompson * base/mask register pair, test the condition shown near the start of 378e2ce7255SDoug Thompson * section 3.5.4 (p. 84, BKDG #26094, K8, revA-E). 379e2ce7255SDoug Thompson */ 380e2ce7255SDoug Thompson for (csrow = 0; csrow < CHIPSELECT_COUNT; csrow++) { 381e2ce7255SDoug Thompson 382e2ce7255SDoug Thompson /* This DRAM chip select is disabled on this node */ 383e2ce7255SDoug Thompson if ((pvt->dcsb0[csrow] & K8_DCSB_CS_ENABLE) == 0) 384e2ce7255SDoug Thompson continue; 385e2ce7255SDoug Thompson 386e2ce7255SDoug Thompson base = base_from_dct_base(pvt, csrow); 387e2ce7255SDoug Thompson mask = ~mask_from_dct_mask(pvt, csrow); 388e2ce7255SDoug Thompson 389e2ce7255SDoug Thompson if ((input_addr & mask) == (base & mask)) { 390e2ce7255SDoug Thompson debugf2("InputAddr 0x%lx matches csrow %d (node %d)\n", 391e2ce7255SDoug Thompson (unsigned long)input_addr, csrow, 392e2ce7255SDoug Thompson pvt->mc_node_id); 393e2ce7255SDoug Thompson 394e2ce7255SDoug Thompson return csrow; 395e2ce7255SDoug Thompson } 396e2ce7255SDoug Thompson } 397e2ce7255SDoug Thompson 398e2ce7255SDoug Thompson debugf2("no matching csrow for InputAddr 0x%lx (MC node %d)\n", 399e2ce7255SDoug Thompson (unsigned long)input_addr, pvt->mc_node_id); 400e2ce7255SDoug Thompson 401e2ce7255SDoug Thompson return -1; 402e2ce7255SDoug Thompson } 403e2ce7255SDoug Thompson 404e2ce7255SDoug Thompson /* 405e2ce7255SDoug Thompson * Return the base value defined by the DRAM Base register for the node 406e2ce7255SDoug Thompson * represented by mci. This function returns the full 40-bit value despite the 407e2ce7255SDoug Thompson * fact that the register only stores bits 39-24 of the value. See section 408e2ce7255SDoug Thompson * 3.4.4.1 (BKDG #26094, K8, revA-E) 409e2ce7255SDoug Thompson */ 410e2ce7255SDoug Thompson static inline u64 get_dram_base(struct mem_ctl_info *mci) 411e2ce7255SDoug Thompson { 412e2ce7255SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 413e2ce7255SDoug Thompson 414e2ce7255SDoug Thompson return pvt->dram_base[pvt->mc_node_id]; 415e2ce7255SDoug Thompson } 416e2ce7255SDoug Thompson 417e2ce7255SDoug Thompson /* 418e2ce7255SDoug Thompson * Obtain info from the DRAM Hole Address Register (section 3.4.8, pub #26094) 419e2ce7255SDoug Thompson * for the node represented by mci. Info is passed back in *hole_base, 420e2ce7255SDoug Thompson * *hole_offset, and *hole_size. Function returns 0 if info is valid or 1 if 421e2ce7255SDoug Thompson * info is invalid. Info may be invalid for either of the following reasons: 422e2ce7255SDoug Thompson * 423e2ce7255SDoug Thompson * - The revision of the node is not E or greater. In this case, the DRAM Hole 424e2ce7255SDoug Thompson * Address Register does not exist. 425e2ce7255SDoug Thompson * 426e2ce7255SDoug Thompson * - The DramHoleValid bit is cleared in the DRAM Hole Address Register, 427e2ce7255SDoug Thompson * indicating that its contents are not valid. 428e2ce7255SDoug Thompson * 429e2ce7255SDoug Thompson * The values passed back in *hole_base, *hole_offset, and *hole_size are 430e2ce7255SDoug Thompson * complete 32-bit values despite the fact that the bitfields in the DHAR 431e2ce7255SDoug Thompson * only represent bits 31-24 of the base and offset values. 432e2ce7255SDoug Thompson */ 433e2ce7255SDoug Thompson int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, 434e2ce7255SDoug Thompson u64 *hole_offset, u64 *hole_size) 435e2ce7255SDoug Thompson { 436e2ce7255SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 437e2ce7255SDoug Thompson u64 base; 438e2ce7255SDoug Thompson 439e2ce7255SDoug Thompson /* only revE and later have the DRAM Hole Address Register */ 440e2ce7255SDoug Thompson if (boot_cpu_data.x86 == 0xf && pvt->ext_model < OPTERON_CPU_REV_E) { 441e2ce7255SDoug Thompson debugf1(" revision %d for node %d does not support DHAR\n", 442e2ce7255SDoug Thompson pvt->ext_model, pvt->mc_node_id); 443e2ce7255SDoug Thompson return 1; 444e2ce7255SDoug Thompson } 445e2ce7255SDoug Thompson 446e2ce7255SDoug Thompson /* only valid for Fam10h */ 447e2ce7255SDoug Thompson if (boot_cpu_data.x86 == 0x10 && 448e2ce7255SDoug Thompson (pvt->dhar & F10_DRAM_MEM_HOIST_VALID) == 0) { 449e2ce7255SDoug Thompson debugf1(" Dram Memory Hoisting is DISABLED on this system\n"); 450e2ce7255SDoug Thompson return 1; 451e2ce7255SDoug Thompson } 452e2ce7255SDoug Thompson 453e2ce7255SDoug Thompson if ((pvt->dhar & DHAR_VALID) == 0) { 454e2ce7255SDoug Thompson debugf1(" Dram Memory Hoisting is DISABLED on this node %d\n", 455e2ce7255SDoug Thompson pvt->mc_node_id); 456e2ce7255SDoug Thompson return 1; 457e2ce7255SDoug Thompson } 458e2ce7255SDoug Thompson 459e2ce7255SDoug Thompson /* This node has Memory Hoisting */ 460e2ce7255SDoug Thompson 461e2ce7255SDoug Thompson /* +------------------+--------------------+--------------------+----- 462e2ce7255SDoug Thompson * | memory | DRAM hole | relocated | 463e2ce7255SDoug Thompson * | [0, (x - 1)] | [x, 0xffffffff] | addresses from | 464e2ce7255SDoug Thompson * | | | DRAM hole | 465e2ce7255SDoug Thompson * | | | [0x100000000, | 466e2ce7255SDoug Thompson * | | | (0x100000000+ | 467e2ce7255SDoug Thompson * | | | (0xffffffff-x))] | 468e2ce7255SDoug Thompson * +------------------+--------------------+--------------------+----- 469e2ce7255SDoug Thompson * 470e2ce7255SDoug Thompson * Above is a diagram of physical memory showing the DRAM hole and the 471e2ce7255SDoug Thompson * relocated addresses from the DRAM hole. As shown, the DRAM hole 472e2ce7255SDoug Thompson * starts at address x (the base address) and extends through address 473e2ce7255SDoug Thompson * 0xffffffff. The DRAM Hole Address Register (DHAR) relocates the 474e2ce7255SDoug Thompson * addresses in the hole so that they start at 0x100000000. 475e2ce7255SDoug Thompson */ 476e2ce7255SDoug Thompson 477e2ce7255SDoug Thompson base = dhar_base(pvt->dhar); 478e2ce7255SDoug Thompson 479e2ce7255SDoug Thompson *hole_base = base; 480e2ce7255SDoug Thompson *hole_size = (0x1ull << 32) - base; 481e2ce7255SDoug Thompson 482e2ce7255SDoug Thompson if (boot_cpu_data.x86 > 0xf) 483e2ce7255SDoug Thompson *hole_offset = f10_dhar_offset(pvt->dhar); 484e2ce7255SDoug Thompson else 485e2ce7255SDoug Thompson *hole_offset = k8_dhar_offset(pvt->dhar); 486e2ce7255SDoug Thompson 487e2ce7255SDoug Thompson debugf1(" DHAR info for node %d base 0x%lx offset 0x%lx size 0x%lx\n", 488e2ce7255SDoug Thompson pvt->mc_node_id, (unsigned long)*hole_base, 489e2ce7255SDoug Thompson (unsigned long)*hole_offset, (unsigned long)*hole_size); 490e2ce7255SDoug Thompson 491e2ce7255SDoug Thompson return 0; 492e2ce7255SDoug Thompson } 493e2ce7255SDoug Thompson EXPORT_SYMBOL_GPL(amd64_get_dram_hole_info); 494e2ce7255SDoug Thompson 49593c2df58SDoug Thompson /* 49693c2df58SDoug Thompson * Return the DramAddr that the SysAddr given by @sys_addr maps to. It is 49793c2df58SDoug Thompson * assumed that sys_addr maps to the node given by mci. 49893c2df58SDoug Thompson * 49993c2df58SDoug Thompson * The first part of section 3.4.4 (p. 70) shows how the DRAM Base (section 50093c2df58SDoug Thompson * 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers are used to translate a 50193c2df58SDoug Thompson * SysAddr to a DramAddr. If the DRAM Hole Address Register (DHAR) is enabled, 50293c2df58SDoug Thompson * then it is also involved in translating a SysAddr to a DramAddr. Sections 50393c2df58SDoug Thompson * 3.4.8 and 3.5.8.2 describe the DHAR and how it is used for memory hoisting. 50493c2df58SDoug Thompson * These parts of the documentation are unclear. I interpret them as follows: 50593c2df58SDoug Thompson * 50693c2df58SDoug Thompson * When node n receives a SysAddr, it processes the SysAddr as follows: 50793c2df58SDoug Thompson * 50893c2df58SDoug Thompson * 1. It extracts the DRAMBase and DRAMLimit values from the DRAM Base and DRAM 50993c2df58SDoug Thompson * Limit registers for node n. If the SysAddr is not within the range 51093c2df58SDoug Thompson * specified by the base and limit values, then node n ignores the Sysaddr 51193c2df58SDoug Thompson * (since it does not map to node n). Otherwise continue to step 2 below. 51293c2df58SDoug Thompson * 51393c2df58SDoug Thompson * 2. If the DramHoleValid bit of the DHAR for node n is clear, the DHAR is 51493c2df58SDoug Thompson * disabled so skip to step 3 below. Otherwise see if the SysAddr is within 51593c2df58SDoug Thompson * the range of relocated addresses (starting at 0x100000000) from the DRAM 51693c2df58SDoug Thompson * hole. If not, skip to step 3 below. Else get the value of the 51793c2df58SDoug Thompson * DramHoleOffset field from the DHAR. To obtain the DramAddr, subtract the 51893c2df58SDoug Thompson * offset defined by this value from the SysAddr. 51993c2df58SDoug Thompson * 52093c2df58SDoug Thompson * 3. Obtain the base address for node n from the DRAMBase field of the DRAM 52193c2df58SDoug Thompson * Base register for node n. To obtain the DramAddr, subtract the base 52293c2df58SDoug Thompson * address from the SysAddr, as shown near the start of section 3.4.4 (p.70). 52393c2df58SDoug Thompson */ 52493c2df58SDoug Thompson static u64 sys_addr_to_dram_addr(struct mem_ctl_info *mci, u64 sys_addr) 52593c2df58SDoug Thompson { 52693c2df58SDoug Thompson u64 dram_base, hole_base, hole_offset, hole_size, dram_addr; 52793c2df58SDoug Thompson int ret = 0; 52893c2df58SDoug Thompson 52993c2df58SDoug Thompson dram_base = get_dram_base(mci); 53093c2df58SDoug Thompson 53193c2df58SDoug Thompson ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, 53293c2df58SDoug Thompson &hole_size); 53393c2df58SDoug Thompson if (!ret) { 53493c2df58SDoug Thompson if ((sys_addr >= (1ull << 32)) && 53593c2df58SDoug Thompson (sys_addr < ((1ull << 32) + hole_size))) { 53693c2df58SDoug Thompson /* use DHAR to translate SysAddr to DramAddr */ 53793c2df58SDoug Thompson dram_addr = sys_addr - hole_offset; 53893c2df58SDoug Thompson 53993c2df58SDoug Thompson debugf2("using DHAR to translate SysAddr 0x%lx to " 54093c2df58SDoug Thompson "DramAddr 0x%lx\n", 54193c2df58SDoug Thompson (unsigned long)sys_addr, 54293c2df58SDoug Thompson (unsigned long)dram_addr); 54393c2df58SDoug Thompson 54493c2df58SDoug Thompson return dram_addr; 54593c2df58SDoug Thompson } 54693c2df58SDoug Thompson } 54793c2df58SDoug Thompson 54893c2df58SDoug Thompson /* 54993c2df58SDoug Thompson * Translate the SysAddr to a DramAddr as shown near the start of 55093c2df58SDoug Thompson * section 3.4.4 (p. 70). Although sys_addr is a 64-bit value, the k8 55193c2df58SDoug Thompson * only deals with 40-bit values. Therefore we discard bits 63-40 of 55293c2df58SDoug Thompson * sys_addr below. If bit 39 of sys_addr is 1 then the bits we 55393c2df58SDoug Thompson * discard are all 1s. Otherwise the bits we discard are all 0s. See 55493c2df58SDoug Thompson * section 3.4.2 of AMD publication 24592: AMD x86-64 Architecture 55593c2df58SDoug Thompson * Programmer's Manual Volume 1 Application Programming. 55693c2df58SDoug Thompson */ 55793c2df58SDoug Thompson dram_addr = (sys_addr & 0xffffffffffull) - dram_base; 55893c2df58SDoug Thompson 55993c2df58SDoug Thompson debugf2("using DRAM Base register to translate SysAddr 0x%lx to " 56093c2df58SDoug Thompson "DramAddr 0x%lx\n", (unsigned long)sys_addr, 56193c2df58SDoug Thompson (unsigned long)dram_addr); 56293c2df58SDoug Thompson return dram_addr; 56393c2df58SDoug Thompson } 56493c2df58SDoug Thompson 56593c2df58SDoug Thompson /* 56693c2df58SDoug Thompson * @intlv_en is the value of the IntlvEn field from a DRAM Base register 56793c2df58SDoug Thompson * (section 3.4.4.1). Return the number of bits from a SysAddr that are used 56893c2df58SDoug Thompson * for node interleaving. 56993c2df58SDoug Thompson */ 57093c2df58SDoug Thompson static int num_node_interleave_bits(unsigned intlv_en) 57193c2df58SDoug Thompson { 57293c2df58SDoug Thompson static const int intlv_shift_table[] = { 0, 1, 0, 2, 0, 0, 0, 3 }; 57393c2df58SDoug Thompson int n; 57493c2df58SDoug Thompson 57593c2df58SDoug Thompson BUG_ON(intlv_en > 7); 57693c2df58SDoug Thompson n = intlv_shift_table[intlv_en]; 57793c2df58SDoug Thompson return n; 57893c2df58SDoug Thompson } 57993c2df58SDoug Thompson 58093c2df58SDoug Thompson /* Translate the DramAddr given by @dram_addr to an InputAddr. */ 58193c2df58SDoug Thompson static u64 dram_addr_to_input_addr(struct mem_ctl_info *mci, u64 dram_addr) 58293c2df58SDoug Thompson { 58393c2df58SDoug Thompson struct amd64_pvt *pvt; 58493c2df58SDoug Thompson int intlv_shift; 58593c2df58SDoug Thompson u64 input_addr; 58693c2df58SDoug Thompson 58793c2df58SDoug Thompson pvt = mci->pvt_info; 58893c2df58SDoug Thompson 58993c2df58SDoug Thompson /* 59093c2df58SDoug Thompson * See the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) 59193c2df58SDoug Thompson * concerning translating a DramAddr to an InputAddr. 59293c2df58SDoug Thompson */ 59393c2df58SDoug Thompson intlv_shift = num_node_interleave_bits(pvt->dram_IntlvEn[0]); 59493c2df58SDoug Thompson input_addr = ((dram_addr >> intlv_shift) & 0xffffff000ull) + 59593c2df58SDoug Thompson (dram_addr & 0xfff); 59693c2df58SDoug Thompson 59793c2df58SDoug Thompson debugf2(" Intlv Shift=%d DramAddr=0x%lx maps to InputAddr=0x%lx\n", 59893c2df58SDoug Thompson intlv_shift, (unsigned long)dram_addr, 59993c2df58SDoug Thompson (unsigned long)input_addr); 60093c2df58SDoug Thompson 60193c2df58SDoug Thompson return input_addr; 60293c2df58SDoug Thompson } 60393c2df58SDoug Thompson 60493c2df58SDoug Thompson /* 60593c2df58SDoug Thompson * Translate the SysAddr represented by @sys_addr to an InputAddr. It is 60693c2df58SDoug Thompson * assumed that @sys_addr maps to the node given by mci. 60793c2df58SDoug Thompson */ 60893c2df58SDoug Thompson static u64 sys_addr_to_input_addr(struct mem_ctl_info *mci, u64 sys_addr) 60993c2df58SDoug Thompson { 61093c2df58SDoug Thompson u64 input_addr; 61193c2df58SDoug Thompson 61293c2df58SDoug Thompson input_addr = 61393c2df58SDoug Thompson dram_addr_to_input_addr(mci, sys_addr_to_dram_addr(mci, sys_addr)); 61493c2df58SDoug Thompson 61593c2df58SDoug Thompson debugf2("SysAdddr 0x%lx translates to InputAddr 0x%lx\n", 61693c2df58SDoug Thompson (unsigned long)sys_addr, (unsigned long)input_addr); 61793c2df58SDoug Thompson 61893c2df58SDoug Thompson return input_addr; 61993c2df58SDoug Thompson } 62093c2df58SDoug Thompson 62193c2df58SDoug Thompson 62293c2df58SDoug Thompson /* 62393c2df58SDoug Thompson * @input_addr is an InputAddr associated with the node represented by mci. 62493c2df58SDoug Thompson * Translate @input_addr to a DramAddr and return the result. 62593c2df58SDoug Thompson */ 62693c2df58SDoug Thompson static u64 input_addr_to_dram_addr(struct mem_ctl_info *mci, u64 input_addr) 62793c2df58SDoug Thompson { 62893c2df58SDoug Thompson struct amd64_pvt *pvt; 62993c2df58SDoug Thompson int node_id, intlv_shift; 63093c2df58SDoug Thompson u64 bits, dram_addr; 63193c2df58SDoug Thompson u32 intlv_sel; 63293c2df58SDoug Thompson 63393c2df58SDoug Thompson /* 63493c2df58SDoug Thompson * Near the start of section 3.4.4 (p. 70, BKDG #26094, K8, revA-E) 63593c2df58SDoug Thompson * shows how to translate a DramAddr to an InputAddr. Here we reverse 63693c2df58SDoug Thompson * this procedure. When translating from a DramAddr to an InputAddr, the 63793c2df58SDoug Thompson * bits used for node interleaving are discarded. Here we recover these 63893c2df58SDoug Thompson * bits from the IntlvSel field of the DRAM Limit register (section 63993c2df58SDoug Thompson * 3.4.4.2) for the node that input_addr is associated with. 64093c2df58SDoug Thompson */ 64193c2df58SDoug Thompson pvt = mci->pvt_info; 64293c2df58SDoug Thompson node_id = pvt->mc_node_id; 64393c2df58SDoug Thompson BUG_ON((node_id < 0) || (node_id > 7)); 64493c2df58SDoug Thompson 64593c2df58SDoug Thompson intlv_shift = num_node_interleave_bits(pvt->dram_IntlvEn[0]); 64693c2df58SDoug Thompson 64793c2df58SDoug Thompson if (intlv_shift == 0) { 64893c2df58SDoug Thompson debugf1(" InputAddr 0x%lx translates to DramAddr of " 64993c2df58SDoug Thompson "same value\n", (unsigned long)input_addr); 65093c2df58SDoug Thompson 65193c2df58SDoug Thompson return input_addr; 65293c2df58SDoug Thompson } 65393c2df58SDoug Thompson 65493c2df58SDoug Thompson bits = ((input_addr & 0xffffff000ull) << intlv_shift) + 65593c2df58SDoug Thompson (input_addr & 0xfff); 65693c2df58SDoug Thompson 65793c2df58SDoug Thompson intlv_sel = pvt->dram_IntlvSel[node_id] & ((1 << intlv_shift) - 1); 65893c2df58SDoug Thompson dram_addr = bits + (intlv_sel << 12); 65993c2df58SDoug Thompson 66093c2df58SDoug Thompson debugf1("InputAddr 0x%lx translates to DramAddr 0x%lx " 66193c2df58SDoug Thompson "(%d node interleave bits)\n", (unsigned long)input_addr, 66293c2df58SDoug Thompson (unsigned long)dram_addr, intlv_shift); 66393c2df58SDoug Thompson 66493c2df58SDoug Thompson return dram_addr; 66593c2df58SDoug Thompson } 66693c2df58SDoug Thompson 66793c2df58SDoug Thompson /* 66893c2df58SDoug Thompson * @dram_addr is a DramAddr that maps to the node represented by mci. Convert 66993c2df58SDoug Thompson * @dram_addr to a SysAddr. 67093c2df58SDoug Thompson */ 67193c2df58SDoug Thompson static u64 dram_addr_to_sys_addr(struct mem_ctl_info *mci, u64 dram_addr) 67293c2df58SDoug Thompson { 67393c2df58SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 67493c2df58SDoug Thompson u64 hole_base, hole_offset, hole_size, base, limit, sys_addr; 67593c2df58SDoug Thompson int ret = 0; 67693c2df58SDoug Thompson 67793c2df58SDoug Thompson ret = amd64_get_dram_hole_info(mci, &hole_base, &hole_offset, 67893c2df58SDoug Thompson &hole_size); 67993c2df58SDoug Thompson if (!ret) { 68093c2df58SDoug Thompson if ((dram_addr >= hole_base) && 68193c2df58SDoug Thompson (dram_addr < (hole_base + hole_size))) { 68293c2df58SDoug Thompson sys_addr = dram_addr + hole_offset; 68393c2df58SDoug Thompson 68493c2df58SDoug Thompson debugf1("using DHAR to translate DramAddr 0x%lx to " 68593c2df58SDoug Thompson "SysAddr 0x%lx\n", (unsigned long)dram_addr, 68693c2df58SDoug Thompson (unsigned long)sys_addr); 68793c2df58SDoug Thompson 68893c2df58SDoug Thompson return sys_addr; 68993c2df58SDoug Thompson } 69093c2df58SDoug Thompson } 69193c2df58SDoug Thompson 69293c2df58SDoug Thompson amd64_get_base_and_limit(pvt, pvt->mc_node_id, &base, &limit); 69393c2df58SDoug Thompson sys_addr = dram_addr + base; 69493c2df58SDoug Thompson 69593c2df58SDoug Thompson /* 69693c2df58SDoug Thompson * The sys_addr we have computed up to this point is a 40-bit value 69793c2df58SDoug Thompson * because the k8 deals with 40-bit values. However, the value we are 69893c2df58SDoug Thompson * supposed to return is a full 64-bit physical address. The AMD 69993c2df58SDoug Thompson * x86-64 architecture specifies that the most significant implemented 70093c2df58SDoug Thompson * address bit through bit 63 of a physical address must be either all 70193c2df58SDoug Thompson * 0s or all 1s. Therefore we sign-extend the 40-bit sys_addr to a 70293c2df58SDoug Thompson * 64-bit value below. See section 3.4.2 of AMD publication 24592: 70393c2df58SDoug Thompson * AMD x86-64 Architecture Programmer's Manual Volume 1 Application 70493c2df58SDoug Thompson * Programming. 70593c2df58SDoug Thompson */ 70693c2df58SDoug Thompson sys_addr |= ~((sys_addr & (1ull << 39)) - 1); 70793c2df58SDoug Thompson 70893c2df58SDoug Thompson debugf1(" Node %d, DramAddr 0x%lx to SysAddr 0x%lx\n", 70993c2df58SDoug Thompson pvt->mc_node_id, (unsigned long)dram_addr, 71093c2df58SDoug Thompson (unsigned long)sys_addr); 71193c2df58SDoug Thompson 71293c2df58SDoug Thompson return sys_addr; 71393c2df58SDoug Thompson } 71493c2df58SDoug Thompson 71593c2df58SDoug Thompson /* 71693c2df58SDoug Thompson * @input_addr is an InputAddr associated with the node given by mci. Translate 71793c2df58SDoug Thompson * @input_addr to a SysAddr. 71893c2df58SDoug Thompson */ 71993c2df58SDoug Thompson static inline u64 input_addr_to_sys_addr(struct mem_ctl_info *mci, 72093c2df58SDoug Thompson u64 input_addr) 72193c2df58SDoug Thompson { 72293c2df58SDoug Thompson return dram_addr_to_sys_addr(mci, 72393c2df58SDoug Thompson input_addr_to_dram_addr(mci, input_addr)); 72493c2df58SDoug Thompson } 72593c2df58SDoug Thompson 72693c2df58SDoug Thompson /* 72793c2df58SDoug Thompson * Find the minimum and maximum InputAddr values that map to the given @csrow. 72893c2df58SDoug Thompson * Pass back these values in *input_addr_min and *input_addr_max. 72993c2df58SDoug Thompson */ 73093c2df58SDoug Thompson static void find_csrow_limits(struct mem_ctl_info *mci, int csrow, 73193c2df58SDoug Thompson u64 *input_addr_min, u64 *input_addr_max) 73293c2df58SDoug Thompson { 73393c2df58SDoug Thompson struct amd64_pvt *pvt; 73493c2df58SDoug Thompson u64 base, mask; 73593c2df58SDoug Thompson 73693c2df58SDoug Thompson pvt = mci->pvt_info; 73793c2df58SDoug Thompson BUG_ON((csrow < 0) || (csrow >= CHIPSELECT_COUNT)); 73893c2df58SDoug Thompson 73993c2df58SDoug Thompson base = base_from_dct_base(pvt, csrow); 74093c2df58SDoug Thompson mask = mask_from_dct_mask(pvt, csrow); 74193c2df58SDoug Thompson 74293c2df58SDoug Thompson *input_addr_min = base & ~mask; 74393c2df58SDoug Thompson *input_addr_max = base | mask | pvt->dcs_mask_notused; 74493c2df58SDoug Thompson } 74593c2df58SDoug Thompson 74693c2df58SDoug Thompson /* 74793c2df58SDoug Thompson * Extract error address from MCA NB Address Low (section 3.6.4.5) and MCA NB 74893c2df58SDoug Thompson * Address High (section 3.6.4.6) register values and return the result. Address 74993c2df58SDoug Thompson * is located in the info structure (nbeah and nbeal), the encoding is device 75093c2df58SDoug Thompson * specific. 75193c2df58SDoug Thompson */ 75293c2df58SDoug Thompson static u64 extract_error_address(struct mem_ctl_info *mci, 753ef44cc4cSBorislav Petkov struct err_regs *info) 75493c2df58SDoug Thompson { 75593c2df58SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 75693c2df58SDoug Thompson 75793c2df58SDoug Thompson return pvt->ops->get_error_address(mci, info); 75893c2df58SDoug Thompson } 75993c2df58SDoug Thompson 76093c2df58SDoug Thompson 76193c2df58SDoug Thompson /* Map the Error address to a PAGE and PAGE OFFSET. */ 76293c2df58SDoug Thompson static inline void error_address_to_page_and_offset(u64 error_address, 76393c2df58SDoug Thompson u32 *page, u32 *offset) 76493c2df58SDoug Thompson { 76593c2df58SDoug Thompson *page = (u32) (error_address >> PAGE_SHIFT); 76693c2df58SDoug Thompson *offset = ((u32) error_address) & ~PAGE_MASK; 76793c2df58SDoug Thompson } 76893c2df58SDoug Thompson 76993c2df58SDoug Thompson /* 77093c2df58SDoug Thompson * @sys_addr is an error address (a SysAddr) extracted from the MCA NB Address 77193c2df58SDoug Thompson * Low (section 3.6.4.5) and MCA NB Address High (section 3.6.4.6) registers 77293c2df58SDoug Thompson * of a node that detected an ECC memory error. mci represents the node that 77393c2df58SDoug Thompson * the error address maps to (possibly different from the node that detected 77493c2df58SDoug Thompson * the error). Return the number of the csrow that sys_addr maps to, or -1 on 77593c2df58SDoug Thompson * error. 77693c2df58SDoug Thompson */ 77793c2df58SDoug Thompson static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) 77893c2df58SDoug Thompson { 77993c2df58SDoug Thompson int csrow; 78093c2df58SDoug Thompson 78193c2df58SDoug Thompson csrow = input_addr_to_csrow(mci, sys_addr_to_input_addr(mci, sys_addr)); 78293c2df58SDoug Thompson 78393c2df58SDoug Thompson if (csrow == -1) 78493c2df58SDoug Thompson amd64_mc_printk(mci, KERN_ERR, 78593c2df58SDoug Thompson "Failed to translate InputAddr to csrow for " 78693c2df58SDoug Thompson "address 0x%lx\n", (unsigned long)sys_addr); 78793c2df58SDoug Thompson return csrow; 78893c2df58SDoug Thompson } 789e2ce7255SDoug Thompson 7902da11654SDoug Thompson static int get_channel_from_ecc_syndrome(unsigned short syndrome); 7912da11654SDoug Thompson 7922da11654SDoug Thompson static void amd64_cpu_display_info(struct amd64_pvt *pvt) 7932da11654SDoug Thompson { 7942da11654SDoug Thompson if (boot_cpu_data.x86 == 0x11) 7952da11654SDoug Thompson edac_printk(KERN_DEBUG, EDAC_MC, "F11h CPU detected\n"); 7962da11654SDoug Thompson else if (boot_cpu_data.x86 == 0x10) 7972da11654SDoug Thompson edac_printk(KERN_DEBUG, EDAC_MC, "F10h CPU detected\n"); 7982da11654SDoug Thompson else if (boot_cpu_data.x86 == 0xf) 7992da11654SDoug Thompson edac_printk(KERN_DEBUG, EDAC_MC, "%s detected\n", 8002da11654SDoug Thompson (pvt->ext_model >= OPTERON_CPU_REV_F) ? 8012da11654SDoug Thompson "Rev F or later" : "Rev E or earlier"); 8022da11654SDoug Thompson else 8032da11654SDoug Thompson /* we'll hardly ever ever get here */ 8042da11654SDoug Thompson edac_printk(KERN_ERR, EDAC_MC, "Unknown cpu!\n"); 8052da11654SDoug Thompson } 8062da11654SDoug Thompson 8072da11654SDoug Thompson /* 8082da11654SDoug Thompson * Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs 8092da11654SDoug Thompson * are ECC capable. 8102da11654SDoug Thompson */ 8112da11654SDoug Thompson static enum edac_type amd64_determine_edac_cap(struct amd64_pvt *pvt) 8122da11654SDoug Thompson { 8132da11654SDoug Thompson int bit; 814584fcff4SBorislav Petkov enum dev_type edac_cap = EDAC_FLAG_NONE; 8152da11654SDoug Thompson 8162da11654SDoug Thompson bit = (boot_cpu_data.x86 > 0xf || pvt->ext_model >= OPTERON_CPU_REV_F) 8172da11654SDoug Thompson ? 19 8182da11654SDoug Thompson : 17; 8192da11654SDoug Thompson 820584fcff4SBorislav Petkov if (pvt->dclr0 & BIT(bit)) 8212da11654SDoug Thompson edac_cap = EDAC_FLAG_SECDED; 8222da11654SDoug Thompson 8232da11654SDoug Thompson return edac_cap; 8242da11654SDoug Thompson } 8252da11654SDoug Thompson 8262da11654SDoug Thompson 8272da11654SDoug Thompson static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt, 8282da11654SDoug Thompson int ganged); 8292da11654SDoug Thompson 8302da11654SDoug Thompson /* Display and decode various NB registers for debug purposes. */ 8312da11654SDoug Thompson static void amd64_dump_misc_regs(struct amd64_pvt *pvt) 8322da11654SDoug Thompson { 8332da11654SDoug Thompson int ganged; 8342da11654SDoug Thompson 8352da11654SDoug Thompson debugf1(" nbcap:0x%8.08x DctDualCap=%s DualNode=%s 8-Node=%s\n", 8362da11654SDoug Thompson pvt->nbcap, 8372da11654SDoug Thompson (pvt->nbcap & K8_NBCAP_DCT_DUAL) ? "True" : "False", 8382da11654SDoug Thompson (pvt->nbcap & K8_NBCAP_DUAL_NODE) ? "True" : "False", 8392da11654SDoug Thompson (pvt->nbcap & K8_NBCAP_8_NODE) ? "True" : "False"); 8402da11654SDoug Thompson debugf1(" ECC Capable=%s ChipKill Capable=%s\n", 8412da11654SDoug Thompson (pvt->nbcap & K8_NBCAP_SECDED) ? "True" : "False", 8422da11654SDoug Thompson (pvt->nbcap & K8_NBCAP_CHIPKILL) ? "True" : "False"); 8432da11654SDoug Thompson debugf1(" DramCfg0-low=0x%08x DIMM-ECC=%s Parity=%s Width=%s\n", 8442da11654SDoug Thompson pvt->dclr0, 8452da11654SDoug Thompson (pvt->dclr0 & BIT(19)) ? "Enabled" : "Disabled", 8462da11654SDoug Thompson (pvt->dclr0 & BIT(8)) ? "Enabled" : "Disabled", 8472da11654SDoug Thompson (pvt->dclr0 & BIT(11)) ? "128b" : "64b"); 8482da11654SDoug Thompson debugf1(" DIMM x4 Present: L0=%s L1=%s L2=%s L3=%s DIMM Type=%s\n", 8492da11654SDoug Thompson (pvt->dclr0 & BIT(12)) ? "Y" : "N", 8502da11654SDoug Thompson (pvt->dclr0 & BIT(13)) ? "Y" : "N", 8512da11654SDoug Thompson (pvt->dclr0 & BIT(14)) ? "Y" : "N", 8522da11654SDoug Thompson (pvt->dclr0 & BIT(15)) ? "Y" : "N", 8532da11654SDoug Thompson (pvt->dclr0 & BIT(16)) ? "UN-Buffered" : "Buffered"); 8542da11654SDoug Thompson 8552da11654SDoug Thompson 8562da11654SDoug Thompson debugf1(" online-spare: 0x%8.08x\n", pvt->online_spare); 8572da11654SDoug Thompson 8582da11654SDoug Thompson if (boot_cpu_data.x86 == 0xf) { 8592da11654SDoug Thompson debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n", 8602da11654SDoug Thompson pvt->dhar, dhar_base(pvt->dhar), 8612da11654SDoug Thompson k8_dhar_offset(pvt->dhar)); 8622da11654SDoug Thompson debugf1(" DramHoleValid=%s\n", 8632da11654SDoug Thompson (pvt->dhar & DHAR_VALID) ? "True" : "False"); 8642da11654SDoug Thompson 8652da11654SDoug Thompson debugf1(" dbam-dkt: 0x%8.08x\n", pvt->dbam0); 8662da11654SDoug Thompson 8672da11654SDoug Thompson /* everything below this point is Fam10h and above */ 8682da11654SDoug Thompson return; 8692da11654SDoug Thompson 8702da11654SDoug Thompson } else { 8712da11654SDoug Thompson debugf1(" dhar: 0x%8.08x Base=0x%08x Offset=0x%08x\n", 8722da11654SDoug Thompson pvt->dhar, dhar_base(pvt->dhar), 8732da11654SDoug Thompson f10_dhar_offset(pvt->dhar)); 8742da11654SDoug Thompson debugf1(" DramMemHoistValid=%s DramHoleValid=%s\n", 8752da11654SDoug Thompson (pvt->dhar & F10_DRAM_MEM_HOIST_VALID) ? 8762da11654SDoug Thompson "True" : "False", 8772da11654SDoug Thompson (pvt->dhar & DHAR_VALID) ? 8782da11654SDoug Thompson "True" : "False"); 8792da11654SDoug Thompson } 8802da11654SDoug Thompson 8812da11654SDoug Thompson /* Only if NOT ganged does dcl1 have valid info */ 8822da11654SDoug Thompson if (!dct_ganging_enabled(pvt)) { 8832da11654SDoug Thompson debugf1(" DramCfg1-low=0x%08x DIMM-ECC=%s Parity=%s " 8842da11654SDoug Thompson "Width=%s\n", pvt->dclr1, 8852da11654SDoug Thompson (pvt->dclr1 & BIT(19)) ? "Enabled" : "Disabled", 8862da11654SDoug Thompson (pvt->dclr1 & BIT(8)) ? "Enabled" : "Disabled", 8872da11654SDoug Thompson (pvt->dclr1 & BIT(11)) ? "128b" : "64b"); 8882da11654SDoug Thompson debugf1(" DIMM x4 Present: L0=%s L1=%s L2=%s L3=%s " 8892da11654SDoug Thompson "DIMM Type=%s\n", 8902da11654SDoug Thompson (pvt->dclr1 & BIT(12)) ? "Y" : "N", 8912da11654SDoug Thompson (pvt->dclr1 & BIT(13)) ? "Y" : "N", 8922da11654SDoug Thompson (pvt->dclr1 & BIT(14)) ? "Y" : "N", 8932da11654SDoug Thompson (pvt->dclr1 & BIT(15)) ? "Y" : "N", 8942da11654SDoug Thompson (pvt->dclr1 & BIT(16)) ? "UN-Buffered" : "Buffered"); 8952da11654SDoug Thompson } 8962da11654SDoug Thompson 8972da11654SDoug Thompson /* 8982da11654SDoug Thompson * Determine if ganged and then dump memory sizes for first controller, 8992da11654SDoug Thompson * and if NOT ganged dump info for 2nd controller. 9002da11654SDoug Thompson */ 9012da11654SDoug Thompson ganged = dct_ganging_enabled(pvt); 9022da11654SDoug Thompson 9032da11654SDoug Thompson f10_debug_display_dimm_sizes(0, pvt, ganged); 9042da11654SDoug Thompson 9052da11654SDoug Thompson if (!ganged) 9062da11654SDoug Thompson f10_debug_display_dimm_sizes(1, pvt, ganged); 9072da11654SDoug Thompson } 9082da11654SDoug Thompson 9092da11654SDoug Thompson /* Read in both of DBAM registers */ 9102da11654SDoug Thompson static void amd64_read_dbam_reg(struct amd64_pvt *pvt) 9112da11654SDoug Thompson { 9122da11654SDoug Thompson int err = 0; 9132da11654SDoug Thompson unsigned int reg; 9142da11654SDoug Thompson 9152da11654SDoug Thompson reg = DBAM0; 9162da11654SDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, reg, &pvt->dbam0); 9172da11654SDoug Thompson if (err) 9182da11654SDoug Thompson goto err_reg; 9192da11654SDoug Thompson 9202da11654SDoug Thompson if (boot_cpu_data.x86 >= 0x10) { 9212da11654SDoug Thompson reg = DBAM1; 9222da11654SDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, reg, &pvt->dbam1); 9232da11654SDoug Thompson 9242da11654SDoug Thompson if (err) 9252da11654SDoug Thompson goto err_reg; 9262da11654SDoug Thompson } 9272da11654SDoug Thompson 928c2718348SDoug Thompson return; 929c2718348SDoug Thompson 9302da11654SDoug Thompson err_reg: 9312da11654SDoug Thompson debugf0("Error reading F2x%03x.\n", reg); 9322da11654SDoug Thompson } 9332da11654SDoug Thompson 93494be4bffSDoug Thompson /* 93594be4bffSDoug Thompson * NOTE: CPU Revision Dependent code: Rev E and Rev F 93694be4bffSDoug Thompson * 93794be4bffSDoug Thompson * Set the DCSB and DCSM mask values depending on the CPU revision value. Also 93894be4bffSDoug Thompson * set the shift factor for the DCSB and DCSM values. 93994be4bffSDoug Thompson * 94094be4bffSDoug Thompson * ->dcs_mask_notused, RevE: 94194be4bffSDoug Thompson * 94294be4bffSDoug Thompson * To find the max InputAddr for the csrow, start with the base address and set 94394be4bffSDoug Thompson * all bits that are "don't care" bits in the test at the start of section 94494be4bffSDoug Thompson * 3.5.4 (p. 84). 94594be4bffSDoug Thompson * 94694be4bffSDoug Thompson * The "don't care" bits are all set bits in the mask and all bits in the gaps 94794be4bffSDoug Thompson * between bit ranges [35:25] and [19:13]. The value REV_E_DCS_NOTUSED_BITS 94894be4bffSDoug Thompson * represents bits [24:20] and [12:0], which are all bits in the above-mentioned 94994be4bffSDoug Thompson * gaps. 95094be4bffSDoug Thompson * 95194be4bffSDoug Thompson * ->dcs_mask_notused, RevF and later: 95294be4bffSDoug Thompson * 95394be4bffSDoug Thompson * To find the max InputAddr for the csrow, start with the base address and set 95494be4bffSDoug Thompson * all bits that are "don't care" bits in the test at the start of NPT section 95594be4bffSDoug Thompson * 4.5.4 (p. 87). 95694be4bffSDoug Thompson * 95794be4bffSDoug Thompson * The "don't care" bits are all set bits in the mask and all bits in the gaps 95894be4bffSDoug Thompson * between bit ranges [36:27] and [21:13]. 95994be4bffSDoug Thompson * 96094be4bffSDoug Thompson * The value REV_F_F1Xh_DCS_NOTUSED_BITS represents bits [26:22] and [12:0], 96194be4bffSDoug Thompson * which are all bits in the above-mentioned gaps. 96294be4bffSDoug Thompson */ 96394be4bffSDoug Thompson static void amd64_set_dct_base_and_mask(struct amd64_pvt *pvt) 96494be4bffSDoug Thompson { 96594be4bffSDoug Thompson if (pvt->ext_model >= OPTERON_CPU_REV_F) { 96694be4bffSDoug Thompson pvt->dcsb_base = REV_F_F1Xh_DCSB_BASE_BITS; 96794be4bffSDoug Thompson pvt->dcsm_mask = REV_F_F1Xh_DCSM_MASK_BITS; 96894be4bffSDoug Thompson pvt->dcs_mask_notused = REV_F_F1Xh_DCS_NOTUSED_BITS; 96994be4bffSDoug Thompson pvt->dcs_shift = REV_F_F1Xh_DCS_SHIFT; 97094be4bffSDoug Thompson 97194be4bffSDoug Thompson switch (boot_cpu_data.x86) { 97294be4bffSDoug Thompson case 0xf: 97394be4bffSDoug Thompson pvt->num_dcsm = REV_F_DCSM_COUNT; 97494be4bffSDoug Thompson break; 97594be4bffSDoug Thompson 97694be4bffSDoug Thompson case 0x10: 97794be4bffSDoug Thompson pvt->num_dcsm = F10_DCSM_COUNT; 97894be4bffSDoug Thompson break; 97994be4bffSDoug Thompson 98094be4bffSDoug Thompson case 0x11: 98194be4bffSDoug Thompson pvt->num_dcsm = F11_DCSM_COUNT; 98294be4bffSDoug Thompson break; 98394be4bffSDoug Thompson 98494be4bffSDoug Thompson default: 98594be4bffSDoug Thompson amd64_printk(KERN_ERR, "Unsupported family!\n"); 98694be4bffSDoug Thompson break; 98794be4bffSDoug Thompson } 98894be4bffSDoug Thompson } else { 98994be4bffSDoug Thompson pvt->dcsb_base = REV_E_DCSB_BASE_BITS; 99094be4bffSDoug Thompson pvt->dcsm_mask = REV_E_DCSM_MASK_BITS; 99194be4bffSDoug Thompson pvt->dcs_mask_notused = REV_E_DCS_NOTUSED_BITS; 99294be4bffSDoug Thompson pvt->dcs_shift = REV_E_DCS_SHIFT; 99394be4bffSDoug Thompson pvt->num_dcsm = REV_E_DCSM_COUNT; 99494be4bffSDoug Thompson } 99594be4bffSDoug Thompson } 99694be4bffSDoug Thompson 99794be4bffSDoug Thompson /* 99894be4bffSDoug Thompson * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask hw registers 99994be4bffSDoug Thompson */ 100094be4bffSDoug Thompson static void amd64_read_dct_base_mask(struct amd64_pvt *pvt) 100194be4bffSDoug Thompson { 100294be4bffSDoug Thompson int cs, reg, err = 0; 100394be4bffSDoug Thompson 100494be4bffSDoug Thompson amd64_set_dct_base_and_mask(pvt); 100594be4bffSDoug Thompson 100694be4bffSDoug Thompson for (cs = 0; cs < CHIPSELECT_COUNT; cs++) { 100794be4bffSDoug Thompson reg = K8_DCSB0 + (cs * 4); 100894be4bffSDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, reg, 100994be4bffSDoug Thompson &pvt->dcsb0[cs]); 101094be4bffSDoug Thompson if (unlikely(err)) 101194be4bffSDoug Thompson debugf0("Reading K8_DCSB0[%d] failed\n", cs); 101294be4bffSDoug Thompson else 101394be4bffSDoug Thompson debugf0(" DCSB0[%d]=0x%08x reg: F2x%x\n", 101494be4bffSDoug Thompson cs, pvt->dcsb0[cs], reg); 101594be4bffSDoug Thompson 101694be4bffSDoug Thompson /* If DCT are NOT ganged, then read in DCT1's base */ 101794be4bffSDoug Thompson if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) { 101894be4bffSDoug Thompson reg = F10_DCSB1 + (cs * 4); 101994be4bffSDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, reg, 102094be4bffSDoug Thompson &pvt->dcsb1[cs]); 102194be4bffSDoug Thompson if (unlikely(err)) 102294be4bffSDoug Thompson debugf0("Reading F10_DCSB1[%d] failed\n", cs); 102394be4bffSDoug Thompson else 102494be4bffSDoug Thompson debugf0(" DCSB1[%d]=0x%08x reg: F2x%x\n", 102594be4bffSDoug Thompson cs, pvt->dcsb1[cs], reg); 102694be4bffSDoug Thompson } else { 102794be4bffSDoug Thompson pvt->dcsb1[cs] = 0; 102894be4bffSDoug Thompson } 102994be4bffSDoug Thompson } 103094be4bffSDoug Thompson 103194be4bffSDoug Thompson for (cs = 0; cs < pvt->num_dcsm; cs++) { 10324afcd2dcSWan Wei reg = K8_DCSM0 + (cs * 4); 103394be4bffSDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, reg, 103494be4bffSDoug Thompson &pvt->dcsm0[cs]); 103594be4bffSDoug Thompson if (unlikely(err)) 103694be4bffSDoug Thompson debugf0("Reading K8_DCSM0 failed\n"); 103794be4bffSDoug Thompson else 103894be4bffSDoug Thompson debugf0(" DCSM0[%d]=0x%08x reg: F2x%x\n", 103994be4bffSDoug Thompson cs, pvt->dcsm0[cs], reg); 104094be4bffSDoug Thompson 104194be4bffSDoug Thompson /* If DCT are NOT ganged, then read in DCT1's mask */ 104294be4bffSDoug Thompson if (boot_cpu_data.x86 >= 0x10 && !dct_ganging_enabled(pvt)) { 104394be4bffSDoug Thompson reg = F10_DCSM1 + (cs * 4); 104494be4bffSDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, reg, 104594be4bffSDoug Thompson &pvt->dcsm1[cs]); 104694be4bffSDoug Thompson if (unlikely(err)) 104794be4bffSDoug Thompson debugf0("Reading F10_DCSM1[%d] failed\n", cs); 104894be4bffSDoug Thompson else 104994be4bffSDoug Thompson debugf0(" DCSM1[%d]=0x%08x reg: F2x%x\n", 105094be4bffSDoug Thompson cs, pvt->dcsm1[cs], reg); 105194be4bffSDoug Thompson } else 105294be4bffSDoug Thompson pvt->dcsm1[cs] = 0; 105394be4bffSDoug Thompson } 105494be4bffSDoug Thompson } 105594be4bffSDoug Thompson 105694be4bffSDoug Thompson static enum mem_type amd64_determine_memory_type(struct amd64_pvt *pvt) 105794be4bffSDoug Thompson { 105894be4bffSDoug Thompson enum mem_type type; 105994be4bffSDoug Thompson 106094be4bffSDoug Thompson if (boot_cpu_data.x86 >= 0x10 || pvt->ext_model >= OPTERON_CPU_REV_F) { 106194be4bffSDoug Thompson /* Rev F and later */ 106294be4bffSDoug Thompson type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2; 106394be4bffSDoug Thompson } else { 106494be4bffSDoug Thompson /* Rev E and earlier */ 106594be4bffSDoug Thompson type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR; 106694be4bffSDoug Thompson } 106794be4bffSDoug Thompson 106894be4bffSDoug Thompson debugf1(" Memory type is: %s\n", 106994be4bffSDoug Thompson (type == MEM_DDR2) ? "MEM_DDR2" : 107094be4bffSDoug Thompson (type == MEM_RDDR2) ? "MEM_RDDR2" : 107194be4bffSDoug Thompson (type == MEM_DDR) ? "MEM_DDR" : "MEM_RDDR"); 107294be4bffSDoug Thompson 107394be4bffSDoug Thompson return type; 107494be4bffSDoug Thompson } 107594be4bffSDoug Thompson 1076ddff876dSDoug Thompson /* 1077ddff876dSDoug Thompson * Read the DRAM Configuration Low register. It differs between CG, D & E revs 1078ddff876dSDoug Thompson * and the later RevF memory controllers (DDR vs DDR2) 1079ddff876dSDoug Thompson * 1080ddff876dSDoug Thompson * Return: 1081ddff876dSDoug Thompson * number of memory channels in operation 1082ddff876dSDoug Thompson * Pass back: 1083ddff876dSDoug Thompson * contents of the DCL0_LOW register 1084ddff876dSDoug Thompson */ 1085ddff876dSDoug Thompson static int k8_early_channel_count(struct amd64_pvt *pvt) 1086ddff876dSDoug Thompson { 1087ddff876dSDoug Thompson int flag, err = 0; 1088ddff876dSDoug Thompson 1089ddff876dSDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0); 1090ddff876dSDoug Thompson if (err) 1091ddff876dSDoug Thompson return err; 1092ddff876dSDoug Thompson 1093ddff876dSDoug Thompson if ((boot_cpu_data.x86_model >> 4) >= OPTERON_CPU_REV_F) { 1094ddff876dSDoug Thompson /* RevF (NPT) and later */ 1095ddff876dSDoug Thompson flag = pvt->dclr0 & F10_WIDTH_128; 1096ddff876dSDoug Thompson } else { 1097ddff876dSDoug Thompson /* RevE and earlier */ 1098ddff876dSDoug Thompson flag = pvt->dclr0 & REVE_WIDTH_128; 1099ddff876dSDoug Thompson } 1100ddff876dSDoug Thompson 1101ddff876dSDoug Thompson /* not used */ 1102ddff876dSDoug Thompson pvt->dclr1 = 0; 1103ddff876dSDoug Thompson 1104ddff876dSDoug Thompson return (flag) ? 2 : 1; 1105ddff876dSDoug Thompson } 1106ddff876dSDoug Thompson 1107ddff876dSDoug Thompson /* extract the ERROR ADDRESS for the K8 CPUs */ 1108ddff876dSDoug Thompson static u64 k8_get_error_address(struct mem_ctl_info *mci, 1109ef44cc4cSBorislav Petkov struct err_regs *info) 1110ddff876dSDoug Thompson { 1111ddff876dSDoug Thompson return (((u64) (info->nbeah & 0xff)) << 32) + 1112ddff876dSDoug Thompson (info->nbeal & ~0x03); 1113ddff876dSDoug Thompson } 1114ddff876dSDoug Thompson 1115ddff876dSDoug Thompson /* 1116ddff876dSDoug Thompson * Read the Base and Limit registers for K8 based Memory controllers; extract 1117ddff876dSDoug Thompson * fields from the 'raw' reg into separate data fields 1118ddff876dSDoug Thompson * 1119ddff876dSDoug Thompson * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN 1120ddff876dSDoug Thompson */ 1121ddff876dSDoug Thompson static void k8_read_dram_base_limit(struct amd64_pvt *pvt, int dram) 1122ddff876dSDoug Thompson { 1123ddff876dSDoug Thompson u32 low; 1124ddff876dSDoug Thompson u32 off = dram << 3; /* 8 bytes between DRAM entries */ 1125ddff876dSDoug Thompson int err; 1126ddff876dSDoug Thompson 1127ddff876dSDoug Thompson err = pci_read_config_dword(pvt->addr_f1_ctl, 1128ddff876dSDoug Thompson K8_DRAM_BASE_LOW + off, &low); 1129ddff876dSDoug Thompson if (err) 1130ddff876dSDoug Thompson debugf0("Reading K8_DRAM_BASE_LOW failed\n"); 1131ddff876dSDoug Thompson 1132ddff876dSDoug Thompson /* Extract parts into separate data entries */ 1133ddff876dSDoug Thompson pvt->dram_base[dram] = ((u64) low & 0xFFFF0000) << 8; 1134ddff876dSDoug Thompson pvt->dram_IntlvEn[dram] = (low >> 8) & 0x7; 1135ddff876dSDoug Thompson pvt->dram_rw_en[dram] = (low & 0x3); 1136ddff876dSDoug Thompson 1137ddff876dSDoug Thompson err = pci_read_config_dword(pvt->addr_f1_ctl, 1138ddff876dSDoug Thompson K8_DRAM_LIMIT_LOW + off, &low); 1139ddff876dSDoug Thompson if (err) 1140ddff876dSDoug Thompson debugf0("Reading K8_DRAM_LIMIT_LOW failed\n"); 1141ddff876dSDoug Thompson 1142ddff876dSDoug Thompson /* 1143ddff876dSDoug Thompson * Extract parts into separate data entries. Limit is the HIGHEST memory 1144ddff876dSDoug Thompson * location of the region, so lower 24 bits need to be all ones 1145ddff876dSDoug Thompson */ 1146ddff876dSDoug Thompson pvt->dram_limit[dram] = (((u64) low & 0xFFFF0000) << 8) | 0x00FFFFFF; 1147ddff876dSDoug Thompson pvt->dram_IntlvSel[dram] = (low >> 8) & 0x7; 1148ddff876dSDoug Thompson pvt->dram_DstNode[dram] = (low & 0x7); 1149ddff876dSDoug Thompson } 1150ddff876dSDoug Thompson 1151ddff876dSDoug Thompson static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, 1152ef44cc4cSBorislav Petkov struct err_regs *info, 1153ddff876dSDoug Thompson u64 SystemAddress) 1154ddff876dSDoug Thompson { 1155ddff876dSDoug Thompson struct mem_ctl_info *src_mci; 1156ddff876dSDoug Thompson unsigned short syndrome; 1157ddff876dSDoug Thompson int channel, csrow; 1158ddff876dSDoug Thompson u32 page, offset; 1159ddff876dSDoug Thompson 1160ddff876dSDoug Thompson /* Extract the syndrome parts and form a 16-bit syndrome */ 1161b70ef010SBorislav Petkov syndrome = HIGH_SYNDROME(info->nbsl) << 8; 1162b70ef010SBorislav Petkov syndrome |= LOW_SYNDROME(info->nbsh); 1163ddff876dSDoug Thompson 1164ddff876dSDoug Thompson /* CHIPKILL enabled */ 1165ddff876dSDoug Thompson if (info->nbcfg & K8_NBCFG_CHIPKILL) { 1166ddff876dSDoug Thompson channel = get_channel_from_ecc_syndrome(syndrome); 1167ddff876dSDoug Thompson if (channel < 0) { 1168ddff876dSDoug Thompson /* 1169ddff876dSDoug Thompson * Syndrome didn't map, so we don't know which of the 1170ddff876dSDoug Thompson * 2 DIMMs is in error. So we need to ID 'both' of them 1171ddff876dSDoug Thompson * as suspect. 1172ddff876dSDoug Thompson */ 1173ddff876dSDoug Thompson amd64_mc_printk(mci, KERN_WARNING, 1174ddff876dSDoug Thompson "unknown syndrome 0x%x - possible error " 1175ddff876dSDoug Thompson "reporting race\n", syndrome); 1176ddff876dSDoug Thompson edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); 1177ddff876dSDoug Thompson return; 1178ddff876dSDoug Thompson } 1179ddff876dSDoug Thompson } else { 1180ddff876dSDoug Thompson /* 1181ddff876dSDoug Thompson * non-chipkill ecc mode 1182ddff876dSDoug Thompson * 1183ddff876dSDoug Thompson * The k8 documentation is unclear about how to determine the 1184ddff876dSDoug Thompson * channel number when using non-chipkill memory. This method 1185ddff876dSDoug Thompson * was obtained from email communication with someone at AMD. 1186ddff876dSDoug Thompson * (Wish the email was placed in this comment - norsk) 1187ddff876dSDoug Thompson */ 1188ddff876dSDoug Thompson channel = ((SystemAddress & BIT(3)) != 0); 1189ddff876dSDoug Thompson } 1190ddff876dSDoug Thompson 1191ddff876dSDoug Thompson /* 1192ddff876dSDoug Thompson * Find out which node the error address belongs to. This may be 1193ddff876dSDoug Thompson * different from the node that detected the error. 1194ddff876dSDoug Thompson */ 1195ddff876dSDoug Thompson src_mci = find_mc_by_sys_addr(mci, SystemAddress); 1196ddff876dSDoug Thompson if (src_mci) { 1197ddff876dSDoug Thompson amd64_mc_printk(mci, KERN_ERR, 1198ddff876dSDoug Thompson "failed to map error address 0x%lx to a node\n", 1199ddff876dSDoug Thompson (unsigned long)SystemAddress); 1200ddff876dSDoug Thompson edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); 1201ddff876dSDoug Thompson return; 1202ddff876dSDoug Thompson } 1203ddff876dSDoug Thompson 1204ddff876dSDoug Thompson /* Now map the SystemAddress to a CSROW */ 1205ddff876dSDoug Thompson csrow = sys_addr_to_csrow(src_mci, SystemAddress); 1206ddff876dSDoug Thompson if (csrow < 0) { 1207ddff876dSDoug Thompson edac_mc_handle_ce_no_info(src_mci, EDAC_MOD_STR); 1208ddff876dSDoug Thompson } else { 1209ddff876dSDoug Thompson error_address_to_page_and_offset(SystemAddress, &page, &offset); 1210ddff876dSDoug Thompson 1211ddff876dSDoug Thompson edac_mc_handle_ce(src_mci, page, offset, syndrome, csrow, 1212ddff876dSDoug Thompson channel, EDAC_MOD_STR); 1213ddff876dSDoug Thompson } 1214ddff876dSDoug Thompson } 1215ddff876dSDoug Thompson 1216ddff876dSDoug Thompson /* 1217ddff876dSDoug Thompson * determrine the number of PAGES in for this DIMM's size based on its DRAM 1218ddff876dSDoug Thompson * Address Mapping. 1219ddff876dSDoug Thompson * 1220ddff876dSDoug Thompson * First step is to calc the number of bits to shift a value of 1 left to 1221ddff876dSDoug Thompson * indicate show many pages. Start with the DBAM value as the starting bits, 1222ddff876dSDoug Thompson * then proceed to adjust those shift bits, based on CPU rev and the table. 1223ddff876dSDoug Thompson * See BKDG on the DBAM 1224ddff876dSDoug Thompson */ 1225ddff876dSDoug Thompson static int k8_dbam_map_to_pages(struct amd64_pvt *pvt, int dram_map) 1226ddff876dSDoug Thompson { 1227ddff876dSDoug Thompson int nr_pages; 1228ddff876dSDoug Thompson 1229ddff876dSDoug Thompson if (pvt->ext_model >= OPTERON_CPU_REV_F) { 1230ddff876dSDoug Thompson nr_pages = 1 << (revf_quad_ddr2_shift[dram_map] - PAGE_SHIFT); 1231ddff876dSDoug Thompson } else { 1232ddff876dSDoug Thompson /* 1233ddff876dSDoug Thompson * RevE and less section; this line is tricky. It collapses the 1234ddff876dSDoug Thompson * table used by RevD and later to one that matches revisions CG 1235ddff876dSDoug Thompson * and earlier. 1236ddff876dSDoug Thompson */ 1237ddff876dSDoug Thompson dram_map -= (pvt->ext_model >= OPTERON_CPU_REV_D) ? 1238ddff876dSDoug Thompson (dram_map > 8 ? 4 : (dram_map > 5 ? 1239ddff876dSDoug Thompson 3 : (dram_map > 2 ? 1 : 0))) : 0; 1240ddff876dSDoug Thompson 1241ddff876dSDoug Thompson /* 25 shift is 32MiB minimum DIMM size in RevE and prior */ 1242ddff876dSDoug Thompson nr_pages = 1 << (dram_map + 25 - PAGE_SHIFT); 1243ddff876dSDoug Thompson } 1244ddff876dSDoug Thompson 1245ddff876dSDoug Thompson return nr_pages; 1246ddff876dSDoug Thompson } 1247ddff876dSDoug Thompson 12481afd3c98SDoug Thompson /* 12491afd3c98SDoug Thompson * Get the number of DCT channels in use. 12501afd3c98SDoug Thompson * 12511afd3c98SDoug Thompson * Return: 12521afd3c98SDoug Thompson * number of Memory Channels in operation 12531afd3c98SDoug Thompson * Pass back: 12541afd3c98SDoug Thompson * contents of the DCL0_LOW register 12551afd3c98SDoug Thompson */ 12561afd3c98SDoug Thompson static int f10_early_channel_count(struct amd64_pvt *pvt) 12571afd3c98SDoug Thompson { 12581afd3c98SDoug Thompson int err = 0, channels = 0; 12591afd3c98SDoug Thompson u32 dbam; 1260ddff876dSDoug Thompson 12611afd3c98SDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0); 12621afd3c98SDoug Thompson if (err) 12631afd3c98SDoug Thompson goto err_reg; 12641afd3c98SDoug Thompson 12651afd3c98SDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_1, &pvt->dclr1); 12661afd3c98SDoug Thompson if (err) 12671afd3c98SDoug Thompson goto err_reg; 12681afd3c98SDoug Thompson 12691afd3c98SDoug Thompson /* If we are in 128 bit mode, then we are using 2 channels */ 12701afd3c98SDoug Thompson if (pvt->dclr0 & F10_WIDTH_128) { 12711afd3c98SDoug Thompson debugf0("Data WIDTH is 128 bits - 2 channels\n"); 12721afd3c98SDoug Thompson channels = 2; 12731afd3c98SDoug Thompson return channels; 12741afd3c98SDoug Thompson } 12751afd3c98SDoug Thompson 12761afd3c98SDoug Thompson /* 12771afd3c98SDoug Thompson * Need to check if in UN-ganged mode: In such, there are 2 channels, 12781afd3c98SDoug Thompson * but they are NOT in 128 bit mode and thus the above 'dcl0' status bit 12791afd3c98SDoug Thompson * will be OFF. 12801afd3c98SDoug Thompson * 12811afd3c98SDoug Thompson * Need to check DCT0[0] and DCT1[0] to see if only one of them has 12821afd3c98SDoug Thompson * their CSEnable bit on. If so, then SINGLE DIMM case. 12831afd3c98SDoug Thompson */ 12841afd3c98SDoug Thompson debugf0("Data WIDTH is NOT 128 bits - need more decoding\n"); 12851afd3c98SDoug Thompson 12861afd3c98SDoug Thompson /* 12871afd3c98SDoug Thompson * Check DRAM Bank Address Mapping values for each DIMM to see if there 12881afd3c98SDoug Thompson * is more than just one DIMM present in unganged mode. Need to check 12891afd3c98SDoug Thompson * both controllers since DIMMs can be placed in either one. 12901afd3c98SDoug Thompson */ 12911afd3c98SDoug Thompson channels = 0; 12921afd3c98SDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, DBAM0, &dbam); 12931afd3c98SDoug Thompson if (err) 12941afd3c98SDoug Thompson goto err_reg; 12951afd3c98SDoug Thompson 12961afd3c98SDoug Thompson if (DBAM_DIMM(0, dbam) > 0) 12971afd3c98SDoug Thompson channels++; 12981afd3c98SDoug Thompson if (DBAM_DIMM(1, dbam) > 0) 12991afd3c98SDoug Thompson channels++; 13001afd3c98SDoug Thompson if (DBAM_DIMM(2, dbam) > 0) 13011afd3c98SDoug Thompson channels++; 13021afd3c98SDoug Thompson if (DBAM_DIMM(3, dbam) > 0) 13031afd3c98SDoug Thompson channels++; 13041afd3c98SDoug Thompson 13051afd3c98SDoug Thompson /* If more than 2 DIMMs are present, then we have 2 channels */ 13061afd3c98SDoug Thompson if (channels > 2) 13071afd3c98SDoug Thompson channels = 2; 13081afd3c98SDoug Thompson else if (channels == 0) { 13091afd3c98SDoug Thompson /* No DIMMs on DCT0, so look at DCT1 */ 13101afd3c98SDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, DBAM1, &dbam); 13111afd3c98SDoug Thompson if (err) 13121afd3c98SDoug Thompson goto err_reg; 13131afd3c98SDoug Thompson 13141afd3c98SDoug Thompson if (DBAM_DIMM(0, dbam) > 0) 13151afd3c98SDoug Thompson channels++; 13161afd3c98SDoug Thompson if (DBAM_DIMM(1, dbam) > 0) 13171afd3c98SDoug Thompson channels++; 13181afd3c98SDoug Thompson if (DBAM_DIMM(2, dbam) > 0) 13191afd3c98SDoug Thompson channels++; 13201afd3c98SDoug Thompson if (DBAM_DIMM(3, dbam) > 0) 13211afd3c98SDoug Thompson channels++; 13221afd3c98SDoug Thompson 13231afd3c98SDoug Thompson if (channels > 2) 13241afd3c98SDoug Thompson channels = 2; 13251afd3c98SDoug Thompson } 13261afd3c98SDoug Thompson 13271afd3c98SDoug Thompson /* If we found ALL 0 values, then assume just ONE DIMM-ONE Channel */ 13281afd3c98SDoug Thompson if (channels == 0) 13291afd3c98SDoug Thompson channels = 1; 13301afd3c98SDoug Thompson 133137da0450SBorislav Petkov debugf0("MCT channel count: %d\n", channels); 13321afd3c98SDoug Thompson 13331afd3c98SDoug Thompson return channels; 13341afd3c98SDoug Thompson 13351afd3c98SDoug Thompson err_reg: 13361afd3c98SDoug Thompson return -1; 13371afd3c98SDoug Thompson 13381afd3c98SDoug Thompson } 13391afd3c98SDoug Thompson 13401afd3c98SDoug Thompson static int f10_dbam_map_to_pages(struct amd64_pvt *pvt, int dram_map) 13411afd3c98SDoug Thompson { 13421afd3c98SDoug Thompson return 1 << (revf_quad_ddr2_shift[dram_map] - PAGE_SHIFT); 13431afd3c98SDoug Thompson } 13441afd3c98SDoug Thompson 13451afd3c98SDoug Thompson /* Enable extended configuration access via 0xCF8 feature */ 13461afd3c98SDoug Thompson static void amd64_setup(struct amd64_pvt *pvt) 13471afd3c98SDoug Thompson { 13481afd3c98SDoug Thompson u32 reg; 13491afd3c98SDoug Thompson 13501afd3c98SDoug Thompson pci_read_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, ®); 13511afd3c98SDoug Thompson 13521afd3c98SDoug Thompson pvt->flags.cf8_extcfg = !!(reg & F10_NB_CFG_LOW_ENABLE_EXT_CFG); 13531afd3c98SDoug Thompson reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG; 13541afd3c98SDoug Thompson pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg); 13551afd3c98SDoug Thompson } 13561afd3c98SDoug Thompson 13571afd3c98SDoug Thompson /* Restore the extended configuration access via 0xCF8 feature */ 13581afd3c98SDoug Thompson static void amd64_teardown(struct amd64_pvt *pvt) 13591afd3c98SDoug Thompson { 13601afd3c98SDoug Thompson u32 reg; 13611afd3c98SDoug Thompson 13621afd3c98SDoug Thompson pci_read_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, ®); 13631afd3c98SDoug Thompson 13641afd3c98SDoug Thompson reg &= ~F10_NB_CFG_LOW_ENABLE_EXT_CFG; 13651afd3c98SDoug Thompson if (pvt->flags.cf8_extcfg) 13661afd3c98SDoug Thompson reg |= F10_NB_CFG_LOW_ENABLE_EXT_CFG; 13671afd3c98SDoug Thompson pci_write_config_dword(pvt->misc_f3_ctl, F10_NB_CFG_HIGH, reg); 13681afd3c98SDoug Thompson } 13691afd3c98SDoug Thompson 13701afd3c98SDoug Thompson static u64 f10_get_error_address(struct mem_ctl_info *mci, 1371ef44cc4cSBorislav Petkov struct err_regs *info) 13721afd3c98SDoug Thompson { 13731afd3c98SDoug Thompson return (((u64) (info->nbeah & 0xffff)) << 32) + 13741afd3c98SDoug Thompson (info->nbeal & ~0x01); 13751afd3c98SDoug Thompson } 13761afd3c98SDoug Thompson 13771afd3c98SDoug Thompson /* 13781afd3c98SDoug Thompson * Read the Base and Limit registers for F10 based Memory controllers. Extract 13791afd3c98SDoug Thompson * fields from the 'raw' reg into separate data fields. 13801afd3c98SDoug Thompson * 13811afd3c98SDoug Thompson * Isolates: BASE, LIMIT, IntlvEn, IntlvSel, RW_EN. 13821afd3c98SDoug Thompson */ 13831afd3c98SDoug Thompson static void f10_read_dram_base_limit(struct amd64_pvt *pvt, int dram) 13841afd3c98SDoug Thompson { 13851afd3c98SDoug Thompson u32 high_offset, low_offset, high_base, low_base, high_limit, low_limit; 13861afd3c98SDoug Thompson 13871afd3c98SDoug Thompson low_offset = K8_DRAM_BASE_LOW + (dram << 3); 13881afd3c98SDoug Thompson high_offset = F10_DRAM_BASE_HIGH + (dram << 3); 13891afd3c98SDoug Thompson 13901afd3c98SDoug Thompson /* read the 'raw' DRAM BASE Address register */ 13911afd3c98SDoug Thompson pci_read_config_dword(pvt->addr_f1_ctl, low_offset, &low_base); 13921afd3c98SDoug Thompson 13931afd3c98SDoug Thompson /* Read from the ECS data register */ 13941afd3c98SDoug Thompson pci_read_config_dword(pvt->addr_f1_ctl, high_offset, &high_base); 13951afd3c98SDoug Thompson 13961afd3c98SDoug Thompson /* Extract parts into separate data entries */ 13971afd3c98SDoug Thompson pvt->dram_rw_en[dram] = (low_base & 0x3); 13981afd3c98SDoug Thompson 13991afd3c98SDoug Thompson if (pvt->dram_rw_en[dram] == 0) 14001afd3c98SDoug Thompson return; 14011afd3c98SDoug Thompson 14021afd3c98SDoug Thompson pvt->dram_IntlvEn[dram] = (low_base >> 8) & 0x7; 14031afd3c98SDoug Thompson 14041afd3c98SDoug Thompson pvt->dram_base[dram] = (((((u64) high_base & 0x000000FF) << 32) | 14051afd3c98SDoug Thompson ((u64) low_base & 0xFFFF0000))) << 8; 14061afd3c98SDoug Thompson 14071afd3c98SDoug Thompson low_offset = K8_DRAM_LIMIT_LOW + (dram << 3); 14081afd3c98SDoug Thompson high_offset = F10_DRAM_LIMIT_HIGH + (dram << 3); 14091afd3c98SDoug Thompson 14101afd3c98SDoug Thompson /* read the 'raw' LIMIT registers */ 14111afd3c98SDoug Thompson pci_read_config_dword(pvt->addr_f1_ctl, low_offset, &low_limit); 14121afd3c98SDoug Thompson 14131afd3c98SDoug Thompson /* Read from the ECS data register for the HIGH portion */ 14141afd3c98SDoug Thompson pci_read_config_dword(pvt->addr_f1_ctl, high_offset, &high_limit); 14151afd3c98SDoug Thompson 14161afd3c98SDoug Thompson debugf0(" HW Regs: BASE=0x%08x-%08x LIMIT= 0x%08x-%08x\n", 14171afd3c98SDoug Thompson high_base, low_base, high_limit, low_limit); 14181afd3c98SDoug Thompson 14191afd3c98SDoug Thompson pvt->dram_DstNode[dram] = (low_limit & 0x7); 14201afd3c98SDoug Thompson pvt->dram_IntlvSel[dram] = (low_limit >> 8) & 0x7; 14211afd3c98SDoug Thompson 14221afd3c98SDoug Thompson /* 14231afd3c98SDoug Thompson * Extract address values and form a LIMIT address. Limit is the HIGHEST 14241afd3c98SDoug Thompson * memory location of the region, so low 24 bits need to be all ones. 14251afd3c98SDoug Thompson */ 14261afd3c98SDoug Thompson low_limit |= 0x0000FFFF; 14271afd3c98SDoug Thompson pvt->dram_limit[dram] = 14281afd3c98SDoug Thompson ((((u64) high_limit << 32) + (u64) low_limit) << 8) | (0xFF); 14291afd3c98SDoug Thompson } 14306163b5d4SDoug Thompson 14316163b5d4SDoug Thompson static void f10_read_dram_ctl_register(struct amd64_pvt *pvt) 14326163b5d4SDoug Thompson { 14336163b5d4SDoug Thompson int err = 0; 14346163b5d4SDoug Thompson 14356163b5d4SDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCTL_SEL_LOW, 14366163b5d4SDoug Thompson &pvt->dram_ctl_select_low); 14376163b5d4SDoug Thompson if (err) { 14386163b5d4SDoug Thompson debugf0("Reading F10_DCTL_SEL_LOW failed\n"); 14396163b5d4SDoug Thompson } else { 14406163b5d4SDoug Thompson debugf0("DRAM_DCTL_SEL_LOW=0x%x DctSelBaseAddr=0x%x\n", 14416163b5d4SDoug Thompson pvt->dram_ctl_select_low, dct_sel_baseaddr(pvt)); 14426163b5d4SDoug Thompson 14436163b5d4SDoug Thompson debugf0(" DRAM DCTs are=%s DRAM Is=%s DRAM-Ctl-" 14446163b5d4SDoug Thompson "sel-hi-range=%s\n", 14456163b5d4SDoug Thompson (dct_ganging_enabled(pvt) ? "GANGED" : "NOT GANGED"), 14466163b5d4SDoug Thompson (dct_dram_enabled(pvt) ? "Enabled" : "Disabled"), 14476163b5d4SDoug Thompson (dct_high_range_enabled(pvt) ? "Enabled" : "Disabled")); 14486163b5d4SDoug Thompson 14496163b5d4SDoug Thompson debugf0(" DctDatIntLv=%s MemCleared=%s DctSelIntLvAddr=0x%x\n", 14506163b5d4SDoug Thompson (dct_data_intlv_enabled(pvt) ? "Enabled" : "Disabled"), 14516163b5d4SDoug Thompson (dct_memory_cleared(pvt) ? "True " : "False "), 14526163b5d4SDoug Thompson dct_sel_interleave_addr(pvt)); 14536163b5d4SDoug Thompson } 14546163b5d4SDoug Thompson 14556163b5d4SDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCTL_SEL_HIGH, 14566163b5d4SDoug Thompson &pvt->dram_ctl_select_high); 14576163b5d4SDoug Thompson if (err) 14586163b5d4SDoug Thompson debugf0("Reading F10_DCTL_SEL_HIGH failed\n"); 14596163b5d4SDoug Thompson } 14606163b5d4SDoug Thompson 1461f71d0a05SDoug Thompson /* 1462f71d0a05SDoug Thompson * determine channel based on the interleaving mode: F10h BKDG, 2.8.9 Memory 1463f71d0a05SDoug Thompson * Interleaving Modes. 1464f71d0a05SDoug Thompson */ 14656163b5d4SDoug Thompson static u32 f10_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, 14666163b5d4SDoug Thompson int hi_range_sel, u32 intlv_en) 14676163b5d4SDoug Thompson { 14686163b5d4SDoug Thompson u32 cs, temp, dct_sel_high = (pvt->dram_ctl_select_low >> 1) & 1; 14696163b5d4SDoug Thompson 14706163b5d4SDoug Thompson if (dct_ganging_enabled(pvt)) 14716163b5d4SDoug Thompson cs = 0; 14726163b5d4SDoug Thompson else if (hi_range_sel) 14736163b5d4SDoug Thompson cs = dct_sel_high; 14746163b5d4SDoug Thompson else if (dct_interleave_enabled(pvt)) { 1475f71d0a05SDoug Thompson /* 1476f71d0a05SDoug Thompson * see F2x110[DctSelIntLvAddr] - channel interleave mode 1477f71d0a05SDoug Thompson */ 14786163b5d4SDoug Thompson if (dct_sel_interleave_addr(pvt) == 0) 14796163b5d4SDoug Thompson cs = sys_addr >> 6 & 1; 14806163b5d4SDoug Thompson else if ((dct_sel_interleave_addr(pvt) >> 1) & 1) { 14816163b5d4SDoug Thompson temp = hweight_long((u32) ((sys_addr >> 16) & 0x1F)) % 2; 14826163b5d4SDoug Thompson 14836163b5d4SDoug Thompson if (dct_sel_interleave_addr(pvt) & 1) 14846163b5d4SDoug Thompson cs = (sys_addr >> 9 & 1) ^ temp; 14856163b5d4SDoug Thompson else 14866163b5d4SDoug Thompson cs = (sys_addr >> 6 & 1) ^ temp; 14876163b5d4SDoug Thompson } else if (intlv_en & 4) 14886163b5d4SDoug Thompson cs = sys_addr >> 15 & 1; 14896163b5d4SDoug Thompson else if (intlv_en & 2) 14906163b5d4SDoug Thompson cs = sys_addr >> 14 & 1; 14916163b5d4SDoug Thompson else if (intlv_en & 1) 14926163b5d4SDoug Thompson cs = sys_addr >> 13 & 1; 14936163b5d4SDoug Thompson else 14946163b5d4SDoug Thompson cs = sys_addr >> 12 & 1; 14956163b5d4SDoug Thompson } else if (dct_high_range_enabled(pvt) && !dct_ganging_enabled(pvt)) 14966163b5d4SDoug Thompson cs = ~dct_sel_high & 1; 14976163b5d4SDoug Thompson else 14986163b5d4SDoug Thompson cs = 0; 14996163b5d4SDoug Thompson 15006163b5d4SDoug Thompson return cs; 15016163b5d4SDoug Thompson } 15026163b5d4SDoug Thompson 15036163b5d4SDoug Thompson static inline u32 f10_map_intlv_en_to_shift(u32 intlv_en) 15046163b5d4SDoug Thompson { 15056163b5d4SDoug Thompson if (intlv_en == 1) 15066163b5d4SDoug Thompson return 1; 15076163b5d4SDoug Thompson else if (intlv_en == 3) 15086163b5d4SDoug Thompson return 2; 15096163b5d4SDoug Thompson else if (intlv_en == 7) 15106163b5d4SDoug Thompson return 3; 15116163b5d4SDoug Thompson 15126163b5d4SDoug Thompson return 0; 15136163b5d4SDoug Thompson } 15146163b5d4SDoug Thompson 1515f71d0a05SDoug Thompson /* See F10h BKDG, 2.8.10.2 DctSelBaseOffset Programming */ 1516f71d0a05SDoug Thompson static inline u64 f10_get_base_addr_offset(u64 sys_addr, int hi_range_sel, 15176163b5d4SDoug Thompson u32 dct_sel_base_addr, 15186163b5d4SDoug Thompson u64 dct_sel_base_off, 1519f71d0a05SDoug Thompson u32 hole_valid, u32 hole_off, 15206163b5d4SDoug Thompson u64 dram_base) 15216163b5d4SDoug Thompson { 15226163b5d4SDoug Thompson u64 chan_off; 15236163b5d4SDoug Thompson 15246163b5d4SDoug Thompson if (hi_range_sel) { 15256163b5d4SDoug Thompson if (!(dct_sel_base_addr & 0xFFFFF800) && 1526f71d0a05SDoug Thompson hole_valid && (sys_addr >= 0x100000000ULL)) 15276163b5d4SDoug Thompson chan_off = hole_off << 16; 15286163b5d4SDoug Thompson else 15296163b5d4SDoug Thompson chan_off = dct_sel_base_off; 15306163b5d4SDoug Thompson } else { 1531f71d0a05SDoug Thompson if (hole_valid && (sys_addr >= 0x100000000ULL)) 15326163b5d4SDoug Thompson chan_off = hole_off << 16; 15336163b5d4SDoug Thompson else 15346163b5d4SDoug Thompson chan_off = dram_base & 0xFFFFF8000000ULL; 15356163b5d4SDoug Thompson } 15366163b5d4SDoug Thompson 15376163b5d4SDoug Thompson return (sys_addr & 0x0000FFFFFFFFFFC0ULL) - 15386163b5d4SDoug Thompson (chan_off & 0x0000FFFFFF800000ULL); 15396163b5d4SDoug Thompson } 15406163b5d4SDoug Thompson 15416163b5d4SDoug Thompson /* Hack for the time being - Can we get this from BIOS?? */ 15426163b5d4SDoug Thompson #define CH0SPARE_RANK 0 15436163b5d4SDoug Thompson #define CH1SPARE_RANK 1 15446163b5d4SDoug Thompson 15456163b5d4SDoug Thompson /* 15466163b5d4SDoug Thompson * checks if the csrow passed in is marked as SPARED, if so returns the new 15476163b5d4SDoug Thompson * spare row 15486163b5d4SDoug Thompson */ 15496163b5d4SDoug Thompson static inline int f10_process_possible_spare(int csrow, 15506163b5d4SDoug Thompson u32 cs, struct amd64_pvt *pvt) 15516163b5d4SDoug Thompson { 15526163b5d4SDoug Thompson u32 swap_done; 15536163b5d4SDoug Thompson u32 bad_dram_cs; 15546163b5d4SDoug Thompson 15556163b5d4SDoug Thompson /* Depending on channel, isolate respective SPARING info */ 15566163b5d4SDoug Thompson if (cs) { 15576163b5d4SDoug Thompson swap_done = F10_ONLINE_SPARE_SWAPDONE1(pvt->online_spare); 15586163b5d4SDoug Thompson bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS1(pvt->online_spare); 15596163b5d4SDoug Thompson if (swap_done && (csrow == bad_dram_cs)) 15606163b5d4SDoug Thompson csrow = CH1SPARE_RANK; 15616163b5d4SDoug Thompson } else { 15626163b5d4SDoug Thompson swap_done = F10_ONLINE_SPARE_SWAPDONE0(pvt->online_spare); 15636163b5d4SDoug Thompson bad_dram_cs = F10_ONLINE_SPARE_BADDRAM_CS0(pvt->online_spare); 15646163b5d4SDoug Thompson if (swap_done && (csrow == bad_dram_cs)) 15656163b5d4SDoug Thompson csrow = CH0SPARE_RANK; 15666163b5d4SDoug Thompson } 15676163b5d4SDoug Thompson return csrow; 15686163b5d4SDoug Thompson } 15696163b5d4SDoug Thompson 15706163b5d4SDoug Thompson /* 15716163b5d4SDoug Thompson * Iterate over the DRAM DCT "base" and "mask" registers looking for a 15726163b5d4SDoug Thompson * SystemAddr match on the specified 'ChannelSelect' and 'NodeID' 15736163b5d4SDoug Thompson * 15746163b5d4SDoug Thompson * Return: 15756163b5d4SDoug Thompson * -EINVAL: NOT FOUND 15766163b5d4SDoug Thompson * 0..csrow = Chip-Select Row 15776163b5d4SDoug Thompson */ 15786163b5d4SDoug Thompson static int f10_lookup_addr_in_dct(u32 in_addr, u32 nid, u32 cs) 15796163b5d4SDoug Thompson { 15806163b5d4SDoug Thompson struct mem_ctl_info *mci; 15816163b5d4SDoug Thompson struct amd64_pvt *pvt; 15826163b5d4SDoug Thompson u32 cs_base, cs_mask; 15836163b5d4SDoug Thompson int cs_found = -EINVAL; 15846163b5d4SDoug Thompson int csrow; 15856163b5d4SDoug Thompson 15866163b5d4SDoug Thompson mci = mci_lookup[nid]; 15876163b5d4SDoug Thompson if (!mci) 15886163b5d4SDoug Thompson return cs_found; 15896163b5d4SDoug Thompson 15906163b5d4SDoug Thompson pvt = mci->pvt_info; 15916163b5d4SDoug Thompson 15926163b5d4SDoug Thompson debugf1("InputAddr=0x%x channelselect=%d\n", in_addr, cs); 15936163b5d4SDoug Thompson 15946163b5d4SDoug Thompson for (csrow = 0; csrow < CHIPSELECT_COUNT; csrow++) { 15956163b5d4SDoug Thompson 15966163b5d4SDoug Thompson cs_base = amd64_get_dct_base(pvt, cs, csrow); 15976163b5d4SDoug Thompson if (!(cs_base & K8_DCSB_CS_ENABLE)) 15986163b5d4SDoug Thompson continue; 15996163b5d4SDoug Thompson 16006163b5d4SDoug Thompson /* 16016163b5d4SDoug Thompson * We have an ENABLED CSROW, Isolate just the MASK bits of the 16026163b5d4SDoug Thompson * target: [28:19] and [13:5], which map to [36:27] and [21:13] 16036163b5d4SDoug Thompson * of the actual address. 16046163b5d4SDoug Thompson */ 16056163b5d4SDoug Thompson cs_base &= REV_F_F1Xh_DCSB_BASE_BITS; 16066163b5d4SDoug Thompson 16076163b5d4SDoug Thompson /* 16086163b5d4SDoug Thompson * Get the DCT Mask, and ENABLE the reserved bits: [18:16] and 16096163b5d4SDoug Thompson * [4:0] to become ON. Then mask off bits [28:0] ([36:8]) 16106163b5d4SDoug Thompson */ 16116163b5d4SDoug Thompson cs_mask = amd64_get_dct_mask(pvt, cs, csrow); 16126163b5d4SDoug Thompson 16136163b5d4SDoug Thompson debugf1(" CSROW=%d CSBase=0x%x RAW CSMask=0x%x\n", 16146163b5d4SDoug Thompson csrow, cs_base, cs_mask); 16156163b5d4SDoug Thompson 16166163b5d4SDoug Thompson cs_mask = (cs_mask | 0x0007C01F) & 0x1FFFFFFF; 16176163b5d4SDoug Thompson 16186163b5d4SDoug Thompson debugf1(" Final CSMask=0x%x\n", cs_mask); 16196163b5d4SDoug Thompson debugf1(" (InputAddr & ~CSMask)=0x%x " 16206163b5d4SDoug Thompson "(CSBase & ~CSMask)=0x%x\n", 16216163b5d4SDoug Thompson (in_addr & ~cs_mask), (cs_base & ~cs_mask)); 16226163b5d4SDoug Thompson 16236163b5d4SDoug Thompson if ((in_addr & ~cs_mask) == (cs_base & ~cs_mask)) { 16246163b5d4SDoug Thompson cs_found = f10_process_possible_spare(csrow, cs, pvt); 16256163b5d4SDoug Thompson 16266163b5d4SDoug Thompson debugf1(" MATCH csrow=%d\n", cs_found); 16276163b5d4SDoug Thompson break; 16286163b5d4SDoug Thompson } 16296163b5d4SDoug Thompson } 16306163b5d4SDoug Thompson return cs_found; 16316163b5d4SDoug Thompson } 16326163b5d4SDoug Thompson 1633f71d0a05SDoug Thompson /* For a given @dram_range, check if @sys_addr falls within it. */ 1634f71d0a05SDoug Thompson static int f10_match_to_this_node(struct amd64_pvt *pvt, int dram_range, 1635f71d0a05SDoug Thompson u64 sys_addr, int *nid, int *chan_sel) 1636f71d0a05SDoug Thompson { 1637f71d0a05SDoug Thompson int node_id, cs_found = -EINVAL, high_range = 0; 1638f71d0a05SDoug Thompson u32 intlv_en, intlv_sel, intlv_shift, hole_off; 1639f71d0a05SDoug Thompson u32 hole_valid, tmp, dct_sel_base, channel; 1640f71d0a05SDoug Thompson u64 dram_base, chan_addr, dct_sel_base_off; 1641f71d0a05SDoug Thompson 1642f71d0a05SDoug Thompson dram_base = pvt->dram_base[dram_range]; 1643f71d0a05SDoug Thompson intlv_en = pvt->dram_IntlvEn[dram_range]; 1644f71d0a05SDoug Thompson 1645f71d0a05SDoug Thompson node_id = pvt->dram_DstNode[dram_range]; 1646f71d0a05SDoug Thompson intlv_sel = pvt->dram_IntlvSel[dram_range]; 1647f71d0a05SDoug Thompson 1648f71d0a05SDoug Thompson debugf1("(dram=%d) Base=0x%llx SystemAddr= 0x%llx Limit=0x%llx\n", 1649f71d0a05SDoug Thompson dram_range, dram_base, sys_addr, pvt->dram_limit[dram_range]); 1650f71d0a05SDoug Thompson 1651f71d0a05SDoug Thompson /* 1652f71d0a05SDoug Thompson * This assumes that one node's DHAR is the same as all the other 1653f71d0a05SDoug Thompson * nodes' DHAR. 1654f71d0a05SDoug Thompson */ 1655f71d0a05SDoug Thompson hole_off = (pvt->dhar & 0x0000FF80); 1656f71d0a05SDoug Thompson hole_valid = (pvt->dhar & 0x1); 1657f71d0a05SDoug Thompson dct_sel_base_off = (pvt->dram_ctl_select_high & 0xFFFFFC00) << 16; 1658f71d0a05SDoug Thompson 1659f71d0a05SDoug Thompson debugf1(" HoleOffset=0x%x HoleValid=0x%x IntlvSel=0x%x\n", 1660f71d0a05SDoug Thompson hole_off, hole_valid, intlv_sel); 1661f71d0a05SDoug Thompson 1662f71d0a05SDoug Thompson if (intlv_en || 1663f71d0a05SDoug Thompson (intlv_sel != ((sys_addr >> 12) & intlv_en))) 1664f71d0a05SDoug Thompson return -EINVAL; 1665f71d0a05SDoug Thompson 1666f71d0a05SDoug Thompson dct_sel_base = dct_sel_baseaddr(pvt); 1667f71d0a05SDoug Thompson 1668f71d0a05SDoug Thompson /* 1669f71d0a05SDoug Thompson * check whether addresses >= DctSelBaseAddr[47:27] are to be used to 1670f71d0a05SDoug Thompson * select between DCT0 and DCT1. 1671f71d0a05SDoug Thompson */ 1672f71d0a05SDoug Thompson if (dct_high_range_enabled(pvt) && 1673f71d0a05SDoug Thompson !dct_ganging_enabled(pvt) && 1674f71d0a05SDoug Thompson ((sys_addr >> 27) >= (dct_sel_base >> 11))) 1675f71d0a05SDoug Thompson high_range = 1; 1676f71d0a05SDoug Thompson 1677f71d0a05SDoug Thompson channel = f10_determine_channel(pvt, sys_addr, high_range, intlv_en); 1678f71d0a05SDoug Thompson 1679f71d0a05SDoug Thompson chan_addr = f10_get_base_addr_offset(sys_addr, high_range, dct_sel_base, 1680f71d0a05SDoug Thompson dct_sel_base_off, hole_valid, 1681f71d0a05SDoug Thompson hole_off, dram_base); 1682f71d0a05SDoug Thompson 1683f71d0a05SDoug Thompson intlv_shift = f10_map_intlv_en_to_shift(intlv_en); 1684f71d0a05SDoug Thompson 1685f71d0a05SDoug Thompson /* remove Node ID (in case of memory interleaving) */ 1686f71d0a05SDoug Thompson tmp = chan_addr & 0xFC0; 1687f71d0a05SDoug Thompson 1688f71d0a05SDoug Thompson chan_addr = ((chan_addr >> intlv_shift) & 0xFFFFFFFFF000ULL) | tmp; 1689f71d0a05SDoug Thompson 1690f71d0a05SDoug Thompson /* remove channel interleave and hash */ 1691f71d0a05SDoug Thompson if (dct_interleave_enabled(pvt) && 1692f71d0a05SDoug Thompson !dct_high_range_enabled(pvt) && 1693f71d0a05SDoug Thompson !dct_ganging_enabled(pvt)) { 1694f71d0a05SDoug Thompson if (dct_sel_interleave_addr(pvt) != 1) 1695f71d0a05SDoug Thompson chan_addr = (chan_addr >> 1) & 0xFFFFFFFFFFFFFFC0ULL; 1696f71d0a05SDoug Thompson else { 1697f71d0a05SDoug Thompson tmp = chan_addr & 0xFC0; 1698f71d0a05SDoug Thompson chan_addr = ((chan_addr & 0xFFFFFFFFFFFFC000ULL) >> 1) 1699f71d0a05SDoug Thompson | tmp; 1700f71d0a05SDoug Thompson } 1701f71d0a05SDoug Thompson } 1702f71d0a05SDoug Thompson 1703f71d0a05SDoug Thompson debugf1(" (ChannelAddrLong=0x%llx) >> 8 becomes InputAddr=0x%x\n", 1704f71d0a05SDoug Thompson chan_addr, (u32)(chan_addr >> 8)); 1705f71d0a05SDoug Thompson 1706f71d0a05SDoug Thompson cs_found = f10_lookup_addr_in_dct(chan_addr >> 8, node_id, channel); 1707f71d0a05SDoug Thompson 1708f71d0a05SDoug Thompson if (cs_found >= 0) { 1709f71d0a05SDoug Thompson *nid = node_id; 1710f71d0a05SDoug Thompson *chan_sel = channel; 1711f71d0a05SDoug Thompson } 1712f71d0a05SDoug Thompson return cs_found; 1713f71d0a05SDoug Thompson } 1714f71d0a05SDoug Thompson 1715f71d0a05SDoug Thompson static int f10_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr, 1716f71d0a05SDoug Thompson int *node, int *chan_sel) 1717f71d0a05SDoug Thompson { 1718f71d0a05SDoug Thompson int dram_range, cs_found = -EINVAL; 1719f71d0a05SDoug Thompson u64 dram_base, dram_limit; 1720f71d0a05SDoug Thompson 1721f71d0a05SDoug Thompson for (dram_range = 0; dram_range < DRAM_REG_COUNT; dram_range++) { 1722f71d0a05SDoug Thompson 1723f71d0a05SDoug Thompson if (!pvt->dram_rw_en[dram_range]) 1724f71d0a05SDoug Thompson continue; 1725f71d0a05SDoug Thompson 1726f71d0a05SDoug Thompson dram_base = pvt->dram_base[dram_range]; 1727f71d0a05SDoug Thompson dram_limit = pvt->dram_limit[dram_range]; 1728f71d0a05SDoug Thompson 1729f71d0a05SDoug Thompson if ((dram_base <= sys_addr) && (sys_addr <= dram_limit)) { 1730f71d0a05SDoug Thompson 1731f71d0a05SDoug Thompson cs_found = f10_match_to_this_node(pvt, dram_range, 1732f71d0a05SDoug Thompson sys_addr, node, 1733f71d0a05SDoug Thompson chan_sel); 1734f71d0a05SDoug Thompson if (cs_found >= 0) 1735f71d0a05SDoug Thompson break; 1736f71d0a05SDoug Thompson } 1737f71d0a05SDoug Thompson } 1738f71d0a05SDoug Thompson return cs_found; 1739f71d0a05SDoug Thompson } 1740f71d0a05SDoug Thompson 1741f71d0a05SDoug Thompson /* 1742f71d0a05SDoug Thompson * This the F10h reference code from AMD to map a @sys_addr to NodeID, 1743f71d0a05SDoug Thompson * CSROW, Channel. 1744f71d0a05SDoug Thompson * 1745f71d0a05SDoug Thompson * The @sys_addr is usually an error address received from the hardware. 1746f71d0a05SDoug Thompson */ 1747f71d0a05SDoug Thompson static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci, 1748ef44cc4cSBorislav Petkov struct err_regs *info, 1749f71d0a05SDoug Thompson u64 sys_addr) 1750f71d0a05SDoug Thompson { 1751f71d0a05SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 1752f71d0a05SDoug Thompson u32 page, offset; 1753f71d0a05SDoug Thompson unsigned short syndrome; 1754f71d0a05SDoug Thompson int nid, csrow, chan = 0; 1755f71d0a05SDoug Thompson 1756f71d0a05SDoug Thompson csrow = f10_translate_sysaddr_to_cs(pvt, sys_addr, &nid, &chan); 1757f71d0a05SDoug Thompson 1758f71d0a05SDoug Thompson if (csrow >= 0) { 1759f71d0a05SDoug Thompson error_address_to_page_and_offset(sys_addr, &page, &offset); 1760f71d0a05SDoug Thompson 1761b70ef010SBorislav Petkov syndrome = HIGH_SYNDROME(info->nbsl) << 8; 1762b70ef010SBorislav Petkov syndrome |= LOW_SYNDROME(info->nbsh); 1763f71d0a05SDoug Thompson 1764f71d0a05SDoug Thompson /* 1765f71d0a05SDoug Thompson * Is CHIPKILL on? If so, then we can attempt to use the 1766f71d0a05SDoug Thompson * syndrome to isolate which channel the error was on. 1767f71d0a05SDoug Thompson */ 1768f71d0a05SDoug Thompson if (pvt->nbcfg & K8_NBCFG_CHIPKILL) 1769f71d0a05SDoug Thompson chan = get_channel_from_ecc_syndrome(syndrome); 1770f71d0a05SDoug Thompson 1771f71d0a05SDoug Thompson if (chan >= 0) { 1772f71d0a05SDoug Thompson edac_mc_handle_ce(mci, page, offset, syndrome, 1773f71d0a05SDoug Thompson csrow, chan, EDAC_MOD_STR); 1774f71d0a05SDoug Thompson } else { 1775f71d0a05SDoug Thompson /* 1776f71d0a05SDoug Thompson * Channel unknown, report all channels on this 1777f71d0a05SDoug Thompson * CSROW as failed. 1778f71d0a05SDoug Thompson */ 1779f71d0a05SDoug Thompson for (chan = 0; chan < mci->csrows[csrow].nr_channels; 1780f71d0a05SDoug Thompson chan++) { 1781f71d0a05SDoug Thompson edac_mc_handle_ce(mci, page, offset, 1782f71d0a05SDoug Thompson syndrome, 1783f71d0a05SDoug Thompson csrow, chan, 1784f71d0a05SDoug Thompson EDAC_MOD_STR); 1785f71d0a05SDoug Thompson } 1786f71d0a05SDoug Thompson } 1787f71d0a05SDoug Thompson 1788f71d0a05SDoug Thompson } else { 1789f71d0a05SDoug Thompson edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); 1790f71d0a05SDoug Thompson } 1791f71d0a05SDoug Thompson } 1792f71d0a05SDoug Thompson 1793f71d0a05SDoug Thompson /* 1794f71d0a05SDoug Thompson * Input (@index) is the DBAM DIMM value (1 of 4) used as an index into a shift 1795f71d0a05SDoug Thompson * table (revf_quad_ddr2_shift) which starts at 128MB DIMM size. Index of 0 1796f71d0a05SDoug Thompson * indicates an empty DIMM slot, as reported by Hardware on empty slots. 1797f71d0a05SDoug Thompson * 1798f71d0a05SDoug Thompson * Normalize to 128MB by subracting 27 bit shift. 1799f71d0a05SDoug Thompson */ 1800f71d0a05SDoug Thompson static int map_dbam_to_csrow_size(int index) 1801f71d0a05SDoug Thompson { 1802f71d0a05SDoug Thompson int mega_bytes = 0; 1803f71d0a05SDoug Thompson 1804f71d0a05SDoug Thompson if (index > 0 && index <= DBAM_MAX_VALUE) 1805f71d0a05SDoug Thompson mega_bytes = ((128 << (revf_quad_ddr2_shift[index]-27))); 1806f71d0a05SDoug Thompson 1807f71d0a05SDoug Thompson return mega_bytes; 1808f71d0a05SDoug Thompson } 1809f71d0a05SDoug Thompson 1810f71d0a05SDoug Thompson /* 1811f71d0a05SDoug Thompson * debug routine to display the memory sizes of a DIMM (ganged or not) and it 1812f71d0a05SDoug Thompson * CSROWs as well 1813f71d0a05SDoug Thompson */ 1814f71d0a05SDoug Thompson static void f10_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt, 1815f71d0a05SDoug Thompson int ganged) 1816f71d0a05SDoug Thompson { 1817f71d0a05SDoug Thompson int dimm, size0, size1; 1818f71d0a05SDoug Thompson u32 dbam; 1819f71d0a05SDoug Thompson u32 *dcsb; 1820f71d0a05SDoug Thompson 1821f71d0a05SDoug Thompson debugf1(" dbam%d: 0x%8.08x CSROW is %s\n", ctrl, 1822f71d0a05SDoug Thompson ctrl ? pvt->dbam1 : pvt->dbam0, 1823f71d0a05SDoug Thompson ganged ? "GANGED - dbam1 not used" : "NON-GANGED"); 1824f71d0a05SDoug Thompson 1825f71d0a05SDoug Thompson dbam = ctrl ? pvt->dbam1 : pvt->dbam0; 1826f71d0a05SDoug Thompson dcsb = ctrl ? pvt->dcsb1 : pvt->dcsb0; 1827f71d0a05SDoug Thompson 1828f71d0a05SDoug Thompson /* Dump memory sizes for DIMM and its CSROWs */ 1829f71d0a05SDoug Thompson for (dimm = 0; dimm < 4; dimm++) { 1830f71d0a05SDoug Thompson 1831f71d0a05SDoug Thompson size0 = 0; 1832f71d0a05SDoug Thompson if (dcsb[dimm*2] & K8_DCSB_CS_ENABLE) 1833f71d0a05SDoug Thompson size0 = map_dbam_to_csrow_size(DBAM_DIMM(dimm, dbam)); 1834f71d0a05SDoug Thompson 1835f71d0a05SDoug Thompson size1 = 0; 1836f71d0a05SDoug Thompson if (dcsb[dimm*2 + 1] & K8_DCSB_CS_ENABLE) 1837f71d0a05SDoug Thompson size1 = map_dbam_to_csrow_size(DBAM_DIMM(dimm, dbam)); 1838f71d0a05SDoug Thompson 1839f71d0a05SDoug Thompson debugf1(" CTRL-%d DIMM-%d=%5dMB CSROW-%d=%5dMB " 1840f71d0a05SDoug Thompson "CSROW-%d=%5dMB\n", 1841f71d0a05SDoug Thompson ctrl, 1842f71d0a05SDoug Thompson dimm, 1843f71d0a05SDoug Thompson size0 + size1, 1844f71d0a05SDoug Thompson dimm * 2, 1845f71d0a05SDoug Thompson size0, 1846f71d0a05SDoug Thompson dimm * 2 + 1, 1847f71d0a05SDoug Thompson size1); 1848f71d0a05SDoug Thompson } 1849f71d0a05SDoug Thompson } 1850f71d0a05SDoug Thompson 1851f71d0a05SDoug Thompson /* 1852f71d0a05SDoug Thompson * Very early hardware probe on pci_probe thread to determine if this module 1853f71d0a05SDoug Thompson * supports the hardware. 1854f71d0a05SDoug Thompson * 1855f71d0a05SDoug Thompson * Return: 1856f71d0a05SDoug Thompson * 0 for OK 1857f71d0a05SDoug Thompson * 1 for error 1858f71d0a05SDoug Thompson */ 1859f71d0a05SDoug Thompson static int f10_probe_valid_hardware(struct amd64_pvt *pvt) 1860f71d0a05SDoug Thompson { 1861f71d0a05SDoug Thompson int ret = 0; 1862f71d0a05SDoug Thompson 1863f71d0a05SDoug Thompson /* 1864f71d0a05SDoug Thompson * If we are on a DDR3 machine, we don't know yet if 1865f71d0a05SDoug Thompson * we support that properly at this time 1866f71d0a05SDoug Thompson */ 1867f71d0a05SDoug Thompson if ((pvt->dchr0 & F10_DCHR_Ddr3Mode) || 1868f71d0a05SDoug Thompson (pvt->dchr1 & F10_DCHR_Ddr3Mode)) { 1869f71d0a05SDoug Thompson 1870f71d0a05SDoug Thompson amd64_printk(KERN_WARNING, 1871f71d0a05SDoug Thompson "%s() This machine is running with DDR3 memory. " 1872f71d0a05SDoug Thompson "This is not currently supported. " 1873f71d0a05SDoug Thompson "DCHR0=0x%x DCHR1=0x%x\n", 1874f71d0a05SDoug Thompson __func__, pvt->dchr0, pvt->dchr1); 1875f71d0a05SDoug Thompson 1876f71d0a05SDoug Thompson amd64_printk(KERN_WARNING, 1877f71d0a05SDoug Thompson " Contact '%s' module MAINTAINER to help add" 1878f71d0a05SDoug Thompson " support.\n", 1879f71d0a05SDoug Thompson EDAC_MOD_STR); 1880f71d0a05SDoug Thompson 1881f71d0a05SDoug Thompson ret = 1; 1882f71d0a05SDoug Thompson 1883f71d0a05SDoug Thompson } 1884f71d0a05SDoug Thompson return ret; 1885f71d0a05SDoug Thompson } 18866163b5d4SDoug Thompson 18874d37607aSDoug Thompson /* 18884d37607aSDoug Thompson * There currently are 3 types type of MC devices for AMD Athlon/Opterons 18894d37607aSDoug Thompson * (as per PCI DEVICE_IDs): 18904d37607aSDoug Thompson * 18914d37607aSDoug Thompson * Family K8: That is the Athlon64 and Opteron CPUs. They all have the same PCI 18924d37607aSDoug Thompson * DEVICE ID, even though there is differences between the different Revisions 18934d37607aSDoug Thompson * (CG,D,E,F). 18944d37607aSDoug Thompson * 18954d37607aSDoug Thompson * Family F10h and F11h. 18964d37607aSDoug Thompson * 18974d37607aSDoug Thompson */ 18984d37607aSDoug Thompson static struct amd64_family_type amd64_family_types[] = { 18994d37607aSDoug Thompson [K8_CPUS] = { 19004d37607aSDoug Thompson .ctl_name = "RevF", 19014d37607aSDoug Thompson .addr_f1_ctl = PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP, 19024d37607aSDoug Thompson .misc_f3_ctl = PCI_DEVICE_ID_AMD_K8_NB_MISC, 19034d37607aSDoug Thompson .ops = { 19044d37607aSDoug Thompson .early_channel_count = k8_early_channel_count, 19054d37607aSDoug Thompson .get_error_address = k8_get_error_address, 19064d37607aSDoug Thompson .read_dram_base_limit = k8_read_dram_base_limit, 19074d37607aSDoug Thompson .map_sysaddr_to_csrow = k8_map_sysaddr_to_csrow, 19084d37607aSDoug Thompson .dbam_map_to_pages = k8_dbam_map_to_pages, 19094d37607aSDoug Thompson } 19104d37607aSDoug Thompson }, 19114d37607aSDoug Thompson [F10_CPUS] = { 19124d37607aSDoug Thompson .ctl_name = "Family 10h", 19134d37607aSDoug Thompson .addr_f1_ctl = PCI_DEVICE_ID_AMD_10H_NB_MAP, 19144d37607aSDoug Thompson .misc_f3_ctl = PCI_DEVICE_ID_AMD_10H_NB_MISC, 19154d37607aSDoug Thompson .ops = { 19164d37607aSDoug Thompson .probe_valid_hardware = f10_probe_valid_hardware, 19174d37607aSDoug Thompson .early_channel_count = f10_early_channel_count, 19184d37607aSDoug Thompson .get_error_address = f10_get_error_address, 19194d37607aSDoug Thompson .read_dram_base_limit = f10_read_dram_base_limit, 19204d37607aSDoug Thompson .read_dram_ctl_register = f10_read_dram_ctl_register, 19214d37607aSDoug Thompson .map_sysaddr_to_csrow = f10_map_sysaddr_to_csrow, 19224d37607aSDoug Thompson .dbam_map_to_pages = f10_dbam_map_to_pages, 19234d37607aSDoug Thompson } 19244d37607aSDoug Thompson }, 19254d37607aSDoug Thompson [F11_CPUS] = { 19264d37607aSDoug Thompson .ctl_name = "Family 11h", 19274d37607aSDoug Thompson .addr_f1_ctl = PCI_DEVICE_ID_AMD_11H_NB_MAP, 19284d37607aSDoug Thompson .misc_f3_ctl = PCI_DEVICE_ID_AMD_11H_NB_MISC, 19294d37607aSDoug Thompson .ops = { 19304d37607aSDoug Thompson .probe_valid_hardware = f10_probe_valid_hardware, 19314d37607aSDoug Thompson .early_channel_count = f10_early_channel_count, 19324d37607aSDoug Thompson .get_error_address = f10_get_error_address, 19334d37607aSDoug Thompson .read_dram_base_limit = f10_read_dram_base_limit, 19344d37607aSDoug Thompson .read_dram_ctl_register = f10_read_dram_ctl_register, 19354d37607aSDoug Thompson .map_sysaddr_to_csrow = f10_map_sysaddr_to_csrow, 19364d37607aSDoug Thompson .dbam_map_to_pages = f10_dbam_map_to_pages, 19374d37607aSDoug Thompson } 19384d37607aSDoug Thompson }, 19394d37607aSDoug Thompson }; 19404d37607aSDoug Thompson 19414d37607aSDoug Thompson static struct pci_dev *pci_get_related_function(unsigned int vendor, 19424d37607aSDoug Thompson unsigned int device, 19434d37607aSDoug Thompson struct pci_dev *related) 19444d37607aSDoug Thompson { 19454d37607aSDoug Thompson struct pci_dev *dev = NULL; 19464d37607aSDoug Thompson 19474d37607aSDoug Thompson dev = pci_get_device(vendor, device, dev); 19484d37607aSDoug Thompson while (dev) { 19494d37607aSDoug Thompson if ((dev->bus->number == related->bus->number) && 19504d37607aSDoug Thompson (PCI_SLOT(dev->devfn) == PCI_SLOT(related->devfn))) 19514d37607aSDoug Thompson break; 19524d37607aSDoug Thompson dev = pci_get_device(vendor, device, dev); 19534d37607aSDoug Thompson } 19544d37607aSDoug Thompson 19554d37607aSDoug Thompson return dev; 19564d37607aSDoug Thompson } 19574d37607aSDoug Thompson 1958b1289d6fSDoug Thompson /* 1959b1289d6fSDoug Thompson * syndrome mapping table for ECC ChipKill devices 1960b1289d6fSDoug Thompson * 1961b1289d6fSDoug Thompson * The comment in each row is the token (nibble) number that is in error. 1962b1289d6fSDoug Thompson * The least significant nibble of the syndrome is the mask for the bits 1963b1289d6fSDoug Thompson * that are in error (need to be toggled) for the particular nibble. 1964b1289d6fSDoug Thompson * 1965b1289d6fSDoug Thompson * Each row contains 16 entries. 1966b1289d6fSDoug Thompson * The first entry (0th) is the channel number for that row of syndromes. 1967b1289d6fSDoug Thompson * The remaining 15 entries are the syndromes for the respective Error 1968b1289d6fSDoug Thompson * bit mask index. 1969b1289d6fSDoug Thompson * 1970b1289d6fSDoug Thompson * 1st index entry is 0x0001 mask, indicating that the rightmost bit is the 1971b1289d6fSDoug Thompson * bit in error. 1972b1289d6fSDoug Thompson * The 2nd index entry is 0x0010 that the second bit is damaged. 1973b1289d6fSDoug Thompson * The 3rd index entry is 0x0011 indicating that the rightmost 2 bits 1974b1289d6fSDoug Thompson * are damaged. 1975b1289d6fSDoug Thompson * Thus so on until index 15, 0x1111, whose entry has the syndrome 1976b1289d6fSDoug Thompson * indicating that all 4 bits are damaged. 1977b1289d6fSDoug Thompson * 1978b1289d6fSDoug Thompson * A search is performed on this table looking for a given syndrome. 1979b1289d6fSDoug Thompson * 1980b1289d6fSDoug Thompson * See the AMD documentation for ECC syndromes. This ECC table is valid 1981b1289d6fSDoug Thompson * across all the versions of the AMD64 processors. 1982b1289d6fSDoug Thompson * 1983b1289d6fSDoug Thompson * A fast lookup is to use the LAST four bits of the 16-bit syndrome as a 1984b1289d6fSDoug Thompson * COLUMN index, then search all ROWS of that column, looking for a match 1985b1289d6fSDoug Thompson * with the input syndrome. The ROW value will be the token number. 1986b1289d6fSDoug Thompson * 1987b1289d6fSDoug Thompson * The 0'th entry on that row, can be returned as the CHANNEL (0 or 1) of this 1988b1289d6fSDoug Thompson * error. 1989b1289d6fSDoug Thompson */ 1990b1289d6fSDoug Thompson #define NUMBER_ECC_ROWS 36 1991b1289d6fSDoug Thompson static const unsigned short ecc_chipkill_syndromes[NUMBER_ECC_ROWS][16] = { 1992b1289d6fSDoug Thompson /* Channel 0 syndromes */ 1993b1289d6fSDoug Thompson {/*0*/ 0, 0xe821, 0x7c32, 0x9413, 0xbb44, 0x5365, 0xc776, 0x2f57, 1994b1289d6fSDoug Thompson 0xdd88, 0x35a9, 0xa1ba, 0x499b, 0x66cc, 0x8eed, 0x1afe, 0xf2df }, 1995b1289d6fSDoug Thompson {/*1*/ 0, 0x5d31, 0xa612, 0xfb23, 0x9584, 0xc8b5, 0x3396, 0x6ea7, 1996b1289d6fSDoug Thompson 0xeac8, 0xb7f9, 0x4cda, 0x11eb, 0x7f4c, 0x227d, 0xd95e, 0x846f }, 1997b1289d6fSDoug Thompson {/*2*/ 0, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0006, 0x0007, 1998b1289d6fSDoug Thompson 0x0008, 0x0009, 0x000a, 0x000b, 0x000c, 0x000d, 0x000e, 0x000f }, 1999b1289d6fSDoug Thompson {/*3*/ 0, 0x2021, 0x3032, 0x1013, 0x4044, 0x6065, 0x7076, 0x5057, 2000b1289d6fSDoug Thompson 0x8088, 0xa0a9, 0xb0ba, 0x909b, 0xc0cc, 0xe0ed, 0xf0fe, 0xd0df }, 2001b1289d6fSDoug Thompson {/*4*/ 0, 0x5041, 0xa082, 0xf0c3, 0x9054, 0xc015, 0x30d6, 0x6097, 2002b1289d6fSDoug Thompson 0xe0a8, 0xb0e9, 0x402a, 0x106b, 0x70fc, 0x20bd, 0xd07e, 0x803f }, 2003b1289d6fSDoug Thompson {/*5*/ 0, 0xbe21, 0xd732, 0x6913, 0x2144, 0x9f65, 0xf676, 0x4857, 2004b1289d6fSDoug Thompson 0x3288, 0x8ca9, 0xe5ba, 0x5b9b, 0x13cc, 0xaded, 0xc4fe, 0x7adf }, 2005b1289d6fSDoug Thompson {/*6*/ 0, 0x4951, 0x8ea2, 0xc7f3, 0x5394, 0x1ac5, 0xdd36, 0x9467, 2006b1289d6fSDoug Thompson 0xa1e8, 0xe8b9, 0x2f4a, 0x661b, 0xf27c, 0xbb2d, 0x7cde, 0x358f }, 2007b1289d6fSDoug Thompson {/*7*/ 0, 0x74e1, 0x9872, 0xec93, 0xd6b4, 0xa255, 0x4ec6, 0x3a27, 2008b1289d6fSDoug Thompson 0x6bd8, 0x1f39, 0xf3aa, 0x874b, 0xbd6c, 0xc98d, 0x251e, 0x51ff }, 2009b1289d6fSDoug Thompson {/*8*/ 0, 0x15c1, 0x2a42, 0x3f83, 0xcef4, 0xdb35, 0xe4b6, 0xf177, 2010b1289d6fSDoug Thompson 0x4758, 0x5299, 0x6d1a, 0x78db, 0x89ac, 0x9c6d, 0xa3ee, 0xb62f }, 2011b1289d6fSDoug Thompson {/*9*/ 0, 0x3d01, 0x1602, 0x2b03, 0x8504, 0xb805, 0x9306, 0xae07, 2012b1289d6fSDoug Thompson 0xca08, 0xf709, 0xdc0a, 0xe10b, 0x4f0c, 0x720d, 0x590e, 0x640f }, 2013b1289d6fSDoug Thompson {/*a*/ 0, 0x9801, 0xec02, 0x7403, 0x6b04, 0xf305, 0x8706, 0x1f07, 2014b1289d6fSDoug Thompson 0xbd08, 0x2509, 0x510a, 0xc90b, 0xd60c, 0x4e0d, 0x3a0e, 0xa20f }, 2015b1289d6fSDoug Thompson {/*b*/ 0, 0xd131, 0x6212, 0xb323, 0x3884, 0xe9b5, 0x5a96, 0x8ba7, 2016b1289d6fSDoug Thompson 0x1cc8, 0xcdf9, 0x7eda, 0xafeb, 0x244c, 0xf57d, 0x465e, 0x976f }, 2017b1289d6fSDoug Thompson {/*c*/ 0, 0xe1d1, 0x7262, 0x93b3, 0xb834, 0x59e5, 0xca56, 0x2b87, 2018b1289d6fSDoug Thompson 0xdc18, 0x3dc9, 0xae7a, 0x4fab, 0x542c, 0x85fd, 0x164e, 0xf79f }, 2019b1289d6fSDoug Thompson {/*d*/ 0, 0x6051, 0xb0a2, 0xd0f3, 0x1094, 0x70c5, 0xa036, 0xc067, 2020b1289d6fSDoug Thompson 0x20e8, 0x40b9, 0x904a, 0x601b, 0x307c, 0x502d, 0x80de, 0xe08f }, 2021b1289d6fSDoug Thompson {/*e*/ 0, 0xa4c1, 0xf842, 0x5c83, 0xe6f4, 0x4235, 0x1eb6, 0xba77, 2022b1289d6fSDoug Thompson 0x7b58, 0xdf99, 0x831a, 0x27db, 0x9dac, 0x396d, 0x65ee, 0xc12f }, 2023b1289d6fSDoug Thompson {/*f*/ 0, 0x11c1, 0x2242, 0x3383, 0xc8f4, 0xd935, 0xeab6, 0xfb77, 2024b1289d6fSDoug Thompson 0x4c58, 0x5d99, 0x6e1a, 0x7fdb, 0x84ac, 0x956d, 0xa6ee, 0xb72f }, 20254d37607aSDoug Thompson 2026b1289d6fSDoug Thompson /* Channel 1 syndromes */ 2027b1289d6fSDoug Thompson {/*10*/ 1, 0x45d1, 0x8a62, 0xcfb3, 0x5e34, 0x1be5, 0xd456, 0x9187, 2028b1289d6fSDoug Thompson 0xa718, 0xe2c9, 0x2d7a, 0x68ab, 0xf92c, 0xbcfd, 0x734e, 0x369f }, 2029b1289d6fSDoug Thompson {/*11*/ 1, 0x63e1, 0xb172, 0xd293, 0x14b4, 0x7755, 0xa5c6, 0xc627, 2030b1289d6fSDoug Thompson 0x28d8, 0x4b39, 0x99aa, 0xfa4b, 0x3c6c, 0x5f8d, 0x8d1e, 0xeeff }, 2031b1289d6fSDoug Thompson {/*12*/ 1, 0xb741, 0xd982, 0x6ec3, 0x2254, 0x9515, 0xfbd6, 0x4c97, 2032b1289d6fSDoug Thompson 0x33a8, 0x84e9, 0xea2a, 0x5d6b, 0x11fc, 0xa6bd, 0xc87e, 0x7f3f }, 2033b1289d6fSDoug Thompson {/*13*/ 1, 0xdd41, 0x6682, 0xbbc3, 0x3554, 0xe815, 0x53d6, 0xce97, 2034b1289d6fSDoug Thompson 0x1aa8, 0xc7e9, 0x7c2a, 0xa1fb, 0x2ffc, 0xf2bd, 0x497e, 0x943f }, 2035b1289d6fSDoug Thompson {/*14*/ 1, 0x2bd1, 0x3d62, 0x16b3, 0x4f34, 0x64e5, 0x7256, 0x5987, 2036b1289d6fSDoug Thompson 0x8518, 0xaec9, 0xb87a, 0x93ab, 0xca2c, 0xe1fd, 0xf74e, 0xdc9f }, 2037b1289d6fSDoug Thompson {/*15*/ 1, 0x83c1, 0xc142, 0x4283, 0xa4f4, 0x2735, 0x65b6, 0xe677, 2038b1289d6fSDoug Thompson 0xf858, 0x7b99, 0x391a, 0xbadb, 0x5cac, 0xdf6d, 0x9dee, 0x1e2f }, 2039b1289d6fSDoug Thompson {/*16*/ 1, 0x8fd1, 0xc562, 0x4ab3, 0xa934, 0x26e5, 0x6c56, 0xe387, 2040b1289d6fSDoug Thompson 0xfe18, 0x71c9, 0x3b7a, 0xb4ab, 0x572c, 0xd8fd, 0x924e, 0x1d9f }, 2041b1289d6fSDoug Thompson {/*17*/ 1, 0x4791, 0x89e2, 0xce73, 0x5264, 0x15f5, 0xdb86, 0x9c17, 2042b1289d6fSDoug Thompson 0xa3b8, 0xe429, 0x2a5a, 0x6dcb, 0xf1dc, 0xb64d, 0x783e, 0x3faf }, 2043b1289d6fSDoug Thompson {/*18*/ 1, 0x5781, 0xa9c2, 0xfe43, 0x92a4, 0xc525, 0x3b66, 0x6ce7, 2044b1289d6fSDoug Thompson 0xe3f8, 0xb479, 0x4a3a, 0x1dbb, 0x715c, 0x26dd, 0xd89e, 0x8f1f }, 2045b1289d6fSDoug Thompson {/*19*/ 1, 0xbf41, 0xd582, 0x6ac3, 0x2954, 0x9615, 0xfcd6, 0x4397, 2046b1289d6fSDoug Thompson 0x3ea8, 0x81e9, 0xeb2a, 0x546b, 0x17fc, 0xa8bd, 0xc27e, 0x7d3f }, 2047b1289d6fSDoug Thompson {/*1a*/ 1, 0x9891, 0xe1e2, 0x7273, 0x6464, 0xf7f5, 0x8586, 0x1617, 2048b1289d6fSDoug Thompson 0xb8b8, 0x2b29, 0x595a, 0xcacb, 0xdcdc, 0x4f4d, 0x3d3e, 0xaeaf }, 2049b1289d6fSDoug Thompson {/*1b*/ 1, 0xcce1, 0x4472, 0x8893, 0xfdb4, 0x3f55, 0xb9c6, 0x7527, 2050b1289d6fSDoug Thompson 0x56d8, 0x9a39, 0x12aa, 0xde4b, 0xab6c, 0x678d, 0xef1e, 0x23ff }, 2051b1289d6fSDoug Thompson {/*1c*/ 1, 0xa761, 0xf9b2, 0x5ed3, 0xe214, 0x4575, 0x1ba6, 0xbcc7, 2052b1289d6fSDoug Thompson 0x7328, 0xd449, 0x8a9a, 0x2dfb, 0x913c, 0x365d, 0x688e, 0xcfef }, 2053b1289d6fSDoug Thompson {/*1d*/ 1, 0xff61, 0x55b2, 0xaad3, 0x7914, 0x8675, 0x2ca6, 0xd3c7, 2054b1289d6fSDoug Thompson 0x9e28, 0x6149, 0xcb9a, 0x34fb, 0xe73c, 0x185d, 0xb28e, 0x4def }, 2055b1289d6fSDoug Thompson {/*1e*/ 1, 0x5451, 0xa8a2, 0xfcf3, 0x9694, 0xc2c5, 0x3e36, 0x6a67, 2056b1289d6fSDoug Thompson 0xebe8, 0xbfb9, 0x434a, 0x171b, 0x7d7c, 0x292d, 0xd5de, 0x818f }, 2057b1289d6fSDoug Thompson {/*1f*/ 1, 0x6fc1, 0xb542, 0xda83, 0x19f4, 0x7635, 0xacb6, 0xc377, 2058b1289d6fSDoug Thompson 0x2e58, 0x4199, 0x9b1a, 0xf4db, 0x37ac, 0x586d, 0x82ee, 0xed2f }, 2059b1289d6fSDoug Thompson 2060b1289d6fSDoug Thompson /* ECC bits are also in the set of tokens and they too can go bad 2061b1289d6fSDoug Thompson * first 2 cover channel 0, while the second 2 cover channel 1 2062b1289d6fSDoug Thompson */ 2063b1289d6fSDoug Thompson {/*20*/ 0, 0xbe01, 0xd702, 0x6903, 0x2104, 0x9f05, 0xf606, 0x4807, 2064b1289d6fSDoug Thompson 0x3208, 0x8c09, 0xe50a, 0x5b0b, 0x130c, 0xad0d, 0xc40e, 0x7a0f }, 2065b1289d6fSDoug Thompson {/*21*/ 0, 0x4101, 0x8202, 0xc303, 0x5804, 0x1905, 0xda06, 0x9b07, 2066b1289d6fSDoug Thompson 0xac08, 0xed09, 0x2e0a, 0x6f0b, 0x640c, 0xb50d, 0x760e, 0x370f }, 2067b1289d6fSDoug Thompson {/*22*/ 1, 0xc441, 0x4882, 0x8cc3, 0xf654, 0x3215, 0xbed6, 0x7a97, 2068b1289d6fSDoug Thompson 0x5ba8, 0x9fe9, 0x132a, 0xd76b, 0xadfc, 0x69bd, 0xe57e, 0x213f }, 2069b1289d6fSDoug Thompson {/*23*/ 1, 0x7621, 0x9b32, 0xed13, 0xda44, 0xac65, 0x4176, 0x3757, 2070b1289d6fSDoug Thompson 0x6f88, 0x19a9, 0xf4ba, 0x829b, 0xb5cc, 0xc3ed, 0x2efe, 0x58df } 2071b1289d6fSDoug Thompson }; 2072b1289d6fSDoug Thompson 2073b1289d6fSDoug Thompson /* 2074b1289d6fSDoug Thompson * Given the syndrome argument, scan each of the channel tables for a syndrome 2075b1289d6fSDoug Thompson * match. Depending on which table it is found, return the channel number. 2076b1289d6fSDoug Thompson */ 2077b1289d6fSDoug Thompson static int get_channel_from_ecc_syndrome(unsigned short syndrome) 2078b1289d6fSDoug Thompson { 2079b1289d6fSDoug Thompson int row; 2080b1289d6fSDoug Thompson int column; 2081b1289d6fSDoug Thompson 2082b1289d6fSDoug Thompson /* Determine column to scan */ 2083b1289d6fSDoug Thompson column = syndrome & 0xF; 2084b1289d6fSDoug Thompson 2085b1289d6fSDoug Thompson /* Scan all rows, looking for syndrome, or end of table */ 2086b1289d6fSDoug Thompson for (row = 0; row < NUMBER_ECC_ROWS; row++) { 2087b1289d6fSDoug Thompson if (ecc_chipkill_syndromes[row][column] == syndrome) 2088b1289d6fSDoug Thompson return ecc_chipkill_syndromes[row][0]; 2089b1289d6fSDoug Thompson } 2090b1289d6fSDoug Thompson 2091b1289d6fSDoug Thompson debugf0("syndrome(%x) not found\n", syndrome); 2092b1289d6fSDoug Thompson return -1; 2093b1289d6fSDoug Thompson } 2094d27bf6faSDoug Thompson 2095d27bf6faSDoug Thompson /* 2096d27bf6faSDoug Thompson * Check for valid error in the NB Status High register. If so, proceed to read 2097d27bf6faSDoug Thompson * NB Status Low, NB Address Low and NB Address High registers and store data 2098d27bf6faSDoug Thompson * into error structure. 2099d27bf6faSDoug Thompson * 2100d27bf6faSDoug Thompson * Returns: 2101d27bf6faSDoug Thompson * - 1: if hardware regs contains valid error info 2102d27bf6faSDoug Thompson * - 0: if no valid error is indicated 2103d27bf6faSDoug Thompson */ 2104d27bf6faSDoug Thompson static int amd64_get_error_info_regs(struct mem_ctl_info *mci, 2105ef44cc4cSBorislav Petkov struct err_regs *regs) 2106d27bf6faSDoug Thompson { 2107d27bf6faSDoug Thompson struct amd64_pvt *pvt; 2108d27bf6faSDoug Thompson struct pci_dev *misc_f3_ctl; 2109d27bf6faSDoug Thompson int err = 0; 2110d27bf6faSDoug Thompson 2111d27bf6faSDoug Thompson pvt = mci->pvt_info; 2112d27bf6faSDoug Thompson misc_f3_ctl = pvt->misc_f3_ctl; 2113d27bf6faSDoug Thompson 2114d27bf6faSDoug Thompson err = pci_read_config_dword(misc_f3_ctl, K8_NBSH, ®s->nbsh); 2115d27bf6faSDoug Thompson if (err) 2116d27bf6faSDoug Thompson goto err_reg; 2117d27bf6faSDoug Thompson 2118d27bf6faSDoug Thompson if (!(regs->nbsh & K8_NBSH_VALID_BIT)) 2119d27bf6faSDoug Thompson return 0; 2120d27bf6faSDoug Thompson 2121d27bf6faSDoug Thompson /* valid error, read remaining error information registers */ 2122d27bf6faSDoug Thompson err = pci_read_config_dword(misc_f3_ctl, K8_NBSL, ®s->nbsl); 2123d27bf6faSDoug Thompson if (err) 2124d27bf6faSDoug Thompson goto err_reg; 2125d27bf6faSDoug Thompson 2126d27bf6faSDoug Thompson err = pci_read_config_dword(misc_f3_ctl, K8_NBEAL, ®s->nbeal); 2127d27bf6faSDoug Thompson if (err) 2128d27bf6faSDoug Thompson goto err_reg; 2129d27bf6faSDoug Thompson 2130d27bf6faSDoug Thompson err = pci_read_config_dword(misc_f3_ctl, K8_NBEAH, ®s->nbeah); 2131d27bf6faSDoug Thompson if (err) 2132d27bf6faSDoug Thompson goto err_reg; 2133d27bf6faSDoug Thompson 2134d27bf6faSDoug Thompson err = pci_read_config_dword(misc_f3_ctl, K8_NBCFG, ®s->nbcfg); 2135d27bf6faSDoug Thompson if (err) 2136d27bf6faSDoug Thompson goto err_reg; 2137d27bf6faSDoug Thompson 2138d27bf6faSDoug Thompson return 1; 2139d27bf6faSDoug Thompson 2140d27bf6faSDoug Thompson err_reg: 2141d27bf6faSDoug Thompson debugf0("Reading error info register failed\n"); 2142d27bf6faSDoug Thompson return 0; 2143d27bf6faSDoug Thompson } 2144d27bf6faSDoug Thompson 2145d27bf6faSDoug Thompson /* 2146d27bf6faSDoug Thompson * This function is called to retrieve the error data from hardware and store it 2147d27bf6faSDoug Thompson * in the info structure. 2148d27bf6faSDoug Thompson * 2149d27bf6faSDoug Thompson * Returns: 2150d27bf6faSDoug Thompson * - 1: if a valid error is found 2151d27bf6faSDoug Thompson * - 0: if no error is found 2152d27bf6faSDoug Thompson */ 2153d27bf6faSDoug Thompson static int amd64_get_error_info(struct mem_ctl_info *mci, 2154ef44cc4cSBorislav Petkov struct err_regs *info) 2155d27bf6faSDoug Thompson { 2156d27bf6faSDoug Thompson struct amd64_pvt *pvt; 2157ef44cc4cSBorislav Petkov struct err_regs regs; 2158d27bf6faSDoug Thompson 2159d27bf6faSDoug Thompson pvt = mci->pvt_info; 2160d27bf6faSDoug Thompson 2161d27bf6faSDoug Thompson if (!amd64_get_error_info_regs(mci, info)) 2162d27bf6faSDoug Thompson return 0; 2163d27bf6faSDoug Thompson 2164d27bf6faSDoug Thompson /* 2165d27bf6faSDoug Thompson * Here's the problem with the K8's EDAC reporting: There are four 2166d27bf6faSDoug Thompson * registers which report pieces of error information. They are shared 2167d27bf6faSDoug Thompson * between CEs and UEs. Furthermore, contrary to what is stated in the 2168d27bf6faSDoug Thompson * BKDG, the overflow bit is never used! Every error always updates the 2169d27bf6faSDoug Thompson * reporting registers. 2170d27bf6faSDoug Thompson * 2171d27bf6faSDoug Thompson * Can you see the race condition? All four error reporting registers 2172d27bf6faSDoug Thompson * must be read before a new error updates them! There is no way to read 2173d27bf6faSDoug Thompson * all four registers atomically. The best than can be done is to detect 2174d27bf6faSDoug Thompson * that a race has occured and then report the error without any kind of 2175d27bf6faSDoug Thompson * precision. 2176d27bf6faSDoug Thompson * 2177d27bf6faSDoug Thompson * What is still positive is that errors are still reported and thus 2178d27bf6faSDoug Thompson * problems can still be detected - just not localized because the 2179d27bf6faSDoug Thompson * syndrome and address are spread out across registers. 2180d27bf6faSDoug Thompson * 2181d27bf6faSDoug Thompson * Grrrrr!!!!! Here's hoping that AMD fixes this in some future K8 rev. 2182d27bf6faSDoug Thompson * UEs and CEs should have separate register sets with proper overflow 2183d27bf6faSDoug Thompson * bits that are used! At very least the problem can be fixed by 2184d27bf6faSDoug Thompson * honoring the ErrValid bit in 'nbsh' and not updating registers - just 2185d27bf6faSDoug Thompson * set the overflow bit - unless the current error is CE and the new 2186d27bf6faSDoug Thompson * error is UE which would be the only situation for overwriting the 2187d27bf6faSDoug Thompson * current values. 2188d27bf6faSDoug Thompson */ 2189d27bf6faSDoug Thompson 2190d27bf6faSDoug Thompson regs = *info; 2191d27bf6faSDoug Thompson 2192d27bf6faSDoug Thompson /* Use info from the second read - most current */ 2193d27bf6faSDoug Thompson if (unlikely(!amd64_get_error_info_regs(mci, info))) 2194d27bf6faSDoug Thompson return 0; 2195d27bf6faSDoug Thompson 2196d27bf6faSDoug Thompson /* clear the error bits in hardware */ 2197d27bf6faSDoug Thompson pci_write_bits32(pvt->misc_f3_ctl, K8_NBSH, 0, K8_NBSH_VALID_BIT); 2198d27bf6faSDoug Thompson 2199d27bf6faSDoug Thompson /* Check for the possible race condition */ 2200d27bf6faSDoug Thompson if ((regs.nbsh != info->nbsh) || 2201d27bf6faSDoug Thompson (regs.nbsl != info->nbsl) || 2202d27bf6faSDoug Thompson (regs.nbeah != info->nbeah) || 2203d27bf6faSDoug Thompson (regs.nbeal != info->nbeal)) { 2204d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_WARNING, 2205d27bf6faSDoug Thompson "hardware STATUS read access race condition " 2206d27bf6faSDoug Thompson "detected!\n"); 2207d27bf6faSDoug Thompson return 0; 2208d27bf6faSDoug Thompson } 2209d27bf6faSDoug Thompson return 1; 2210d27bf6faSDoug Thompson } 2211d27bf6faSDoug Thompson 2212d27bf6faSDoug Thompson static inline void amd64_decode_gart_tlb_error(struct mem_ctl_info *mci, 2213ef44cc4cSBorislav Petkov struct err_regs *info) 2214d27bf6faSDoug Thompson { 2215b70ef010SBorislav Petkov u32 ec = ERROR_CODE(info->nbsl); 2216d27bf6faSDoug Thompson 2217d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_ERR, 2218d27bf6faSDoug Thompson "GART TLB event: transaction type(%s), " 2219b70ef010SBorislav Petkov "cache level(%s)\n", TT_MSG(ec), LL_MSG(ec)); 2220d27bf6faSDoug Thompson } 2221d27bf6faSDoug Thompson 2222d27bf6faSDoug Thompson static inline void amd64_decode_mem_cache_error(struct mem_ctl_info *mci, 2223ef44cc4cSBorislav Petkov struct err_regs *info) 2224d27bf6faSDoug Thompson { 2225b70ef010SBorislav Petkov u32 ec = ERROR_CODE(info->nbsl); 2226d27bf6faSDoug Thompson 2227d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_ERR, 2228d27bf6faSDoug Thompson "cache hierarchy error: memory transaction type(%s), " 2229d27bf6faSDoug Thompson "transaction type(%s), cache level(%s)\n", 2230b70ef010SBorislav Petkov RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec)); 2231d27bf6faSDoug Thompson } 2232d27bf6faSDoug Thompson 2233d27bf6faSDoug Thompson 2234d27bf6faSDoug Thompson /* 2235d27bf6faSDoug Thompson * Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR 2236d27bf6faSDoug Thompson * ADDRESS and process. 2237d27bf6faSDoug Thompson */ 2238d27bf6faSDoug Thompson static void amd64_handle_ce(struct mem_ctl_info *mci, 2239ef44cc4cSBorislav Petkov struct err_regs *info) 2240d27bf6faSDoug Thompson { 2241d27bf6faSDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 2242d27bf6faSDoug Thompson u64 SystemAddress; 2243d27bf6faSDoug Thompson 2244d27bf6faSDoug Thompson /* Ensure that the Error Address is VALID */ 2245d27bf6faSDoug Thompson if ((info->nbsh & K8_NBSH_VALID_ERROR_ADDR) == 0) { 2246d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_ERR, 2247d27bf6faSDoug Thompson "HW has no ERROR_ADDRESS available\n"); 2248d27bf6faSDoug Thompson edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR); 2249d27bf6faSDoug Thompson return; 2250d27bf6faSDoug Thompson } 2251d27bf6faSDoug Thompson 2252d27bf6faSDoug Thompson SystemAddress = extract_error_address(mci, info); 2253d27bf6faSDoug Thompson 2254d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_ERR, 2255d27bf6faSDoug Thompson "CE ERROR_ADDRESS= 0x%llx\n", SystemAddress); 2256d27bf6faSDoug Thompson 2257d27bf6faSDoug Thompson pvt->ops->map_sysaddr_to_csrow(mci, info, SystemAddress); 2258d27bf6faSDoug Thompson } 2259d27bf6faSDoug Thompson 2260d27bf6faSDoug Thompson /* Handle any Un-correctable Errors (UEs) */ 2261d27bf6faSDoug Thompson static void amd64_handle_ue(struct mem_ctl_info *mci, 2262ef44cc4cSBorislav Petkov struct err_regs *info) 2263d27bf6faSDoug Thompson { 2264d27bf6faSDoug Thompson int csrow; 2265d27bf6faSDoug Thompson u64 SystemAddress; 2266d27bf6faSDoug Thompson u32 page, offset; 2267d27bf6faSDoug Thompson struct mem_ctl_info *log_mci, *src_mci = NULL; 2268d27bf6faSDoug Thompson 2269d27bf6faSDoug Thompson log_mci = mci; 2270d27bf6faSDoug Thompson 2271d27bf6faSDoug Thompson if ((info->nbsh & K8_NBSH_VALID_ERROR_ADDR) == 0) { 2272d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_CRIT, 2273d27bf6faSDoug Thompson "HW has no ERROR_ADDRESS available\n"); 2274d27bf6faSDoug Thompson edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); 2275d27bf6faSDoug Thompson return; 2276d27bf6faSDoug Thompson } 2277d27bf6faSDoug Thompson 2278d27bf6faSDoug Thompson SystemAddress = extract_error_address(mci, info); 2279d27bf6faSDoug Thompson 2280d27bf6faSDoug Thompson /* 2281d27bf6faSDoug Thompson * Find out which node the error address belongs to. This may be 2282d27bf6faSDoug Thompson * different from the node that detected the error. 2283d27bf6faSDoug Thompson */ 2284d27bf6faSDoug Thompson src_mci = find_mc_by_sys_addr(mci, SystemAddress); 2285d27bf6faSDoug Thompson if (!src_mci) { 2286d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_CRIT, 2287d27bf6faSDoug Thompson "ERROR ADDRESS (0x%lx) value NOT mapped to a MC\n", 2288d27bf6faSDoug Thompson (unsigned long)SystemAddress); 2289d27bf6faSDoug Thompson edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); 2290d27bf6faSDoug Thompson return; 2291d27bf6faSDoug Thompson } 2292d27bf6faSDoug Thompson 2293d27bf6faSDoug Thompson log_mci = src_mci; 2294d27bf6faSDoug Thompson 2295d27bf6faSDoug Thompson csrow = sys_addr_to_csrow(log_mci, SystemAddress); 2296d27bf6faSDoug Thompson if (csrow < 0) { 2297d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_CRIT, 2298d27bf6faSDoug Thompson "ERROR_ADDRESS (0x%lx) value NOT mapped to 'csrow'\n", 2299d27bf6faSDoug Thompson (unsigned long)SystemAddress); 2300d27bf6faSDoug Thompson edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR); 2301d27bf6faSDoug Thompson } else { 2302d27bf6faSDoug Thompson error_address_to_page_and_offset(SystemAddress, &page, &offset); 2303d27bf6faSDoug Thompson edac_mc_handle_ue(log_mci, page, offset, csrow, EDAC_MOD_STR); 2304d27bf6faSDoug Thompson } 2305d27bf6faSDoug Thompson } 2306d27bf6faSDoug Thompson 2307d27bf6faSDoug Thompson static void amd64_decode_bus_error(struct mem_ctl_info *mci, 2308ef44cc4cSBorislav Petkov struct err_regs *info) 2309d27bf6faSDoug Thompson { 2310b70ef010SBorislav Petkov u32 ec = ERROR_CODE(info->nbsl); 2311b70ef010SBorislav Petkov u32 xec = EXT_ERROR_CODE(info->nbsl); 2312d27bf6faSDoug Thompson 2313d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_ERR, 2314d27bf6faSDoug Thompson "BUS ERROR:\n" 2315d27bf6faSDoug Thompson " time-out(%s) mem or i/o(%s)\n" 2316d27bf6faSDoug Thompson " participating processor(%s)\n" 2317d27bf6faSDoug Thompson " memory transaction type(%s)\n" 2318d27bf6faSDoug Thompson " cache level(%s) Error Found by: %s\n", 2319b70ef010SBorislav Petkov TO_MSG(ec), II_MSG(ec), PP_MSG(ec), RRRR_MSG(ec), LL_MSG(ec), 2320d27bf6faSDoug Thompson (info->nbsh & K8_NBSH_ERR_SCRUBER) ? 2321d27bf6faSDoug Thompson "Scrubber" : "Normal Operation"); 2322d27bf6faSDoug Thompson 2323b70ef010SBorislav Petkov 2324b70ef010SBorislav Petkov /* Bail early out if this was an 'observed' error */ 2325b70ef010SBorislav Petkov if (PP(ec) == K8_NBSL_PP_OBS) 2326b70ef010SBorislav Petkov return; 2327d27bf6faSDoug Thompson 2328d27bf6faSDoug Thompson /* Parse out the extended error code for ECC events */ 2329b70ef010SBorislav Petkov switch (xec) { 2330d27bf6faSDoug Thompson /* F10 changed to one Extended ECC error code */ 2331d27bf6faSDoug Thompson case F10_NBSL_EXT_ERR_RES: /* Reserved field */ 2332d27bf6faSDoug Thompson case F10_NBSL_EXT_ERR_ECC: /* F10 ECC ext err code */ 2333d27bf6faSDoug Thompson break; 2334d27bf6faSDoug Thompson 2335d27bf6faSDoug Thompson default: 2336d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_ERR, "NOT ECC: no special error " 2337d27bf6faSDoug Thompson "handling for this error\n"); 2338d27bf6faSDoug Thompson return; 2339d27bf6faSDoug Thompson } 2340d27bf6faSDoug Thompson 2341d27bf6faSDoug Thompson if (info->nbsh & K8_NBSH_CECC) 2342d27bf6faSDoug Thompson amd64_handle_ce(mci, info); 2343d27bf6faSDoug Thompson else if (info->nbsh & K8_NBSH_UECC) 2344d27bf6faSDoug Thompson amd64_handle_ue(mci, info); 2345d27bf6faSDoug Thompson 2346d27bf6faSDoug Thompson /* 2347d27bf6faSDoug Thompson * If main error is CE then overflow must be CE. If main error is UE 2348d27bf6faSDoug Thompson * then overflow is unknown. We'll call the overflow a CE - if 2349d27bf6faSDoug Thompson * panic_on_ue is set then we're already panic'ed and won't arrive 2350d27bf6faSDoug Thompson * here. Else, then apparently someone doesn't think that UE's are 2351d27bf6faSDoug Thompson * catastrophic. 2352d27bf6faSDoug Thompson */ 2353d27bf6faSDoug Thompson if (info->nbsh & K8_NBSH_OVERFLOW) 2354d27bf6faSDoug Thompson edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR 2355d27bf6faSDoug Thompson "Error Overflow set"); 2356d27bf6faSDoug Thompson } 2357d27bf6faSDoug Thompson 23585110dbdeSBorislav Petkov void amd64_decode_nb_mce(struct mem_ctl_info *mci, struct err_regs *regs, 2359d27bf6faSDoug Thompson int handle_errors) 2360d27bf6faSDoug Thompson { 23615110dbdeSBorislav Petkov struct amd64_pvt *pvt = mci->pvt_info; 23625110dbdeSBorislav Petkov int ecc; 23635110dbdeSBorislav Petkov u32 ec = ERROR_CODE(regs->nbsl); 23645110dbdeSBorislav Petkov u32 xec = EXT_ERROR_CODE(regs->nbsl); 2365d27bf6faSDoug Thompson 2366d27bf6faSDoug Thompson if (!handle_errors) 23675110dbdeSBorislav Petkov return; 2368d27bf6faSDoug Thompson 23695110dbdeSBorislav Petkov pr_emerg(" Northbridge ERROR, mc node %d", pvt->mc_node_id); 2370d27bf6faSDoug Thompson 23715110dbdeSBorislav Petkov /* 23725110dbdeSBorislav Petkov * F10h, revD can disable ErrCpu[3:0] so check that first and also the 23735110dbdeSBorislav Petkov * value encoding has changed so interpret those differently 2374d27bf6faSDoug Thompson */ 23755110dbdeSBorislav Petkov if ((boot_cpu_data.x86 == 0x10) && 23765110dbdeSBorislav Petkov (boot_cpu_data.x86_model > 8)) { 23775110dbdeSBorislav Petkov if (regs->nbsh & K8_NBSH_ERR_CPU_VAL) 23785110dbdeSBorislav Petkov pr_cont(", core: %u\n", (u8)(regs->nbsh & 0xf)); 23795110dbdeSBorislav Petkov } else { 23805110dbdeSBorislav Petkov pr_cont(", core: %d\n", ilog2((regs->nbsh & 0xf))); 23815110dbdeSBorislav Petkov } 23825110dbdeSBorislav Petkov 23835110dbdeSBorislav Petkov pr_emerg(" Error: %sorrected", 23845110dbdeSBorislav Petkov ((regs->nbsh & K8_NBSH_UC_ERR) ? "Unc" : "C")); 23855110dbdeSBorislav Petkov pr_cont(", Report Error: %s", 23865110dbdeSBorislav Petkov ((regs->nbsh & K8_NBSH_ERR_EN) ? "yes" : "no")); 23875110dbdeSBorislav Petkov pr_cont(", MiscV: %svalid, CPU context corrupt: %s", 23885110dbdeSBorislav Petkov ((regs->nbsh & K8_NBSH_MISCV) ? "" : "In"), 23895110dbdeSBorislav Petkov ((regs->nbsh & K8_NBSH_PCC) ? "yes" : "no")); 23905110dbdeSBorislav Petkov 23915110dbdeSBorislav Petkov /* do the two bits[14:13] together */ 23925110dbdeSBorislav Petkov ecc = regs->nbsh & (0x3 << 13); 23935110dbdeSBorislav Petkov if (ecc) 23945110dbdeSBorislav Petkov pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U")); 23955110dbdeSBorislav Petkov 23965110dbdeSBorislav Petkov pr_cont("\n"); 23975110dbdeSBorislav Petkov 23985110dbdeSBorislav Petkov if (TLB_ERROR(ec)) { 2399d27bf6faSDoug Thompson /* 2400d27bf6faSDoug Thompson * GART errors are intended to help graphics driver developers 2401d27bf6faSDoug Thompson * to detect bad GART PTEs. It is recommended by AMD to disable 2402d27bf6faSDoug Thompson * GART table walk error reporting by default[1] (currently 2403d27bf6faSDoug Thompson * being disabled in mce_cpu_quirks()) and according to the 2404d27bf6faSDoug Thompson * comment in mce_cpu_quirks(), such GART errors can be 2405d27bf6faSDoug Thompson * incorrectly triggered. We may see these errors anyway and 2406d27bf6faSDoug Thompson * unless requested by the user, they won't be reported. 2407d27bf6faSDoug Thompson * 2408d27bf6faSDoug Thompson * [1] section 13.10.1 on BIOS and Kernel Developers Guide for 2409d27bf6faSDoug Thompson * AMD NPT family 0Fh processors 2410d27bf6faSDoug Thompson */ 24115110dbdeSBorislav Petkov if (!report_gart_errors) 24125110dbdeSBorislav Petkov return; 2413d27bf6faSDoug Thompson 24145110dbdeSBorislav Petkov pr_emerg("GART TLB error\n"); 2415ef44cc4cSBorislav Petkov amd64_decode_gart_tlb_error(mci, regs); 24165110dbdeSBorislav Petkov } else if (MEM_ERROR(ec)) { 24175110dbdeSBorislav Petkov pr_emerg("Memory/Cache error\n"); 2418ef44cc4cSBorislav Petkov amd64_decode_mem_cache_error(mci, regs); 24195110dbdeSBorislav Petkov } else if (BUS_ERROR(ec)) { 24205110dbdeSBorislav Petkov pr_emerg("Bus (Link/DRAM) error\n"); 2421ef44cc4cSBorislav Petkov amd64_decode_bus_error(mci, regs); 2422d27bf6faSDoug Thompson } else { 2423d27bf6faSDoug Thompson /* shouldn't reach here! */ 2424d27bf6faSDoug Thompson amd64_mc_printk(mci, KERN_WARNING, 2425d27bf6faSDoug Thompson "%s(): unknown MCE error 0x%x\n", __func__, 24265110dbdeSBorislav Petkov ec); 2427d27bf6faSDoug Thompson } 2428d27bf6faSDoug Thompson 24295110dbdeSBorislav Petkov pr_emerg("%s.\n", EXT_ERR_MSG(xec)); 2430d27bf6faSDoug Thompson 2431d27bf6faSDoug Thompson /* 2432d27bf6faSDoug Thompson * Check the UE bit of the NB status high register, if set generate some 2433d27bf6faSDoug Thompson * logs. If NOT a GART error, then process the event as a NO-INFO event. 2434d27bf6faSDoug Thompson * If it was a GART error, skip that process. 2435d27bf6faSDoug Thompson */ 24365110dbdeSBorislav Petkov if (regs->nbsh & K8_NBSH_UC_ERR && !report_gart_errors) 24375110dbdeSBorislav Petkov edac_mc_handle_ue_no_info(mci, "UE bit is set"); 2438d27bf6faSDoug Thompson } 2439d27bf6faSDoug Thompson 24400ec449eeSDoug Thompson /* 24410ec449eeSDoug Thompson * The main polling 'check' function, called FROM the edac core to perform the 24420ec449eeSDoug Thompson * error checking and if an error is encountered, error processing. 24430ec449eeSDoug Thompson */ 24440ec449eeSDoug Thompson static void amd64_check(struct mem_ctl_info *mci) 24450ec449eeSDoug Thompson { 2446ef44cc4cSBorislav Petkov struct err_regs regs; 24470ec449eeSDoug Thompson 2448ef44cc4cSBorislav Petkov if (amd64_get_error_info(mci, ®s)) 24495110dbdeSBorislav Petkov amd64_decode_nb_mce(mci, ®s, 1); 24500ec449eeSDoug Thompson } 24510ec449eeSDoug Thompson 24520ec449eeSDoug Thompson /* 24530ec449eeSDoug Thompson * Input: 24540ec449eeSDoug Thompson * 1) struct amd64_pvt which contains pvt->dram_f2_ctl pointer 24550ec449eeSDoug Thompson * 2) AMD Family index value 24560ec449eeSDoug Thompson * 24570ec449eeSDoug Thompson * Ouput: 24580ec449eeSDoug Thompson * Upon return of 0, the following filled in: 24590ec449eeSDoug Thompson * 24600ec449eeSDoug Thompson * struct pvt->addr_f1_ctl 24610ec449eeSDoug Thompson * struct pvt->misc_f3_ctl 24620ec449eeSDoug Thompson * 24630ec449eeSDoug Thompson * Filled in with related device funcitions of 'dram_f2_ctl' 24640ec449eeSDoug Thompson * These devices are "reserved" via the pci_get_device() 24650ec449eeSDoug Thompson * 24660ec449eeSDoug Thompson * Upon return of 1 (error status): 24670ec449eeSDoug Thompson * 24680ec449eeSDoug Thompson * Nothing reserved 24690ec449eeSDoug Thompson */ 24700ec449eeSDoug Thompson static int amd64_reserve_mc_sibling_devices(struct amd64_pvt *pvt, int mc_idx) 24710ec449eeSDoug Thompson { 24720ec449eeSDoug Thompson const struct amd64_family_type *amd64_dev = &amd64_family_types[mc_idx]; 24730ec449eeSDoug Thompson 24740ec449eeSDoug Thompson /* Reserve the ADDRESS MAP Device */ 24750ec449eeSDoug Thompson pvt->addr_f1_ctl = pci_get_related_function(pvt->dram_f2_ctl->vendor, 24760ec449eeSDoug Thompson amd64_dev->addr_f1_ctl, 24770ec449eeSDoug Thompson pvt->dram_f2_ctl); 24780ec449eeSDoug Thompson 24790ec449eeSDoug Thompson if (!pvt->addr_f1_ctl) { 24800ec449eeSDoug Thompson amd64_printk(KERN_ERR, "error address map device not found: " 24810ec449eeSDoug Thompson "vendor %x device 0x%x (broken BIOS?)\n", 24820ec449eeSDoug Thompson PCI_VENDOR_ID_AMD, amd64_dev->addr_f1_ctl); 24830ec449eeSDoug Thompson return 1; 24840ec449eeSDoug Thompson } 24850ec449eeSDoug Thompson 24860ec449eeSDoug Thompson /* Reserve the MISC Device */ 24870ec449eeSDoug Thompson pvt->misc_f3_ctl = pci_get_related_function(pvt->dram_f2_ctl->vendor, 24880ec449eeSDoug Thompson amd64_dev->misc_f3_ctl, 24890ec449eeSDoug Thompson pvt->dram_f2_ctl); 24900ec449eeSDoug Thompson 24910ec449eeSDoug Thompson if (!pvt->misc_f3_ctl) { 24920ec449eeSDoug Thompson pci_dev_put(pvt->addr_f1_ctl); 24930ec449eeSDoug Thompson pvt->addr_f1_ctl = NULL; 24940ec449eeSDoug Thompson 24950ec449eeSDoug Thompson amd64_printk(KERN_ERR, "error miscellaneous device not found: " 24960ec449eeSDoug Thompson "vendor %x device 0x%x (broken BIOS?)\n", 24970ec449eeSDoug Thompson PCI_VENDOR_ID_AMD, amd64_dev->misc_f3_ctl); 24980ec449eeSDoug Thompson return 1; 24990ec449eeSDoug Thompson } 25000ec449eeSDoug Thompson 25010ec449eeSDoug Thompson debugf1(" Addr Map device PCI Bus ID:\t%s\n", 25020ec449eeSDoug Thompson pci_name(pvt->addr_f1_ctl)); 25030ec449eeSDoug Thompson debugf1(" DRAM MEM-CTL PCI Bus ID:\t%s\n", 25040ec449eeSDoug Thompson pci_name(pvt->dram_f2_ctl)); 25050ec449eeSDoug Thompson debugf1(" Misc device PCI Bus ID:\t%s\n", 25060ec449eeSDoug Thompson pci_name(pvt->misc_f3_ctl)); 25070ec449eeSDoug Thompson 25080ec449eeSDoug Thompson return 0; 25090ec449eeSDoug Thompson } 25100ec449eeSDoug Thompson 25110ec449eeSDoug Thompson static void amd64_free_mc_sibling_devices(struct amd64_pvt *pvt) 25120ec449eeSDoug Thompson { 25130ec449eeSDoug Thompson pci_dev_put(pvt->addr_f1_ctl); 25140ec449eeSDoug Thompson pci_dev_put(pvt->misc_f3_ctl); 25150ec449eeSDoug Thompson } 25160ec449eeSDoug Thompson 25170ec449eeSDoug Thompson /* 25180ec449eeSDoug Thompson * Retrieve the hardware registers of the memory controller (this includes the 25190ec449eeSDoug Thompson * 'Address Map' and 'Misc' device regs) 25200ec449eeSDoug Thompson */ 25210ec449eeSDoug Thompson static void amd64_read_mc_registers(struct amd64_pvt *pvt) 25220ec449eeSDoug Thompson { 25230ec449eeSDoug Thompson u64 msr_val; 25240ec449eeSDoug Thompson int dram, err = 0; 25250ec449eeSDoug Thompson 25260ec449eeSDoug Thompson /* 25270ec449eeSDoug Thompson * Retrieve TOP_MEM and TOP_MEM2; no masking off of reserved bits since 25280ec449eeSDoug Thompson * those are Read-As-Zero 25290ec449eeSDoug Thompson */ 25300ec449eeSDoug Thompson rdmsrl(MSR_K8_TOP_MEM1, msr_val); 25310ec449eeSDoug Thompson pvt->top_mem = msr_val >> 23; 25320ec449eeSDoug Thompson debugf0(" TOP_MEM=0x%08llx\n", pvt->top_mem); 25330ec449eeSDoug Thompson 25340ec449eeSDoug Thompson /* check first whether TOP_MEM2 is enabled */ 25350ec449eeSDoug Thompson rdmsrl(MSR_K8_SYSCFG, msr_val); 25360ec449eeSDoug Thompson if (msr_val & (1U << 21)) { 25370ec449eeSDoug Thompson rdmsrl(MSR_K8_TOP_MEM2, msr_val); 25380ec449eeSDoug Thompson pvt->top_mem2 = msr_val >> 23; 25390ec449eeSDoug Thompson debugf0(" TOP_MEM2=0x%08llx\n", pvt->top_mem2); 25400ec449eeSDoug Thompson } else 25410ec449eeSDoug Thompson debugf0(" TOP_MEM2 disabled.\n"); 25420ec449eeSDoug Thompson 25430ec449eeSDoug Thompson amd64_cpu_display_info(pvt); 25440ec449eeSDoug Thompson 25450ec449eeSDoug Thompson err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCAP, &pvt->nbcap); 25460ec449eeSDoug Thompson if (err) 25470ec449eeSDoug Thompson goto err_reg; 25480ec449eeSDoug Thompson 25490ec449eeSDoug Thompson if (pvt->ops->read_dram_ctl_register) 25500ec449eeSDoug Thompson pvt->ops->read_dram_ctl_register(pvt); 25510ec449eeSDoug Thompson 25520ec449eeSDoug Thompson for (dram = 0; dram < DRAM_REG_COUNT; dram++) { 25530ec449eeSDoug Thompson /* 25540ec449eeSDoug Thompson * Call CPU specific READ function to get the DRAM Base and 25550ec449eeSDoug Thompson * Limit values from the DCT. 25560ec449eeSDoug Thompson */ 25570ec449eeSDoug Thompson pvt->ops->read_dram_base_limit(pvt, dram); 25580ec449eeSDoug Thompson 25590ec449eeSDoug Thompson /* 25600ec449eeSDoug Thompson * Only print out debug info on rows with both R and W Enabled. 25610ec449eeSDoug Thompson * Normal processing, compiler should optimize this whole 'if' 25620ec449eeSDoug Thompson * debug output block away. 25630ec449eeSDoug Thompson */ 25640ec449eeSDoug Thompson if (pvt->dram_rw_en[dram] != 0) { 25650ec449eeSDoug Thompson debugf1(" DRAM_BASE[%d]: 0x%8.08x-%8.08x " 25660ec449eeSDoug Thompson "DRAM_LIMIT: 0x%8.08x-%8.08x\n", 25670ec449eeSDoug Thompson dram, 25680ec449eeSDoug Thompson (u32)(pvt->dram_base[dram] >> 32), 25690ec449eeSDoug Thompson (u32)(pvt->dram_base[dram] & 0xFFFFFFFF), 25700ec449eeSDoug Thompson (u32)(pvt->dram_limit[dram] >> 32), 25710ec449eeSDoug Thompson (u32)(pvt->dram_limit[dram] & 0xFFFFFFFF)); 25720ec449eeSDoug Thompson debugf1(" IntlvEn=%s %s %s " 25730ec449eeSDoug Thompson "IntlvSel=%d DstNode=%d\n", 25740ec449eeSDoug Thompson pvt->dram_IntlvEn[dram] ? 25750ec449eeSDoug Thompson "Enabled" : "Disabled", 25760ec449eeSDoug Thompson (pvt->dram_rw_en[dram] & 0x2) ? "W" : "!W", 25770ec449eeSDoug Thompson (pvt->dram_rw_en[dram] & 0x1) ? "R" : "!R", 25780ec449eeSDoug Thompson pvt->dram_IntlvSel[dram], 25790ec449eeSDoug Thompson pvt->dram_DstNode[dram]); 25800ec449eeSDoug Thompson } 25810ec449eeSDoug Thompson } 25820ec449eeSDoug Thompson 25830ec449eeSDoug Thompson amd64_read_dct_base_mask(pvt); 25840ec449eeSDoug Thompson 25850ec449eeSDoug Thompson err = pci_read_config_dword(pvt->addr_f1_ctl, K8_DHAR, &pvt->dhar); 25860ec449eeSDoug Thompson if (err) 25870ec449eeSDoug Thompson goto err_reg; 25880ec449eeSDoug Thompson 25890ec449eeSDoug Thompson amd64_read_dbam_reg(pvt); 25900ec449eeSDoug Thompson 25910ec449eeSDoug Thompson err = pci_read_config_dword(pvt->misc_f3_ctl, 25920ec449eeSDoug Thompson F10_ONLINE_SPARE, &pvt->online_spare); 25930ec449eeSDoug Thompson if (err) 25940ec449eeSDoug Thompson goto err_reg; 25950ec449eeSDoug Thompson 25960ec449eeSDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_0, &pvt->dclr0); 25970ec449eeSDoug Thompson if (err) 25980ec449eeSDoug Thompson goto err_reg; 25990ec449eeSDoug Thompson 26000ec449eeSDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCHR_0, &pvt->dchr0); 26010ec449eeSDoug Thompson if (err) 26020ec449eeSDoug Thompson goto err_reg; 26030ec449eeSDoug Thompson 26040ec449eeSDoug Thompson if (!dct_ganging_enabled(pvt)) { 26050ec449eeSDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCLR_1, 26060ec449eeSDoug Thompson &pvt->dclr1); 26070ec449eeSDoug Thompson if (err) 26080ec449eeSDoug Thompson goto err_reg; 26090ec449eeSDoug Thompson 26100ec449eeSDoug Thompson err = pci_read_config_dword(pvt->dram_f2_ctl, F10_DCHR_1, 26110ec449eeSDoug Thompson &pvt->dchr1); 26120ec449eeSDoug Thompson if (err) 26130ec449eeSDoug Thompson goto err_reg; 26140ec449eeSDoug Thompson } 26150ec449eeSDoug Thompson 26160ec449eeSDoug Thompson amd64_dump_misc_regs(pvt); 26170ec449eeSDoug Thompson 2618c2718348SDoug Thompson return; 2619c2718348SDoug Thompson 26200ec449eeSDoug Thompson err_reg: 26210ec449eeSDoug Thompson debugf0("Reading an MC register failed\n"); 26220ec449eeSDoug Thompson 26230ec449eeSDoug Thompson } 26240ec449eeSDoug Thompson 26250ec449eeSDoug Thompson /* 26260ec449eeSDoug Thompson * NOTE: CPU Revision Dependent code 26270ec449eeSDoug Thompson * 26280ec449eeSDoug Thompson * Input: 26290ec449eeSDoug Thompson * @csrow_nr ChipSelect Row Number (0..CHIPSELECT_COUNT-1) 26300ec449eeSDoug Thompson * k8 private pointer to --> 26310ec449eeSDoug Thompson * DRAM Bank Address mapping register 26320ec449eeSDoug Thompson * node_id 26330ec449eeSDoug Thompson * DCL register where dual_channel_active is 26340ec449eeSDoug Thompson * 26350ec449eeSDoug Thompson * The DBAM register consists of 4 sets of 4 bits each definitions: 26360ec449eeSDoug Thompson * 26370ec449eeSDoug Thompson * Bits: CSROWs 26380ec449eeSDoug Thompson * 0-3 CSROWs 0 and 1 26390ec449eeSDoug Thompson * 4-7 CSROWs 2 and 3 26400ec449eeSDoug Thompson * 8-11 CSROWs 4 and 5 26410ec449eeSDoug Thompson * 12-15 CSROWs 6 and 7 26420ec449eeSDoug Thompson * 26430ec449eeSDoug Thompson * Values range from: 0 to 15 26440ec449eeSDoug Thompson * The meaning of the values depends on CPU revision and dual-channel state, 26450ec449eeSDoug Thompson * see relevant BKDG more info. 26460ec449eeSDoug Thompson * 26470ec449eeSDoug Thompson * The memory controller provides for total of only 8 CSROWs in its current 26480ec449eeSDoug Thompson * architecture. Each "pair" of CSROWs normally represents just one DIMM in 26490ec449eeSDoug Thompson * single channel or two (2) DIMMs in dual channel mode. 26500ec449eeSDoug Thompson * 26510ec449eeSDoug Thompson * The following code logic collapses the various tables for CSROW based on CPU 26520ec449eeSDoug Thompson * revision. 26530ec449eeSDoug Thompson * 26540ec449eeSDoug Thompson * Returns: 26550ec449eeSDoug Thompson * The number of PAGE_SIZE pages on the specified CSROW number it 26560ec449eeSDoug Thompson * encompasses 26570ec449eeSDoug Thompson * 26580ec449eeSDoug Thompson */ 26590ec449eeSDoug Thompson static u32 amd64_csrow_nr_pages(int csrow_nr, struct amd64_pvt *pvt) 26600ec449eeSDoug Thompson { 26610ec449eeSDoug Thompson u32 dram_map, nr_pages; 26620ec449eeSDoug Thompson 26630ec449eeSDoug Thompson /* 26640ec449eeSDoug Thompson * The math on this doesn't look right on the surface because x/2*4 can 26650ec449eeSDoug Thompson * be simplified to x*2 but this expression makes use of the fact that 26660ec449eeSDoug Thompson * it is integral math where 1/2=0. This intermediate value becomes the 26670ec449eeSDoug Thompson * number of bits to shift the DBAM register to extract the proper CSROW 26680ec449eeSDoug Thompson * field. 26690ec449eeSDoug Thompson */ 26700ec449eeSDoug Thompson dram_map = (pvt->dbam0 >> ((csrow_nr / 2) * 4)) & 0xF; 26710ec449eeSDoug Thompson 26720ec449eeSDoug Thompson nr_pages = pvt->ops->dbam_map_to_pages(pvt, dram_map); 26730ec449eeSDoug Thompson 26740ec449eeSDoug Thompson /* 26750ec449eeSDoug Thompson * If dual channel then double the memory size of single channel. 26760ec449eeSDoug Thompson * Channel count is 1 or 2 26770ec449eeSDoug Thompson */ 26780ec449eeSDoug Thompson nr_pages <<= (pvt->channel_count - 1); 26790ec449eeSDoug Thompson 26800ec449eeSDoug Thompson debugf0(" (csrow=%d) DBAM map index= %d\n", csrow_nr, dram_map); 26810ec449eeSDoug Thompson debugf0(" nr_pages= %u channel-count = %d\n", 26820ec449eeSDoug Thompson nr_pages, pvt->channel_count); 26830ec449eeSDoug Thompson 26840ec449eeSDoug Thompson return nr_pages; 26850ec449eeSDoug Thompson } 26860ec449eeSDoug Thompson 26870ec449eeSDoug Thompson /* 26880ec449eeSDoug Thompson * Initialize the array of csrow attribute instances, based on the values 26890ec449eeSDoug Thompson * from pci config hardware registers. 26900ec449eeSDoug Thompson */ 26910ec449eeSDoug Thompson static int amd64_init_csrows(struct mem_ctl_info *mci) 26920ec449eeSDoug Thompson { 26930ec449eeSDoug Thompson struct csrow_info *csrow; 26940ec449eeSDoug Thompson struct amd64_pvt *pvt; 26950ec449eeSDoug Thompson u64 input_addr_min, input_addr_max, sys_addr; 26960ec449eeSDoug Thompson int i, err = 0, empty = 1; 26970ec449eeSDoug Thompson 26980ec449eeSDoug Thompson pvt = mci->pvt_info; 26990ec449eeSDoug Thompson 27000ec449eeSDoug Thompson err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &pvt->nbcfg); 27010ec449eeSDoug Thompson if (err) 27020ec449eeSDoug Thompson debugf0("Reading K8_NBCFG failed\n"); 27030ec449eeSDoug Thompson 27040ec449eeSDoug Thompson debugf0("NBCFG= 0x%x CHIPKILL= %s DRAM ECC= %s\n", pvt->nbcfg, 27050ec449eeSDoug Thompson (pvt->nbcfg & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled", 27060ec449eeSDoug Thompson (pvt->nbcfg & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled" 27070ec449eeSDoug Thompson ); 27080ec449eeSDoug Thompson 27090ec449eeSDoug Thompson for (i = 0; i < CHIPSELECT_COUNT; i++) { 27100ec449eeSDoug Thompson csrow = &mci->csrows[i]; 27110ec449eeSDoug Thompson 27120ec449eeSDoug Thompson if ((pvt->dcsb0[i] & K8_DCSB_CS_ENABLE) == 0) { 27130ec449eeSDoug Thompson debugf1("----CSROW %d EMPTY for node %d\n", i, 27140ec449eeSDoug Thompson pvt->mc_node_id); 27150ec449eeSDoug Thompson continue; 27160ec449eeSDoug Thompson } 27170ec449eeSDoug Thompson 27180ec449eeSDoug Thompson debugf1("----CSROW %d VALID for MC node %d\n", 27190ec449eeSDoug Thompson i, pvt->mc_node_id); 27200ec449eeSDoug Thompson 27210ec449eeSDoug Thompson empty = 0; 27220ec449eeSDoug Thompson csrow->nr_pages = amd64_csrow_nr_pages(i, pvt); 27230ec449eeSDoug Thompson find_csrow_limits(mci, i, &input_addr_min, &input_addr_max); 27240ec449eeSDoug Thompson sys_addr = input_addr_to_sys_addr(mci, input_addr_min); 27250ec449eeSDoug Thompson csrow->first_page = (u32) (sys_addr >> PAGE_SHIFT); 27260ec449eeSDoug Thompson sys_addr = input_addr_to_sys_addr(mci, input_addr_max); 27270ec449eeSDoug Thompson csrow->last_page = (u32) (sys_addr >> PAGE_SHIFT); 27280ec449eeSDoug Thompson csrow->page_mask = ~mask_from_dct_mask(pvt, i); 27290ec449eeSDoug Thompson /* 8 bytes of resolution */ 27300ec449eeSDoug Thompson 27310ec449eeSDoug Thompson csrow->mtype = amd64_determine_memory_type(pvt); 27320ec449eeSDoug Thompson 27330ec449eeSDoug Thompson debugf1(" for MC node %d csrow %d:\n", pvt->mc_node_id, i); 27340ec449eeSDoug Thompson debugf1(" input_addr_min: 0x%lx input_addr_max: 0x%lx\n", 27350ec449eeSDoug Thompson (unsigned long)input_addr_min, 27360ec449eeSDoug Thompson (unsigned long)input_addr_max); 27370ec449eeSDoug Thompson debugf1(" sys_addr: 0x%lx page_mask: 0x%lx\n", 27380ec449eeSDoug Thompson (unsigned long)sys_addr, csrow->page_mask); 27390ec449eeSDoug Thompson debugf1(" nr_pages: %u first_page: 0x%lx " 27400ec449eeSDoug Thompson "last_page: 0x%lx\n", 27410ec449eeSDoug Thompson (unsigned)csrow->nr_pages, 27420ec449eeSDoug Thompson csrow->first_page, csrow->last_page); 27430ec449eeSDoug Thompson 27440ec449eeSDoug Thompson /* 27450ec449eeSDoug Thompson * determine whether CHIPKILL or JUST ECC or NO ECC is operating 27460ec449eeSDoug Thompson */ 27470ec449eeSDoug Thompson if (pvt->nbcfg & K8_NBCFG_ECC_ENABLE) 27480ec449eeSDoug Thompson csrow->edac_mode = 27490ec449eeSDoug Thompson (pvt->nbcfg & K8_NBCFG_CHIPKILL) ? 27500ec449eeSDoug Thompson EDAC_S4ECD4ED : EDAC_SECDED; 27510ec449eeSDoug Thompson else 27520ec449eeSDoug Thompson csrow->edac_mode = EDAC_NONE; 27530ec449eeSDoug Thompson } 27540ec449eeSDoug Thompson 27550ec449eeSDoug Thompson return empty; 27560ec449eeSDoug Thompson } 2757d27bf6faSDoug Thompson 2758f9431992SDoug Thompson /* 2759f9431992SDoug Thompson * Only if 'ecc_enable_override' is set AND BIOS had ECC disabled, do "we" 2760f9431992SDoug Thompson * enable it. 2761f9431992SDoug Thompson */ 2762f9431992SDoug Thompson static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci) 2763f9431992SDoug Thompson { 2764f9431992SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 2765f9431992SDoug Thompson const cpumask_t *cpumask = cpumask_of_node(pvt->mc_node_id); 2766f9431992SDoug Thompson int cpu, idx = 0, err = 0; 2767f9431992SDoug Thompson struct msr msrs[cpumask_weight(cpumask)]; 2768f9431992SDoug Thompson u32 value; 2769f9431992SDoug Thompson u32 mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn; 2770f9431992SDoug Thompson 2771f9431992SDoug Thompson if (!ecc_enable_override) 2772f9431992SDoug Thompson return; 2773f9431992SDoug Thompson 2774f9431992SDoug Thompson memset(msrs, 0, sizeof(msrs)); 2775f9431992SDoug Thompson 2776f9431992SDoug Thompson amd64_printk(KERN_WARNING, 2777f9431992SDoug Thompson "'ecc_enable_override' parameter is active, " 2778f9431992SDoug Thompson "Enabling AMD ECC hardware now: CAUTION\n"); 2779f9431992SDoug Thompson 2780f9431992SDoug Thompson err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCTL, &value); 2781f9431992SDoug Thompson if (err) 2782f9431992SDoug Thompson debugf0("Reading K8_NBCTL failed\n"); 2783f9431992SDoug Thompson 2784f9431992SDoug Thompson /* turn on UECCn and CECCEn bits */ 2785f9431992SDoug Thompson pvt->old_nbctl = value & mask; 2786f9431992SDoug Thompson pvt->nbctl_mcgctl_saved = 1; 2787f9431992SDoug Thompson 2788f9431992SDoug Thompson value |= mask; 2789f9431992SDoug Thompson pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value); 2790f9431992SDoug Thompson 2791f9431992SDoug Thompson rdmsr_on_cpus(cpumask, K8_MSR_MCGCTL, msrs); 2792f9431992SDoug Thompson 2793f9431992SDoug Thompson for_each_cpu(cpu, cpumask) { 2794f9431992SDoug Thompson if (msrs[idx].l & K8_MSR_MCGCTL_NBE) 2795f9431992SDoug Thompson set_bit(idx, &pvt->old_mcgctl); 2796f9431992SDoug Thompson 2797f9431992SDoug Thompson msrs[idx].l |= K8_MSR_MCGCTL_NBE; 2798f9431992SDoug Thompson idx++; 2799f9431992SDoug Thompson } 2800f9431992SDoug Thompson wrmsr_on_cpus(cpumask, K8_MSR_MCGCTL, msrs); 2801f9431992SDoug Thompson 2802f9431992SDoug Thompson err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &value); 2803f9431992SDoug Thompson if (err) 2804f9431992SDoug Thompson debugf0("Reading K8_NBCFG failed\n"); 2805f9431992SDoug Thompson 2806f9431992SDoug Thompson debugf0("NBCFG(1)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value, 2807f9431992SDoug Thompson (value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled", 2808f9431992SDoug Thompson (value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled"); 2809f9431992SDoug Thompson 2810f9431992SDoug Thompson if (!(value & K8_NBCFG_ECC_ENABLE)) { 2811f9431992SDoug Thompson amd64_printk(KERN_WARNING, 2812f9431992SDoug Thompson "This node reports that DRAM ECC is " 2813f9431992SDoug Thompson "currently Disabled; ENABLING now\n"); 2814f9431992SDoug Thompson 2815f9431992SDoug Thompson /* Attempt to turn on DRAM ECC Enable */ 2816f9431992SDoug Thompson value |= K8_NBCFG_ECC_ENABLE; 2817f9431992SDoug Thompson pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCFG, value); 2818f9431992SDoug Thompson 2819f9431992SDoug Thompson err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &value); 2820f9431992SDoug Thompson if (err) 2821f9431992SDoug Thompson debugf0("Reading K8_NBCFG failed\n"); 2822f9431992SDoug Thompson 2823f9431992SDoug Thompson if (!(value & K8_NBCFG_ECC_ENABLE)) { 2824f9431992SDoug Thompson amd64_printk(KERN_WARNING, 2825f9431992SDoug Thompson "Hardware rejects Enabling DRAM ECC checking\n" 2826f9431992SDoug Thompson "Check memory DIMM configuration\n"); 2827f9431992SDoug Thompson } else { 2828f9431992SDoug Thompson amd64_printk(KERN_DEBUG, 2829f9431992SDoug Thompson "Hardware accepted DRAM ECC Enable\n"); 2830f9431992SDoug Thompson } 2831f9431992SDoug Thompson } 2832f9431992SDoug Thompson debugf0("NBCFG(2)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value, 2833f9431992SDoug Thompson (value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled", 2834f9431992SDoug Thompson (value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled"); 2835f9431992SDoug Thompson 2836f9431992SDoug Thompson pvt->ctl_error_info.nbcfg = value; 2837f9431992SDoug Thompson } 2838f9431992SDoug Thompson 2839f9431992SDoug Thompson static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt) 2840f9431992SDoug Thompson { 2841f9431992SDoug Thompson const cpumask_t *cpumask = cpumask_of_node(pvt->mc_node_id); 2842f9431992SDoug Thompson int cpu, idx = 0, err = 0; 2843f9431992SDoug Thompson struct msr msrs[cpumask_weight(cpumask)]; 2844f9431992SDoug Thompson u32 value; 2845f9431992SDoug Thompson u32 mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn; 2846f9431992SDoug Thompson 2847f9431992SDoug Thompson if (!pvt->nbctl_mcgctl_saved) 2848f9431992SDoug Thompson return; 2849f9431992SDoug Thompson 2850f9431992SDoug Thompson memset(msrs, 0, sizeof(msrs)); 2851f9431992SDoug Thompson 2852f9431992SDoug Thompson err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCTL, &value); 2853f9431992SDoug Thompson if (err) 2854f9431992SDoug Thompson debugf0("Reading K8_NBCTL failed\n"); 2855f9431992SDoug Thompson value &= ~mask; 2856f9431992SDoug Thompson value |= pvt->old_nbctl; 2857f9431992SDoug Thompson 2858f9431992SDoug Thompson /* restore the NB Enable MCGCTL bit */ 2859f9431992SDoug Thompson pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value); 2860f9431992SDoug Thompson 2861f9431992SDoug Thompson rdmsr_on_cpus(cpumask, K8_MSR_MCGCTL, msrs); 2862f9431992SDoug Thompson 2863f9431992SDoug Thompson for_each_cpu(cpu, cpumask) { 2864f9431992SDoug Thompson msrs[idx].l &= ~K8_MSR_MCGCTL_NBE; 2865f9431992SDoug Thompson msrs[idx].l |= 2866f9431992SDoug Thompson test_bit(idx, &pvt->old_mcgctl) << K8_MSR_MCGCTL_NBE; 2867f9431992SDoug Thompson idx++; 2868f9431992SDoug Thompson } 2869f9431992SDoug Thompson 2870f9431992SDoug Thompson wrmsr_on_cpus(cpumask, K8_MSR_MCGCTL, msrs); 2871f9431992SDoug Thompson } 2872f9431992SDoug Thompson 2873f9431992SDoug Thompson static void check_mcg_ctl(void *ret) 2874f9431992SDoug Thompson { 2875f9431992SDoug Thompson u64 msr_val = 0; 2876f9431992SDoug Thompson u8 nbe; 2877f9431992SDoug Thompson 2878f9431992SDoug Thompson rdmsrl(MSR_IA32_MCG_CTL, msr_val); 2879f9431992SDoug Thompson nbe = msr_val & K8_MSR_MCGCTL_NBE; 2880f9431992SDoug Thompson 2881f9431992SDoug Thompson debugf0("core: %u, MCG_CTL: 0x%llx, NB MSR is %s\n", 2882f9431992SDoug Thompson raw_smp_processor_id(), msr_val, 2883f9431992SDoug Thompson (nbe ? "enabled" : "disabled")); 2884f9431992SDoug Thompson 2885f9431992SDoug Thompson if (!nbe) 2886f9431992SDoug Thompson *(int *)ret = 0; 2887f9431992SDoug Thompson } 2888f9431992SDoug Thompson 2889f9431992SDoug Thompson /* check MCG_CTL on all the cpus on this node */ 2890f9431992SDoug Thompson static int amd64_mcg_ctl_enabled_on_cpus(const cpumask_t *mask) 2891f9431992SDoug Thompson { 2892f9431992SDoug Thompson int ret = 1; 2893f9431992SDoug Thompson preempt_disable(); 2894f9431992SDoug Thompson smp_call_function_many(mask, check_mcg_ctl, &ret, 1); 2895f9431992SDoug Thompson preempt_enable(); 2896f9431992SDoug Thompson 2897f9431992SDoug Thompson return ret; 2898f9431992SDoug Thompson } 2899f9431992SDoug Thompson 2900f9431992SDoug Thompson /* 2901f9431992SDoug Thompson * EDAC requires that the BIOS have ECC enabled before taking over the 2902f9431992SDoug Thompson * processing of ECC errors. This is because the BIOS can properly initialize 2903f9431992SDoug Thompson * the memory system completely. A command line option allows to force-enable 2904f9431992SDoug Thompson * hardware ECC later in amd64_enable_ecc_error_reporting(). 2905f9431992SDoug Thompson */ 2906f9431992SDoug Thompson static int amd64_check_ecc_enabled(struct amd64_pvt *pvt) 2907f9431992SDoug Thompson { 2908f9431992SDoug Thompson u32 value; 2909f9431992SDoug Thompson int err = 0, ret = 0; 2910f9431992SDoug Thompson u8 ecc_enabled = 0; 2911f9431992SDoug Thompson 2912f9431992SDoug Thompson err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &value); 2913f9431992SDoug Thompson if (err) 2914f9431992SDoug Thompson debugf0("Reading K8_NBCTL failed\n"); 2915f9431992SDoug Thompson 2916f9431992SDoug Thompson ecc_enabled = !!(value & K8_NBCFG_ECC_ENABLE); 2917f9431992SDoug Thompson 2918f9431992SDoug Thompson ret = amd64_mcg_ctl_enabled_on_cpus(cpumask_of_node(pvt->mc_node_id)); 2919f9431992SDoug Thompson 2920f9431992SDoug Thompson debugf0("K8_NBCFG=0x%x, DRAM ECC is %s\n", value, 2921f9431992SDoug Thompson (value & K8_NBCFG_ECC_ENABLE ? "enabled" : "disabled")); 2922f9431992SDoug Thompson 2923f9431992SDoug Thompson if (!ecc_enabled || !ret) { 2924f9431992SDoug Thompson if (!ecc_enabled) { 2925f9431992SDoug Thompson amd64_printk(KERN_WARNING, "This node reports that " 2926f9431992SDoug Thompson "Memory ECC is currently " 2927f9431992SDoug Thompson "disabled.\n"); 2928f9431992SDoug Thompson 2929f9431992SDoug Thompson amd64_printk(KERN_WARNING, "bit 0x%lx in register " 2930f9431992SDoug Thompson "F3x%x of the MISC_CONTROL device (%s) " 2931f9431992SDoug Thompson "should be enabled\n", K8_NBCFG_ECC_ENABLE, 2932f9431992SDoug Thompson K8_NBCFG, pci_name(pvt->misc_f3_ctl)); 2933f9431992SDoug Thompson } 2934f9431992SDoug Thompson if (!ret) { 2935f9431992SDoug Thompson amd64_printk(KERN_WARNING, "bit 0x%016lx in MSR 0x%08x " 2936f9431992SDoug Thompson "of node %d should be enabled\n", 2937f9431992SDoug Thompson K8_MSR_MCGCTL_NBE, MSR_IA32_MCG_CTL, 2938f9431992SDoug Thompson pvt->mc_node_id); 2939f9431992SDoug Thompson } 2940f9431992SDoug Thompson if (!ecc_enable_override) { 2941f9431992SDoug Thompson amd64_printk(KERN_WARNING, "WARNING: ECC is NOT " 2942f9431992SDoug Thompson "currently enabled by the BIOS. Module " 2943f9431992SDoug Thompson "will NOT be loaded.\n" 2944f9431992SDoug Thompson " Either Enable ECC in the BIOS, " 2945f9431992SDoug Thompson "or use the 'ecc_enable_override' " 2946f9431992SDoug Thompson "parameter.\n" 2947f9431992SDoug Thompson " Might be a BIOS bug, if BIOS says " 2948f9431992SDoug Thompson "ECC is enabled\n" 2949f9431992SDoug Thompson " Use of the override can cause " 2950f9431992SDoug Thompson "unknown side effects.\n"); 2951f9431992SDoug Thompson ret = -ENODEV; 295230c875cbSBorislav Petkov } else 295330c875cbSBorislav Petkov /* 295430c875cbSBorislav Petkov * enable further driver loading if ECC enable is 295530c875cbSBorislav Petkov * overridden. 295630c875cbSBorislav Petkov */ 295730c875cbSBorislav Petkov ret = 0; 2958f9431992SDoug Thompson } else { 2959f9431992SDoug Thompson amd64_printk(KERN_INFO, 2960f9431992SDoug Thompson "ECC is enabled by BIOS, Proceeding " 2961f9431992SDoug Thompson "with EDAC module initialization\n"); 2962f9431992SDoug Thompson 2963126b67b8SDoug Thompson /* Signal good ECC status */ 2964126b67b8SDoug Thompson ret = 0; 2965126b67b8SDoug Thompson 2966f9431992SDoug Thompson /* CLEAR the override, since BIOS controlled it */ 2967f9431992SDoug Thompson ecc_enable_override = 0; 2968f9431992SDoug Thompson } 2969f9431992SDoug Thompson 2970f9431992SDoug Thompson return ret; 2971f9431992SDoug Thompson } 2972f9431992SDoug Thompson 29737d6034d3SDoug Thompson struct mcidev_sysfs_attribute sysfs_attrs[ARRAY_SIZE(amd64_dbg_attrs) + 29747d6034d3SDoug Thompson ARRAY_SIZE(amd64_inj_attrs) + 29757d6034d3SDoug Thompson 1]; 29767d6034d3SDoug Thompson 29777d6034d3SDoug Thompson struct mcidev_sysfs_attribute terminator = { .attr = { .name = NULL } }; 29787d6034d3SDoug Thompson 29797d6034d3SDoug Thompson static void amd64_set_mc_sysfs_attributes(struct mem_ctl_info *mci) 29807d6034d3SDoug Thompson { 29817d6034d3SDoug Thompson unsigned int i = 0, j = 0; 29827d6034d3SDoug Thompson 29837d6034d3SDoug Thompson for (; i < ARRAY_SIZE(amd64_dbg_attrs); i++) 29847d6034d3SDoug Thompson sysfs_attrs[i] = amd64_dbg_attrs[i]; 29857d6034d3SDoug Thompson 29867d6034d3SDoug Thompson for (j = 0; j < ARRAY_SIZE(amd64_inj_attrs); j++, i++) 29877d6034d3SDoug Thompson sysfs_attrs[i] = amd64_inj_attrs[j]; 29887d6034d3SDoug Thompson 29897d6034d3SDoug Thompson sysfs_attrs[i] = terminator; 29907d6034d3SDoug Thompson 29917d6034d3SDoug Thompson mci->mc_driver_sysfs_attributes = sysfs_attrs; 29927d6034d3SDoug Thompson } 29937d6034d3SDoug Thompson 29947d6034d3SDoug Thompson static void amd64_setup_mci_misc_attributes(struct mem_ctl_info *mci) 29957d6034d3SDoug Thompson { 29967d6034d3SDoug Thompson struct amd64_pvt *pvt = mci->pvt_info; 29977d6034d3SDoug Thompson 29987d6034d3SDoug Thompson mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; 29997d6034d3SDoug Thompson mci->edac_ctl_cap = EDAC_FLAG_NONE; 30007d6034d3SDoug Thompson 30017d6034d3SDoug Thompson if (pvt->nbcap & K8_NBCAP_SECDED) 30027d6034d3SDoug Thompson mci->edac_ctl_cap |= EDAC_FLAG_SECDED; 30037d6034d3SDoug Thompson 30047d6034d3SDoug Thompson if (pvt->nbcap & K8_NBCAP_CHIPKILL) 30057d6034d3SDoug Thompson mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; 30067d6034d3SDoug Thompson 30077d6034d3SDoug Thompson mci->edac_cap = amd64_determine_edac_cap(pvt); 30087d6034d3SDoug Thompson mci->mod_name = EDAC_MOD_STR; 30097d6034d3SDoug Thompson mci->mod_ver = EDAC_AMD64_VERSION; 30107d6034d3SDoug Thompson mci->ctl_name = get_amd_family_name(pvt->mc_type_index); 30117d6034d3SDoug Thompson mci->dev_name = pci_name(pvt->dram_f2_ctl); 30127d6034d3SDoug Thompson mci->ctl_page_to_phys = NULL; 30137d6034d3SDoug Thompson 30147d6034d3SDoug Thompson /* IMPORTANT: Set the polling 'check' function in this module */ 30157d6034d3SDoug Thompson mci->edac_check = amd64_check; 30167d6034d3SDoug Thompson 30177d6034d3SDoug Thompson /* memory scrubber interface */ 30187d6034d3SDoug Thompson mci->set_sdram_scrub_rate = amd64_set_scrub_rate; 30197d6034d3SDoug Thompson mci->get_sdram_scrub_rate = amd64_get_scrub_rate; 30207d6034d3SDoug Thompson } 30217d6034d3SDoug Thompson 30227d6034d3SDoug Thompson /* 30237d6034d3SDoug Thompson * Init stuff for this DRAM Controller device. 30247d6034d3SDoug Thompson * 30257d6034d3SDoug Thompson * Due to a hardware feature on Fam10h CPUs, the Enable Extended Configuration 30267d6034d3SDoug Thompson * Space feature MUST be enabled on ALL Processors prior to actually reading 30277d6034d3SDoug Thompson * from the ECS registers. Since the loading of the module can occur on any 30287d6034d3SDoug Thompson * 'core', and cores don't 'see' all the other processors ECS data when the 30297d6034d3SDoug Thompson * others are NOT enabled. Our solution is to first enable ECS access in this 30307d6034d3SDoug Thompson * routine on all processors, gather some data in a amd64_pvt structure and 30317d6034d3SDoug Thompson * later come back in a finish-setup function to perform that final 30327d6034d3SDoug Thompson * initialization. See also amd64_init_2nd_stage() for that. 30337d6034d3SDoug Thompson */ 30347d6034d3SDoug Thompson static int amd64_probe_one_instance(struct pci_dev *dram_f2_ctl, 30357d6034d3SDoug Thompson int mc_type_index) 30367d6034d3SDoug Thompson { 30377d6034d3SDoug Thompson struct amd64_pvt *pvt = NULL; 30387d6034d3SDoug Thompson int err = 0, ret; 30397d6034d3SDoug Thompson 30407d6034d3SDoug Thompson ret = -ENOMEM; 30417d6034d3SDoug Thompson pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL); 30427d6034d3SDoug Thompson if (!pvt) 30437d6034d3SDoug Thompson goto err_exit; 30447d6034d3SDoug Thompson 304537da0450SBorislav Petkov pvt->mc_node_id = get_node_id(dram_f2_ctl); 30467d6034d3SDoug Thompson 30477d6034d3SDoug Thompson pvt->dram_f2_ctl = dram_f2_ctl; 30487d6034d3SDoug Thompson pvt->ext_model = boot_cpu_data.x86_model >> 4; 30497d6034d3SDoug Thompson pvt->mc_type_index = mc_type_index; 30507d6034d3SDoug Thompson pvt->ops = family_ops(mc_type_index); 30517d6034d3SDoug Thompson pvt->old_mcgctl = 0; 30527d6034d3SDoug Thompson 30537d6034d3SDoug Thompson /* 30547d6034d3SDoug Thompson * We have the dram_f2_ctl device as an argument, now go reserve its 30557d6034d3SDoug Thompson * sibling devices from the PCI system. 30567d6034d3SDoug Thompson */ 30577d6034d3SDoug Thompson ret = -ENODEV; 30587d6034d3SDoug Thompson err = amd64_reserve_mc_sibling_devices(pvt, mc_type_index); 30597d6034d3SDoug Thompson if (err) 30607d6034d3SDoug Thompson goto err_free; 30617d6034d3SDoug Thompson 30627d6034d3SDoug Thompson ret = -EINVAL; 30637d6034d3SDoug Thompson err = amd64_check_ecc_enabled(pvt); 30647d6034d3SDoug Thompson if (err) 30657d6034d3SDoug Thompson goto err_put; 30667d6034d3SDoug Thompson 30677d6034d3SDoug Thompson /* 30687d6034d3SDoug Thompson * Key operation here: setup of HW prior to performing ops on it. Some 30697d6034d3SDoug Thompson * setup is required to access ECS data. After this is performed, the 30707d6034d3SDoug Thompson * 'teardown' function must be called upon error and normal exit paths. 30717d6034d3SDoug Thompson */ 30727d6034d3SDoug Thompson if (boot_cpu_data.x86 >= 0x10) 30737d6034d3SDoug Thompson amd64_setup(pvt); 30747d6034d3SDoug Thompson 30757d6034d3SDoug Thompson /* 30767d6034d3SDoug Thompson * Save the pointer to the private data for use in 2nd initialization 30777d6034d3SDoug Thompson * stage 30787d6034d3SDoug Thompson */ 30797d6034d3SDoug Thompson pvt_lookup[pvt->mc_node_id] = pvt; 30807d6034d3SDoug Thompson 30817d6034d3SDoug Thompson return 0; 30827d6034d3SDoug Thompson 30837d6034d3SDoug Thompson err_put: 30847d6034d3SDoug Thompson amd64_free_mc_sibling_devices(pvt); 30857d6034d3SDoug Thompson 30867d6034d3SDoug Thompson err_free: 30877d6034d3SDoug Thompson kfree(pvt); 30887d6034d3SDoug Thompson 30897d6034d3SDoug Thompson err_exit: 30907d6034d3SDoug Thompson return ret; 30917d6034d3SDoug Thompson } 30927d6034d3SDoug Thompson 30937d6034d3SDoug Thompson /* 30947d6034d3SDoug Thompson * This is the finishing stage of the init code. Needs to be performed after all 30957d6034d3SDoug Thompson * MCs' hardware have been prepped for accessing extended config space. 30967d6034d3SDoug Thompson */ 30977d6034d3SDoug Thompson static int amd64_init_2nd_stage(struct amd64_pvt *pvt) 30987d6034d3SDoug Thompson { 30997d6034d3SDoug Thompson int node_id = pvt->mc_node_id; 31007d6034d3SDoug Thompson struct mem_ctl_info *mci; 31017d6034d3SDoug Thompson int ret, err = 0; 31027d6034d3SDoug Thompson 31037d6034d3SDoug Thompson amd64_read_mc_registers(pvt); 31047d6034d3SDoug Thompson 31057d6034d3SDoug Thompson ret = -ENODEV; 31067d6034d3SDoug Thompson if (pvt->ops->probe_valid_hardware) { 31077d6034d3SDoug Thompson err = pvt->ops->probe_valid_hardware(pvt); 31087d6034d3SDoug Thompson if (err) 31097d6034d3SDoug Thompson goto err_exit; 31107d6034d3SDoug Thompson } 31117d6034d3SDoug Thompson 31127d6034d3SDoug Thompson /* 31137d6034d3SDoug Thompson * We need to determine how many memory channels there are. Then use 31147d6034d3SDoug Thompson * that information for calculating the size of the dynamic instance 31157d6034d3SDoug Thompson * tables in the 'mci' structure 31167d6034d3SDoug Thompson */ 31177d6034d3SDoug Thompson pvt->channel_count = pvt->ops->early_channel_count(pvt); 31187d6034d3SDoug Thompson if (pvt->channel_count < 0) 31197d6034d3SDoug Thompson goto err_exit; 31207d6034d3SDoug Thompson 31217d6034d3SDoug Thompson ret = -ENOMEM; 31227d6034d3SDoug Thompson mci = edac_mc_alloc(0, CHIPSELECT_COUNT, pvt->channel_count, node_id); 31237d6034d3SDoug Thompson if (!mci) 31247d6034d3SDoug Thompson goto err_exit; 31257d6034d3SDoug Thompson 31267d6034d3SDoug Thompson mci->pvt_info = pvt; 31277d6034d3SDoug Thompson 31287d6034d3SDoug Thompson mci->dev = &pvt->dram_f2_ctl->dev; 31297d6034d3SDoug Thompson amd64_setup_mci_misc_attributes(mci); 31307d6034d3SDoug Thompson 31317d6034d3SDoug Thompson if (amd64_init_csrows(mci)) 31327d6034d3SDoug Thompson mci->edac_cap = EDAC_FLAG_NONE; 31337d6034d3SDoug Thompson 31347d6034d3SDoug Thompson amd64_enable_ecc_error_reporting(mci); 31357d6034d3SDoug Thompson amd64_set_mc_sysfs_attributes(mci); 31367d6034d3SDoug Thompson 31377d6034d3SDoug Thompson ret = -ENODEV; 31387d6034d3SDoug Thompson if (edac_mc_add_mc(mci)) { 31397d6034d3SDoug Thompson debugf1("failed edac_mc_add_mc()\n"); 31407d6034d3SDoug Thompson goto err_add_mc; 31417d6034d3SDoug Thompson } 31427d6034d3SDoug Thompson 31437d6034d3SDoug Thompson mci_lookup[node_id] = mci; 31447d6034d3SDoug Thompson pvt_lookup[node_id] = NULL; 31457d6034d3SDoug Thompson return 0; 31467d6034d3SDoug Thompson 31477d6034d3SDoug Thompson err_add_mc: 31487d6034d3SDoug Thompson edac_mc_free(mci); 31497d6034d3SDoug Thompson 31507d6034d3SDoug Thompson err_exit: 31517d6034d3SDoug Thompson debugf0("failure to init 2nd stage: ret=%d\n", ret); 31527d6034d3SDoug Thompson 31537d6034d3SDoug Thompson amd64_restore_ecc_error_reporting(pvt); 31547d6034d3SDoug Thompson 31557d6034d3SDoug Thompson if (boot_cpu_data.x86 > 0xf) 31567d6034d3SDoug Thompson amd64_teardown(pvt); 31577d6034d3SDoug Thompson 31587d6034d3SDoug Thompson amd64_free_mc_sibling_devices(pvt); 31597d6034d3SDoug Thompson 31607d6034d3SDoug Thompson kfree(pvt_lookup[pvt->mc_node_id]); 31617d6034d3SDoug Thompson pvt_lookup[node_id] = NULL; 31627d6034d3SDoug Thompson 31637d6034d3SDoug Thompson return ret; 31647d6034d3SDoug Thompson } 31657d6034d3SDoug Thompson 31667d6034d3SDoug Thompson 31677d6034d3SDoug Thompson static int __devinit amd64_init_one_instance(struct pci_dev *pdev, 31687d6034d3SDoug Thompson const struct pci_device_id *mc_type) 31697d6034d3SDoug Thompson { 31707d6034d3SDoug Thompson int ret = 0; 31717d6034d3SDoug Thompson 317237da0450SBorislav Petkov debugf0("(MC node=%d,mc_type='%s')\n", get_node_id(pdev), 31737d6034d3SDoug Thompson get_amd_family_name(mc_type->driver_data)); 31747d6034d3SDoug Thompson 31757d6034d3SDoug Thompson ret = pci_enable_device(pdev); 31767d6034d3SDoug Thompson if (ret < 0) 31777d6034d3SDoug Thompson ret = -EIO; 31787d6034d3SDoug Thompson else 31797d6034d3SDoug Thompson ret = amd64_probe_one_instance(pdev, mc_type->driver_data); 31807d6034d3SDoug Thompson 31817d6034d3SDoug Thompson if (ret < 0) 31827d6034d3SDoug Thompson debugf0("ret=%d\n", ret); 31837d6034d3SDoug Thompson 31847d6034d3SDoug Thompson return ret; 31857d6034d3SDoug Thompson } 31867d6034d3SDoug Thompson 31877d6034d3SDoug Thompson static void __devexit amd64_remove_one_instance(struct pci_dev *pdev) 31887d6034d3SDoug Thompson { 31897d6034d3SDoug Thompson struct mem_ctl_info *mci; 31907d6034d3SDoug Thompson struct amd64_pvt *pvt; 31917d6034d3SDoug Thompson 31927d6034d3SDoug Thompson /* Remove from EDAC CORE tracking list */ 31937d6034d3SDoug Thompson mci = edac_mc_del_mc(&pdev->dev); 31947d6034d3SDoug Thompson if (!mci) 31957d6034d3SDoug Thompson return; 31967d6034d3SDoug Thompson 31977d6034d3SDoug Thompson pvt = mci->pvt_info; 31987d6034d3SDoug Thompson 31997d6034d3SDoug Thompson amd64_restore_ecc_error_reporting(pvt); 32007d6034d3SDoug Thompson 32017d6034d3SDoug Thompson if (boot_cpu_data.x86 > 0xf) 32027d6034d3SDoug Thompson amd64_teardown(pvt); 32037d6034d3SDoug Thompson 32047d6034d3SDoug Thompson amd64_free_mc_sibling_devices(pvt); 32057d6034d3SDoug Thompson 32067d6034d3SDoug Thompson kfree(pvt); 32077d6034d3SDoug Thompson mci->pvt_info = NULL; 32087d6034d3SDoug Thompson 32097d6034d3SDoug Thompson mci_lookup[pvt->mc_node_id] = NULL; 32107d6034d3SDoug Thompson 32117d6034d3SDoug Thompson /* Free the EDAC CORE resources */ 32127d6034d3SDoug Thompson edac_mc_free(mci); 32137d6034d3SDoug Thompson } 32147d6034d3SDoug Thompson 32157d6034d3SDoug Thompson /* 32167d6034d3SDoug Thompson * This table is part of the interface for loading drivers for PCI devices. The 32177d6034d3SDoug Thompson * PCI core identifies what devices are on a system during boot, and then 32187d6034d3SDoug Thompson * inquiry this table to see if this driver is for a given device found. 32197d6034d3SDoug Thompson */ 32207d6034d3SDoug Thompson static const struct pci_device_id amd64_pci_table[] __devinitdata = { 32217d6034d3SDoug Thompson { 32227d6034d3SDoug Thompson .vendor = PCI_VENDOR_ID_AMD, 32237d6034d3SDoug Thompson .device = PCI_DEVICE_ID_AMD_K8_NB_MEMCTL, 32247d6034d3SDoug Thompson .subvendor = PCI_ANY_ID, 32257d6034d3SDoug Thompson .subdevice = PCI_ANY_ID, 32267d6034d3SDoug Thompson .class = 0, 32277d6034d3SDoug Thompson .class_mask = 0, 32287d6034d3SDoug Thompson .driver_data = K8_CPUS 32297d6034d3SDoug Thompson }, 32307d6034d3SDoug Thompson { 32317d6034d3SDoug Thompson .vendor = PCI_VENDOR_ID_AMD, 32327d6034d3SDoug Thompson .device = PCI_DEVICE_ID_AMD_10H_NB_DRAM, 32337d6034d3SDoug Thompson .subvendor = PCI_ANY_ID, 32347d6034d3SDoug Thompson .subdevice = PCI_ANY_ID, 32357d6034d3SDoug Thompson .class = 0, 32367d6034d3SDoug Thompson .class_mask = 0, 32377d6034d3SDoug Thompson .driver_data = F10_CPUS 32387d6034d3SDoug Thompson }, 32397d6034d3SDoug Thompson { 32407d6034d3SDoug Thompson .vendor = PCI_VENDOR_ID_AMD, 32417d6034d3SDoug Thompson .device = PCI_DEVICE_ID_AMD_11H_NB_DRAM, 32427d6034d3SDoug Thompson .subvendor = PCI_ANY_ID, 32437d6034d3SDoug Thompson .subdevice = PCI_ANY_ID, 32447d6034d3SDoug Thompson .class = 0, 32457d6034d3SDoug Thompson .class_mask = 0, 32467d6034d3SDoug Thompson .driver_data = F11_CPUS 32477d6034d3SDoug Thompson }, 32487d6034d3SDoug Thompson {0, } 32497d6034d3SDoug Thompson }; 32507d6034d3SDoug Thompson MODULE_DEVICE_TABLE(pci, amd64_pci_table); 32517d6034d3SDoug Thompson 32527d6034d3SDoug Thompson static struct pci_driver amd64_pci_driver = { 32537d6034d3SDoug Thompson .name = EDAC_MOD_STR, 32547d6034d3SDoug Thompson .probe = amd64_init_one_instance, 32557d6034d3SDoug Thompson .remove = __devexit_p(amd64_remove_one_instance), 32567d6034d3SDoug Thompson .id_table = amd64_pci_table, 32577d6034d3SDoug Thompson }; 32587d6034d3SDoug Thompson 32597d6034d3SDoug Thompson static void amd64_setup_pci_device(void) 32607d6034d3SDoug Thompson { 32617d6034d3SDoug Thompson struct mem_ctl_info *mci; 32627d6034d3SDoug Thompson struct amd64_pvt *pvt; 32637d6034d3SDoug Thompson 32647d6034d3SDoug Thompson if (amd64_ctl_pci) 32657d6034d3SDoug Thompson return; 32667d6034d3SDoug Thompson 32677d6034d3SDoug Thompson mci = mci_lookup[0]; 32687d6034d3SDoug Thompson if (mci) { 32697d6034d3SDoug Thompson 32707d6034d3SDoug Thompson pvt = mci->pvt_info; 32717d6034d3SDoug Thompson amd64_ctl_pci = 32727d6034d3SDoug Thompson edac_pci_create_generic_ctl(&pvt->dram_f2_ctl->dev, 32737d6034d3SDoug Thompson EDAC_MOD_STR); 32747d6034d3SDoug Thompson 32757d6034d3SDoug Thompson if (!amd64_ctl_pci) { 32767d6034d3SDoug Thompson pr_warning("%s(): Unable to create PCI control\n", 32777d6034d3SDoug Thompson __func__); 32787d6034d3SDoug Thompson 32797d6034d3SDoug Thompson pr_warning("%s(): PCI error report via EDAC not set\n", 32807d6034d3SDoug Thompson __func__); 32817d6034d3SDoug Thompson } 32827d6034d3SDoug Thompson } 32837d6034d3SDoug Thompson } 32847d6034d3SDoug Thompson 32857d6034d3SDoug Thompson static int __init amd64_edac_init(void) 32867d6034d3SDoug Thompson { 32877d6034d3SDoug Thompson int nb, err = -ENODEV; 32887d6034d3SDoug Thompson 32897d6034d3SDoug Thompson edac_printk(KERN_INFO, EDAC_MOD_STR, EDAC_AMD64_VERSION "\n"); 32907d6034d3SDoug Thompson 32917d6034d3SDoug Thompson opstate_init(); 32927d6034d3SDoug Thompson 32937d6034d3SDoug Thompson if (cache_k8_northbridges() < 0) 32947d6034d3SDoug Thompson goto err_exit; 32957d6034d3SDoug Thompson 32967d6034d3SDoug Thompson err = pci_register_driver(&amd64_pci_driver); 32977d6034d3SDoug Thompson if (err) 32987d6034d3SDoug Thompson return err; 32997d6034d3SDoug Thompson 33007d6034d3SDoug Thompson /* 33017d6034d3SDoug Thompson * At this point, the array 'pvt_lookup[]' contains pointers to alloc'd 33027d6034d3SDoug Thompson * amd64_pvt structs. These will be used in the 2nd stage init function 33037d6034d3SDoug Thompson * to finish initialization of the MC instances. 33047d6034d3SDoug Thompson */ 33057d6034d3SDoug Thompson for (nb = 0; nb < num_k8_northbridges; nb++) { 33067d6034d3SDoug Thompson if (!pvt_lookup[nb]) 33077d6034d3SDoug Thompson continue; 33087d6034d3SDoug Thompson 33097d6034d3SDoug Thompson err = amd64_init_2nd_stage(pvt_lookup[nb]); 33107d6034d3SDoug Thompson if (err) 331137da0450SBorislav Petkov goto err_2nd_stage; 33127d6034d3SDoug Thompson } 33137d6034d3SDoug Thompson 33147d6034d3SDoug Thompson amd64_setup_pci_device(); 33157d6034d3SDoug Thompson 33167d6034d3SDoug Thompson return 0; 33177d6034d3SDoug Thompson 331837da0450SBorislav Petkov err_2nd_stage: 331937da0450SBorislav Petkov debugf0("2nd stage failed\n"); 332037da0450SBorislav Petkov 33217d6034d3SDoug Thompson err_exit: 33227d6034d3SDoug Thompson pci_unregister_driver(&amd64_pci_driver); 33237d6034d3SDoug Thompson 33247d6034d3SDoug Thompson return err; 33257d6034d3SDoug Thompson } 33267d6034d3SDoug Thompson 33277d6034d3SDoug Thompson static void __exit amd64_edac_exit(void) 33287d6034d3SDoug Thompson { 33297d6034d3SDoug Thompson if (amd64_ctl_pci) 33307d6034d3SDoug Thompson edac_pci_release_generic_ctl(amd64_ctl_pci); 33317d6034d3SDoug Thompson 33327d6034d3SDoug Thompson pci_unregister_driver(&amd64_pci_driver); 33337d6034d3SDoug Thompson } 33347d6034d3SDoug Thompson 33357d6034d3SDoug Thompson module_init(amd64_edac_init); 33367d6034d3SDoug Thompson module_exit(amd64_edac_exit); 33377d6034d3SDoug Thompson 33387d6034d3SDoug Thompson MODULE_LICENSE("GPL"); 33397d6034d3SDoug Thompson MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, " 33407d6034d3SDoug Thompson "Dave Peterson, Thayne Harbaugh"); 33417d6034d3SDoug Thompson MODULE_DESCRIPTION("MC support for AMD64 memory controllers - " 33427d6034d3SDoug Thompson EDAC_AMD64_VERSION); 33437d6034d3SDoug Thompson 33447d6034d3SDoug Thompson module_param(edac_op_state, int, 0444); 33457d6034d3SDoug Thompson MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 3346