1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved 4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved. 5 * Copyright 2011-2012 Calxeda, Inc. 6 */ 7 8 #include <asm/cacheflush.h> 9 #include <linux/ctype.h> 10 #include <linux/delay.h> 11 #include <linux/edac.h> 12 #include <linux/firmware/intel/stratix10-smc.h> 13 #include <linux/genalloc.h> 14 #include <linux/interrupt.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/kernel.h> 17 #include <linux/mfd/altera-sysmgr.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/notifier.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_platform.h> 23 #include <linux/panic_notifier.h> 24 #include <linux/platform_device.h> 25 #include <linux/regmap.h> 26 #include <linux/types.h> 27 #include <linux/uaccess.h> 28 29 #include "altera_edac.h" 30 #include "edac_module.h" 31 32 #define EDAC_MOD_STR "altera_edac" 33 #define EDAC_DEVICE "Altera" 34 35 #ifdef CONFIG_EDAC_ALTERA_SDRAM 36 static const struct altr_sdram_prv_data c5_data = { 37 .ecc_ctrl_offset = CV_CTLCFG_OFST, 38 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN, 39 .ecc_stat_offset = CV_DRAMSTS_OFST, 40 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR, 41 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR, 42 .ecc_saddr_offset = CV_ERRADDR_OFST, 43 .ecc_daddr_offset = CV_ERRADDR_OFST, 44 .ecc_cecnt_offset = CV_SBECOUNT_OFST, 45 .ecc_uecnt_offset = CV_DBECOUNT_OFST, 46 .ecc_irq_en_offset = CV_DRAMINTR_OFST, 47 .ecc_irq_en_mask = CV_DRAMINTR_INTREN, 48 .ecc_irq_clr_offset = CV_DRAMINTR_OFST, 49 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN), 50 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST, 51 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR, 52 .ce_ue_trgr_offset = CV_CTLCFG_OFST, 53 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR, 54 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR, 55 }; 56 57 static const struct altr_sdram_prv_data a10_data = { 58 .ecc_ctrl_offset = A10_ECCCTRL1_OFST, 59 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN, 60 .ecc_stat_offset = A10_INTSTAT_OFST, 61 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR, 62 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR, 63 .ecc_saddr_offset = A10_SERRADDR_OFST, 64 .ecc_daddr_offset = A10_DERRADDR_OFST, 65 .ecc_irq_en_offset = A10_ERRINTEN_OFST, 66 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK, 67 .ecc_irq_clr_offset = A10_INTSTAT_OFST, 68 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR), 69 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST, 70 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK, 71 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST, 72 .ce_set_mask = A10_DIAGINT_TSERRA_MASK, 73 .ue_set_mask = A10_DIAGINT_TDERRA_MASK, 74 }; 75 76 /*********************** EDAC Memory Controller Functions ****************/ 77 78 /* The SDRAM controller uses the EDAC Memory Controller framework. */ 79 80 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id) 81 { 82 struct mem_ctl_info *mci = dev_id; 83 struct altr_sdram_mc_data *drvdata = mci->pvt_info; 84 const struct altr_sdram_prv_data *priv = drvdata->data; 85 u32 status, err_count = 1, err_addr; 86 87 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status); 88 89 if (status & priv->ecc_stat_ue_mask) { 90 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset, 91 &err_addr); 92 if (priv->ecc_uecnt_offset) 93 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset, 94 &err_count); 95 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n", 96 err_count, err_addr); 97 } 98 if (status & priv->ecc_stat_ce_mask) { 99 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, 100 &err_addr); 101 if (priv->ecc_uecnt_offset) 102 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset, 103 &err_count); 104 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count, 105 err_addr >> PAGE_SHIFT, 106 err_addr & ~PAGE_MASK, 0, 107 0, 0, -1, mci->ctl_name, ""); 108 /* Clear IRQ to resume */ 109 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset, 110 priv->ecc_irq_clr_mask); 111 112 return IRQ_HANDLED; 113 } 114 return IRQ_NONE; 115 } 116 117 static ssize_t altr_sdr_mc_err_inject_write(struct file *file, 118 const char __user *data, 119 size_t count, loff_t *ppos) 120 { 121 struct mem_ctl_info *mci = file->private_data; 122 struct altr_sdram_mc_data *drvdata = mci->pvt_info; 123 const struct altr_sdram_prv_data *priv = drvdata->data; 124 u32 *ptemp; 125 dma_addr_t dma_handle; 126 u32 reg, read_reg; 127 128 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL); 129 if (!ptemp) { 130 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); 131 edac_printk(KERN_ERR, EDAC_MC, 132 "Inject: Buffer Allocation error\n"); 133 return -ENOMEM; 134 } 135 136 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset, 137 &read_reg); 138 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask); 139 140 /* Error are injected by writing a word while the SBE or DBE 141 * bit in the CTLCFG register is set. Reading the word will 142 * trigger the SBE or DBE error and the corresponding IRQ. 143 */ 144 if (count == 3) { 145 edac_printk(KERN_ALERT, EDAC_MC, 146 "Inject Double bit error\n"); 147 local_irq_disable(); 148 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, 149 (read_reg | priv->ue_set_mask)); 150 local_irq_enable(); 151 } else { 152 edac_printk(KERN_ALERT, EDAC_MC, 153 "Inject Single bit error\n"); 154 local_irq_disable(); 155 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, 156 (read_reg | priv->ce_set_mask)); 157 local_irq_enable(); 158 } 159 160 ptemp[0] = 0x5A5A5A5A; 161 ptemp[1] = 0xA5A5A5A5; 162 163 /* Clear the error injection bits */ 164 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg); 165 /* Ensure it has been written out */ 166 wmb(); 167 168 /* 169 * To trigger the error, we need to read the data back 170 * (the data was written with errors above). 171 * The READ_ONCE macros and printk are used to prevent the 172 * the compiler optimizing these reads out. 173 */ 174 reg = READ_ONCE(ptemp[0]); 175 read_reg = READ_ONCE(ptemp[1]); 176 /* Force Read */ 177 rmb(); 178 179 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n", 180 reg, read_reg); 181 182 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); 183 184 return count; 185 } 186 187 static const struct file_operations altr_sdr_mc_debug_inject_fops = { 188 .open = simple_open, 189 .write = altr_sdr_mc_err_inject_write, 190 .llseek = generic_file_llseek, 191 }; 192 193 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci) 194 { 195 if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) 196 return; 197 198 if (!mci->debugfs) 199 return; 200 201 edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci, 202 &altr_sdr_mc_debug_inject_fops); 203 } 204 205 /* Get total memory size from Open Firmware DTB */ 206 static unsigned long get_total_mem(void) 207 { 208 struct device_node *np = NULL; 209 struct resource res; 210 int ret; 211 unsigned long total_mem = 0; 212 213 for_each_node_by_type(np, "memory") { 214 ret = of_address_to_resource(np, 0, &res); 215 if (ret) 216 continue; 217 218 total_mem += resource_size(&res); 219 } 220 edac_dbg(0, "total_mem 0x%lx\n", total_mem); 221 return total_mem; 222 } 223 224 static const struct of_device_id altr_sdram_ctrl_of_match[] = { 225 { .compatible = "altr,sdram-edac", .data = &c5_data}, 226 { .compatible = "altr,sdram-edac-a10", .data = &a10_data}, 227 {}, 228 }; 229 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match); 230 231 static int a10_init(struct regmap *mc_vbase) 232 { 233 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST, 234 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) { 235 edac_printk(KERN_ERR, EDAC_MC, 236 "Error setting SB IRQ mode\n"); 237 return -ENODEV; 238 } 239 240 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) { 241 edac_printk(KERN_ERR, EDAC_MC, 242 "Error setting trigger count\n"); 243 return -ENODEV; 244 } 245 246 return 0; 247 } 248 249 static int a10_unmask_irq(struct platform_device *pdev, u32 mask) 250 { 251 void __iomem *sm_base; 252 int ret = 0; 253 254 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32), 255 dev_name(&pdev->dev))) { 256 edac_printk(KERN_ERR, EDAC_MC, 257 "Unable to request mem region\n"); 258 return -EBUSY; 259 } 260 261 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32)); 262 if (!sm_base) { 263 edac_printk(KERN_ERR, EDAC_MC, 264 "Unable to ioremap device\n"); 265 266 ret = -ENOMEM; 267 goto release; 268 } 269 270 iowrite32(mask, sm_base); 271 272 iounmap(sm_base); 273 274 release: 275 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32)); 276 277 return ret; 278 } 279 280 static int altr_sdram_probe(struct platform_device *pdev) 281 { 282 const struct of_device_id *id; 283 struct edac_mc_layer layers[2]; 284 struct mem_ctl_info *mci; 285 struct altr_sdram_mc_data *drvdata; 286 const struct altr_sdram_prv_data *priv; 287 struct regmap *mc_vbase; 288 struct dimm_info *dimm; 289 u32 read_reg; 290 int irq, irq2, res = 0; 291 unsigned long mem_size, irqflags = 0; 292 293 id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev); 294 if (!id) 295 return -ENODEV; 296 297 /* Grab the register range from the sdr controller in device tree */ 298 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 299 "altr,sdr-syscon"); 300 if (IS_ERR(mc_vbase)) { 301 edac_printk(KERN_ERR, EDAC_MC, 302 "regmap for altr,sdr-syscon lookup failed.\n"); 303 return -ENODEV; 304 } 305 306 /* Check specific dependencies for the module */ 307 priv = of_match_node(altr_sdram_ctrl_of_match, 308 pdev->dev.of_node)->data; 309 310 /* Validate the SDRAM controller has ECC enabled */ 311 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) || 312 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) { 313 edac_printk(KERN_ERR, EDAC_MC, 314 "No ECC/ECC disabled [0x%08X]\n", read_reg); 315 return -ENODEV; 316 } 317 318 /* Grab memory size from device tree. */ 319 mem_size = get_total_mem(); 320 if (!mem_size) { 321 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n"); 322 return -ENODEV; 323 } 324 325 /* Ensure the SDRAM Interrupt is disabled */ 326 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset, 327 priv->ecc_irq_en_mask, 0)) { 328 edac_printk(KERN_ERR, EDAC_MC, 329 "Error disabling SDRAM ECC IRQ\n"); 330 return -ENODEV; 331 } 332 333 /* Toggle to clear the SDRAM Error count */ 334 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, 335 priv->ecc_cnt_rst_mask, 336 priv->ecc_cnt_rst_mask)) { 337 edac_printk(KERN_ERR, EDAC_MC, 338 "Error clearing SDRAM ECC count\n"); 339 return -ENODEV; 340 } 341 342 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, 343 priv->ecc_cnt_rst_mask, 0)) { 344 edac_printk(KERN_ERR, EDAC_MC, 345 "Error clearing SDRAM ECC count\n"); 346 return -ENODEV; 347 } 348 349 irq = platform_get_irq(pdev, 0); 350 if (irq < 0) { 351 edac_printk(KERN_ERR, EDAC_MC, 352 "No irq %d in DT\n", irq); 353 return irq; 354 } 355 356 /* Arria10 has a 2nd IRQ */ 357 irq2 = platform_get_irq(pdev, 1); 358 359 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 360 layers[0].size = 1; 361 layers[0].is_virt_csrow = true; 362 layers[1].type = EDAC_MC_LAYER_CHANNEL; 363 layers[1].size = 1; 364 layers[1].is_virt_csrow = false; 365 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 366 sizeof(struct altr_sdram_mc_data)); 367 if (!mci) 368 return -ENOMEM; 369 370 mci->pdev = &pdev->dev; 371 drvdata = mci->pvt_info; 372 drvdata->mc_vbase = mc_vbase; 373 drvdata->data = priv; 374 platform_set_drvdata(pdev, mci); 375 376 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { 377 edac_printk(KERN_ERR, EDAC_MC, 378 "Unable to get managed device resource\n"); 379 res = -ENOMEM; 380 goto free; 381 } 382 383 mci->mtype_cap = MEM_FLAG_DDR3; 384 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 385 mci->edac_cap = EDAC_FLAG_SECDED; 386 mci->mod_name = EDAC_MOD_STR; 387 mci->ctl_name = dev_name(&pdev->dev); 388 mci->scrub_mode = SCRUB_SW_SRC; 389 mci->dev_name = dev_name(&pdev->dev); 390 391 dimm = *mci->dimms; 392 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1; 393 dimm->grain = 8; 394 dimm->dtype = DEV_X8; 395 dimm->mtype = MEM_DDR3; 396 dimm->edac_mode = EDAC_SECDED; 397 398 res = edac_mc_add_mc(mci); 399 if (res < 0) 400 goto err; 401 402 /* Only the Arria10 has separate IRQs */ 403 if (of_machine_is_compatible("altr,socfpga-arria10")) { 404 /* Arria10 specific initialization */ 405 res = a10_init(mc_vbase); 406 if (res < 0) 407 goto err2; 408 409 res = devm_request_irq(&pdev->dev, irq2, 410 altr_sdram_mc_err_handler, 411 IRQF_SHARED, dev_name(&pdev->dev), mci); 412 if (res < 0) { 413 edac_mc_printk(mci, KERN_ERR, 414 "Unable to request irq %d\n", irq2); 415 res = -ENODEV; 416 goto err2; 417 } 418 419 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK); 420 if (res < 0) 421 goto err2; 422 423 irqflags = IRQF_SHARED; 424 } 425 426 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler, 427 irqflags, dev_name(&pdev->dev), mci); 428 if (res < 0) { 429 edac_mc_printk(mci, KERN_ERR, 430 "Unable to request irq %d\n", irq); 431 res = -ENODEV; 432 goto err2; 433 } 434 435 /* Infrastructure ready - enable the IRQ */ 436 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset, 437 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) { 438 edac_mc_printk(mci, KERN_ERR, 439 "Error enabling SDRAM ECC IRQ\n"); 440 res = -ENODEV; 441 goto err2; 442 } 443 444 altr_sdr_mc_create_debugfs_nodes(mci); 445 446 devres_close_group(&pdev->dev, NULL); 447 448 return 0; 449 450 err2: 451 edac_mc_del_mc(&pdev->dev); 452 err: 453 devres_release_group(&pdev->dev, NULL); 454 free: 455 edac_mc_free(mci); 456 edac_printk(KERN_ERR, EDAC_MC, 457 "EDAC Probe Failed; Error %d\n", res); 458 459 return res; 460 } 461 462 static int altr_sdram_remove(struct platform_device *pdev) 463 { 464 struct mem_ctl_info *mci = platform_get_drvdata(pdev); 465 466 edac_mc_del_mc(&pdev->dev); 467 edac_mc_free(mci); 468 platform_set_drvdata(pdev, NULL); 469 470 return 0; 471 } 472 473 /* 474 * If you want to suspend, need to disable EDAC by removing it 475 * from the device tree or defconfig. 476 */ 477 #ifdef CONFIG_PM 478 static int altr_sdram_prepare(struct device *dev) 479 { 480 pr_err("Suspend not allowed when EDAC is enabled.\n"); 481 482 return -EPERM; 483 } 484 485 static const struct dev_pm_ops altr_sdram_pm_ops = { 486 .prepare = altr_sdram_prepare, 487 }; 488 #endif 489 490 static struct platform_driver altr_sdram_edac_driver = { 491 .probe = altr_sdram_probe, 492 .remove = altr_sdram_remove, 493 .driver = { 494 .name = "altr_sdram_edac", 495 #ifdef CONFIG_PM 496 .pm = &altr_sdram_pm_ops, 497 #endif 498 .of_match_table = altr_sdram_ctrl_of_match, 499 }, 500 }; 501 502 module_platform_driver(altr_sdram_edac_driver); 503 504 #endif /* CONFIG_EDAC_ALTERA_SDRAM */ 505 506 /************************* EDAC Parent Probe *************************/ 507 508 static const struct of_device_id altr_edac_device_of_match[]; 509 510 static const struct of_device_id altr_edac_of_match[] = { 511 { .compatible = "altr,socfpga-ecc-manager" }, 512 {}, 513 }; 514 MODULE_DEVICE_TABLE(of, altr_edac_of_match); 515 516 static int altr_edac_probe(struct platform_device *pdev) 517 { 518 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match, 519 NULL, &pdev->dev); 520 return 0; 521 } 522 523 static struct platform_driver altr_edac_driver = { 524 .probe = altr_edac_probe, 525 .driver = { 526 .name = "socfpga_ecc_manager", 527 .of_match_table = altr_edac_of_match, 528 }, 529 }; 530 module_platform_driver(altr_edac_driver); 531 532 /************************* EDAC Device Functions *************************/ 533 534 /* 535 * EDAC Device Functions (shared between various IPs). 536 * The discrete memories use the EDAC Device framework. The probe 537 * and error handling functions are very similar between memories 538 * so they are shared. The memory allocation and freeing for EDAC 539 * trigger testing are different for each memory. 540 */ 541 542 #ifdef CONFIG_EDAC_ALTERA_OCRAM 543 static const struct edac_device_prv_data ocramecc_data; 544 #endif 545 #ifdef CONFIG_EDAC_ALTERA_L2C 546 static const struct edac_device_prv_data l2ecc_data; 547 #endif 548 #ifdef CONFIG_EDAC_ALTERA_OCRAM 549 static const struct edac_device_prv_data a10_ocramecc_data; 550 #endif 551 #ifdef CONFIG_EDAC_ALTERA_L2C 552 static const struct edac_device_prv_data a10_l2ecc_data; 553 #endif 554 555 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id) 556 { 557 irqreturn_t ret_value = IRQ_NONE; 558 struct edac_device_ctl_info *dci = dev_id; 559 struct altr_edac_device_dev *drvdata = dci->pvt_info; 560 const struct edac_device_prv_data *priv = drvdata->data; 561 562 if (irq == drvdata->sb_irq) { 563 if (priv->ce_clear_mask) 564 writel(priv->ce_clear_mask, drvdata->base); 565 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name); 566 ret_value = IRQ_HANDLED; 567 } else if (irq == drvdata->db_irq) { 568 if (priv->ue_clear_mask) 569 writel(priv->ue_clear_mask, drvdata->base); 570 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name); 571 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); 572 ret_value = IRQ_HANDLED; 573 } else { 574 WARN_ON(1); 575 } 576 577 return ret_value; 578 } 579 580 static ssize_t __maybe_unused 581 altr_edac_device_trig(struct file *file, const char __user *user_buf, 582 size_t count, loff_t *ppos) 583 584 { 585 u32 *ptemp, i, error_mask; 586 int result = 0; 587 u8 trig_type; 588 unsigned long flags; 589 struct edac_device_ctl_info *edac_dci = file->private_data; 590 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 591 const struct edac_device_prv_data *priv = drvdata->data; 592 void *generic_ptr = edac_dci->dev; 593 594 if (!user_buf || get_user(trig_type, user_buf)) 595 return -EFAULT; 596 597 if (!priv->alloc_mem) 598 return -ENOMEM; 599 600 /* 601 * Note that generic_ptr is initialized to the device * but in 602 * some alloc_functions, this is overridden and returns data. 603 */ 604 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr); 605 if (!ptemp) { 606 edac_printk(KERN_ERR, EDAC_DEVICE, 607 "Inject: Buffer Allocation error\n"); 608 return -ENOMEM; 609 } 610 611 if (trig_type == ALTR_UE_TRIGGER_CHAR) 612 error_mask = priv->ue_set_mask; 613 else 614 error_mask = priv->ce_set_mask; 615 616 edac_printk(KERN_ALERT, EDAC_DEVICE, 617 "Trigger Error Mask (0x%X)\n", error_mask); 618 619 local_irq_save(flags); 620 /* write ECC corrupted data out. */ 621 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) { 622 /* Read data so we're in the correct state */ 623 rmb(); 624 if (READ_ONCE(ptemp[i])) 625 result = -1; 626 /* Toggle Error bit (it is latched), leave ECC enabled */ 627 writel(error_mask, (drvdata->base + priv->set_err_ofst)); 628 writel(priv->ecc_enable_mask, (drvdata->base + 629 priv->set_err_ofst)); 630 ptemp[i] = i; 631 } 632 /* Ensure it has been written out */ 633 wmb(); 634 local_irq_restore(flags); 635 636 if (result) 637 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n"); 638 639 /* Read out written data. ECC error caused here */ 640 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++) 641 if (READ_ONCE(ptemp[i]) != i) 642 edac_printk(KERN_ERR, EDAC_DEVICE, 643 "Read doesn't match written data\n"); 644 645 if (priv->free_mem) 646 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr); 647 648 return count; 649 } 650 651 static const struct file_operations altr_edac_device_inject_fops __maybe_unused = { 652 .open = simple_open, 653 .write = altr_edac_device_trig, 654 .llseek = generic_file_llseek, 655 }; 656 657 static ssize_t __maybe_unused 658 altr_edac_a10_device_trig(struct file *file, const char __user *user_buf, 659 size_t count, loff_t *ppos); 660 661 static const struct file_operations altr_edac_a10_device_inject_fops __maybe_unused = { 662 .open = simple_open, 663 .write = altr_edac_a10_device_trig, 664 .llseek = generic_file_llseek, 665 }; 666 667 static ssize_t __maybe_unused 668 altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf, 669 size_t count, loff_t *ppos); 670 671 static const struct file_operations altr_edac_a10_device_inject2_fops __maybe_unused = { 672 .open = simple_open, 673 .write = altr_edac_a10_device_trig2, 674 .llseek = generic_file_llseek, 675 }; 676 677 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci, 678 const struct edac_device_prv_data *priv) 679 { 680 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 681 682 if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) 683 return; 684 685 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name); 686 if (!drvdata->debugfs_dir) 687 return; 688 689 if (!edac_debugfs_create_file("altr_trigger", S_IWUSR, 690 drvdata->debugfs_dir, edac_dci, 691 priv->inject_fops)) 692 debugfs_remove_recursive(drvdata->debugfs_dir); 693 } 694 695 static const struct of_device_id altr_edac_device_of_match[] = { 696 #ifdef CONFIG_EDAC_ALTERA_L2C 697 { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data }, 698 #endif 699 #ifdef CONFIG_EDAC_ALTERA_OCRAM 700 { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data }, 701 #endif 702 {}, 703 }; 704 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match); 705 706 /* 707 * altr_edac_device_probe() 708 * This is a generic EDAC device driver that will support 709 * various Altera memory devices such as the L2 cache ECC and 710 * OCRAM ECC as well as the memories for other peripherals. 711 * Module specific initialization is done by passing the 712 * function index in the device tree. 713 */ 714 static int altr_edac_device_probe(struct platform_device *pdev) 715 { 716 struct edac_device_ctl_info *dci; 717 struct altr_edac_device_dev *drvdata; 718 struct resource *r; 719 int res = 0; 720 struct device_node *np = pdev->dev.of_node; 721 char *ecc_name = (char *)np->name; 722 static int dev_instance; 723 724 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { 725 edac_printk(KERN_ERR, EDAC_DEVICE, 726 "Unable to open devm\n"); 727 return -ENOMEM; 728 } 729 730 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 731 if (!r) { 732 edac_printk(KERN_ERR, EDAC_DEVICE, 733 "Unable to get mem resource\n"); 734 res = -ENODEV; 735 goto fail; 736 } 737 738 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r), 739 dev_name(&pdev->dev))) { 740 edac_printk(KERN_ERR, EDAC_DEVICE, 741 "%s:Error requesting mem region\n", ecc_name); 742 res = -EBUSY; 743 goto fail; 744 } 745 746 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name, 747 1, ecc_name, 1, 0, NULL, 0, 748 dev_instance++); 749 750 if (!dci) { 751 edac_printk(KERN_ERR, EDAC_DEVICE, 752 "%s: Unable to allocate EDAC device\n", ecc_name); 753 res = -ENOMEM; 754 goto fail; 755 } 756 757 drvdata = dci->pvt_info; 758 dci->dev = &pdev->dev; 759 platform_set_drvdata(pdev, dci); 760 drvdata->edac_dev_name = ecc_name; 761 762 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); 763 if (!drvdata->base) { 764 res = -ENOMEM; 765 goto fail1; 766 } 767 768 /* Get driver specific data for this EDAC device */ 769 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data; 770 771 /* Check specific dependencies for the module */ 772 if (drvdata->data->setup) { 773 res = drvdata->data->setup(drvdata); 774 if (res) 775 goto fail1; 776 } 777 778 drvdata->sb_irq = platform_get_irq(pdev, 0); 779 res = devm_request_irq(&pdev->dev, drvdata->sb_irq, 780 altr_edac_device_handler, 781 0, dev_name(&pdev->dev), dci); 782 if (res) 783 goto fail1; 784 785 drvdata->db_irq = platform_get_irq(pdev, 1); 786 res = devm_request_irq(&pdev->dev, drvdata->db_irq, 787 altr_edac_device_handler, 788 0, dev_name(&pdev->dev), dci); 789 if (res) 790 goto fail1; 791 792 dci->mod_name = "Altera ECC Manager"; 793 dci->dev_name = drvdata->edac_dev_name; 794 795 res = edac_device_add_device(dci); 796 if (res) 797 goto fail1; 798 799 altr_create_edacdev_dbgfs(dci, drvdata->data); 800 801 devres_close_group(&pdev->dev, NULL); 802 803 return 0; 804 805 fail1: 806 edac_device_free_ctl_info(dci); 807 fail: 808 devres_release_group(&pdev->dev, NULL); 809 edac_printk(KERN_ERR, EDAC_DEVICE, 810 "%s:Error setting up EDAC device: %d\n", ecc_name, res); 811 812 return res; 813 } 814 815 static int altr_edac_device_remove(struct platform_device *pdev) 816 { 817 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev); 818 struct altr_edac_device_dev *drvdata = dci->pvt_info; 819 820 debugfs_remove_recursive(drvdata->debugfs_dir); 821 edac_device_del_device(&pdev->dev); 822 edac_device_free_ctl_info(dci); 823 824 return 0; 825 } 826 827 static struct platform_driver altr_edac_device_driver = { 828 .probe = altr_edac_device_probe, 829 .remove = altr_edac_device_remove, 830 .driver = { 831 .name = "altr_edac_device", 832 .of_match_table = altr_edac_device_of_match, 833 }, 834 }; 835 module_platform_driver(altr_edac_device_driver); 836 837 /******************* Arria10 Device ECC Shared Functions *****************/ 838 839 /* 840 * Test for memory's ECC dependencies upon entry because platform specific 841 * startup should have initialized the memory and enabled the ECC. 842 * Can't turn on ECC here because accessing un-initialized memory will 843 * cause CE/UE errors possibly causing an ABORT. 844 */ 845 static int __maybe_unused 846 altr_check_ecc_deps(struct altr_edac_device_dev *device) 847 { 848 void __iomem *base = device->base; 849 const struct edac_device_prv_data *prv = device->data; 850 851 if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask) 852 return 0; 853 854 edac_printk(KERN_ERR, EDAC_DEVICE, 855 "%s: No ECC present or ECC disabled.\n", 856 device->edac_dev_name); 857 return -ENODEV; 858 } 859 860 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id) 861 { 862 struct altr_edac_device_dev *dci = dev_id; 863 void __iomem *base = dci->base; 864 865 if (irq == dci->sb_irq) { 866 writel(ALTR_A10_ECC_SERRPENA, 867 base + ALTR_A10_ECC_INTSTAT_OFST); 868 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); 869 870 return IRQ_HANDLED; 871 } else if (irq == dci->db_irq) { 872 writel(ALTR_A10_ECC_DERRPENA, 873 base + ALTR_A10_ECC_INTSTAT_OFST); 874 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); 875 if (dci->data->panic) 876 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); 877 878 return IRQ_HANDLED; 879 } 880 881 WARN_ON(1); 882 883 return IRQ_NONE; 884 } 885 886 /******************* Arria10 Memory Buffer Functions *********************/ 887 888 static inline int a10_get_irq_mask(struct device_node *np) 889 { 890 int irq; 891 const u32 *handle = of_get_property(np, "interrupts", NULL); 892 893 if (!handle) 894 return -ENODEV; 895 irq = be32_to_cpup(handle); 896 return irq; 897 } 898 899 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr) 900 { 901 u32 value = readl(ioaddr); 902 903 value |= bit_mask; 904 writel(value, ioaddr); 905 } 906 907 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr) 908 { 909 u32 value = readl(ioaddr); 910 911 value &= ~bit_mask; 912 writel(value, ioaddr); 913 } 914 915 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr) 916 { 917 u32 value = readl(ioaddr); 918 919 return (value & bit_mask) ? 1 : 0; 920 } 921 922 /* 923 * This function uses the memory initialization block in the Arria10 ECC 924 * controller to initialize/clear the entire memory data and ECC data. 925 */ 926 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port) 927 { 928 int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US; 929 u32 init_mask, stat_mask, clear_mask; 930 int ret = 0; 931 932 if (port) { 933 init_mask = ALTR_A10_ECC_INITB; 934 stat_mask = ALTR_A10_ECC_INITCOMPLETEB; 935 clear_mask = ALTR_A10_ECC_ERRPENB_MASK; 936 } else { 937 init_mask = ALTR_A10_ECC_INITA; 938 stat_mask = ALTR_A10_ECC_INITCOMPLETEA; 939 clear_mask = ALTR_A10_ECC_ERRPENA_MASK; 940 } 941 942 ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST)); 943 while (limit--) { 944 if (ecc_test_bits(stat_mask, 945 (ioaddr + ALTR_A10_ECC_INITSTAT_OFST))) 946 break; 947 udelay(1); 948 } 949 if (limit < 0) 950 ret = -EBUSY; 951 952 /* Clear any pending ECC interrupts */ 953 writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST)); 954 955 return ret; 956 } 957 958 static __init int __maybe_unused 959 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask, 960 u32 ecc_ctrl_en_mask, bool dual_port) 961 { 962 int ret = 0; 963 void __iomem *ecc_block_base; 964 struct regmap *ecc_mgr_map; 965 char *ecc_name; 966 struct device_node *np_eccmgr; 967 968 ecc_name = (char *)np->name; 969 970 /* Get the ECC Manager - parent of the device EDACs */ 971 np_eccmgr = of_get_parent(np); 972 973 ecc_mgr_map = 974 altr_sysmgr_regmap_lookup_by_phandle(np_eccmgr, 975 "altr,sysmgr-syscon"); 976 977 of_node_put(np_eccmgr); 978 if (IS_ERR(ecc_mgr_map)) { 979 edac_printk(KERN_ERR, EDAC_DEVICE, 980 "Unable to get syscon altr,sysmgr-syscon\n"); 981 return -ENODEV; 982 } 983 984 /* Map the ECC Block */ 985 ecc_block_base = of_iomap(np, 0); 986 if (!ecc_block_base) { 987 edac_printk(KERN_ERR, EDAC_DEVICE, 988 "Unable to map %s ECC block\n", ecc_name); 989 return -ENODEV; 990 } 991 992 /* Disable ECC */ 993 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask); 994 writel(ALTR_A10_ECC_SERRINTEN, 995 (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST)); 996 ecc_clear_bits(ecc_ctrl_en_mask, 997 (ecc_block_base + ALTR_A10_ECC_CTRL_OFST)); 998 /* Ensure all writes complete */ 999 wmb(); 1000 /* Use HW initialization block to initialize memory for ECC */ 1001 ret = altr_init_memory_port(ecc_block_base, 0); 1002 if (ret) { 1003 edac_printk(KERN_ERR, EDAC_DEVICE, 1004 "ECC: cannot init %s PORTA memory\n", ecc_name); 1005 goto out; 1006 } 1007 1008 if (dual_port) { 1009 ret = altr_init_memory_port(ecc_block_base, 1); 1010 if (ret) { 1011 edac_printk(KERN_ERR, EDAC_DEVICE, 1012 "ECC: cannot init %s PORTB memory\n", 1013 ecc_name); 1014 goto out; 1015 } 1016 } 1017 1018 /* Interrupt mode set to every SBERR */ 1019 regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST, 1020 ALTR_A10_ECC_INTMODE); 1021 /* Enable ECC */ 1022 ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base + 1023 ALTR_A10_ECC_CTRL_OFST)); 1024 writel(ALTR_A10_ECC_SERRINTEN, 1025 (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST)); 1026 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask); 1027 /* Ensure all writes complete */ 1028 wmb(); 1029 out: 1030 iounmap(ecc_block_base); 1031 return ret; 1032 } 1033 1034 static int validate_parent_available(struct device_node *np); 1035 static const struct of_device_id altr_edac_a10_device_of_match[]; 1036 static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat) 1037 { 1038 int irq; 1039 struct device_node *child, *np; 1040 1041 np = of_find_compatible_node(NULL, NULL, 1042 "altr,socfpga-a10-ecc-manager"); 1043 if (!np) { 1044 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n"); 1045 return -ENODEV; 1046 } 1047 1048 for_each_child_of_node(np, child) { 1049 const struct of_device_id *pdev_id; 1050 const struct edac_device_prv_data *prv; 1051 1052 if (!of_device_is_available(child)) 1053 continue; 1054 if (!of_device_is_compatible(child, compat)) 1055 continue; 1056 1057 if (validate_parent_available(child)) 1058 continue; 1059 1060 irq = a10_get_irq_mask(child); 1061 if (irq < 0) 1062 continue; 1063 1064 /* Get matching node and check for valid result */ 1065 pdev_id = of_match_node(altr_edac_a10_device_of_match, child); 1066 if (IS_ERR_OR_NULL(pdev_id)) 1067 continue; 1068 1069 /* Validate private data pointer before dereferencing */ 1070 prv = pdev_id->data; 1071 if (!prv) 1072 continue; 1073 1074 altr_init_a10_ecc_block(child, BIT(irq), 1075 prv->ecc_enable_mask, 0); 1076 } 1077 1078 of_node_put(np); 1079 return 0; 1080 } 1081 1082 /*********************** SDRAM EDAC Device Functions *********************/ 1083 1084 #ifdef CONFIG_EDAC_ALTERA_SDRAM 1085 1086 /* 1087 * A legacy U-Boot bug only enabled memory mapped access to the ECC Enable 1088 * register if ECC is enabled. Linux checks the ECC Enable register to 1089 * determine ECC status. 1090 * Use an SMC call (which always works) to determine ECC enablement. 1091 */ 1092 static int altr_s10_sdram_check_ecc_deps(struct altr_edac_device_dev *device) 1093 { 1094 const struct edac_device_prv_data *prv = device->data; 1095 unsigned long sdram_ecc_addr; 1096 struct arm_smccc_res result; 1097 struct device_node *np; 1098 phys_addr_t sdram_addr; 1099 u32 read_reg; 1100 int ret; 1101 1102 np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl"); 1103 if (!np) 1104 goto sdram_err; 1105 1106 sdram_addr = of_translate_address(np, of_get_address(np, 0, 1107 NULL, NULL)); 1108 of_node_put(np); 1109 sdram_ecc_addr = (unsigned long)sdram_addr + prv->ecc_en_ofst; 1110 arm_smccc_smc(INTEL_SIP_SMC_REG_READ, sdram_ecc_addr, 1111 0, 0, 0, 0, 0, 0, &result); 1112 read_reg = (unsigned int)result.a1; 1113 ret = (int)result.a0; 1114 if (!ret && (read_reg & prv->ecc_enable_mask)) 1115 return 0; 1116 1117 sdram_err: 1118 edac_printk(KERN_ERR, EDAC_DEVICE, 1119 "%s: No ECC present or ECC disabled.\n", 1120 device->edac_dev_name); 1121 return -ENODEV; 1122 } 1123 1124 static const struct edac_device_prv_data s10_sdramecc_data = { 1125 .setup = altr_s10_sdram_check_ecc_deps, 1126 .ce_clear_mask = ALTR_S10_ECC_SERRPENA, 1127 .ue_clear_mask = ALTR_S10_ECC_DERRPENA, 1128 .ecc_enable_mask = ALTR_S10_ECC_EN, 1129 .ecc_en_ofst = ALTR_S10_ECC_CTRL_SDRAM_OFST, 1130 .ce_set_mask = ALTR_S10_ECC_TSERRA, 1131 .ue_set_mask = ALTR_S10_ECC_TDERRA, 1132 .set_err_ofst = ALTR_S10_ECC_INTTEST_OFST, 1133 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1134 .inject_fops = &altr_edac_a10_device_inject_fops, 1135 }; 1136 #endif /* CONFIG_EDAC_ALTERA_SDRAM */ 1137 1138 /*********************** OCRAM EDAC Device Functions *********************/ 1139 1140 #ifdef CONFIG_EDAC_ALTERA_OCRAM 1141 1142 static void *ocram_alloc_mem(size_t size, void **other) 1143 { 1144 struct device_node *np; 1145 struct gen_pool *gp; 1146 void *sram_addr; 1147 1148 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); 1149 if (!np) 1150 return NULL; 1151 1152 gp = of_gen_pool_get(np, "iram", 0); 1153 of_node_put(np); 1154 if (!gp) 1155 return NULL; 1156 1157 sram_addr = (void *)gen_pool_alloc(gp, size); 1158 if (!sram_addr) 1159 return NULL; 1160 1161 memset(sram_addr, 0, size); 1162 /* Ensure data is written out */ 1163 wmb(); 1164 1165 /* Remember this handle for freeing later */ 1166 *other = gp; 1167 1168 return sram_addr; 1169 } 1170 1171 static void ocram_free_mem(void *p, size_t size, void *other) 1172 { 1173 gen_pool_free((struct gen_pool *)other, (unsigned long)p, size); 1174 } 1175 1176 static const struct edac_device_prv_data ocramecc_data = { 1177 .setup = altr_check_ecc_deps, 1178 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR), 1179 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR), 1180 .alloc_mem = ocram_alloc_mem, 1181 .free_mem = ocram_free_mem, 1182 .ecc_enable_mask = ALTR_OCR_ECC_EN, 1183 .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET, 1184 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS), 1185 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD), 1186 .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET, 1187 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE, 1188 .inject_fops = &altr_edac_device_inject_fops, 1189 }; 1190 1191 static int __maybe_unused 1192 altr_check_ocram_deps_init(struct altr_edac_device_dev *device) 1193 { 1194 void __iomem *base = device->base; 1195 int ret; 1196 1197 ret = altr_check_ecc_deps(device); 1198 if (ret) 1199 return ret; 1200 1201 /* Verify OCRAM has been initialized */ 1202 if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA, 1203 (base + ALTR_A10_ECC_INITSTAT_OFST))) 1204 return -ENODEV; 1205 1206 /* Enable IRQ on Single Bit Error */ 1207 writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST)); 1208 /* Ensure all writes complete */ 1209 wmb(); 1210 1211 return 0; 1212 } 1213 1214 static const struct edac_device_prv_data a10_ocramecc_data = { 1215 .setup = altr_check_ocram_deps_init, 1216 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1217 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1218 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM, 1219 .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL, 1220 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1221 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1222 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1223 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1224 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1225 .inject_fops = &altr_edac_a10_device_inject2_fops, 1226 /* 1227 * OCRAM panic on uncorrectable error because sleep/resume 1228 * functions and FPGA contents are stored in OCRAM. Prefer 1229 * a kernel panic over executing/loading corrupted data. 1230 */ 1231 .panic = true, 1232 }; 1233 1234 #endif /* CONFIG_EDAC_ALTERA_OCRAM */ 1235 1236 /********************* L2 Cache EDAC Device Functions ********************/ 1237 1238 #ifdef CONFIG_EDAC_ALTERA_L2C 1239 1240 static void *l2_alloc_mem(size_t size, void **other) 1241 { 1242 struct device *dev = *other; 1243 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL); 1244 1245 if (!ptemp) 1246 return NULL; 1247 1248 /* Make sure everything is written out */ 1249 wmb(); 1250 1251 /* 1252 * Clean all cache levels up to LoC (includes L2) 1253 * This ensures the corrupted data is written into 1254 * L2 cache for readback test (which causes ECC error). 1255 */ 1256 flush_cache_all(); 1257 1258 return ptemp; 1259 } 1260 1261 static void l2_free_mem(void *p, size_t size, void *other) 1262 { 1263 struct device *dev = other; 1264 1265 if (dev && p) 1266 devm_kfree(dev, p); 1267 } 1268 1269 /* 1270 * altr_l2_check_deps() 1271 * Test for L2 cache ECC dependencies upon entry because 1272 * platform specific startup should have initialized the L2 1273 * memory and enabled the ECC. 1274 * Bail if ECC is not enabled. 1275 * Note that L2 Cache Enable is forced at build time. 1276 */ 1277 static int altr_l2_check_deps(struct altr_edac_device_dev *device) 1278 { 1279 void __iomem *base = device->base; 1280 const struct edac_device_prv_data *prv = device->data; 1281 1282 if ((readl(base) & prv->ecc_enable_mask) == 1283 prv->ecc_enable_mask) 1284 return 0; 1285 1286 edac_printk(KERN_ERR, EDAC_DEVICE, 1287 "L2: No ECC present, or ECC disabled\n"); 1288 return -ENODEV; 1289 } 1290 1291 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id) 1292 { 1293 struct altr_edac_device_dev *dci = dev_id; 1294 1295 if (irq == dci->sb_irq) { 1296 regmap_write(dci->edac->ecc_mgr_map, 1297 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, 1298 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB); 1299 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); 1300 1301 return IRQ_HANDLED; 1302 } else if (irq == dci->db_irq) { 1303 regmap_write(dci->edac->ecc_mgr_map, 1304 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, 1305 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB); 1306 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); 1307 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); 1308 1309 return IRQ_HANDLED; 1310 } 1311 1312 WARN_ON(1); 1313 1314 return IRQ_NONE; 1315 } 1316 1317 static const struct edac_device_prv_data l2ecc_data = { 1318 .setup = altr_l2_check_deps, 1319 .ce_clear_mask = 0, 1320 .ue_clear_mask = 0, 1321 .alloc_mem = l2_alloc_mem, 1322 .free_mem = l2_free_mem, 1323 .ecc_enable_mask = ALTR_L2_ECC_EN, 1324 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS), 1325 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD), 1326 .set_err_ofst = ALTR_L2_ECC_REG_OFFSET, 1327 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, 1328 .inject_fops = &altr_edac_device_inject_fops, 1329 }; 1330 1331 static const struct edac_device_prv_data a10_l2ecc_data = { 1332 .setup = altr_l2_check_deps, 1333 .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR, 1334 .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR, 1335 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2, 1336 .alloc_mem = l2_alloc_mem, 1337 .free_mem = l2_free_mem, 1338 .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL, 1339 .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK, 1340 .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK, 1341 .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST, 1342 .ecc_irq_handler = altr_edac_a10_l2_irq, 1343 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, 1344 .inject_fops = &altr_edac_device_inject_fops, 1345 }; 1346 1347 #endif /* CONFIG_EDAC_ALTERA_L2C */ 1348 1349 /********************* Ethernet Device Functions ********************/ 1350 1351 #ifdef CONFIG_EDAC_ALTERA_ETHERNET 1352 1353 static int __init socfpga_init_ethernet_ecc(struct altr_edac_device_dev *dev) 1354 { 1355 int ret; 1356 1357 ret = altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc"); 1358 if (ret) 1359 return ret; 1360 1361 return altr_check_ecc_deps(dev); 1362 } 1363 1364 static const struct edac_device_prv_data a10_enetecc_data = { 1365 .setup = socfpga_init_ethernet_ecc, 1366 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1367 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1368 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1369 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1370 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1371 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1372 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1373 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1374 .inject_fops = &altr_edac_a10_device_inject2_fops, 1375 }; 1376 1377 #endif /* CONFIG_EDAC_ALTERA_ETHERNET */ 1378 1379 /********************** NAND Device Functions **********************/ 1380 1381 #ifdef CONFIG_EDAC_ALTERA_NAND 1382 1383 static int __init socfpga_init_nand_ecc(struct altr_edac_device_dev *device) 1384 { 1385 int ret; 1386 1387 ret = altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc"); 1388 if (ret) 1389 return ret; 1390 1391 return altr_check_ecc_deps(device); 1392 } 1393 1394 static const struct edac_device_prv_data a10_nandecc_data = { 1395 .setup = socfpga_init_nand_ecc, 1396 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1397 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1398 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1399 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1400 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1401 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1402 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1403 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1404 .inject_fops = &altr_edac_a10_device_inject_fops, 1405 }; 1406 1407 #endif /* CONFIG_EDAC_ALTERA_NAND */ 1408 1409 /********************** DMA Device Functions **********************/ 1410 1411 #ifdef CONFIG_EDAC_ALTERA_DMA 1412 1413 static int __init socfpga_init_dma_ecc(struct altr_edac_device_dev *device) 1414 { 1415 int ret; 1416 1417 ret = altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc"); 1418 if (ret) 1419 return ret; 1420 1421 return altr_check_ecc_deps(device); 1422 } 1423 1424 static const struct edac_device_prv_data a10_dmaecc_data = { 1425 .setup = socfpga_init_dma_ecc, 1426 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1427 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1428 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1429 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1430 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1431 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1432 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1433 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1434 .inject_fops = &altr_edac_a10_device_inject_fops, 1435 }; 1436 1437 #endif /* CONFIG_EDAC_ALTERA_DMA */ 1438 1439 /********************** USB Device Functions **********************/ 1440 1441 #ifdef CONFIG_EDAC_ALTERA_USB 1442 1443 static int __init socfpga_init_usb_ecc(struct altr_edac_device_dev *device) 1444 { 1445 int ret; 1446 1447 ret = altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc"); 1448 if (ret) 1449 return ret; 1450 1451 return altr_check_ecc_deps(device); 1452 } 1453 1454 static const struct edac_device_prv_data a10_usbecc_data = { 1455 .setup = socfpga_init_usb_ecc, 1456 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1457 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1458 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1459 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1460 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1461 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1462 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1463 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1464 .inject_fops = &altr_edac_a10_device_inject2_fops, 1465 }; 1466 1467 #endif /* CONFIG_EDAC_ALTERA_USB */ 1468 1469 /********************** QSPI Device Functions **********************/ 1470 1471 #ifdef CONFIG_EDAC_ALTERA_QSPI 1472 1473 static int __init socfpga_init_qspi_ecc(struct altr_edac_device_dev *device) 1474 { 1475 int ret; 1476 1477 ret = altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc"); 1478 if (ret) 1479 return ret; 1480 1481 return altr_check_ecc_deps(device); 1482 } 1483 1484 static const struct edac_device_prv_data a10_qspiecc_data = { 1485 .setup = socfpga_init_qspi_ecc, 1486 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1487 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1488 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1489 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1490 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1491 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1492 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1493 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1494 .inject_fops = &altr_edac_a10_device_inject_fops, 1495 }; 1496 1497 #endif /* CONFIG_EDAC_ALTERA_QSPI */ 1498 1499 /********************* SDMMC Device Functions **********************/ 1500 1501 #ifdef CONFIG_EDAC_ALTERA_SDMMC 1502 1503 static const struct edac_device_prv_data a10_sdmmceccb_data; 1504 static int altr_portb_setup(struct altr_edac_device_dev *device) 1505 { 1506 struct edac_device_ctl_info *dci; 1507 struct altr_edac_device_dev *altdev; 1508 char *ecc_name = "sdmmcb-ecc"; 1509 int edac_idx, rc; 1510 struct device_node *np; 1511 const struct edac_device_prv_data *prv = &a10_sdmmceccb_data; 1512 1513 rc = altr_check_ecc_deps(device); 1514 if (rc) 1515 return rc; 1516 1517 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc"); 1518 if (!np) { 1519 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n"); 1520 return -ENODEV; 1521 } 1522 1523 /* Create the PortB EDAC device */ 1524 edac_idx = edac_device_alloc_index(); 1525 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1, 1526 ecc_name, 1, 0, NULL, 0, edac_idx); 1527 if (!dci) { 1528 edac_printk(KERN_ERR, EDAC_DEVICE, 1529 "%s: Unable to allocate PortB EDAC device\n", 1530 ecc_name); 1531 return -ENOMEM; 1532 } 1533 1534 /* Initialize the PortB EDAC device structure from PortA structure */ 1535 altdev = dci->pvt_info; 1536 *altdev = *device; 1537 1538 if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL)) 1539 return -ENOMEM; 1540 1541 /* Update PortB specific values */ 1542 altdev->edac_dev_name = ecc_name; 1543 altdev->edac_idx = edac_idx; 1544 altdev->edac_dev = dci; 1545 altdev->data = prv; 1546 dci->dev = &altdev->ddev; 1547 dci->ctl_name = "Altera ECC Manager"; 1548 dci->mod_name = ecc_name; 1549 dci->dev_name = ecc_name; 1550 1551 /* 1552 * Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly 1553 * 1554 * FIXME: Instead of ifdefs with different architectures the driver 1555 * should properly use compatibles. 1556 */ 1557 #ifdef CONFIG_64BIT 1558 altdev->sb_irq = irq_of_parse_and_map(np, 1); 1559 #else 1560 altdev->sb_irq = irq_of_parse_and_map(np, 2); 1561 #endif 1562 if (!altdev->sb_irq) { 1563 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n"); 1564 rc = -ENODEV; 1565 goto err_release_group_1; 1566 } 1567 rc = devm_request_irq(&altdev->ddev, altdev->sb_irq, 1568 prv->ecc_irq_handler, 1569 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 1570 ecc_name, altdev); 1571 if (rc) { 1572 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n"); 1573 goto err_release_group_1; 1574 } 1575 1576 #ifdef CONFIG_64BIT 1577 /* Use IRQ to determine SError origin instead of assigning IRQ */ 1578 rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq); 1579 if (rc) { 1580 edac_printk(KERN_ERR, EDAC_DEVICE, 1581 "Error PortB DBIRQ alloc\n"); 1582 goto err_release_group_1; 1583 } 1584 #else 1585 altdev->db_irq = irq_of_parse_and_map(np, 3); 1586 if (!altdev->db_irq) { 1587 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n"); 1588 rc = -ENODEV; 1589 goto err_release_group_1; 1590 } 1591 rc = devm_request_irq(&altdev->ddev, altdev->db_irq, 1592 prv->ecc_irq_handler, 1593 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 1594 ecc_name, altdev); 1595 if (rc) { 1596 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n"); 1597 goto err_release_group_1; 1598 } 1599 #endif 1600 1601 rc = edac_device_add_device(dci); 1602 if (rc) { 1603 edac_printk(KERN_ERR, EDAC_DEVICE, 1604 "edac_device_add_device portB failed\n"); 1605 rc = -ENOMEM; 1606 goto err_release_group_1; 1607 } 1608 altr_create_edacdev_dbgfs(dci, prv); 1609 1610 list_add(&altdev->next, &altdev->edac->a10_ecc_devices); 1611 1612 devres_remove_group(&altdev->ddev, altr_portb_setup); 1613 1614 return 0; 1615 1616 err_release_group_1: 1617 edac_device_free_ctl_info(dci); 1618 devres_release_group(&altdev->ddev, altr_portb_setup); 1619 edac_printk(KERN_ERR, EDAC_DEVICE, 1620 "%s:Error setting up EDAC device: %d\n", ecc_name, rc); 1621 return rc; 1622 } 1623 1624 static int __init socfpga_init_sdmmc_ecc(struct altr_edac_device_dev *device) 1625 { 1626 int rc = -ENODEV; 1627 struct device_node *child; 1628 1629 child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc"); 1630 if (!child) 1631 return -ENODEV; 1632 1633 if (!of_device_is_available(child)) 1634 goto exit; 1635 1636 if (validate_parent_available(child)) 1637 goto exit; 1638 1639 /* Init portB */ 1640 rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK, 1641 a10_sdmmceccb_data.ecc_enable_mask, 1); 1642 if (rc) 1643 goto exit; 1644 1645 /* Setup portB */ 1646 return altr_portb_setup(device); 1647 1648 exit: 1649 of_node_put(child); 1650 return rc; 1651 } 1652 1653 static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id) 1654 { 1655 struct altr_edac_device_dev *ad = dev_id; 1656 void __iomem *base = ad->base; 1657 const struct edac_device_prv_data *priv = ad->data; 1658 1659 if (irq == ad->sb_irq) { 1660 writel(priv->ce_clear_mask, 1661 base + ALTR_A10_ECC_INTSTAT_OFST); 1662 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name); 1663 return IRQ_HANDLED; 1664 } else if (irq == ad->db_irq) { 1665 writel(priv->ue_clear_mask, 1666 base + ALTR_A10_ECC_INTSTAT_OFST); 1667 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name); 1668 return IRQ_HANDLED; 1669 } 1670 1671 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq); 1672 1673 return IRQ_NONE; 1674 } 1675 1676 static const struct edac_device_prv_data a10_sdmmcecca_data = { 1677 .setup = socfpga_init_sdmmc_ecc, 1678 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1679 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1680 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1681 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1682 .ce_set_mask = ALTR_A10_ECC_SERRPENA, 1683 .ue_set_mask = ALTR_A10_ECC_DERRPENA, 1684 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1685 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1686 .inject_fops = &altr_edac_a10_device_inject_fops, 1687 }; 1688 1689 static const struct edac_device_prv_data a10_sdmmceccb_data = { 1690 .setup = socfpga_init_sdmmc_ecc, 1691 .ce_clear_mask = ALTR_A10_ECC_SERRPENB, 1692 .ue_clear_mask = ALTR_A10_ECC_DERRPENB, 1693 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1694 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1695 .ce_set_mask = ALTR_A10_ECC_TSERRB, 1696 .ue_set_mask = ALTR_A10_ECC_TDERRB, 1697 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1698 .ecc_irq_handler = altr_edac_a10_ecc_irq_portb, 1699 .inject_fops = &altr_edac_a10_device_inject_fops, 1700 }; 1701 1702 #endif /* CONFIG_EDAC_ALTERA_SDMMC */ 1703 1704 /********************* Arria10 EDAC Device Functions *************************/ 1705 static const struct of_device_id altr_edac_a10_device_of_match[] = { 1706 #ifdef CONFIG_EDAC_ALTERA_L2C 1707 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data }, 1708 #endif 1709 #ifdef CONFIG_EDAC_ALTERA_OCRAM 1710 { .compatible = "altr,socfpga-a10-ocram-ecc", 1711 .data = &a10_ocramecc_data }, 1712 #endif 1713 #ifdef CONFIG_EDAC_ALTERA_ETHERNET 1714 { .compatible = "altr,socfpga-eth-mac-ecc", 1715 .data = &a10_enetecc_data }, 1716 #endif 1717 #ifdef CONFIG_EDAC_ALTERA_NAND 1718 { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data }, 1719 #endif 1720 #ifdef CONFIG_EDAC_ALTERA_DMA 1721 { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data }, 1722 #endif 1723 #ifdef CONFIG_EDAC_ALTERA_USB 1724 { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data }, 1725 #endif 1726 #ifdef CONFIG_EDAC_ALTERA_QSPI 1727 { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data }, 1728 #endif 1729 #ifdef CONFIG_EDAC_ALTERA_SDMMC 1730 { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data }, 1731 #endif 1732 #ifdef CONFIG_EDAC_ALTERA_SDRAM 1733 { .compatible = "altr,sdram-edac-s10", .data = &s10_sdramecc_data }, 1734 #endif 1735 {}, 1736 }; 1737 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match); 1738 1739 /* 1740 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5 1741 * because 2 IRQs are shared among the all ECC peripherals. The ECC 1742 * manager manages the IRQs and the children. 1743 * Based on xgene_edac.c peripheral code. 1744 */ 1745 1746 static ssize_t __maybe_unused 1747 altr_edac_a10_device_trig(struct file *file, const char __user *user_buf, 1748 size_t count, loff_t *ppos) 1749 { 1750 struct edac_device_ctl_info *edac_dci = file->private_data; 1751 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 1752 const struct edac_device_prv_data *priv = drvdata->data; 1753 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst); 1754 unsigned long flags; 1755 u8 trig_type; 1756 1757 if (!user_buf || get_user(trig_type, user_buf)) 1758 return -EFAULT; 1759 1760 local_irq_save(flags); 1761 if (trig_type == ALTR_UE_TRIGGER_CHAR) 1762 writel(priv->ue_set_mask, set_addr); 1763 else 1764 writel(priv->ce_set_mask, set_addr); 1765 1766 /* Ensure the interrupt test bits are set */ 1767 wmb(); 1768 local_irq_restore(flags); 1769 1770 return count; 1771 } 1772 1773 /* 1774 * The Stratix10 EDAC Error Injection Functions differ from Arria10 1775 * slightly. A few Arria10 peripherals can use this injection function. 1776 * Inject the error into the memory and then readback to trigger the IRQ. 1777 */ 1778 static ssize_t __maybe_unused 1779 altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf, 1780 size_t count, loff_t *ppos) 1781 { 1782 struct edac_device_ctl_info *edac_dci = file->private_data; 1783 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 1784 const struct edac_device_prv_data *priv = drvdata->data; 1785 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst); 1786 unsigned long flags; 1787 u8 trig_type; 1788 1789 if (!user_buf || get_user(trig_type, user_buf)) 1790 return -EFAULT; 1791 1792 local_irq_save(flags); 1793 if (trig_type == ALTR_UE_TRIGGER_CHAR) { 1794 writel(priv->ue_set_mask, set_addr); 1795 } else { 1796 /* Setup read/write of 4 bytes */ 1797 writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST); 1798 /* Setup Address to 0 */ 1799 writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST); 1800 /* Setup accctrl to read & ecc & data override */ 1801 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST); 1802 /* Kick it. */ 1803 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST); 1804 /* Setup write for single bit change */ 1805 writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1, 1806 drvdata->base + ECC_BLK_WDATA0_OFST); 1807 writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST), 1808 drvdata->base + ECC_BLK_WDATA1_OFST); 1809 writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST), 1810 drvdata->base + ECC_BLK_WDATA2_OFST); 1811 writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST), 1812 drvdata->base + ECC_BLK_WDATA3_OFST); 1813 1814 /* Copy Read ECC to Write ECC */ 1815 writel(readl(drvdata->base + ECC_BLK_RECC0_OFST), 1816 drvdata->base + ECC_BLK_WECC0_OFST); 1817 writel(readl(drvdata->base + ECC_BLK_RECC1_OFST), 1818 drvdata->base + ECC_BLK_WECC1_OFST); 1819 /* Setup accctrl to write & ecc override & data override */ 1820 writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST); 1821 /* Kick it. */ 1822 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST); 1823 /* Setup accctrl to read & ecc overwrite & data overwrite */ 1824 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST); 1825 /* Kick it. */ 1826 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST); 1827 } 1828 1829 /* Ensure the interrupt test bits are set */ 1830 wmb(); 1831 local_irq_restore(flags); 1832 1833 return count; 1834 } 1835 1836 static void altr_edac_a10_irq_handler(struct irq_desc *desc) 1837 { 1838 int dberr, bit, sm_offset, irq_status; 1839 struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc); 1840 struct irq_chip *chip = irq_desc_get_chip(desc); 1841 int irq = irq_desc_get_irq(desc); 1842 unsigned long bits; 1843 1844 dberr = (irq == edac->db_irq) ? 1 : 0; 1845 sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST : 1846 A10_SYSMGR_ECC_INTSTAT_SERR_OFST; 1847 1848 chained_irq_enter(chip, desc); 1849 1850 regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status); 1851 1852 bits = irq_status; 1853 for_each_set_bit(bit, &bits, 32) 1854 generic_handle_domain_irq(edac->domain, dberr * 32 + bit); 1855 1856 chained_irq_exit(chip, desc); 1857 } 1858 1859 static int validate_parent_available(struct device_node *np) 1860 { 1861 struct device_node *parent; 1862 int ret = 0; 1863 1864 /* SDRAM must be present for Linux (implied parent) */ 1865 if (of_device_is_compatible(np, "altr,sdram-edac-s10")) 1866 return 0; 1867 1868 /* Ensure parent device is enabled if parent node exists */ 1869 parent = of_parse_phandle(np, "altr,ecc-parent", 0); 1870 if (parent && !of_device_is_available(parent)) 1871 ret = -ENODEV; 1872 1873 of_node_put(parent); 1874 return ret; 1875 } 1876 1877 static int get_s10_sdram_edac_resource(struct device_node *np, 1878 struct resource *res) 1879 { 1880 struct device_node *parent; 1881 int ret; 1882 1883 parent = of_parse_phandle(np, "altr,sdr-syscon", 0); 1884 if (!parent) 1885 return -ENODEV; 1886 1887 ret = of_address_to_resource(parent, 0, res); 1888 of_node_put(parent); 1889 1890 return ret; 1891 } 1892 1893 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac, 1894 struct device_node *np) 1895 { 1896 struct edac_device_ctl_info *dci; 1897 struct altr_edac_device_dev *altdev; 1898 char *ecc_name = (char *)np->name; 1899 struct resource res; 1900 int edac_idx; 1901 int rc = 0; 1902 const struct edac_device_prv_data *prv; 1903 /* Get matching node and check for valid result */ 1904 const struct of_device_id *pdev_id = 1905 of_match_node(altr_edac_a10_device_of_match, np); 1906 if (IS_ERR_OR_NULL(pdev_id)) 1907 return -ENODEV; 1908 1909 /* Get driver specific data for this EDAC device */ 1910 prv = pdev_id->data; 1911 if (IS_ERR_OR_NULL(prv)) 1912 return -ENODEV; 1913 1914 if (validate_parent_available(np)) 1915 return -ENODEV; 1916 1917 if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL)) 1918 return -ENOMEM; 1919 1920 if (of_device_is_compatible(np, "altr,sdram-edac-s10")) 1921 rc = get_s10_sdram_edac_resource(np, &res); 1922 else 1923 rc = of_address_to_resource(np, 0, &res); 1924 1925 if (rc < 0) { 1926 edac_printk(KERN_ERR, EDAC_DEVICE, 1927 "%s: no resource address\n", ecc_name); 1928 goto err_release_group; 1929 } 1930 1931 edac_idx = edac_device_alloc_index(); 1932 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1933 1, ecc_name, 1, 0, NULL, 0, 1934 edac_idx); 1935 1936 if (!dci) { 1937 edac_printk(KERN_ERR, EDAC_DEVICE, 1938 "%s: Unable to allocate EDAC device\n", ecc_name); 1939 rc = -ENOMEM; 1940 goto err_release_group; 1941 } 1942 1943 altdev = dci->pvt_info; 1944 dci->dev = edac->dev; 1945 altdev->edac_dev_name = ecc_name; 1946 altdev->edac_idx = edac_idx; 1947 altdev->edac = edac; 1948 altdev->edac_dev = dci; 1949 altdev->data = prv; 1950 altdev->ddev = *edac->dev; 1951 dci->dev = &altdev->ddev; 1952 dci->ctl_name = "Altera ECC Manager"; 1953 dci->mod_name = ecc_name; 1954 dci->dev_name = ecc_name; 1955 1956 altdev->base = devm_ioremap_resource(edac->dev, &res); 1957 if (IS_ERR(altdev->base)) { 1958 rc = PTR_ERR(altdev->base); 1959 goto err_release_group1; 1960 } 1961 1962 /* Check specific dependencies for the module */ 1963 if (altdev->data->setup) { 1964 rc = altdev->data->setup(altdev); 1965 if (rc) 1966 goto err_release_group1; 1967 } 1968 1969 altdev->sb_irq = irq_of_parse_and_map(np, 0); 1970 if (!altdev->sb_irq) { 1971 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n"); 1972 rc = -ENODEV; 1973 goto err_release_group1; 1974 } 1975 rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler, 1976 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 1977 ecc_name, altdev); 1978 if (rc) { 1979 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n"); 1980 goto err_release_group1; 1981 } 1982 1983 #ifdef CONFIG_64BIT 1984 /* Use IRQ to determine SError origin instead of assigning IRQ */ 1985 rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq); 1986 if (rc) { 1987 edac_printk(KERN_ERR, EDAC_DEVICE, 1988 "Unable to parse DB IRQ index\n"); 1989 goto err_release_group1; 1990 } 1991 #else 1992 altdev->db_irq = irq_of_parse_and_map(np, 1); 1993 if (!altdev->db_irq) { 1994 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n"); 1995 rc = -ENODEV; 1996 goto err_release_group1; 1997 } 1998 rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler, 1999 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 2000 ecc_name, altdev); 2001 if (rc) { 2002 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n"); 2003 goto err_release_group1; 2004 } 2005 #endif 2006 2007 rc = edac_device_add_device(dci); 2008 if (rc) { 2009 dev_err(edac->dev, "edac_device_add_device failed\n"); 2010 rc = -ENOMEM; 2011 goto err_release_group1; 2012 } 2013 2014 altr_create_edacdev_dbgfs(dci, prv); 2015 2016 list_add(&altdev->next, &edac->a10_ecc_devices); 2017 2018 devres_remove_group(edac->dev, altr_edac_a10_device_add); 2019 2020 return 0; 2021 2022 err_release_group1: 2023 edac_device_free_ctl_info(dci); 2024 err_release_group: 2025 devres_release_group(edac->dev, NULL); 2026 edac_printk(KERN_ERR, EDAC_DEVICE, 2027 "%s:Error setting up EDAC device: %d\n", ecc_name, rc); 2028 2029 return rc; 2030 } 2031 2032 static void a10_eccmgr_irq_mask(struct irq_data *d) 2033 { 2034 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); 2035 2036 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, 2037 BIT(d->hwirq)); 2038 } 2039 2040 static void a10_eccmgr_irq_unmask(struct irq_data *d) 2041 { 2042 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); 2043 2044 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, 2045 BIT(d->hwirq)); 2046 } 2047 2048 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq, 2049 irq_hw_number_t hwirq) 2050 { 2051 struct altr_arria10_edac *edac = d->host_data; 2052 2053 irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq); 2054 irq_set_chip_data(irq, edac); 2055 irq_set_noprobe(irq); 2056 2057 return 0; 2058 } 2059 2060 static const struct irq_domain_ops a10_eccmgr_ic_ops = { 2061 .map = a10_eccmgr_irqdomain_map, 2062 .xlate = irq_domain_xlate_twocell, 2063 }; 2064 2065 /************** Stratix 10 EDAC Double Bit Error Handler ************/ 2066 #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m) 2067 2068 #ifdef CONFIG_64BIT 2069 /* panic routine issues reboot on non-zero panic_timeout */ 2070 extern int panic_timeout; 2071 2072 /* 2073 * The double bit error is handled through SError which is fatal. This is 2074 * called as a panic notifier to printout ECC error info as part of the panic. 2075 */ 2076 static int s10_edac_dberr_handler(struct notifier_block *this, 2077 unsigned long event, void *ptr) 2078 { 2079 struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier); 2080 int err_addr, dberror; 2081 2082 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST, 2083 &dberror); 2084 regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror); 2085 if (dberror & S10_DBE_IRQ_MASK) { 2086 struct list_head *position; 2087 struct altr_edac_device_dev *ed; 2088 struct arm_smccc_res result; 2089 2090 /* Find the matching DBE in the list of devices */ 2091 list_for_each(position, &edac->a10_ecc_devices) { 2092 ed = list_entry(position, struct altr_edac_device_dev, 2093 next); 2094 if (!(BIT(ed->db_irq) & dberror)) 2095 continue; 2096 2097 writel(ALTR_A10_ECC_DERRPENA, 2098 ed->base + ALTR_A10_ECC_INTSTAT_OFST); 2099 err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST); 2100 regmap_write(edac->ecc_mgr_map, 2101 S10_SYSMGR_UE_ADDR_OFST, err_addr); 2102 edac_printk(KERN_ERR, EDAC_DEVICE, 2103 "EDAC: [Fatal DBE on %s @ 0x%08X]\n", 2104 ed->edac_dev_name, err_addr); 2105 break; 2106 } 2107 /* Notify the System through SMC. Reboot delay = 1 second */ 2108 panic_timeout = 1; 2109 arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0, 2110 0, 0, &result); 2111 } 2112 2113 return NOTIFY_DONE; 2114 } 2115 #endif 2116 2117 /****************** Arria 10 EDAC Probe Function *********************/ 2118 static int altr_edac_a10_probe(struct platform_device *pdev) 2119 { 2120 struct altr_arria10_edac *edac; 2121 struct device_node *child; 2122 2123 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL); 2124 if (!edac) 2125 return -ENOMEM; 2126 2127 edac->dev = &pdev->dev; 2128 platform_set_drvdata(pdev, edac); 2129 INIT_LIST_HEAD(&edac->a10_ecc_devices); 2130 2131 edac->ecc_mgr_map = 2132 altr_sysmgr_regmap_lookup_by_phandle(pdev->dev.of_node, 2133 "altr,sysmgr-syscon"); 2134 2135 if (IS_ERR(edac->ecc_mgr_map)) { 2136 edac_printk(KERN_ERR, EDAC_DEVICE, 2137 "Unable to get syscon altr,sysmgr-syscon\n"); 2138 return PTR_ERR(edac->ecc_mgr_map); 2139 } 2140 2141 edac->irq_chip.name = pdev->dev.of_node->name; 2142 edac->irq_chip.irq_mask = a10_eccmgr_irq_mask; 2143 edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask; 2144 edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64, 2145 &a10_eccmgr_ic_ops, edac); 2146 if (!edac->domain) { 2147 dev_err(&pdev->dev, "Error adding IRQ domain\n"); 2148 return -ENOMEM; 2149 } 2150 2151 edac->sb_irq = platform_get_irq(pdev, 0); 2152 if (edac->sb_irq < 0) 2153 return edac->sb_irq; 2154 2155 irq_set_chained_handler_and_data(edac->sb_irq, 2156 altr_edac_a10_irq_handler, 2157 edac); 2158 2159 #ifdef CONFIG_64BIT 2160 { 2161 int dberror, err_addr; 2162 2163 edac->panic_notifier.notifier_call = s10_edac_dberr_handler; 2164 atomic_notifier_chain_register(&panic_notifier_list, 2165 &edac->panic_notifier); 2166 2167 /* Printout a message if uncorrectable error previously. */ 2168 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, 2169 &dberror); 2170 if (dberror) { 2171 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST, 2172 &err_addr); 2173 edac_printk(KERN_ERR, EDAC_DEVICE, 2174 "Previous Boot UE detected[0x%X] @ 0x%X\n", 2175 dberror, err_addr); 2176 /* Reset the sticky registers */ 2177 regmap_write(edac->ecc_mgr_map, 2178 S10_SYSMGR_UE_VAL_OFST, 0); 2179 regmap_write(edac->ecc_mgr_map, 2180 S10_SYSMGR_UE_ADDR_OFST, 0); 2181 } 2182 } 2183 #else 2184 edac->db_irq = platform_get_irq(pdev, 1); 2185 if (edac->db_irq < 0) 2186 return edac->db_irq; 2187 2188 irq_set_chained_handler_and_data(edac->db_irq, 2189 altr_edac_a10_irq_handler, edac); 2190 #endif 2191 2192 for_each_child_of_node(pdev->dev.of_node, child) { 2193 if (!of_device_is_available(child)) 2194 continue; 2195 2196 if (of_match_node(altr_edac_a10_device_of_match, child)) 2197 altr_edac_a10_device_add(edac, child); 2198 2199 #ifdef CONFIG_EDAC_ALTERA_SDRAM 2200 else if (of_device_is_compatible(child, "altr,sdram-edac-a10")) 2201 of_platform_populate(pdev->dev.of_node, 2202 altr_sdram_ctrl_of_match, 2203 NULL, &pdev->dev); 2204 #endif 2205 } 2206 2207 return 0; 2208 } 2209 2210 static const struct of_device_id altr_edac_a10_of_match[] = { 2211 { .compatible = "altr,socfpga-a10-ecc-manager" }, 2212 { .compatible = "altr,socfpga-s10-ecc-manager" }, 2213 {}, 2214 }; 2215 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match); 2216 2217 static struct platform_driver altr_edac_a10_driver = { 2218 .probe = altr_edac_a10_probe, 2219 .driver = { 2220 .name = "socfpga_a10_ecc_manager", 2221 .of_match_table = altr_edac_a10_of_match, 2222 }, 2223 }; 2224 module_platform_driver(altr_edac_a10_driver); 2225 2226 MODULE_AUTHOR("Thor Thayer"); 2227 MODULE_DESCRIPTION("EDAC Driver for Altera Memories"); 2228