1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved 4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved. 5 * Copyright 2011-2012 Calxeda, Inc. 6 */ 7 8 #include <asm/cacheflush.h> 9 #include <linux/ctype.h> 10 #include <linux/delay.h> 11 #include <linux/edac.h> 12 #include <linux/firmware/intel/stratix10-smc.h> 13 #include <linux/genalloc.h> 14 #include <linux/interrupt.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/kernel.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/notifier.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/regmap.h> 24 #include <linux/types.h> 25 #include <linux/uaccess.h> 26 27 #include "altera_edac.h" 28 #include "edac_module.h" 29 30 #define EDAC_MOD_STR "altera_edac" 31 #define EDAC_DEVICE "Altera" 32 33 #ifdef CONFIG_EDAC_ALTERA_SDRAM 34 static const struct altr_sdram_prv_data c5_data = { 35 .ecc_ctrl_offset = CV_CTLCFG_OFST, 36 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN, 37 .ecc_stat_offset = CV_DRAMSTS_OFST, 38 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR, 39 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR, 40 .ecc_saddr_offset = CV_ERRADDR_OFST, 41 .ecc_daddr_offset = CV_ERRADDR_OFST, 42 .ecc_cecnt_offset = CV_SBECOUNT_OFST, 43 .ecc_uecnt_offset = CV_DBECOUNT_OFST, 44 .ecc_irq_en_offset = CV_DRAMINTR_OFST, 45 .ecc_irq_en_mask = CV_DRAMINTR_INTREN, 46 .ecc_irq_clr_offset = CV_DRAMINTR_OFST, 47 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN), 48 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST, 49 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR, 50 .ce_ue_trgr_offset = CV_CTLCFG_OFST, 51 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR, 52 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR, 53 }; 54 55 static const struct altr_sdram_prv_data a10_data = { 56 .ecc_ctrl_offset = A10_ECCCTRL1_OFST, 57 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN, 58 .ecc_stat_offset = A10_INTSTAT_OFST, 59 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR, 60 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR, 61 .ecc_saddr_offset = A10_SERRADDR_OFST, 62 .ecc_daddr_offset = A10_DERRADDR_OFST, 63 .ecc_irq_en_offset = A10_ERRINTEN_OFST, 64 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK, 65 .ecc_irq_clr_offset = A10_INTSTAT_OFST, 66 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR), 67 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST, 68 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK, 69 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST, 70 .ce_set_mask = A10_DIAGINT_TSERRA_MASK, 71 .ue_set_mask = A10_DIAGINT_TDERRA_MASK, 72 }; 73 74 /*********************** EDAC Memory Controller Functions ****************/ 75 76 /* The SDRAM controller uses the EDAC Memory Controller framework. */ 77 78 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id) 79 { 80 struct mem_ctl_info *mci = dev_id; 81 struct altr_sdram_mc_data *drvdata = mci->pvt_info; 82 const struct altr_sdram_prv_data *priv = drvdata->data; 83 u32 status, err_count = 1, err_addr; 84 85 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status); 86 87 if (status & priv->ecc_stat_ue_mask) { 88 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset, 89 &err_addr); 90 if (priv->ecc_uecnt_offset) 91 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset, 92 &err_count); 93 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n", 94 err_count, err_addr); 95 } 96 if (status & priv->ecc_stat_ce_mask) { 97 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, 98 &err_addr); 99 if (priv->ecc_uecnt_offset) 100 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset, 101 &err_count); 102 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count, 103 err_addr >> PAGE_SHIFT, 104 err_addr & ~PAGE_MASK, 0, 105 0, 0, -1, mci->ctl_name, ""); 106 /* Clear IRQ to resume */ 107 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset, 108 priv->ecc_irq_clr_mask); 109 110 return IRQ_HANDLED; 111 } 112 return IRQ_NONE; 113 } 114 115 static ssize_t altr_sdr_mc_err_inject_write(struct file *file, 116 const char __user *data, 117 size_t count, loff_t *ppos) 118 { 119 struct mem_ctl_info *mci = file->private_data; 120 struct altr_sdram_mc_data *drvdata = mci->pvt_info; 121 const struct altr_sdram_prv_data *priv = drvdata->data; 122 u32 *ptemp; 123 dma_addr_t dma_handle; 124 u32 reg, read_reg; 125 126 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL); 127 if (!ptemp) { 128 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); 129 edac_printk(KERN_ERR, EDAC_MC, 130 "Inject: Buffer Allocation error\n"); 131 return -ENOMEM; 132 } 133 134 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset, 135 &read_reg); 136 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask); 137 138 /* Error are injected by writing a word while the SBE or DBE 139 * bit in the CTLCFG register is set. Reading the word will 140 * trigger the SBE or DBE error and the corresponding IRQ. 141 */ 142 if (count == 3) { 143 edac_printk(KERN_ALERT, EDAC_MC, 144 "Inject Double bit error\n"); 145 local_irq_disable(); 146 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, 147 (read_reg | priv->ue_set_mask)); 148 local_irq_enable(); 149 } else { 150 edac_printk(KERN_ALERT, EDAC_MC, 151 "Inject Single bit error\n"); 152 local_irq_disable(); 153 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, 154 (read_reg | priv->ce_set_mask)); 155 local_irq_enable(); 156 } 157 158 ptemp[0] = 0x5A5A5A5A; 159 ptemp[1] = 0xA5A5A5A5; 160 161 /* Clear the error injection bits */ 162 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg); 163 /* Ensure it has been written out */ 164 wmb(); 165 166 /* 167 * To trigger the error, we need to read the data back 168 * (the data was written with errors above). 169 * The READ_ONCE macros and printk are used to prevent the 170 * the compiler optimizing these reads out. 171 */ 172 reg = READ_ONCE(ptemp[0]); 173 read_reg = READ_ONCE(ptemp[1]); 174 /* Force Read */ 175 rmb(); 176 177 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n", 178 reg, read_reg); 179 180 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); 181 182 return count; 183 } 184 185 static const struct file_operations altr_sdr_mc_debug_inject_fops = { 186 .open = simple_open, 187 .write = altr_sdr_mc_err_inject_write, 188 .llseek = generic_file_llseek, 189 }; 190 191 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci) 192 { 193 if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) 194 return; 195 196 if (!mci->debugfs) 197 return; 198 199 edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci, 200 &altr_sdr_mc_debug_inject_fops); 201 } 202 203 /* Get total memory size from Open Firmware DTB */ 204 static unsigned long get_total_mem(void) 205 { 206 struct device_node *np = NULL; 207 struct resource res; 208 int ret; 209 unsigned long total_mem = 0; 210 211 for_each_node_by_type(np, "memory") { 212 ret = of_address_to_resource(np, 0, &res); 213 if (ret) 214 continue; 215 216 total_mem += resource_size(&res); 217 } 218 edac_dbg(0, "total_mem 0x%lx\n", total_mem); 219 return total_mem; 220 } 221 222 static const struct of_device_id altr_sdram_ctrl_of_match[] = { 223 { .compatible = "altr,sdram-edac", .data = &c5_data}, 224 { .compatible = "altr,sdram-edac-a10", .data = &a10_data}, 225 { .compatible = "altr,sdram-edac-s10", .data = &a10_data}, 226 {}, 227 }; 228 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match); 229 230 static int a10_init(struct regmap *mc_vbase) 231 { 232 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST, 233 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) { 234 edac_printk(KERN_ERR, EDAC_MC, 235 "Error setting SB IRQ mode\n"); 236 return -ENODEV; 237 } 238 239 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) { 240 edac_printk(KERN_ERR, EDAC_MC, 241 "Error setting trigger count\n"); 242 return -ENODEV; 243 } 244 245 return 0; 246 } 247 248 static int a10_unmask_irq(struct platform_device *pdev, u32 mask) 249 { 250 void __iomem *sm_base; 251 int ret = 0; 252 253 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32), 254 dev_name(&pdev->dev))) { 255 edac_printk(KERN_ERR, EDAC_MC, 256 "Unable to request mem region\n"); 257 return -EBUSY; 258 } 259 260 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32)); 261 if (!sm_base) { 262 edac_printk(KERN_ERR, EDAC_MC, 263 "Unable to ioremap device\n"); 264 265 ret = -ENOMEM; 266 goto release; 267 } 268 269 iowrite32(mask, sm_base); 270 271 iounmap(sm_base); 272 273 release: 274 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32)); 275 276 return ret; 277 } 278 279 static int socfpga_is_a10(void); 280 static int altr_sdram_probe(struct platform_device *pdev) 281 { 282 const struct of_device_id *id; 283 struct edac_mc_layer layers[2]; 284 struct mem_ctl_info *mci; 285 struct altr_sdram_mc_data *drvdata; 286 const struct altr_sdram_prv_data *priv; 287 struct regmap *mc_vbase; 288 struct dimm_info *dimm; 289 u32 read_reg; 290 int irq, irq2, res = 0; 291 unsigned long mem_size, irqflags = 0; 292 293 id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev); 294 if (!id) 295 return -ENODEV; 296 297 /* Grab the register range from the sdr controller in device tree */ 298 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 299 "altr,sdr-syscon"); 300 if (IS_ERR(mc_vbase)) { 301 edac_printk(KERN_ERR, EDAC_MC, 302 "regmap for altr,sdr-syscon lookup failed.\n"); 303 return -ENODEV; 304 } 305 306 /* Check specific dependencies for the module */ 307 priv = of_match_node(altr_sdram_ctrl_of_match, 308 pdev->dev.of_node)->data; 309 310 /* Validate the SDRAM controller has ECC enabled */ 311 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) || 312 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) { 313 edac_printk(KERN_ERR, EDAC_MC, 314 "No ECC/ECC disabled [0x%08X]\n", read_reg); 315 return -ENODEV; 316 } 317 318 /* Grab memory size from device tree. */ 319 mem_size = get_total_mem(); 320 if (!mem_size) { 321 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n"); 322 return -ENODEV; 323 } 324 325 /* Ensure the SDRAM Interrupt is disabled */ 326 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset, 327 priv->ecc_irq_en_mask, 0)) { 328 edac_printk(KERN_ERR, EDAC_MC, 329 "Error disabling SDRAM ECC IRQ\n"); 330 return -ENODEV; 331 } 332 333 /* Toggle to clear the SDRAM Error count */ 334 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, 335 priv->ecc_cnt_rst_mask, 336 priv->ecc_cnt_rst_mask)) { 337 edac_printk(KERN_ERR, EDAC_MC, 338 "Error clearing SDRAM ECC count\n"); 339 return -ENODEV; 340 } 341 342 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, 343 priv->ecc_cnt_rst_mask, 0)) { 344 edac_printk(KERN_ERR, EDAC_MC, 345 "Error clearing SDRAM ECC count\n"); 346 return -ENODEV; 347 } 348 349 irq = platform_get_irq(pdev, 0); 350 if (irq < 0) { 351 edac_printk(KERN_ERR, EDAC_MC, 352 "No irq %d in DT\n", irq); 353 return -ENODEV; 354 } 355 356 /* Arria10 has a 2nd IRQ */ 357 irq2 = platform_get_irq(pdev, 1); 358 359 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 360 layers[0].size = 1; 361 layers[0].is_virt_csrow = true; 362 layers[1].type = EDAC_MC_LAYER_CHANNEL; 363 layers[1].size = 1; 364 layers[1].is_virt_csrow = false; 365 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 366 sizeof(struct altr_sdram_mc_data)); 367 if (!mci) 368 return -ENOMEM; 369 370 mci->pdev = &pdev->dev; 371 drvdata = mci->pvt_info; 372 drvdata->mc_vbase = mc_vbase; 373 drvdata->data = priv; 374 platform_set_drvdata(pdev, mci); 375 376 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { 377 edac_printk(KERN_ERR, EDAC_MC, 378 "Unable to get managed device resource\n"); 379 res = -ENOMEM; 380 goto free; 381 } 382 383 mci->mtype_cap = MEM_FLAG_DDR3; 384 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 385 mci->edac_cap = EDAC_FLAG_SECDED; 386 mci->mod_name = EDAC_MOD_STR; 387 mci->ctl_name = dev_name(&pdev->dev); 388 mci->scrub_mode = SCRUB_SW_SRC; 389 mci->dev_name = dev_name(&pdev->dev); 390 391 dimm = *mci->dimms; 392 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1; 393 dimm->grain = 8; 394 dimm->dtype = DEV_X8; 395 dimm->mtype = MEM_DDR3; 396 dimm->edac_mode = EDAC_SECDED; 397 398 res = edac_mc_add_mc(mci); 399 if (res < 0) 400 goto err; 401 402 /* Only the Arria10 has separate IRQs */ 403 if (socfpga_is_a10()) { 404 /* Arria10 specific initialization */ 405 res = a10_init(mc_vbase); 406 if (res < 0) 407 goto err2; 408 409 res = devm_request_irq(&pdev->dev, irq2, 410 altr_sdram_mc_err_handler, 411 IRQF_SHARED, dev_name(&pdev->dev), mci); 412 if (res < 0) { 413 edac_mc_printk(mci, KERN_ERR, 414 "Unable to request irq %d\n", irq2); 415 res = -ENODEV; 416 goto err2; 417 } 418 419 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK); 420 if (res < 0) 421 goto err2; 422 423 irqflags = IRQF_SHARED; 424 } 425 426 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler, 427 irqflags, dev_name(&pdev->dev), mci); 428 if (res < 0) { 429 edac_mc_printk(mci, KERN_ERR, 430 "Unable to request irq %d\n", irq); 431 res = -ENODEV; 432 goto err2; 433 } 434 435 /* Infrastructure ready - enable the IRQ */ 436 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset, 437 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) { 438 edac_mc_printk(mci, KERN_ERR, 439 "Error enabling SDRAM ECC IRQ\n"); 440 res = -ENODEV; 441 goto err2; 442 } 443 444 altr_sdr_mc_create_debugfs_nodes(mci); 445 446 devres_close_group(&pdev->dev, NULL); 447 448 return 0; 449 450 err2: 451 edac_mc_del_mc(&pdev->dev); 452 err: 453 devres_release_group(&pdev->dev, NULL); 454 free: 455 edac_mc_free(mci); 456 edac_printk(KERN_ERR, EDAC_MC, 457 "EDAC Probe Failed; Error %d\n", res); 458 459 return res; 460 } 461 462 static int altr_sdram_remove(struct platform_device *pdev) 463 { 464 struct mem_ctl_info *mci = platform_get_drvdata(pdev); 465 466 edac_mc_del_mc(&pdev->dev); 467 edac_mc_free(mci); 468 platform_set_drvdata(pdev, NULL); 469 470 return 0; 471 } 472 473 /* 474 * If you want to suspend, need to disable EDAC by removing it 475 * from the device tree or defconfig. 476 */ 477 #ifdef CONFIG_PM 478 static int altr_sdram_prepare(struct device *dev) 479 { 480 pr_err("Suspend not allowed when EDAC is enabled.\n"); 481 482 return -EPERM; 483 } 484 485 static const struct dev_pm_ops altr_sdram_pm_ops = { 486 .prepare = altr_sdram_prepare, 487 }; 488 #endif 489 490 static struct platform_driver altr_sdram_edac_driver = { 491 .probe = altr_sdram_probe, 492 .remove = altr_sdram_remove, 493 .driver = { 494 .name = "altr_sdram_edac", 495 #ifdef CONFIG_PM 496 .pm = &altr_sdram_pm_ops, 497 #endif 498 .of_match_table = altr_sdram_ctrl_of_match, 499 }, 500 }; 501 502 module_platform_driver(altr_sdram_edac_driver); 503 504 #endif /* CONFIG_EDAC_ALTERA_SDRAM */ 505 506 /**************** Stratix 10 EDAC Memory Controller Functions ************/ 507 508 /** 509 * s10_protected_reg_write 510 * Write to a protected SMC register. 511 * @context: Not used. 512 * @reg: Address of register 513 * @value: Value to write 514 * Return: INTEL_SIP_SMC_STATUS_OK (0) on success 515 * INTEL_SIP_SMC_REG_ERROR on error 516 * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported 517 */ 518 static int s10_protected_reg_write(void *context, unsigned int reg, 519 unsigned int val) 520 { 521 struct arm_smccc_res result; 522 unsigned long offset = (unsigned long)context; 523 524 arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, offset + reg, val, 0, 0, 525 0, 0, 0, &result); 526 527 return (int)result.a0; 528 } 529 530 /** 531 * s10_protected_reg_read 532 * Read the status of a protected SMC register 533 * @context: Not used. 534 * @reg: Address of register 535 * @value: Value read. 536 * Return: INTEL_SIP_SMC_STATUS_OK (0) on success 537 * INTEL_SIP_SMC_REG_ERROR on error 538 * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported 539 */ 540 static int s10_protected_reg_read(void *context, unsigned int reg, 541 unsigned int *val) 542 { 543 struct arm_smccc_res result; 544 unsigned long offset = (unsigned long)context; 545 546 arm_smccc_smc(INTEL_SIP_SMC_REG_READ, offset + reg, 0, 0, 0, 547 0, 0, 0, &result); 548 549 *val = (unsigned int)result.a1; 550 551 return (int)result.a0; 552 } 553 554 static const struct regmap_config s10_sdram_regmap_cfg = { 555 .name = "s10_ddr", 556 .reg_bits = 32, 557 .reg_stride = 4, 558 .val_bits = 32, 559 .max_register = 0xffd12228, 560 .reg_read = s10_protected_reg_read, 561 .reg_write = s10_protected_reg_write, 562 .use_single_read = true, 563 .use_single_write = true, 564 }; 565 566 /************** </Stratix10 EDAC Memory Controller Functions> ***********/ 567 568 /************************* EDAC Parent Probe *************************/ 569 570 static const struct of_device_id altr_edac_device_of_match[]; 571 572 static const struct of_device_id altr_edac_of_match[] = { 573 { .compatible = "altr,socfpga-ecc-manager" }, 574 {}, 575 }; 576 MODULE_DEVICE_TABLE(of, altr_edac_of_match); 577 578 static int altr_edac_probe(struct platform_device *pdev) 579 { 580 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match, 581 NULL, &pdev->dev); 582 return 0; 583 } 584 585 static struct platform_driver altr_edac_driver = { 586 .probe = altr_edac_probe, 587 .driver = { 588 .name = "socfpga_ecc_manager", 589 .of_match_table = altr_edac_of_match, 590 }, 591 }; 592 module_platform_driver(altr_edac_driver); 593 594 /************************* EDAC Device Functions *************************/ 595 596 /* 597 * EDAC Device Functions (shared between various IPs). 598 * The discrete memories use the EDAC Device framework. The probe 599 * and error handling functions are very similar between memories 600 * so they are shared. The memory allocation and freeing for EDAC 601 * trigger testing are different for each memory. 602 */ 603 604 static const struct edac_device_prv_data ocramecc_data; 605 static const struct edac_device_prv_data l2ecc_data; 606 static const struct edac_device_prv_data a10_ocramecc_data; 607 static const struct edac_device_prv_data a10_l2ecc_data; 608 609 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id) 610 { 611 irqreturn_t ret_value = IRQ_NONE; 612 struct edac_device_ctl_info *dci = dev_id; 613 struct altr_edac_device_dev *drvdata = dci->pvt_info; 614 const struct edac_device_prv_data *priv = drvdata->data; 615 616 if (irq == drvdata->sb_irq) { 617 if (priv->ce_clear_mask) 618 writel(priv->ce_clear_mask, drvdata->base); 619 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name); 620 ret_value = IRQ_HANDLED; 621 } else if (irq == drvdata->db_irq) { 622 if (priv->ue_clear_mask) 623 writel(priv->ue_clear_mask, drvdata->base); 624 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name); 625 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); 626 ret_value = IRQ_HANDLED; 627 } else { 628 WARN_ON(1); 629 } 630 631 return ret_value; 632 } 633 634 static ssize_t altr_edac_device_trig(struct file *file, 635 const char __user *user_buf, 636 size_t count, loff_t *ppos) 637 638 { 639 u32 *ptemp, i, error_mask; 640 int result = 0; 641 u8 trig_type; 642 unsigned long flags; 643 struct edac_device_ctl_info *edac_dci = file->private_data; 644 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 645 const struct edac_device_prv_data *priv = drvdata->data; 646 void *generic_ptr = edac_dci->dev; 647 648 if (!user_buf || get_user(trig_type, user_buf)) 649 return -EFAULT; 650 651 if (!priv->alloc_mem) 652 return -ENOMEM; 653 654 /* 655 * Note that generic_ptr is initialized to the device * but in 656 * some alloc_functions, this is overridden and returns data. 657 */ 658 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr); 659 if (!ptemp) { 660 edac_printk(KERN_ERR, EDAC_DEVICE, 661 "Inject: Buffer Allocation error\n"); 662 return -ENOMEM; 663 } 664 665 if (trig_type == ALTR_UE_TRIGGER_CHAR) 666 error_mask = priv->ue_set_mask; 667 else 668 error_mask = priv->ce_set_mask; 669 670 edac_printk(KERN_ALERT, EDAC_DEVICE, 671 "Trigger Error Mask (0x%X)\n", error_mask); 672 673 local_irq_save(flags); 674 /* write ECC corrupted data out. */ 675 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) { 676 /* Read data so we're in the correct state */ 677 rmb(); 678 if (READ_ONCE(ptemp[i])) 679 result = -1; 680 /* Toggle Error bit (it is latched), leave ECC enabled */ 681 writel(error_mask, (drvdata->base + priv->set_err_ofst)); 682 writel(priv->ecc_enable_mask, (drvdata->base + 683 priv->set_err_ofst)); 684 ptemp[i] = i; 685 } 686 /* Ensure it has been written out */ 687 wmb(); 688 local_irq_restore(flags); 689 690 if (result) 691 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n"); 692 693 /* Read out written data. ECC error caused here */ 694 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++) 695 if (READ_ONCE(ptemp[i]) != i) 696 edac_printk(KERN_ERR, EDAC_DEVICE, 697 "Read doesn't match written data\n"); 698 699 if (priv->free_mem) 700 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr); 701 702 return count; 703 } 704 705 static const struct file_operations altr_edac_device_inject_fops = { 706 .open = simple_open, 707 .write = altr_edac_device_trig, 708 .llseek = generic_file_llseek, 709 }; 710 711 static ssize_t altr_edac_a10_device_trig(struct file *file, 712 const char __user *user_buf, 713 size_t count, loff_t *ppos); 714 715 static const struct file_operations altr_edac_a10_device_inject_fops = { 716 .open = simple_open, 717 .write = altr_edac_a10_device_trig, 718 .llseek = generic_file_llseek, 719 }; 720 721 static ssize_t altr_edac_a10_device_trig2(struct file *file, 722 const char __user *user_buf, 723 size_t count, loff_t *ppos); 724 725 static const struct file_operations altr_edac_a10_device_inject2_fops = { 726 .open = simple_open, 727 .write = altr_edac_a10_device_trig2, 728 .llseek = generic_file_llseek, 729 }; 730 731 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci, 732 const struct edac_device_prv_data *priv) 733 { 734 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 735 736 if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) 737 return; 738 739 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name); 740 if (!drvdata->debugfs_dir) 741 return; 742 743 if (!edac_debugfs_create_file("altr_trigger", S_IWUSR, 744 drvdata->debugfs_dir, edac_dci, 745 priv->inject_fops)) 746 debugfs_remove_recursive(drvdata->debugfs_dir); 747 } 748 749 static const struct of_device_id altr_edac_device_of_match[] = { 750 #ifdef CONFIG_EDAC_ALTERA_L2C 751 { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data }, 752 #endif 753 #ifdef CONFIG_EDAC_ALTERA_OCRAM 754 { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data }, 755 #endif 756 {}, 757 }; 758 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match); 759 760 /* 761 * altr_edac_device_probe() 762 * This is a generic EDAC device driver that will support 763 * various Altera memory devices such as the L2 cache ECC and 764 * OCRAM ECC as well as the memories for other peripherals. 765 * Module specific initialization is done by passing the 766 * function index in the device tree. 767 */ 768 static int altr_edac_device_probe(struct platform_device *pdev) 769 { 770 struct edac_device_ctl_info *dci; 771 struct altr_edac_device_dev *drvdata; 772 struct resource *r; 773 int res = 0; 774 struct device_node *np = pdev->dev.of_node; 775 char *ecc_name = (char *)np->name; 776 static int dev_instance; 777 778 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { 779 edac_printk(KERN_ERR, EDAC_DEVICE, 780 "Unable to open devm\n"); 781 return -ENOMEM; 782 } 783 784 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 785 if (!r) { 786 edac_printk(KERN_ERR, EDAC_DEVICE, 787 "Unable to get mem resource\n"); 788 res = -ENODEV; 789 goto fail; 790 } 791 792 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r), 793 dev_name(&pdev->dev))) { 794 edac_printk(KERN_ERR, EDAC_DEVICE, 795 "%s:Error requesting mem region\n", ecc_name); 796 res = -EBUSY; 797 goto fail; 798 } 799 800 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name, 801 1, ecc_name, 1, 0, NULL, 0, 802 dev_instance++); 803 804 if (!dci) { 805 edac_printk(KERN_ERR, EDAC_DEVICE, 806 "%s: Unable to allocate EDAC device\n", ecc_name); 807 res = -ENOMEM; 808 goto fail; 809 } 810 811 drvdata = dci->pvt_info; 812 dci->dev = &pdev->dev; 813 platform_set_drvdata(pdev, dci); 814 drvdata->edac_dev_name = ecc_name; 815 816 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); 817 if (!drvdata->base) { 818 res = -ENOMEM; 819 goto fail1; 820 } 821 822 /* Get driver specific data for this EDAC device */ 823 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data; 824 825 /* Check specific dependencies for the module */ 826 if (drvdata->data->setup) { 827 res = drvdata->data->setup(drvdata); 828 if (res) 829 goto fail1; 830 } 831 832 drvdata->sb_irq = platform_get_irq(pdev, 0); 833 res = devm_request_irq(&pdev->dev, drvdata->sb_irq, 834 altr_edac_device_handler, 835 0, dev_name(&pdev->dev), dci); 836 if (res) 837 goto fail1; 838 839 drvdata->db_irq = platform_get_irq(pdev, 1); 840 res = devm_request_irq(&pdev->dev, drvdata->db_irq, 841 altr_edac_device_handler, 842 0, dev_name(&pdev->dev), dci); 843 if (res) 844 goto fail1; 845 846 dci->mod_name = "Altera ECC Manager"; 847 dci->dev_name = drvdata->edac_dev_name; 848 849 res = edac_device_add_device(dci); 850 if (res) 851 goto fail1; 852 853 altr_create_edacdev_dbgfs(dci, drvdata->data); 854 855 devres_close_group(&pdev->dev, NULL); 856 857 return 0; 858 859 fail1: 860 edac_device_free_ctl_info(dci); 861 fail: 862 devres_release_group(&pdev->dev, NULL); 863 edac_printk(KERN_ERR, EDAC_DEVICE, 864 "%s:Error setting up EDAC device: %d\n", ecc_name, res); 865 866 return res; 867 } 868 869 static int altr_edac_device_remove(struct platform_device *pdev) 870 { 871 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev); 872 struct altr_edac_device_dev *drvdata = dci->pvt_info; 873 874 debugfs_remove_recursive(drvdata->debugfs_dir); 875 edac_device_del_device(&pdev->dev); 876 edac_device_free_ctl_info(dci); 877 878 return 0; 879 } 880 881 static struct platform_driver altr_edac_device_driver = { 882 .probe = altr_edac_device_probe, 883 .remove = altr_edac_device_remove, 884 .driver = { 885 .name = "altr_edac_device", 886 .of_match_table = altr_edac_device_of_match, 887 }, 888 }; 889 module_platform_driver(altr_edac_device_driver); 890 891 /******************* Arria10 Device ECC Shared Functions *****************/ 892 893 /* 894 * Test for memory's ECC dependencies upon entry because platform specific 895 * startup should have initialized the memory and enabled the ECC. 896 * Can't turn on ECC here because accessing un-initialized memory will 897 * cause CE/UE errors possibly causing an ABORT. 898 */ 899 static int __maybe_unused 900 altr_check_ecc_deps(struct altr_edac_device_dev *device) 901 { 902 void __iomem *base = device->base; 903 const struct edac_device_prv_data *prv = device->data; 904 905 if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask) 906 return 0; 907 908 edac_printk(KERN_ERR, EDAC_DEVICE, 909 "%s: No ECC present or ECC disabled.\n", 910 device->edac_dev_name); 911 return -ENODEV; 912 } 913 914 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id) 915 { 916 struct altr_edac_device_dev *dci = dev_id; 917 void __iomem *base = dci->base; 918 919 if (irq == dci->sb_irq) { 920 writel(ALTR_A10_ECC_SERRPENA, 921 base + ALTR_A10_ECC_INTSTAT_OFST); 922 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); 923 924 return IRQ_HANDLED; 925 } else if (irq == dci->db_irq) { 926 writel(ALTR_A10_ECC_DERRPENA, 927 base + ALTR_A10_ECC_INTSTAT_OFST); 928 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); 929 if (dci->data->panic) 930 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); 931 932 return IRQ_HANDLED; 933 } 934 935 WARN_ON(1); 936 937 return IRQ_NONE; 938 } 939 940 /******************* Arria10 Memory Buffer Functions *********************/ 941 942 static inline int a10_get_irq_mask(struct device_node *np) 943 { 944 int irq; 945 const u32 *handle = of_get_property(np, "interrupts", NULL); 946 947 if (!handle) 948 return -ENODEV; 949 irq = be32_to_cpup(handle); 950 return irq; 951 } 952 953 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr) 954 { 955 u32 value = readl(ioaddr); 956 957 value |= bit_mask; 958 writel(value, ioaddr); 959 } 960 961 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr) 962 { 963 u32 value = readl(ioaddr); 964 965 value &= ~bit_mask; 966 writel(value, ioaddr); 967 } 968 969 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr) 970 { 971 u32 value = readl(ioaddr); 972 973 return (value & bit_mask) ? 1 : 0; 974 } 975 976 /* 977 * This function uses the memory initialization block in the Arria10 ECC 978 * controller to initialize/clear the entire memory data and ECC data. 979 */ 980 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port) 981 { 982 int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US; 983 u32 init_mask, stat_mask, clear_mask; 984 int ret = 0; 985 986 if (port) { 987 init_mask = ALTR_A10_ECC_INITB; 988 stat_mask = ALTR_A10_ECC_INITCOMPLETEB; 989 clear_mask = ALTR_A10_ECC_ERRPENB_MASK; 990 } else { 991 init_mask = ALTR_A10_ECC_INITA; 992 stat_mask = ALTR_A10_ECC_INITCOMPLETEA; 993 clear_mask = ALTR_A10_ECC_ERRPENA_MASK; 994 } 995 996 ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST)); 997 while (limit--) { 998 if (ecc_test_bits(stat_mask, 999 (ioaddr + ALTR_A10_ECC_INITSTAT_OFST))) 1000 break; 1001 udelay(1); 1002 } 1003 if (limit < 0) 1004 ret = -EBUSY; 1005 1006 /* Clear any pending ECC interrupts */ 1007 writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST)); 1008 1009 return ret; 1010 } 1011 1012 static int socfpga_is_a10(void) 1013 { 1014 return of_machine_is_compatible("altr,socfpga-arria10"); 1015 } 1016 1017 static int socfpga_is_s10(void) 1018 { 1019 return of_machine_is_compatible("altr,socfpga-stratix10"); 1020 } 1021 1022 static __init int __maybe_unused 1023 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask, 1024 u32 ecc_ctrl_en_mask, bool dual_port) 1025 { 1026 int ret = 0; 1027 void __iomem *ecc_block_base; 1028 struct regmap *ecc_mgr_map; 1029 char *ecc_name; 1030 struct device_node *np_eccmgr; 1031 1032 ecc_name = (char *)np->name; 1033 1034 /* Get the ECC Manager - parent of the device EDACs */ 1035 np_eccmgr = of_get_parent(np); 1036 1037 if (socfpga_is_a10()) { 1038 ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr, 1039 "altr,sysmgr-syscon"); 1040 } else { 1041 struct device_node *sysmgr_np; 1042 struct resource res; 1043 uintptr_t base; 1044 1045 sysmgr_np = of_parse_phandle(np_eccmgr, 1046 "altr,sysmgr-syscon", 0); 1047 if (!sysmgr_np) { 1048 edac_printk(KERN_ERR, EDAC_DEVICE, 1049 "Unable to find altr,sysmgr-syscon\n"); 1050 return -ENODEV; 1051 } 1052 1053 if (of_address_to_resource(sysmgr_np, 0, &res)) { 1054 of_node_put(sysmgr_np); 1055 return -ENOMEM; 1056 } 1057 1058 /* Need physical address for SMCC call */ 1059 base = res.start; 1060 1061 ecc_mgr_map = regmap_init(NULL, NULL, (void *)base, 1062 &s10_sdram_regmap_cfg); 1063 of_node_put(sysmgr_np); 1064 } 1065 of_node_put(np_eccmgr); 1066 if (IS_ERR(ecc_mgr_map)) { 1067 edac_printk(KERN_ERR, EDAC_DEVICE, 1068 "Unable to get syscon altr,sysmgr-syscon\n"); 1069 return -ENODEV; 1070 } 1071 1072 /* Map the ECC Block */ 1073 ecc_block_base = of_iomap(np, 0); 1074 if (!ecc_block_base) { 1075 edac_printk(KERN_ERR, EDAC_DEVICE, 1076 "Unable to map %s ECC block\n", ecc_name); 1077 return -ENODEV; 1078 } 1079 1080 /* Disable ECC */ 1081 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask); 1082 writel(ALTR_A10_ECC_SERRINTEN, 1083 (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST)); 1084 ecc_clear_bits(ecc_ctrl_en_mask, 1085 (ecc_block_base + ALTR_A10_ECC_CTRL_OFST)); 1086 /* Ensure all writes complete */ 1087 wmb(); 1088 /* Use HW initialization block to initialize memory for ECC */ 1089 ret = altr_init_memory_port(ecc_block_base, 0); 1090 if (ret) { 1091 edac_printk(KERN_ERR, EDAC_DEVICE, 1092 "ECC: cannot init %s PORTA memory\n", ecc_name); 1093 goto out; 1094 } 1095 1096 if (dual_port) { 1097 ret = altr_init_memory_port(ecc_block_base, 1); 1098 if (ret) { 1099 edac_printk(KERN_ERR, EDAC_DEVICE, 1100 "ECC: cannot init %s PORTB memory\n", 1101 ecc_name); 1102 goto out; 1103 } 1104 } 1105 1106 /* Interrupt mode set to every SBERR */ 1107 regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST, 1108 ALTR_A10_ECC_INTMODE); 1109 /* Enable ECC */ 1110 ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base + 1111 ALTR_A10_ECC_CTRL_OFST)); 1112 writel(ALTR_A10_ECC_SERRINTEN, 1113 (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST)); 1114 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask); 1115 /* Ensure all writes complete */ 1116 wmb(); 1117 out: 1118 iounmap(ecc_block_base); 1119 return ret; 1120 } 1121 1122 static int validate_parent_available(struct device_node *np); 1123 static const struct of_device_id altr_edac_a10_device_of_match[]; 1124 static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat) 1125 { 1126 int irq; 1127 struct device_node *child, *np; 1128 1129 if (!socfpga_is_a10() && !socfpga_is_s10()) 1130 return -ENODEV; 1131 1132 np = of_find_compatible_node(NULL, NULL, 1133 "altr,socfpga-a10-ecc-manager"); 1134 if (!np) { 1135 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n"); 1136 return -ENODEV; 1137 } 1138 1139 for_each_child_of_node(np, child) { 1140 const struct of_device_id *pdev_id; 1141 const struct edac_device_prv_data *prv; 1142 1143 if (!of_device_is_available(child)) 1144 continue; 1145 if (!of_device_is_compatible(child, compat)) 1146 continue; 1147 1148 if (validate_parent_available(child)) 1149 continue; 1150 1151 irq = a10_get_irq_mask(child); 1152 if (irq < 0) 1153 continue; 1154 1155 /* Get matching node and check for valid result */ 1156 pdev_id = of_match_node(altr_edac_a10_device_of_match, child); 1157 if (IS_ERR_OR_NULL(pdev_id)) 1158 continue; 1159 1160 /* Validate private data pointer before dereferencing */ 1161 prv = pdev_id->data; 1162 if (!prv) 1163 continue; 1164 1165 altr_init_a10_ecc_block(child, BIT(irq), 1166 prv->ecc_enable_mask, 0); 1167 } 1168 1169 of_node_put(np); 1170 return 0; 1171 } 1172 1173 /*********************** OCRAM EDAC Device Functions *********************/ 1174 1175 #ifdef CONFIG_EDAC_ALTERA_OCRAM 1176 1177 static void *ocram_alloc_mem(size_t size, void **other) 1178 { 1179 struct device_node *np; 1180 struct gen_pool *gp; 1181 void *sram_addr; 1182 1183 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); 1184 if (!np) 1185 return NULL; 1186 1187 gp = of_gen_pool_get(np, "iram", 0); 1188 of_node_put(np); 1189 if (!gp) 1190 return NULL; 1191 1192 sram_addr = (void *)gen_pool_alloc(gp, size); 1193 if (!sram_addr) 1194 return NULL; 1195 1196 memset(sram_addr, 0, size); 1197 /* Ensure data is written out */ 1198 wmb(); 1199 1200 /* Remember this handle for freeing later */ 1201 *other = gp; 1202 1203 return sram_addr; 1204 } 1205 1206 static void ocram_free_mem(void *p, size_t size, void *other) 1207 { 1208 gen_pool_free((struct gen_pool *)other, (unsigned long)p, size); 1209 } 1210 1211 static const struct edac_device_prv_data ocramecc_data = { 1212 .setup = altr_check_ecc_deps, 1213 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR), 1214 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR), 1215 .alloc_mem = ocram_alloc_mem, 1216 .free_mem = ocram_free_mem, 1217 .ecc_enable_mask = ALTR_OCR_ECC_EN, 1218 .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET, 1219 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS), 1220 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD), 1221 .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET, 1222 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE, 1223 .inject_fops = &altr_edac_device_inject_fops, 1224 }; 1225 1226 static const struct edac_device_prv_data a10_ocramecc_data = { 1227 .setup = altr_check_ecc_deps, 1228 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1229 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1230 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM, 1231 .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL, 1232 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1233 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1234 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1235 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1236 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1237 .inject_fops = &altr_edac_a10_device_inject_fops, 1238 /* 1239 * OCRAM panic on uncorrectable error because sleep/resume 1240 * functions and FPGA contents are stored in OCRAM. Prefer 1241 * a kernel panic over executing/loading corrupted data. 1242 */ 1243 .panic = true, 1244 }; 1245 1246 #endif /* CONFIG_EDAC_ALTERA_OCRAM */ 1247 1248 /********************* L2 Cache EDAC Device Functions ********************/ 1249 1250 #ifdef CONFIG_EDAC_ALTERA_L2C 1251 1252 static void *l2_alloc_mem(size_t size, void **other) 1253 { 1254 struct device *dev = *other; 1255 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL); 1256 1257 if (!ptemp) 1258 return NULL; 1259 1260 /* Make sure everything is written out */ 1261 wmb(); 1262 1263 /* 1264 * Clean all cache levels up to LoC (includes L2) 1265 * This ensures the corrupted data is written into 1266 * L2 cache for readback test (which causes ECC error). 1267 */ 1268 flush_cache_all(); 1269 1270 return ptemp; 1271 } 1272 1273 static void l2_free_mem(void *p, size_t size, void *other) 1274 { 1275 struct device *dev = other; 1276 1277 if (dev && p) 1278 devm_kfree(dev, p); 1279 } 1280 1281 /* 1282 * altr_l2_check_deps() 1283 * Test for L2 cache ECC dependencies upon entry because 1284 * platform specific startup should have initialized the L2 1285 * memory and enabled the ECC. 1286 * Bail if ECC is not enabled. 1287 * Note that L2 Cache Enable is forced at build time. 1288 */ 1289 static int altr_l2_check_deps(struct altr_edac_device_dev *device) 1290 { 1291 void __iomem *base = device->base; 1292 const struct edac_device_prv_data *prv = device->data; 1293 1294 if ((readl(base) & prv->ecc_enable_mask) == 1295 prv->ecc_enable_mask) 1296 return 0; 1297 1298 edac_printk(KERN_ERR, EDAC_DEVICE, 1299 "L2: No ECC present, or ECC disabled\n"); 1300 return -ENODEV; 1301 } 1302 1303 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id) 1304 { 1305 struct altr_edac_device_dev *dci = dev_id; 1306 1307 if (irq == dci->sb_irq) { 1308 regmap_write(dci->edac->ecc_mgr_map, 1309 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, 1310 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB); 1311 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); 1312 1313 return IRQ_HANDLED; 1314 } else if (irq == dci->db_irq) { 1315 regmap_write(dci->edac->ecc_mgr_map, 1316 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, 1317 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB); 1318 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); 1319 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); 1320 1321 return IRQ_HANDLED; 1322 } 1323 1324 WARN_ON(1); 1325 1326 return IRQ_NONE; 1327 } 1328 1329 static const struct edac_device_prv_data l2ecc_data = { 1330 .setup = altr_l2_check_deps, 1331 .ce_clear_mask = 0, 1332 .ue_clear_mask = 0, 1333 .alloc_mem = l2_alloc_mem, 1334 .free_mem = l2_free_mem, 1335 .ecc_enable_mask = ALTR_L2_ECC_EN, 1336 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS), 1337 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD), 1338 .set_err_ofst = ALTR_L2_ECC_REG_OFFSET, 1339 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, 1340 .inject_fops = &altr_edac_device_inject_fops, 1341 }; 1342 1343 static const struct edac_device_prv_data a10_l2ecc_data = { 1344 .setup = altr_l2_check_deps, 1345 .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR, 1346 .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR, 1347 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2, 1348 .alloc_mem = l2_alloc_mem, 1349 .free_mem = l2_free_mem, 1350 .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL, 1351 .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK, 1352 .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK, 1353 .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST, 1354 .ecc_irq_handler = altr_edac_a10_l2_irq, 1355 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, 1356 .inject_fops = &altr_edac_device_inject_fops, 1357 }; 1358 1359 #endif /* CONFIG_EDAC_ALTERA_L2C */ 1360 1361 /********************* Ethernet Device Functions ********************/ 1362 1363 #ifdef CONFIG_EDAC_ALTERA_ETHERNET 1364 1365 static int __init socfpga_init_ethernet_ecc(struct altr_edac_device_dev *dev) 1366 { 1367 int ret; 1368 1369 ret = altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc"); 1370 if (ret) 1371 return ret; 1372 1373 return altr_check_ecc_deps(dev); 1374 } 1375 1376 static const struct edac_device_prv_data a10_enetecc_data = { 1377 .setup = socfpga_init_ethernet_ecc, 1378 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1379 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1380 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1381 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1382 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1383 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1384 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1385 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1386 .inject_fops = &altr_edac_a10_device_inject2_fops, 1387 }; 1388 1389 #endif /* CONFIG_EDAC_ALTERA_ETHERNET */ 1390 1391 /********************** NAND Device Functions **********************/ 1392 1393 #ifdef CONFIG_EDAC_ALTERA_NAND 1394 1395 static int __init socfpga_init_nand_ecc(struct altr_edac_device_dev *device) 1396 { 1397 int ret; 1398 1399 ret = altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc"); 1400 if (ret) 1401 return ret; 1402 1403 return altr_check_ecc_deps(device); 1404 } 1405 1406 static const struct edac_device_prv_data a10_nandecc_data = { 1407 .setup = socfpga_init_nand_ecc, 1408 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1409 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1410 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1411 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1412 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1413 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1414 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1415 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1416 .inject_fops = &altr_edac_a10_device_inject_fops, 1417 }; 1418 1419 #endif /* CONFIG_EDAC_ALTERA_NAND */ 1420 1421 /********************** DMA Device Functions **********************/ 1422 1423 #ifdef CONFIG_EDAC_ALTERA_DMA 1424 1425 static int __init socfpga_init_dma_ecc(struct altr_edac_device_dev *device) 1426 { 1427 int ret; 1428 1429 ret = altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc"); 1430 if (ret) 1431 return ret; 1432 1433 return altr_check_ecc_deps(device); 1434 } 1435 1436 static const struct edac_device_prv_data a10_dmaecc_data = { 1437 .setup = socfpga_init_dma_ecc, 1438 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1439 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1440 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1441 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1442 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1443 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1444 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1445 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1446 .inject_fops = &altr_edac_a10_device_inject_fops, 1447 }; 1448 1449 #endif /* CONFIG_EDAC_ALTERA_DMA */ 1450 1451 /********************** USB Device Functions **********************/ 1452 1453 #ifdef CONFIG_EDAC_ALTERA_USB 1454 1455 static int __init socfpga_init_usb_ecc(struct altr_edac_device_dev *device) 1456 { 1457 int ret; 1458 1459 ret = altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc"); 1460 if (ret) 1461 return ret; 1462 1463 return altr_check_ecc_deps(device); 1464 } 1465 1466 static const struct edac_device_prv_data a10_usbecc_data = { 1467 .setup = socfpga_init_usb_ecc, 1468 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1469 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1470 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1471 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1472 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1473 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1474 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1475 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1476 .inject_fops = &altr_edac_a10_device_inject2_fops, 1477 }; 1478 1479 #endif /* CONFIG_EDAC_ALTERA_USB */ 1480 1481 /********************** QSPI Device Functions **********************/ 1482 1483 #ifdef CONFIG_EDAC_ALTERA_QSPI 1484 1485 static int __init socfpga_init_qspi_ecc(struct altr_edac_device_dev *device) 1486 { 1487 int ret; 1488 1489 ret = altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc"); 1490 if (ret) 1491 return ret; 1492 1493 return altr_check_ecc_deps(device); 1494 } 1495 1496 static const struct edac_device_prv_data a10_qspiecc_data = { 1497 .setup = socfpga_init_qspi_ecc, 1498 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1499 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1500 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1501 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1502 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1503 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1504 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1505 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1506 .inject_fops = &altr_edac_a10_device_inject_fops, 1507 }; 1508 1509 #endif /* CONFIG_EDAC_ALTERA_QSPI */ 1510 1511 /********************* SDMMC Device Functions **********************/ 1512 1513 #ifdef CONFIG_EDAC_ALTERA_SDMMC 1514 1515 static const struct edac_device_prv_data a10_sdmmceccb_data; 1516 static int altr_portb_setup(struct altr_edac_device_dev *device) 1517 { 1518 struct edac_device_ctl_info *dci; 1519 struct altr_edac_device_dev *altdev; 1520 char *ecc_name = "sdmmcb-ecc"; 1521 int edac_idx, rc; 1522 struct device_node *np; 1523 const struct edac_device_prv_data *prv = &a10_sdmmceccb_data; 1524 1525 rc = altr_check_ecc_deps(device); 1526 if (rc) 1527 return rc; 1528 1529 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc"); 1530 if (!np) { 1531 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n"); 1532 return -ENODEV; 1533 } 1534 1535 /* Create the PortB EDAC device */ 1536 edac_idx = edac_device_alloc_index(); 1537 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1, 1538 ecc_name, 1, 0, NULL, 0, edac_idx); 1539 if (!dci) { 1540 edac_printk(KERN_ERR, EDAC_DEVICE, 1541 "%s: Unable to allocate PortB EDAC device\n", 1542 ecc_name); 1543 return -ENOMEM; 1544 } 1545 1546 /* Initialize the PortB EDAC device structure from PortA structure */ 1547 altdev = dci->pvt_info; 1548 *altdev = *device; 1549 1550 if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL)) 1551 return -ENOMEM; 1552 1553 /* Update PortB specific values */ 1554 altdev->edac_dev_name = ecc_name; 1555 altdev->edac_idx = edac_idx; 1556 altdev->edac_dev = dci; 1557 altdev->data = prv; 1558 dci->dev = &altdev->ddev; 1559 dci->ctl_name = "Altera ECC Manager"; 1560 dci->mod_name = ecc_name; 1561 dci->dev_name = ecc_name; 1562 1563 /* Update the IRQs for PortB */ 1564 altdev->sb_irq = irq_of_parse_and_map(np, 2); 1565 if (!altdev->sb_irq) { 1566 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n"); 1567 rc = -ENODEV; 1568 goto err_release_group_1; 1569 } 1570 rc = devm_request_irq(&altdev->ddev, altdev->sb_irq, 1571 prv->ecc_irq_handler, 1572 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 1573 ecc_name, altdev); 1574 if (rc) { 1575 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n"); 1576 goto err_release_group_1; 1577 } 1578 1579 altdev->db_irq = irq_of_parse_and_map(np, 3); 1580 if (!altdev->db_irq) { 1581 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n"); 1582 rc = -ENODEV; 1583 goto err_release_group_1; 1584 } 1585 rc = devm_request_irq(&altdev->ddev, altdev->db_irq, 1586 prv->ecc_irq_handler, 1587 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 1588 ecc_name, altdev); 1589 if (rc) { 1590 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n"); 1591 goto err_release_group_1; 1592 } 1593 1594 rc = edac_device_add_device(dci); 1595 if (rc) { 1596 edac_printk(KERN_ERR, EDAC_DEVICE, 1597 "edac_device_add_device portB failed\n"); 1598 rc = -ENOMEM; 1599 goto err_release_group_1; 1600 } 1601 altr_create_edacdev_dbgfs(dci, prv); 1602 1603 list_add(&altdev->next, &altdev->edac->a10_ecc_devices); 1604 1605 devres_remove_group(&altdev->ddev, altr_portb_setup); 1606 1607 return 0; 1608 1609 err_release_group_1: 1610 edac_device_free_ctl_info(dci); 1611 devres_release_group(&altdev->ddev, altr_portb_setup); 1612 edac_printk(KERN_ERR, EDAC_DEVICE, 1613 "%s:Error setting up EDAC device: %d\n", ecc_name, rc); 1614 return rc; 1615 } 1616 1617 static int __init socfpga_init_sdmmc_ecc(struct altr_edac_device_dev *device) 1618 { 1619 int rc = -ENODEV; 1620 struct device_node *child; 1621 1622 child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc"); 1623 if (!child) 1624 return -ENODEV; 1625 1626 if (!of_device_is_available(child)) 1627 goto exit; 1628 1629 if (validate_parent_available(child)) 1630 goto exit; 1631 1632 /* Init portB */ 1633 rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK, 1634 a10_sdmmceccb_data.ecc_enable_mask, 1); 1635 if (rc) 1636 goto exit; 1637 1638 /* Setup portB */ 1639 return altr_portb_setup(device); 1640 1641 exit: 1642 of_node_put(child); 1643 return rc; 1644 } 1645 1646 static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id) 1647 { 1648 struct altr_edac_device_dev *ad = dev_id; 1649 void __iomem *base = ad->base; 1650 const struct edac_device_prv_data *priv = ad->data; 1651 1652 if (irq == ad->sb_irq) { 1653 writel(priv->ce_clear_mask, 1654 base + ALTR_A10_ECC_INTSTAT_OFST); 1655 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name); 1656 return IRQ_HANDLED; 1657 } else if (irq == ad->db_irq) { 1658 writel(priv->ue_clear_mask, 1659 base + ALTR_A10_ECC_INTSTAT_OFST); 1660 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name); 1661 return IRQ_HANDLED; 1662 } 1663 1664 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq); 1665 1666 return IRQ_NONE; 1667 } 1668 1669 static const struct edac_device_prv_data a10_sdmmcecca_data = { 1670 .setup = socfpga_init_sdmmc_ecc, 1671 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1672 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1673 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1674 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1675 .ce_set_mask = ALTR_A10_ECC_SERRPENA, 1676 .ue_set_mask = ALTR_A10_ECC_DERRPENA, 1677 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1678 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1679 .inject_fops = &altr_edac_a10_device_inject_fops, 1680 }; 1681 1682 static const struct edac_device_prv_data a10_sdmmceccb_data = { 1683 .setup = socfpga_init_sdmmc_ecc, 1684 .ce_clear_mask = ALTR_A10_ECC_SERRPENB, 1685 .ue_clear_mask = ALTR_A10_ECC_DERRPENB, 1686 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1687 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1688 .ce_set_mask = ALTR_A10_ECC_TSERRB, 1689 .ue_set_mask = ALTR_A10_ECC_TDERRB, 1690 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1691 .ecc_irq_handler = altr_edac_a10_ecc_irq_portb, 1692 .inject_fops = &altr_edac_a10_device_inject_fops, 1693 }; 1694 1695 #endif /* CONFIG_EDAC_ALTERA_SDMMC */ 1696 1697 /********************* Arria10 EDAC Device Functions *************************/ 1698 static const struct of_device_id altr_edac_a10_device_of_match[] = { 1699 #ifdef CONFIG_EDAC_ALTERA_L2C 1700 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data }, 1701 #endif 1702 #ifdef CONFIG_EDAC_ALTERA_OCRAM 1703 { .compatible = "altr,socfpga-a10-ocram-ecc", 1704 .data = &a10_ocramecc_data }, 1705 #endif 1706 #ifdef CONFIG_EDAC_ALTERA_ETHERNET 1707 { .compatible = "altr,socfpga-eth-mac-ecc", 1708 .data = &a10_enetecc_data }, 1709 #endif 1710 #ifdef CONFIG_EDAC_ALTERA_NAND 1711 { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data }, 1712 #endif 1713 #ifdef CONFIG_EDAC_ALTERA_DMA 1714 { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data }, 1715 #endif 1716 #ifdef CONFIG_EDAC_ALTERA_USB 1717 { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data }, 1718 #endif 1719 #ifdef CONFIG_EDAC_ALTERA_QSPI 1720 { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data }, 1721 #endif 1722 #ifdef CONFIG_EDAC_ALTERA_SDMMC 1723 { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data }, 1724 #endif 1725 {}, 1726 }; 1727 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match); 1728 1729 /* 1730 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5 1731 * because 2 IRQs are shared among the all ECC peripherals. The ECC 1732 * manager manages the IRQs and the children. 1733 * Based on xgene_edac.c peripheral code. 1734 */ 1735 1736 static ssize_t altr_edac_a10_device_trig(struct file *file, 1737 const char __user *user_buf, 1738 size_t count, loff_t *ppos) 1739 { 1740 struct edac_device_ctl_info *edac_dci = file->private_data; 1741 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 1742 const struct edac_device_prv_data *priv = drvdata->data; 1743 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst); 1744 unsigned long flags; 1745 u8 trig_type; 1746 1747 if (!user_buf || get_user(trig_type, user_buf)) 1748 return -EFAULT; 1749 1750 local_irq_save(flags); 1751 if (trig_type == ALTR_UE_TRIGGER_CHAR) 1752 writel(priv->ue_set_mask, set_addr); 1753 else 1754 writel(priv->ce_set_mask, set_addr); 1755 1756 /* Ensure the interrupt test bits are set */ 1757 wmb(); 1758 local_irq_restore(flags); 1759 1760 return count; 1761 } 1762 1763 /* 1764 * The Stratix10 EDAC Error Injection Functions differ from Arria10 1765 * slightly. A few Arria10 peripherals can use this injection function. 1766 * Inject the error into the memory and then readback to trigger the IRQ. 1767 */ 1768 static ssize_t altr_edac_a10_device_trig2(struct file *file, 1769 const char __user *user_buf, 1770 size_t count, loff_t *ppos) 1771 { 1772 struct edac_device_ctl_info *edac_dci = file->private_data; 1773 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 1774 const struct edac_device_prv_data *priv = drvdata->data; 1775 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst); 1776 unsigned long flags; 1777 u8 trig_type; 1778 1779 if (!user_buf || get_user(trig_type, user_buf)) 1780 return -EFAULT; 1781 1782 local_irq_save(flags); 1783 if (trig_type == ALTR_UE_TRIGGER_CHAR) { 1784 writel(priv->ue_set_mask, set_addr); 1785 } else { 1786 /* Setup read/write of 4 bytes */ 1787 writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST); 1788 /* Setup Address to 0 */ 1789 writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST); 1790 /* Setup accctrl to read & ecc & data override */ 1791 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST); 1792 /* Kick it. */ 1793 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST); 1794 /* Setup write for single bit change */ 1795 writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1, 1796 drvdata->base + ECC_BLK_WDATA0_OFST); 1797 writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST), 1798 drvdata->base + ECC_BLK_WDATA1_OFST); 1799 writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST), 1800 drvdata->base + ECC_BLK_WDATA2_OFST); 1801 writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST), 1802 drvdata->base + ECC_BLK_WDATA3_OFST); 1803 1804 /* Copy Read ECC to Write ECC */ 1805 writel(readl(drvdata->base + ECC_BLK_RECC0_OFST), 1806 drvdata->base + ECC_BLK_WECC0_OFST); 1807 writel(readl(drvdata->base + ECC_BLK_RECC1_OFST), 1808 drvdata->base + ECC_BLK_WECC1_OFST); 1809 /* Setup accctrl to write & ecc override & data override */ 1810 writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST); 1811 /* Kick it. */ 1812 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST); 1813 /* Setup accctrl to read & ecc overwrite & data overwrite */ 1814 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST); 1815 /* Kick it. */ 1816 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST); 1817 } 1818 1819 /* Ensure the interrupt test bits are set */ 1820 wmb(); 1821 local_irq_restore(flags); 1822 1823 return count; 1824 } 1825 1826 static void altr_edac_a10_irq_handler(struct irq_desc *desc) 1827 { 1828 int dberr, bit, sm_offset, irq_status; 1829 struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc); 1830 struct irq_chip *chip = irq_desc_get_chip(desc); 1831 int irq = irq_desc_get_irq(desc); 1832 1833 dberr = (irq == edac->db_irq) ? 1 : 0; 1834 sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST : 1835 A10_SYSMGR_ECC_INTSTAT_SERR_OFST; 1836 1837 chained_irq_enter(chip, desc); 1838 1839 regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status); 1840 1841 for_each_set_bit(bit, (unsigned long *)&irq_status, 32) { 1842 irq = irq_linear_revmap(edac->domain, dberr * 32 + bit); 1843 if (irq) 1844 generic_handle_irq(irq); 1845 } 1846 1847 chained_irq_exit(chip, desc); 1848 } 1849 1850 static int validate_parent_available(struct device_node *np) 1851 { 1852 struct device_node *parent; 1853 int ret = 0; 1854 1855 /* Ensure parent device is enabled if parent node exists */ 1856 parent = of_parse_phandle(np, "altr,ecc-parent", 0); 1857 if (parent && !of_device_is_available(parent)) 1858 ret = -ENODEV; 1859 1860 of_node_put(parent); 1861 return ret; 1862 } 1863 1864 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac, 1865 struct device_node *np) 1866 { 1867 struct edac_device_ctl_info *dci; 1868 struct altr_edac_device_dev *altdev; 1869 char *ecc_name = (char *)np->name; 1870 struct resource res; 1871 int edac_idx; 1872 int rc = 0; 1873 const struct edac_device_prv_data *prv; 1874 /* Get matching node and check for valid result */ 1875 const struct of_device_id *pdev_id = 1876 of_match_node(altr_edac_a10_device_of_match, np); 1877 if (IS_ERR_OR_NULL(pdev_id)) 1878 return -ENODEV; 1879 1880 /* Get driver specific data for this EDAC device */ 1881 prv = pdev_id->data; 1882 if (IS_ERR_OR_NULL(prv)) 1883 return -ENODEV; 1884 1885 if (validate_parent_available(np)) 1886 return -ENODEV; 1887 1888 if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL)) 1889 return -ENOMEM; 1890 1891 rc = of_address_to_resource(np, 0, &res); 1892 if (rc < 0) { 1893 edac_printk(KERN_ERR, EDAC_DEVICE, 1894 "%s: no resource address\n", ecc_name); 1895 goto err_release_group; 1896 } 1897 1898 edac_idx = edac_device_alloc_index(); 1899 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1900 1, ecc_name, 1, 0, NULL, 0, 1901 edac_idx); 1902 1903 if (!dci) { 1904 edac_printk(KERN_ERR, EDAC_DEVICE, 1905 "%s: Unable to allocate EDAC device\n", ecc_name); 1906 rc = -ENOMEM; 1907 goto err_release_group; 1908 } 1909 1910 altdev = dci->pvt_info; 1911 dci->dev = edac->dev; 1912 altdev->edac_dev_name = ecc_name; 1913 altdev->edac_idx = edac_idx; 1914 altdev->edac = edac; 1915 altdev->edac_dev = dci; 1916 altdev->data = prv; 1917 altdev->ddev = *edac->dev; 1918 dci->dev = &altdev->ddev; 1919 dci->ctl_name = "Altera ECC Manager"; 1920 dci->mod_name = ecc_name; 1921 dci->dev_name = ecc_name; 1922 1923 altdev->base = devm_ioremap_resource(edac->dev, &res); 1924 if (IS_ERR(altdev->base)) { 1925 rc = PTR_ERR(altdev->base); 1926 goto err_release_group1; 1927 } 1928 1929 /* Check specific dependencies for the module */ 1930 if (altdev->data->setup) { 1931 rc = altdev->data->setup(altdev); 1932 if (rc) 1933 goto err_release_group1; 1934 } 1935 1936 altdev->sb_irq = irq_of_parse_and_map(np, 0); 1937 if (!altdev->sb_irq) { 1938 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n"); 1939 rc = -ENODEV; 1940 goto err_release_group1; 1941 } 1942 rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler, 1943 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 1944 ecc_name, altdev); 1945 if (rc) { 1946 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n"); 1947 goto err_release_group1; 1948 } 1949 1950 #ifdef CONFIG_ARCH_STRATIX10 1951 /* Use IRQ to determine SError origin instead of assigning IRQ */ 1952 rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq); 1953 if (rc) { 1954 edac_printk(KERN_ERR, EDAC_DEVICE, 1955 "Unable to parse DB IRQ index\n"); 1956 goto err_release_group1; 1957 } 1958 #else 1959 altdev->db_irq = irq_of_parse_and_map(np, 1); 1960 if (!altdev->db_irq) { 1961 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n"); 1962 rc = -ENODEV; 1963 goto err_release_group1; 1964 } 1965 rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler, 1966 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 1967 ecc_name, altdev); 1968 if (rc) { 1969 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n"); 1970 goto err_release_group1; 1971 } 1972 #endif 1973 1974 rc = edac_device_add_device(dci); 1975 if (rc) { 1976 dev_err(edac->dev, "edac_device_add_device failed\n"); 1977 rc = -ENOMEM; 1978 goto err_release_group1; 1979 } 1980 1981 altr_create_edacdev_dbgfs(dci, prv); 1982 1983 list_add(&altdev->next, &edac->a10_ecc_devices); 1984 1985 devres_remove_group(edac->dev, altr_edac_a10_device_add); 1986 1987 return 0; 1988 1989 err_release_group1: 1990 edac_device_free_ctl_info(dci); 1991 err_release_group: 1992 devres_release_group(edac->dev, NULL); 1993 edac_printk(KERN_ERR, EDAC_DEVICE, 1994 "%s:Error setting up EDAC device: %d\n", ecc_name, rc); 1995 1996 return rc; 1997 } 1998 1999 static void a10_eccmgr_irq_mask(struct irq_data *d) 2000 { 2001 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); 2002 2003 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, 2004 BIT(d->hwirq)); 2005 } 2006 2007 static void a10_eccmgr_irq_unmask(struct irq_data *d) 2008 { 2009 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); 2010 2011 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, 2012 BIT(d->hwirq)); 2013 } 2014 2015 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq, 2016 irq_hw_number_t hwirq) 2017 { 2018 struct altr_arria10_edac *edac = d->host_data; 2019 2020 irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq); 2021 irq_set_chip_data(irq, edac); 2022 irq_set_noprobe(irq); 2023 2024 return 0; 2025 } 2026 2027 static const struct irq_domain_ops a10_eccmgr_ic_ops = { 2028 .map = a10_eccmgr_irqdomain_map, 2029 .xlate = irq_domain_xlate_twocell, 2030 }; 2031 2032 /************** Stratix 10 EDAC Double Bit Error Handler ************/ 2033 #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m) 2034 2035 #ifdef CONFIG_ARCH_STRATIX10 2036 /* panic routine issues reboot on non-zero panic_timeout */ 2037 extern int panic_timeout; 2038 2039 /* 2040 * The double bit error is handled through SError which is fatal. This is 2041 * called as a panic notifier to printout ECC error info as part of the panic. 2042 */ 2043 static int s10_edac_dberr_handler(struct notifier_block *this, 2044 unsigned long event, void *ptr) 2045 { 2046 struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier); 2047 int err_addr, dberror; 2048 2049 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST, 2050 &dberror); 2051 regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror); 2052 if (dberror & S10_DBE_IRQ_MASK) { 2053 struct list_head *position; 2054 struct altr_edac_device_dev *ed; 2055 struct arm_smccc_res result; 2056 2057 /* Find the matching DBE in the list of devices */ 2058 list_for_each(position, &edac->a10_ecc_devices) { 2059 ed = list_entry(position, struct altr_edac_device_dev, 2060 next); 2061 if (!(BIT(ed->db_irq) & dberror)) 2062 continue; 2063 2064 writel(ALTR_A10_ECC_DERRPENA, 2065 ed->base + ALTR_A10_ECC_INTSTAT_OFST); 2066 err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST); 2067 regmap_write(edac->ecc_mgr_map, 2068 S10_SYSMGR_UE_ADDR_OFST, err_addr); 2069 edac_printk(KERN_ERR, EDAC_DEVICE, 2070 "EDAC: [Fatal DBE on %s @ 0x%08X]\n", 2071 ed->edac_dev_name, err_addr); 2072 break; 2073 } 2074 /* Notify the System through SMC. Reboot delay = 1 second */ 2075 panic_timeout = 1; 2076 arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0, 2077 0, 0, &result); 2078 } 2079 2080 return NOTIFY_DONE; 2081 } 2082 #endif 2083 2084 /****************** Arria 10 EDAC Probe Function *********************/ 2085 static int altr_edac_a10_probe(struct platform_device *pdev) 2086 { 2087 struct altr_arria10_edac *edac; 2088 struct device_node *child; 2089 2090 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL); 2091 if (!edac) 2092 return -ENOMEM; 2093 2094 edac->dev = &pdev->dev; 2095 platform_set_drvdata(pdev, edac); 2096 INIT_LIST_HEAD(&edac->a10_ecc_devices); 2097 2098 if (socfpga_is_a10()) { 2099 edac->ecc_mgr_map = 2100 syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 2101 "altr,sysmgr-syscon"); 2102 } else { 2103 struct device_node *sysmgr_np; 2104 struct resource res; 2105 uintptr_t base; 2106 2107 sysmgr_np = of_parse_phandle(pdev->dev.of_node, 2108 "altr,sysmgr-syscon", 0); 2109 if (!sysmgr_np) { 2110 edac_printk(KERN_ERR, EDAC_DEVICE, 2111 "Unable to find altr,sysmgr-syscon\n"); 2112 return -ENODEV; 2113 } 2114 2115 if (of_address_to_resource(sysmgr_np, 0, &res)) 2116 return -ENOMEM; 2117 2118 /* Need physical address for SMCC call */ 2119 base = res.start; 2120 2121 edac->ecc_mgr_map = devm_regmap_init(&pdev->dev, NULL, 2122 (void *)base, 2123 &s10_sdram_regmap_cfg); 2124 } 2125 2126 if (IS_ERR(edac->ecc_mgr_map)) { 2127 edac_printk(KERN_ERR, EDAC_DEVICE, 2128 "Unable to get syscon altr,sysmgr-syscon\n"); 2129 return PTR_ERR(edac->ecc_mgr_map); 2130 } 2131 2132 edac->irq_chip.name = pdev->dev.of_node->name; 2133 edac->irq_chip.irq_mask = a10_eccmgr_irq_mask; 2134 edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask; 2135 edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64, 2136 &a10_eccmgr_ic_ops, edac); 2137 if (!edac->domain) { 2138 dev_err(&pdev->dev, "Error adding IRQ domain\n"); 2139 return -ENOMEM; 2140 } 2141 2142 edac->sb_irq = platform_get_irq(pdev, 0); 2143 if (edac->sb_irq < 0) { 2144 dev_err(&pdev->dev, "No SBERR IRQ resource\n"); 2145 return edac->sb_irq; 2146 } 2147 2148 irq_set_chained_handler_and_data(edac->sb_irq, 2149 altr_edac_a10_irq_handler, 2150 edac); 2151 2152 #ifdef CONFIG_ARCH_STRATIX10 2153 { 2154 int dberror, err_addr; 2155 2156 edac->panic_notifier.notifier_call = s10_edac_dberr_handler; 2157 atomic_notifier_chain_register(&panic_notifier_list, 2158 &edac->panic_notifier); 2159 2160 /* Printout a message if uncorrectable error previously. */ 2161 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, 2162 &dberror); 2163 if (dberror) { 2164 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST, 2165 &err_addr); 2166 edac_printk(KERN_ERR, EDAC_DEVICE, 2167 "Previous Boot UE detected[0x%X] @ 0x%X\n", 2168 dberror, err_addr); 2169 /* Reset the sticky registers */ 2170 regmap_write(edac->ecc_mgr_map, 2171 S10_SYSMGR_UE_VAL_OFST, 0); 2172 regmap_write(edac->ecc_mgr_map, 2173 S10_SYSMGR_UE_ADDR_OFST, 0); 2174 } 2175 } 2176 #else 2177 edac->db_irq = platform_get_irq(pdev, 1); 2178 if (edac->db_irq < 0) { 2179 dev_err(&pdev->dev, "No DBERR IRQ resource\n"); 2180 return edac->db_irq; 2181 } 2182 irq_set_chained_handler_and_data(edac->db_irq, 2183 altr_edac_a10_irq_handler, edac); 2184 #endif 2185 2186 for_each_child_of_node(pdev->dev.of_node, child) { 2187 if (!of_device_is_available(child)) 2188 continue; 2189 2190 if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc") || 2191 of_device_is_compatible(child, "altr,socfpga-a10-ocram-ecc") || 2192 of_device_is_compatible(child, "altr,socfpga-eth-mac-ecc") || 2193 of_device_is_compatible(child, "altr,socfpga-nand-ecc") || 2194 of_device_is_compatible(child, "altr,socfpga-dma-ecc") || 2195 of_device_is_compatible(child, "altr,socfpga-usb-ecc") || 2196 of_device_is_compatible(child, "altr,socfpga-qspi-ecc") || 2197 of_device_is_compatible(child, "altr,socfpga-sdmmc-ecc")) 2198 2199 altr_edac_a10_device_add(edac, child); 2200 2201 #ifdef CONFIG_EDAC_ALTERA_SDRAM 2202 else if ((of_device_is_compatible(child, "altr,sdram-edac-a10")) || 2203 (of_device_is_compatible(child, "altr,sdram-edac-s10"))) 2204 of_platform_populate(pdev->dev.of_node, 2205 altr_sdram_ctrl_of_match, 2206 NULL, &pdev->dev); 2207 #endif 2208 } 2209 2210 return 0; 2211 } 2212 2213 static const struct of_device_id altr_edac_a10_of_match[] = { 2214 { .compatible = "altr,socfpga-a10-ecc-manager" }, 2215 { .compatible = "altr,socfpga-s10-ecc-manager" }, 2216 {}, 2217 }; 2218 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match); 2219 2220 static struct platform_driver altr_edac_a10_driver = { 2221 .probe = altr_edac_a10_probe, 2222 .driver = { 2223 .name = "socfpga_a10_ecc_manager", 2224 .of_match_table = altr_edac_a10_of_match, 2225 }, 2226 }; 2227 module_platform_driver(altr_edac_a10_driver); 2228 2229 MODULE_LICENSE("GPL v2"); 2230 MODULE_AUTHOR("Thor Thayer"); 2231 MODULE_DESCRIPTION("EDAC Driver for Altera Memories"); 2232