1 /* 2 * Copyright Altera Corporation (C) 2014-2016. All rights reserved. 3 * Copyright 2011-2012 Calxeda, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 * Adapted from the highbank_mc_edac driver. 18 */ 19 20 #include <asm/cacheflush.h> 21 #include <linux/ctype.h> 22 #include <linux/edac.h> 23 #include <linux/genalloc.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/mfd/syscon.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/regmap.h> 30 #include <linux/types.h> 31 #include <linux/uaccess.h> 32 33 #include "altera_edac.h" 34 #include "edac_core.h" 35 #include "edac_module.h" 36 37 #define EDAC_MOD_STR "altera_edac" 38 #define EDAC_VERSION "1" 39 #define EDAC_DEVICE "Altera" 40 41 static const struct altr_sdram_prv_data c5_data = { 42 .ecc_ctrl_offset = CV_CTLCFG_OFST, 43 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN, 44 .ecc_stat_offset = CV_DRAMSTS_OFST, 45 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR, 46 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR, 47 .ecc_saddr_offset = CV_ERRADDR_OFST, 48 .ecc_daddr_offset = CV_ERRADDR_OFST, 49 .ecc_cecnt_offset = CV_SBECOUNT_OFST, 50 .ecc_uecnt_offset = CV_DBECOUNT_OFST, 51 .ecc_irq_en_offset = CV_DRAMINTR_OFST, 52 .ecc_irq_en_mask = CV_DRAMINTR_INTREN, 53 .ecc_irq_clr_offset = CV_DRAMINTR_OFST, 54 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN), 55 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST, 56 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR, 57 .ce_ue_trgr_offset = CV_CTLCFG_OFST, 58 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR, 59 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR, 60 }; 61 62 static const struct altr_sdram_prv_data a10_data = { 63 .ecc_ctrl_offset = A10_ECCCTRL1_OFST, 64 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN, 65 .ecc_stat_offset = A10_INTSTAT_OFST, 66 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR, 67 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR, 68 .ecc_saddr_offset = A10_SERRADDR_OFST, 69 .ecc_daddr_offset = A10_DERRADDR_OFST, 70 .ecc_irq_en_offset = A10_ERRINTEN_OFST, 71 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK, 72 .ecc_irq_clr_offset = A10_INTSTAT_OFST, 73 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR), 74 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST, 75 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK, 76 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST, 77 .ce_set_mask = A10_DIAGINT_TSERRA_MASK, 78 .ue_set_mask = A10_DIAGINT_TDERRA_MASK, 79 }; 80 81 /************************** EDAC Device Defines **************************/ 82 83 /* OCRAM ECC Management Group Defines */ 84 #define ALTR_MAN_GRP_OCRAM_ECC_OFFSET 0x04 85 #define ALTR_OCR_ECC_EN BIT(0) 86 #define ALTR_OCR_ECC_INJS BIT(1) 87 #define ALTR_OCR_ECC_INJD BIT(2) 88 #define ALTR_OCR_ECC_SERR BIT(3) 89 #define ALTR_OCR_ECC_DERR BIT(4) 90 91 /* L2 ECC Management Group Defines */ 92 #define ALTR_MAN_GRP_L2_ECC_OFFSET 0x00 93 #define ALTR_L2_ECC_EN BIT(0) 94 #define ALTR_L2_ECC_INJS BIT(1) 95 #define ALTR_L2_ECC_INJD BIT(2) 96 97 #define ALTR_UE_TRIGGER_CHAR 'U' /* Trigger for UE */ 98 #define ALTR_TRIGGER_READ_WRD_CNT 32 /* Line size x 4 */ 99 #define ALTR_TRIG_OCRAM_BYTE_SIZE 128 /* Line size x 4 */ 100 #define ALTR_TRIG_L2C_BYTE_SIZE 4096 /* Full Page */ 101 102 /*********************** EDAC Memory Controller Functions ****************/ 103 104 /* The SDRAM controller uses the EDAC Memory Controller framework. */ 105 106 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id) 107 { 108 struct mem_ctl_info *mci = dev_id; 109 struct altr_sdram_mc_data *drvdata = mci->pvt_info; 110 const struct altr_sdram_prv_data *priv = drvdata->data; 111 u32 status, err_count = 1, err_addr; 112 113 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status); 114 115 if (status & priv->ecc_stat_ue_mask) { 116 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset, 117 &err_addr); 118 if (priv->ecc_uecnt_offset) 119 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset, 120 &err_count); 121 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n", 122 err_count, err_addr); 123 } 124 if (status & priv->ecc_stat_ce_mask) { 125 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, 126 &err_addr); 127 if (priv->ecc_uecnt_offset) 128 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset, 129 &err_count); 130 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count, 131 err_addr >> PAGE_SHIFT, 132 err_addr & ~PAGE_MASK, 0, 133 0, 0, -1, mci->ctl_name, ""); 134 /* Clear IRQ to resume */ 135 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset, 136 priv->ecc_irq_clr_mask); 137 138 return IRQ_HANDLED; 139 } 140 return IRQ_NONE; 141 } 142 143 static ssize_t altr_sdr_mc_err_inject_write(struct file *file, 144 const char __user *data, 145 size_t count, loff_t *ppos) 146 { 147 struct mem_ctl_info *mci = file->private_data; 148 struct altr_sdram_mc_data *drvdata = mci->pvt_info; 149 const struct altr_sdram_prv_data *priv = drvdata->data; 150 u32 *ptemp; 151 dma_addr_t dma_handle; 152 u32 reg, read_reg; 153 154 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL); 155 if (!ptemp) { 156 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); 157 edac_printk(KERN_ERR, EDAC_MC, 158 "Inject: Buffer Allocation error\n"); 159 return -ENOMEM; 160 } 161 162 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset, 163 &read_reg); 164 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask); 165 166 /* Error are injected by writing a word while the SBE or DBE 167 * bit in the CTLCFG register is set. Reading the word will 168 * trigger the SBE or DBE error and the corresponding IRQ. 169 */ 170 if (count == 3) { 171 edac_printk(KERN_ALERT, EDAC_MC, 172 "Inject Double bit error\n"); 173 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, 174 (read_reg | priv->ue_set_mask)); 175 } else { 176 edac_printk(KERN_ALERT, EDAC_MC, 177 "Inject Single bit error\n"); 178 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, 179 (read_reg | priv->ce_set_mask)); 180 } 181 182 ptemp[0] = 0x5A5A5A5A; 183 ptemp[1] = 0xA5A5A5A5; 184 185 /* Clear the error injection bits */ 186 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg); 187 /* Ensure it has been written out */ 188 wmb(); 189 190 /* 191 * To trigger the error, we need to read the data back 192 * (the data was written with errors above). 193 * The ACCESS_ONCE macros and printk are used to prevent the 194 * the compiler optimizing these reads out. 195 */ 196 reg = ACCESS_ONCE(ptemp[0]); 197 read_reg = ACCESS_ONCE(ptemp[1]); 198 /* Force Read */ 199 rmb(); 200 201 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n", 202 reg, read_reg); 203 204 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); 205 206 return count; 207 } 208 209 static const struct file_operations altr_sdr_mc_debug_inject_fops = { 210 .open = simple_open, 211 .write = altr_sdr_mc_err_inject_write, 212 .llseek = generic_file_llseek, 213 }; 214 215 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci) 216 { 217 if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) 218 return; 219 220 if (!mci->debugfs) 221 return; 222 223 edac_debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci, 224 &altr_sdr_mc_debug_inject_fops); 225 } 226 227 /* Get total memory size from Open Firmware DTB */ 228 static unsigned long get_total_mem(void) 229 { 230 struct device_node *np = NULL; 231 const unsigned int *reg, *reg_end; 232 int len, sw, aw; 233 unsigned long start, size, total_mem = 0; 234 235 for_each_node_by_type(np, "memory") { 236 aw = of_n_addr_cells(np); 237 sw = of_n_size_cells(np); 238 reg = (const unsigned int *)of_get_property(np, "reg", &len); 239 reg_end = reg + (len / sizeof(u32)); 240 241 total_mem = 0; 242 do { 243 start = of_read_number(reg, aw); 244 reg += aw; 245 size = of_read_number(reg, sw); 246 reg += sw; 247 total_mem += size; 248 } while (reg < reg_end); 249 } 250 edac_dbg(0, "total_mem 0x%lx\n", total_mem); 251 return total_mem; 252 } 253 254 static const struct of_device_id altr_sdram_ctrl_of_match[] = { 255 { .compatible = "altr,sdram-edac", .data = (void *)&c5_data}, 256 { .compatible = "altr,sdram-edac-a10", .data = (void *)&a10_data}, 257 {}, 258 }; 259 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match); 260 261 static int a10_init(struct regmap *mc_vbase) 262 { 263 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST, 264 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) { 265 edac_printk(KERN_ERR, EDAC_MC, 266 "Error setting SB IRQ mode\n"); 267 return -ENODEV; 268 } 269 270 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) { 271 edac_printk(KERN_ERR, EDAC_MC, 272 "Error setting trigger count\n"); 273 return -ENODEV; 274 } 275 276 return 0; 277 } 278 279 static int a10_unmask_irq(struct platform_device *pdev, u32 mask) 280 { 281 void __iomem *sm_base; 282 int ret = 0; 283 284 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32), 285 dev_name(&pdev->dev))) { 286 edac_printk(KERN_ERR, EDAC_MC, 287 "Unable to request mem region\n"); 288 return -EBUSY; 289 } 290 291 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32)); 292 if (!sm_base) { 293 edac_printk(KERN_ERR, EDAC_MC, 294 "Unable to ioremap device\n"); 295 296 ret = -ENOMEM; 297 goto release; 298 } 299 300 iowrite32(mask, sm_base); 301 302 iounmap(sm_base); 303 304 release: 305 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32)); 306 307 return ret; 308 } 309 310 static int altr_sdram_probe(struct platform_device *pdev) 311 { 312 const struct of_device_id *id; 313 struct edac_mc_layer layers[2]; 314 struct mem_ctl_info *mci; 315 struct altr_sdram_mc_data *drvdata; 316 const struct altr_sdram_prv_data *priv; 317 struct regmap *mc_vbase; 318 struct dimm_info *dimm; 319 u32 read_reg; 320 int irq, irq2, res = 0; 321 unsigned long mem_size, irqflags = 0; 322 323 id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev); 324 if (!id) 325 return -ENODEV; 326 327 /* Grab the register range from the sdr controller in device tree */ 328 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 329 "altr,sdr-syscon"); 330 if (IS_ERR(mc_vbase)) { 331 edac_printk(KERN_ERR, EDAC_MC, 332 "regmap for altr,sdr-syscon lookup failed.\n"); 333 return -ENODEV; 334 } 335 336 /* Check specific dependencies for the module */ 337 priv = of_match_node(altr_sdram_ctrl_of_match, 338 pdev->dev.of_node)->data; 339 340 /* Validate the SDRAM controller has ECC enabled */ 341 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) || 342 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) { 343 edac_printk(KERN_ERR, EDAC_MC, 344 "No ECC/ECC disabled [0x%08X]\n", read_reg); 345 return -ENODEV; 346 } 347 348 /* Grab memory size from device tree. */ 349 mem_size = get_total_mem(); 350 if (!mem_size) { 351 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n"); 352 return -ENODEV; 353 } 354 355 /* Ensure the SDRAM Interrupt is disabled */ 356 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset, 357 priv->ecc_irq_en_mask, 0)) { 358 edac_printk(KERN_ERR, EDAC_MC, 359 "Error disabling SDRAM ECC IRQ\n"); 360 return -ENODEV; 361 } 362 363 /* Toggle to clear the SDRAM Error count */ 364 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, 365 priv->ecc_cnt_rst_mask, 366 priv->ecc_cnt_rst_mask)) { 367 edac_printk(KERN_ERR, EDAC_MC, 368 "Error clearing SDRAM ECC count\n"); 369 return -ENODEV; 370 } 371 372 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, 373 priv->ecc_cnt_rst_mask, 0)) { 374 edac_printk(KERN_ERR, EDAC_MC, 375 "Error clearing SDRAM ECC count\n"); 376 return -ENODEV; 377 } 378 379 irq = platform_get_irq(pdev, 0); 380 if (irq < 0) { 381 edac_printk(KERN_ERR, EDAC_MC, 382 "No irq %d in DT\n", irq); 383 return -ENODEV; 384 } 385 386 /* Arria10 has a 2nd IRQ */ 387 irq2 = platform_get_irq(pdev, 1); 388 389 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 390 layers[0].size = 1; 391 layers[0].is_virt_csrow = true; 392 layers[1].type = EDAC_MC_LAYER_CHANNEL; 393 layers[1].size = 1; 394 layers[1].is_virt_csrow = false; 395 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 396 sizeof(struct altr_sdram_mc_data)); 397 if (!mci) 398 return -ENOMEM; 399 400 mci->pdev = &pdev->dev; 401 drvdata = mci->pvt_info; 402 drvdata->mc_vbase = mc_vbase; 403 drvdata->data = priv; 404 platform_set_drvdata(pdev, mci); 405 406 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { 407 edac_printk(KERN_ERR, EDAC_MC, 408 "Unable to get managed device resource\n"); 409 res = -ENOMEM; 410 goto free; 411 } 412 413 mci->mtype_cap = MEM_FLAG_DDR3; 414 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 415 mci->edac_cap = EDAC_FLAG_SECDED; 416 mci->mod_name = EDAC_MOD_STR; 417 mci->mod_ver = EDAC_VERSION; 418 mci->ctl_name = dev_name(&pdev->dev); 419 mci->scrub_mode = SCRUB_SW_SRC; 420 mci->dev_name = dev_name(&pdev->dev); 421 422 dimm = *mci->dimms; 423 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1; 424 dimm->grain = 8; 425 dimm->dtype = DEV_X8; 426 dimm->mtype = MEM_DDR3; 427 dimm->edac_mode = EDAC_SECDED; 428 429 res = edac_mc_add_mc(mci); 430 if (res < 0) 431 goto err; 432 433 /* Only the Arria10 has separate IRQs */ 434 if (irq2 > 0) { 435 /* Arria10 specific initialization */ 436 res = a10_init(mc_vbase); 437 if (res < 0) 438 goto err2; 439 440 res = devm_request_irq(&pdev->dev, irq2, 441 altr_sdram_mc_err_handler, 442 IRQF_SHARED, dev_name(&pdev->dev), mci); 443 if (res < 0) { 444 edac_mc_printk(mci, KERN_ERR, 445 "Unable to request irq %d\n", irq2); 446 res = -ENODEV; 447 goto err2; 448 } 449 450 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK); 451 if (res < 0) 452 goto err2; 453 454 irqflags = IRQF_SHARED; 455 } 456 457 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler, 458 irqflags, dev_name(&pdev->dev), mci); 459 if (res < 0) { 460 edac_mc_printk(mci, KERN_ERR, 461 "Unable to request irq %d\n", irq); 462 res = -ENODEV; 463 goto err2; 464 } 465 466 /* Infrastructure ready - enable the IRQ */ 467 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset, 468 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) { 469 edac_mc_printk(mci, KERN_ERR, 470 "Error enabling SDRAM ECC IRQ\n"); 471 res = -ENODEV; 472 goto err2; 473 } 474 475 altr_sdr_mc_create_debugfs_nodes(mci); 476 477 devres_close_group(&pdev->dev, NULL); 478 479 return 0; 480 481 err2: 482 edac_mc_del_mc(&pdev->dev); 483 err: 484 devres_release_group(&pdev->dev, NULL); 485 free: 486 edac_mc_free(mci); 487 edac_printk(KERN_ERR, EDAC_MC, 488 "EDAC Probe Failed; Error %d\n", res); 489 490 return res; 491 } 492 493 static int altr_sdram_remove(struct platform_device *pdev) 494 { 495 struct mem_ctl_info *mci = platform_get_drvdata(pdev); 496 497 edac_mc_del_mc(&pdev->dev); 498 edac_mc_free(mci); 499 platform_set_drvdata(pdev, NULL); 500 501 return 0; 502 } 503 504 /* 505 * If you want to suspend, need to disable EDAC by removing it 506 * from the device tree or defconfig. 507 */ 508 #ifdef CONFIG_PM 509 static int altr_sdram_prepare(struct device *dev) 510 { 511 pr_err("Suspend not allowed when EDAC is enabled.\n"); 512 513 return -EPERM; 514 } 515 516 static const struct dev_pm_ops altr_sdram_pm_ops = { 517 .prepare = altr_sdram_prepare, 518 }; 519 #endif 520 521 static struct platform_driver altr_sdram_edac_driver = { 522 .probe = altr_sdram_probe, 523 .remove = altr_sdram_remove, 524 .driver = { 525 .name = "altr_sdram_edac", 526 #ifdef CONFIG_PM 527 .pm = &altr_sdram_pm_ops, 528 #endif 529 .of_match_table = altr_sdram_ctrl_of_match, 530 }, 531 }; 532 533 module_platform_driver(altr_sdram_edac_driver); 534 535 /************************* EDAC Parent Probe *************************/ 536 537 static const struct of_device_id altr_edac_device_of_match[]; 538 539 static const struct of_device_id altr_edac_of_match[] = { 540 { .compatible = "altr,socfpga-ecc-manager" }, 541 {}, 542 }; 543 MODULE_DEVICE_TABLE(of, altr_edac_of_match); 544 545 static int altr_edac_probe(struct platform_device *pdev) 546 { 547 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match, 548 NULL, &pdev->dev); 549 return 0; 550 } 551 552 static struct platform_driver altr_edac_driver = { 553 .probe = altr_edac_probe, 554 .driver = { 555 .name = "socfpga_ecc_manager", 556 .of_match_table = altr_edac_of_match, 557 }, 558 }; 559 module_platform_driver(altr_edac_driver); 560 561 /************************* EDAC Device Functions *************************/ 562 563 /* 564 * EDAC Device Functions (shared between various IPs). 565 * The discrete memories use the EDAC Device framework. The probe 566 * and error handling functions are very similar between memories 567 * so they are shared. The memory allocation and freeing for EDAC 568 * trigger testing are different for each memory. 569 */ 570 571 const struct edac_device_prv_data ocramecc_data; 572 const struct edac_device_prv_data l2ecc_data; 573 574 struct edac_device_prv_data { 575 int (*setup)(struct platform_device *pdev, void __iomem *base); 576 int ce_clear_mask; 577 int ue_clear_mask; 578 char dbgfs_name[20]; 579 void * (*alloc_mem)(size_t size, void **other); 580 void (*free_mem)(void *p, size_t size, void *other); 581 int ecc_enable_mask; 582 int ce_set_mask; 583 int ue_set_mask; 584 int trig_alloc_sz; 585 }; 586 587 struct altr_edac_device_dev { 588 void __iomem *base; 589 int sb_irq; 590 int db_irq; 591 const struct edac_device_prv_data *data; 592 struct dentry *debugfs_dir; 593 char *edac_dev_name; 594 }; 595 596 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id) 597 { 598 irqreturn_t ret_value = IRQ_NONE; 599 struct edac_device_ctl_info *dci = dev_id; 600 struct altr_edac_device_dev *drvdata = dci->pvt_info; 601 const struct edac_device_prv_data *priv = drvdata->data; 602 603 if (irq == drvdata->sb_irq) { 604 if (priv->ce_clear_mask) 605 writel(priv->ce_clear_mask, drvdata->base); 606 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name); 607 ret_value = IRQ_HANDLED; 608 } else if (irq == drvdata->db_irq) { 609 if (priv->ue_clear_mask) 610 writel(priv->ue_clear_mask, drvdata->base); 611 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name); 612 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); 613 ret_value = IRQ_HANDLED; 614 } else { 615 WARN_ON(1); 616 } 617 618 return ret_value; 619 } 620 621 static ssize_t altr_edac_device_trig(struct file *file, 622 const char __user *user_buf, 623 size_t count, loff_t *ppos) 624 625 { 626 u32 *ptemp, i, error_mask; 627 int result = 0; 628 u8 trig_type; 629 unsigned long flags; 630 struct edac_device_ctl_info *edac_dci = file->private_data; 631 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 632 const struct edac_device_prv_data *priv = drvdata->data; 633 void *generic_ptr = edac_dci->dev; 634 635 if (!user_buf || get_user(trig_type, user_buf)) 636 return -EFAULT; 637 638 if (!priv->alloc_mem) 639 return -ENOMEM; 640 641 /* 642 * Note that generic_ptr is initialized to the device * but in 643 * some alloc_functions, this is overridden and returns data. 644 */ 645 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr); 646 if (!ptemp) { 647 edac_printk(KERN_ERR, EDAC_DEVICE, 648 "Inject: Buffer Allocation error\n"); 649 return -ENOMEM; 650 } 651 652 if (trig_type == ALTR_UE_TRIGGER_CHAR) 653 error_mask = priv->ue_set_mask; 654 else 655 error_mask = priv->ce_set_mask; 656 657 edac_printk(KERN_ALERT, EDAC_DEVICE, 658 "Trigger Error Mask (0x%X)\n", error_mask); 659 660 local_irq_save(flags); 661 /* write ECC corrupted data out. */ 662 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) { 663 /* Read data so we're in the correct state */ 664 rmb(); 665 if (ACCESS_ONCE(ptemp[i])) 666 result = -1; 667 /* Toggle Error bit (it is latched), leave ECC enabled */ 668 writel(error_mask, drvdata->base); 669 writel(priv->ecc_enable_mask, drvdata->base); 670 ptemp[i] = i; 671 } 672 /* Ensure it has been written out */ 673 wmb(); 674 local_irq_restore(flags); 675 676 if (result) 677 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n"); 678 679 /* Read out written data. ECC error caused here */ 680 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++) 681 if (ACCESS_ONCE(ptemp[i]) != i) 682 edac_printk(KERN_ERR, EDAC_DEVICE, 683 "Read doesn't match written data\n"); 684 685 if (priv->free_mem) 686 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr); 687 688 return count; 689 } 690 691 static const struct file_operations altr_edac_device_inject_fops = { 692 .open = simple_open, 693 .write = altr_edac_device_trig, 694 .llseek = generic_file_llseek, 695 }; 696 697 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci, 698 const struct edac_device_prv_data *priv) 699 { 700 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 701 702 if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) 703 return; 704 705 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name); 706 if (!drvdata->debugfs_dir) 707 return; 708 709 if (!edac_debugfs_create_file(priv->dbgfs_name, S_IWUSR, 710 drvdata->debugfs_dir, edac_dci, 711 &altr_edac_device_inject_fops)) 712 debugfs_remove_recursive(drvdata->debugfs_dir); 713 } 714 715 static const struct of_device_id altr_edac_device_of_match[] = { 716 #ifdef CONFIG_EDAC_ALTERA_L2C 717 { .compatible = "altr,socfpga-l2-ecc", .data = (void *)&l2ecc_data }, 718 #endif 719 #ifdef CONFIG_EDAC_ALTERA_OCRAM 720 { .compatible = "altr,socfpga-ocram-ecc", 721 .data = (void *)&ocramecc_data }, 722 #endif 723 {}, 724 }; 725 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match); 726 727 /* 728 * altr_edac_device_probe() 729 * This is a generic EDAC device driver that will support 730 * various Altera memory devices such as the L2 cache ECC and 731 * OCRAM ECC as well as the memories for other peripherals. 732 * Module specific initialization is done by passing the 733 * function index in the device tree. 734 */ 735 static int altr_edac_device_probe(struct platform_device *pdev) 736 { 737 struct edac_device_ctl_info *dci; 738 struct altr_edac_device_dev *drvdata; 739 struct resource *r; 740 int res = 0; 741 struct device_node *np = pdev->dev.of_node; 742 char *ecc_name = (char *)np->name; 743 static int dev_instance; 744 745 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { 746 edac_printk(KERN_ERR, EDAC_DEVICE, 747 "Unable to open devm\n"); 748 return -ENOMEM; 749 } 750 751 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 752 if (!r) { 753 edac_printk(KERN_ERR, EDAC_DEVICE, 754 "Unable to get mem resource\n"); 755 res = -ENODEV; 756 goto fail; 757 } 758 759 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r), 760 dev_name(&pdev->dev))) { 761 edac_printk(KERN_ERR, EDAC_DEVICE, 762 "%s:Error requesting mem region\n", ecc_name); 763 res = -EBUSY; 764 goto fail; 765 } 766 767 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name, 768 1, ecc_name, 1, 0, NULL, 0, 769 dev_instance++); 770 771 if (!dci) { 772 edac_printk(KERN_ERR, EDAC_DEVICE, 773 "%s: Unable to allocate EDAC device\n", ecc_name); 774 res = -ENOMEM; 775 goto fail; 776 } 777 778 drvdata = dci->pvt_info; 779 dci->dev = &pdev->dev; 780 platform_set_drvdata(pdev, dci); 781 drvdata->edac_dev_name = ecc_name; 782 783 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); 784 if (!drvdata->base) 785 goto fail1; 786 787 /* Get driver specific data for this EDAC device */ 788 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data; 789 790 /* Check specific dependencies for the module */ 791 if (drvdata->data->setup) { 792 res = drvdata->data->setup(pdev, drvdata->base); 793 if (res) 794 goto fail1; 795 } 796 797 drvdata->sb_irq = platform_get_irq(pdev, 0); 798 res = devm_request_irq(&pdev->dev, drvdata->sb_irq, 799 altr_edac_device_handler, 800 0, dev_name(&pdev->dev), dci); 801 if (res) 802 goto fail1; 803 804 drvdata->db_irq = platform_get_irq(pdev, 1); 805 res = devm_request_irq(&pdev->dev, drvdata->db_irq, 806 altr_edac_device_handler, 807 0, dev_name(&pdev->dev), dci); 808 if (res) 809 goto fail1; 810 811 dci->mod_name = "Altera ECC Manager"; 812 dci->dev_name = drvdata->edac_dev_name; 813 814 res = edac_device_add_device(dci); 815 if (res) 816 goto fail1; 817 818 altr_create_edacdev_dbgfs(dci, drvdata->data); 819 820 devres_close_group(&pdev->dev, NULL); 821 822 return 0; 823 824 fail1: 825 edac_device_free_ctl_info(dci); 826 fail: 827 devres_release_group(&pdev->dev, NULL); 828 edac_printk(KERN_ERR, EDAC_DEVICE, 829 "%s:Error setting up EDAC device: %d\n", ecc_name, res); 830 831 return res; 832 } 833 834 static int altr_edac_device_remove(struct platform_device *pdev) 835 { 836 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev); 837 struct altr_edac_device_dev *drvdata = dci->pvt_info; 838 839 debugfs_remove_recursive(drvdata->debugfs_dir); 840 edac_device_del_device(&pdev->dev); 841 edac_device_free_ctl_info(dci); 842 843 return 0; 844 } 845 846 static struct platform_driver altr_edac_device_driver = { 847 .probe = altr_edac_device_probe, 848 .remove = altr_edac_device_remove, 849 .driver = { 850 .name = "altr_edac_device", 851 .of_match_table = altr_edac_device_of_match, 852 }, 853 }; 854 module_platform_driver(altr_edac_device_driver); 855 856 /*********************** OCRAM EDAC Device Functions *********************/ 857 858 #ifdef CONFIG_EDAC_ALTERA_OCRAM 859 860 static void *ocram_alloc_mem(size_t size, void **other) 861 { 862 struct device_node *np; 863 struct gen_pool *gp; 864 void *sram_addr; 865 866 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); 867 if (!np) 868 return NULL; 869 870 gp = of_gen_pool_get(np, "iram", 0); 871 of_node_put(np); 872 if (!gp) 873 return NULL; 874 875 sram_addr = (void *)gen_pool_alloc(gp, size); 876 if (!sram_addr) 877 return NULL; 878 879 memset(sram_addr, 0, size); 880 /* Ensure data is written out */ 881 wmb(); 882 883 /* Remember this handle for freeing later */ 884 *other = gp; 885 886 return sram_addr; 887 } 888 889 static void ocram_free_mem(void *p, size_t size, void *other) 890 { 891 gen_pool_free((struct gen_pool *)other, (u32)p, size); 892 } 893 894 /* 895 * altr_ocram_check_deps() 896 * Test for OCRAM cache ECC dependencies upon entry because 897 * platform specific startup should have initialized the 898 * On-Chip RAM memory and enabled the ECC. 899 * Can't turn on ECC here because accessing un-initialized 900 * memory will cause CE/UE errors possibly causing an ABORT. 901 */ 902 static int altr_ocram_check_deps(struct platform_device *pdev, 903 void __iomem *base) 904 { 905 if (readl(base) & ALTR_OCR_ECC_EN) 906 return 0; 907 908 edac_printk(KERN_ERR, EDAC_DEVICE, 909 "OCRAM: No ECC present or ECC disabled.\n"); 910 return -ENODEV; 911 } 912 913 const struct edac_device_prv_data ocramecc_data = { 914 .setup = altr_ocram_check_deps, 915 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR), 916 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR), 917 .dbgfs_name = "altr_ocram_trigger", 918 .alloc_mem = ocram_alloc_mem, 919 .free_mem = ocram_free_mem, 920 .ecc_enable_mask = ALTR_OCR_ECC_EN, 921 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS), 922 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD), 923 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE, 924 }; 925 926 #endif /* CONFIG_EDAC_ALTERA_OCRAM */ 927 928 /********************* L2 Cache EDAC Device Functions ********************/ 929 930 #ifdef CONFIG_EDAC_ALTERA_L2C 931 932 static void *l2_alloc_mem(size_t size, void **other) 933 { 934 struct device *dev = *other; 935 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL); 936 937 if (!ptemp) 938 return NULL; 939 940 /* Make sure everything is written out */ 941 wmb(); 942 943 /* 944 * Clean all cache levels up to LoC (includes L2) 945 * This ensures the corrupted data is written into 946 * L2 cache for readback test (which causes ECC error). 947 */ 948 flush_cache_all(); 949 950 return ptemp; 951 } 952 953 static void l2_free_mem(void *p, size_t size, void *other) 954 { 955 struct device *dev = other; 956 957 if (dev && p) 958 devm_kfree(dev, p); 959 } 960 961 /* 962 * altr_l2_check_deps() 963 * Test for L2 cache ECC dependencies upon entry because 964 * platform specific startup should have initialized the L2 965 * memory and enabled the ECC. 966 * Bail if ECC is not enabled. 967 * Note that L2 Cache Enable is forced at build time. 968 */ 969 static int altr_l2_check_deps(struct platform_device *pdev, 970 void __iomem *base) 971 { 972 if (readl(base) & ALTR_L2_ECC_EN) 973 return 0; 974 975 edac_printk(KERN_ERR, EDAC_DEVICE, 976 "L2: No ECC present, or ECC disabled\n"); 977 return -ENODEV; 978 } 979 980 const struct edac_device_prv_data l2ecc_data = { 981 .setup = altr_l2_check_deps, 982 .ce_clear_mask = 0, 983 .ue_clear_mask = 0, 984 .dbgfs_name = "altr_l2_trigger", 985 .alloc_mem = l2_alloc_mem, 986 .free_mem = l2_free_mem, 987 .ecc_enable_mask = ALTR_L2_ECC_EN, 988 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS), 989 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD), 990 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, 991 }; 992 993 #endif /* CONFIG_EDAC_ALTERA_L2C */ 994 995 MODULE_LICENSE("GPL v2"); 996 MODULE_AUTHOR("Thor Thayer"); 997 MODULE_DESCRIPTION("EDAC Driver for Altera Memories"); 998