1# 2# EDAC Kconfig 3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com 4# Licensed and distributed under the GPL 5 6config EDAC_ATOMIC_SCRUB 7 bool 8 9config EDAC_SUPPORT 10 bool 11 12menuconfig EDAC 13 bool "EDAC (Error Detection And Correction) reporting" 14 depends on HAS_IOMEM && EDAC_SUPPORT 15 help 16 EDAC is designed to report errors in the core system. 17 These are low-level errors that are reported in the CPU or 18 supporting chipset or other subsystems: 19 memory errors, cache errors, PCI errors, thermal throttling, etc.. 20 If unsure, select 'Y'. 21 22 If this code is reporting problems on your system, please 23 see the EDAC project web pages for more information at: 24 25 <http://bluesmoke.sourceforge.net/> 26 27 and: 28 29 <http://buttersideup.com/edacwiki> 30 31 There is also a mailing list for the EDAC project, which can 32 be found via the sourceforge page. 33 34if EDAC 35 36config EDAC_LEGACY_SYSFS 37 bool "EDAC legacy sysfs" 38 default y 39 help 40 Enable the compatibility sysfs nodes. 41 Use 'Y' if your edac utilities aren't ported to work with the newer 42 structures. 43 44config EDAC_DEBUG 45 bool "Debugging" 46 select DEBUG_FS 47 help 48 This turns on debugging information for the entire EDAC subsystem. 49 You do so by inserting edac_module with "edac_debug_level=x." Valid 50 levels are 0-4 (from low to high) and by default it is set to 2. 51 Usually you should select 'N' here. 52 53config EDAC_DECODE_MCE 54 tristate "Decode MCEs in human-readable form (only on AMD for now)" 55 depends on CPU_SUP_AMD && X86_MCE_AMD 56 default y 57 ---help--- 58 Enable this option if you want to decode Machine Check Exceptions 59 occurring on your machine in human-readable form. 60 61 You should definitely say Y here in case you want to decode MCEs 62 which occur really early upon boot, before the module infrastructure 63 has been initialized. 64 65config EDAC_MM_EDAC 66 tristate "Main Memory EDAC (Error Detection And Correction) reporting" 67 select RAS 68 help 69 Some systems are able to detect and correct errors in main 70 memory. EDAC can report statistics on memory error 71 detection and correction (EDAC - or commonly referred to ECC 72 errors). EDAC will also try to decode where these errors 73 occurred so that a particular failing memory module can be 74 replaced. If unsure, select 'Y'. 75 76config EDAC_GHES 77 bool "Output ACPI APEI/GHES BIOS detected errors via EDAC" 78 depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y) 79 default y 80 help 81 Not all machines support hardware-driven error report. Some of those 82 provide a BIOS-driven error report mechanism via ACPI, using the 83 APEI/GHES driver. By enabling this option, the error reports provided 84 by GHES are sent to userspace via the EDAC API. 85 86 When this option is enabled, it will disable the hardware-driven 87 mechanisms, if a GHES BIOS is detected, entering into the 88 "Firmware First" mode. 89 90 It should be noticed that keeping both GHES and a hardware-driven 91 error mechanism won't work well, as BIOS will race with OS, while 92 reading the error registers. So, if you want to not use "Firmware 93 first" GHES error mechanism, you should disable GHES either at 94 compilation time or by passing "ghes.disable=1" Kernel parameter 95 at boot time. 96 97 In doubt, say 'Y'. 98 99config EDAC_AMD64 100 tristate "AMD64 (Opteron, Athlon64)" 101 depends on EDAC_MM_EDAC && AMD_NB && EDAC_DECODE_MCE 102 help 103 Support for error detection and correction of DRAM ECC errors on 104 the AMD64 families (>= K8) of memory controllers. 105 106config EDAC_AMD64_ERROR_INJECTION 107 bool "Sysfs HW Error injection facilities" 108 depends on EDAC_AMD64 109 help 110 Recent Opterons (Family 10h and later) provide for Memory Error 111 Injection into the ECC detection circuits. The amd64_edac module 112 allows the operator/user to inject Uncorrectable and Correctable 113 errors into DRAM. 114 115 When enabled, in each of the respective memory controller directories 116 (/sys/devices/system/edac/mc/mcX), there are 3 input files: 117 118 - inject_section (0..3, 16-byte section of 64-byte cacheline), 119 - inject_word (0..8, 16-bit word of 16-byte section), 120 - inject_ecc_vector (hex ecc vector: select bits of inject word) 121 122 In addition, there are two control files, inject_read and inject_write, 123 which trigger the DRAM ECC Read and Write respectively. 124 125config EDAC_AMD76X 126 tristate "AMD 76x (760, 762, 768)" 127 depends on EDAC_MM_EDAC && PCI && X86_32 128 help 129 Support for error detection and correction on the AMD 76x 130 series of chipsets used with the Athlon processor. 131 132config EDAC_E7XXX 133 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" 134 depends on EDAC_MM_EDAC && PCI && X86_32 135 help 136 Support for error detection and correction on the Intel 137 E7205, E7500, E7501 and E7505 server chipsets. 138 139config EDAC_E752X 140 tristate "Intel e752x (e7520, e7525, e7320) and 3100" 141 depends on EDAC_MM_EDAC && PCI && X86 142 help 143 Support for error detection and correction on the Intel 144 E7520, E7525, E7320 server chipsets. 145 146config EDAC_I82443BXGX 147 tristate "Intel 82443BX/GX (440BX/GX)" 148 depends on EDAC_MM_EDAC && PCI && X86_32 149 depends on BROKEN 150 help 151 Support for error detection and correction on the Intel 152 82443BX/GX memory controllers (440BX/GX chipsets). 153 154config EDAC_I82875P 155 tristate "Intel 82875p (D82875P, E7210)" 156 depends on EDAC_MM_EDAC && PCI && X86_32 157 help 158 Support for error detection and correction on the Intel 159 DP82785P and E7210 server chipsets. 160 161config EDAC_I82975X 162 tristate "Intel 82975x (D82975x)" 163 depends on EDAC_MM_EDAC && PCI && X86 164 help 165 Support for error detection and correction on the Intel 166 DP82975x server chipsets. 167 168config EDAC_I3000 169 tristate "Intel 3000/3010" 170 depends on EDAC_MM_EDAC && PCI && X86 171 help 172 Support for error detection and correction on the Intel 173 3000 and 3010 server chipsets. 174 175config EDAC_I3200 176 tristate "Intel 3200" 177 depends on EDAC_MM_EDAC && PCI && X86 178 help 179 Support for error detection and correction on the Intel 180 3200 and 3210 server chipsets. 181 182config EDAC_IE31200 183 tristate "Intel e312xx" 184 depends on EDAC_MM_EDAC && PCI && X86 185 help 186 Support for error detection and correction on the Intel 187 E3-1200 based DRAM controllers. 188 189config EDAC_X38 190 tristate "Intel X38" 191 depends on EDAC_MM_EDAC && PCI && X86 192 help 193 Support for error detection and correction on the Intel 194 X38 server chipsets. 195 196config EDAC_I5400 197 tristate "Intel 5400 (Seaburg) chipsets" 198 depends on EDAC_MM_EDAC && PCI && X86 199 help 200 Support for error detection and correction the Intel 201 i5400 MCH chipset (Seaburg). 202 203config EDAC_I7CORE 204 tristate "Intel i7 Core (Nehalem) processors" 205 depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL 206 help 207 Support for error detection and correction the Intel 208 i7 Core (Nehalem) Integrated Memory Controller that exists on 209 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx 210 and Xeon 55xx processors. 211 212config EDAC_I82860 213 tristate "Intel 82860" 214 depends on EDAC_MM_EDAC && PCI && X86_32 215 help 216 Support for error detection and correction on the Intel 217 82860 chipset. 218 219config EDAC_R82600 220 tristate "Radisys 82600 embedded chipset" 221 depends on EDAC_MM_EDAC && PCI && X86_32 222 help 223 Support for error detection and correction on the Radisys 224 82600 embedded chipset. 225 226config EDAC_I5000 227 tristate "Intel Greencreek/Blackford chipset" 228 depends on EDAC_MM_EDAC && X86 && PCI 229 help 230 Support for error detection and correction the Intel 231 Greekcreek/Blackford chipsets. 232 233config EDAC_I5100 234 tristate "Intel San Clemente MCH" 235 depends on EDAC_MM_EDAC && X86 && PCI 236 help 237 Support for error detection and correction the Intel 238 San Clemente MCH. 239 240config EDAC_I7300 241 tristate "Intel Clarksboro MCH" 242 depends on EDAC_MM_EDAC && X86 && PCI 243 help 244 Support for error detection and correction the Intel 245 Clarksboro MCH (Intel 7300 chipset). 246 247config EDAC_SBRIDGE 248 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" 249 depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL 250 depends on PCI_MMCONFIG 251 help 252 Support for error detection and correction the Intel 253 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. 254 255config EDAC_SKX 256 tristate "Intel Skylake server Integrated MC" 257 depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL 258 depends on PCI_MMCONFIG 259 help 260 Support for error detection and correction the Intel 261 Skylake server Integrated Memory Controllers. 262 263config EDAC_PND2 264 tristate "Intel Pondicherry2" 265 depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL 266 help 267 Support for error detection and correction on the Intel 268 Pondicherry2 Integrated Memory Controller. This SoC IP is 269 first used on the Apollo Lake platform and Denverton 270 micro-server but may appear on others in the future. 271 272config EDAC_MPC85XX 273 tristate "Freescale MPC83xx / MPC85xx" 274 depends on EDAC_MM_EDAC && FSL_SOC 275 help 276 Support for error detection and correction on the Freescale 277 MPC8349, MPC8560, MPC8540, MPC8548, T4240 278 279config EDAC_LAYERSCAPE 280 tristate "Freescale Layerscape DDR" 281 depends on EDAC_MM_EDAC && ARCH_LAYERSCAPE 282 help 283 Support for error detection and correction on Freescale memory 284 controllers on Layerscape SoCs. 285 286config EDAC_MV64X60 287 tristate "Marvell MV64x60" 288 depends on EDAC_MM_EDAC && MV64X60 289 help 290 Support for error detection and correction on the Marvell 291 MV64360 and MV64460 chipsets. 292 293config EDAC_PASEMI 294 tristate "PA Semi PWRficient" 295 depends on EDAC_MM_EDAC && PCI 296 depends on PPC_PASEMI 297 help 298 Support for error detection and correction on PA Semi 299 PWRficient. 300 301config EDAC_CELL 302 tristate "Cell Broadband Engine memory controller" 303 depends on EDAC_MM_EDAC && PPC_CELL_COMMON 304 help 305 Support for error detection and correction on the 306 Cell Broadband Engine internal memory controller 307 on platform without a hypervisor 308 309config EDAC_PPC4XX 310 tristate "PPC4xx IBM DDR2 Memory Controller" 311 depends on EDAC_MM_EDAC && 4xx 312 help 313 This enables support for EDAC on the ECC memory used 314 with the IBM DDR2 memory controller found in various 315 PowerPC 4xx embedded processors such as the 405EX[r], 316 440SP, 440SPe, 460EX, 460GT and 460SX. 317 318config EDAC_AMD8131 319 tristate "AMD8131 HyperTransport PCI-X Tunnel" 320 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE 321 help 322 Support for error detection and correction on the 323 AMD8131 HyperTransport PCI-X Tunnel chip. 324 Note, add more Kconfig dependency if it's adopted 325 on some machine other than Maple. 326 327config EDAC_AMD8111 328 tristate "AMD8111 HyperTransport I/O Hub" 329 depends on EDAC_MM_EDAC && PCI && PPC_MAPLE 330 help 331 Support for error detection and correction on the 332 AMD8111 HyperTransport I/O Hub chip. 333 Note, add more Kconfig dependency if it's adopted 334 on some machine other than Maple. 335 336config EDAC_CPC925 337 tristate "IBM CPC925 Memory Controller (PPC970FX)" 338 depends on EDAC_MM_EDAC && PPC64 339 help 340 Support for error detection and correction on the 341 IBM CPC925 Bridge and Memory Controller, which is 342 a companion chip to the PowerPC 970 family of 343 processors. 344 345config EDAC_TILE 346 tristate "Tilera Memory Controller" 347 depends on EDAC_MM_EDAC && TILE 348 default y 349 help 350 Support for error detection and correction on the 351 Tilera memory controller. 352 353config EDAC_HIGHBANK_MC 354 tristate "Highbank Memory Controller" 355 depends on EDAC_MM_EDAC && ARCH_HIGHBANK 356 help 357 Support for error detection and correction on the 358 Calxeda Highbank memory controller. 359 360config EDAC_HIGHBANK_L2 361 tristate "Highbank L2 Cache" 362 depends on EDAC_MM_EDAC && ARCH_HIGHBANK 363 help 364 Support for error detection and correction on the 365 Calxeda Highbank memory controller. 366 367config EDAC_OCTEON_PC 368 tristate "Cavium Octeon Primary Caches" 369 depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON 370 help 371 Support for error detection and correction on the primary caches of 372 the cnMIPS cores of Cavium Octeon family SOCs. 373 374config EDAC_OCTEON_L2C 375 tristate "Cavium Octeon Secondary Caches (L2C)" 376 depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC 377 help 378 Support for error detection and correction on the 379 Cavium Octeon family of SOCs. 380 381config EDAC_OCTEON_LMC 382 tristate "Cavium Octeon DRAM Memory Controller (LMC)" 383 depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC 384 help 385 Support for error detection and correction on the 386 Cavium Octeon family of SOCs. 387 388config EDAC_OCTEON_PCI 389 tristate "Cavium Octeon PCI Controller" 390 depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC 391 help 392 Support for error detection and correction on the 393 Cavium Octeon family of SOCs. 394 395config EDAC_ALTERA 396 bool "Altera SOCFPGA ECC" 397 depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA 398 help 399 Support for error detection and correction on the 400 Altera SOCs. This must be selected for SDRAM ECC. 401 Note that the preloader must initialize the SDRAM 402 before loading the kernel. 403 404config EDAC_ALTERA_L2C 405 bool "Altera L2 Cache ECC" 406 depends on EDAC_ALTERA=y && CACHE_L2X0 407 help 408 Support for error detection and correction on the 409 Altera L2 cache Memory for Altera SoCs. This option 410 requires L2 cache. 411 412config EDAC_ALTERA_OCRAM 413 bool "Altera On-Chip RAM ECC" 414 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR 415 help 416 Support for error detection and correction on the 417 Altera On-Chip RAM Memory for Altera SoCs. 418 419config EDAC_ALTERA_ETHERNET 420 bool "Altera Ethernet FIFO ECC" 421 depends on EDAC_ALTERA=y 422 help 423 Support for error detection and correction on the 424 Altera Ethernet FIFO Memory for Altera SoCs. 425 426config EDAC_ALTERA_NAND 427 bool "Altera NAND FIFO ECC" 428 depends on EDAC_ALTERA=y && MTD_NAND_DENALI 429 help 430 Support for error detection and correction on the 431 Altera NAND FIFO Memory for Altera SoCs. 432 433config EDAC_ALTERA_DMA 434 bool "Altera DMA FIFO ECC" 435 depends on EDAC_ALTERA=y && PL330_DMA=y 436 help 437 Support for error detection and correction on the 438 Altera DMA FIFO Memory for Altera SoCs. 439 440config EDAC_ALTERA_USB 441 bool "Altera USB FIFO ECC" 442 depends on EDAC_ALTERA=y && USB_DWC2 443 help 444 Support for error detection and correction on the 445 Altera USB FIFO Memory for Altera SoCs. 446 447config EDAC_ALTERA_QSPI 448 bool "Altera QSPI FIFO ECC" 449 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI 450 help 451 Support for error detection and correction on the 452 Altera QSPI FIFO Memory for Altera SoCs. 453 454config EDAC_ALTERA_SDMMC 455 bool "Altera SDMMC FIFO ECC" 456 depends on EDAC_ALTERA=y && MMC_DW 457 help 458 Support for error detection and correction on the 459 Altera SDMMC FIFO Memory for Altera SoCs. 460 461config EDAC_SYNOPSYS 462 tristate "Synopsys DDR Memory Controller" 463 depends on EDAC_MM_EDAC && ARCH_ZYNQ 464 help 465 Support for error detection and correction on the Synopsys DDR 466 memory controller. 467 468config EDAC_XGENE 469 tristate "APM X-Gene SoC" 470 depends on EDAC_MM_EDAC && (ARM64 || COMPILE_TEST) 471 help 472 Support for error detection and correction on the 473 APM X-Gene family of SOCs. 474 475endif # EDAC 476