1# 2# EDAC Kconfig 3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com 4# Licensed and distributed under the GPL 5 6config EDAC_ATOMIC_SCRUB 7 bool 8 9config EDAC_SUPPORT 10 bool 11 12menuconfig EDAC 13 tristate "EDAC (Error Detection And Correction) reporting" 14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS 15 help 16 EDAC is a subsystem along with hardware-specific drivers designed to 17 report hardware errors. These are low-level errors that are reported 18 in the CPU or supporting chipset or other subsystems: 19 memory errors, cache errors, PCI errors, thermal throttling, etc.. 20 If unsure, select 'Y'. 21 22 The mailing list for the EDAC project is linux-edac@vger.kernel.org. 23 24if EDAC 25 26config EDAC_LEGACY_SYSFS 27 bool "EDAC legacy sysfs" 28 default y 29 help 30 Enable the compatibility sysfs nodes. 31 Use 'Y' if your edac utilities aren't ported to work with the newer 32 structures. 33 34config EDAC_DEBUG 35 bool "Debugging" 36 select DEBUG_FS 37 help 38 This turns on debugging information for the entire EDAC subsystem. 39 You do so by inserting edac_module with "edac_debug_level=x." Valid 40 levels are 0-4 (from low to high) and by default it is set to 2. 41 Usually you should select 'N' here. 42 43config EDAC_DECODE_MCE 44 tristate "Decode MCEs in human-readable form (only on AMD for now)" 45 depends on CPU_SUP_AMD && X86_MCE_AMD 46 default y 47 ---help--- 48 Enable this option if you want to decode Machine Check Exceptions 49 occurring on your machine in human-readable form. 50 51 You should definitely say Y here in case you want to decode MCEs 52 which occur really early upon boot, before the module infrastructure 53 has been initialized. 54 55config EDAC_GHES 56 bool "Output ACPI APEI/GHES BIOS detected errors via EDAC" 57 depends on ACPI_APEI_GHES && (EDAC=y) 58 help 59 Not all machines support hardware-driven error report. Some of those 60 provide a BIOS-driven error report mechanism via ACPI, using the 61 APEI/GHES driver. By enabling this option, the error reports provided 62 by GHES are sent to userspace via the EDAC API. 63 64 When this option is enabled, it will disable the hardware-driven 65 mechanisms, if a GHES BIOS is detected, entering into the 66 "Firmware First" mode. 67 68 It should be noticed that keeping both GHES and a hardware-driven 69 error mechanism won't work well, as BIOS will race with OS, while 70 reading the error registers. So, if you want to not use "Firmware 71 first" GHES error mechanism, you should disable GHES either at 72 compilation time or by passing "ghes.disable=1" Kernel parameter 73 at boot time. 74 75 In doubt, say 'Y'. 76 77config EDAC_AMD64 78 tristate "AMD64 (Opteron, Athlon64)" 79 depends on AMD_NB && EDAC_DECODE_MCE 80 help 81 Support for error detection and correction of DRAM ECC errors on 82 the AMD64 families (>= K8) of memory controllers. 83 84config EDAC_AMD64_ERROR_INJECTION 85 bool "Sysfs HW Error injection facilities" 86 depends on EDAC_AMD64 87 help 88 Recent Opterons (Family 10h and later) provide for Memory Error 89 Injection into the ECC detection circuits. The amd64_edac module 90 allows the operator/user to inject Uncorrectable and Correctable 91 errors into DRAM. 92 93 When enabled, in each of the respective memory controller directories 94 (/sys/devices/system/edac/mc/mcX), there are 3 input files: 95 96 - inject_section (0..3, 16-byte section of 64-byte cacheline), 97 - inject_word (0..8, 16-bit word of 16-byte section), 98 - inject_ecc_vector (hex ecc vector: select bits of inject word) 99 100 In addition, there are two control files, inject_read and inject_write, 101 which trigger the DRAM ECC Read and Write respectively. 102 103config EDAC_AMD76X 104 tristate "AMD 76x (760, 762, 768)" 105 depends on PCI && X86_32 106 help 107 Support for error detection and correction on the AMD 76x 108 series of chipsets used with the Athlon processor. 109 110config EDAC_E7XXX 111 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" 112 depends on PCI && X86_32 113 help 114 Support for error detection and correction on the Intel 115 E7205, E7500, E7501 and E7505 server chipsets. 116 117config EDAC_E752X 118 tristate "Intel e752x (e7520, e7525, e7320) and 3100" 119 depends on PCI && X86 120 help 121 Support for error detection and correction on the Intel 122 E7520, E7525, E7320 server chipsets. 123 124config EDAC_I82443BXGX 125 tristate "Intel 82443BX/GX (440BX/GX)" 126 depends on PCI && X86_32 127 depends on BROKEN 128 help 129 Support for error detection and correction on the Intel 130 82443BX/GX memory controllers (440BX/GX chipsets). 131 132config EDAC_I82875P 133 tristate "Intel 82875p (D82875P, E7210)" 134 depends on PCI && X86_32 135 help 136 Support for error detection and correction on the Intel 137 DP82785P and E7210 server chipsets. 138 139config EDAC_I82975X 140 tristate "Intel 82975x (D82975x)" 141 depends on PCI && X86 142 help 143 Support for error detection and correction on the Intel 144 DP82975x server chipsets. 145 146config EDAC_I3000 147 tristate "Intel 3000/3010" 148 depends on PCI && X86 149 help 150 Support for error detection and correction on the Intel 151 3000 and 3010 server chipsets. 152 153config EDAC_I3200 154 tristate "Intel 3200" 155 depends on PCI && X86 156 help 157 Support for error detection and correction on the Intel 158 3200 and 3210 server chipsets. 159 160config EDAC_IE31200 161 tristate "Intel e312xx" 162 depends on PCI && X86 163 help 164 Support for error detection and correction on the Intel 165 E3-1200 based DRAM controllers. 166 167config EDAC_X38 168 tristate "Intel X38" 169 depends on PCI && X86 170 help 171 Support for error detection and correction on the Intel 172 X38 server chipsets. 173 174config EDAC_I5400 175 tristate "Intel 5400 (Seaburg) chipsets" 176 depends on PCI && X86 177 help 178 Support for error detection and correction the Intel 179 i5400 MCH chipset (Seaburg). 180 181config EDAC_I7CORE 182 tristate "Intel i7 Core (Nehalem) processors" 183 depends on PCI && X86 && X86_MCE_INTEL 184 help 185 Support for error detection and correction the Intel 186 i7 Core (Nehalem) Integrated Memory Controller that exists on 187 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx 188 and Xeon 55xx processors. 189 190config EDAC_I82860 191 tristate "Intel 82860" 192 depends on PCI && X86_32 193 help 194 Support for error detection and correction on the Intel 195 82860 chipset. 196 197config EDAC_R82600 198 tristate "Radisys 82600 embedded chipset" 199 depends on PCI && X86_32 200 help 201 Support for error detection and correction on the Radisys 202 82600 embedded chipset. 203 204config EDAC_I5000 205 tristate "Intel Greencreek/Blackford chipset" 206 depends on X86 && PCI 207 help 208 Support for error detection and correction the Intel 209 Greekcreek/Blackford chipsets. 210 211config EDAC_I5100 212 tristate "Intel San Clemente MCH" 213 depends on X86 && PCI 214 help 215 Support for error detection and correction the Intel 216 San Clemente MCH. 217 218config EDAC_I7300 219 tristate "Intel Clarksboro MCH" 220 depends on X86 && PCI 221 help 222 Support for error detection and correction the Intel 223 Clarksboro MCH (Intel 7300 chipset). 224 225config EDAC_SBRIDGE 226 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" 227 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG 228 help 229 Support for error detection and correction the Intel 230 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. 231 232config EDAC_SKX 233 tristate "Intel Skylake server Integrated MC" 234 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG 235 select DMI 236 help 237 Support for error detection and correction the Intel 238 Skylake server Integrated Memory Controllers. If your 239 system has non-volatile DIMMs you should also manually 240 select CONFIG_ACPI_NFIT. 241 242config EDAC_PND2 243 tristate "Intel Pondicherry2" 244 depends on PCI && X86_64 && X86_MCE_INTEL 245 help 246 Support for error detection and correction on the Intel 247 Pondicherry2 Integrated Memory Controller. This SoC IP is 248 first used on the Apollo Lake platform and Denverton 249 micro-server but may appear on others in the future. 250 251config EDAC_MPC85XX 252 tristate "Freescale MPC83xx / MPC85xx" 253 depends on FSL_SOC 254 help 255 Support for error detection and correction on the Freescale 256 MPC8349, MPC8560, MPC8540, MPC8548, T4240 257 258config EDAC_LAYERSCAPE 259 tristate "Freescale Layerscape DDR" 260 depends on ARCH_LAYERSCAPE || SOC_LS1021A 261 help 262 Support for error detection and correction on Freescale memory 263 controllers on Layerscape SoCs. 264 265config EDAC_MV64X60 266 tristate "Marvell MV64x60" 267 depends on MV64X60 268 help 269 Support for error detection and correction on the Marvell 270 MV64360 and MV64460 chipsets. 271 272config EDAC_PASEMI 273 tristate "PA Semi PWRficient" 274 depends on PPC_PASEMI && PCI 275 help 276 Support for error detection and correction on PA Semi 277 PWRficient. 278 279config EDAC_CELL 280 tristate "Cell Broadband Engine memory controller" 281 depends on PPC_CELL_COMMON 282 help 283 Support for error detection and correction on the 284 Cell Broadband Engine internal memory controller 285 on platform without a hypervisor 286 287config EDAC_PPC4XX 288 tristate "PPC4xx IBM DDR2 Memory Controller" 289 depends on 4xx 290 help 291 This enables support for EDAC on the ECC memory used 292 with the IBM DDR2 memory controller found in various 293 PowerPC 4xx embedded processors such as the 405EX[r], 294 440SP, 440SPe, 460EX, 460GT and 460SX. 295 296config EDAC_AMD8131 297 tristate "AMD8131 HyperTransport PCI-X Tunnel" 298 depends on PCI && PPC_MAPLE 299 help 300 Support for error detection and correction on the 301 AMD8131 HyperTransport PCI-X Tunnel chip. 302 Note, add more Kconfig dependency if it's adopted 303 on some machine other than Maple. 304 305config EDAC_AMD8111 306 tristate "AMD8111 HyperTransport I/O Hub" 307 depends on PCI && PPC_MAPLE 308 help 309 Support for error detection and correction on the 310 AMD8111 HyperTransport I/O Hub chip. 311 Note, add more Kconfig dependency if it's adopted 312 on some machine other than Maple. 313 314config EDAC_CPC925 315 tristate "IBM CPC925 Memory Controller (PPC970FX)" 316 depends on PPC64 317 help 318 Support for error detection and correction on the 319 IBM CPC925 Bridge and Memory Controller, which is 320 a companion chip to the PowerPC 970 family of 321 processors. 322 323config EDAC_HIGHBANK_MC 324 tristate "Highbank Memory Controller" 325 depends on ARCH_HIGHBANK 326 help 327 Support for error detection and correction on the 328 Calxeda Highbank memory controller. 329 330config EDAC_HIGHBANK_L2 331 tristate "Highbank L2 Cache" 332 depends on ARCH_HIGHBANK 333 help 334 Support for error detection and correction on the 335 Calxeda Highbank memory controller. 336 337config EDAC_OCTEON_PC 338 tristate "Cavium Octeon Primary Caches" 339 depends on CPU_CAVIUM_OCTEON 340 help 341 Support for error detection and correction on the primary caches of 342 the cnMIPS cores of Cavium Octeon family SOCs. 343 344config EDAC_OCTEON_L2C 345 tristate "Cavium Octeon Secondary Caches (L2C)" 346 depends on CAVIUM_OCTEON_SOC 347 help 348 Support for error detection and correction on the 349 Cavium Octeon family of SOCs. 350 351config EDAC_OCTEON_LMC 352 tristate "Cavium Octeon DRAM Memory Controller (LMC)" 353 depends on CAVIUM_OCTEON_SOC 354 help 355 Support for error detection and correction on the 356 Cavium Octeon family of SOCs. 357 358config EDAC_OCTEON_PCI 359 tristate "Cavium Octeon PCI Controller" 360 depends on PCI && CAVIUM_OCTEON_SOC 361 help 362 Support for error detection and correction on the 363 Cavium Octeon family of SOCs. 364 365config EDAC_THUNDERX 366 tristate "Cavium ThunderX EDAC" 367 depends on ARM64 368 depends on PCI 369 help 370 Support for error detection and correction on the 371 Cavium ThunderX memory controllers (LMC), Cache 372 Coherent Processor Interconnect (CCPI) and L2 cache 373 blocks (TAD, CBC, MCI). 374 375config EDAC_ALTERA 376 bool "Altera SOCFPGA ECC" 377 depends on EDAC=y && ARCH_SOCFPGA 378 help 379 Support for error detection and correction on the 380 Altera SOCs. This must be selected for SDRAM ECC. 381 Note that the preloader must initialize the SDRAM 382 before loading the kernel. 383 384config EDAC_ALTERA_L2C 385 bool "Altera L2 Cache ECC" 386 depends on EDAC_ALTERA=y && CACHE_L2X0 387 help 388 Support for error detection and correction on the 389 Altera L2 cache Memory for Altera SoCs. This option 390 requires L2 cache. 391 392config EDAC_ALTERA_OCRAM 393 bool "Altera On-Chip RAM ECC" 394 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR 395 help 396 Support for error detection and correction on the 397 Altera On-Chip RAM Memory for Altera SoCs. 398 399config EDAC_ALTERA_ETHERNET 400 bool "Altera Ethernet FIFO ECC" 401 depends on EDAC_ALTERA=y 402 help 403 Support for error detection and correction on the 404 Altera Ethernet FIFO Memory for Altera SoCs. 405 406config EDAC_ALTERA_NAND 407 bool "Altera NAND FIFO ECC" 408 depends on EDAC_ALTERA=y && MTD_NAND_DENALI 409 help 410 Support for error detection and correction on the 411 Altera NAND FIFO Memory for Altera SoCs. 412 413config EDAC_ALTERA_DMA 414 bool "Altera DMA FIFO ECC" 415 depends on EDAC_ALTERA=y && PL330_DMA=y 416 help 417 Support for error detection and correction on the 418 Altera DMA FIFO Memory for Altera SoCs. 419 420config EDAC_ALTERA_USB 421 bool "Altera USB FIFO ECC" 422 depends on EDAC_ALTERA=y && USB_DWC2 423 help 424 Support for error detection and correction on the 425 Altera USB FIFO Memory for Altera SoCs. 426 427config EDAC_ALTERA_QSPI 428 bool "Altera QSPI FIFO ECC" 429 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI 430 help 431 Support for error detection and correction on the 432 Altera QSPI FIFO Memory for Altera SoCs. 433 434config EDAC_ALTERA_SDMMC 435 bool "Altera SDMMC FIFO ECC" 436 depends on EDAC_ALTERA=y && MMC_DW 437 help 438 Support for error detection and correction on the 439 Altera SDMMC FIFO Memory for Altera SoCs. 440 441config EDAC_SYNOPSYS 442 tristate "Synopsys DDR Memory Controller" 443 depends on ARCH_ZYNQ 444 help 445 Support for error detection and correction on the Synopsys DDR 446 memory controller. 447 448config EDAC_XGENE 449 tristate "APM X-Gene SoC" 450 depends on (ARM64 || COMPILE_TEST) 451 help 452 Support for error detection and correction on the 453 APM X-Gene family of SOCs. 454 455config EDAC_TI 456 tristate "Texas Instruments DDR3 ECC Controller" 457 depends on ARCH_KEYSTONE || SOC_DRA7XX 458 help 459 Support for error detection and correction on the 460 TI SoCs. 461 462endif # EDAC 463