1# 2# EDAC Kconfig 3# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com 4# Licensed and distributed under the GPL 5 6config EDAC_ATOMIC_SCRUB 7 bool 8 9config EDAC_SUPPORT 10 bool 11 12menuconfig EDAC 13 tristate "EDAC (Error Detection And Correction) reporting" 14 depends on HAS_IOMEM && EDAC_SUPPORT && RAS 15 help 16 EDAC is a subsystem along with hardware-specific drivers designed to 17 report hardware errors. These are low-level errors that are reported 18 in the CPU or supporting chipset or other subsystems: 19 memory errors, cache errors, PCI errors, thermal throttling, etc.. 20 If unsure, select 'Y'. 21 22 The mailing list for the EDAC project is linux-edac@vger.kernel.org. 23 24if EDAC 25 26config EDAC_LEGACY_SYSFS 27 bool "EDAC legacy sysfs" 28 default y 29 help 30 Enable the compatibility sysfs nodes. 31 Use 'Y' if your edac utilities aren't ported to work with the newer 32 structures. 33 34config EDAC_DEBUG 35 bool "Debugging" 36 select DEBUG_FS 37 help 38 This turns on debugging information for the entire EDAC subsystem. 39 You do so by inserting edac_module with "edac_debug_level=x." Valid 40 levels are 0-4 (from low to high) and by default it is set to 2. 41 Usually you should select 'N' here. 42 43config EDAC_DECODE_MCE 44 tristate "Decode MCEs in human-readable form (only on AMD for now)" 45 depends on CPU_SUP_AMD && X86_MCE_AMD 46 default y 47 help 48 Enable this option if you want to decode Machine Check Exceptions 49 occurring on your machine in human-readable form. 50 51 You should definitely say Y here in case you want to decode MCEs 52 which occur really early upon boot, before the module infrastructure 53 has been initialized. 54 55config EDAC_GHES 56 bool "Output ACPI APEI/GHES BIOS detected errors via EDAC" 57 depends on ACPI_APEI_GHES && (EDAC=y) 58 select UEFI_CPER 59 help 60 Not all machines support hardware-driven error report. Some of those 61 provide a BIOS-driven error report mechanism via ACPI, using the 62 APEI/GHES driver. By enabling this option, the error reports provided 63 by GHES are sent to userspace via the EDAC API. 64 65 When this option is enabled, it will disable the hardware-driven 66 mechanisms, if a GHES BIOS is detected, entering into the 67 "Firmware First" mode. 68 69 It should be noticed that keeping both GHES and a hardware-driven 70 error mechanism won't work well, as BIOS will race with OS, while 71 reading the error registers. So, if you want to not use "Firmware 72 first" GHES error mechanism, you should disable GHES either at 73 compilation time or by passing "ghes.disable=1" Kernel parameter 74 at boot time. 75 76 In doubt, say 'Y'. 77 78config EDAC_AMD64 79 tristate "AMD64 (Opteron, Athlon64)" 80 depends on AMD_NB && EDAC_DECODE_MCE 81 help 82 Support for error detection and correction of DRAM ECC errors on 83 the AMD64 families (>= K8) of memory controllers. 84 85 When EDAC_DEBUG is enabled, hardware error injection facilities 86 through sysfs are available: 87 88 AMD CPUs up to and excluding family 0x17 provide for Memory 89 Error Injection into the ECC detection circuits. The amd64_edac 90 module allows the operator/user to inject Uncorrectable and 91 Correctable errors into DRAM. 92 93 When enabled, in each of the respective memory controller directories 94 (/sys/devices/system/edac/mc/mcX), there are 3 input files: 95 96 - inject_section (0..3, 16-byte section of 64-byte cacheline), 97 - inject_word (0..8, 16-bit word of 16-byte section), 98 - inject_ecc_vector (hex ecc vector: select bits of inject word) 99 100 In addition, there are two control files, inject_read and inject_write, 101 which trigger the DRAM ECC Read and Write respectively. 102 103config EDAC_AL_MC 104 tristate "Amazon's Annapurna Lab Memory Controller" 105 depends on (ARCH_ALPINE || COMPILE_TEST) 106 help 107 Support for error detection and correction for Amazon's Annapurna 108 Labs Alpine chips which allow 1 bit correction and 2 bits detection. 109 110config EDAC_AMD76X 111 tristate "AMD 76x (760, 762, 768)" 112 depends on PCI && X86_32 113 help 114 Support for error detection and correction on the AMD 76x 115 series of chipsets used with the Athlon processor. 116 117config EDAC_E7XXX 118 tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" 119 depends on PCI && X86_32 120 help 121 Support for error detection and correction on the Intel 122 E7205, E7500, E7501 and E7505 server chipsets. 123 124config EDAC_E752X 125 tristate "Intel e752x (e7520, e7525, e7320) and 3100" 126 depends on PCI && X86 127 help 128 Support for error detection and correction on the Intel 129 E7520, E7525, E7320 server chipsets. 130 131config EDAC_I82443BXGX 132 tristate "Intel 82443BX/GX (440BX/GX)" 133 depends on PCI && X86_32 134 depends on BROKEN 135 help 136 Support for error detection and correction on the Intel 137 82443BX/GX memory controllers (440BX/GX chipsets). 138 139config EDAC_I82875P 140 tristate "Intel 82875p (D82875P, E7210)" 141 depends on PCI && X86_32 142 help 143 Support for error detection and correction on the Intel 144 DP82785P and E7210 server chipsets. 145 146config EDAC_I82975X 147 tristate "Intel 82975x (D82975x)" 148 depends on PCI && X86 149 help 150 Support for error detection and correction on the Intel 151 DP82975x server chipsets. 152 153config EDAC_I3000 154 tristate "Intel 3000/3010" 155 depends on PCI && X86 156 help 157 Support for error detection and correction on the Intel 158 3000 and 3010 server chipsets. 159 160config EDAC_I3200 161 tristate "Intel 3200" 162 depends on PCI && X86 163 help 164 Support for error detection and correction on the Intel 165 3200 and 3210 server chipsets. 166 167config EDAC_IE31200 168 tristate "Intel e312xx" 169 depends on PCI && X86 170 help 171 Support for error detection and correction on the Intel 172 E3-1200 based DRAM controllers. 173 174config EDAC_X38 175 tristate "Intel X38" 176 depends on PCI && X86 177 help 178 Support for error detection and correction on the Intel 179 X38 server chipsets. 180 181config EDAC_I5400 182 tristate "Intel 5400 (Seaburg) chipsets" 183 depends on PCI && X86 184 help 185 Support for error detection and correction the Intel 186 i5400 MCH chipset (Seaburg). 187 188config EDAC_I7CORE 189 tristate "Intel i7 Core (Nehalem) processors" 190 depends on PCI && X86 && X86_MCE_INTEL 191 help 192 Support for error detection and correction the Intel 193 i7 Core (Nehalem) Integrated Memory Controller that exists on 194 newer processors like i7 Core, i7 Core Extreme, Xeon 35xx 195 and Xeon 55xx processors. 196 197config EDAC_I82860 198 tristate "Intel 82860" 199 depends on PCI && X86_32 200 help 201 Support for error detection and correction on the Intel 202 82860 chipset. 203 204config EDAC_R82600 205 tristate "Radisys 82600 embedded chipset" 206 depends on PCI && X86_32 207 help 208 Support for error detection and correction on the Radisys 209 82600 embedded chipset. 210 211config EDAC_I5000 212 tristate "Intel Greencreek/Blackford chipset" 213 depends on X86 && PCI 214 help 215 Support for error detection and correction the Intel 216 Greekcreek/Blackford chipsets. 217 218config EDAC_I5100 219 tristate "Intel San Clemente MCH" 220 depends on X86 && PCI 221 help 222 Support for error detection and correction the Intel 223 San Clemente MCH. 224 225config EDAC_I7300 226 tristate "Intel Clarksboro MCH" 227 depends on X86 && PCI 228 help 229 Support for error detection and correction the Intel 230 Clarksboro MCH (Intel 7300 chipset). 231 232config EDAC_SBRIDGE 233 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" 234 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG 235 help 236 Support for error detection and correction the Intel 237 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. 238 239config EDAC_SKX 240 tristate "Intel Skylake server Integrated MC" 241 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 242 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y 243 select DMI 244 select ACPI_ADXL 245 help 246 Support for error detection and correction the Intel 247 Skylake server Integrated Memory Controllers. If your 248 system has non-volatile DIMMs you should also manually 249 select CONFIG_ACPI_NFIT. 250 251config EDAC_I10NM 252 tristate "Intel 10nm server Integrated MC" 253 depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI 254 depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y 255 select DMI 256 select ACPI_ADXL 257 help 258 Support for error detection and correction the Intel 259 10nm server Integrated Memory Controllers. If your 260 system has non-volatile DIMMs you should also manually 261 select CONFIG_ACPI_NFIT. 262 263config EDAC_PND2 264 tristate "Intel Pondicherry2" 265 depends on PCI && X86_64 && X86_MCE_INTEL 266 select P2SB if X86 267 help 268 Support for error detection and correction on the Intel 269 Pondicherry2 Integrated Memory Controller. This SoC IP is 270 first used on the Apollo Lake platform and Denverton 271 micro-server but may appear on others in the future. 272 273config EDAC_IGEN6 274 tristate "Intel client SoC Integrated MC" 275 depends on PCI && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG 276 depends on X86_64 && X86_MCE_INTEL 277 help 278 Support for error detection and correction on the Intel 279 client SoC Integrated Memory Controller using In-Band ECC IP. 280 This In-Band ECC is first used on the Elkhart Lake SoC but 281 may appear on others in the future. 282 283config EDAC_MPC85XX 284 bool "Freescale MPC83xx / MPC85xx" 285 depends on FSL_SOC && EDAC=y 286 help 287 Support for error detection and correction on the Freescale 288 MPC8349, MPC8560, MPC8540, MPC8548, T4240 289 290config EDAC_LAYERSCAPE 291 tristate "Freescale Layerscape DDR" 292 depends on ARCH_LAYERSCAPE || SOC_LS1021A 293 help 294 Support for error detection and correction on Freescale memory 295 controllers on Layerscape SoCs. 296 297config EDAC_PASEMI 298 tristate "PA Semi PWRficient" 299 depends on PPC_PASEMI && PCI 300 help 301 Support for error detection and correction on PA Semi 302 PWRficient. 303 304config EDAC_CELL 305 tristate "Cell Broadband Engine memory controller" 306 depends on PPC_CELL_COMMON 307 help 308 Support for error detection and correction on the 309 Cell Broadband Engine internal memory controller 310 on platform without a hypervisor 311 312config EDAC_PPC4XX 313 tristate "PPC4xx IBM DDR2 Memory Controller" 314 depends on 4xx 315 help 316 This enables support for EDAC on the ECC memory used 317 with the IBM DDR2 memory controller found in various 318 PowerPC 4xx embedded processors such as the 405EX[r], 319 440SP, 440SPe, 460EX, 460GT and 460SX. 320 321config EDAC_AMD8131 322 tristate "AMD8131 HyperTransport PCI-X Tunnel" 323 depends on PCI && PPC_MAPLE 324 help 325 Support for error detection and correction on the 326 AMD8131 HyperTransport PCI-X Tunnel chip. 327 Note, add more Kconfig dependency if it's adopted 328 on some machine other than Maple. 329 330config EDAC_AMD8111 331 tristate "AMD8111 HyperTransport I/O Hub" 332 depends on PCI && PPC_MAPLE 333 help 334 Support for error detection and correction on the 335 AMD8111 HyperTransport I/O Hub chip. 336 Note, add more Kconfig dependency if it's adopted 337 on some machine other than Maple. 338 339config EDAC_CPC925 340 tristate "IBM CPC925 Memory Controller (PPC970FX)" 341 depends on PPC64 342 help 343 Support for error detection and correction on the 344 IBM CPC925 Bridge and Memory Controller, which is 345 a companion chip to the PowerPC 970 family of 346 processors. 347 348config EDAC_HIGHBANK_MC 349 tristate "Highbank Memory Controller" 350 depends on ARCH_HIGHBANK 351 help 352 Support for error detection and correction on the 353 Calxeda Highbank memory controller. 354 355config EDAC_HIGHBANK_L2 356 tristate "Highbank L2 Cache" 357 depends on ARCH_HIGHBANK 358 help 359 Support for error detection and correction on the 360 Calxeda Highbank memory controller. 361 362config EDAC_OCTEON_PC 363 tristate "Cavium Octeon Primary Caches" 364 depends on CPU_CAVIUM_OCTEON 365 help 366 Support for error detection and correction on the primary caches of 367 the cnMIPS cores of Cavium Octeon family SOCs. 368 369config EDAC_OCTEON_L2C 370 tristate "Cavium Octeon Secondary Caches (L2C)" 371 depends on CAVIUM_OCTEON_SOC 372 help 373 Support for error detection and correction on the 374 Cavium Octeon family of SOCs. 375 376config EDAC_OCTEON_LMC 377 tristate "Cavium Octeon DRAM Memory Controller (LMC)" 378 depends on CAVIUM_OCTEON_SOC 379 help 380 Support for error detection and correction on the 381 Cavium Octeon family of SOCs. 382 383config EDAC_OCTEON_PCI 384 tristate "Cavium Octeon PCI Controller" 385 depends on PCI && CAVIUM_OCTEON_SOC 386 help 387 Support for error detection and correction on the 388 Cavium Octeon family of SOCs. 389 390config EDAC_THUNDERX 391 tristate "Cavium ThunderX EDAC" 392 depends on ARM64 393 depends on PCI 394 help 395 Support for error detection and correction on the 396 Cavium ThunderX memory controllers (LMC), Cache 397 Coherent Processor Interconnect (CCPI) and L2 cache 398 blocks (TAD, CBC, MCI). 399 400config EDAC_ALTERA 401 bool "Altera SOCFPGA ECC" 402 depends on EDAC=y && ARCH_INTEL_SOCFPGA 403 help 404 Support for error detection and correction on the 405 Altera SOCs. This is the global enable for the 406 various Altera peripherals. 407 408config EDAC_ALTERA_SDRAM 409 bool "Altera SDRAM ECC" 410 depends on EDAC_ALTERA=y 411 help 412 Support for error detection and correction on the 413 Altera SDRAM Memory for Altera SoCs. Note that the 414 preloader must initialize the SDRAM before loading 415 the kernel. 416 417config EDAC_ALTERA_L2C 418 bool "Altera L2 Cache ECC" 419 depends on EDAC_ALTERA=y && CACHE_L2X0 420 help 421 Support for error detection and correction on the 422 Altera L2 cache Memory for Altera SoCs. This option 423 requires L2 cache. 424 425config EDAC_ALTERA_OCRAM 426 bool "Altera On-Chip RAM ECC" 427 depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR 428 help 429 Support for error detection and correction on the 430 Altera On-Chip RAM Memory for Altera SoCs. 431 432config EDAC_ALTERA_ETHERNET 433 bool "Altera Ethernet FIFO ECC" 434 depends on EDAC_ALTERA=y 435 help 436 Support for error detection and correction on the 437 Altera Ethernet FIFO Memory for Altera SoCs. 438 439config EDAC_ALTERA_NAND 440 bool "Altera NAND FIFO ECC" 441 depends on EDAC_ALTERA=y && MTD_NAND_DENALI 442 help 443 Support for error detection and correction on the 444 Altera NAND FIFO Memory for Altera SoCs. 445 446config EDAC_ALTERA_DMA 447 bool "Altera DMA FIFO ECC" 448 depends on EDAC_ALTERA=y && PL330_DMA=y 449 help 450 Support for error detection and correction on the 451 Altera DMA FIFO Memory for Altera SoCs. 452 453config EDAC_ALTERA_USB 454 bool "Altera USB FIFO ECC" 455 depends on EDAC_ALTERA=y && USB_DWC2 456 help 457 Support for error detection and correction on the 458 Altera USB FIFO Memory for Altera SoCs. 459 460config EDAC_ALTERA_QSPI 461 bool "Altera QSPI FIFO ECC" 462 depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI 463 help 464 Support for error detection and correction on the 465 Altera QSPI FIFO Memory for Altera SoCs. 466 467config EDAC_ALTERA_SDMMC 468 bool "Altera SDMMC FIFO ECC" 469 depends on EDAC_ALTERA=y && MMC_DW 470 help 471 Support for error detection and correction on the 472 Altera SDMMC FIFO Memory for Altera SoCs. 473 474config EDAC_SIFIVE 475 bool "Sifive platform EDAC driver" 476 depends on EDAC=y && SIFIVE_L2 477 help 478 Support for error detection and correction on the SiFive SoCs. 479 480config EDAC_ARMADA_XP 481 bool "Marvell Armada XP DDR and L2 Cache ECC" 482 depends on MACH_MVEBU_V7 483 help 484 Support for error correction and detection on the Marvell Aramada XP 485 DDR RAM and L2 cache controllers. 486 487config EDAC_SYNOPSYS 488 tristate "Synopsys DDR Memory Controller" 489 depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC 490 help 491 Support for error detection and correction on the Synopsys DDR 492 memory controller. 493 494config EDAC_XGENE 495 tristate "APM X-Gene SoC" 496 depends on (ARM64 || COMPILE_TEST) 497 help 498 Support for error detection and correction on the 499 APM X-Gene family of SOCs. 500 501config EDAC_TI 502 tristate "Texas Instruments DDR3 ECC Controller" 503 depends on ARCH_KEYSTONE || SOC_DRA7XX 504 help 505 Support for error detection and correction on the TI SoCs. 506 507config EDAC_QCOM 508 tristate "QCOM EDAC Controller" 509 depends on ARCH_QCOM && QCOM_LLCC 510 help 511 Support for error detection and correction on the 512 Qualcomm Technologies, Inc. SoCs. 513 514 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs). 515 As of now, it supports error reporting for Last Level Cache Controller (LLCC) 516 of Tag RAM and Data RAM. 517 518 For debugging issues having to do with stability and overall system 519 health, you should probably say 'Y' here. 520 521config EDAC_ASPEED 522 tristate "Aspeed AST BMC SoC" 523 depends on ARCH_ASPEED 524 help 525 Support for error detection and correction on the Aspeed AST BMC SoC. 526 527 First, ECC must be configured in the bootloader. Then, this driver 528 will expose error counters via the EDAC kernel framework. 529 530config EDAC_BLUEFIELD 531 tristate "Mellanox BlueField Memory ECC" 532 depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST) 533 help 534 Support for error detection and correction on the 535 Mellanox BlueField SoCs. 536 537config EDAC_DMC520 538 tristate "ARM DMC-520 ECC" 539 depends on ARM64 540 help 541 Support for error detection and correction on the 542 SoCs with ARM DMC-520 DRAM controller. 543 544endif # EDAC 545