1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Xilinx ZynqMP DPDMA Engine driver 4 * 5 * Copyright (C) 2015 - 2020 Xilinx, Inc. 6 * 7 * Author: Hyun Woo Kwon <hyun.kwon@xilinx.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/clk.h> 13 #include <linux/debugfs.h> 14 #include <linux/delay.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dmapool.h> 17 #include <linux/interrupt.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_dma.h> 21 #include <linux/platform_device.h> 22 #include <linux/sched.h> 23 #include <linux/slab.h> 24 #include <linux/spinlock.h> 25 #include <linux/wait.h> 26 27 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> 28 29 #include "../dmaengine.h" 30 #include "../virt-dma.h" 31 32 /* DPDMA registers */ 33 #define XILINX_DPDMA_ERR_CTRL 0x000 34 #define XILINX_DPDMA_ISR 0x004 35 #define XILINX_DPDMA_IMR 0x008 36 #define XILINX_DPDMA_IEN 0x00c 37 #define XILINX_DPDMA_IDS 0x010 38 #define XILINX_DPDMA_INTR_DESC_DONE(n) BIT((n) + 0) 39 #define XILINX_DPDMA_INTR_DESC_DONE_MASK GENMASK(5, 0) 40 #define XILINX_DPDMA_INTR_NO_OSTAND(n) BIT((n) + 6) 41 #define XILINX_DPDMA_INTR_NO_OSTAND_MASK GENMASK(11, 6) 42 #define XILINX_DPDMA_INTR_AXI_ERR(n) BIT((n) + 12) 43 #define XILINX_DPDMA_INTR_AXI_ERR_MASK GENMASK(17, 12) 44 #define XILINX_DPDMA_INTR_DESC_ERR(n) BIT((n) + 16) 45 #define XILINX_DPDMA_INTR_DESC_ERR_MASK GENMASK(23, 18) 46 #define XILINX_DPDMA_INTR_WR_CMD_FIFO_FULL BIT(24) 47 #define XILINX_DPDMA_INTR_WR_DATA_FIFO_FULL BIT(25) 48 #define XILINX_DPDMA_INTR_AXI_4K_CROSS BIT(26) 49 #define XILINX_DPDMA_INTR_VSYNC BIT(27) 50 #define XILINX_DPDMA_INTR_CHAN_ERR_MASK 0x00041000 51 #define XILINX_DPDMA_INTR_CHAN_ERR 0x00fff000 52 #define XILINX_DPDMA_INTR_GLOBAL_ERR 0x07000000 53 #define XILINX_DPDMA_INTR_ERR_ALL 0x07fff000 54 #define XILINX_DPDMA_INTR_CHAN_MASK 0x00041041 55 #define XILINX_DPDMA_INTR_GLOBAL_MASK 0x0f000000 56 #define XILINX_DPDMA_INTR_ALL 0x0fffffff 57 #define XILINX_DPDMA_EISR 0x014 58 #define XILINX_DPDMA_EIMR 0x018 59 #define XILINX_DPDMA_EIEN 0x01c 60 #define XILINX_DPDMA_EIDS 0x020 61 #define XILINX_DPDMA_EINTR_INV_APB BIT(0) 62 #define XILINX_DPDMA_EINTR_RD_AXI_ERR(n) BIT((n) + 1) 63 #define XILINX_DPDMA_EINTR_RD_AXI_ERR_MASK GENMASK(6, 1) 64 #define XILINX_DPDMA_EINTR_PRE_ERR(n) BIT((n) + 7) 65 #define XILINX_DPDMA_EINTR_PRE_ERR_MASK GENMASK(12, 7) 66 #define XILINX_DPDMA_EINTR_CRC_ERR(n) BIT((n) + 13) 67 #define XILINX_DPDMA_EINTR_CRC_ERR_MASK GENMASK(18, 13) 68 #define XILINX_DPDMA_EINTR_WR_AXI_ERR(n) BIT((n) + 19) 69 #define XILINX_DPDMA_EINTR_WR_AXI_ERR_MASK GENMASK(24, 19) 70 #define XILINX_DPDMA_EINTR_DESC_DONE_ERR(n) BIT((n) + 25) 71 #define XILINX_DPDMA_EINTR_DESC_DONE_ERR_MASK GENMASK(30, 25) 72 #define XILINX_DPDMA_EINTR_RD_CMD_FIFO_FULL BIT(32) 73 #define XILINX_DPDMA_EINTR_CHAN_ERR_MASK 0x02082082 74 #define XILINX_DPDMA_EINTR_CHAN_ERR 0x7ffffffe 75 #define XILINX_DPDMA_EINTR_GLOBAL_ERR 0x80000001 76 #define XILINX_DPDMA_EINTR_ALL 0xffffffff 77 #define XILINX_DPDMA_CNTL 0x100 78 #define XILINX_DPDMA_GBL 0x104 79 #define XILINX_DPDMA_GBL_TRIG_MASK(n) ((n) << 0) 80 #define XILINX_DPDMA_GBL_RETRIG_MASK(n) ((n) << 6) 81 #define XILINX_DPDMA_ALC0_CNTL 0x108 82 #define XILINX_DPDMA_ALC0_STATUS 0x10c 83 #define XILINX_DPDMA_ALC0_MAX 0x110 84 #define XILINX_DPDMA_ALC0_MIN 0x114 85 #define XILINX_DPDMA_ALC0_ACC 0x118 86 #define XILINX_DPDMA_ALC0_ACC_TRAN 0x11c 87 #define XILINX_DPDMA_ALC1_CNTL 0x120 88 #define XILINX_DPDMA_ALC1_STATUS 0x124 89 #define XILINX_DPDMA_ALC1_MAX 0x128 90 #define XILINX_DPDMA_ALC1_MIN 0x12c 91 #define XILINX_DPDMA_ALC1_ACC 0x130 92 #define XILINX_DPDMA_ALC1_ACC_TRAN 0x134 93 94 /* Channel register */ 95 #define XILINX_DPDMA_CH_BASE 0x200 96 #define XILINX_DPDMA_CH_OFFSET 0x100 97 #define XILINX_DPDMA_CH_DESC_START_ADDRE 0x000 98 #define XILINX_DPDMA_CH_DESC_START_ADDRE_MASK GENMASK(15, 0) 99 #define XILINX_DPDMA_CH_DESC_START_ADDR 0x004 100 #define XILINX_DPDMA_CH_DESC_NEXT_ADDRE 0x008 101 #define XILINX_DPDMA_CH_DESC_NEXT_ADDR 0x00c 102 #define XILINX_DPDMA_CH_PYLD_CUR_ADDRE 0x010 103 #define XILINX_DPDMA_CH_PYLD_CUR_ADDR 0x014 104 #define XILINX_DPDMA_CH_CNTL 0x018 105 #define XILINX_DPDMA_CH_CNTL_ENABLE BIT(0) 106 #define XILINX_DPDMA_CH_CNTL_PAUSE BIT(1) 107 #define XILINX_DPDMA_CH_CNTL_QOS_DSCR_WR_MASK GENMASK(5, 2) 108 #define XILINX_DPDMA_CH_CNTL_QOS_DSCR_RD_MASK GENMASK(9, 6) 109 #define XILINX_DPDMA_CH_CNTL_QOS_DATA_RD_MASK GENMASK(13, 10) 110 #define XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS 11 111 #define XILINX_DPDMA_CH_STATUS 0x01c 112 #define XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK GENMASK(24, 21) 113 #define XILINX_DPDMA_CH_VDO 0x020 114 #define XILINX_DPDMA_CH_PYLD_SZ 0x024 115 #define XILINX_DPDMA_CH_DESC_ID 0x028 116 #define XILINX_DPDMA_CH_DESC_ID_MASK GENMASK(15, 0) 117 118 /* DPDMA descriptor fields */ 119 #define XILINX_DPDMA_DESC_CONTROL_PREEMBLE 0xa5 120 #define XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR BIT(8) 121 #define XILINX_DPDMA_DESC_CONTROL_DESC_UPDATE BIT(9) 122 #define XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE BIT(10) 123 #define XILINX_DPDMA_DESC_CONTROL_FRAG_MODE BIT(18) 124 #define XILINX_DPDMA_DESC_CONTROL_LAST BIT(19) 125 #define XILINX_DPDMA_DESC_CONTROL_ENABLE_CRC BIT(20) 126 #define XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME BIT(21) 127 #define XILINX_DPDMA_DESC_ID_MASK GENMASK(15, 0) 128 #define XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK GENMASK(17, 0) 129 #define XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK GENMASK(31, 18) 130 #define XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK GENMASK(15, 0) 131 #define XILINX_DPDMA_DESC_ADDR_EXT_SRC_ADDR_MASK GENMASK(31, 16) 132 133 #define XILINX_DPDMA_ALIGN_BYTES 256 134 #define XILINX_DPDMA_LINESIZE_ALIGN_BITS 128 135 136 #define XILINX_DPDMA_NUM_CHAN 6 137 138 struct xilinx_dpdma_chan; 139 140 /** 141 * struct xilinx_dpdma_hw_desc - DPDMA hardware descriptor 142 * @control: control configuration field 143 * @desc_id: descriptor ID 144 * @xfer_size: transfer size 145 * @hsize_stride: horizontal size and stride 146 * @timestamp_lsb: LSB of time stamp 147 * @timestamp_msb: MSB of time stamp 148 * @addr_ext: upper 16 bit of 48 bit address (next_desc and src_addr) 149 * @next_desc: next descriptor 32 bit address 150 * @src_addr: payload source address (1st page, 32 LSB) 151 * @addr_ext_23: payload source address (3nd and 3rd pages, 16 LSBs) 152 * @addr_ext_45: payload source address (4th and 5th pages, 16 LSBs) 153 * @src_addr2: payload source address (2nd page, 32 LSB) 154 * @src_addr3: payload source address (3rd page, 32 LSB) 155 * @src_addr4: payload source address (4th page, 32 LSB) 156 * @src_addr5: payload source address (5th page, 32 LSB) 157 * @crc: descriptor CRC 158 */ 159 struct xilinx_dpdma_hw_desc { 160 u32 control; 161 u32 desc_id; 162 u32 xfer_size; 163 u32 hsize_stride; 164 u32 timestamp_lsb; 165 u32 timestamp_msb; 166 u32 addr_ext; 167 u32 next_desc; 168 u32 src_addr; 169 u32 addr_ext_23; 170 u32 addr_ext_45; 171 u32 src_addr2; 172 u32 src_addr3; 173 u32 src_addr4; 174 u32 src_addr5; 175 u32 crc; 176 } __aligned(XILINX_DPDMA_ALIGN_BYTES); 177 178 /** 179 * struct xilinx_dpdma_sw_desc - DPDMA software descriptor 180 * @hw: DPDMA hardware descriptor 181 * @node: list node for software descriptors 182 * @dma_addr: DMA address of the software descriptor 183 */ 184 struct xilinx_dpdma_sw_desc { 185 struct xilinx_dpdma_hw_desc hw; 186 struct list_head node; 187 dma_addr_t dma_addr; 188 }; 189 190 /** 191 * struct xilinx_dpdma_tx_desc - DPDMA transaction descriptor 192 * @vdesc: virtual DMA descriptor 193 * @chan: DMA channel 194 * @descriptors: list of software descriptors 195 * @error: an error has been detected with this descriptor 196 */ 197 struct xilinx_dpdma_tx_desc { 198 struct virt_dma_desc vdesc; 199 struct xilinx_dpdma_chan *chan; 200 struct list_head descriptors; 201 bool error; 202 }; 203 204 #define to_dpdma_tx_desc(_desc) \ 205 container_of(_desc, struct xilinx_dpdma_tx_desc, vdesc) 206 207 /** 208 * struct xilinx_dpdma_chan - DPDMA channel 209 * @vchan: virtual DMA channel 210 * @reg: register base address 211 * @id: channel ID 212 * @wait_to_stop: queue to wait for outstanding transacitons before stopping 213 * @running: true if the channel is running 214 * @first_frame: flag for the first frame of stream 215 * @video_group: flag if multi-channel operation is needed for video channels 216 * @lock: lock to access struct xilinx_dpdma_chan 217 * @desc_pool: descriptor allocation pool 218 * @err_task: error IRQ bottom half handler 219 * @desc: References to descriptors being processed 220 * @desc.pending: Descriptor schedule to the hardware, pending execution 221 * @desc.active: Descriptor being executed by the hardware 222 * @xdev: DPDMA device 223 */ 224 struct xilinx_dpdma_chan { 225 struct virt_dma_chan vchan; 226 void __iomem *reg; 227 unsigned int id; 228 229 wait_queue_head_t wait_to_stop; 230 bool running; 231 bool first_frame; 232 bool video_group; 233 234 spinlock_t lock; /* lock to access struct xilinx_dpdma_chan */ 235 struct dma_pool *desc_pool; 236 struct tasklet_struct err_task; 237 238 struct { 239 struct xilinx_dpdma_tx_desc *pending; 240 struct xilinx_dpdma_tx_desc *active; 241 } desc; 242 243 struct xilinx_dpdma_device *xdev; 244 }; 245 246 #define to_xilinx_chan(_chan) \ 247 container_of(_chan, struct xilinx_dpdma_chan, vchan.chan) 248 249 /** 250 * struct xilinx_dpdma_device - DPDMA device 251 * @common: generic dma device structure 252 * @reg: register base address 253 * @dev: generic device structure 254 * @irq: the interrupt number 255 * @axi_clk: axi clock 256 * @chan: DPDMA channels 257 * @ext_addr: flag for 64 bit system (48 bit addressing) 258 */ 259 struct xilinx_dpdma_device { 260 struct dma_device common; 261 void __iomem *reg; 262 struct device *dev; 263 int irq; 264 265 struct clk *axi_clk; 266 struct xilinx_dpdma_chan *chan[XILINX_DPDMA_NUM_CHAN]; 267 268 bool ext_addr; 269 }; 270 271 /* ----------------------------------------------------------------------------- 272 * DebugFS 273 */ 274 #define XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE 32 275 #define XILINX_DPDMA_DEBUGFS_UINT16_MAX_STR "65535" 276 277 /* Match xilinx_dpdma_testcases vs dpdma_debugfs_reqs[] entry */ 278 enum xilinx_dpdma_testcases { 279 DPDMA_TC_INTR_DONE, 280 DPDMA_TC_NONE 281 }; 282 283 struct xilinx_dpdma_debugfs { 284 enum xilinx_dpdma_testcases testcase; 285 u16 xilinx_dpdma_irq_done_count; 286 unsigned int chan_id; 287 }; 288 289 static struct xilinx_dpdma_debugfs dpdma_debugfs; 290 struct xilinx_dpdma_debugfs_request { 291 const char *name; 292 enum xilinx_dpdma_testcases tc; 293 ssize_t (*read)(char *buf); 294 int (*write)(char *args); 295 }; 296 297 static void xilinx_dpdma_debugfs_desc_done_irq(struct xilinx_dpdma_chan *chan) 298 { 299 if (IS_ENABLED(CONFIG_DEBUG_FS) && chan->id == dpdma_debugfs.chan_id) 300 dpdma_debugfs.xilinx_dpdma_irq_done_count++; 301 } 302 303 static ssize_t xilinx_dpdma_debugfs_desc_done_irq_read(char *buf) 304 { 305 size_t out_str_len; 306 307 dpdma_debugfs.testcase = DPDMA_TC_NONE; 308 309 out_str_len = strlen(XILINX_DPDMA_DEBUGFS_UINT16_MAX_STR); 310 out_str_len = min_t(size_t, XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE, 311 out_str_len); 312 snprintf(buf, out_str_len, "%d", 313 dpdma_debugfs.xilinx_dpdma_irq_done_count); 314 315 return 0; 316 } 317 318 static int xilinx_dpdma_debugfs_desc_done_irq_write(char *args) 319 { 320 char *arg; 321 int ret; 322 u32 id; 323 324 arg = strsep(&args, " "); 325 if (!arg || strncasecmp(arg, "start", 5)) 326 return -EINVAL; 327 328 arg = strsep(&args, " "); 329 if (!arg) 330 return -EINVAL; 331 332 ret = kstrtou32(arg, 0, &id); 333 if (ret < 0) 334 return ret; 335 336 if (id < ZYNQMP_DPDMA_VIDEO0 || id > ZYNQMP_DPDMA_AUDIO1) 337 return -EINVAL; 338 339 dpdma_debugfs.testcase = DPDMA_TC_INTR_DONE; 340 dpdma_debugfs.xilinx_dpdma_irq_done_count = 0; 341 dpdma_debugfs.chan_id = id; 342 343 return 0; 344 } 345 346 /* Match xilinx_dpdma_testcases vs dpdma_debugfs_reqs[] entry */ 347 static struct xilinx_dpdma_debugfs_request dpdma_debugfs_reqs[] = { 348 { 349 .name = "DESCRIPTOR_DONE_INTR", 350 .tc = DPDMA_TC_INTR_DONE, 351 .read = xilinx_dpdma_debugfs_desc_done_irq_read, 352 .write = xilinx_dpdma_debugfs_desc_done_irq_write, 353 }, 354 }; 355 356 static ssize_t xilinx_dpdma_debugfs_read(struct file *f, char __user *buf, 357 size_t size, loff_t *pos) 358 { 359 enum xilinx_dpdma_testcases testcase; 360 char *kern_buff; 361 int ret = 0; 362 363 if (*pos != 0 || size <= 0) 364 return -EINVAL; 365 366 kern_buff = kzalloc(XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE, GFP_KERNEL); 367 if (!kern_buff) { 368 dpdma_debugfs.testcase = DPDMA_TC_NONE; 369 return -ENOMEM; 370 } 371 372 testcase = READ_ONCE(dpdma_debugfs.testcase); 373 if (testcase != DPDMA_TC_NONE) { 374 ret = dpdma_debugfs_reqs[testcase].read(kern_buff); 375 if (ret < 0) 376 goto done; 377 } else { 378 strlcpy(kern_buff, "No testcase executed", 379 XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE); 380 } 381 382 size = min(size, strlen(kern_buff)); 383 if (copy_to_user(buf, kern_buff, size)) 384 ret = -EFAULT; 385 386 done: 387 kfree(kern_buff); 388 if (ret) 389 return ret; 390 391 *pos = size + 1; 392 return size; 393 } 394 395 static ssize_t xilinx_dpdma_debugfs_write(struct file *f, 396 const char __user *buf, size_t size, 397 loff_t *pos) 398 { 399 char *kern_buff, *kern_buff_start; 400 char *testcase; 401 unsigned int i; 402 int ret; 403 404 if (*pos != 0 || size <= 0) 405 return -EINVAL; 406 407 /* Supporting single instance of test as of now. */ 408 if (dpdma_debugfs.testcase != DPDMA_TC_NONE) 409 return -EBUSY; 410 411 kern_buff = kzalloc(size, GFP_KERNEL); 412 if (!kern_buff) 413 return -ENOMEM; 414 kern_buff_start = kern_buff; 415 416 ret = strncpy_from_user(kern_buff, buf, size); 417 if (ret < 0) 418 goto done; 419 420 /* Read the testcase name from a user request. */ 421 testcase = strsep(&kern_buff, " "); 422 423 for (i = 0; i < ARRAY_SIZE(dpdma_debugfs_reqs); i++) { 424 if (!strcasecmp(testcase, dpdma_debugfs_reqs[i].name)) 425 break; 426 } 427 428 if (i == ARRAY_SIZE(dpdma_debugfs_reqs)) { 429 ret = -EINVAL; 430 goto done; 431 } 432 433 ret = dpdma_debugfs_reqs[i].write(kern_buff); 434 if (ret < 0) 435 goto done; 436 437 ret = size; 438 439 done: 440 kfree(kern_buff_start); 441 return ret; 442 } 443 444 static const struct file_operations fops_xilinx_dpdma_dbgfs = { 445 .owner = THIS_MODULE, 446 .read = xilinx_dpdma_debugfs_read, 447 .write = xilinx_dpdma_debugfs_write, 448 }; 449 450 static void xilinx_dpdma_debugfs_init(struct xilinx_dpdma_device *xdev) 451 { 452 struct dentry *dent; 453 454 dpdma_debugfs.testcase = DPDMA_TC_NONE; 455 456 dent = debugfs_create_file("testcase", 0444, xdev->common.dbg_dev_root, 457 NULL, &fops_xilinx_dpdma_dbgfs); 458 if (IS_ERR(dent)) 459 dev_err(xdev->dev, "Failed to create debugfs testcase file\n"); 460 } 461 462 /* ----------------------------------------------------------------------------- 463 * I/O Accessors 464 */ 465 466 static inline u32 dpdma_read(void __iomem *base, u32 offset) 467 { 468 return ioread32(base + offset); 469 } 470 471 static inline void dpdma_write(void __iomem *base, u32 offset, u32 val) 472 { 473 iowrite32(val, base + offset); 474 } 475 476 static inline void dpdma_clr(void __iomem *base, u32 offset, u32 clr) 477 { 478 dpdma_write(base, offset, dpdma_read(base, offset) & ~clr); 479 } 480 481 static inline void dpdma_set(void __iomem *base, u32 offset, u32 set) 482 { 483 dpdma_write(base, offset, dpdma_read(base, offset) | set); 484 } 485 486 /* ----------------------------------------------------------------------------- 487 * Descriptor Operations 488 */ 489 490 /** 491 * xilinx_dpdma_sw_desc_set_dma_addrs - Set DMA addresses in the descriptor 492 * @xdev: DPDMA device 493 * @sw_desc: The software descriptor in which to set DMA addresses 494 * @prev: The previous descriptor 495 * @dma_addr: array of dma addresses 496 * @num_src_addr: number of addresses in @dma_addr 497 * 498 * Set all the DMA addresses in the hardware descriptor corresponding to @dev 499 * from @dma_addr. If a previous descriptor is specified in @prev, its next 500 * descriptor DMA address is set to the DMA address of @sw_desc. @prev may be 501 * identical to @sw_desc for cyclic transfers. 502 */ 503 static void xilinx_dpdma_sw_desc_set_dma_addrs(struct xilinx_dpdma_device *xdev, 504 struct xilinx_dpdma_sw_desc *sw_desc, 505 struct xilinx_dpdma_sw_desc *prev, 506 dma_addr_t dma_addr[], 507 unsigned int num_src_addr) 508 { 509 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw; 510 unsigned int i; 511 512 hw_desc->src_addr = lower_32_bits(dma_addr[0]); 513 if (xdev->ext_addr) 514 hw_desc->addr_ext |= 515 FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_SRC_ADDR_MASK, 516 upper_32_bits(dma_addr[0])); 517 518 for (i = 1; i < num_src_addr; i++) { 519 u32 *addr = &hw_desc->src_addr2; 520 521 addr[i - 1] = lower_32_bits(dma_addr[i]); 522 523 if (xdev->ext_addr) { 524 u32 *addr_ext = &hw_desc->addr_ext_23; 525 u32 addr_msb; 526 527 addr_msb = upper_32_bits(dma_addr[i]) & GENMASK(15, 0); 528 addr_msb <<= 16 * ((i - 1) % 2); 529 addr_ext[(i - 1) / 2] |= addr_msb; 530 } 531 } 532 533 if (!prev) 534 return; 535 536 prev->hw.next_desc = lower_32_bits(sw_desc->dma_addr); 537 if (xdev->ext_addr) 538 prev->hw.addr_ext |= 539 FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK, 540 upper_32_bits(sw_desc->dma_addr)); 541 } 542 543 /** 544 * xilinx_dpdma_chan_alloc_sw_desc - Allocate a software descriptor 545 * @chan: DPDMA channel 546 * 547 * Allocate a software descriptor from the channel's descriptor pool. 548 * 549 * Return: a software descriptor or NULL. 550 */ 551 static struct xilinx_dpdma_sw_desc * 552 xilinx_dpdma_chan_alloc_sw_desc(struct xilinx_dpdma_chan *chan) 553 { 554 struct xilinx_dpdma_sw_desc *sw_desc; 555 dma_addr_t dma_addr; 556 557 sw_desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &dma_addr); 558 if (!sw_desc) 559 return NULL; 560 561 sw_desc->dma_addr = dma_addr; 562 563 return sw_desc; 564 } 565 566 /** 567 * xilinx_dpdma_chan_free_sw_desc - Free a software descriptor 568 * @chan: DPDMA channel 569 * @sw_desc: software descriptor to free 570 * 571 * Free a software descriptor from the channel's descriptor pool. 572 */ 573 static void 574 xilinx_dpdma_chan_free_sw_desc(struct xilinx_dpdma_chan *chan, 575 struct xilinx_dpdma_sw_desc *sw_desc) 576 { 577 dma_pool_free(chan->desc_pool, sw_desc, sw_desc->dma_addr); 578 } 579 580 /** 581 * xilinx_dpdma_chan_dump_tx_desc - Dump a tx descriptor 582 * @chan: DPDMA channel 583 * @tx_desc: tx descriptor to dump 584 * 585 * Dump contents of a tx descriptor 586 */ 587 static void xilinx_dpdma_chan_dump_tx_desc(struct xilinx_dpdma_chan *chan, 588 struct xilinx_dpdma_tx_desc *tx_desc) 589 { 590 struct xilinx_dpdma_sw_desc *sw_desc; 591 struct device *dev = chan->xdev->dev; 592 unsigned int i = 0; 593 594 dev_dbg(dev, "------- TX descriptor dump start -------\n"); 595 dev_dbg(dev, "------- channel ID = %d -------\n", chan->id); 596 597 list_for_each_entry(sw_desc, &tx_desc->descriptors, node) { 598 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw; 599 600 dev_dbg(dev, "------- HW descriptor %d -------\n", i++); 601 dev_dbg(dev, "descriptor DMA addr: %pad\n", &sw_desc->dma_addr); 602 dev_dbg(dev, "control: 0x%08x\n", hw_desc->control); 603 dev_dbg(dev, "desc_id: 0x%08x\n", hw_desc->desc_id); 604 dev_dbg(dev, "xfer_size: 0x%08x\n", hw_desc->xfer_size); 605 dev_dbg(dev, "hsize_stride: 0x%08x\n", hw_desc->hsize_stride); 606 dev_dbg(dev, "timestamp_lsb: 0x%08x\n", hw_desc->timestamp_lsb); 607 dev_dbg(dev, "timestamp_msb: 0x%08x\n", hw_desc->timestamp_msb); 608 dev_dbg(dev, "addr_ext: 0x%08x\n", hw_desc->addr_ext); 609 dev_dbg(dev, "next_desc: 0x%08x\n", hw_desc->next_desc); 610 dev_dbg(dev, "src_addr: 0x%08x\n", hw_desc->src_addr); 611 dev_dbg(dev, "addr_ext_23: 0x%08x\n", hw_desc->addr_ext_23); 612 dev_dbg(dev, "addr_ext_45: 0x%08x\n", hw_desc->addr_ext_45); 613 dev_dbg(dev, "src_addr2: 0x%08x\n", hw_desc->src_addr2); 614 dev_dbg(dev, "src_addr3: 0x%08x\n", hw_desc->src_addr3); 615 dev_dbg(dev, "src_addr4: 0x%08x\n", hw_desc->src_addr4); 616 dev_dbg(dev, "src_addr5: 0x%08x\n", hw_desc->src_addr5); 617 dev_dbg(dev, "crc: 0x%08x\n", hw_desc->crc); 618 } 619 620 dev_dbg(dev, "------- TX descriptor dump end -------\n"); 621 } 622 623 /** 624 * xilinx_dpdma_chan_alloc_tx_desc - Allocate a transaction descriptor 625 * @chan: DPDMA channel 626 * 627 * Allocate a tx descriptor. 628 * 629 * Return: a tx descriptor or NULL. 630 */ 631 static struct xilinx_dpdma_tx_desc * 632 xilinx_dpdma_chan_alloc_tx_desc(struct xilinx_dpdma_chan *chan) 633 { 634 struct xilinx_dpdma_tx_desc *tx_desc; 635 636 tx_desc = kzalloc(sizeof(*tx_desc), GFP_NOWAIT); 637 if (!tx_desc) 638 return NULL; 639 640 INIT_LIST_HEAD(&tx_desc->descriptors); 641 tx_desc->chan = chan; 642 tx_desc->error = false; 643 644 return tx_desc; 645 } 646 647 /** 648 * xilinx_dpdma_chan_free_tx_desc - Free a virtual DMA descriptor 649 * @vdesc: virtual DMA descriptor 650 * 651 * Free the virtual DMA descriptor @vdesc including its software descriptors. 652 */ 653 static void xilinx_dpdma_chan_free_tx_desc(struct virt_dma_desc *vdesc) 654 { 655 struct xilinx_dpdma_sw_desc *sw_desc, *next; 656 struct xilinx_dpdma_tx_desc *desc; 657 658 if (!vdesc) 659 return; 660 661 desc = to_dpdma_tx_desc(vdesc); 662 663 list_for_each_entry_safe(sw_desc, next, &desc->descriptors, node) { 664 list_del(&sw_desc->node); 665 xilinx_dpdma_chan_free_sw_desc(desc->chan, sw_desc); 666 } 667 668 kfree(desc); 669 } 670 671 /** 672 * xilinx_dpdma_chan_prep_interleaved_dma - Prepare an interleaved dma 673 * descriptor 674 * @chan: DPDMA channel 675 * @xt: dma interleaved template 676 * 677 * Prepare a tx descriptor including internal software/hardware descriptors 678 * based on @xt. 679 * 680 * Return: A DPDMA TX descriptor on success, or NULL. 681 */ 682 static struct xilinx_dpdma_tx_desc * 683 xilinx_dpdma_chan_prep_interleaved_dma(struct xilinx_dpdma_chan *chan, 684 struct dma_interleaved_template *xt) 685 { 686 struct xilinx_dpdma_tx_desc *tx_desc; 687 struct xilinx_dpdma_sw_desc *sw_desc; 688 struct xilinx_dpdma_hw_desc *hw_desc; 689 size_t hsize = xt->sgl[0].size; 690 size_t stride = hsize + xt->sgl[0].icg; 691 692 if (!IS_ALIGNED(xt->src_start, XILINX_DPDMA_ALIGN_BYTES)) { 693 dev_err(chan->xdev->dev, 694 "chan%u: buffer should be aligned at %d B\n", 695 chan->id, XILINX_DPDMA_ALIGN_BYTES); 696 return NULL; 697 } 698 699 tx_desc = xilinx_dpdma_chan_alloc_tx_desc(chan); 700 if (!tx_desc) 701 return NULL; 702 703 sw_desc = xilinx_dpdma_chan_alloc_sw_desc(chan); 704 if (!sw_desc) { 705 xilinx_dpdma_chan_free_tx_desc(&tx_desc->vdesc); 706 return NULL; 707 } 708 709 xilinx_dpdma_sw_desc_set_dma_addrs(chan->xdev, sw_desc, sw_desc, 710 &xt->src_start, 1); 711 712 hw_desc = &sw_desc->hw; 713 hsize = ALIGN(hsize, XILINX_DPDMA_LINESIZE_ALIGN_BITS / 8); 714 hw_desc->xfer_size = hsize * xt->numf; 715 hw_desc->hsize_stride = 716 FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK, hsize) | 717 FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK, 718 stride / 16); 719 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_PREEMBLE; 720 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR; 721 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE; 722 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME; 723 724 list_add_tail(&sw_desc->node, &tx_desc->descriptors); 725 726 return tx_desc; 727 } 728 729 /* ----------------------------------------------------------------------------- 730 * DPDMA Channel Operations 731 */ 732 733 /** 734 * xilinx_dpdma_chan_enable - Enable the channel 735 * @chan: DPDMA channel 736 * 737 * Enable the channel and its interrupts. Set the QoS values for video class. 738 */ 739 static void xilinx_dpdma_chan_enable(struct xilinx_dpdma_chan *chan) 740 { 741 u32 reg; 742 743 reg = (XILINX_DPDMA_INTR_CHAN_MASK << chan->id) 744 | XILINX_DPDMA_INTR_GLOBAL_MASK; 745 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg); 746 reg = (XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id) 747 | XILINX_DPDMA_INTR_GLOBAL_ERR; 748 dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg); 749 750 reg = XILINX_DPDMA_CH_CNTL_ENABLE 751 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DSCR_WR_MASK, 752 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS) 753 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DSCR_RD_MASK, 754 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS) 755 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DATA_RD_MASK, 756 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS); 757 dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, reg); 758 } 759 760 /** 761 * xilinx_dpdma_chan_disable - Disable the channel 762 * @chan: DPDMA channel 763 * 764 * Disable the channel and its interrupts. 765 */ 766 static void xilinx_dpdma_chan_disable(struct xilinx_dpdma_chan *chan) 767 { 768 u32 reg; 769 770 reg = XILINX_DPDMA_INTR_CHAN_MASK << chan->id; 771 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg); 772 reg = XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id; 773 dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg); 774 775 dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE); 776 } 777 778 /** 779 * xilinx_dpdma_chan_pause - Pause the channel 780 * @chan: DPDMA channel 781 * 782 * Pause the channel. 783 */ 784 static void xilinx_dpdma_chan_pause(struct xilinx_dpdma_chan *chan) 785 { 786 dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE); 787 } 788 789 /** 790 * xilinx_dpdma_chan_unpause - Unpause the channel 791 * @chan: DPDMA channel 792 * 793 * Unpause the channel. 794 */ 795 static void xilinx_dpdma_chan_unpause(struct xilinx_dpdma_chan *chan) 796 { 797 dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE); 798 } 799 800 static u32 xilinx_dpdma_chan_video_group_ready(struct xilinx_dpdma_chan *chan) 801 { 802 struct xilinx_dpdma_device *xdev = chan->xdev; 803 u32 channels = 0; 804 unsigned int i; 805 806 for (i = ZYNQMP_DPDMA_VIDEO0; i <= ZYNQMP_DPDMA_VIDEO2; i++) { 807 if (xdev->chan[i]->video_group && !xdev->chan[i]->running) 808 return 0; 809 810 if (xdev->chan[i]->video_group) 811 channels |= BIT(i); 812 } 813 814 return channels; 815 } 816 817 /** 818 * xilinx_dpdma_chan_queue_transfer - Queue the next transfer 819 * @chan: DPDMA channel 820 * 821 * Queue the next descriptor, if any, to the hardware. If the channel is 822 * stopped, start it first. Otherwise retrigger it with the next descriptor. 823 */ 824 static void xilinx_dpdma_chan_queue_transfer(struct xilinx_dpdma_chan *chan) 825 { 826 struct xilinx_dpdma_device *xdev = chan->xdev; 827 struct xilinx_dpdma_sw_desc *sw_desc; 828 struct xilinx_dpdma_tx_desc *desc; 829 struct virt_dma_desc *vdesc; 830 u32 reg, channels; 831 bool first_frame; 832 833 lockdep_assert_held(&chan->lock); 834 835 if (chan->desc.pending) 836 return; 837 838 if (!chan->running) { 839 xilinx_dpdma_chan_unpause(chan); 840 xilinx_dpdma_chan_enable(chan); 841 chan->first_frame = true; 842 chan->running = true; 843 } 844 845 vdesc = vchan_next_desc(&chan->vchan); 846 if (!vdesc) 847 return; 848 849 desc = to_dpdma_tx_desc(vdesc); 850 chan->desc.pending = desc; 851 list_del(&desc->vdesc.node); 852 853 /* 854 * Assign the cookie to descriptors in this transaction. Only 16 bit 855 * will be used, but it should be enough. 856 */ 857 list_for_each_entry(sw_desc, &desc->descriptors, node) 858 sw_desc->hw.desc_id = desc->vdesc.tx.cookie 859 & XILINX_DPDMA_CH_DESC_ID_MASK; 860 861 sw_desc = list_first_entry(&desc->descriptors, 862 struct xilinx_dpdma_sw_desc, node); 863 dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR, 864 lower_32_bits(sw_desc->dma_addr)); 865 if (xdev->ext_addr) 866 dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE, 867 FIELD_PREP(XILINX_DPDMA_CH_DESC_START_ADDRE_MASK, 868 upper_32_bits(sw_desc->dma_addr))); 869 870 first_frame = chan->first_frame; 871 chan->first_frame = false; 872 873 if (chan->video_group) { 874 channels = xilinx_dpdma_chan_video_group_ready(chan); 875 /* 876 * Trigger the transfer only when all channels in the group are 877 * ready. 878 */ 879 if (!channels) 880 return; 881 } else { 882 channels = BIT(chan->id); 883 } 884 885 if (first_frame) 886 reg = XILINX_DPDMA_GBL_TRIG_MASK(channels); 887 else 888 reg = XILINX_DPDMA_GBL_RETRIG_MASK(channels); 889 890 dpdma_write(xdev->reg, XILINX_DPDMA_GBL, reg); 891 } 892 893 /** 894 * xilinx_dpdma_chan_ostand - Number of outstanding transactions 895 * @chan: DPDMA channel 896 * 897 * Read and return the number of outstanding transactions from register. 898 * 899 * Return: Number of outstanding transactions from the status register. 900 */ 901 static u32 xilinx_dpdma_chan_ostand(struct xilinx_dpdma_chan *chan) 902 { 903 return FIELD_GET(XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK, 904 dpdma_read(chan->reg, XILINX_DPDMA_CH_STATUS)); 905 } 906 907 /** 908 * xilinx_dpdma_chan_notify_no_ostand - Notify no outstanding transaction event 909 * @chan: DPDMA channel 910 * 911 * Notify waiters for no outstanding event, so waiters can stop the channel 912 * safely. This function is supposed to be called when 'no outstanding' 913 * interrupt is generated. The 'no outstanding' interrupt is disabled and 914 * should be re-enabled when this event is handled. If the channel status 915 * register still shows some number of outstanding transactions, the interrupt 916 * remains enabled. 917 * 918 * Return: 0 on success. On failure, -EWOULDBLOCK if there's still outstanding 919 * transaction(s). 920 */ 921 static int xilinx_dpdma_chan_notify_no_ostand(struct xilinx_dpdma_chan *chan) 922 { 923 u32 cnt; 924 925 cnt = xilinx_dpdma_chan_ostand(chan); 926 if (cnt) { 927 dev_dbg(chan->xdev->dev, 928 "chan%u: %d outstanding transactions\n", 929 chan->id, cnt); 930 return -EWOULDBLOCK; 931 } 932 933 /* Disable 'no outstanding' interrupt */ 934 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IDS, 935 XILINX_DPDMA_INTR_NO_OSTAND(chan->id)); 936 wake_up(&chan->wait_to_stop); 937 938 return 0; 939 } 940 941 /** 942 * xilinx_dpdma_chan_wait_no_ostand - Wait for the no outstanding irq 943 * @chan: DPDMA channel 944 * 945 * Wait for the no outstanding transaction interrupt. This functions can sleep 946 * for 50ms. 947 * 948 * Return: 0 on success. On failure, -ETIMEOUT for time out, or the error code 949 * from wait_event_interruptible_timeout(). 950 */ 951 static int xilinx_dpdma_chan_wait_no_ostand(struct xilinx_dpdma_chan *chan) 952 { 953 int ret; 954 955 /* Wait for a no outstanding transaction interrupt upto 50msec */ 956 ret = wait_event_interruptible_timeout(chan->wait_to_stop, 957 !xilinx_dpdma_chan_ostand(chan), 958 msecs_to_jiffies(50)); 959 if (ret > 0) { 960 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, 961 XILINX_DPDMA_INTR_NO_OSTAND(chan->id)); 962 return 0; 963 } 964 965 dev_err(chan->xdev->dev, "chan%u: not ready to stop: %d trans\n", 966 chan->id, xilinx_dpdma_chan_ostand(chan)); 967 968 if (ret == 0) 969 return -ETIMEDOUT; 970 971 return ret; 972 } 973 974 /** 975 * xilinx_dpdma_chan_poll_no_ostand - Poll the outstanding transaction status 976 * @chan: DPDMA channel 977 * 978 * Poll the outstanding transaction status, and return when there's no 979 * outstanding transaction. This functions can be used in the interrupt context 980 * or where the atomicity is required. Calling thread may wait more than 50ms. 981 * 982 * Return: 0 on success, or -ETIMEDOUT. 983 */ 984 static int xilinx_dpdma_chan_poll_no_ostand(struct xilinx_dpdma_chan *chan) 985 { 986 u32 cnt, loop = 50000; 987 988 /* Poll at least for 50ms (20 fps). */ 989 do { 990 cnt = xilinx_dpdma_chan_ostand(chan); 991 udelay(1); 992 } while (loop-- > 0 && cnt); 993 994 if (loop) { 995 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, 996 XILINX_DPDMA_INTR_NO_OSTAND(chan->id)); 997 return 0; 998 } 999 1000 dev_err(chan->xdev->dev, "chan%u: not ready to stop: %d trans\n", 1001 chan->id, xilinx_dpdma_chan_ostand(chan)); 1002 1003 return -ETIMEDOUT; 1004 } 1005 1006 /** 1007 * xilinx_dpdma_chan_stop - Stop the channel 1008 * @chan: DPDMA channel 1009 * 1010 * Stop a previously paused channel by first waiting for completion of all 1011 * outstanding transaction and then disabling the channel. 1012 * 1013 * Return: 0 on success, or -ETIMEDOUT if the channel failed to stop. 1014 */ 1015 static int xilinx_dpdma_chan_stop(struct xilinx_dpdma_chan *chan) 1016 { 1017 unsigned long flags; 1018 int ret; 1019 1020 ret = xilinx_dpdma_chan_wait_no_ostand(chan); 1021 if (ret) 1022 return ret; 1023 1024 spin_lock_irqsave(&chan->lock, flags); 1025 xilinx_dpdma_chan_disable(chan); 1026 chan->running = false; 1027 spin_unlock_irqrestore(&chan->lock, flags); 1028 1029 return 0; 1030 } 1031 1032 /** 1033 * xilinx_dpdma_chan_done_irq - Handle hardware descriptor completion 1034 * @chan: DPDMA channel 1035 * 1036 * Handle completion of the currently active descriptor (@chan->desc.active). As 1037 * we currently support cyclic transfers only, this just invokes the cyclic 1038 * callback. The descriptor will be completed at the VSYNC interrupt when a new 1039 * descriptor replaces it. 1040 */ 1041 static void xilinx_dpdma_chan_done_irq(struct xilinx_dpdma_chan *chan) 1042 { 1043 struct xilinx_dpdma_tx_desc *active; 1044 unsigned long flags; 1045 1046 spin_lock_irqsave(&chan->lock, flags); 1047 1048 xilinx_dpdma_debugfs_desc_done_irq(chan); 1049 1050 active = chan->desc.active; 1051 if (active) 1052 vchan_cyclic_callback(&active->vdesc); 1053 else 1054 dev_warn(chan->xdev->dev, 1055 "chan%u: DONE IRQ with no active descriptor!\n", 1056 chan->id); 1057 1058 spin_unlock_irqrestore(&chan->lock, flags); 1059 } 1060 1061 /** 1062 * xilinx_dpdma_chan_vsync_irq - Handle hardware descriptor scheduling 1063 * @chan: DPDMA channel 1064 * 1065 * At VSYNC the active descriptor may have been replaced by the pending 1066 * descriptor. Detect this through the DESC_ID and perform appropriate 1067 * bookkeeping. 1068 */ 1069 static void xilinx_dpdma_chan_vsync_irq(struct xilinx_dpdma_chan *chan) 1070 { 1071 struct xilinx_dpdma_tx_desc *pending; 1072 struct xilinx_dpdma_sw_desc *sw_desc; 1073 unsigned long flags; 1074 u32 desc_id; 1075 1076 spin_lock_irqsave(&chan->lock, flags); 1077 1078 pending = chan->desc.pending; 1079 if (!chan->running || !pending) 1080 goto out; 1081 1082 desc_id = dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_ID) 1083 & XILINX_DPDMA_CH_DESC_ID_MASK; 1084 1085 /* If the retrigger raced with vsync, retry at the next frame. */ 1086 sw_desc = list_first_entry(&pending->descriptors, 1087 struct xilinx_dpdma_sw_desc, node); 1088 if (sw_desc->hw.desc_id != desc_id) { 1089 dev_dbg(chan->xdev->dev, 1090 "chan%u: vsync race lost (%u != %u), retrying\n", 1091 chan->id, sw_desc->hw.desc_id, desc_id); 1092 goto out; 1093 } 1094 1095 /* 1096 * Complete the active descriptor, if any, promote the pending 1097 * descriptor to active, and queue the next transfer, if any. 1098 */ 1099 if (chan->desc.active) 1100 vchan_cookie_complete(&chan->desc.active->vdesc); 1101 chan->desc.active = pending; 1102 chan->desc.pending = NULL; 1103 1104 xilinx_dpdma_chan_queue_transfer(chan); 1105 1106 out: 1107 spin_unlock_irqrestore(&chan->lock, flags); 1108 } 1109 1110 /** 1111 * xilinx_dpdma_chan_err - Detect any channel error 1112 * @chan: DPDMA channel 1113 * @isr: masked Interrupt Status Register 1114 * @eisr: Error Interrupt Status Register 1115 * 1116 * Return: true if any channel error occurs, or false otherwise. 1117 */ 1118 static bool 1119 xilinx_dpdma_chan_err(struct xilinx_dpdma_chan *chan, u32 isr, u32 eisr) 1120 { 1121 if (!chan) 1122 return false; 1123 1124 if (chan->running && 1125 ((isr & (XILINX_DPDMA_INTR_CHAN_ERR_MASK << chan->id)) || 1126 (eisr & (XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id)))) 1127 return true; 1128 1129 return false; 1130 } 1131 1132 /** 1133 * xilinx_dpdma_chan_handle_err - DPDMA channel error handling 1134 * @chan: DPDMA channel 1135 * 1136 * This function is called when any channel error or any global error occurs. 1137 * The function disables the paused channel by errors and determines 1138 * if the current active descriptor can be rescheduled depending on 1139 * the descriptor status. 1140 */ 1141 static void xilinx_dpdma_chan_handle_err(struct xilinx_dpdma_chan *chan) 1142 { 1143 struct xilinx_dpdma_device *xdev = chan->xdev; 1144 struct xilinx_dpdma_tx_desc *active; 1145 unsigned long flags; 1146 1147 spin_lock_irqsave(&chan->lock, flags); 1148 1149 dev_dbg(xdev->dev, "chan%u: cur desc addr = 0x%04x%08x\n", 1150 chan->id, 1151 dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE), 1152 dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR)); 1153 dev_dbg(xdev->dev, "chan%u: cur payload addr = 0x%04x%08x\n", 1154 chan->id, 1155 dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDRE), 1156 dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDR)); 1157 1158 xilinx_dpdma_chan_disable(chan); 1159 chan->running = false; 1160 1161 if (!chan->desc.active) 1162 goto out_unlock; 1163 1164 active = chan->desc.active; 1165 chan->desc.active = NULL; 1166 1167 xilinx_dpdma_chan_dump_tx_desc(chan, active); 1168 1169 if (active->error) 1170 dev_dbg(xdev->dev, "chan%u: repeated error on desc\n", 1171 chan->id); 1172 1173 /* Reschedule if there's no new descriptor */ 1174 if (!chan->desc.pending && 1175 list_empty(&chan->vchan.desc_issued)) { 1176 active->error = true; 1177 list_add_tail(&active->vdesc.node, 1178 &chan->vchan.desc_issued); 1179 } else { 1180 xilinx_dpdma_chan_free_tx_desc(&active->vdesc); 1181 } 1182 1183 out_unlock: 1184 spin_unlock_irqrestore(&chan->lock, flags); 1185 } 1186 1187 /* ----------------------------------------------------------------------------- 1188 * DMA Engine Operations 1189 */ 1190 1191 static struct dma_async_tx_descriptor * 1192 xilinx_dpdma_prep_interleaved_dma(struct dma_chan *dchan, 1193 struct dma_interleaved_template *xt, 1194 unsigned long flags) 1195 { 1196 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1197 struct xilinx_dpdma_tx_desc *desc; 1198 1199 if (xt->dir != DMA_MEM_TO_DEV) 1200 return NULL; 1201 1202 if (!xt->numf || !xt->sgl[0].size) 1203 return NULL; 1204 1205 if (!(flags & DMA_PREP_REPEAT) || !(flags & DMA_PREP_LOAD_EOT)) 1206 return NULL; 1207 1208 desc = xilinx_dpdma_chan_prep_interleaved_dma(chan, xt); 1209 if (!desc) 1210 return NULL; 1211 1212 vchan_tx_prep(&chan->vchan, &desc->vdesc, flags | DMA_CTRL_ACK); 1213 1214 return &desc->vdesc.tx; 1215 } 1216 1217 /** 1218 * xilinx_dpdma_alloc_chan_resources - Allocate resources for the channel 1219 * @dchan: DMA channel 1220 * 1221 * Allocate a descriptor pool for the channel. 1222 * 1223 * Return: 0 on success, or -ENOMEM if failed to allocate a pool. 1224 */ 1225 static int xilinx_dpdma_alloc_chan_resources(struct dma_chan *dchan) 1226 { 1227 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1228 size_t align = __alignof__(struct xilinx_dpdma_sw_desc); 1229 1230 chan->desc_pool = dma_pool_create(dev_name(chan->xdev->dev), 1231 chan->xdev->dev, 1232 sizeof(struct xilinx_dpdma_sw_desc), 1233 align, 0); 1234 if (!chan->desc_pool) { 1235 dev_err(chan->xdev->dev, 1236 "chan%u: failed to allocate a descriptor pool\n", 1237 chan->id); 1238 return -ENOMEM; 1239 } 1240 1241 return 0; 1242 } 1243 1244 /** 1245 * xilinx_dpdma_free_chan_resources - Free all resources for the channel 1246 * @dchan: DMA channel 1247 * 1248 * Free resources associated with the virtual DMA channel, and destroy the 1249 * descriptor pool. 1250 */ 1251 static void xilinx_dpdma_free_chan_resources(struct dma_chan *dchan) 1252 { 1253 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1254 1255 vchan_free_chan_resources(&chan->vchan); 1256 1257 dma_pool_destroy(chan->desc_pool); 1258 chan->desc_pool = NULL; 1259 } 1260 1261 static void xilinx_dpdma_issue_pending(struct dma_chan *dchan) 1262 { 1263 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1264 unsigned long flags; 1265 1266 spin_lock_irqsave(&chan->vchan.lock, flags); 1267 if (vchan_issue_pending(&chan->vchan)) 1268 xilinx_dpdma_chan_queue_transfer(chan); 1269 spin_unlock_irqrestore(&chan->vchan.lock, flags); 1270 } 1271 1272 static int xilinx_dpdma_config(struct dma_chan *dchan, 1273 struct dma_slave_config *config) 1274 { 1275 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1276 unsigned long flags; 1277 1278 /* 1279 * The destination address doesn't need to be specified as the DPDMA is 1280 * hardwired to the destination (the DP controller). The transfer 1281 * width, burst size and port window size are thus meaningless, they're 1282 * fixed both on the DPDMA side and on the DP controller side. 1283 */ 1284 1285 spin_lock_irqsave(&chan->lock, flags); 1286 1287 /* 1288 * Abuse the slave_id to indicate that the channel is part of a video 1289 * group. 1290 */ 1291 if (chan->id <= ZYNQMP_DPDMA_VIDEO2) 1292 chan->video_group = config->slave_id != 0; 1293 1294 spin_unlock_irqrestore(&chan->lock, flags); 1295 1296 return 0; 1297 } 1298 1299 static int xilinx_dpdma_pause(struct dma_chan *dchan) 1300 { 1301 xilinx_dpdma_chan_pause(to_xilinx_chan(dchan)); 1302 1303 return 0; 1304 } 1305 1306 static int xilinx_dpdma_resume(struct dma_chan *dchan) 1307 { 1308 xilinx_dpdma_chan_unpause(to_xilinx_chan(dchan)); 1309 1310 return 0; 1311 } 1312 1313 /** 1314 * xilinx_dpdma_terminate_all - Terminate the channel and descriptors 1315 * @dchan: DMA channel 1316 * 1317 * Pause the channel without waiting for ongoing transfers to complete. Waiting 1318 * for completion is performed by xilinx_dpdma_synchronize() that will disable 1319 * the channel to complete the stop. 1320 * 1321 * All the descriptors associated with the channel that are guaranteed not to 1322 * be touched by the hardware. The pending and active descriptor are not 1323 * touched, and will be freed either upon completion, or by 1324 * xilinx_dpdma_synchronize(). 1325 * 1326 * Return: 0 on success, or -ETIMEDOUT if the channel failed to stop. 1327 */ 1328 static int xilinx_dpdma_terminate_all(struct dma_chan *dchan) 1329 { 1330 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1331 struct xilinx_dpdma_device *xdev = chan->xdev; 1332 LIST_HEAD(descriptors); 1333 unsigned long flags; 1334 unsigned int i; 1335 1336 /* Pause the channel (including the whole video group if applicable). */ 1337 if (chan->video_group) { 1338 for (i = ZYNQMP_DPDMA_VIDEO0; i <= ZYNQMP_DPDMA_VIDEO2; i++) { 1339 if (xdev->chan[i]->video_group && 1340 xdev->chan[i]->running) { 1341 xilinx_dpdma_chan_pause(xdev->chan[i]); 1342 xdev->chan[i]->video_group = false; 1343 } 1344 } 1345 } else { 1346 xilinx_dpdma_chan_pause(chan); 1347 } 1348 1349 /* Gather all the descriptors we can free and free them. */ 1350 spin_lock_irqsave(&chan->vchan.lock, flags); 1351 vchan_get_all_descriptors(&chan->vchan, &descriptors); 1352 spin_unlock_irqrestore(&chan->vchan.lock, flags); 1353 1354 vchan_dma_desc_free_list(&chan->vchan, &descriptors); 1355 1356 return 0; 1357 } 1358 1359 /** 1360 * xilinx_dpdma_synchronize - Synchronize callback execution 1361 * @dchan: DMA channel 1362 * 1363 * Synchronizing callback execution ensures that all previously issued 1364 * transfers have completed and all associated callbacks have been called and 1365 * have returned. 1366 * 1367 * This function waits for the DMA channel to stop. It assumes it has been 1368 * paused by a previous call to dmaengine_terminate_async(), and that no new 1369 * pending descriptors have been issued with dma_async_issue_pending(). The 1370 * behaviour is undefined otherwise. 1371 */ 1372 static void xilinx_dpdma_synchronize(struct dma_chan *dchan) 1373 { 1374 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1375 unsigned long flags; 1376 1377 xilinx_dpdma_chan_stop(chan); 1378 1379 spin_lock_irqsave(&chan->vchan.lock, flags); 1380 if (chan->desc.pending) { 1381 vchan_terminate_vdesc(&chan->desc.pending->vdesc); 1382 chan->desc.pending = NULL; 1383 } 1384 if (chan->desc.active) { 1385 vchan_terminate_vdesc(&chan->desc.active->vdesc); 1386 chan->desc.active = NULL; 1387 } 1388 spin_unlock_irqrestore(&chan->vchan.lock, flags); 1389 1390 vchan_synchronize(&chan->vchan); 1391 } 1392 1393 /* ----------------------------------------------------------------------------- 1394 * Interrupt and Tasklet Handling 1395 */ 1396 1397 /** 1398 * xilinx_dpdma_err - Detect any global error 1399 * @isr: Interrupt Status Register 1400 * @eisr: Error Interrupt Status Register 1401 * 1402 * Return: True if any global error occurs, or false otherwise. 1403 */ 1404 static bool xilinx_dpdma_err(u32 isr, u32 eisr) 1405 { 1406 if (isr & XILINX_DPDMA_INTR_GLOBAL_ERR || 1407 eisr & XILINX_DPDMA_EINTR_GLOBAL_ERR) 1408 return true; 1409 1410 return false; 1411 } 1412 1413 /** 1414 * xilinx_dpdma_handle_err_irq - Handle DPDMA error interrupt 1415 * @xdev: DPDMA device 1416 * @isr: masked Interrupt Status Register 1417 * @eisr: Error Interrupt Status Register 1418 * 1419 * Handle if any error occurs based on @isr and @eisr. This function disables 1420 * corresponding error interrupts, and those should be re-enabled once handling 1421 * is done. 1422 */ 1423 static void xilinx_dpdma_handle_err_irq(struct xilinx_dpdma_device *xdev, 1424 u32 isr, u32 eisr) 1425 { 1426 bool err = xilinx_dpdma_err(isr, eisr); 1427 unsigned int i; 1428 1429 dev_dbg_ratelimited(xdev->dev, 1430 "error irq: isr = 0x%08x, eisr = 0x%08x\n", 1431 isr, eisr); 1432 1433 /* Disable channel error interrupts until errors are handled. */ 1434 dpdma_write(xdev->reg, XILINX_DPDMA_IDS, 1435 isr & ~XILINX_DPDMA_INTR_GLOBAL_ERR); 1436 dpdma_write(xdev->reg, XILINX_DPDMA_EIDS, 1437 eisr & ~XILINX_DPDMA_EINTR_GLOBAL_ERR); 1438 1439 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) 1440 if (err || xilinx_dpdma_chan_err(xdev->chan[i], isr, eisr)) 1441 tasklet_schedule(&xdev->chan[i]->err_task); 1442 } 1443 1444 /** 1445 * xilinx_dpdma_enable_irq - Enable interrupts 1446 * @xdev: DPDMA device 1447 * 1448 * Enable interrupts. 1449 */ 1450 static void xilinx_dpdma_enable_irq(struct xilinx_dpdma_device *xdev) 1451 { 1452 dpdma_write(xdev->reg, XILINX_DPDMA_IEN, XILINX_DPDMA_INTR_ALL); 1453 dpdma_write(xdev->reg, XILINX_DPDMA_EIEN, XILINX_DPDMA_EINTR_ALL); 1454 } 1455 1456 /** 1457 * xilinx_dpdma_disable_irq - Disable interrupts 1458 * @xdev: DPDMA device 1459 * 1460 * Disable interrupts. 1461 */ 1462 static void xilinx_dpdma_disable_irq(struct xilinx_dpdma_device *xdev) 1463 { 1464 dpdma_write(xdev->reg, XILINX_DPDMA_IDS, XILINX_DPDMA_INTR_ALL); 1465 dpdma_write(xdev->reg, XILINX_DPDMA_EIDS, XILINX_DPDMA_EINTR_ALL); 1466 } 1467 1468 /** 1469 * xilinx_dpdma_chan_err_task - Per channel tasklet for error handling 1470 * @t: pointer to the tasklet associated with this handler 1471 * 1472 * Per channel error handling tasklet. This function waits for the outstanding 1473 * transaction to complete and triggers error handling. After error handling, 1474 * re-enable channel error interrupts, and restart the channel if needed. 1475 */ 1476 static void xilinx_dpdma_chan_err_task(struct tasklet_struct *t) 1477 { 1478 struct xilinx_dpdma_chan *chan = from_tasklet(chan, t, err_task); 1479 struct xilinx_dpdma_device *xdev = chan->xdev; 1480 unsigned long flags; 1481 1482 /* Proceed error handling even when polling fails. */ 1483 xilinx_dpdma_chan_poll_no_ostand(chan); 1484 1485 xilinx_dpdma_chan_handle_err(chan); 1486 1487 dpdma_write(xdev->reg, XILINX_DPDMA_IEN, 1488 XILINX_DPDMA_INTR_CHAN_ERR_MASK << chan->id); 1489 dpdma_write(xdev->reg, XILINX_DPDMA_EIEN, 1490 XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id); 1491 1492 spin_lock_irqsave(&chan->lock, flags); 1493 xilinx_dpdma_chan_queue_transfer(chan); 1494 spin_unlock_irqrestore(&chan->lock, flags); 1495 } 1496 1497 static irqreturn_t xilinx_dpdma_irq_handler(int irq, void *data) 1498 { 1499 struct xilinx_dpdma_device *xdev = data; 1500 unsigned long mask; 1501 unsigned int i; 1502 u32 status; 1503 u32 error; 1504 1505 status = dpdma_read(xdev->reg, XILINX_DPDMA_ISR); 1506 error = dpdma_read(xdev->reg, XILINX_DPDMA_EISR); 1507 if (!status && !error) 1508 return IRQ_NONE; 1509 1510 dpdma_write(xdev->reg, XILINX_DPDMA_ISR, status); 1511 dpdma_write(xdev->reg, XILINX_DPDMA_EISR, error); 1512 1513 if (status & XILINX_DPDMA_INTR_VSYNC) { 1514 /* 1515 * There's a single VSYNC interrupt that needs to be processed 1516 * by each running channel to update the active descriptor. 1517 */ 1518 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) { 1519 struct xilinx_dpdma_chan *chan = xdev->chan[i]; 1520 1521 if (chan) 1522 xilinx_dpdma_chan_vsync_irq(chan); 1523 } 1524 } 1525 1526 mask = FIELD_GET(XILINX_DPDMA_INTR_DESC_DONE_MASK, status); 1527 if (mask) { 1528 for_each_set_bit(i, &mask, ARRAY_SIZE(xdev->chan)) 1529 xilinx_dpdma_chan_done_irq(xdev->chan[i]); 1530 } 1531 1532 mask = FIELD_GET(XILINX_DPDMA_INTR_NO_OSTAND_MASK, status); 1533 if (mask) { 1534 for_each_set_bit(i, &mask, ARRAY_SIZE(xdev->chan)) 1535 xilinx_dpdma_chan_notify_no_ostand(xdev->chan[i]); 1536 } 1537 1538 mask = status & XILINX_DPDMA_INTR_ERR_ALL; 1539 if (mask || error) 1540 xilinx_dpdma_handle_err_irq(xdev, mask, error); 1541 1542 return IRQ_HANDLED; 1543 } 1544 1545 /* ----------------------------------------------------------------------------- 1546 * Initialization & Cleanup 1547 */ 1548 1549 static int xilinx_dpdma_chan_init(struct xilinx_dpdma_device *xdev, 1550 unsigned int chan_id) 1551 { 1552 struct xilinx_dpdma_chan *chan; 1553 1554 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL); 1555 if (!chan) 1556 return -ENOMEM; 1557 1558 chan->id = chan_id; 1559 chan->reg = xdev->reg + XILINX_DPDMA_CH_BASE 1560 + XILINX_DPDMA_CH_OFFSET * chan->id; 1561 chan->running = false; 1562 chan->xdev = xdev; 1563 1564 spin_lock_init(&chan->lock); 1565 init_waitqueue_head(&chan->wait_to_stop); 1566 1567 tasklet_setup(&chan->err_task, xilinx_dpdma_chan_err_task); 1568 1569 chan->vchan.desc_free = xilinx_dpdma_chan_free_tx_desc; 1570 vchan_init(&chan->vchan, &xdev->common); 1571 1572 xdev->chan[chan->id] = chan; 1573 1574 return 0; 1575 } 1576 1577 static void xilinx_dpdma_chan_remove(struct xilinx_dpdma_chan *chan) 1578 { 1579 if (!chan) 1580 return; 1581 1582 tasklet_kill(&chan->err_task); 1583 list_del(&chan->vchan.chan.device_node); 1584 } 1585 1586 static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec, 1587 struct of_dma *ofdma) 1588 { 1589 struct xilinx_dpdma_device *xdev = ofdma->of_dma_data; 1590 u32 chan_id = dma_spec->args[0]; 1591 1592 if (chan_id >= ARRAY_SIZE(xdev->chan)) 1593 return NULL; 1594 1595 if (!xdev->chan[chan_id]) 1596 return NULL; 1597 1598 return dma_get_slave_channel(&xdev->chan[chan_id]->vchan.chan); 1599 } 1600 1601 static void dpdma_hw_init(struct xilinx_dpdma_device *xdev) 1602 { 1603 unsigned int i; 1604 void __iomem *reg; 1605 1606 /* Disable all interrupts */ 1607 xilinx_dpdma_disable_irq(xdev); 1608 1609 /* Stop all channels */ 1610 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) { 1611 reg = xdev->reg + XILINX_DPDMA_CH_BASE 1612 + XILINX_DPDMA_CH_OFFSET * i; 1613 dpdma_clr(reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE); 1614 } 1615 1616 /* Clear the interrupt status registers */ 1617 dpdma_write(xdev->reg, XILINX_DPDMA_ISR, XILINX_DPDMA_INTR_ALL); 1618 dpdma_write(xdev->reg, XILINX_DPDMA_EISR, XILINX_DPDMA_EINTR_ALL); 1619 } 1620 1621 static int xilinx_dpdma_probe(struct platform_device *pdev) 1622 { 1623 struct xilinx_dpdma_device *xdev; 1624 struct dma_device *ddev; 1625 unsigned int i; 1626 int ret; 1627 1628 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL); 1629 if (!xdev) 1630 return -ENOMEM; 1631 1632 xdev->dev = &pdev->dev; 1633 xdev->ext_addr = sizeof(dma_addr_t) > 4; 1634 1635 INIT_LIST_HEAD(&xdev->common.channels); 1636 1637 platform_set_drvdata(pdev, xdev); 1638 1639 xdev->axi_clk = devm_clk_get(xdev->dev, "axi_clk"); 1640 if (IS_ERR(xdev->axi_clk)) 1641 return PTR_ERR(xdev->axi_clk); 1642 1643 xdev->reg = devm_platform_ioremap_resource(pdev, 0); 1644 if (IS_ERR(xdev->reg)) 1645 return PTR_ERR(xdev->reg); 1646 1647 dpdma_hw_init(xdev); 1648 1649 xdev->irq = platform_get_irq(pdev, 0); 1650 if (xdev->irq < 0) { 1651 dev_err(xdev->dev, "failed to get platform irq\n"); 1652 return xdev->irq; 1653 } 1654 1655 ret = request_irq(xdev->irq, xilinx_dpdma_irq_handler, IRQF_SHARED, 1656 dev_name(xdev->dev), xdev); 1657 if (ret) { 1658 dev_err(xdev->dev, "failed to request IRQ\n"); 1659 return ret; 1660 } 1661 1662 ddev = &xdev->common; 1663 ddev->dev = &pdev->dev; 1664 1665 dma_cap_set(DMA_SLAVE, ddev->cap_mask); 1666 dma_cap_set(DMA_PRIVATE, ddev->cap_mask); 1667 dma_cap_set(DMA_INTERLEAVE, ddev->cap_mask); 1668 dma_cap_set(DMA_REPEAT, ddev->cap_mask); 1669 dma_cap_set(DMA_LOAD_EOT, ddev->cap_mask); 1670 ddev->copy_align = fls(XILINX_DPDMA_ALIGN_BYTES - 1); 1671 1672 ddev->device_alloc_chan_resources = xilinx_dpdma_alloc_chan_resources; 1673 ddev->device_free_chan_resources = xilinx_dpdma_free_chan_resources; 1674 ddev->device_prep_interleaved_dma = xilinx_dpdma_prep_interleaved_dma; 1675 /* TODO: Can we achieve better granularity ? */ 1676 ddev->device_tx_status = dma_cookie_status; 1677 ddev->device_issue_pending = xilinx_dpdma_issue_pending; 1678 ddev->device_config = xilinx_dpdma_config; 1679 ddev->device_pause = xilinx_dpdma_pause; 1680 ddev->device_resume = xilinx_dpdma_resume; 1681 ddev->device_terminate_all = xilinx_dpdma_terminate_all; 1682 ddev->device_synchronize = xilinx_dpdma_synchronize; 1683 ddev->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED); 1684 ddev->directions = BIT(DMA_MEM_TO_DEV); 1685 ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; 1686 1687 for (i = 0; i < ARRAY_SIZE(xdev->chan); ++i) { 1688 ret = xilinx_dpdma_chan_init(xdev, i); 1689 if (ret < 0) { 1690 dev_err(xdev->dev, "failed to initialize channel %u\n", 1691 i); 1692 goto error; 1693 } 1694 } 1695 1696 ret = clk_prepare_enable(xdev->axi_clk); 1697 if (ret) { 1698 dev_err(xdev->dev, "failed to enable the axi clock\n"); 1699 goto error; 1700 } 1701 1702 ret = dma_async_device_register(ddev); 1703 if (ret) { 1704 dev_err(xdev->dev, "failed to register the dma device\n"); 1705 goto error_dma_async; 1706 } 1707 1708 ret = of_dma_controller_register(xdev->dev->of_node, 1709 of_dma_xilinx_xlate, ddev); 1710 if (ret) { 1711 dev_err(xdev->dev, "failed to register DMA to DT DMA helper\n"); 1712 goto error_of_dma; 1713 } 1714 1715 xilinx_dpdma_enable_irq(xdev); 1716 1717 xilinx_dpdma_debugfs_init(xdev); 1718 1719 dev_info(&pdev->dev, "Xilinx DPDMA engine is probed\n"); 1720 1721 return 0; 1722 1723 error_of_dma: 1724 dma_async_device_unregister(ddev); 1725 error_dma_async: 1726 clk_disable_unprepare(xdev->axi_clk); 1727 error: 1728 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) 1729 xilinx_dpdma_chan_remove(xdev->chan[i]); 1730 1731 free_irq(xdev->irq, xdev); 1732 1733 return ret; 1734 } 1735 1736 static int xilinx_dpdma_remove(struct platform_device *pdev) 1737 { 1738 struct xilinx_dpdma_device *xdev = platform_get_drvdata(pdev); 1739 unsigned int i; 1740 1741 /* Start by disabling the IRQ to avoid races during cleanup. */ 1742 free_irq(xdev->irq, xdev); 1743 1744 xilinx_dpdma_disable_irq(xdev); 1745 of_dma_controller_free(pdev->dev.of_node); 1746 dma_async_device_unregister(&xdev->common); 1747 clk_disable_unprepare(xdev->axi_clk); 1748 1749 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) 1750 xilinx_dpdma_chan_remove(xdev->chan[i]); 1751 1752 return 0; 1753 } 1754 1755 static const struct of_device_id xilinx_dpdma_of_match[] = { 1756 { .compatible = "xlnx,zynqmp-dpdma",}, 1757 { /* end of table */ }, 1758 }; 1759 MODULE_DEVICE_TABLE(of, xilinx_dpdma_of_match); 1760 1761 static struct platform_driver xilinx_dpdma_driver = { 1762 .probe = xilinx_dpdma_probe, 1763 .remove = xilinx_dpdma_remove, 1764 .driver = { 1765 .name = "xilinx-zynqmp-dpdma", 1766 .of_match_table = xilinx_dpdma_of_match, 1767 }, 1768 }; 1769 1770 module_platform_driver(xilinx_dpdma_driver); 1771 1772 MODULE_AUTHOR("Xilinx, Inc."); 1773 MODULE_DESCRIPTION("Xilinx ZynqMP DPDMA driver"); 1774 MODULE_LICENSE("GPL v2"); 1775