1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Xilinx ZynqMP DPDMA Engine driver 4 * 5 * Copyright (C) 2015 - 2020 Xilinx, Inc. 6 * 7 * Author: Hyun Woo Kwon <hyun.kwon@xilinx.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/clk.h> 13 #include <linux/debugfs.h> 14 #include <linux/delay.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dmapool.h> 17 #include <linux/interrupt.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_dma.h> 21 #include <linux/platform_device.h> 22 #include <linux/sched.h> 23 #include <linux/slab.h> 24 #include <linux/spinlock.h> 25 #include <linux/wait.h> 26 27 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> 28 29 #include "../dmaengine.h" 30 #include "../virt-dma.h" 31 32 /* DPDMA registers */ 33 #define XILINX_DPDMA_ERR_CTRL 0x000 34 #define XILINX_DPDMA_ISR 0x004 35 #define XILINX_DPDMA_IMR 0x008 36 #define XILINX_DPDMA_IEN 0x00c 37 #define XILINX_DPDMA_IDS 0x010 38 #define XILINX_DPDMA_INTR_DESC_DONE(n) BIT((n) + 0) 39 #define XILINX_DPDMA_INTR_DESC_DONE_MASK GENMASK(5, 0) 40 #define XILINX_DPDMA_INTR_NO_OSTAND(n) BIT((n) + 6) 41 #define XILINX_DPDMA_INTR_NO_OSTAND_MASK GENMASK(11, 6) 42 #define XILINX_DPDMA_INTR_AXI_ERR(n) BIT((n) + 12) 43 #define XILINX_DPDMA_INTR_AXI_ERR_MASK GENMASK(17, 12) 44 #define XILINX_DPDMA_INTR_DESC_ERR(n) BIT((n) + 16) 45 #define XILINX_DPDMA_INTR_DESC_ERR_MASK GENMASK(23, 18) 46 #define XILINX_DPDMA_INTR_WR_CMD_FIFO_FULL BIT(24) 47 #define XILINX_DPDMA_INTR_WR_DATA_FIFO_FULL BIT(25) 48 #define XILINX_DPDMA_INTR_AXI_4K_CROSS BIT(26) 49 #define XILINX_DPDMA_INTR_VSYNC BIT(27) 50 #define XILINX_DPDMA_INTR_CHAN_ERR_MASK 0x00041000 51 #define XILINX_DPDMA_INTR_CHAN_ERR 0x00fff000 52 #define XILINX_DPDMA_INTR_GLOBAL_ERR 0x07000000 53 #define XILINX_DPDMA_INTR_ERR_ALL 0x07fff000 54 #define XILINX_DPDMA_INTR_CHAN_MASK 0x00041041 55 #define XILINX_DPDMA_INTR_GLOBAL_MASK 0x0f000000 56 #define XILINX_DPDMA_INTR_ALL 0x0fffffff 57 #define XILINX_DPDMA_EISR 0x014 58 #define XILINX_DPDMA_EIMR 0x018 59 #define XILINX_DPDMA_EIEN 0x01c 60 #define XILINX_DPDMA_EIDS 0x020 61 #define XILINX_DPDMA_EINTR_INV_APB BIT(0) 62 #define XILINX_DPDMA_EINTR_RD_AXI_ERR(n) BIT((n) + 1) 63 #define XILINX_DPDMA_EINTR_RD_AXI_ERR_MASK GENMASK(6, 1) 64 #define XILINX_DPDMA_EINTR_PRE_ERR(n) BIT((n) + 7) 65 #define XILINX_DPDMA_EINTR_PRE_ERR_MASK GENMASK(12, 7) 66 #define XILINX_DPDMA_EINTR_CRC_ERR(n) BIT((n) + 13) 67 #define XILINX_DPDMA_EINTR_CRC_ERR_MASK GENMASK(18, 13) 68 #define XILINX_DPDMA_EINTR_WR_AXI_ERR(n) BIT((n) + 19) 69 #define XILINX_DPDMA_EINTR_WR_AXI_ERR_MASK GENMASK(24, 19) 70 #define XILINX_DPDMA_EINTR_DESC_DONE_ERR(n) BIT((n) + 25) 71 #define XILINX_DPDMA_EINTR_DESC_DONE_ERR_MASK GENMASK(30, 25) 72 #define XILINX_DPDMA_EINTR_RD_CMD_FIFO_FULL BIT(32) 73 #define XILINX_DPDMA_EINTR_CHAN_ERR_MASK 0x02082082 74 #define XILINX_DPDMA_EINTR_CHAN_ERR 0x7ffffffe 75 #define XILINX_DPDMA_EINTR_GLOBAL_ERR 0x80000001 76 #define XILINX_DPDMA_EINTR_ALL 0xffffffff 77 #define XILINX_DPDMA_CNTL 0x100 78 #define XILINX_DPDMA_GBL 0x104 79 #define XILINX_DPDMA_GBL_TRIG_MASK(n) ((n) << 0) 80 #define XILINX_DPDMA_GBL_RETRIG_MASK(n) ((n) << 6) 81 #define XILINX_DPDMA_ALC0_CNTL 0x108 82 #define XILINX_DPDMA_ALC0_STATUS 0x10c 83 #define XILINX_DPDMA_ALC0_MAX 0x110 84 #define XILINX_DPDMA_ALC0_MIN 0x114 85 #define XILINX_DPDMA_ALC0_ACC 0x118 86 #define XILINX_DPDMA_ALC0_ACC_TRAN 0x11c 87 #define XILINX_DPDMA_ALC1_CNTL 0x120 88 #define XILINX_DPDMA_ALC1_STATUS 0x124 89 #define XILINX_DPDMA_ALC1_MAX 0x128 90 #define XILINX_DPDMA_ALC1_MIN 0x12c 91 #define XILINX_DPDMA_ALC1_ACC 0x130 92 #define XILINX_DPDMA_ALC1_ACC_TRAN 0x134 93 94 /* Channel register */ 95 #define XILINX_DPDMA_CH_BASE 0x200 96 #define XILINX_DPDMA_CH_OFFSET 0x100 97 #define XILINX_DPDMA_CH_DESC_START_ADDRE 0x000 98 #define XILINX_DPDMA_CH_DESC_START_ADDRE_MASK GENMASK(15, 0) 99 #define XILINX_DPDMA_CH_DESC_START_ADDR 0x004 100 #define XILINX_DPDMA_CH_DESC_NEXT_ADDRE 0x008 101 #define XILINX_DPDMA_CH_DESC_NEXT_ADDR 0x00c 102 #define XILINX_DPDMA_CH_PYLD_CUR_ADDRE 0x010 103 #define XILINX_DPDMA_CH_PYLD_CUR_ADDR 0x014 104 #define XILINX_DPDMA_CH_CNTL 0x018 105 #define XILINX_DPDMA_CH_CNTL_ENABLE BIT(0) 106 #define XILINX_DPDMA_CH_CNTL_PAUSE BIT(1) 107 #define XILINX_DPDMA_CH_CNTL_QOS_DSCR_WR_MASK GENMASK(5, 2) 108 #define XILINX_DPDMA_CH_CNTL_QOS_DSCR_RD_MASK GENMASK(9, 6) 109 #define XILINX_DPDMA_CH_CNTL_QOS_DATA_RD_MASK GENMASK(13, 10) 110 #define XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS 11 111 #define XILINX_DPDMA_CH_STATUS 0x01c 112 #define XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK GENMASK(24, 21) 113 #define XILINX_DPDMA_CH_VDO 0x020 114 #define XILINX_DPDMA_CH_PYLD_SZ 0x024 115 #define XILINX_DPDMA_CH_DESC_ID 0x028 116 117 /* DPDMA descriptor fields */ 118 #define XILINX_DPDMA_DESC_CONTROL_PREEMBLE 0xa5 119 #define XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR BIT(8) 120 #define XILINX_DPDMA_DESC_CONTROL_DESC_UPDATE BIT(9) 121 #define XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE BIT(10) 122 #define XILINX_DPDMA_DESC_CONTROL_FRAG_MODE BIT(18) 123 #define XILINX_DPDMA_DESC_CONTROL_LAST BIT(19) 124 #define XILINX_DPDMA_DESC_CONTROL_ENABLE_CRC BIT(20) 125 #define XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME BIT(21) 126 #define XILINX_DPDMA_DESC_ID_MASK GENMASK(15, 0) 127 #define XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK GENMASK(17, 0) 128 #define XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK GENMASK(31, 18) 129 #define XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK GENMASK(15, 0) 130 #define XILINX_DPDMA_DESC_ADDR_EXT_SRC_ADDR_MASK GENMASK(31, 16) 131 132 #define XILINX_DPDMA_ALIGN_BYTES 256 133 #define XILINX_DPDMA_LINESIZE_ALIGN_BITS 128 134 135 #define XILINX_DPDMA_NUM_CHAN 6 136 137 struct xilinx_dpdma_chan; 138 139 /** 140 * struct xilinx_dpdma_hw_desc - DPDMA hardware descriptor 141 * @control: control configuration field 142 * @desc_id: descriptor ID 143 * @xfer_size: transfer size 144 * @hsize_stride: horizontal size and stride 145 * @timestamp_lsb: LSB of time stamp 146 * @timestamp_msb: MSB of time stamp 147 * @addr_ext: upper 16 bit of 48 bit address (next_desc and src_addr) 148 * @next_desc: next descriptor 32 bit address 149 * @src_addr: payload source address (1st page, 32 LSB) 150 * @addr_ext_23: payload source address (3nd and 3rd pages, 16 LSBs) 151 * @addr_ext_45: payload source address (4th and 5th pages, 16 LSBs) 152 * @src_addr2: payload source address (2nd page, 32 LSB) 153 * @src_addr3: payload source address (3rd page, 32 LSB) 154 * @src_addr4: payload source address (4th page, 32 LSB) 155 * @src_addr5: payload source address (5th page, 32 LSB) 156 * @crc: descriptor CRC 157 */ 158 struct xilinx_dpdma_hw_desc { 159 u32 control; 160 u32 desc_id; 161 u32 xfer_size; 162 u32 hsize_stride; 163 u32 timestamp_lsb; 164 u32 timestamp_msb; 165 u32 addr_ext; 166 u32 next_desc; 167 u32 src_addr; 168 u32 addr_ext_23; 169 u32 addr_ext_45; 170 u32 src_addr2; 171 u32 src_addr3; 172 u32 src_addr4; 173 u32 src_addr5; 174 u32 crc; 175 } __aligned(XILINX_DPDMA_ALIGN_BYTES); 176 177 /** 178 * struct xilinx_dpdma_sw_desc - DPDMA software descriptor 179 * @hw: DPDMA hardware descriptor 180 * @node: list node for software descriptors 181 * @dma_addr: DMA address of the software descriptor 182 */ 183 struct xilinx_dpdma_sw_desc { 184 struct xilinx_dpdma_hw_desc hw; 185 struct list_head node; 186 dma_addr_t dma_addr; 187 }; 188 189 /** 190 * struct xilinx_dpdma_tx_desc - DPDMA transaction descriptor 191 * @vdesc: virtual DMA descriptor 192 * @chan: DMA channel 193 * @descriptors: list of software descriptors 194 * @error: an error has been detected with this descriptor 195 */ 196 struct xilinx_dpdma_tx_desc { 197 struct virt_dma_desc vdesc; 198 struct xilinx_dpdma_chan *chan; 199 struct list_head descriptors; 200 bool error; 201 }; 202 203 #define to_dpdma_tx_desc(_desc) \ 204 container_of(_desc, struct xilinx_dpdma_tx_desc, vdesc) 205 206 /** 207 * struct xilinx_dpdma_chan - DPDMA channel 208 * @vchan: virtual DMA channel 209 * @reg: register base address 210 * @id: channel ID 211 * @wait_to_stop: queue to wait for outstanding transacitons before stopping 212 * @running: true if the channel is running 213 * @first_frame: flag for the first frame of stream 214 * @video_group: flag if multi-channel operation is needed for video channels 215 * @lock: lock to access struct xilinx_dpdma_chan 216 * @desc_pool: descriptor allocation pool 217 * @err_task: error IRQ bottom half handler 218 * @desc: References to descriptors being processed 219 * @desc.pending: Descriptor schedule to the hardware, pending execution 220 * @desc.active: Descriptor being executed by the hardware 221 * @xdev: DPDMA device 222 */ 223 struct xilinx_dpdma_chan { 224 struct virt_dma_chan vchan; 225 void __iomem *reg; 226 unsigned int id; 227 228 wait_queue_head_t wait_to_stop; 229 bool running; 230 bool first_frame; 231 bool video_group; 232 233 spinlock_t lock; /* lock to access struct xilinx_dpdma_chan */ 234 struct dma_pool *desc_pool; 235 struct tasklet_struct err_task; 236 237 struct { 238 struct xilinx_dpdma_tx_desc *pending; 239 struct xilinx_dpdma_tx_desc *active; 240 } desc; 241 242 struct xilinx_dpdma_device *xdev; 243 }; 244 245 #define to_xilinx_chan(_chan) \ 246 container_of(_chan, struct xilinx_dpdma_chan, vchan.chan) 247 248 /** 249 * struct xilinx_dpdma_device - DPDMA device 250 * @common: generic dma device structure 251 * @reg: register base address 252 * @dev: generic device structure 253 * @irq: the interrupt number 254 * @axi_clk: axi clock 255 * @chan: DPDMA channels 256 * @ext_addr: flag for 64 bit system (48 bit addressing) 257 */ 258 struct xilinx_dpdma_device { 259 struct dma_device common; 260 void __iomem *reg; 261 struct device *dev; 262 int irq; 263 264 struct clk *axi_clk; 265 struct xilinx_dpdma_chan *chan[XILINX_DPDMA_NUM_CHAN]; 266 267 bool ext_addr; 268 }; 269 270 /* ----------------------------------------------------------------------------- 271 * DebugFS 272 */ 273 274 #ifdef CONFIG_DEBUG_FS 275 276 #define XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE 32 277 #define XILINX_DPDMA_DEBUGFS_UINT16_MAX_STR "65535" 278 279 /* Match xilinx_dpdma_testcases vs dpdma_debugfs_reqs[] entry */ 280 enum xilinx_dpdma_testcases { 281 DPDMA_TC_INTR_DONE, 282 DPDMA_TC_NONE 283 }; 284 285 struct xilinx_dpdma_debugfs { 286 enum xilinx_dpdma_testcases testcase; 287 u16 xilinx_dpdma_irq_done_count; 288 unsigned int chan_id; 289 }; 290 291 static struct xilinx_dpdma_debugfs dpdma_debugfs; 292 struct xilinx_dpdma_debugfs_request { 293 const char *name; 294 enum xilinx_dpdma_testcases tc; 295 ssize_t (*read)(char *buf); 296 int (*write)(char *args); 297 }; 298 299 static void xilinx_dpdma_debugfs_desc_done_irq(struct xilinx_dpdma_chan *chan) 300 { 301 if (chan->id == dpdma_debugfs.chan_id) 302 dpdma_debugfs.xilinx_dpdma_irq_done_count++; 303 } 304 305 static ssize_t xilinx_dpdma_debugfs_desc_done_irq_read(char *buf) 306 { 307 size_t out_str_len; 308 309 dpdma_debugfs.testcase = DPDMA_TC_NONE; 310 311 out_str_len = strlen(XILINX_DPDMA_DEBUGFS_UINT16_MAX_STR); 312 out_str_len = min_t(size_t, XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE, 313 out_str_len); 314 snprintf(buf, out_str_len, "%d", 315 dpdma_debugfs.xilinx_dpdma_irq_done_count); 316 317 return 0; 318 } 319 320 static int xilinx_dpdma_debugfs_desc_done_irq_write(char *args) 321 { 322 char *arg; 323 int ret; 324 u32 id; 325 326 arg = strsep(&args, " "); 327 if (!arg || strncasecmp(arg, "start", 5)) 328 return -EINVAL; 329 330 arg = strsep(&args, " "); 331 if (!arg) 332 return -EINVAL; 333 334 ret = kstrtou32(arg, 0, &id); 335 if (ret < 0) 336 return ret; 337 338 if (id < ZYNQMP_DPDMA_VIDEO0 || id > ZYNQMP_DPDMA_AUDIO1) 339 return -EINVAL; 340 341 dpdma_debugfs.testcase = DPDMA_TC_INTR_DONE; 342 dpdma_debugfs.xilinx_dpdma_irq_done_count = 0; 343 dpdma_debugfs.chan_id = id; 344 345 return 0; 346 } 347 348 /* Match xilinx_dpdma_testcases vs dpdma_debugfs_reqs[] entry */ 349 static struct xilinx_dpdma_debugfs_request dpdma_debugfs_reqs[] = { 350 { 351 .name = "DESCRIPTOR_DONE_INTR", 352 .tc = DPDMA_TC_INTR_DONE, 353 .read = xilinx_dpdma_debugfs_desc_done_irq_read, 354 .write = xilinx_dpdma_debugfs_desc_done_irq_write, 355 }, 356 }; 357 358 static ssize_t xilinx_dpdma_debugfs_read(struct file *f, char __user *buf, 359 size_t size, loff_t *pos) 360 { 361 enum xilinx_dpdma_testcases testcase; 362 char *kern_buff; 363 int ret = 0; 364 365 if (*pos != 0 || size <= 0) 366 return -EINVAL; 367 368 kern_buff = kzalloc(XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE, GFP_KERNEL); 369 if (!kern_buff) { 370 dpdma_debugfs.testcase = DPDMA_TC_NONE; 371 return -ENOMEM; 372 } 373 374 testcase = READ_ONCE(dpdma_debugfs.testcase); 375 if (testcase != DPDMA_TC_NONE) { 376 ret = dpdma_debugfs_reqs[testcase].read(kern_buff); 377 if (ret < 0) 378 goto done; 379 } else { 380 strlcpy(kern_buff, "No testcase executed", 381 XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE); 382 } 383 384 size = min(size, strlen(kern_buff)); 385 if (copy_to_user(buf, kern_buff, size)) 386 ret = -EFAULT; 387 388 done: 389 kfree(kern_buff); 390 if (ret) 391 return ret; 392 393 *pos = size + 1; 394 return size; 395 } 396 397 static ssize_t xilinx_dpdma_debugfs_write(struct file *f, 398 const char __user *buf, size_t size, 399 loff_t *pos) 400 { 401 char *kern_buff, *kern_buff_start; 402 char *testcase; 403 unsigned int i; 404 int ret; 405 406 if (*pos != 0 || size <= 0) 407 return -EINVAL; 408 409 /* Supporting single instance of test as of now. */ 410 if (dpdma_debugfs.testcase != DPDMA_TC_NONE) 411 return -EBUSY; 412 413 kern_buff = kzalloc(size, GFP_KERNEL); 414 if (!kern_buff) 415 return -ENOMEM; 416 kern_buff_start = kern_buff; 417 418 ret = strncpy_from_user(kern_buff, buf, size); 419 if (ret < 0) 420 goto done; 421 422 /* Read the testcase name from a user request. */ 423 testcase = strsep(&kern_buff, " "); 424 425 for (i = 0; i < ARRAY_SIZE(dpdma_debugfs_reqs); i++) { 426 if (!strcasecmp(testcase, dpdma_debugfs_reqs[i].name)) 427 break; 428 } 429 430 if (i == ARRAY_SIZE(dpdma_debugfs_reqs)) { 431 ret = -EINVAL; 432 goto done; 433 } 434 435 ret = dpdma_debugfs_reqs[i].write(kern_buff); 436 if (ret < 0) 437 goto done; 438 439 ret = size; 440 441 done: 442 kfree(kern_buff_start); 443 return ret; 444 } 445 446 static const struct file_operations fops_xilinx_dpdma_dbgfs = { 447 .owner = THIS_MODULE, 448 .read = xilinx_dpdma_debugfs_read, 449 .write = xilinx_dpdma_debugfs_write, 450 }; 451 452 static void xilinx_dpdma_debugfs_init(struct xilinx_dpdma_device *xdev) 453 { 454 struct dentry *dent; 455 456 dpdma_debugfs.testcase = DPDMA_TC_NONE; 457 458 dent = debugfs_create_file("testcase", 0444, xdev->common.dbg_dev_root, 459 NULL, &fops_xilinx_dpdma_dbgfs); 460 if (IS_ERR(dent)) 461 dev_err(xdev->dev, "Failed to create debugfs testcase file\n"); 462 } 463 464 #else 465 static void xilinx_dpdma_debugfs_init(struct xilinx_dpdma_device *xdev) 466 { 467 } 468 469 static void xilinx_dpdma_debugfs_desc_done_irq(struct xilinx_dpdma_chan *chan) 470 { 471 } 472 #endif /* CONFIG_DEBUG_FS */ 473 474 /* ----------------------------------------------------------------------------- 475 * I/O Accessors 476 */ 477 478 static inline u32 dpdma_read(void __iomem *base, u32 offset) 479 { 480 return ioread32(base + offset); 481 } 482 483 static inline void dpdma_write(void __iomem *base, u32 offset, u32 val) 484 { 485 iowrite32(val, base + offset); 486 } 487 488 static inline void dpdma_clr(void __iomem *base, u32 offset, u32 clr) 489 { 490 dpdma_write(base, offset, dpdma_read(base, offset) & ~clr); 491 } 492 493 static inline void dpdma_set(void __iomem *base, u32 offset, u32 set) 494 { 495 dpdma_write(base, offset, dpdma_read(base, offset) | set); 496 } 497 498 /* ----------------------------------------------------------------------------- 499 * Descriptor Operations 500 */ 501 502 /** 503 * xilinx_dpdma_sw_desc_set_dma_addrs - Set DMA addresses in the descriptor 504 * @xdev: DPDMA device 505 * @sw_desc: The software descriptor in which to set DMA addresses 506 * @prev: The previous descriptor 507 * @dma_addr: array of dma addresses 508 * @num_src_addr: number of addresses in @dma_addr 509 * 510 * Set all the DMA addresses in the hardware descriptor corresponding to @dev 511 * from @dma_addr. If a previous descriptor is specified in @prev, its next 512 * descriptor DMA address is set to the DMA address of @sw_desc. @prev may be 513 * identical to @sw_desc for cyclic transfers. 514 */ 515 static void xilinx_dpdma_sw_desc_set_dma_addrs(struct xilinx_dpdma_device *xdev, 516 struct xilinx_dpdma_sw_desc *sw_desc, 517 struct xilinx_dpdma_sw_desc *prev, 518 dma_addr_t dma_addr[], 519 unsigned int num_src_addr) 520 { 521 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw; 522 unsigned int i; 523 524 hw_desc->src_addr = lower_32_bits(dma_addr[0]); 525 if (xdev->ext_addr) 526 hw_desc->addr_ext |= 527 FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_SRC_ADDR_MASK, 528 upper_32_bits(dma_addr[0])); 529 530 for (i = 1; i < num_src_addr; i++) { 531 u32 *addr = &hw_desc->src_addr2; 532 533 addr[i-1] = lower_32_bits(dma_addr[i]); 534 535 if (xdev->ext_addr) { 536 u32 *addr_ext = &hw_desc->addr_ext_23; 537 u32 addr_msb; 538 539 addr_msb = upper_32_bits(dma_addr[i]) & GENMASK(15, 0); 540 addr_msb <<= 16 * ((i - 1) % 2); 541 addr_ext[(i - 1) / 2] |= addr_msb; 542 } 543 } 544 545 if (!prev) 546 return; 547 548 prev->hw.next_desc = lower_32_bits(sw_desc->dma_addr); 549 if (xdev->ext_addr) 550 prev->hw.addr_ext |= 551 FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK, 552 upper_32_bits(sw_desc->dma_addr)); 553 } 554 555 /** 556 * xilinx_dpdma_chan_alloc_sw_desc - Allocate a software descriptor 557 * @chan: DPDMA channel 558 * 559 * Allocate a software descriptor from the channel's descriptor pool. 560 * 561 * Return: a software descriptor or NULL. 562 */ 563 static struct xilinx_dpdma_sw_desc * 564 xilinx_dpdma_chan_alloc_sw_desc(struct xilinx_dpdma_chan *chan) 565 { 566 struct xilinx_dpdma_sw_desc *sw_desc; 567 dma_addr_t dma_addr; 568 569 sw_desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &dma_addr); 570 if (!sw_desc) 571 return NULL; 572 573 sw_desc->dma_addr = dma_addr; 574 575 return sw_desc; 576 } 577 578 /** 579 * xilinx_dpdma_chan_free_sw_desc - Free a software descriptor 580 * @chan: DPDMA channel 581 * @sw_desc: software descriptor to free 582 * 583 * Free a software descriptor from the channel's descriptor pool. 584 */ 585 static void 586 xilinx_dpdma_chan_free_sw_desc(struct xilinx_dpdma_chan *chan, 587 struct xilinx_dpdma_sw_desc *sw_desc) 588 { 589 dma_pool_free(chan->desc_pool, sw_desc, sw_desc->dma_addr); 590 } 591 592 /** 593 * xilinx_dpdma_chan_dump_tx_desc - Dump a tx descriptor 594 * @chan: DPDMA channel 595 * @tx_desc: tx descriptor to dump 596 * 597 * Dump contents of a tx descriptor 598 */ 599 static void xilinx_dpdma_chan_dump_tx_desc(struct xilinx_dpdma_chan *chan, 600 struct xilinx_dpdma_tx_desc *tx_desc) 601 { 602 struct xilinx_dpdma_sw_desc *sw_desc; 603 struct device *dev = chan->xdev->dev; 604 unsigned int i = 0; 605 606 dev_dbg(dev, "------- TX descriptor dump start -------\n"); 607 dev_dbg(dev, "------- channel ID = %d -------\n", chan->id); 608 609 list_for_each_entry(sw_desc, &tx_desc->descriptors, node) { 610 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw; 611 612 dev_dbg(dev, "------- HW descriptor %d -------\n", i++); 613 dev_dbg(dev, "descriptor DMA addr: %pad\n", &sw_desc->dma_addr); 614 dev_dbg(dev, "control: 0x%08x\n", hw_desc->control); 615 dev_dbg(dev, "desc_id: 0x%08x\n", hw_desc->desc_id); 616 dev_dbg(dev, "xfer_size: 0x%08x\n", hw_desc->xfer_size); 617 dev_dbg(dev, "hsize_stride: 0x%08x\n", hw_desc->hsize_stride); 618 dev_dbg(dev, "timestamp_lsb: 0x%08x\n", hw_desc->timestamp_lsb); 619 dev_dbg(dev, "timestamp_msb: 0x%08x\n", hw_desc->timestamp_msb); 620 dev_dbg(dev, "addr_ext: 0x%08x\n", hw_desc->addr_ext); 621 dev_dbg(dev, "next_desc: 0x%08x\n", hw_desc->next_desc); 622 dev_dbg(dev, "src_addr: 0x%08x\n", hw_desc->src_addr); 623 dev_dbg(dev, "addr_ext_23: 0x%08x\n", hw_desc->addr_ext_23); 624 dev_dbg(dev, "addr_ext_45: 0x%08x\n", hw_desc->addr_ext_45); 625 dev_dbg(dev, "src_addr2: 0x%08x\n", hw_desc->src_addr2); 626 dev_dbg(dev, "src_addr3: 0x%08x\n", hw_desc->src_addr3); 627 dev_dbg(dev, "src_addr4: 0x%08x\n", hw_desc->src_addr4); 628 dev_dbg(dev, "src_addr5: 0x%08x\n", hw_desc->src_addr5); 629 dev_dbg(dev, "crc: 0x%08x\n", hw_desc->crc); 630 } 631 632 dev_dbg(dev, "------- TX descriptor dump end -------\n"); 633 } 634 635 /** 636 * xilinx_dpdma_chan_alloc_tx_desc - Allocate a transaction descriptor 637 * @chan: DPDMA channel 638 * 639 * Allocate a tx descriptor. 640 * 641 * Return: a tx descriptor or NULL. 642 */ 643 static struct xilinx_dpdma_tx_desc * 644 xilinx_dpdma_chan_alloc_tx_desc(struct xilinx_dpdma_chan *chan) 645 { 646 struct xilinx_dpdma_tx_desc *tx_desc; 647 648 tx_desc = kzalloc(sizeof(*tx_desc), GFP_NOWAIT); 649 if (!tx_desc) 650 return NULL; 651 652 INIT_LIST_HEAD(&tx_desc->descriptors); 653 tx_desc->chan = chan; 654 tx_desc->error = false; 655 656 return tx_desc; 657 } 658 659 /** 660 * xilinx_dpdma_chan_free_tx_desc - Free a virtual DMA descriptor 661 * @vdesc: virtual DMA descriptor 662 * 663 * Free the virtual DMA descriptor @vdesc including its software descriptors. 664 */ 665 static void xilinx_dpdma_chan_free_tx_desc(struct virt_dma_desc *vdesc) 666 { 667 struct xilinx_dpdma_sw_desc *sw_desc, *next; 668 struct xilinx_dpdma_tx_desc *desc; 669 670 if (!vdesc) 671 return; 672 673 desc = to_dpdma_tx_desc(vdesc); 674 675 list_for_each_entry_safe(sw_desc, next, &desc->descriptors, node) { 676 list_del(&sw_desc->node); 677 xilinx_dpdma_chan_free_sw_desc(desc->chan, sw_desc); 678 } 679 680 kfree(desc); 681 } 682 683 /** 684 * xilinx_dpdma_chan_prep_interleaved_dma - Prepare an interleaved dma 685 * descriptor 686 * @chan: DPDMA channel 687 * @xt: dma interleaved template 688 * 689 * Prepare a tx descriptor including internal software/hardware descriptors 690 * based on @xt. 691 * 692 * Return: A DPDMA TX descriptor on success, or NULL. 693 */ 694 static struct xilinx_dpdma_tx_desc * 695 xilinx_dpdma_chan_prep_interleaved_dma(struct xilinx_dpdma_chan *chan, 696 struct dma_interleaved_template *xt) 697 { 698 struct xilinx_dpdma_tx_desc *tx_desc; 699 struct xilinx_dpdma_sw_desc *sw_desc; 700 struct xilinx_dpdma_hw_desc *hw_desc; 701 size_t hsize = xt->sgl[0].size; 702 size_t stride = hsize + xt->sgl[0].icg; 703 704 if (!IS_ALIGNED(xt->src_start, XILINX_DPDMA_ALIGN_BYTES)) { 705 dev_err(chan->xdev->dev, 706 "chan%u: buffer should be aligned at %d B\n", 707 chan->id, XILINX_DPDMA_ALIGN_BYTES); 708 return NULL; 709 } 710 711 tx_desc = xilinx_dpdma_chan_alloc_tx_desc(chan); 712 if (!tx_desc) 713 return NULL; 714 715 sw_desc = xilinx_dpdma_chan_alloc_sw_desc(chan); 716 if (!sw_desc) { 717 xilinx_dpdma_chan_free_tx_desc(&tx_desc->vdesc); 718 return NULL; 719 } 720 721 xilinx_dpdma_sw_desc_set_dma_addrs(chan->xdev, sw_desc, sw_desc, 722 &xt->src_start, 1); 723 724 hw_desc = &sw_desc->hw; 725 hsize = ALIGN(hsize, XILINX_DPDMA_LINESIZE_ALIGN_BITS / 8); 726 hw_desc->xfer_size = hsize * xt->numf; 727 hw_desc->hsize_stride = 728 FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK, hsize) | 729 FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK, 730 stride / 16); 731 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_PREEMBLE; 732 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR; 733 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE; 734 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME; 735 736 list_add_tail(&sw_desc->node, &tx_desc->descriptors); 737 738 return tx_desc; 739 } 740 741 /* ----------------------------------------------------------------------------- 742 * DPDMA Channel Operations 743 */ 744 745 /** 746 * xilinx_dpdma_chan_enable - Enable the channel 747 * @chan: DPDMA channel 748 * 749 * Enable the channel and its interrupts. Set the QoS values for video class. 750 */ 751 static void xilinx_dpdma_chan_enable(struct xilinx_dpdma_chan *chan) 752 { 753 u32 reg; 754 755 reg = (XILINX_DPDMA_INTR_CHAN_MASK << chan->id) 756 | XILINX_DPDMA_INTR_GLOBAL_MASK; 757 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg); 758 reg = (XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id) 759 | XILINX_DPDMA_INTR_GLOBAL_ERR; 760 dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg); 761 762 reg = XILINX_DPDMA_CH_CNTL_ENABLE 763 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DSCR_WR_MASK, 764 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS) 765 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DSCR_RD_MASK, 766 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS) 767 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DATA_RD_MASK, 768 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS); 769 dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, reg); 770 } 771 772 /** 773 * xilinx_dpdma_chan_disable - Disable the channel 774 * @chan: DPDMA channel 775 * 776 * Disable the channel and its interrupts. 777 */ 778 static void xilinx_dpdma_chan_disable(struct xilinx_dpdma_chan *chan) 779 { 780 u32 reg; 781 782 reg = XILINX_DPDMA_INTR_CHAN_MASK << chan->id; 783 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg); 784 reg = XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id; 785 dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg); 786 787 dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE); 788 } 789 790 /** 791 * xilinx_dpdma_chan_pause - Pause the channel 792 * @chan: DPDMA channel 793 * 794 * Pause the channel. 795 */ 796 static void xilinx_dpdma_chan_pause(struct xilinx_dpdma_chan *chan) 797 { 798 dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE); 799 } 800 801 /** 802 * xilinx_dpdma_chan_unpause - Unpause the channel 803 * @chan: DPDMA channel 804 * 805 * Unpause the channel. 806 */ 807 static void xilinx_dpdma_chan_unpause(struct xilinx_dpdma_chan *chan) 808 { 809 dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE); 810 } 811 812 static u32 xilinx_dpdma_chan_video_group_ready(struct xilinx_dpdma_chan *chan) 813 { 814 struct xilinx_dpdma_device *xdev = chan->xdev; 815 u32 channels = 0; 816 unsigned int i; 817 818 for (i = ZYNQMP_DPDMA_VIDEO0; i <= ZYNQMP_DPDMA_VIDEO2; i++) { 819 if (xdev->chan[i]->video_group && !xdev->chan[i]->running) 820 return 0; 821 822 if (xdev->chan[i]->video_group) 823 channels |= BIT(i); 824 } 825 826 return channels; 827 } 828 829 /** 830 * xilinx_dpdma_chan_queue_transfer - Queue the next transfer 831 * @chan: DPDMA channel 832 * 833 * Queue the next descriptor, if any, to the hardware. If the channel is 834 * stopped, start it first. Otherwise retrigger it with the next descriptor. 835 */ 836 static void xilinx_dpdma_chan_queue_transfer(struct xilinx_dpdma_chan *chan) 837 { 838 struct xilinx_dpdma_device *xdev = chan->xdev; 839 struct xilinx_dpdma_sw_desc *sw_desc; 840 struct xilinx_dpdma_tx_desc *desc; 841 struct virt_dma_desc *vdesc; 842 u32 reg, channels; 843 bool first_frame; 844 845 lockdep_assert_held(&chan->lock); 846 847 if (chan->desc.pending) 848 return; 849 850 if (!chan->running) { 851 xilinx_dpdma_chan_unpause(chan); 852 xilinx_dpdma_chan_enable(chan); 853 chan->first_frame = true; 854 chan->running = true; 855 } 856 857 vdesc = vchan_next_desc(&chan->vchan); 858 if (!vdesc) 859 return; 860 861 desc = to_dpdma_tx_desc(vdesc); 862 chan->desc.pending = desc; 863 list_del(&desc->vdesc.node); 864 865 /* 866 * Assign the cookie to descriptors in this transaction. Only 16 bit 867 * will be used, but it should be enough. 868 */ 869 list_for_each_entry(sw_desc, &desc->descriptors, node) 870 sw_desc->hw.desc_id = desc->vdesc.tx.cookie; 871 872 sw_desc = list_first_entry(&desc->descriptors, 873 struct xilinx_dpdma_sw_desc, node); 874 dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR, 875 lower_32_bits(sw_desc->dma_addr)); 876 if (xdev->ext_addr) 877 dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE, 878 FIELD_PREP(XILINX_DPDMA_CH_DESC_START_ADDRE_MASK, 879 upper_32_bits(sw_desc->dma_addr))); 880 881 first_frame = chan->first_frame; 882 chan->first_frame = false; 883 884 if (chan->video_group) { 885 channels = xilinx_dpdma_chan_video_group_ready(chan); 886 /* 887 * Trigger the transfer only when all channels in the group are 888 * ready. 889 */ 890 if (!channels) 891 return; 892 } else { 893 channels = BIT(chan->id); 894 } 895 896 if (first_frame) 897 reg = XILINX_DPDMA_GBL_TRIG_MASK(channels); 898 else 899 reg = XILINX_DPDMA_GBL_RETRIG_MASK(channels); 900 901 dpdma_write(xdev->reg, XILINX_DPDMA_GBL, reg); 902 } 903 904 /** 905 * xilinx_dpdma_chan_ostand - Number of outstanding transactions 906 * @chan: DPDMA channel 907 * 908 * Read and return the number of outstanding transactions from register. 909 * 910 * Return: Number of outstanding transactions from the status register. 911 */ 912 static u32 xilinx_dpdma_chan_ostand(struct xilinx_dpdma_chan *chan) 913 { 914 return FIELD_GET(XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK, 915 dpdma_read(chan->reg, XILINX_DPDMA_CH_STATUS)); 916 } 917 918 /** 919 * xilinx_dpdma_chan_no_ostand - Notify no outstanding transaction event 920 * @chan: DPDMA channel 921 * 922 * Notify waiters for no outstanding event, so waiters can stop the channel 923 * safely. This function is supposed to be called when 'no outstanding' 924 * interrupt is generated. The 'no outstanding' interrupt is disabled and 925 * should be re-enabled when this event is handled. If the channel status 926 * register still shows some number of outstanding transactions, the interrupt 927 * remains enabled. 928 * 929 * Return: 0 on success. On failure, -EWOULDBLOCK if there's still outstanding 930 * transaction(s). 931 */ 932 static int xilinx_dpdma_chan_notify_no_ostand(struct xilinx_dpdma_chan *chan) 933 { 934 u32 cnt; 935 936 cnt = xilinx_dpdma_chan_ostand(chan); 937 if (cnt) { 938 dev_dbg(chan->xdev->dev, 939 "chan%u: %d outstanding transactions\n", 940 chan->id, cnt); 941 return -EWOULDBLOCK; 942 } 943 944 /* Disable 'no outstanding' interrupt */ 945 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IDS, 946 XILINX_DPDMA_INTR_NO_OSTAND(chan->id)); 947 wake_up(&chan->wait_to_stop); 948 949 return 0; 950 } 951 952 /** 953 * xilinx_dpdma_chan_wait_no_ostand - Wait for the no outstanding irq 954 * @chan: DPDMA channel 955 * 956 * Wait for the no outstanding transaction interrupt. This functions can sleep 957 * for 50ms. 958 * 959 * Return: 0 on success. On failure, -ETIMEOUT for time out, or the error code 960 * from wait_event_interruptible_timeout(). 961 */ 962 static int xilinx_dpdma_chan_wait_no_ostand(struct xilinx_dpdma_chan *chan) 963 { 964 int ret; 965 966 /* Wait for a no outstanding transaction interrupt upto 50msec */ 967 ret = wait_event_interruptible_timeout(chan->wait_to_stop, 968 !xilinx_dpdma_chan_ostand(chan), 969 msecs_to_jiffies(50)); 970 if (ret > 0) { 971 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, 972 XILINX_DPDMA_INTR_NO_OSTAND(chan->id)); 973 return 0; 974 } 975 976 dev_err(chan->xdev->dev, "chan%u: not ready to stop: %d trans\n", 977 chan->id, xilinx_dpdma_chan_ostand(chan)); 978 979 if (ret == 0) 980 return -ETIMEDOUT; 981 982 return ret; 983 } 984 985 /** 986 * xilinx_dpdma_chan_poll_no_ostand - Poll the outstanding transaction status 987 * @chan: DPDMA channel 988 * 989 * Poll the outstanding transaction status, and return when there's no 990 * outstanding transaction. This functions can be used in the interrupt context 991 * or where the atomicity is required. Calling thread may wait more than 50ms. 992 * 993 * Return: 0 on success, or -ETIMEDOUT. 994 */ 995 static int xilinx_dpdma_chan_poll_no_ostand(struct xilinx_dpdma_chan *chan) 996 { 997 u32 cnt, loop = 50000; 998 999 /* Poll at least for 50ms (20 fps). */ 1000 do { 1001 cnt = xilinx_dpdma_chan_ostand(chan); 1002 udelay(1); 1003 } while (loop-- > 0 && cnt); 1004 1005 if (loop) { 1006 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, 1007 XILINX_DPDMA_INTR_NO_OSTAND(chan->id)); 1008 return 0; 1009 } 1010 1011 dev_err(chan->xdev->dev, "chan%u: not ready to stop: %d trans\n", 1012 chan->id, xilinx_dpdma_chan_ostand(chan)); 1013 1014 return -ETIMEDOUT; 1015 } 1016 1017 /** 1018 * xilinx_dpdma_chan_stop - Stop the channel 1019 * @chan: DPDMA channel 1020 * 1021 * Stop a previously paused channel by first waiting for completion of all 1022 * outstanding transaction and then disabling the channel. 1023 * 1024 * Return: 0 on success, or -ETIMEDOUT if the channel failed to stop. 1025 */ 1026 static int xilinx_dpdma_chan_stop(struct xilinx_dpdma_chan *chan) 1027 { 1028 unsigned long flags; 1029 int ret; 1030 1031 ret = xilinx_dpdma_chan_wait_no_ostand(chan); 1032 if (ret) 1033 return ret; 1034 1035 spin_lock_irqsave(&chan->lock, flags); 1036 xilinx_dpdma_chan_disable(chan); 1037 chan->running = false; 1038 spin_unlock_irqrestore(&chan->lock, flags); 1039 1040 return 0; 1041 } 1042 1043 /** 1044 * xilinx_dpdma_chan_done_irq - Handle hardware descriptor completion 1045 * @chan: DPDMA channel 1046 * 1047 * Handle completion of the currently active descriptor (@chan->desc.active). As 1048 * we currently support cyclic transfers only, this just invokes the cyclic 1049 * callback. The descriptor will be completed at the VSYNC interrupt when a new 1050 * descriptor replaces it. 1051 */ 1052 static void xilinx_dpdma_chan_done_irq(struct xilinx_dpdma_chan *chan) 1053 { 1054 struct xilinx_dpdma_tx_desc *active; 1055 unsigned long flags; 1056 1057 spin_lock_irqsave(&chan->lock, flags); 1058 1059 xilinx_dpdma_debugfs_desc_done_irq(chan); 1060 1061 active = chan->desc.active; 1062 if (active) 1063 vchan_cyclic_callback(&active->vdesc); 1064 else 1065 dev_warn(chan->xdev->dev, 1066 "chan%u: DONE IRQ with no active descriptor!\n", 1067 chan->id); 1068 1069 spin_unlock_irqrestore(&chan->lock, flags); 1070 } 1071 1072 /** 1073 * xilinx_dpdma_chan_vsync_irq - Handle hardware descriptor scheduling 1074 * @chan: DPDMA channel 1075 * 1076 * At VSYNC the active descriptor may have been replaced by the pending 1077 * descriptor. Detect this through the DESC_ID and perform appropriate 1078 * bookkeeping. 1079 */ 1080 static void xilinx_dpdma_chan_vsync_irq(struct xilinx_dpdma_chan *chan) 1081 { 1082 struct xilinx_dpdma_tx_desc *pending; 1083 struct xilinx_dpdma_sw_desc *sw_desc; 1084 unsigned long flags; 1085 u32 desc_id; 1086 1087 spin_lock_irqsave(&chan->lock, flags); 1088 1089 pending = chan->desc.pending; 1090 if (!chan->running || !pending) 1091 goto out; 1092 1093 desc_id = dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_ID); 1094 1095 /* If the retrigger raced with vsync, retry at the next frame. */ 1096 sw_desc = list_first_entry(&pending->descriptors, 1097 struct xilinx_dpdma_sw_desc, node); 1098 if (sw_desc->hw.desc_id != desc_id) 1099 goto out; 1100 1101 /* 1102 * Complete the active descriptor, if any, promote the pending 1103 * descriptor to active, and queue the next transfer, if any. 1104 */ 1105 if (chan->desc.active) 1106 vchan_cookie_complete(&chan->desc.active->vdesc); 1107 chan->desc.active = pending; 1108 chan->desc.pending = NULL; 1109 1110 xilinx_dpdma_chan_queue_transfer(chan); 1111 1112 out: 1113 spin_unlock_irqrestore(&chan->lock, flags); 1114 } 1115 1116 /** 1117 * xilinx_dpdma_chan_err - Detect any channel error 1118 * @chan: DPDMA channel 1119 * @isr: masked Interrupt Status Register 1120 * @eisr: Error Interrupt Status Register 1121 * 1122 * Return: true if any channel error occurs, or false otherwise. 1123 */ 1124 static bool 1125 xilinx_dpdma_chan_err(struct xilinx_dpdma_chan *chan, u32 isr, u32 eisr) 1126 { 1127 if (!chan) 1128 return false; 1129 1130 if (chan->running && 1131 ((isr & (XILINX_DPDMA_INTR_CHAN_ERR_MASK << chan->id)) || 1132 (eisr & (XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id)))) 1133 return true; 1134 1135 return false; 1136 } 1137 1138 /** 1139 * xilinx_dpdma_chan_handle_err - DPDMA channel error handling 1140 * @chan: DPDMA channel 1141 * 1142 * This function is called when any channel error or any global error occurs. 1143 * The function disables the paused channel by errors and determines 1144 * if the current active descriptor can be rescheduled depending on 1145 * the descriptor status. 1146 */ 1147 static void xilinx_dpdma_chan_handle_err(struct xilinx_dpdma_chan *chan) 1148 { 1149 struct xilinx_dpdma_device *xdev = chan->xdev; 1150 struct xilinx_dpdma_tx_desc *active; 1151 unsigned long flags; 1152 1153 spin_lock_irqsave(&chan->lock, flags); 1154 1155 dev_dbg(xdev->dev, "chan%u: cur desc addr = 0x%04x%08x\n", 1156 chan->id, 1157 dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE), 1158 dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR)); 1159 dev_dbg(xdev->dev, "chan%u: cur payload addr = 0x%04x%08x\n", 1160 chan->id, 1161 dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDRE), 1162 dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDR)); 1163 1164 xilinx_dpdma_chan_disable(chan); 1165 chan->running = false; 1166 1167 if (!chan->desc.active) 1168 goto out_unlock; 1169 1170 active = chan->desc.active; 1171 chan->desc.active = NULL; 1172 1173 xilinx_dpdma_chan_dump_tx_desc(chan, active); 1174 1175 if (active->error) 1176 dev_dbg(xdev->dev, "chan%u: repeated error on desc\n", 1177 chan->id); 1178 1179 /* Reschedule if there's no new descriptor */ 1180 if (!chan->desc.pending && 1181 list_empty(&chan->vchan.desc_issued)) { 1182 active->error = true; 1183 list_add_tail(&active->vdesc.node, 1184 &chan->vchan.desc_issued); 1185 } else { 1186 xilinx_dpdma_chan_free_tx_desc(&active->vdesc); 1187 } 1188 1189 out_unlock: 1190 spin_unlock_irqrestore(&chan->lock, flags); 1191 } 1192 1193 /* ----------------------------------------------------------------------------- 1194 * DMA Engine Operations 1195 */ 1196 1197 static struct dma_async_tx_descriptor * 1198 xilinx_dpdma_prep_interleaved_dma(struct dma_chan *dchan, 1199 struct dma_interleaved_template *xt, 1200 unsigned long flags) 1201 { 1202 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1203 struct xilinx_dpdma_tx_desc *desc; 1204 1205 if (xt->dir != DMA_MEM_TO_DEV) 1206 return NULL; 1207 1208 if (!xt->numf || !xt->sgl[0].size) 1209 return NULL; 1210 1211 if (!(flags & DMA_PREP_REPEAT) || !(flags & DMA_PREP_LOAD_EOT)) 1212 return NULL; 1213 1214 desc = xilinx_dpdma_chan_prep_interleaved_dma(chan, xt); 1215 if (!desc) 1216 return NULL; 1217 1218 vchan_tx_prep(&chan->vchan, &desc->vdesc, flags | DMA_CTRL_ACK); 1219 1220 return &desc->vdesc.tx; 1221 } 1222 1223 /** 1224 * xilinx_dpdma_alloc_chan_resources - Allocate resources for the channel 1225 * @dchan: DMA channel 1226 * 1227 * Allocate a descriptor pool for the channel. 1228 * 1229 * Return: 0 on success, or -ENOMEM if failed to allocate a pool. 1230 */ 1231 static int xilinx_dpdma_alloc_chan_resources(struct dma_chan *dchan) 1232 { 1233 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1234 size_t align = __alignof__(struct xilinx_dpdma_sw_desc); 1235 1236 chan->desc_pool = dma_pool_create(dev_name(chan->xdev->dev), 1237 chan->xdev->dev, 1238 sizeof(struct xilinx_dpdma_sw_desc), 1239 align, 0); 1240 if (!chan->desc_pool) { 1241 dev_err(chan->xdev->dev, 1242 "chan%u: failed to allocate a descriptor pool\n", 1243 chan->id); 1244 return -ENOMEM; 1245 } 1246 1247 return 0; 1248 } 1249 1250 /** 1251 * xilinx_dpdma_free_chan_resources - Free all resources for the channel 1252 * @dchan: DMA channel 1253 * 1254 * Free resources associated with the virtual DMA channel, and destroy the 1255 * descriptor pool. 1256 */ 1257 static void xilinx_dpdma_free_chan_resources(struct dma_chan *dchan) 1258 { 1259 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1260 1261 vchan_free_chan_resources(&chan->vchan); 1262 1263 dma_pool_destroy(chan->desc_pool); 1264 chan->desc_pool = NULL; 1265 } 1266 1267 static void xilinx_dpdma_issue_pending(struct dma_chan *dchan) 1268 { 1269 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1270 unsigned long flags; 1271 1272 spin_lock_irqsave(&chan->vchan.lock, flags); 1273 if (vchan_issue_pending(&chan->vchan)) 1274 xilinx_dpdma_chan_queue_transfer(chan); 1275 spin_unlock_irqrestore(&chan->vchan.lock, flags); 1276 } 1277 1278 static int xilinx_dpdma_config(struct dma_chan *dchan, 1279 struct dma_slave_config *config) 1280 { 1281 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1282 unsigned long flags; 1283 1284 /* 1285 * The destination address doesn't need to be specified as the DPDMA is 1286 * hardwired to the destination (the DP controller). The transfer 1287 * width, burst size and port window size are thus meaningless, they're 1288 * fixed both on the DPDMA side and on the DP controller side. 1289 */ 1290 1291 spin_lock_irqsave(&chan->lock, flags); 1292 1293 /* 1294 * Abuse the slave_id to indicate that the channel is part of a video 1295 * group. 1296 */ 1297 if (chan->id <= ZYNQMP_DPDMA_VIDEO2) 1298 chan->video_group = config->slave_id != 0; 1299 1300 spin_unlock_irqrestore(&chan->lock, flags); 1301 1302 return 0; 1303 } 1304 1305 static int xilinx_dpdma_pause(struct dma_chan *dchan) 1306 { 1307 xilinx_dpdma_chan_pause(to_xilinx_chan(dchan)); 1308 1309 return 0; 1310 } 1311 1312 static int xilinx_dpdma_resume(struct dma_chan *dchan) 1313 { 1314 xilinx_dpdma_chan_unpause(to_xilinx_chan(dchan)); 1315 1316 return 0; 1317 } 1318 1319 /** 1320 * xilinx_dpdma_terminate_all - Terminate the channel and descriptors 1321 * @dchan: DMA channel 1322 * 1323 * Pause the channel without waiting for ongoing transfers to complete. Waiting 1324 * for completion is performed by xilinx_dpdma_synchronize() that will disable 1325 * the channel to complete the stop. 1326 * 1327 * All the descriptors associated with the channel that are guaranteed not to 1328 * be touched by the hardware. The pending and active descriptor are not 1329 * touched, and will be freed either upon completion, or by 1330 * xilinx_dpdma_synchronize(). 1331 * 1332 * Return: 0 on success, or -ETIMEDOUT if the channel failed to stop. 1333 */ 1334 static int xilinx_dpdma_terminate_all(struct dma_chan *dchan) 1335 { 1336 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1337 struct xilinx_dpdma_device *xdev = chan->xdev; 1338 LIST_HEAD(descriptors); 1339 unsigned long flags; 1340 unsigned int i; 1341 1342 /* Pause the channel (including the whole video group if applicable). */ 1343 if (chan->video_group) { 1344 for (i = ZYNQMP_DPDMA_VIDEO0; i <= ZYNQMP_DPDMA_VIDEO2; i++) { 1345 if (xdev->chan[i]->video_group && 1346 xdev->chan[i]->running) { 1347 xilinx_dpdma_chan_pause(xdev->chan[i]); 1348 xdev->chan[i]->video_group = false; 1349 } 1350 } 1351 } else { 1352 xilinx_dpdma_chan_pause(chan); 1353 } 1354 1355 /* Gather all the descriptors we can free and free them. */ 1356 spin_lock_irqsave(&chan->vchan.lock, flags); 1357 vchan_get_all_descriptors(&chan->vchan, &descriptors); 1358 spin_unlock_irqrestore(&chan->vchan.lock, flags); 1359 1360 vchan_dma_desc_free_list(&chan->vchan, &descriptors); 1361 1362 return 0; 1363 } 1364 1365 /** 1366 * xilinx_dpdma_synchronize - Synchronize callback execution 1367 * @dchan: DMA channel 1368 * 1369 * Synchronizing callback execution ensures that all previously issued 1370 * transfers have completed and all associated callbacks have been called and 1371 * have returned. 1372 * 1373 * This function waits for the DMA channel to stop. It assumes it has been 1374 * paused by a previous call to dmaengine_terminate_async(), and that no new 1375 * pending descriptors have been issued with dma_async_issue_pending(). The 1376 * behaviour is undefined otherwise. 1377 */ 1378 static void xilinx_dpdma_synchronize(struct dma_chan *dchan) 1379 { 1380 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1381 unsigned long flags; 1382 1383 xilinx_dpdma_chan_stop(chan); 1384 1385 spin_lock_irqsave(&chan->vchan.lock, flags); 1386 if (chan->desc.pending) { 1387 vchan_terminate_vdesc(&chan->desc.pending->vdesc); 1388 chan->desc.pending = NULL; 1389 } 1390 if (chan->desc.active) { 1391 vchan_terminate_vdesc(&chan->desc.active->vdesc); 1392 chan->desc.active = NULL; 1393 } 1394 spin_unlock_irqrestore(&chan->vchan.lock, flags); 1395 1396 vchan_synchronize(&chan->vchan); 1397 } 1398 1399 /* ----------------------------------------------------------------------------- 1400 * Interrupt and Tasklet Handling 1401 */ 1402 1403 /** 1404 * xilinx_dpdma_err - Detect any global error 1405 * @isr: Interrupt Status Register 1406 * @eisr: Error Interrupt Status Register 1407 * 1408 * Return: True if any global error occurs, or false otherwise. 1409 */ 1410 static bool xilinx_dpdma_err(u32 isr, u32 eisr) 1411 { 1412 if (isr & XILINX_DPDMA_INTR_GLOBAL_ERR || 1413 eisr & XILINX_DPDMA_EINTR_GLOBAL_ERR) 1414 return true; 1415 1416 return false; 1417 } 1418 1419 /** 1420 * xilinx_dpdma_handle_err_irq - Handle DPDMA error interrupt 1421 * @xdev: DPDMA device 1422 * @isr: masked Interrupt Status Register 1423 * @eisr: Error Interrupt Status Register 1424 * 1425 * Handle if any error occurs based on @isr and @eisr. This function disables 1426 * corresponding error interrupts, and those should be re-enabled once handling 1427 * is done. 1428 */ 1429 static void xilinx_dpdma_handle_err_irq(struct xilinx_dpdma_device *xdev, 1430 u32 isr, u32 eisr) 1431 { 1432 bool err = xilinx_dpdma_err(isr, eisr); 1433 unsigned int i; 1434 1435 dev_dbg_ratelimited(xdev->dev, 1436 "error irq: isr = 0x%08x, eisr = 0x%08x\n", 1437 isr, eisr); 1438 1439 /* Disable channel error interrupts until errors are handled. */ 1440 dpdma_write(xdev->reg, XILINX_DPDMA_IDS, 1441 isr & ~XILINX_DPDMA_INTR_GLOBAL_ERR); 1442 dpdma_write(xdev->reg, XILINX_DPDMA_EIDS, 1443 eisr & ~XILINX_DPDMA_EINTR_GLOBAL_ERR); 1444 1445 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) 1446 if (err || xilinx_dpdma_chan_err(xdev->chan[i], isr, eisr)) 1447 tasklet_schedule(&xdev->chan[i]->err_task); 1448 } 1449 1450 /** 1451 * xilinx_dpdma_enable_irq - Enable interrupts 1452 * @xdev: DPDMA device 1453 * 1454 * Enable interrupts. 1455 */ 1456 static void xilinx_dpdma_enable_irq(struct xilinx_dpdma_device *xdev) 1457 { 1458 dpdma_write(xdev->reg, XILINX_DPDMA_IEN, XILINX_DPDMA_INTR_ALL); 1459 dpdma_write(xdev->reg, XILINX_DPDMA_EIEN, XILINX_DPDMA_EINTR_ALL); 1460 } 1461 1462 /** 1463 * xilinx_dpdma_disable_irq - Disable interrupts 1464 * @xdev: DPDMA device 1465 * 1466 * Disable interrupts. 1467 */ 1468 static void xilinx_dpdma_disable_irq(struct xilinx_dpdma_device *xdev) 1469 { 1470 dpdma_write(xdev->reg, XILINX_DPDMA_IDS, XILINX_DPDMA_INTR_ERR_ALL); 1471 dpdma_write(xdev->reg, XILINX_DPDMA_EIDS, XILINX_DPDMA_EINTR_ALL); 1472 } 1473 1474 /** 1475 * xilinx_dpdma_chan_err_task - Per channel tasklet for error handling 1476 * @t: pointer to the tasklet associated with this handler 1477 * 1478 * Per channel error handling tasklet. This function waits for the outstanding 1479 * transaction to complete and triggers error handling. After error handling, 1480 * re-enable channel error interrupts, and restart the channel if needed. 1481 */ 1482 static void xilinx_dpdma_chan_err_task(struct tasklet_struct *t) 1483 { 1484 struct xilinx_dpdma_chan *chan = from_tasklet(chan, t, err_task); 1485 struct xilinx_dpdma_device *xdev = chan->xdev; 1486 unsigned long flags; 1487 1488 /* Proceed error handling even when polling fails. */ 1489 xilinx_dpdma_chan_poll_no_ostand(chan); 1490 1491 xilinx_dpdma_chan_handle_err(chan); 1492 1493 dpdma_write(xdev->reg, XILINX_DPDMA_IEN, 1494 XILINX_DPDMA_INTR_CHAN_ERR_MASK << chan->id); 1495 dpdma_write(xdev->reg, XILINX_DPDMA_EIEN, 1496 XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id); 1497 1498 spin_lock_irqsave(&chan->lock, flags); 1499 xilinx_dpdma_chan_queue_transfer(chan); 1500 spin_unlock_irqrestore(&chan->lock, flags); 1501 } 1502 1503 static irqreturn_t xilinx_dpdma_irq_handler(int irq, void *data) 1504 { 1505 struct xilinx_dpdma_device *xdev = data; 1506 unsigned long mask; 1507 unsigned int i; 1508 u32 status; 1509 u32 error; 1510 1511 status = dpdma_read(xdev->reg, XILINX_DPDMA_ISR); 1512 error = dpdma_read(xdev->reg, XILINX_DPDMA_EISR); 1513 if (!status && !error) 1514 return IRQ_NONE; 1515 1516 dpdma_write(xdev->reg, XILINX_DPDMA_ISR, status); 1517 dpdma_write(xdev->reg, XILINX_DPDMA_EISR, error); 1518 1519 if (status & XILINX_DPDMA_INTR_VSYNC) { 1520 /* 1521 * There's a single VSYNC interrupt that needs to be processed 1522 * by each running channel to update the active descriptor. 1523 */ 1524 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) { 1525 struct xilinx_dpdma_chan *chan = xdev->chan[i]; 1526 1527 if (chan) 1528 xilinx_dpdma_chan_vsync_irq(chan); 1529 } 1530 } 1531 1532 mask = FIELD_GET(XILINX_DPDMA_INTR_DESC_DONE_MASK, status); 1533 if (mask) { 1534 for_each_set_bit(i, &mask, ARRAY_SIZE(xdev->chan)) 1535 xilinx_dpdma_chan_done_irq(xdev->chan[i]); 1536 } 1537 1538 mask = FIELD_GET(XILINX_DPDMA_INTR_NO_OSTAND_MASK, status); 1539 if (mask) { 1540 for_each_set_bit(i, &mask, ARRAY_SIZE(xdev->chan)) 1541 xilinx_dpdma_chan_notify_no_ostand(xdev->chan[i]); 1542 } 1543 1544 mask = status & XILINX_DPDMA_INTR_ERR_ALL; 1545 if (mask || error) 1546 xilinx_dpdma_handle_err_irq(xdev, mask, error); 1547 1548 return IRQ_HANDLED; 1549 } 1550 1551 /* ----------------------------------------------------------------------------- 1552 * Initialization & Cleanup 1553 */ 1554 1555 static int xilinx_dpdma_chan_init(struct xilinx_dpdma_device *xdev, 1556 unsigned int chan_id) 1557 { 1558 struct xilinx_dpdma_chan *chan; 1559 1560 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL); 1561 if (!chan) 1562 return -ENOMEM; 1563 1564 chan->id = chan_id; 1565 chan->reg = xdev->reg + XILINX_DPDMA_CH_BASE 1566 + XILINX_DPDMA_CH_OFFSET * chan->id; 1567 chan->running = false; 1568 chan->xdev = xdev; 1569 1570 spin_lock_init(&chan->lock); 1571 init_waitqueue_head(&chan->wait_to_stop); 1572 1573 tasklet_setup(&chan->err_task, xilinx_dpdma_chan_err_task); 1574 1575 chan->vchan.desc_free = xilinx_dpdma_chan_free_tx_desc; 1576 vchan_init(&chan->vchan, &xdev->common); 1577 1578 xdev->chan[chan->id] = chan; 1579 1580 return 0; 1581 } 1582 1583 static void xilinx_dpdma_chan_remove(struct xilinx_dpdma_chan *chan) 1584 { 1585 if (!chan) 1586 return; 1587 1588 tasklet_kill(&chan->err_task); 1589 list_del(&chan->vchan.chan.device_node); 1590 } 1591 1592 static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec, 1593 struct of_dma *ofdma) 1594 { 1595 struct xilinx_dpdma_device *xdev = ofdma->of_dma_data; 1596 uint32_t chan_id = dma_spec->args[0]; 1597 1598 if (chan_id >= ARRAY_SIZE(xdev->chan)) 1599 return NULL; 1600 1601 if (!xdev->chan[chan_id]) 1602 return NULL; 1603 1604 return dma_get_slave_channel(&xdev->chan[chan_id]->vchan.chan); 1605 } 1606 1607 static int xilinx_dpdma_probe(struct platform_device *pdev) 1608 { 1609 struct xilinx_dpdma_device *xdev; 1610 struct dma_device *ddev; 1611 unsigned int i; 1612 int ret; 1613 1614 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL); 1615 if (!xdev) 1616 return -ENOMEM; 1617 1618 xdev->dev = &pdev->dev; 1619 xdev->ext_addr = sizeof(dma_addr_t) > 4; 1620 1621 INIT_LIST_HEAD(&xdev->common.channels); 1622 1623 platform_set_drvdata(pdev, xdev); 1624 1625 xdev->axi_clk = devm_clk_get(xdev->dev, "axi_clk"); 1626 if (IS_ERR(xdev->axi_clk)) 1627 return PTR_ERR(xdev->axi_clk); 1628 1629 xdev->reg = devm_platform_ioremap_resource(pdev, 0); 1630 if (IS_ERR(xdev->reg)) 1631 return PTR_ERR(xdev->reg); 1632 1633 xdev->irq = platform_get_irq(pdev, 0); 1634 if (xdev->irq < 0) { 1635 dev_err(xdev->dev, "failed to get platform irq\n"); 1636 return xdev->irq; 1637 } 1638 1639 ret = request_irq(xdev->irq, xilinx_dpdma_irq_handler, IRQF_SHARED, 1640 dev_name(xdev->dev), xdev); 1641 if (ret) { 1642 dev_err(xdev->dev, "failed to request IRQ\n"); 1643 return ret; 1644 } 1645 1646 ddev = &xdev->common; 1647 ddev->dev = &pdev->dev; 1648 1649 dma_cap_set(DMA_SLAVE, ddev->cap_mask); 1650 dma_cap_set(DMA_PRIVATE, ddev->cap_mask); 1651 dma_cap_set(DMA_INTERLEAVE, ddev->cap_mask); 1652 dma_cap_set(DMA_REPEAT, ddev->cap_mask); 1653 dma_cap_set(DMA_LOAD_EOT, ddev->cap_mask); 1654 ddev->copy_align = fls(XILINX_DPDMA_ALIGN_BYTES - 1); 1655 1656 ddev->device_alloc_chan_resources = xilinx_dpdma_alloc_chan_resources; 1657 ddev->device_free_chan_resources = xilinx_dpdma_free_chan_resources; 1658 ddev->device_prep_interleaved_dma = xilinx_dpdma_prep_interleaved_dma; 1659 /* TODO: Can we achieve better granularity ? */ 1660 ddev->device_tx_status = dma_cookie_status; 1661 ddev->device_issue_pending = xilinx_dpdma_issue_pending; 1662 ddev->device_config = xilinx_dpdma_config; 1663 ddev->device_pause = xilinx_dpdma_pause; 1664 ddev->device_resume = xilinx_dpdma_resume; 1665 ddev->device_terminate_all = xilinx_dpdma_terminate_all; 1666 ddev->device_synchronize = xilinx_dpdma_synchronize; 1667 ddev->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED); 1668 ddev->directions = BIT(DMA_MEM_TO_DEV); 1669 ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; 1670 1671 for (i = 0; i < ARRAY_SIZE(xdev->chan); ++i) { 1672 ret = xilinx_dpdma_chan_init(xdev, i); 1673 if (ret < 0) { 1674 dev_err(xdev->dev, "failed to initialize channel %u\n", 1675 i); 1676 goto error; 1677 } 1678 } 1679 1680 ret = clk_prepare_enable(xdev->axi_clk); 1681 if (ret) { 1682 dev_err(xdev->dev, "failed to enable the axi clock\n"); 1683 goto error; 1684 } 1685 1686 ret = dma_async_device_register(ddev); 1687 if (ret) { 1688 dev_err(xdev->dev, "failed to register the dma device\n"); 1689 goto error_dma_async; 1690 } 1691 1692 ret = of_dma_controller_register(xdev->dev->of_node, 1693 of_dma_xilinx_xlate, ddev); 1694 if (ret) { 1695 dev_err(xdev->dev, "failed to register DMA to DT DMA helper\n"); 1696 goto error_of_dma; 1697 } 1698 1699 xilinx_dpdma_enable_irq(xdev); 1700 1701 xilinx_dpdma_debugfs_init(xdev); 1702 1703 dev_info(&pdev->dev, "Xilinx DPDMA engine is probed\n"); 1704 1705 return 0; 1706 1707 error_of_dma: 1708 dma_async_device_unregister(ddev); 1709 error_dma_async: 1710 clk_disable_unprepare(xdev->axi_clk); 1711 error: 1712 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) 1713 xilinx_dpdma_chan_remove(xdev->chan[i]); 1714 1715 free_irq(xdev->irq, xdev); 1716 1717 return ret; 1718 } 1719 1720 static int xilinx_dpdma_remove(struct platform_device *pdev) 1721 { 1722 struct xilinx_dpdma_device *xdev = platform_get_drvdata(pdev); 1723 unsigned int i; 1724 1725 /* Start by disabling the IRQ to avoid races during cleanup. */ 1726 free_irq(xdev->irq, xdev); 1727 1728 xilinx_dpdma_disable_irq(xdev); 1729 of_dma_controller_free(pdev->dev.of_node); 1730 dma_async_device_unregister(&xdev->common); 1731 clk_disable_unprepare(xdev->axi_clk); 1732 1733 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) 1734 xilinx_dpdma_chan_remove(xdev->chan[i]); 1735 1736 return 0; 1737 } 1738 1739 static const struct of_device_id xilinx_dpdma_of_match[] = { 1740 { .compatible = "xlnx,zynqmp-dpdma",}, 1741 { /* end of table */ }, 1742 }; 1743 MODULE_DEVICE_TABLE(of, xilinx_dpdma_of_match); 1744 1745 static struct platform_driver xilinx_dpdma_driver = { 1746 .probe = xilinx_dpdma_probe, 1747 .remove = xilinx_dpdma_remove, 1748 .driver = { 1749 .name = "xilinx-zynqmp-dpdma", 1750 .of_match_table = xilinx_dpdma_of_match, 1751 }, 1752 }; 1753 1754 module_platform_driver(xilinx_dpdma_driver); 1755 1756 MODULE_AUTHOR("Xilinx, Inc."); 1757 MODULE_DESCRIPTION("Xilinx ZynqMP DPDMA driver"); 1758 MODULE_LICENSE("GPL v2"); 1759