1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Xilinx ZynqMP DPDMA Engine driver
4 *
5 * Copyright (C) 2015 - 2020 Xilinx, Inc.
6 *
7 * Author: Hyun Woo Kwon <hyun.kwon@xilinx.com>
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/clk.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/dma/xilinx_dpdma.h>
16 #include <linux/dmaengine.h>
17 #include <linux/dmapool.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/of.h>
21 #include <linux/of_dma.h>
22 #include <linux/platform_device.h>
23 #include <linux/sched.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/wait.h>
27
28 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
29
30 #include "../dmaengine.h"
31 #include "../virt-dma.h"
32
33 /* DPDMA registers */
34 #define XILINX_DPDMA_ERR_CTRL 0x000
35 #define XILINX_DPDMA_ISR 0x004
36 #define XILINX_DPDMA_IMR 0x008
37 #define XILINX_DPDMA_IEN 0x00c
38 #define XILINX_DPDMA_IDS 0x010
39 #define XILINX_DPDMA_INTR_DESC_DONE(n) BIT((n) + 0)
40 #define XILINX_DPDMA_INTR_DESC_DONE_MASK GENMASK(5, 0)
41 #define XILINX_DPDMA_INTR_NO_OSTAND(n) BIT((n) + 6)
42 #define XILINX_DPDMA_INTR_NO_OSTAND_MASK GENMASK(11, 6)
43 #define XILINX_DPDMA_INTR_AXI_ERR(n) BIT((n) + 12)
44 #define XILINX_DPDMA_INTR_AXI_ERR_MASK GENMASK(17, 12)
45 #define XILINX_DPDMA_INTR_DESC_ERR(n) BIT((n) + 16)
46 #define XILINX_DPDMA_INTR_DESC_ERR_MASK GENMASK(23, 18)
47 #define XILINX_DPDMA_INTR_WR_CMD_FIFO_FULL BIT(24)
48 #define XILINX_DPDMA_INTR_WR_DATA_FIFO_FULL BIT(25)
49 #define XILINX_DPDMA_INTR_AXI_4K_CROSS BIT(26)
50 #define XILINX_DPDMA_INTR_VSYNC BIT(27)
51 #define XILINX_DPDMA_INTR_CHAN_ERR_MASK 0x00041000
52 #define XILINX_DPDMA_INTR_CHAN_ERR 0x00fff000
53 #define XILINX_DPDMA_INTR_GLOBAL_ERR 0x07000000
54 #define XILINX_DPDMA_INTR_ERR_ALL 0x07fff000
55 #define XILINX_DPDMA_INTR_CHAN_MASK 0x00041041
56 #define XILINX_DPDMA_INTR_GLOBAL_MASK 0x0f000000
57 #define XILINX_DPDMA_INTR_ALL 0x0fffffff
58 #define XILINX_DPDMA_EISR 0x014
59 #define XILINX_DPDMA_EIMR 0x018
60 #define XILINX_DPDMA_EIEN 0x01c
61 #define XILINX_DPDMA_EIDS 0x020
62 #define XILINX_DPDMA_EINTR_INV_APB BIT(0)
63 #define XILINX_DPDMA_EINTR_RD_AXI_ERR(n) BIT((n) + 1)
64 #define XILINX_DPDMA_EINTR_RD_AXI_ERR_MASK GENMASK(6, 1)
65 #define XILINX_DPDMA_EINTR_PRE_ERR(n) BIT((n) + 7)
66 #define XILINX_DPDMA_EINTR_PRE_ERR_MASK GENMASK(12, 7)
67 #define XILINX_DPDMA_EINTR_CRC_ERR(n) BIT((n) + 13)
68 #define XILINX_DPDMA_EINTR_CRC_ERR_MASK GENMASK(18, 13)
69 #define XILINX_DPDMA_EINTR_WR_AXI_ERR(n) BIT((n) + 19)
70 #define XILINX_DPDMA_EINTR_WR_AXI_ERR_MASK GENMASK(24, 19)
71 #define XILINX_DPDMA_EINTR_DESC_DONE_ERR(n) BIT((n) + 25)
72 #define XILINX_DPDMA_EINTR_DESC_DONE_ERR_MASK GENMASK(30, 25)
73 #define XILINX_DPDMA_EINTR_RD_CMD_FIFO_FULL BIT(32)
74 #define XILINX_DPDMA_EINTR_CHAN_ERR_MASK 0x02082082
75 #define XILINX_DPDMA_EINTR_CHAN_ERR 0x7ffffffe
76 #define XILINX_DPDMA_EINTR_GLOBAL_ERR 0x80000001
77 #define XILINX_DPDMA_EINTR_ALL 0xffffffff
78 #define XILINX_DPDMA_CNTL 0x100
79 #define XILINX_DPDMA_GBL 0x104
80 #define XILINX_DPDMA_GBL_TRIG_MASK(n) ((n) << 0)
81 #define XILINX_DPDMA_GBL_RETRIG_MASK(n) ((n) << 6)
82 #define XILINX_DPDMA_ALC0_CNTL 0x108
83 #define XILINX_DPDMA_ALC0_STATUS 0x10c
84 #define XILINX_DPDMA_ALC0_MAX 0x110
85 #define XILINX_DPDMA_ALC0_MIN 0x114
86 #define XILINX_DPDMA_ALC0_ACC 0x118
87 #define XILINX_DPDMA_ALC0_ACC_TRAN 0x11c
88 #define XILINX_DPDMA_ALC1_CNTL 0x120
89 #define XILINX_DPDMA_ALC1_STATUS 0x124
90 #define XILINX_DPDMA_ALC1_MAX 0x128
91 #define XILINX_DPDMA_ALC1_MIN 0x12c
92 #define XILINX_DPDMA_ALC1_ACC 0x130
93 #define XILINX_DPDMA_ALC1_ACC_TRAN 0x134
94
95 /* Channel register */
96 #define XILINX_DPDMA_CH_BASE 0x200
97 #define XILINX_DPDMA_CH_OFFSET 0x100
98 #define XILINX_DPDMA_CH_DESC_START_ADDRE 0x000
99 #define XILINX_DPDMA_CH_DESC_START_ADDRE_MASK GENMASK(15, 0)
100 #define XILINX_DPDMA_CH_DESC_START_ADDR 0x004
101 #define XILINX_DPDMA_CH_DESC_NEXT_ADDRE 0x008
102 #define XILINX_DPDMA_CH_DESC_NEXT_ADDR 0x00c
103 #define XILINX_DPDMA_CH_PYLD_CUR_ADDRE 0x010
104 #define XILINX_DPDMA_CH_PYLD_CUR_ADDR 0x014
105 #define XILINX_DPDMA_CH_CNTL 0x018
106 #define XILINX_DPDMA_CH_CNTL_ENABLE BIT(0)
107 #define XILINX_DPDMA_CH_CNTL_PAUSE BIT(1)
108 #define XILINX_DPDMA_CH_CNTL_QOS_DSCR_WR_MASK GENMASK(5, 2)
109 #define XILINX_DPDMA_CH_CNTL_QOS_DSCR_RD_MASK GENMASK(9, 6)
110 #define XILINX_DPDMA_CH_CNTL_QOS_DATA_RD_MASK GENMASK(13, 10)
111 #define XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS 11
112 #define XILINX_DPDMA_CH_STATUS 0x01c
113 #define XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK GENMASK(24, 21)
114 #define XILINX_DPDMA_CH_VDO 0x020
115 #define XILINX_DPDMA_CH_PYLD_SZ 0x024
116 #define XILINX_DPDMA_CH_DESC_ID 0x028
117 #define XILINX_DPDMA_CH_DESC_ID_MASK GENMASK(15, 0)
118
119 /* DPDMA descriptor fields */
120 #define XILINX_DPDMA_DESC_CONTROL_PREEMBLE 0xa5
121 #define XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR BIT(8)
122 #define XILINX_DPDMA_DESC_CONTROL_DESC_UPDATE BIT(9)
123 #define XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE BIT(10)
124 #define XILINX_DPDMA_DESC_CONTROL_FRAG_MODE BIT(18)
125 #define XILINX_DPDMA_DESC_CONTROL_LAST BIT(19)
126 #define XILINX_DPDMA_DESC_CONTROL_ENABLE_CRC BIT(20)
127 #define XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME BIT(21)
128 #define XILINX_DPDMA_DESC_ID_MASK GENMASK(15, 0)
129 #define XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK GENMASK(17, 0)
130 #define XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK GENMASK(31, 18)
131 #define XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK GENMASK(15, 0)
132 #define XILINX_DPDMA_DESC_ADDR_EXT_SRC_ADDR_MASK GENMASK(31, 16)
133
134 #define XILINX_DPDMA_ALIGN_BYTES 256
135 #define XILINX_DPDMA_LINESIZE_ALIGN_BITS 128
136
137 #define XILINX_DPDMA_NUM_CHAN 6
138
139 struct xilinx_dpdma_chan;
140
141 /**
142 * struct xilinx_dpdma_hw_desc - DPDMA hardware descriptor
143 * @control: control configuration field
144 * @desc_id: descriptor ID
145 * @xfer_size: transfer size
146 * @hsize_stride: horizontal size and stride
147 * @timestamp_lsb: LSB of time stamp
148 * @timestamp_msb: MSB of time stamp
149 * @addr_ext: upper 16 bit of 48 bit address (next_desc and src_addr)
150 * @next_desc: next descriptor 32 bit address
151 * @src_addr: payload source address (1st page, 32 LSB)
152 * @addr_ext_23: payload source address (3nd and 3rd pages, 16 LSBs)
153 * @addr_ext_45: payload source address (4th and 5th pages, 16 LSBs)
154 * @src_addr2: payload source address (2nd page, 32 LSB)
155 * @src_addr3: payload source address (3rd page, 32 LSB)
156 * @src_addr4: payload source address (4th page, 32 LSB)
157 * @src_addr5: payload source address (5th page, 32 LSB)
158 * @crc: descriptor CRC
159 */
160 struct xilinx_dpdma_hw_desc {
161 u32 control;
162 u32 desc_id;
163 u32 xfer_size;
164 u32 hsize_stride;
165 u32 timestamp_lsb;
166 u32 timestamp_msb;
167 u32 addr_ext;
168 u32 next_desc;
169 u32 src_addr;
170 u32 addr_ext_23;
171 u32 addr_ext_45;
172 u32 src_addr2;
173 u32 src_addr3;
174 u32 src_addr4;
175 u32 src_addr5;
176 u32 crc;
177 } __aligned(XILINX_DPDMA_ALIGN_BYTES);
178
179 /**
180 * struct xilinx_dpdma_sw_desc - DPDMA software descriptor
181 * @hw: DPDMA hardware descriptor
182 * @node: list node for software descriptors
183 * @dma_addr: DMA address of the software descriptor
184 */
185 struct xilinx_dpdma_sw_desc {
186 struct xilinx_dpdma_hw_desc hw;
187 struct list_head node;
188 dma_addr_t dma_addr;
189 };
190
191 /**
192 * struct xilinx_dpdma_tx_desc - DPDMA transaction descriptor
193 * @vdesc: virtual DMA descriptor
194 * @chan: DMA channel
195 * @descriptors: list of software descriptors
196 * @error: an error has been detected with this descriptor
197 */
198 struct xilinx_dpdma_tx_desc {
199 struct virt_dma_desc vdesc;
200 struct xilinx_dpdma_chan *chan;
201 struct list_head descriptors;
202 bool error;
203 };
204
205 #define to_dpdma_tx_desc(_desc) \
206 container_of(_desc, struct xilinx_dpdma_tx_desc, vdesc)
207
208 /**
209 * struct xilinx_dpdma_chan - DPDMA channel
210 * @vchan: virtual DMA channel
211 * @reg: register base address
212 * @id: channel ID
213 * @wait_to_stop: queue to wait for outstanding transacitons before stopping
214 * @running: true if the channel is running
215 * @first_frame: flag for the first frame of stream
216 * @video_group: flag if multi-channel operation is needed for video channels
217 * @lock: lock to access struct xilinx_dpdma_chan. Must be taken before
218 * @vchan.lock, if both are to be held.
219 * @desc_pool: descriptor allocation pool
220 * @err_task: error IRQ bottom half handler
221 * @desc: References to descriptors being processed
222 * @desc.pending: Descriptor schedule to the hardware, pending execution
223 * @desc.active: Descriptor being executed by the hardware
224 * @xdev: DPDMA device
225 */
226 struct xilinx_dpdma_chan {
227 struct virt_dma_chan vchan;
228 void __iomem *reg;
229 unsigned int id;
230
231 wait_queue_head_t wait_to_stop;
232 bool running;
233 bool first_frame;
234 bool video_group;
235
236 spinlock_t lock; /* lock to access struct xilinx_dpdma_chan */
237 struct dma_pool *desc_pool;
238 struct tasklet_struct err_task;
239
240 struct {
241 struct xilinx_dpdma_tx_desc *pending;
242 struct xilinx_dpdma_tx_desc *active;
243 } desc;
244
245 struct xilinx_dpdma_device *xdev;
246 };
247
248 #define to_xilinx_chan(_chan) \
249 container_of(_chan, struct xilinx_dpdma_chan, vchan.chan)
250
251 /**
252 * struct xilinx_dpdma_device - DPDMA device
253 * @common: generic dma device structure
254 * @reg: register base address
255 * @dev: generic device structure
256 * @irq: the interrupt number
257 * @axi_clk: axi clock
258 * @chan: DPDMA channels
259 * @ext_addr: flag for 64 bit system (48 bit addressing)
260 */
261 struct xilinx_dpdma_device {
262 struct dma_device common;
263 void __iomem *reg;
264 struct device *dev;
265 int irq;
266
267 struct clk *axi_clk;
268 struct xilinx_dpdma_chan *chan[XILINX_DPDMA_NUM_CHAN];
269
270 bool ext_addr;
271 };
272
273 /* -----------------------------------------------------------------------------
274 * DebugFS
275 */
276 #define XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE 32
277 #define XILINX_DPDMA_DEBUGFS_UINT16_MAX_STR "65535"
278
279 /* Match xilinx_dpdma_testcases vs dpdma_debugfs_reqs[] entry */
280 enum xilinx_dpdma_testcases {
281 DPDMA_TC_INTR_DONE,
282 DPDMA_TC_NONE
283 };
284
285 struct xilinx_dpdma_debugfs {
286 enum xilinx_dpdma_testcases testcase;
287 u16 xilinx_dpdma_irq_done_count;
288 unsigned int chan_id;
289 };
290
291 static struct xilinx_dpdma_debugfs dpdma_debugfs;
292 struct xilinx_dpdma_debugfs_request {
293 const char *name;
294 enum xilinx_dpdma_testcases tc;
295 ssize_t (*read)(char *buf);
296 int (*write)(char *args);
297 };
298
xilinx_dpdma_debugfs_desc_done_irq(struct xilinx_dpdma_chan * chan)299 static void xilinx_dpdma_debugfs_desc_done_irq(struct xilinx_dpdma_chan *chan)
300 {
301 if (IS_ENABLED(CONFIG_DEBUG_FS) && chan->id == dpdma_debugfs.chan_id)
302 dpdma_debugfs.xilinx_dpdma_irq_done_count++;
303 }
304
xilinx_dpdma_debugfs_desc_done_irq_read(char * buf)305 static ssize_t xilinx_dpdma_debugfs_desc_done_irq_read(char *buf)
306 {
307 size_t out_str_len;
308
309 dpdma_debugfs.testcase = DPDMA_TC_NONE;
310
311 out_str_len = strlen(XILINX_DPDMA_DEBUGFS_UINT16_MAX_STR);
312 out_str_len = min_t(size_t, XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE,
313 out_str_len);
314 snprintf(buf, out_str_len, "%d",
315 dpdma_debugfs.xilinx_dpdma_irq_done_count);
316
317 return 0;
318 }
319
xilinx_dpdma_debugfs_desc_done_irq_write(char * args)320 static int xilinx_dpdma_debugfs_desc_done_irq_write(char *args)
321 {
322 char *arg;
323 int ret;
324 u32 id;
325
326 arg = strsep(&args, " ");
327 if (!arg || strncasecmp(arg, "start", 5))
328 return -EINVAL;
329
330 arg = strsep(&args, " ");
331 if (!arg)
332 return -EINVAL;
333
334 ret = kstrtou32(arg, 0, &id);
335 if (ret < 0)
336 return ret;
337
338 if (id < ZYNQMP_DPDMA_VIDEO0 || id > ZYNQMP_DPDMA_AUDIO1)
339 return -EINVAL;
340
341 dpdma_debugfs.testcase = DPDMA_TC_INTR_DONE;
342 dpdma_debugfs.xilinx_dpdma_irq_done_count = 0;
343 dpdma_debugfs.chan_id = id;
344
345 return 0;
346 }
347
348 /* Match xilinx_dpdma_testcases vs dpdma_debugfs_reqs[] entry */
349 static struct xilinx_dpdma_debugfs_request dpdma_debugfs_reqs[] = {
350 {
351 .name = "DESCRIPTOR_DONE_INTR",
352 .tc = DPDMA_TC_INTR_DONE,
353 .read = xilinx_dpdma_debugfs_desc_done_irq_read,
354 .write = xilinx_dpdma_debugfs_desc_done_irq_write,
355 },
356 };
357
xilinx_dpdma_debugfs_read(struct file * f,char __user * buf,size_t size,loff_t * pos)358 static ssize_t xilinx_dpdma_debugfs_read(struct file *f, char __user *buf,
359 size_t size, loff_t *pos)
360 {
361 enum xilinx_dpdma_testcases testcase;
362 char *kern_buff;
363 int ret = 0;
364
365 if (*pos != 0 || size <= 0)
366 return -EINVAL;
367
368 kern_buff = kzalloc(XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE, GFP_KERNEL);
369 if (!kern_buff) {
370 dpdma_debugfs.testcase = DPDMA_TC_NONE;
371 return -ENOMEM;
372 }
373
374 testcase = READ_ONCE(dpdma_debugfs.testcase);
375 if (testcase != DPDMA_TC_NONE) {
376 ret = dpdma_debugfs_reqs[testcase].read(kern_buff);
377 if (ret < 0)
378 goto done;
379 } else {
380 strscpy(kern_buff, "No testcase executed",
381 XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE);
382 }
383
384 size = min(size, strlen(kern_buff));
385 if (copy_to_user(buf, kern_buff, size))
386 ret = -EFAULT;
387
388 done:
389 kfree(kern_buff);
390 if (ret)
391 return ret;
392
393 *pos = size + 1;
394 return size;
395 }
396
xilinx_dpdma_debugfs_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)397 static ssize_t xilinx_dpdma_debugfs_write(struct file *f,
398 const char __user *buf, size_t size,
399 loff_t *pos)
400 {
401 char *kern_buff, *kern_buff_start;
402 char *testcase;
403 unsigned int i;
404 int ret;
405
406 if (*pos != 0 || size <= 0)
407 return -EINVAL;
408
409 /* Supporting single instance of test as of now. */
410 if (dpdma_debugfs.testcase != DPDMA_TC_NONE)
411 return -EBUSY;
412
413 kern_buff = kzalloc(size, GFP_KERNEL);
414 if (!kern_buff)
415 return -ENOMEM;
416 kern_buff_start = kern_buff;
417
418 ret = strncpy_from_user(kern_buff, buf, size);
419 if (ret < 0)
420 goto done;
421
422 /* Read the testcase name from a user request. */
423 testcase = strsep(&kern_buff, " ");
424
425 for (i = 0; i < ARRAY_SIZE(dpdma_debugfs_reqs); i++) {
426 if (!strcasecmp(testcase, dpdma_debugfs_reqs[i].name))
427 break;
428 }
429
430 if (i == ARRAY_SIZE(dpdma_debugfs_reqs)) {
431 ret = -EINVAL;
432 goto done;
433 }
434
435 ret = dpdma_debugfs_reqs[i].write(kern_buff);
436 if (ret < 0)
437 goto done;
438
439 ret = size;
440
441 done:
442 kfree(kern_buff_start);
443 return ret;
444 }
445
446 static const struct file_operations fops_xilinx_dpdma_dbgfs = {
447 .owner = THIS_MODULE,
448 .read = xilinx_dpdma_debugfs_read,
449 .write = xilinx_dpdma_debugfs_write,
450 };
451
xilinx_dpdma_debugfs_init(struct xilinx_dpdma_device * xdev)452 static void xilinx_dpdma_debugfs_init(struct xilinx_dpdma_device *xdev)
453 {
454 struct dentry *dent;
455
456 dpdma_debugfs.testcase = DPDMA_TC_NONE;
457
458 dent = debugfs_create_file("testcase", 0444, xdev->common.dbg_dev_root,
459 NULL, &fops_xilinx_dpdma_dbgfs);
460 if (IS_ERR(dent))
461 dev_err(xdev->dev, "Failed to create debugfs testcase file\n");
462 }
463
464 /* -----------------------------------------------------------------------------
465 * I/O Accessors
466 */
467
dpdma_read(void __iomem * base,u32 offset)468 static inline u32 dpdma_read(void __iomem *base, u32 offset)
469 {
470 return ioread32(base + offset);
471 }
472
dpdma_write(void __iomem * base,u32 offset,u32 val)473 static inline void dpdma_write(void __iomem *base, u32 offset, u32 val)
474 {
475 iowrite32(val, base + offset);
476 }
477
dpdma_clr(void __iomem * base,u32 offset,u32 clr)478 static inline void dpdma_clr(void __iomem *base, u32 offset, u32 clr)
479 {
480 dpdma_write(base, offset, dpdma_read(base, offset) & ~clr);
481 }
482
dpdma_set(void __iomem * base,u32 offset,u32 set)483 static inline void dpdma_set(void __iomem *base, u32 offset, u32 set)
484 {
485 dpdma_write(base, offset, dpdma_read(base, offset) | set);
486 }
487
488 /* -----------------------------------------------------------------------------
489 * Descriptor Operations
490 */
491
492 /**
493 * xilinx_dpdma_sw_desc_set_dma_addrs - Set DMA addresses in the descriptor
494 * @xdev: DPDMA device
495 * @sw_desc: The software descriptor in which to set DMA addresses
496 * @prev: The previous descriptor
497 * @dma_addr: array of dma addresses
498 * @num_src_addr: number of addresses in @dma_addr
499 *
500 * Set all the DMA addresses in the hardware descriptor corresponding to @dev
501 * from @dma_addr. If a previous descriptor is specified in @prev, its next
502 * descriptor DMA address is set to the DMA address of @sw_desc. @prev may be
503 * identical to @sw_desc for cyclic transfers.
504 */
xilinx_dpdma_sw_desc_set_dma_addrs(struct xilinx_dpdma_device * xdev,struct xilinx_dpdma_sw_desc * sw_desc,struct xilinx_dpdma_sw_desc * prev,dma_addr_t dma_addr[],unsigned int num_src_addr)505 static void xilinx_dpdma_sw_desc_set_dma_addrs(struct xilinx_dpdma_device *xdev,
506 struct xilinx_dpdma_sw_desc *sw_desc,
507 struct xilinx_dpdma_sw_desc *prev,
508 dma_addr_t dma_addr[],
509 unsigned int num_src_addr)
510 {
511 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;
512 unsigned int i;
513
514 hw_desc->src_addr = lower_32_bits(dma_addr[0]);
515 if (xdev->ext_addr)
516 hw_desc->addr_ext |=
517 FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_SRC_ADDR_MASK,
518 upper_32_bits(dma_addr[0]));
519
520 for (i = 1; i < num_src_addr; i++) {
521 u32 *addr = &hw_desc->src_addr2;
522
523 addr[i - 1] = lower_32_bits(dma_addr[i]);
524
525 if (xdev->ext_addr) {
526 u32 *addr_ext = &hw_desc->addr_ext_23;
527 u32 addr_msb;
528
529 addr_msb = upper_32_bits(dma_addr[i]) & GENMASK(15, 0);
530 addr_msb <<= 16 * ((i - 1) % 2);
531 addr_ext[(i - 1) / 2] |= addr_msb;
532 }
533 }
534
535 if (!prev)
536 return;
537
538 prev->hw.next_desc = lower_32_bits(sw_desc->dma_addr);
539 if (xdev->ext_addr)
540 prev->hw.addr_ext |=
541 FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK,
542 upper_32_bits(sw_desc->dma_addr));
543 }
544
545 /**
546 * xilinx_dpdma_chan_alloc_sw_desc - Allocate a software descriptor
547 * @chan: DPDMA channel
548 *
549 * Allocate a software descriptor from the channel's descriptor pool.
550 *
551 * Return: a software descriptor or NULL.
552 */
553 static struct xilinx_dpdma_sw_desc *
xilinx_dpdma_chan_alloc_sw_desc(struct xilinx_dpdma_chan * chan)554 xilinx_dpdma_chan_alloc_sw_desc(struct xilinx_dpdma_chan *chan)
555 {
556 struct xilinx_dpdma_sw_desc *sw_desc;
557 dma_addr_t dma_addr;
558
559 sw_desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &dma_addr);
560 if (!sw_desc)
561 return NULL;
562
563 sw_desc->dma_addr = dma_addr;
564
565 return sw_desc;
566 }
567
568 /**
569 * xilinx_dpdma_chan_free_sw_desc - Free a software descriptor
570 * @chan: DPDMA channel
571 * @sw_desc: software descriptor to free
572 *
573 * Free a software descriptor from the channel's descriptor pool.
574 */
575 static void
xilinx_dpdma_chan_free_sw_desc(struct xilinx_dpdma_chan * chan,struct xilinx_dpdma_sw_desc * sw_desc)576 xilinx_dpdma_chan_free_sw_desc(struct xilinx_dpdma_chan *chan,
577 struct xilinx_dpdma_sw_desc *sw_desc)
578 {
579 dma_pool_free(chan->desc_pool, sw_desc, sw_desc->dma_addr);
580 }
581
582 /**
583 * xilinx_dpdma_chan_dump_tx_desc - Dump a tx descriptor
584 * @chan: DPDMA channel
585 * @tx_desc: tx descriptor to dump
586 *
587 * Dump contents of a tx descriptor
588 */
xilinx_dpdma_chan_dump_tx_desc(struct xilinx_dpdma_chan * chan,struct xilinx_dpdma_tx_desc * tx_desc)589 static void xilinx_dpdma_chan_dump_tx_desc(struct xilinx_dpdma_chan *chan,
590 struct xilinx_dpdma_tx_desc *tx_desc)
591 {
592 struct xilinx_dpdma_sw_desc *sw_desc;
593 struct device *dev = chan->xdev->dev;
594 unsigned int i = 0;
595
596 dev_dbg(dev, "------- TX descriptor dump start -------\n");
597 dev_dbg(dev, "------- channel ID = %d -------\n", chan->id);
598
599 list_for_each_entry(sw_desc, &tx_desc->descriptors, node) {
600 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw;
601
602 dev_dbg(dev, "------- HW descriptor %d -------\n", i++);
603 dev_dbg(dev, "descriptor DMA addr: %pad\n", &sw_desc->dma_addr);
604 dev_dbg(dev, "control: 0x%08x\n", hw_desc->control);
605 dev_dbg(dev, "desc_id: 0x%08x\n", hw_desc->desc_id);
606 dev_dbg(dev, "xfer_size: 0x%08x\n", hw_desc->xfer_size);
607 dev_dbg(dev, "hsize_stride: 0x%08x\n", hw_desc->hsize_stride);
608 dev_dbg(dev, "timestamp_lsb: 0x%08x\n", hw_desc->timestamp_lsb);
609 dev_dbg(dev, "timestamp_msb: 0x%08x\n", hw_desc->timestamp_msb);
610 dev_dbg(dev, "addr_ext: 0x%08x\n", hw_desc->addr_ext);
611 dev_dbg(dev, "next_desc: 0x%08x\n", hw_desc->next_desc);
612 dev_dbg(dev, "src_addr: 0x%08x\n", hw_desc->src_addr);
613 dev_dbg(dev, "addr_ext_23: 0x%08x\n", hw_desc->addr_ext_23);
614 dev_dbg(dev, "addr_ext_45: 0x%08x\n", hw_desc->addr_ext_45);
615 dev_dbg(dev, "src_addr2: 0x%08x\n", hw_desc->src_addr2);
616 dev_dbg(dev, "src_addr3: 0x%08x\n", hw_desc->src_addr3);
617 dev_dbg(dev, "src_addr4: 0x%08x\n", hw_desc->src_addr4);
618 dev_dbg(dev, "src_addr5: 0x%08x\n", hw_desc->src_addr5);
619 dev_dbg(dev, "crc: 0x%08x\n", hw_desc->crc);
620 }
621
622 dev_dbg(dev, "------- TX descriptor dump end -------\n");
623 }
624
625 /**
626 * xilinx_dpdma_chan_alloc_tx_desc - Allocate a transaction descriptor
627 * @chan: DPDMA channel
628 *
629 * Allocate a tx descriptor.
630 *
631 * Return: a tx descriptor or NULL.
632 */
633 static struct xilinx_dpdma_tx_desc *
xilinx_dpdma_chan_alloc_tx_desc(struct xilinx_dpdma_chan * chan)634 xilinx_dpdma_chan_alloc_tx_desc(struct xilinx_dpdma_chan *chan)
635 {
636 struct xilinx_dpdma_tx_desc *tx_desc;
637
638 tx_desc = kzalloc(sizeof(*tx_desc), GFP_NOWAIT);
639 if (!tx_desc)
640 return NULL;
641
642 INIT_LIST_HEAD(&tx_desc->descriptors);
643 tx_desc->chan = chan;
644 tx_desc->error = false;
645
646 return tx_desc;
647 }
648
649 /**
650 * xilinx_dpdma_chan_free_tx_desc - Free a virtual DMA descriptor
651 * @vdesc: virtual DMA descriptor
652 *
653 * Free the virtual DMA descriptor @vdesc including its software descriptors.
654 */
xilinx_dpdma_chan_free_tx_desc(struct virt_dma_desc * vdesc)655 static void xilinx_dpdma_chan_free_tx_desc(struct virt_dma_desc *vdesc)
656 {
657 struct xilinx_dpdma_sw_desc *sw_desc, *next;
658 struct xilinx_dpdma_tx_desc *desc;
659
660 if (!vdesc)
661 return;
662
663 desc = to_dpdma_tx_desc(vdesc);
664
665 list_for_each_entry_safe(sw_desc, next, &desc->descriptors, node) {
666 list_del(&sw_desc->node);
667 xilinx_dpdma_chan_free_sw_desc(desc->chan, sw_desc);
668 }
669
670 kfree(desc);
671 }
672
673 /**
674 * xilinx_dpdma_chan_prep_interleaved_dma - Prepare an interleaved dma
675 * descriptor
676 * @chan: DPDMA channel
677 * @xt: dma interleaved template
678 *
679 * Prepare a tx descriptor including internal software/hardware descriptors
680 * based on @xt.
681 *
682 * Return: A DPDMA TX descriptor on success, or NULL.
683 */
684 static struct xilinx_dpdma_tx_desc *
xilinx_dpdma_chan_prep_interleaved_dma(struct xilinx_dpdma_chan * chan,struct dma_interleaved_template * xt)685 xilinx_dpdma_chan_prep_interleaved_dma(struct xilinx_dpdma_chan *chan,
686 struct dma_interleaved_template *xt)
687 {
688 struct xilinx_dpdma_tx_desc *tx_desc;
689 struct xilinx_dpdma_sw_desc *sw_desc;
690 struct xilinx_dpdma_hw_desc *hw_desc;
691 size_t hsize = xt->sgl[0].size;
692 size_t stride = hsize + xt->sgl[0].icg;
693
694 if (!IS_ALIGNED(xt->src_start, XILINX_DPDMA_ALIGN_BYTES)) {
695 dev_err(chan->xdev->dev,
696 "chan%u: buffer should be aligned at %d B\n",
697 chan->id, XILINX_DPDMA_ALIGN_BYTES);
698 return NULL;
699 }
700
701 tx_desc = xilinx_dpdma_chan_alloc_tx_desc(chan);
702 if (!tx_desc)
703 return NULL;
704
705 sw_desc = xilinx_dpdma_chan_alloc_sw_desc(chan);
706 if (!sw_desc) {
707 xilinx_dpdma_chan_free_tx_desc(&tx_desc->vdesc);
708 return NULL;
709 }
710
711 xilinx_dpdma_sw_desc_set_dma_addrs(chan->xdev, sw_desc, sw_desc,
712 &xt->src_start, 1);
713
714 hw_desc = &sw_desc->hw;
715 hsize = ALIGN(hsize, XILINX_DPDMA_LINESIZE_ALIGN_BITS / 8);
716 hw_desc->xfer_size = hsize * xt->numf;
717 hw_desc->hsize_stride =
718 FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK, hsize) |
719 FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK,
720 stride / 16);
721 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_PREEMBLE;
722 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR;
723 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE;
724 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME;
725
726 list_add_tail(&sw_desc->node, &tx_desc->descriptors);
727
728 return tx_desc;
729 }
730
731 /* -----------------------------------------------------------------------------
732 * DPDMA Channel Operations
733 */
734
735 /**
736 * xilinx_dpdma_chan_enable - Enable the channel
737 * @chan: DPDMA channel
738 *
739 * Enable the channel and its interrupts. Set the QoS values for video class.
740 */
xilinx_dpdma_chan_enable(struct xilinx_dpdma_chan * chan)741 static void xilinx_dpdma_chan_enable(struct xilinx_dpdma_chan *chan)
742 {
743 u32 reg;
744
745 reg = (XILINX_DPDMA_INTR_CHAN_MASK << chan->id)
746 | XILINX_DPDMA_INTR_GLOBAL_MASK;
747 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg);
748 reg = (XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id)
749 | XILINX_DPDMA_INTR_GLOBAL_ERR;
750 dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg);
751
752 reg = XILINX_DPDMA_CH_CNTL_ENABLE
753 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DSCR_WR_MASK,
754 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS)
755 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DSCR_RD_MASK,
756 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS)
757 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DATA_RD_MASK,
758 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS);
759 dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, reg);
760 }
761
762 /**
763 * xilinx_dpdma_chan_disable - Disable the channel
764 * @chan: DPDMA channel
765 *
766 * Disable the channel and its interrupts.
767 */
xilinx_dpdma_chan_disable(struct xilinx_dpdma_chan * chan)768 static void xilinx_dpdma_chan_disable(struct xilinx_dpdma_chan *chan)
769 {
770 u32 reg;
771
772 reg = XILINX_DPDMA_INTR_CHAN_MASK << chan->id;
773 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg);
774 reg = XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id;
775 dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg);
776
777 dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE);
778 }
779
780 /**
781 * xilinx_dpdma_chan_pause - Pause the channel
782 * @chan: DPDMA channel
783 *
784 * Pause the channel.
785 */
xilinx_dpdma_chan_pause(struct xilinx_dpdma_chan * chan)786 static void xilinx_dpdma_chan_pause(struct xilinx_dpdma_chan *chan)
787 {
788 dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE);
789 }
790
791 /**
792 * xilinx_dpdma_chan_unpause - Unpause the channel
793 * @chan: DPDMA channel
794 *
795 * Unpause the channel.
796 */
xilinx_dpdma_chan_unpause(struct xilinx_dpdma_chan * chan)797 static void xilinx_dpdma_chan_unpause(struct xilinx_dpdma_chan *chan)
798 {
799 dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE);
800 }
801
xilinx_dpdma_chan_video_group_ready(struct xilinx_dpdma_chan * chan)802 static u32 xilinx_dpdma_chan_video_group_ready(struct xilinx_dpdma_chan *chan)
803 {
804 struct xilinx_dpdma_device *xdev = chan->xdev;
805 u32 channels = 0;
806 unsigned int i;
807
808 for (i = ZYNQMP_DPDMA_VIDEO0; i <= ZYNQMP_DPDMA_VIDEO2; i++) {
809 if (xdev->chan[i]->video_group && !xdev->chan[i]->running)
810 return 0;
811
812 if (xdev->chan[i]->video_group)
813 channels |= BIT(i);
814 }
815
816 return channels;
817 }
818
819 /**
820 * xilinx_dpdma_chan_queue_transfer - Queue the next transfer
821 * @chan: DPDMA channel
822 *
823 * Queue the next descriptor, if any, to the hardware. If the channel is
824 * stopped, start it first. Otherwise retrigger it with the next descriptor.
825 */
xilinx_dpdma_chan_queue_transfer(struct xilinx_dpdma_chan * chan)826 static void xilinx_dpdma_chan_queue_transfer(struct xilinx_dpdma_chan *chan)
827 {
828 struct xilinx_dpdma_device *xdev = chan->xdev;
829 struct xilinx_dpdma_sw_desc *sw_desc;
830 struct xilinx_dpdma_tx_desc *desc;
831 struct virt_dma_desc *vdesc;
832 u32 reg, channels;
833 bool first_frame;
834
835 lockdep_assert_held(&chan->lock);
836
837 if (chan->desc.pending)
838 return;
839
840 if (!chan->running) {
841 xilinx_dpdma_chan_unpause(chan);
842 xilinx_dpdma_chan_enable(chan);
843 chan->first_frame = true;
844 chan->running = true;
845 }
846
847 vdesc = vchan_next_desc(&chan->vchan);
848 if (!vdesc)
849 return;
850
851 desc = to_dpdma_tx_desc(vdesc);
852 chan->desc.pending = desc;
853 list_del(&desc->vdesc.node);
854
855 /*
856 * Assign the cookie to descriptors in this transaction. Only 16 bit
857 * will be used, but it should be enough.
858 */
859 list_for_each_entry(sw_desc, &desc->descriptors, node)
860 sw_desc->hw.desc_id = desc->vdesc.tx.cookie
861 & XILINX_DPDMA_CH_DESC_ID_MASK;
862
863 sw_desc = list_first_entry(&desc->descriptors,
864 struct xilinx_dpdma_sw_desc, node);
865 dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR,
866 lower_32_bits(sw_desc->dma_addr));
867 if (xdev->ext_addr)
868 dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE,
869 FIELD_PREP(XILINX_DPDMA_CH_DESC_START_ADDRE_MASK,
870 upper_32_bits(sw_desc->dma_addr)));
871
872 first_frame = chan->first_frame;
873 chan->first_frame = false;
874
875 if (chan->video_group) {
876 channels = xilinx_dpdma_chan_video_group_ready(chan);
877 /*
878 * Trigger the transfer only when all channels in the group are
879 * ready.
880 */
881 if (!channels)
882 return;
883 } else {
884 channels = BIT(chan->id);
885 }
886
887 if (first_frame)
888 reg = XILINX_DPDMA_GBL_TRIG_MASK(channels);
889 else
890 reg = XILINX_DPDMA_GBL_RETRIG_MASK(channels);
891
892 dpdma_write(xdev->reg, XILINX_DPDMA_GBL, reg);
893 }
894
895 /**
896 * xilinx_dpdma_chan_ostand - Number of outstanding transactions
897 * @chan: DPDMA channel
898 *
899 * Read and return the number of outstanding transactions from register.
900 *
901 * Return: Number of outstanding transactions from the status register.
902 */
xilinx_dpdma_chan_ostand(struct xilinx_dpdma_chan * chan)903 static u32 xilinx_dpdma_chan_ostand(struct xilinx_dpdma_chan *chan)
904 {
905 return FIELD_GET(XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK,
906 dpdma_read(chan->reg, XILINX_DPDMA_CH_STATUS));
907 }
908
909 /**
910 * xilinx_dpdma_chan_notify_no_ostand - Notify no outstanding transaction event
911 * @chan: DPDMA channel
912 *
913 * Notify waiters for no outstanding event, so waiters can stop the channel
914 * safely. This function is supposed to be called when 'no outstanding'
915 * interrupt is generated. The 'no outstanding' interrupt is disabled and
916 * should be re-enabled when this event is handled. If the channel status
917 * register still shows some number of outstanding transactions, the interrupt
918 * remains enabled.
919 *
920 * Return: 0 on success. On failure, -EWOULDBLOCK if there's still outstanding
921 * transaction(s).
922 */
xilinx_dpdma_chan_notify_no_ostand(struct xilinx_dpdma_chan * chan)923 static int xilinx_dpdma_chan_notify_no_ostand(struct xilinx_dpdma_chan *chan)
924 {
925 u32 cnt;
926
927 cnt = xilinx_dpdma_chan_ostand(chan);
928 if (cnt) {
929 dev_dbg(chan->xdev->dev,
930 "chan%u: %d outstanding transactions\n",
931 chan->id, cnt);
932 return -EWOULDBLOCK;
933 }
934
935 /* Disable 'no outstanding' interrupt */
936 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IDS,
937 XILINX_DPDMA_INTR_NO_OSTAND(chan->id));
938 wake_up(&chan->wait_to_stop);
939
940 return 0;
941 }
942
943 /**
944 * xilinx_dpdma_chan_wait_no_ostand - Wait for the no outstanding irq
945 * @chan: DPDMA channel
946 *
947 * Wait for the no outstanding transaction interrupt. This functions can sleep
948 * for 50ms.
949 *
950 * Return: 0 on success. On failure, -ETIMEOUT for time out, or the error code
951 * from wait_event_interruptible_timeout().
952 */
xilinx_dpdma_chan_wait_no_ostand(struct xilinx_dpdma_chan * chan)953 static int xilinx_dpdma_chan_wait_no_ostand(struct xilinx_dpdma_chan *chan)
954 {
955 int ret;
956
957 /* Wait for a no outstanding transaction interrupt upto 50msec */
958 ret = wait_event_interruptible_timeout(chan->wait_to_stop,
959 !xilinx_dpdma_chan_ostand(chan),
960 msecs_to_jiffies(50));
961 if (ret > 0) {
962 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN,
963 XILINX_DPDMA_INTR_NO_OSTAND(chan->id));
964 return 0;
965 }
966
967 dev_err(chan->xdev->dev, "chan%u: not ready to stop: %d trans\n",
968 chan->id, xilinx_dpdma_chan_ostand(chan));
969
970 if (ret == 0)
971 return -ETIMEDOUT;
972
973 return ret;
974 }
975
976 /**
977 * xilinx_dpdma_chan_poll_no_ostand - Poll the outstanding transaction status
978 * @chan: DPDMA channel
979 *
980 * Poll the outstanding transaction status, and return when there's no
981 * outstanding transaction. This functions can be used in the interrupt context
982 * or where the atomicity is required. Calling thread may wait more than 50ms.
983 *
984 * Return: 0 on success, or -ETIMEDOUT.
985 */
xilinx_dpdma_chan_poll_no_ostand(struct xilinx_dpdma_chan * chan)986 static int xilinx_dpdma_chan_poll_no_ostand(struct xilinx_dpdma_chan *chan)
987 {
988 u32 cnt, loop = 50000;
989
990 /* Poll at least for 50ms (20 fps). */
991 do {
992 cnt = xilinx_dpdma_chan_ostand(chan);
993 udelay(1);
994 } while (loop-- > 0 && cnt);
995
996 if (loop) {
997 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN,
998 XILINX_DPDMA_INTR_NO_OSTAND(chan->id));
999 return 0;
1000 }
1001
1002 dev_err(chan->xdev->dev, "chan%u: not ready to stop: %d trans\n",
1003 chan->id, xilinx_dpdma_chan_ostand(chan));
1004
1005 return -ETIMEDOUT;
1006 }
1007
1008 /**
1009 * xilinx_dpdma_chan_stop - Stop the channel
1010 * @chan: DPDMA channel
1011 *
1012 * Stop a previously paused channel by first waiting for completion of all
1013 * outstanding transaction and then disabling the channel.
1014 *
1015 * Return: 0 on success, or -ETIMEDOUT if the channel failed to stop.
1016 */
xilinx_dpdma_chan_stop(struct xilinx_dpdma_chan * chan)1017 static int xilinx_dpdma_chan_stop(struct xilinx_dpdma_chan *chan)
1018 {
1019 unsigned long flags;
1020 int ret;
1021
1022 ret = xilinx_dpdma_chan_wait_no_ostand(chan);
1023 if (ret)
1024 return ret;
1025
1026 spin_lock_irqsave(&chan->lock, flags);
1027 xilinx_dpdma_chan_disable(chan);
1028 chan->running = false;
1029 spin_unlock_irqrestore(&chan->lock, flags);
1030
1031 return 0;
1032 }
1033
1034 /**
1035 * xilinx_dpdma_chan_done_irq - Handle hardware descriptor completion
1036 * @chan: DPDMA channel
1037 *
1038 * Handle completion of the currently active descriptor (@chan->desc.active). As
1039 * we currently support cyclic transfers only, this just invokes the cyclic
1040 * callback. The descriptor will be completed at the VSYNC interrupt when a new
1041 * descriptor replaces it.
1042 */
xilinx_dpdma_chan_done_irq(struct xilinx_dpdma_chan * chan)1043 static void xilinx_dpdma_chan_done_irq(struct xilinx_dpdma_chan *chan)
1044 {
1045 struct xilinx_dpdma_tx_desc *active;
1046 unsigned long flags;
1047
1048 spin_lock_irqsave(&chan->lock, flags);
1049
1050 xilinx_dpdma_debugfs_desc_done_irq(chan);
1051
1052 active = chan->desc.active;
1053 if (active)
1054 vchan_cyclic_callback(&active->vdesc);
1055 else
1056 dev_warn(chan->xdev->dev,
1057 "chan%u: DONE IRQ with no active descriptor!\n",
1058 chan->id);
1059
1060 spin_unlock_irqrestore(&chan->lock, flags);
1061 }
1062
1063 /**
1064 * xilinx_dpdma_chan_vsync_irq - Handle hardware descriptor scheduling
1065 * @chan: DPDMA channel
1066 *
1067 * At VSYNC the active descriptor may have been replaced by the pending
1068 * descriptor. Detect this through the DESC_ID and perform appropriate
1069 * bookkeeping.
1070 */
xilinx_dpdma_chan_vsync_irq(struct xilinx_dpdma_chan * chan)1071 static void xilinx_dpdma_chan_vsync_irq(struct xilinx_dpdma_chan *chan)
1072 {
1073 struct xilinx_dpdma_tx_desc *pending;
1074 struct xilinx_dpdma_sw_desc *sw_desc;
1075 unsigned long flags;
1076 u32 desc_id;
1077
1078 spin_lock_irqsave(&chan->lock, flags);
1079
1080 pending = chan->desc.pending;
1081 if (!chan->running || !pending)
1082 goto out;
1083
1084 desc_id = dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_ID)
1085 & XILINX_DPDMA_CH_DESC_ID_MASK;
1086
1087 /* If the retrigger raced with vsync, retry at the next frame. */
1088 sw_desc = list_first_entry(&pending->descriptors,
1089 struct xilinx_dpdma_sw_desc, node);
1090 if (sw_desc->hw.desc_id != desc_id) {
1091 dev_dbg(chan->xdev->dev,
1092 "chan%u: vsync race lost (%u != %u), retrying\n",
1093 chan->id, sw_desc->hw.desc_id, desc_id);
1094 goto out;
1095 }
1096
1097 /*
1098 * Complete the active descriptor, if any, promote the pending
1099 * descriptor to active, and queue the next transfer, if any.
1100 */
1101 spin_lock(&chan->vchan.lock);
1102 if (chan->desc.active)
1103 vchan_cookie_complete(&chan->desc.active->vdesc);
1104 chan->desc.active = pending;
1105 chan->desc.pending = NULL;
1106
1107 xilinx_dpdma_chan_queue_transfer(chan);
1108 spin_unlock(&chan->vchan.lock);
1109
1110 out:
1111 spin_unlock_irqrestore(&chan->lock, flags);
1112 }
1113
1114 /**
1115 * xilinx_dpdma_chan_err - Detect any channel error
1116 * @chan: DPDMA channel
1117 * @isr: masked Interrupt Status Register
1118 * @eisr: Error Interrupt Status Register
1119 *
1120 * Return: true if any channel error occurs, or false otherwise.
1121 */
1122 static bool
xilinx_dpdma_chan_err(struct xilinx_dpdma_chan * chan,u32 isr,u32 eisr)1123 xilinx_dpdma_chan_err(struct xilinx_dpdma_chan *chan, u32 isr, u32 eisr)
1124 {
1125 if (!chan)
1126 return false;
1127
1128 if (chan->running &&
1129 ((isr & (XILINX_DPDMA_INTR_CHAN_ERR_MASK << chan->id)) ||
1130 (eisr & (XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id))))
1131 return true;
1132
1133 return false;
1134 }
1135
1136 /**
1137 * xilinx_dpdma_chan_handle_err - DPDMA channel error handling
1138 * @chan: DPDMA channel
1139 *
1140 * This function is called when any channel error or any global error occurs.
1141 * The function disables the paused channel by errors and determines
1142 * if the current active descriptor can be rescheduled depending on
1143 * the descriptor status.
1144 */
xilinx_dpdma_chan_handle_err(struct xilinx_dpdma_chan * chan)1145 static void xilinx_dpdma_chan_handle_err(struct xilinx_dpdma_chan *chan)
1146 {
1147 struct xilinx_dpdma_device *xdev = chan->xdev;
1148 struct xilinx_dpdma_tx_desc *active;
1149 unsigned long flags;
1150
1151 spin_lock_irqsave(&chan->lock, flags);
1152
1153 dev_dbg(xdev->dev, "chan%u: cur desc addr = 0x%04x%08x\n",
1154 chan->id,
1155 dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE),
1156 dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR));
1157 dev_dbg(xdev->dev, "chan%u: cur payload addr = 0x%04x%08x\n",
1158 chan->id,
1159 dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDRE),
1160 dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDR));
1161
1162 xilinx_dpdma_chan_disable(chan);
1163 chan->running = false;
1164
1165 if (!chan->desc.active)
1166 goto out_unlock;
1167
1168 active = chan->desc.active;
1169 chan->desc.active = NULL;
1170
1171 xilinx_dpdma_chan_dump_tx_desc(chan, active);
1172
1173 if (active->error)
1174 dev_dbg(xdev->dev, "chan%u: repeated error on desc\n",
1175 chan->id);
1176
1177 /* Reschedule if there's no new descriptor */
1178 if (!chan->desc.pending &&
1179 list_empty(&chan->vchan.desc_issued)) {
1180 active->error = true;
1181 list_add_tail(&active->vdesc.node,
1182 &chan->vchan.desc_issued);
1183 } else {
1184 xilinx_dpdma_chan_free_tx_desc(&active->vdesc);
1185 }
1186
1187 out_unlock:
1188 spin_unlock_irqrestore(&chan->lock, flags);
1189 }
1190
1191 /* -----------------------------------------------------------------------------
1192 * DMA Engine Operations
1193 */
1194
1195 static struct dma_async_tx_descriptor *
xilinx_dpdma_prep_interleaved_dma(struct dma_chan * dchan,struct dma_interleaved_template * xt,unsigned long flags)1196 xilinx_dpdma_prep_interleaved_dma(struct dma_chan *dchan,
1197 struct dma_interleaved_template *xt,
1198 unsigned long flags)
1199 {
1200 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1201 struct xilinx_dpdma_tx_desc *desc;
1202
1203 if (xt->dir != DMA_MEM_TO_DEV)
1204 return NULL;
1205
1206 if (!xt->numf || !xt->sgl[0].size)
1207 return NULL;
1208
1209 if (!(flags & DMA_PREP_REPEAT) || !(flags & DMA_PREP_LOAD_EOT))
1210 return NULL;
1211
1212 desc = xilinx_dpdma_chan_prep_interleaved_dma(chan, xt);
1213 if (!desc)
1214 return NULL;
1215
1216 vchan_tx_prep(&chan->vchan, &desc->vdesc, flags | DMA_CTRL_ACK);
1217
1218 return &desc->vdesc.tx;
1219 }
1220
1221 /**
1222 * xilinx_dpdma_alloc_chan_resources - Allocate resources for the channel
1223 * @dchan: DMA channel
1224 *
1225 * Allocate a descriptor pool for the channel.
1226 *
1227 * Return: 0 on success, or -ENOMEM if failed to allocate a pool.
1228 */
xilinx_dpdma_alloc_chan_resources(struct dma_chan * dchan)1229 static int xilinx_dpdma_alloc_chan_resources(struct dma_chan *dchan)
1230 {
1231 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1232 size_t align = __alignof__(struct xilinx_dpdma_sw_desc);
1233
1234 chan->desc_pool = dma_pool_create(dev_name(chan->xdev->dev),
1235 chan->xdev->dev,
1236 sizeof(struct xilinx_dpdma_sw_desc),
1237 align, 0);
1238 if (!chan->desc_pool) {
1239 dev_err(chan->xdev->dev,
1240 "chan%u: failed to allocate a descriptor pool\n",
1241 chan->id);
1242 return -ENOMEM;
1243 }
1244
1245 return 0;
1246 }
1247
1248 /**
1249 * xilinx_dpdma_free_chan_resources - Free all resources for the channel
1250 * @dchan: DMA channel
1251 *
1252 * Free resources associated with the virtual DMA channel, and destroy the
1253 * descriptor pool.
1254 */
xilinx_dpdma_free_chan_resources(struct dma_chan * dchan)1255 static void xilinx_dpdma_free_chan_resources(struct dma_chan *dchan)
1256 {
1257 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1258
1259 vchan_free_chan_resources(&chan->vchan);
1260
1261 dma_pool_destroy(chan->desc_pool);
1262 chan->desc_pool = NULL;
1263 }
1264
xilinx_dpdma_issue_pending(struct dma_chan * dchan)1265 static void xilinx_dpdma_issue_pending(struct dma_chan *dchan)
1266 {
1267 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1268 unsigned long flags;
1269
1270 spin_lock_irqsave(&chan->lock, flags);
1271 spin_lock(&chan->vchan.lock);
1272 if (vchan_issue_pending(&chan->vchan))
1273 xilinx_dpdma_chan_queue_transfer(chan);
1274 spin_unlock(&chan->vchan.lock);
1275 spin_unlock_irqrestore(&chan->lock, flags);
1276 }
1277
xilinx_dpdma_config(struct dma_chan * dchan,struct dma_slave_config * config)1278 static int xilinx_dpdma_config(struct dma_chan *dchan,
1279 struct dma_slave_config *config)
1280 {
1281 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1282 struct xilinx_dpdma_peripheral_config *pconfig;
1283 unsigned long flags;
1284
1285 /*
1286 * The destination address doesn't need to be specified as the DPDMA is
1287 * hardwired to the destination (the DP controller). The transfer
1288 * width, burst size and port window size are thus meaningless, they're
1289 * fixed both on the DPDMA side and on the DP controller side.
1290 */
1291
1292 /*
1293 * Use the peripheral_config to indicate that the channel is part
1294 * of a video group. This requires matching use of the custom
1295 * structure in each driver.
1296 */
1297 pconfig = config->peripheral_config;
1298 if (WARN_ON(pconfig && config->peripheral_size != sizeof(*pconfig)))
1299 return -EINVAL;
1300
1301 spin_lock_irqsave(&chan->lock, flags);
1302 if (chan->id <= ZYNQMP_DPDMA_VIDEO2 && pconfig)
1303 chan->video_group = pconfig->video_group;
1304 spin_unlock_irqrestore(&chan->lock, flags);
1305
1306 return 0;
1307 }
1308
xilinx_dpdma_pause(struct dma_chan * dchan)1309 static int xilinx_dpdma_pause(struct dma_chan *dchan)
1310 {
1311 xilinx_dpdma_chan_pause(to_xilinx_chan(dchan));
1312
1313 return 0;
1314 }
1315
xilinx_dpdma_resume(struct dma_chan * dchan)1316 static int xilinx_dpdma_resume(struct dma_chan *dchan)
1317 {
1318 xilinx_dpdma_chan_unpause(to_xilinx_chan(dchan));
1319
1320 return 0;
1321 }
1322
1323 /**
1324 * xilinx_dpdma_terminate_all - Terminate the channel and descriptors
1325 * @dchan: DMA channel
1326 *
1327 * Pause the channel without waiting for ongoing transfers to complete. Waiting
1328 * for completion is performed by xilinx_dpdma_synchronize() that will disable
1329 * the channel to complete the stop.
1330 *
1331 * All the descriptors associated with the channel that are guaranteed not to
1332 * be touched by the hardware. The pending and active descriptor are not
1333 * touched, and will be freed either upon completion, or by
1334 * xilinx_dpdma_synchronize().
1335 *
1336 * Return: 0 on success, or -ETIMEDOUT if the channel failed to stop.
1337 */
xilinx_dpdma_terminate_all(struct dma_chan * dchan)1338 static int xilinx_dpdma_terminate_all(struct dma_chan *dchan)
1339 {
1340 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1341 struct xilinx_dpdma_device *xdev = chan->xdev;
1342 LIST_HEAD(descriptors);
1343 unsigned long flags;
1344 unsigned int i;
1345
1346 /* Pause the channel (including the whole video group if applicable). */
1347 if (chan->video_group) {
1348 for (i = ZYNQMP_DPDMA_VIDEO0; i <= ZYNQMP_DPDMA_VIDEO2; i++) {
1349 if (xdev->chan[i]->video_group &&
1350 xdev->chan[i]->running) {
1351 xilinx_dpdma_chan_pause(xdev->chan[i]);
1352 xdev->chan[i]->video_group = false;
1353 }
1354 }
1355 } else {
1356 xilinx_dpdma_chan_pause(chan);
1357 }
1358
1359 /* Gather all the descriptors we can free and free them. */
1360 spin_lock_irqsave(&chan->vchan.lock, flags);
1361 vchan_get_all_descriptors(&chan->vchan, &descriptors);
1362 spin_unlock_irqrestore(&chan->vchan.lock, flags);
1363
1364 vchan_dma_desc_free_list(&chan->vchan, &descriptors);
1365
1366 return 0;
1367 }
1368
1369 /**
1370 * xilinx_dpdma_synchronize - Synchronize callback execution
1371 * @dchan: DMA channel
1372 *
1373 * Synchronizing callback execution ensures that all previously issued
1374 * transfers have completed and all associated callbacks have been called and
1375 * have returned.
1376 *
1377 * This function waits for the DMA channel to stop. It assumes it has been
1378 * paused by a previous call to dmaengine_terminate_async(), and that no new
1379 * pending descriptors have been issued with dma_async_issue_pending(). The
1380 * behaviour is undefined otherwise.
1381 */
xilinx_dpdma_synchronize(struct dma_chan * dchan)1382 static void xilinx_dpdma_synchronize(struct dma_chan *dchan)
1383 {
1384 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan);
1385 unsigned long flags;
1386
1387 xilinx_dpdma_chan_stop(chan);
1388
1389 spin_lock_irqsave(&chan->vchan.lock, flags);
1390 if (chan->desc.pending) {
1391 vchan_terminate_vdesc(&chan->desc.pending->vdesc);
1392 chan->desc.pending = NULL;
1393 }
1394 if (chan->desc.active) {
1395 vchan_terminate_vdesc(&chan->desc.active->vdesc);
1396 chan->desc.active = NULL;
1397 }
1398 spin_unlock_irqrestore(&chan->vchan.lock, flags);
1399
1400 vchan_synchronize(&chan->vchan);
1401 }
1402
1403 /* -----------------------------------------------------------------------------
1404 * Interrupt and Tasklet Handling
1405 */
1406
1407 /**
1408 * xilinx_dpdma_err - Detect any global error
1409 * @isr: Interrupt Status Register
1410 * @eisr: Error Interrupt Status Register
1411 *
1412 * Return: True if any global error occurs, or false otherwise.
1413 */
xilinx_dpdma_err(u32 isr,u32 eisr)1414 static bool xilinx_dpdma_err(u32 isr, u32 eisr)
1415 {
1416 if (isr & XILINX_DPDMA_INTR_GLOBAL_ERR ||
1417 eisr & XILINX_DPDMA_EINTR_GLOBAL_ERR)
1418 return true;
1419
1420 return false;
1421 }
1422
1423 /**
1424 * xilinx_dpdma_handle_err_irq - Handle DPDMA error interrupt
1425 * @xdev: DPDMA device
1426 * @isr: masked Interrupt Status Register
1427 * @eisr: Error Interrupt Status Register
1428 *
1429 * Handle if any error occurs based on @isr and @eisr. This function disables
1430 * corresponding error interrupts, and those should be re-enabled once handling
1431 * is done.
1432 */
xilinx_dpdma_handle_err_irq(struct xilinx_dpdma_device * xdev,u32 isr,u32 eisr)1433 static void xilinx_dpdma_handle_err_irq(struct xilinx_dpdma_device *xdev,
1434 u32 isr, u32 eisr)
1435 {
1436 bool err = xilinx_dpdma_err(isr, eisr);
1437 unsigned int i;
1438
1439 dev_dbg_ratelimited(xdev->dev,
1440 "error irq: isr = 0x%08x, eisr = 0x%08x\n",
1441 isr, eisr);
1442
1443 /* Disable channel error interrupts until errors are handled. */
1444 dpdma_write(xdev->reg, XILINX_DPDMA_IDS,
1445 isr & ~XILINX_DPDMA_INTR_GLOBAL_ERR);
1446 dpdma_write(xdev->reg, XILINX_DPDMA_EIDS,
1447 eisr & ~XILINX_DPDMA_EINTR_GLOBAL_ERR);
1448
1449 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++)
1450 if (err || xilinx_dpdma_chan_err(xdev->chan[i], isr, eisr))
1451 tasklet_schedule(&xdev->chan[i]->err_task);
1452 }
1453
1454 /**
1455 * xilinx_dpdma_enable_irq - Enable interrupts
1456 * @xdev: DPDMA device
1457 *
1458 * Enable interrupts.
1459 */
xilinx_dpdma_enable_irq(struct xilinx_dpdma_device * xdev)1460 static void xilinx_dpdma_enable_irq(struct xilinx_dpdma_device *xdev)
1461 {
1462 dpdma_write(xdev->reg, XILINX_DPDMA_IEN, XILINX_DPDMA_INTR_ALL);
1463 dpdma_write(xdev->reg, XILINX_DPDMA_EIEN, XILINX_DPDMA_EINTR_ALL);
1464 }
1465
1466 /**
1467 * xilinx_dpdma_disable_irq - Disable interrupts
1468 * @xdev: DPDMA device
1469 *
1470 * Disable interrupts.
1471 */
xilinx_dpdma_disable_irq(struct xilinx_dpdma_device * xdev)1472 static void xilinx_dpdma_disable_irq(struct xilinx_dpdma_device *xdev)
1473 {
1474 dpdma_write(xdev->reg, XILINX_DPDMA_IDS, XILINX_DPDMA_INTR_ALL);
1475 dpdma_write(xdev->reg, XILINX_DPDMA_EIDS, XILINX_DPDMA_EINTR_ALL);
1476 }
1477
1478 /**
1479 * xilinx_dpdma_chan_err_task - Per channel tasklet for error handling
1480 * @t: pointer to the tasklet associated with this handler
1481 *
1482 * Per channel error handling tasklet. This function waits for the outstanding
1483 * transaction to complete and triggers error handling. After error handling,
1484 * re-enable channel error interrupts, and restart the channel if needed.
1485 */
xilinx_dpdma_chan_err_task(struct tasklet_struct * t)1486 static void xilinx_dpdma_chan_err_task(struct tasklet_struct *t)
1487 {
1488 struct xilinx_dpdma_chan *chan = from_tasklet(chan, t, err_task);
1489 struct xilinx_dpdma_device *xdev = chan->xdev;
1490 unsigned long flags;
1491
1492 /* Proceed error handling even when polling fails. */
1493 xilinx_dpdma_chan_poll_no_ostand(chan);
1494
1495 xilinx_dpdma_chan_handle_err(chan);
1496
1497 dpdma_write(xdev->reg, XILINX_DPDMA_IEN,
1498 XILINX_DPDMA_INTR_CHAN_ERR_MASK << chan->id);
1499 dpdma_write(xdev->reg, XILINX_DPDMA_EIEN,
1500 XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id);
1501
1502 spin_lock_irqsave(&chan->lock, flags);
1503 spin_lock(&chan->vchan.lock);
1504 xilinx_dpdma_chan_queue_transfer(chan);
1505 spin_unlock(&chan->vchan.lock);
1506 spin_unlock_irqrestore(&chan->lock, flags);
1507 }
1508
xilinx_dpdma_irq_handler(int irq,void * data)1509 static irqreturn_t xilinx_dpdma_irq_handler(int irq, void *data)
1510 {
1511 struct xilinx_dpdma_device *xdev = data;
1512 unsigned long mask;
1513 unsigned int i;
1514 u32 status;
1515 u32 error;
1516
1517 status = dpdma_read(xdev->reg, XILINX_DPDMA_ISR);
1518 error = dpdma_read(xdev->reg, XILINX_DPDMA_EISR);
1519 if (!status && !error)
1520 return IRQ_NONE;
1521
1522 dpdma_write(xdev->reg, XILINX_DPDMA_ISR, status);
1523 dpdma_write(xdev->reg, XILINX_DPDMA_EISR, error);
1524
1525 if (status & XILINX_DPDMA_INTR_VSYNC) {
1526 /*
1527 * There's a single VSYNC interrupt that needs to be processed
1528 * by each running channel to update the active descriptor.
1529 */
1530 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) {
1531 struct xilinx_dpdma_chan *chan = xdev->chan[i];
1532
1533 if (chan)
1534 xilinx_dpdma_chan_vsync_irq(chan);
1535 }
1536 }
1537
1538 mask = FIELD_GET(XILINX_DPDMA_INTR_DESC_DONE_MASK, status);
1539 if (mask) {
1540 for_each_set_bit(i, &mask, ARRAY_SIZE(xdev->chan))
1541 xilinx_dpdma_chan_done_irq(xdev->chan[i]);
1542 }
1543
1544 mask = FIELD_GET(XILINX_DPDMA_INTR_NO_OSTAND_MASK, status);
1545 if (mask) {
1546 for_each_set_bit(i, &mask, ARRAY_SIZE(xdev->chan))
1547 xilinx_dpdma_chan_notify_no_ostand(xdev->chan[i]);
1548 }
1549
1550 mask = status & XILINX_DPDMA_INTR_ERR_ALL;
1551 if (mask || error)
1552 xilinx_dpdma_handle_err_irq(xdev, mask, error);
1553
1554 return IRQ_HANDLED;
1555 }
1556
1557 /* -----------------------------------------------------------------------------
1558 * Initialization & Cleanup
1559 */
1560
xilinx_dpdma_chan_init(struct xilinx_dpdma_device * xdev,unsigned int chan_id)1561 static int xilinx_dpdma_chan_init(struct xilinx_dpdma_device *xdev,
1562 unsigned int chan_id)
1563 {
1564 struct xilinx_dpdma_chan *chan;
1565
1566 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL);
1567 if (!chan)
1568 return -ENOMEM;
1569
1570 chan->id = chan_id;
1571 chan->reg = xdev->reg + XILINX_DPDMA_CH_BASE
1572 + XILINX_DPDMA_CH_OFFSET * chan->id;
1573 chan->running = false;
1574 chan->xdev = xdev;
1575
1576 spin_lock_init(&chan->lock);
1577 init_waitqueue_head(&chan->wait_to_stop);
1578
1579 tasklet_setup(&chan->err_task, xilinx_dpdma_chan_err_task);
1580
1581 chan->vchan.desc_free = xilinx_dpdma_chan_free_tx_desc;
1582 vchan_init(&chan->vchan, &xdev->common);
1583
1584 xdev->chan[chan->id] = chan;
1585
1586 return 0;
1587 }
1588
xilinx_dpdma_chan_remove(struct xilinx_dpdma_chan * chan)1589 static void xilinx_dpdma_chan_remove(struct xilinx_dpdma_chan *chan)
1590 {
1591 if (!chan)
1592 return;
1593
1594 tasklet_kill(&chan->err_task);
1595 list_del(&chan->vchan.chan.device_node);
1596 }
1597
of_dma_xilinx_xlate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)1598 static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
1599 struct of_dma *ofdma)
1600 {
1601 struct xilinx_dpdma_device *xdev = ofdma->of_dma_data;
1602 u32 chan_id = dma_spec->args[0];
1603
1604 if (chan_id >= ARRAY_SIZE(xdev->chan))
1605 return NULL;
1606
1607 if (!xdev->chan[chan_id])
1608 return NULL;
1609
1610 return dma_get_slave_channel(&xdev->chan[chan_id]->vchan.chan);
1611 }
1612
dpdma_hw_init(struct xilinx_dpdma_device * xdev)1613 static void dpdma_hw_init(struct xilinx_dpdma_device *xdev)
1614 {
1615 unsigned int i;
1616 void __iomem *reg;
1617
1618 /* Disable all interrupts */
1619 xilinx_dpdma_disable_irq(xdev);
1620
1621 /* Stop all channels */
1622 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) {
1623 reg = xdev->reg + XILINX_DPDMA_CH_BASE
1624 + XILINX_DPDMA_CH_OFFSET * i;
1625 dpdma_clr(reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE);
1626 }
1627
1628 /* Clear the interrupt status registers */
1629 dpdma_write(xdev->reg, XILINX_DPDMA_ISR, XILINX_DPDMA_INTR_ALL);
1630 dpdma_write(xdev->reg, XILINX_DPDMA_EISR, XILINX_DPDMA_EINTR_ALL);
1631 }
1632
xilinx_dpdma_probe(struct platform_device * pdev)1633 static int xilinx_dpdma_probe(struct platform_device *pdev)
1634 {
1635 struct xilinx_dpdma_device *xdev;
1636 struct dma_device *ddev;
1637 unsigned int i;
1638 int ret;
1639
1640 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL);
1641 if (!xdev)
1642 return -ENOMEM;
1643
1644 xdev->dev = &pdev->dev;
1645 xdev->ext_addr = sizeof(dma_addr_t) > 4;
1646
1647 INIT_LIST_HEAD(&xdev->common.channels);
1648
1649 platform_set_drvdata(pdev, xdev);
1650
1651 xdev->axi_clk = devm_clk_get(xdev->dev, "axi_clk");
1652 if (IS_ERR(xdev->axi_clk))
1653 return PTR_ERR(xdev->axi_clk);
1654
1655 xdev->reg = devm_platform_ioremap_resource(pdev, 0);
1656 if (IS_ERR(xdev->reg))
1657 return PTR_ERR(xdev->reg);
1658
1659 dpdma_hw_init(xdev);
1660
1661 xdev->irq = platform_get_irq(pdev, 0);
1662 if (xdev->irq < 0)
1663 return xdev->irq;
1664
1665 ret = request_irq(xdev->irq, xilinx_dpdma_irq_handler, IRQF_SHARED,
1666 dev_name(xdev->dev), xdev);
1667 if (ret) {
1668 dev_err(xdev->dev, "failed to request IRQ\n");
1669 return ret;
1670 }
1671
1672 ddev = &xdev->common;
1673 ddev->dev = &pdev->dev;
1674
1675 dma_cap_set(DMA_SLAVE, ddev->cap_mask);
1676 dma_cap_set(DMA_PRIVATE, ddev->cap_mask);
1677 dma_cap_set(DMA_INTERLEAVE, ddev->cap_mask);
1678 dma_cap_set(DMA_REPEAT, ddev->cap_mask);
1679 dma_cap_set(DMA_LOAD_EOT, ddev->cap_mask);
1680 ddev->copy_align = fls(XILINX_DPDMA_ALIGN_BYTES - 1);
1681
1682 ddev->device_alloc_chan_resources = xilinx_dpdma_alloc_chan_resources;
1683 ddev->device_free_chan_resources = xilinx_dpdma_free_chan_resources;
1684 ddev->device_prep_interleaved_dma = xilinx_dpdma_prep_interleaved_dma;
1685 /* TODO: Can we achieve better granularity ? */
1686 ddev->device_tx_status = dma_cookie_status;
1687 ddev->device_issue_pending = xilinx_dpdma_issue_pending;
1688 ddev->device_config = xilinx_dpdma_config;
1689 ddev->device_pause = xilinx_dpdma_pause;
1690 ddev->device_resume = xilinx_dpdma_resume;
1691 ddev->device_terminate_all = xilinx_dpdma_terminate_all;
1692 ddev->device_synchronize = xilinx_dpdma_synchronize;
1693 ddev->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED);
1694 ddev->directions = BIT(DMA_MEM_TO_DEV);
1695 ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1696
1697 for (i = 0; i < ARRAY_SIZE(xdev->chan); ++i) {
1698 ret = xilinx_dpdma_chan_init(xdev, i);
1699 if (ret < 0) {
1700 dev_err(xdev->dev, "failed to initialize channel %u\n",
1701 i);
1702 goto error;
1703 }
1704 }
1705
1706 ret = clk_prepare_enable(xdev->axi_clk);
1707 if (ret) {
1708 dev_err(xdev->dev, "failed to enable the axi clock\n");
1709 goto error;
1710 }
1711
1712 ret = dma_async_device_register(ddev);
1713 if (ret) {
1714 dev_err(xdev->dev, "failed to register the dma device\n");
1715 goto error_dma_async;
1716 }
1717
1718 ret = of_dma_controller_register(xdev->dev->of_node,
1719 of_dma_xilinx_xlate, ddev);
1720 if (ret) {
1721 dev_err(xdev->dev, "failed to register DMA to DT DMA helper\n");
1722 goto error_of_dma;
1723 }
1724
1725 xilinx_dpdma_enable_irq(xdev);
1726
1727 xilinx_dpdma_debugfs_init(xdev);
1728
1729 dev_info(&pdev->dev, "Xilinx DPDMA engine is probed\n");
1730
1731 return 0;
1732
1733 error_of_dma:
1734 dma_async_device_unregister(ddev);
1735 error_dma_async:
1736 clk_disable_unprepare(xdev->axi_clk);
1737 error:
1738 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++)
1739 xilinx_dpdma_chan_remove(xdev->chan[i]);
1740
1741 free_irq(xdev->irq, xdev);
1742
1743 return ret;
1744 }
1745
xilinx_dpdma_remove(struct platform_device * pdev)1746 static int xilinx_dpdma_remove(struct platform_device *pdev)
1747 {
1748 struct xilinx_dpdma_device *xdev = platform_get_drvdata(pdev);
1749 unsigned int i;
1750
1751 /* Start by disabling the IRQ to avoid races during cleanup. */
1752 free_irq(xdev->irq, xdev);
1753
1754 xilinx_dpdma_disable_irq(xdev);
1755 of_dma_controller_free(pdev->dev.of_node);
1756 dma_async_device_unregister(&xdev->common);
1757 clk_disable_unprepare(xdev->axi_clk);
1758
1759 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++)
1760 xilinx_dpdma_chan_remove(xdev->chan[i]);
1761
1762 return 0;
1763 }
1764
1765 static const struct of_device_id xilinx_dpdma_of_match[] = {
1766 { .compatible = "xlnx,zynqmp-dpdma",},
1767 { /* end of table */ },
1768 };
1769 MODULE_DEVICE_TABLE(of, xilinx_dpdma_of_match);
1770
1771 static struct platform_driver xilinx_dpdma_driver = {
1772 .probe = xilinx_dpdma_probe,
1773 .remove = xilinx_dpdma_remove,
1774 .driver = {
1775 .name = "xilinx-zynqmp-dpdma",
1776 .of_match_table = xilinx_dpdma_of_match,
1777 },
1778 };
1779
1780 module_platform_driver(xilinx_dpdma_driver);
1781
1782 MODULE_AUTHOR("Xilinx, Inc.");
1783 MODULE_DESCRIPTION("Xilinx ZynqMP DPDMA driver");
1784 MODULE_LICENSE("GPL v2");
1785