1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 5 */ 6 7 #include <linux/kernel.h> 8 9 #include "k3-psil-priv.h" 10 11 #define PSIL_PDMA_XY_TR(x) \ 12 { \ 13 .thread_id = x, \ 14 .ep_config = { \ 15 .ep_type = PSIL_EP_PDMA_XY, \ 16 .mapped_channel_id = -1, \ 17 .default_flow_id = -1, \ 18 }, \ 19 } 20 21 #define PSIL_PDMA_XY_PKT(x) \ 22 { \ 23 .thread_id = x, \ 24 .ep_config = { \ 25 .ep_type = PSIL_EP_PDMA_XY, \ 26 .mapped_channel_id = -1, \ 27 .default_flow_id = -1, \ 28 .pkt_mode = 1, \ 29 }, \ 30 } 31 32 #define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \ 33 { \ 34 .thread_id = x, \ 35 .ep_config = { \ 36 .ep_type = PSIL_EP_NATIVE, \ 37 .pkt_mode = 1, \ 38 .needs_epib = 1, \ 39 .psd_size = 16, \ 40 .mapped_channel_id = ch, \ 41 .flow_start = flow_base, \ 42 .flow_num = flow_cnt, \ 43 .default_flow_id = flow_base, \ 44 }, \ 45 } 46 47 #define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \ 48 { \ 49 .thread_id = x, \ 50 .ep_config = { \ 51 .ep_type = PSIL_EP_NATIVE, \ 52 .pkt_mode = 1, \ 53 .needs_epib = 1, \ 54 .psd_size = 64, \ 55 .mapped_channel_id = ch, \ 56 .flow_start = flow_base, \ 57 .flow_num = flow_cnt, \ 58 .default_flow_id = default_flow, \ 59 .notdpkt = tx, \ 60 }, \ 61 } 62 63 /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ 64 static struct psil_ep am64_src_ep_map[] = { 65 /* SAUL */ 66 PSIL_SAUL(0x4000, 17, 32, 8, 32, 0), 67 PSIL_SAUL(0x4001, 18, 32, 8, 33, 0), 68 PSIL_SAUL(0x4002, 19, 40, 8, 40, 0), 69 PSIL_SAUL(0x4003, 20, 40, 8, 41, 0), 70 /* ICSS_G0 */ 71 PSIL_ETHERNET(0x4100, 21, 48, 16), 72 PSIL_ETHERNET(0x4101, 22, 64, 16), 73 PSIL_ETHERNET(0x4102, 23, 80, 16), 74 PSIL_ETHERNET(0x4103, 24, 96, 16), 75 /* ICSS_G1 */ 76 PSIL_ETHERNET(0x4200, 25, 112, 16), 77 PSIL_ETHERNET(0x4201, 26, 128, 16), 78 PSIL_ETHERNET(0x4202, 27, 144, 16), 79 PSIL_ETHERNET(0x4203, 28, 160, 16), 80 /* PDMA_MAIN0 - SPI0-3 */ 81 PSIL_PDMA_XY_PKT(0x4300), 82 PSIL_PDMA_XY_PKT(0x4301), 83 PSIL_PDMA_XY_PKT(0x4302), 84 PSIL_PDMA_XY_PKT(0x4303), 85 PSIL_PDMA_XY_PKT(0x4304), 86 PSIL_PDMA_XY_PKT(0x4305), 87 PSIL_PDMA_XY_PKT(0x4306), 88 PSIL_PDMA_XY_PKT(0x4307), 89 PSIL_PDMA_XY_PKT(0x4308), 90 PSIL_PDMA_XY_PKT(0x4309), 91 PSIL_PDMA_XY_PKT(0x430a), 92 PSIL_PDMA_XY_PKT(0x430b), 93 PSIL_PDMA_XY_PKT(0x430c), 94 PSIL_PDMA_XY_PKT(0x430d), 95 PSIL_PDMA_XY_PKT(0x430e), 96 PSIL_PDMA_XY_PKT(0x430f), 97 /* PDMA_MAIN0 - USART0-1 */ 98 PSIL_PDMA_XY_PKT(0x4310), 99 PSIL_PDMA_XY_PKT(0x4311), 100 /* PDMA_MAIN1 - SPI4 */ 101 PSIL_PDMA_XY_PKT(0x4400), 102 PSIL_PDMA_XY_PKT(0x4401), 103 PSIL_PDMA_XY_PKT(0x4402), 104 PSIL_PDMA_XY_PKT(0x4403), 105 /* PDMA_MAIN1 - USART2-6 */ 106 PSIL_PDMA_XY_PKT(0x4404), 107 PSIL_PDMA_XY_PKT(0x4405), 108 PSIL_PDMA_XY_PKT(0x4406), 109 PSIL_PDMA_XY_PKT(0x4407), 110 PSIL_PDMA_XY_PKT(0x4408), 111 /* PDMA_MAIN1 - ADCs */ 112 PSIL_PDMA_XY_TR(0x440f), 113 PSIL_PDMA_XY_TR(0x4410), 114 /* CPSW2 */ 115 PSIL_ETHERNET(0x4500, 16, 16, 16), 116 }; 117 118 /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ 119 static struct psil_ep am64_dst_ep_map[] = { 120 /* SAUL */ 121 PSIL_SAUL(0xc000, 24, 80, 8, 80, 1), 122 PSIL_SAUL(0xc001, 25, 88, 8, 88, 1), 123 /* ICSS_G0 */ 124 PSIL_ETHERNET(0xc100, 26, 96, 1), 125 PSIL_ETHERNET(0xc101, 27, 97, 1), 126 PSIL_ETHERNET(0xc102, 28, 98, 1), 127 PSIL_ETHERNET(0xc103, 29, 99, 1), 128 PSIL_ETHERNET(0xc104, 30, 100, 1), 129 PSIL_ETHERNET(0xc105, 31, 101, 1), 130 PSIL_ETHERNET(0xc106, 32, 102, 1), 131 PSIL_ETHERNET(0xc107, 33, 103, 1), 132 /* ICSS_G1 */ 133 PSIL_ETHERNET(0xc200, 34, 104, 1), 134 PSIL_ETHERNET(0xc201, 35, 105, 1), 135 PSIL_ETHERNET(0xc202, 36, 106, 1), 136 PSIL_ETHERNET(0xc203, 37, 107, 1), 137 PSIL_ETHERNET(0xc204, 38, 108, 1), 138 PSIL_ETHERNET(0xc205, 39, 109, 1), 139 PSIL_ETHERNET(0xc206, 40, 110, 1), 140 PSIL_ETHERNET(0xc207, 41, 111, 1), 141 /* CPSW2 */ 142 PSIL_ETHERNET(0xc500, 16, 16, 8), 143 PSIL_ETHERNET(0xc501, 17, 24, 8), 144 PSIL_ETHERNET(0xc502, 18, 32, 8), 145 PSIL_ETHERNET(0xc503, 19, 40, 8), 146 PSIL_ETHERNET(0xc504, 20, 48, 8), 147 PSIL_ETHERNET(0xc505, 21, 56, 8), 148 PSIL_ETHERNET(0xc506, 22, 64, 8), 149 PSIL_ETHERNET(0xc507, 23, 72, 8), 150 }; 151 152 struct psil_ep_map am64_ep_map = { 153 .name = "am64", 154 .src = am64_src_ep_map, 155 .src_count = ARRAY_SIZE(am64_src_ep_map), 156 .dst = am64_dst_ep_map, 157 .dst_count = ARRAY_SIZE(am64_dst_ep_map), 158 }; 159