1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * ADMA driver for Nvidia's Tegra210 ADMA controller. 4 * 5 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/iopoll.h> 10 #include <linux/module.h> 11 #include <linux/of_device.h> 12 #include <linux/of_dma.h> 13 #include <linux/of_irq.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/slab.h> 16 17 #include "virt-dma.h" 18 19 #define ADMA_CH_CMD 0x00 20 #define ADMA_CH_STATUS 0x0c 21 #define ADMA_CH_STATUS_XFER_EN BIT(0) 22 #define ADMA_CH_STATUS_XFER_PAUSED BIT(1) 23 24 #define ADMA_CH_INT_STATUS 0x10 25 #define ADMA_CH_INT_STATUS_XFER_DONE BIT(0) 26 27 #define ADMA_CH_INT_CLEAR 0x1c 28 #define ADMA_CH_CTRL 0x24 29 #define ADMA_CH_CTRL_DIR(val) (((val) & 0xf) << 12) 30 #define ADMA_CH_CTRL_DIR_AHUB2MEM 2 31 #define ADMA_CH_CTRL_DIR_MEM2AHUB 4 32 #define ADMA_CH_CTRL_MODE_CONTINUOUS (2 << 8) 33 #define ADMA_CH_CTRL_FLOWCTRL_EN BIT(1) 34 #define ADMA_CH_CTRL_XFER_PAUSE_SHIFT 0 35 36 #define ADMA_CH_CONFIG 0x28 37 #define ADMA_CH_CONFIG_SRC_BUF(val) (((val) & 0x7) << 28) 38 #define ADMA_CH_CONFIG_TRG_BUF(val) (((val) & 0x7) << 24) 39 #define ADMA_CH_CONFIG_BURST_SIZE_SHIFT 20 40 #define ADMA_CH_CONFIG_MAX_BURST_SIZE 16 41 #define ADMA_CH_CONFIG_WEIGHT_FOR_WRR(val) ((val) & 0xf) 42 #define ADMA_CH_CONFIG_MAX_BUFS 8 43 44 #define ADMA_CH_FIFO_CTRL 0x2c 45 #define TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(val) (((val) & 0xf) << 8) 46 #define TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(val) ((val) & 0xf) 47 #define TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(val) (((val) & 0x1f) << 8) 48 #define TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(val) ((val) & 0x1f) 49 50 #define ADMA_CH_LOWER_SRC_ADDR 0x34 51 #define ADMA_CH_LOWER_TRG_ADDR 0x3c 52 #define ADMA_CH_TC 0x44 53 #define ADMA_CH_TC_COUNT_MASK 0x3ffffffc 54 55 #define ADMA_CH_XFER_STATUS 0x54 56 #define ADMA_CH_XFER_STATUS_COUNT_MASK 0xffff 57 58 #define ADMA_GLOBAL_CMD 0x00 59 #define ADMA_GLOBAL_SOFT_RESET 0x04 60 61 #define TEGRA_ADMA_BURST_COMPLETE_TIME 20 62 63 #define TEGRA210_FIFO_CTRL_DEFAULT (TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \ 64 TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE(3)) 65 66 #define TEGRA186_FIFO_CTRL_DEFAULT (TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE(3) | \ 67 TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE(3)) 68 69 #define ADMA_CH_REG_FIELD_VAL(val, mask, shift) (((val) & mask) << shift) 70 71 struct tegra_adma; 72 73 /* 74 * struct tegra_adma_chip_data - Tegra chip specific data 75 * @global_reg_offset: Register offset of DMA global register. 76 * @global_int_clear: Register offset of DMA global interrupt clear. 77 * @ch_req_tx_shift: Register offset for AHUB transmit channel select. 78 * @ch_req_rx_shift: Register offset for AHUB receive channel select. 79 * @ch_base_offset: Register offset of DMA channel registers. 80 * @ch_fifo_ctrl: Default value for channel FIFO CTRL register. 81 * @ch_req_mask: Mask for Tx or Rx channel select. 82 * @ch_req_max: Maximum number of Tx or Rx channels available. 83 * @ch_reg_size: Size of DMA channel register space. 84 * @nr_channels: Number of DMA channels available. 85 */ 86 struct tegra_adma_chip_data { 87 unsigned int (*adma_get_burst_config)(unsigned int burst_size); 88 unsigned int global_reg_offset; 89 unsigned int global_int_clear; 90 unsigned int ch_req_tx_shift; 91 unsigned int ch_req_rx_shift; 92 unsigned int ch_base_offset; 93 unsigned int ch_fifo_ctrl; 94 unsigned int ch_req_mask; 95 unsigned int ch_req_max; 96 unsigned int ch_reg_size; 97 unsigned int nr_channels; 98 }; 99 100 /* 101 * struct tegra_adma_chan_regs - Tegra ADMA channel registers 102 */ 103 struct tegra_adma_chan_regs { 104 unsigned int ctrl; 105 unsigned int config; 106 unsigned int src_addr; 107 unsigned int trg_addr; 108 unsigned int fifo_ctrl; 109 unsigned int cmd; 110 unsigned int tc; 111 }; 112 113 /* 114 * struct tegra_adma_desc - Tegra ADMA descriptor to manage transfer requests. 115 */ 116 struct tegra_adma_desc { 117 struct virt_dma_desc vd; 118 struct tegra_adma_chan_regs ch_regs; 119 size_t buf_len; 120 size_t period_len; 121 size_t num_periods; 122 }; 123 124 /* 125 * struct tegra_adma_chan - Tegra ADMA channel information 126 */ 127 struct tegra_adma_chan { 128 struct virt_dma_chan vc; 129 struct tegra_adma_desc *desc; 130 struct tegra_adma *tdma; 131 int irq; 132 void __iomem *chan_addr; 133 134 /* Slave channel configuration info */ 135 struct dma_slave_config sconfig; 136 enum dma_transfer_direction sreq_dir; 137 unsigned int sreq_index; 138 bool sreq_reserved; 139 struct tegra_adma_chan_regs ch_regs; 140 141 /* Transfer count and position info */ 142 unsigned int tx_buf_count; 143 unsigned int tx_buf_pos; 144 }; 145 146 /* 147 * struct tegra_adma - Tegra ADMA controller information 148 */ 149 struct tegra_adma { 150 struct dma_device dma_dev; 151 struct device *dev; 152 void __iomem *base_addr; 153 struct clk *ahub_clk; 154 unsigned int nr_channels; 155 unsigned long rx_requests_reserved; 156 unsigned long tx_requests_reserved; 157 158 /* Used to store global command register state when suspending */ 159 unsigned int global_cmd; 160 161 const struct tegra_adma_chip_data *cdata; 162 163 /* Last member of the structure */ 164 struct tegra_adma_chan channels[0]; 165 }; 166 167 static inline void tdma_write(struct tegra_adma *tdma, u32 reg, u32 val) 168 { 169 writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg); 170 } 171 172 static inline u32 tdma_read(struct tegra_adma *tdma, u32 reg) 173 { 174 return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg); 175 } 176 177 static inline void tdma_ch_write(struct tegra_adma_chan *tdc, u32 reg, u32 val) 178 { 179 writel(val, tdc->chan_addr + reg); 180 } 181 182 static inline u32 tdma_ch_read(struct tegra_adma_chan *tdc, u32 reg) 183 { 184 return readl(tdc->chan_addr + reg); 185 } 186 187 static inline struct tegra_adma_chan *to_tegra_adma_chan(struct dma_chan *dc) 188 { 189 return container_of(dc, struct tegra_adma_chan, vc.chan); 190 } 191 192 static inline struct tegra_adma_desc *to_tegra_adma_desc( 193 struct dma_async_tx_descriptor *td) 194 { 195 return container_of(td, struct tegra_adma_desc, vd.tx); 196 } 197 198 static inline struct device *tdc2dev(struct tegra_adma_chan *tdc) 199 { 200 return tdc->tdma->dev; 201 } 202 203 static void tegra_adma_desc_free(struct virt_dma_desc *vd) 204 { 205 kfree(container_of(vd, struct tegra_adma_desc, vd)); 206 } 207 208 static int tegra_adma_slave_config(struct dma_chan *dc, 209 struct dma_slave_config *sconfig) 210 { 211 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); 212 213 memcpy(&tdc->sconfig, sconfig, sizeof(*sconfig)); 214 215 return 0; 216 } 217 218 static int tegra_adma_init(struct tegra_adma *tdma) 219 { 220 u32 status; 221 int ret; 222 223 /* Clear any interrupts */ 224 tdma_write(tdma, tdma->cdata->global_int_clear, 0x1); 225 226 /* Assert soft reset */ 227 tdma_write(tdma, ADMA_GLOBAL_SOFT_RESET, 0x1); 228 229 /* Wait for reset to clear */ 230 ret = readx_poll_timeout(readl, 231 tdma->base_addr + 232 tdma->cdata->global_reg_offset + 233 ADMA_GLOBAL_SOFT_RESET, 234 status, status == 0, 20, 10000); 235 if (ret) 236 return ret; 237 238 /* Enable global ADMA registers */ 239 tdma_write(tdma, ADMA_GLOBAL_CMD, 1); 240 241 return 0; 242 } 243 244 static int tegra_adma_request_alloc(struct tegra_adma_chan *tdc, 245 enum dma_transfer_direction direction) 246 { 247 struct tegra_adma *tdma = tdc->tdma; 248 unsigned int sreq_index = tdc->sreq_index; 249 250 if (tdc->sreq_reserved) 251 return tdc->sreq_dir == direction ? 0 : -EINVAL; 252 253 if (sreq_index > tdma->cdata->ch_req_max) { 254 dev_err(tdma->dev, "invalid DMA request\n"); 255 return -EINVAL; 256 } 257 258 switch (direction) { 259 case DMA_MEM_TO_DEV: 260 if (test_and_set_bit(sreq_index, &tdma->tx_requests_reserved)) { 261 dev_err(tdma->dev, "DMA request reserved\n"); 262 return -EINVAL; 263 } 264 break; 265 266 case DMA_DEV_TO_MEM: 267 if (test_and_set_bit(sreq_index, &tdma->rx_requests_reserved)) { 268 dev_err(tdma->dev, "DMA request reserved\n"); 269 return -EINVAL; 270 } 271 break; 272 273 default: 274 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n", 275 dma_chan_name(&tdc->vc.chan)); 276 return -EINVAL; 277 } 278 279 tdc->sreq_dir = direction; 280 tdc->sreq_reserved = true; 281 282 return 0; 283 } 284 285 static void tegra_adma_request_free(struct tegra_adma_chan *tdc) 286 { 287 struct tegra_adma *tdma = tdc->tdma; 288 289 if (!tdc->sreq_reserved) 290 return; 291 292 switch (tdc->sreq_dir) { 293 case DMA_MEM_TO_DEV: 294 clear_bit(tdc->sreq_index, &tdma->tx_requests_reserved); 295 break; 296 297 case DMA_DEV_TO_MEM: 298 clear_bit(tdc->sreq_index, &tdma->rx_requests_reserved); 299 break; 300 301 default: 302 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n", 303 dma_chan_name(&tdc->vc.chan)); 304 return; 305 } 306 307 tdc->sreq_reserved = false; 308 } 309 310 static u32 tegra_adma_irq_status(struct tegra_adma_chan *tdc) 311 { 312 u32 status = tdma_ch_read(tdc, ADMA_CH_INT_STATUS); 313 314 return status & ADMA_CH_INT_STATUS_XFER_DONE; 315 } 316 317 static u32 tegra_adma_irq_clear(struct tegra_adma_chan *tdc) 318 { 319 u32 status = tegra_adma_irq_status(tdc); 320 321 if (status) 322 tdma_ch_write(tdc, ADMA_CH_INT_CLEAR, status); 323 324 return status; 325 } 326 327 static void tegra_adma_stop(struct tegra_adma_chan *tdc) 328 { 329 unsigned int status; 330 331 /* Disable ADMA */ 332 tdma_ch_write(tdc, ADMA_CH_CMD, 0); 333 334 /* Clear interrupt status */ 335 tegra_adma_irq_clear(tdc); 336 337 if (readx_poll_timeout_atomic(readl, tdc->chan_addr + ADMA_CH_STATUS, 338 status, !(status & ADMA_CH_STATUS_XFER_EN), 339 20, 10000)) { 340 dev_err(tdc2dev(tdc), "unable to stop DMA channel\n"); 341 return; 342 } 343 344 kfree(tdc->desc); 345 tdc->desc = NULL; 346 } 347 348 static void tegra_adma_start(struct tegra_adma_chan *tdc) 349 { 350 struct virt_dma_desc *vd = vchan_next_desc(&tdc->vc); 351 struct tegra_adma_chan_regs *ch_regs; 352 struct tegra_adma_desc *desc; 353 354 if (!vd) 355 return; 356 357 list_del(&vd->node); 358 359 desc = to_tegra_adma_desc(&vd->tx); 360 361 if (!desc) { 362 dev_warn(tdc2dev(tdc), "unable to start DMA, no descriptor\n"); 363 return; 364 } 365 366 ch_regs = &desc->ch_regs; 367 368 tdc->tx_buf_pos = 0; 369 tdc->tx_buf_count = 0; 370 tdma_ch_write(tdc, ADMA_CH_TC, ch_regs->tc); 371 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); 372 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_regs->src_addr); 373 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_regs->trg_addr); 374 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl); 375 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config); 376 377 /* Start ADMA */ 378 tdma_ch_write(tdc, ADMA_CH_CMD, 1); 379 380 tdc->desc = desc; 381 } 382 383 static unsigned int tegra_adma_get_residue(struct tegra_adma_chan *tdc) 384 { 385 struct tegra_adma_desc *desc = tdc->desc; 386 unsigned int max = ADMA_CH_XFER_STATUS_COUNT_MASK + 1; 387 unsigned int pos = tdma_ch_read(tdc, ADMA_CH_XFER_STATUS); 388 unsigned int periods_remaining; 389 390 /* 391 * Handle wrap around of buffer count register 392 */ 393 if (pos < tdc->tx_buf_pos) 394 tdc->tx_buf_count += pos + (max - tdc->tx_buf_pos); 395 else 396 tdc->tx_buf_count += pos - tdc->tx_buf_pos; 397 398 periods_remaining = tdc->tx_buf_count % desc->num_periods; 399 tdc->tx_buf_pos = pos; 400 401 return desc->buf_len - (periods_remaining * desc->period_len); 402 } 403 404 static irqreturn_t tegra_adma_isr(int irq, void *dev_id) 405 { 406 struct tegra_adma_chan *tdc = dev_id; 407 unsigned long status; 408 unsigned long flags; 409 410 spin_lock_irqsave(&tdc->vc.lock, flags); 411 412 status = tegra_adma_irq_clear(tdc); 413 if (status == 0 || !tdc->desc) { 414 spin_unlock_irqrestore(&tdc->vc.lock, flags); 415 return IRQ_NONE; 416 } 417 418 vchan_cyclic_callback(&tdc->desc->vd); 419 420 spin_unlock_irqrestore(&tdc->vc.lock, flags); 421 422 return IRQ_HANDLED; 423 } 424 425 static void tegra_adma_issue_pending(struct dma_chan *dc) 426 { 427 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); 428 unsigned long flags; 429 430 spin_lock_irqsave(&tdc->vc.lock, flags); 431 432 if (vchan_issue_pending(&tdc->vc)) { 433 if (!tdc->desc) 434 tegra_adma_start(tdc); 435 } 436 437 spin_unlock_irqrestore(&tdc->vc.lock, flags); 438 } 439 440 static bool tegra_adma_is_paused(struct tegra_adma_chan *tdc) 441 { 442 u32 csts; 443 444 csts = tdma_ch_read(tdc, ADMA_CH_STATUS); 445 csts &= ADMA_CH_STATUS_XFER_PAUSED; 446 447 return csts ? true : false; 448 } 449 450 static int tegra_adma_pause(struct dma_chan *dc) 451 { 452 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); 453 struct tegra_adma_desc *desc = tdc->desc; 454 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; 455 int dcnt = 10; 456 457 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); 458 ch_regs->ctrl |= (1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT); 459 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); 460 461 while (dcnt-- && !tegra_adma_is_paused(tdc)) 462 udelay(TEGRA_ADMA_BURST_COMPLETE_TIME); 463 464 if (dcnt < 0) { 465 dev_err(tdc2dev(tdc), "unable to pause DMA channel\n"); 466 return -EBUSY; 467 } 468 469 return 0; 470 } 471 472 static int tegra_adma_resume(struct dma_chan *dc) 473 { 474 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); 475 struct tegra_adma_desc *desc = tdc->desc; 476 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; 477 478 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); 479 ch_regs->ctrl &= ~(1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT); 480 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); 481 482 return 0; 483 } 484 485 static int tegra_adma_terminate_all(struct dma_chan *dc) 486 { 487 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); 488 unsigned long flags; 489 LIST_HEAD(head); 490 491 spin_lock_irqsave(&tdc->vc.lock, flags); 492 493 if (tdc->desc) 494 tegra_adma_stop(tdc); 495 496 tegra_adma_request_free(tdc); 497 vchan_get_all_descriptors(&tdc->vc, &head); 498 spin_unlock_irqrestore(&tdc->vc.lock, flags); 499 vchan_dma_desc_free_list(&tdc->vc, &head); 500 501 return 0; 502 } 503 504 static enum dma_status tegra_adma_tx_status(struct dma_chan *dc, 505 dma_cookie_t cookie, 506 struct dma_tx_state *txstate) 507 { 508 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); 509 struct tegra_adma_desc *desc; 510 struct virt_dma_desc *vd; 511 enum dma_status ret; 512 unsigned long flags; 513 unsigned int residual; 514 515 ret = dma_cookie_status(dc, cookie, txstate); 516 if (ret == DMA_COMPLETE || !txstate) 517 return ret; 518 519 spin_lock_irqsave(&tdc->vc.lock, flags); 520 521 vd = vchan_find_desc(&tdc->vc, cookie); 522 if (vd) { 523 desc = to_tegra_adma_desc(&vd->tx); 524 residual = desc->ch_regs.tc; 525 } else if (tdc->desc && tdc->desc->vd.tx.cookie == cookie) { 526 residual = tegra_adma_get_residue(tdc); 527 } else { 528 residual = 0; 529 } 530 531 spin_unlock_irqrestore(&tdc->vc.lock, flags); 532 533 dma_set_residue(txstate, residual); 534 535 return ret; 536 } 537 538 static unsigned int tegra210_adma_get_burst_config(unsigned int burst_size) 539 { 540 if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE) 541 burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE; 542 543 return fls(burst_size) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT; 544 } 545 546 static unsigned int tegra186_adma_get_burst_config(unsigned int burst_size) 547 { 548 if (!burst_size || burst_size > ADMA_CH_CONFIG_MAX_BURST_SIZE) 549 burst_size = ADMA_CH_CONFIG_MAX_BURST_SIZE; 550 551 return (burst_size - 1) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT; 552 } 553 554 static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc, 555 struct tegra_adma_desc *desc, 556 dma_addr_t buf_addr, 557 enum dma_transfer_direction direction) 558 { 559 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; 560 const struct tegra_adma_chip_data *cdata = tdc->tdma->cdata; 561 unsigned int burst_size, adma_dir; 562 563 if (desc->num_periods > ADMA_CH_CONFIG_MAX_BUFS) 564 return -EINVAL; 565 566 switch (direction) { 567 case DMA_MEM_TO_DEV: 568 adma_dir = ADMA_CH_CTRL_DIR_MEM2AHUB; 569 burst_size = tdc->sconfig.dst_maxburst; 570 ch_regs->config = ADMA_CH_CONFIG_SRC_BUF(desc->num_periods - 1); 571 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index, 572 cdata->ch_req_mask, 573 cdata->ch_req_tx_shift); 574 ch_regs->src_addr = buf_addr; 575 break; 576 577 case DMA_DEV_TO_MEM: 578 adma_dir = ADMA_CH_CTRL_DIR_AHUB2MEM; 579 burst_size = tdc->sconfig.src_maxburst; 580 ch_regs->config = ADMA_CH_CONFIG_TRG_BUF(desc->num_periods - 1); 581 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index, 582 cdata->ch_req_mask, 583 cdata->ch_req_rx_shift); 584 ch_regs->trg_addr = buf_addr; 585 break; 586 587 default: 588 dev_err(tdc2dev(tdc), "DMA direction is not supported\n"); 589 return -EINVAL; 590 } 591 592 ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir) | 593 ADMA_CH_CTRL_MODE_CONTINUOUS | 594 ADMA_CH_CTRL_FLOWCTRL_EN; 595 ch_regs->config |= cdata->adma_get_burst_config(burst_size); 596 ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1); 597 ch_regs->fifo_ctrl = cdata->ch_fifo_ctrl; 598 ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK; 599 600 return tegra_adma_request_alloc(tdc, direction); 601 } 602 603 static struct dma_async_tx_descriptor *tegra_adma_prep_dma_cyclic( 604 struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len, 605 size_t period_len, enum dma_transfer_direction direction, 606 unsigned long flags) 607 { 608 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); 609 struct tegra_adma_desc *desc = NULL; 610 611 if (!buf_len || !period_len || period_len > ADMA_CH_TC_COUNT_MASK) { 612 dev_err(tdc2dev(tdc), "invalid buffer/period len\n"); 613 return NULL; 614 } 615 616 if (buf_len % period_len) { 617 dev_err(tdc2dev(tdc), "buf_len not a multiple of period_len\n"); 618 return NULL; 619 } 620 621 if (!IS_ALIGNED(buf_addr, 4)) { 622 dev_err(tdc2dev(tdc), "invalid buffer alignment\n"); 623 return NULL; 624 } 625 626 desc = kzalloc(sizeof(*desc), GFP_NOWAIT); 627 if (!desc) 628 return NULL; 629 630 desc->buf_len = buf_len; 631 desc->period_len = period_len; 632 desc->num_periods = buf_len / period_len; 633 634 if (tegra_adma_set_xfer_params(tdc, desc, buf_addr, direction)) { 635 kfree(desc); 636 return NULL; 637 } 638 639 return vchan_tx_prep(&tdc->vc, &desc->vd, flags); 640 } 641 642 static int tegra_adma_alloc_chan_resources(struct dma_chan *dc) 643 { 644 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); 645 int ret; 646 647 ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc); 648 if (ret) { 649 dev_err(tdc2dev(tdc), "failed to get interrupt for %s\n", 650 dma_chan_name(dc)); 651 return ret; 652 } 653 654 ret = pm_runtime_get_sync(tdc2dev(tdc)); 655 if (ret < 0) { 656 free_irq(tdc->irq, tdc); 657 return ret; 658 } 659 660 dma_cookie_init(&tdc->vc.chan); 661 662 return 0; 663 } 664 665 static void tegra_adma_free_chan_resources(struct dma_chan *dc) 666 { 667 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); 668 669 tegra_adma_terminate_all(dc); 670 vchan_free_chan_resources(&tdc->vc); 671 tasklet_kill(&tdc->vc.task); 672 free_irq(tdc->irq, tdc); 673 pm_runtime_put(tdc2dev(tdc)); 674 675 tdc->sreq_index = 0; 676 tdc->sreq_dir = DMA_TRANS_NONE; 677 } 678 679 static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec, 680 struct of_dma *ofdma) 681 { 682 struct tegra_adma *tdma = ofdma->of_dma_data; 683 struct tegra_adma_chan *tdc; 684 struct dma_chan *chan; 685 unsigned int sreq_index; 686 687 if (dma_spec->args_count != 1) 688 return NULL; 689 690 sreq_index = dma_spec->args[0]; 691 692 if (sreq_index == 0) { 693 dev_err(tdma->dev, "DMA request must not be 0\n"); 694 return NULL; 695 } 696 697 chan = dma_get_any_slave_channel(&tdma->dma_dev); 698 if (!chan) 699 return NULL; 700 701 tdc = to_tegra_adma_chan(chan); 702 tdc->sreq_index = sreq_index; 703 704 return chan; 705 } 706 707 static int __maybe_unused tegra_adma_runtime_suspend(struct device *dev) 708 { 709 struct tegra_adma *tdma = dev_get_drvdata(dev); 710 struct tegra_adma_chan_regs *ch_reg; 711 struct tegra_adma_chan *tdc; 712 int i; 713 714 tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD); 715 if (!tdma->global_cmd) 716 goto clk_disable; 717 718 for (i = 0; i < tdma->nr_channels; i++) { 719 tdc = &tdma->channels[i]; 720 ch_reg = &tdc->ch_regs; 721 ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD); 722 /* skip if channel is not active */ 723 if (!ch_reg->cmd) 724 continue; 725 ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC); 726 ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR); 727 ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR); 728 ch_reg->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); 729 ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL); 730 ch_reg->config = tdma_ch_read(tdc, ADMA_CH_CONFIG); 731 } 732 733 clk_disable: 734 clk_disable_unprepare(tdma->ahub_clk); 735 736 return 0; 737 } 738 739 static int __maybe_unused tegra_adma_runtime_resume(struct device *dev) 740 { 741 struct tegra_adma *tdma = dev_get_drvdata(dev); 742 struct tegra_adma_chan_regs *ch_reg; 743 struct tegra_adma_chan *tdc; 744 int ret, i; 745 746 ret = clk_prepare_enable(tdma->ahub_clk); 747 if (ret) { 748 dev_err(dev, "ahub clk_enable failed: %d\n", ret); 749 return ret; 750 } 751 tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); 752 753 if (!tdma->global_cmd) 754 return 0; 755 756 for (i = 0; i < tdma->nr_channels; i++) { 757 tdc = &tdma->channels[i]; 758 ch_reg = &tdc->ch_regs; 759 /* skip if channel was not active earlier */ 760 if (!ch_reg->cmd) 761 continue; 762 tdma_ch_write(tdc, ADMA_CH_TC, ch_reg->tc); 763 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_reg->src_addr); 764 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_reg->trg_addr); 765 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl); 766 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl); 767 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config); 768 tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd); 769 } 770 771 return 0; 772 } 773 774 static const struct tegra_adma_chip_data tegra210_chip_data = { 775 .adma_get_burst_config = tegra210_adma_get_burst_config, 776 .global_reg_offset = 0xc00, 777 .global_int_clear = 0x20, 778 .ch_req_tx_shift = 28, 779 .ch_req_rx_shift = 24, 780 .ch_base_offset = 0, 781 .ch_fifo_ctrl = TEGRA210_FIFO_CTRL_DEFAULT, 782 .ch_req_mask = 0xf, 783 .ch_req_max = 10, 784 .ch_reg_size = 0x80, 785 .nr_channels = 22, 786 }; 787 788 static const struct tegra_adma_chip_data tegra186_chip_data = { 789 .adma_get_burst_config = tegra186_adma_get_burst_config, 790 .global_reg_offset = 0, 791 .global_int_clear = 0x402c, 792 .ch_req_tx_shift = 27, 793 .ch_req_rx_shift = 22, 794 .ch_base_offset = 0x10000, 795 .ch_fifo_ctrl = TEGRA186_FIFO_CTRL_DEFAULT, 796 .ch_req_mask = 0x1f, 797 .ch_req_max = 20, 798 .ch_reg_size = 0x100, 799 .nr_channels = 32, 800 }; 801 802 static const struct of_device_id tegra_adma_of_match[] = { 803 { .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data }, 804 { .compatible = "nvidia,tegra186-adma", .data = &tegra186_chip_data }, 805 { }, 806 }; 807 MODULE_DEVICE_TABLE(of, tegra_adma_of_match); 808 809 static int tegra_adma_probe(struct platform_device *pdev) 810 { 811 const struct tegra_adma_chip_data *cdata; 812 struct tegra_adma *tdma; 813 struct resource *res; 814 int ret, i; 815 816 cdata = of_device_get_match_data(&pdev->dev); 817 if (!cdata) { 818 dev_err(&pdev->dev, "device match data not found\n"); 819 return -ENODEV; 820 } 821 822 tdma = devm_kzalloc(&pdev->dev, 823 struct_size(tdma, channels, cdata->nr_channels), 824 GFP_KERNEL); 825 if (!tdma) 826 return -ENOMEM; 827 828 tdma->dev = &pdev->dev; 829 tdma->cdata = cdata; 830 tdma->nr_channels = cdata->nr_channels; 831 platform_set_drvdata(pdev, tdma); 832 833 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 834 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res); 835 if (IS_ERR(tdma->base_addr)) 836 return PTR_ERR(tdma->base_addr); 837 838 tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio"); 839 if (IS_ERR(tdma->ahub_clk)) { 840 dev_err(&pdev->dev, "Error: Missing ahub controller clock\n"); 841 return PTR_ERR(tdma->ahub_clk); 842 } 843 844 INIT_LIST_HEAD(&tdma->dma_dev.channels); 845 for (i = 0; i < tdma->nr_channels; i++) { 846 struct tegra_adma_chan *tdc = &tdma->channels[i]; 847 848 tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset 849 + (cdata->ch_reg_size * i); 850 851 tdc->irq = of_irq_get(pdev->dev.of_node, i); 852 if (tdc->irq <= 0) { 853 ret = tdc->irq ?: -ENXIO; 854 goto irq_dispose; 855 } 856 857 vchan_init(&tdc->vc, &tdma->dma_dev); 858 tdc->vc.desc_free = tegra_adma_desc_free; 859 tdc->tdma = tdma; 860 } 861 862 pm_runtime_enable(&pdev->dev); 863 864 ret = pm_runtime_get_sync(&pdev->dev); 865 if (ret < 0) 866 goto rpm_disable; 867 868 ret = tegra_adma_init(tdma); 869 if (ret) 870 goto rpm_put; 871 872 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask); 873 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask); 874 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask); 875 876 tdma->dma_dev.dev = &pdev->dev; 877 tdma->dma_dev.device_alloc_chan_resources = 878 tegra_adma_alloc_chan_resources; 879 tdma->dma_dev.device_free_chan_resources = 880 tegra_adma_free_chan_resources; 881 tdma->dma_dev.device_issue_pending = tegra_adma_issue_pending; 882 tdma->dma_dev.device_prep_dma_cyclic = tegra_adma_prep_dma_cyclic; 883 tdma->dma_dev.device_config = tegra_adma_slave_config; 884 tdma->dma_dev.device_tx_status = tegra_adma_tx_status; 885 tdma->dma_dev.device_terminate_all = tegra_adma_terminate_all; 886 tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 887 tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 888 tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 889 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 890 tdma->dma_dev.device_pause = tegra_adma_pause; 891 tdma->dma_dev.device_resume = tegra_adma_resume; 892 893 ret = dma_async_device_register(&tdma->dma_dev); 894 if (ret < 0) { 895 dev_err(&pdev->dev, "ADMA registration failed: %d\n", ret); 896 goto irq_dispose; 897 } 898 899 ret = of_dma_controller_register(pdev->dev.of_node, 900 tegra_dma_of_xlate, tdma); 901 if (ret < 0) { 902 dev_err(&pdev->dev, "ADMA OF registration failed %d\n", ret); 903 goto dma_remove; 904 } 905 906 pm_runtime_put(&pdev->dev); 907 908 dev_info(&pdev->dev, "Tegra210 ADMA driver registered %d channels\n", 909 tdma->nr_channels); 910 911 return 0; 912 913 dma_remove: 914 dma_async_device_unregister(&tdma->dma_dev); 915 rpm_put: 916 pm_runtime_put_sync(&pdev->dev); 917 rpm_disable: 918 pm_runtime_disable(&pdev->dev); 919 irq_dispose: 920 while (--i >= 0) 921 irq_dispose_mapping(tdma->channels[i].irq); 922 923 return ret; 924 } 925 926 static int tegra_adma_remove(struct platform_device *pdev) 927 { 928 struct tegra_adma *tdma = platform_get_drvdata(pdev); 929 int i; 930 931 of_dma_controller_free(pdev->dev.of_node); 932 dma_async_device_unregister(&tdma->dma_dev); 933 934 for (i = 0; i < tdma->nr_channels; ++i) 935 irq_dispose_mapping(tdma->channels[i].irq); 936 937 pm_runtime_put_sync(&pdev->dev); 938 pm_runtime_disable(&pdev->dev); 939 940 return 0; 941 } 942 943 static const struct dev_pm_ops tegra_adma_dev_pm_ops = { 944 SET_RUNTIME_PM_OPS(tegra_adma_runtime_suspend, 945 tegra_adma_runtime_resume, NULL) 946 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 947 pm_runtime_force_resume) 948 }; 949 950 static struct platform_driver tegra_admac_driver = { 951 .driver = { 952 .name = "tegra-adma", 953 .pm = &tegra_adma_dev_pm_ops, 954 .of_match_table = tegra_adma_of_match, 955 }, 956 .probe = tegra_adma_probe, 957 .remove = tegra_adma_remove, 958 }; 959 960 module_platform_driver(tegra_admac_driver); 961 962 MODULE_ALIAS("platform:tegra210-adma"); 963 MODULE_DESCRIPTION("NVIDIA Tegra ADMA driver"); 964 MODULE_AUTHOR("Dara Ramesh <dramesh@nvidia.com>"); 965 MODULE_AUTHOR("Jon Hunter <jonathanh@nvidia.com>"); 966 MODULE_LICENSE("GPL v2"); 967