1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * DMA driver for Nvidia's Tegra20 APB DMA controller. 4 * 5 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dmaengine.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/err.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/mm.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/of_dma.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/reset.h> 26 #include <linux/slab.h> 27 28 #include "dmaengine.h" 29 30 #define CREATE_TRACE_POINTS 31 #include <trace/events/tegra_apb_dma.h> 32 33 #define TEGRA_APBDMA_GENERAL 0x0 34 #define TEGRA_APBDMA_GENERAL_ENABLE BIT(31) 35 36 #define TEGRA_APBDMA_CONTROL 0x010 37 #define TEGRA_APBDMA_IRQ_MASK 0x01c 38 #define TEGRA_APBDMA_IRQ_MASK_SET 0x020 39 40 /* CSR register */ 41 #define TEGRA_APBDMA_CHAN_CSR 0x00 42 #define TEGRA_APBDMA_CSR_ENB BIT(31) 43 #define TEGRA_APBDMA_CSR_IE_EOC BIT(30) 44 #define TEGRA_APBDMA_CSR_HOLD BIT(29) 45 #define TEGRA_APBDMA_CSR_DIR BIT(28) 46 #define TEGRA_APBDMA_CSR_ONCE BIT(27) 47 #define TEGRA_APBDMA_CSR_FLOW BIT(21) 48 #define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT 16 49 #define TEGRA_APBDMA_CSR_REQ_SEL_MASK 0x1F 50 #define TEGRA_APBDMA_CSR_WCOUNT_MASK 0xFFFC 51 52 /* STATUS register */ 53 #define TEGRA_APBDMA_CHAN_STATUS 0x004 54 #define TEGRA_APBDMA_STATUS_BUSY BIT(31) 55 #define TEGRA_APBDMA_STATUS_ISE_EOC BIT(30) 56 #define TEGRA_APBDMA_STATUS_HALT BIT(29) 57 #define TEGRA_APBDMA_STATUS_PING_PONG BIT(28) 58 #define TEGRA_APBDMA_STATUS_COUNT_SHIFT 2 59 #define TEGRA_APBDMA_STATUS_COUNT_MASK 0xFFFC 60 61 #define TEGRA_APBDMA_CHAN_CSRE 0x00C 62 #define TEGRA_APBDMA_CHAN_CSRE_PAUSE (1 << 31) 63 64 /* AHB memory address */ 65 #define TEGRA_APBDMA_CHAN_AHBPTR 0x010 66 67 /* AHB sequence register */ 68 #define TEGRA_APBDMA_CHAN_AHBSEQ 0x14 69 #define TEGRA_APBDMA_AHBSEQ_INTR_ENB BIT(31) 70 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8 (0 << 28) 71 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16 (1 << 28) 72 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32 (2 << 28) 73 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64 (3 << 28) 74 #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128 (4 << 28) 75 #define TEGRA_APBDMA_AHBSEQ_DATA_SWAP BIT(27) 76 #define TEGRA_APBDMA_AHBSEQ_BURST_1 (4 << 24) 77 #define TEGRA_APBDMA_AHBSEQ_BURST_4 (5 << 24) 78 #define TEGRA_APBDMA_AHBSEQ_BURST_8 (6 << 24) 79 #define TEGRA_APBDMA_AHBSEQ_DBL_BUF BIT(19) 80 #define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT 16 81 #define TEGRA_APBDMA_AHBSEQ_WRAP_NONE 0 82 83 /* APB address */ 84 #define TEGRA_APBDMA_CHAN_APBPTR 0x018 85 86 /* APB sequence register */ 87 #define TEGRA_APBDMA_CHAN_APBSEQ 0x01c 88 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8 (0 << 28) 89 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16 (1 << 28) 90 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32 (2 << 28) 91 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64 (3 << 28) 92 #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128 (4 << 28) 93 #define TEGRA_APBDMA_APBSEQ_DATA_SWAP BIT(27) 94 #define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1 (1 << 16) 95 96 /* Tegra148 specific registers */ 97 #define TEGRA_APBDMA_CHAN_WCOUNT 0x20 98 99 #define TEGRA_APBDMA_CHAN_WORD_TRANSFER 0x24 100 101 /* 102 * If any burst is in flight and DMA paused then this is the time to complete 103 * on-flight burst and update DMA status register. 104 */ 105 #define TEGRA_APBDMA_BURST_COMPLETE_TIME 20 106 107 /* Channel base address offset from APBDMA base address */ 108 #define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET 0x1000 109 110 #define TEGRA_APBDMA_SLAVE_ID_INVALID (TEGRA_APBDMA_CSR_REQ_SEL_MASK + 1) 111 112 struct tegra_dma; 113 114 /* 115 * tegra_dma_chip_data Tegra chip specific DMA data 116 * @nr_channels: Number of channels available in the controller. 117 * @channel_reg_size: Channel register size/stride. 118 * @max_dma_count: Maximum DMA transfer count supported by DMA controller. 119 * @support_channel_pause: Support channel wise pause of dma. 120 * @support_separate_wcount_reg: Support separate word count register. 121 */ 122 struct tegra_dma_chip_data { 123 int nr_channels; 124 int channel_reg_size; 125 int max_dma_count; 126 bool support_channel_pause; 127 bool support_separate_wcount_reg; 128 }; 129 130 /* DMA channel registers */ 131 struct tegra_dma_channel_regs { 132 unsigned long csr; 133 unsigned long ahb_ptr; 134 unsigned long apb_ptr; 135 unsigned long ahb_seq; 136 unsigned long apb_seq; 137 unsigned long wcount; 138 }; 139 140 /* 141 * tegra_dma_sg_req: DMA request details to configure hardware. This 142 * contains the details for one transfer to configure DMA hw. 143 * The client's request for data transfer can be broken into multiple 144 * sub-transfer as per requester details and hw support. 145 * This sub transfer get added in the list of transfer and point to Tegra 146 * DMA descriptor which manages the transfer details. 147 */ 148 struct tegra_dma_sg_req { 149 struct tegra_dma_channel_regs ch_regs; 150 unsigned int req_len; 151 bool configured; 152 bool last_sg; 153 struct list_head node; 154 struct tegra_dma_desc *dma_desc; 155 unsigned int words_xferred; 156 }; 157 158 /* 159 * tegra_dma_desc: Tegra DMA descriptors which manages the client requests. 160 * This descriptor keep track of transfer status, callbacks and request 161 * counts etc. 162 */ 163 struct tegra_dma_desc { 164 struct dma_async_tx_descriptor txd; 165 unsigned int bytes_requested; 166 unsigned int bytes_transferred; 167 enum dma_status dma_status; 168 struct list_head node; 169 struct list_head tx_list; 170 struct list_head cb_node; 171 int cb_count; 172 }; 173 174 struct tegra_dma_channel; 175 176 typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc, 177 bool to_terminate); 178 179 /* tegra_dma_channel: Channel specific information */ 180 struct tegra_dma_channel { 181 struct dma_chan dma_chan; 182 char name[12]; 183 bool config_init; 184 int id; 185 int irq; 186 void __iomem *chan_addr; 187 spinlock_t lock; 188 bool busy; 189 struct tegra_dma *tdma; 190 bool cyclic; 191 192 /* Different lists for managing the requests */ 193 struct list_head free_sg_req; 194 struct list_head pending_sg_req; 195 struct list_head free_dma_desc; 196 struct list_head cb_desc; 197 198 /* ISR handler and tasklet for bottom half of isr handling */ 199 dma_isr_handler isr_handler; 200 struct tasklet_struct tasklet; 201 202 /* Channel-slave specific configuration */ 203 unsigned int slave_id; 204 struct dma_slave_config dma_sconfig; 205 struct tegra_dma_channel_regs channel_reg; 206 }; 207 208 /* tegra_dma: Tegra DMA specific information */ 209 struct tegra_dma { 210 struct dma_device dma_dev; 211 struct device *dev; 212 struct clk *dma_clk; 213 struct reset_control *rst; 214 spinlock_t global_lock; 215 void __iomem *base_addr; 216 const struct tegra_dma_chip_data *chip_data; 217 218 /* 219 * Counter for managing global pausing of the DMA controller. 220 * Only applicable for devices that don't support individual 221 * channel pausing. 222 */ 223 u32 global_pause_count; 224 225 /* Some register need to be cache before suspend */ 226 u32 reg_gen; 227 228 /* Last member of the structure */ 229 struct tegra_dma_channel channels[0]; 230 }; 231 232 static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val) 233 { 234 writel(val, tdma->base_addr + reg); 235 } 236 237 static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg) 238 { 239 return readl(tdma->base_addr + reg); 240 } 241 242 static inline void tdc_write(struct tegra_dma_channel *tdc, 243 u32 reg, u32 val) 244 { 245 writel(val, tdc->chan_addr + reg); 246 } 247 248 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg) 249 { 250 return readl(tdc->chan_addr + reg); 251 } 252 253 static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc) 254 { 255 return container_of(dc, struct tegra_dma_channel, dma_chan); 256 } 257 258 static inline struct tegra_dma_desc *txd_to_tegra_dma_desc( 259 struct dma_async_tx_descriptor *td) 260 { 261 return container_of(td, struct tegra_dma_desc, txd); 262 } 263 264 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc) 265 { 266 return &tdc->dma_chan.dev->device; 267 } 268 269 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx); 270 static int tegra_dma_runtime_suspend(struct device *dev); 271 static int tegra_dma_runtime_resume(struct device *dev); 272 273 /* Get DMA desc from free list, if not there then allocate it. */ 274 static struct tegra_dma_desc *tegra_dma_desc_get( 275 struct tegra_dma_channel *tdc) 276 { 277 struct tegra_dma_desc *dma_desc; 278 unsigned long flags; 279 280 spin_lock_irqsave(&tdc->lock, flags); 281 282 /* Do not allocate if desc are waiting for ack */ 283 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) { 284 if (async_tx_test_ack(&dma_desc->txd)) { 285 list_del(&dma_desc->node); 286 spin_unlock_irqrestore(&tdc->lock, flags); 287 dma_desc->txd.flags = 0; 288 return dma_desc; 289 } 290 } 291 292 spin_unlock_irqrestore(&tdc->lock, flags); 293 294 /* Allocate DMA desc */ 295 dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT); 296 if (!dma_desc) 297 return NULL; 298 299 dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan); 300 dma_desc->txd.tx_submit = tegra_dma_tx_submit; 301 dma_desc->txd.flags = 0; 302 return dma_desc; 303 } 304 305 static void tegra_dma_desc_put(struct tegra_dma_channel *tdc, 306 struct tegra_dma_desc *dma_desc) 307 { 308 unsigned long flags; 309 310 spin_lock_irqsave(&tdc->lock, flags); 311 if (!list_empty(&dma_desc->tx_list)) 312 list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req); 313 list_add_tail(&dma_desc->node, &tdc->free_dma_desc); 314 spin_unlock_irqrestore(&tdc->lock, flags); 315 } 316 317 static struct tegra_dma_sg_req *tegra_dma_sg_req_get( 318 struct tegra_dma_channel *tdc) 319 { 320 struct tegra_dma_sg_req *sg_req = NULL; 321 unsigned long flags; 322 323 spin_lock_irqsave(&tdc->lock, flags); 324 if (!list_empty(&tdc->free_sg_req)) { 325 sg_req = list_first_entry(&tdc->free_sg_req, 326 typeof(*sg_req), node); 327 list_del(&sg_req->node); 328 spin_unlock_irqrestore(&tdc->lock, flags); 329 return sg_req; 330 } 331 spin_unlock_irqrestore(&tdc->lock, flags); 332 333 sg_req = kzalloc(sizeof(struct tegra_dma_sg_req), GFP_NOWAIT); 334 335 return sg_req; 336 } 337 338 static int tegra_dma_slave_config(struct dma_chan *dc, 339 struct dma_slave_config *sconfig) 340 { 341 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 342 343 if (!list_empty(&tdc->pending_sg_req)) { 344 dev_err(tdc2dev(tdc), "Configuration not allowed\n"); 345 return -EBUSY; 346 } 347 348 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig)); 349 if (tdc->slave_id == TEGRA_APBDMA_SLAVE_ID_INVALID && 350 sconfig->device_fc) { 351 if (sconfig->slave_id > TEGRA_APBDMA_CSR_REQ_SEL_MASK) 352 return -EINVAL; 353 tdc->slave_id = sconfig->slave_id; 354 } 355 tdc->config_init = true; 356 return 0; 357 } 358 359 static void tegra_dma_global_pause(struct tegra_dma_channel *tdc, 360 bool wait_for_burst_complete) 361 { 362 struct tegra_dma *tdma = tdc->tdma; 363 364 spin_lock(&tdma->global_lock); 365 366 if (tdc->tdma->global_pause_count == 0) { 367 tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0); 368 if (wait_for_burst_complete) 369 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME); 370 } 371 372 tdc->tdma->global_pause_count++; 373 374 spin_unlock(&tdma->global_lock); 375 } 376 377 static void tegra_dma_global_resume(struct tegra_dma_channel *tdc) 378 { 379 struct tegra_dma *tdma = tdc->tdma; 380 381 spin_lock(&tdma->global_lock); 382 383 if (WARN_ON(tdc->tdma->global_pause_count == 0)) 384 goto out; 385 386 if (--tdc->tdma->global_pause_count == 0) 387 tdma_write(tdma, TEGRA_APBDMA_GENERAL, 388 TEGRA_APBDMA_GENERAL_ENABLE); 389 390 out: 391 spin_unlock(&tdma->global_lock); 392 } 393 394 static void tegra_dma_pause(struct tegra_dma_channel *tdc, 395 bool wait_for_burst_complete) 396 { 397 struct tegra_dma *tdma = tdc->tdma; 398 399 if (tdma->chip_data->support_channel_pause) { 400 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 401 TEGRA_APBDMA_CHAN_CSRE_PAUSE); 402 if (wait_for_burst_complete) 403 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME); 404 } else { 405 tegra_dma_global_pause(tdc, wait_for_burst_complete); 406 } 407 } 408 409 static void tegra_dma_resume(struct tegra_dma_channel *tdc) 410 { 411 struct tegra_dma *tdma = tdc->tdma; 412 413 if (tdma->chip_data->support_channel_pause) { 414 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0); 415 } else { 416 tegra_dma_global_resume(tdc); 417 } 418 } 419 420 static void tegra_dma_stop(struct tegra_dma_channel *tdc) 421 { 422 u32 csr; 423 u32 status; 424 425 /* Disable interrupts */ 426 csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR); 427 csr &= ~TEGRA_APBDMA_CSR_IE_EOC; 428 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr); 429 430 /* Disable DMA */ 431 csr &= ~TEGRA_APBDMA_CSR_ENB; 432 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr); 433 434 /* Clear interrupt status if it is there */ 435 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); 436 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) { 437 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__); 438 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status); 439 } 440 tdc->busy = false; 441 } 442 443 static void tegra_dma_start(struct tegra_dma_channel *tdc, 444 struct tegra_dma_sg_req *sg_req) 445 { 446 struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs; 447 448 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr); 449 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq); 450 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr); 451 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq); 452 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr); 453 if (tdc->tdma->chip_data->support_separate_wcount_reg) 454 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, ch_regs->wcount); 455 456 /* Start DMA */ 457 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, 458 ch_regs->csr | TEGRA_APBDMA_CSR_ENB); 459 } 460 461 static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc, 462 struct tegra_dma_sg_req *nsg_req) 463 { 464 unsigned long status; 465 466 /* 467 * The DMA controller reloads the new configuration for next transfer 468 * after last burst of current transfer completes. 469 * If there is no IEC status then this makes sure that last burst 470 * has not be completed. There may be case that last burst is on 471 * flight and so it can complete but because DMA is paused, it 472 * will not generates interrupt as well as not reload the new 473 * configuration. 474 * If there is already IEC status then interrupt handler need to 475 * load new configuration. 476 */ 477 tegra_dma_pause(tdc, false); 478 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); 479 480 /* 481 * If interrupt is pending then do nothing as the ISR will handle 482 * the programing for new request. 483 */ 484 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) { 485 dev_err(tdc2dev(tdc), 486 "Skipping new configuration as interrupt is pending\n"); 487 tegra_dma_resume(tdc); 488 return; 489 } 490 491 /* Safe to program new configuration */ 492 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr); 493 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr); 494 if (tdc->tdma->chip_data->support_separate_wcount_reg) 495 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, 496 nsg_req->ch_regs.wcount); 497 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, 498 nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB); 499 nsg_req->configured = true; 500 nsg_req->words_xferred = 0; 501 502 tegra_dma_resume(tdc); 503 } 504 505 static void tdc_start_head_req(struct tegra_dma_channel *tdc) 506 { 507 struct tegra_dma_sg_req *sg_req; 508 509 if (list_empty(&tdc->pending_sg_req)) 510 return; 511 512 sg_req = list_first_entry(&tdc->pending_sg_req, 513 typeof(*sg_req), node); 514 tegra_dma_start(tdc, sg_req); 515 sg_req->configured = true; 516 sg_req->words_xferred = 0; 517 tdc->busy = true; 518 } 519 520 static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc) 521 { 522 struct tegra_dma_sg_req *hsgreq; 523 struct tegra_dma_sg_req *hnsgreq; 524 525 if (list_empty(&tdc->pending_sg_req)) 526 return; 527 528 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node); 529 if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) { 530 hnsgreq = list_first_entry(&hsgreq->node, 531 typeof(*hnsgreq), node); 532 tegra_dma_configure_for_next(tdc, hnsgreq); 533 } 534 } 535 536 static inline int get_current_xferred_count(struct tegra_dma_channel *tdc, 537 struct tegra_dma_sg_req *sg_req, unsigned long status) 538 { 539 return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4; 540 } 541 542 static void tegra_dma_abort_all(struct tegra_dma_channel *tdc) 543 { 544 struct tegra_dma_sg_req *sgreq; 545 struct tegra_dma_desc *dma_desc; 546 547 while (!list_empty(&tdc->pending_sg_req)) { 548 sgreq = list_first_entry(&tdc->pending_sg_req, 549 typeof(*sgreq), node); 550 list_move_tail(&sgreq->node, &tdc->free_sg_req); 551 if (sgreq->last_sg) { 552 dma_desc = sgreq->dma_desc; 553 dma_desc->dma_status = DMA_ERROR; 554 list_add_tail(&dma_desc->node, &tdc->free_dma_desc); 555 556 /* Add in cb list if it is not there. */ 557 if (!dma_desc->cb_count) 558 list_add_tail(&dma_desc->cb_node, 559 &tdc->cb_desc); 560 dma_desc->cb_count++; 561 } 562 } 563 tdc->isr_handler = NULL; 564 } 565 566 static bool handle_continuous_head_request(struct tegra_dma_channel *tdc, 567 struct tegra_dma_sg_req *last_sg_req, bool to_terminate) 568 { 569 struct tegra_dma_sg_req *hsgreq = NULL; 570 571 if (list_empty(&tdc->pending_sg_req)) { 572 dev_err(tdc2dev(tdc), "DMA is running without req\n"); 573 tegra_dma_stop(tdc); 574 return false; 575 } 576 577 /* 578 * Check that head req on list should be in flight. 579 * If it is not in flight then abort transfer as 580 * looping of transfer can not continue. 581 */ 582 hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node); 583 if (!hsgreq->configured) { 584 tegra_dma_stop(tdc); 585 dev_err(tdc2dev(tdc), "Error in DMA transfer, aborting DMA\n"); 586 tegra_dma_abort_all(tdc); 587 return false; 588 } 589 590 /* Configure next request */ 591 if (!to_terminate) 592 tdc_configure_next_head_desc(tdc); 593 return true; 594 } 595 596 static void handle_once_dma_done(struct tegra_dma_channel *tdc, 597 bool to_terminate) 598 { 599 struct tegra_dma_sg_req *sgreq; 600 struct tegra_dma_desc *dma_desc; 601 602 tdc->busy = false; 603 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node); 604 dma_desc = sgreq->dma_desc; 605 dma_desc->bytes_transferred += sgreq->req_len; 606 607 list_del(&sgreq->node); 608 if (sgreq->last_sg) { 609 dma_desc->dma_status = DMA_COMPLETE; 610 dma_cookie_complete(&dma_desc->txd); 611 if (!dma_desc->cb_count) 612 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc); 613 dma_desc->cb_count++; 614 list_add_tail(&dma_desc->node, &tdc->free_dma_desc); 615 } 616 list_add_tail(&sgreq->node, &tdc->free_sg_req); 617 618 /* Do not start DMA if it is going to be terminate */ 619 if (to_terminate || list_empty(&tdc->pending_sg_req)) 620 return; 621 622 tdc_start_head_req(tdc); 623 } 624 625 static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc, 626 bool to_terminate) 627 { 628 struct tegra_dma_sg_req *sgreq; 629 struct tegra_dma_desc *dma_desc; 630 bool st; 631 632 sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node); 633 dma_desc = sgreq->dma_desc; 634 /* if we dma for long enough the transfer count will wrap */ 635 dma_desc->bytes_transferred = 636 (dma_desc->bytes_transferred + sgreq->req_len) % 637 dma_desc->bytes_requested; 638 639 /* Callback need to be call */ 640 if (!dma_desc->cb_count) 641 list_add_tail(&dma_desc->cb_node, &tdc->cb_desc); 642 dma_desc->cb_count++; 643 644 sgreq->words_xferred = 0; 645 646 /* If not last req then put at end of pending list */ 647 if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) { 648 list_move_tail(&sgreq->node, &tdc->pending_sg_req); 649 sgreq->configured = false; 650 st = handle_continuous_head_request(tdc, sgreq, to_terminate); 651 if (!st) 652 dma_desc->dma_status = DMA_ERROR; 653 } 654 } 655 656 static void tegra_dma_tasklet(unsigned long data) 657 { 658 struct tegra_dma_channel *tdc = (struct tegra_dma_channel *)data; 659 struct dmaengine_desc_callback cb; 660 struct tegra_dma_desc *dma_desc; 661 unsigned long flags; 662 int cb_count; 663 664 spin_lock_irqsave(&tdc->lock, flags); 665 while (!list_empty(&tdc->cb_desc)) { 666 dma_desc = list_first_entry(&tdc->cb_desc, 667 typeof(*dma_desc), cb_node); 668 list_del(&dma_desc->cb_node); 669 dmaengine_desc_get_callback(&dma_desc->txd, &cb); 670 cb_count = dma_desc->cb_count; 671 dma_desc->cb_count = 0; 672 trace_tegra_dma_complete_cb(&tdc->dma_chan, cb_count, 673 cb.callback); 674 spin_unlock_irqrestore(&tdc->lock, flags); 675 while (cb_count--) 676 dmaengine_desc_callback_invoke(&cb, NULL); 677 spin_lock_irqsave(&tdc->lock, flags); 678 } 679 spin_unlock_irqrestore(&tdc->lock, flags); 680 } 681 682 static irqreturn_t tegra_dma_isr(int irq, void *dev_id) 683 { 684 struct tegra_dma_channel *tdc = dev_id; 685 unsigned long status; 686 unsigned long flags; 687 688 spin_lock_irqsave(&tdc->lock, flags); 689 690 trace_tegra_dma_isr(&tdc->dma_chan, irq); 691 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); 692 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) { 693 tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status); 694 tdc->isr_handler(tdc, false); 695 tasklet_schedule(&tdc->tasklet); 696 spin_unlock_irqrestore(&tdc->lock, flags); 697 return IRQ_HANDLED; 698 } 699 700 spin_unlock_irqrestore(&tdc->lock, flags); 701 dev_info(tdc2dev(tdc), 702 "Interrupt already served status 0x%08lx\n", status); 703 return IRQ_NONE; 704 } 705 706 static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd) 707 { 708 struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd); 709 struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan); 710 unsigned long flags; 711 dma_cookie_t cookie; 712 713 spin_lock_irqsave(&tdc->lock, flags); 714 dma_desc->dma_status = DMA_IN_PROGRESS; 715 cookie = dma_cookie_assign(&dma_desc->txd); 716 list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req); 717 spin_unlock_irqrestore(&tdc->lock, flags); 718 return cookie; 719 } 720 721 static void tegra_dma_issue_pending(struct dma_chan *dc) 722 { 723 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 724 unsigned long flags; 725 726 spin_lock_irqsave(&tdc->lock, flags); 727 if (list_empty(&tdc->pending_sg_req)) { 728 dev_err(tdc2dev(tdc), "No DMA request\n"); 729 goto end; 730 } 731 if (!tdc->busy) { 732 tdc_start_head_req(tdc); 733 734 /* Continuous single mode: Configure next req */ 735 if (tdc->cyclic) { 736 /* 737 * Wait for 1 burst time for configure DMA for 738 * next transfer. 739 */ 740 udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME); 741 tdc_configure_next_head_desc(tdc); 742 } 743 } 744 end: 745 spin_unlock_irqrestore(&tdc->lock, flags); 746 } 747 748 static int tegra_dma_terminate_all(struct dma_chan *dc) 749 { 750 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 751 struct tegra_dma_sg_req *sgreq; 752 struct tegra_dma_desc *dma_desc; 753 unsigned long flags; 754 unsigned long status; 755 unsigned long wcount; 756 bool was_busy; 757 758 spin_lock_irqsave(&tdc->lock, flags); 759 if (list_empty(&tdc->pending_sg_req)) { 760 spin_unlock_irqrestore(&tdc->lock, flags); 761 return 0; 762 } 763 764 if (!tdc->busy) 765 goto skip_dma_stop; 766 767 /* Pause DMA before checking the queue status */ 768 tegra_dma_pause(tdc, true); 769 770 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); 771 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) { 772 dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__); 773 tdc->isr_handler(tdc, true); 774 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); 775 } 776 if (tdc->tdma->chip_data->support_separate_wcount_reg) 777 wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER); 778 else 779 wcount = status; 780 781 was_busy = tdc->busy; 782 tegra_dma_stop(tdc); 783 784 if (!list_empty(&tdc->pending_sg_req) && was_busy) { 785 sgreq = list_first_entry(&tdc->pending_sg_req, 786 typeof(*sgreq), node); 787 sgreq->dma_desc->bytes_transferred += 788 get_current_xferred_count(tdc, sgreq, wcount); 789 } 790 tegra_dma_resume(tdc); 791 792 skip_dma_stop: 793 tegra_dma_abort_all(tdc); 794 795 while (!list_empty(&tdc->cb_desc)) { 796 dma_desc = list_first_entry(&tdc->cb_desc, 797 typeof(*dma_desc), cb_node); 798 list_del(&dma_desc->cb_node); 799 dma_desc->cb_count = 0; 800 } 801 spin_unlock_irqrestore(&tdc->lock, flags); 802 return 0; 803 } 804 805 static unsigned int tegra_dma_sg_bytes_xferred(struct tegra_dma_channel *tdc, 806 struct tegra_dma_sg_req *sg_req) 807 { 808 unsigned long status, wcount = 0; 809 810 if (!list_is_first(&sg_req->node, &tdc->pending_sg_req)) 811 return 0; 812 813 if (tdc->tdma->chip_data->support_separate_wcount_reg) 814 wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER); 815 816 status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS); 817 818 if (!tdc->tdma->chip_data->support_separate_wcount_reg) 819 wcount = status; 820 821 if (status & TEGRA_APBDMA_STATUS_ISE_EOC) 822 return sg_req->req_len; 823 824 wcount = get_current_xferred_count(tdc, sg_req, wcount); 825 826 if (!wcount) { 827 /* 828 * If wcount wasn't ever polled for this SG before, then 829 * simply assume that transfer hasn't started yet. 830 * 831 * Otherwise it's the end of the transfer. 832 * 833 * The alternative would be to poll the status register 834 * until EOC bit is set or wcount goes UP. That's so 835 * because EOC bit is getting set only after the last 836 * burst's completion and counter is less than the actual 837 * transfer size by 4 bytes. The counter value wraps around 838 * in a cyclic mode before EOC is set(!), so we can't easily 839 * distinguish start of transfer from its end. 840 */ 841 if (sg_req->words_xferred) 842 wcount = sg_req->req_len - 4; 843 844 } else if (wcount < sg_req->words_xferred) { 845 /* 846 * This case will never happen for a non-cyclic transfer. 847 * 848 * For a cyclic transfer, although it is possible for the 849 * next transfer to have already started (resetting the word 850 * count), this case should still not happen because we should 851 * have detected that the EOC bit is set and hence the transfer 852 * was completed. 853 */ 854 WARN_ON_ONCE(1); 855 856 wcount = sg_req->req_len - 4; 857 } else { 858 sg_req->words_xferred = wcount; 859 } 860 861 return wcount; 862 } 863 864 static enum dma_status tegra_dma_tx_status(struct dma_chan *dc, 865 dma_cookie_t cookie, struct dma_tx_state *txstate) 866 { 867 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 868 struct tegra_dma_desc *dma_desc; 869 struct tegra_dma_sg_req *sg_req; 870 enum dma_status ret; 871 unsigned long flags; 872 unsigned int residual; 873 unsigned int bytes = 0; 874 875 ret = dma_cookie_status(dc, cookie, txstate); 876 if (ret == DMA_COMPLETE) 877 return ret; 878 879 spin_lock_irqsave(&tdc->lock, flags); 880 881 /* Check on wait_ack desc status */ 882 list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) { 883 if (dma_desc->txd.cookie == cookie) { 884 ret = dma_desc->dma_status; 885 goto found; 886 } 887 } 888 889 /* Check in pending list */ 890 list_for_each_entry(sg_req, &tdc->pending_sg_req, node) { 891 dma_desc = sg_req->dma_desc; 892 if (dma_desc->txd.cookie == cookie) { 893 bytes = tegra_dma_sg_bytes_xferred(tdc, sg_req); 894 ret = dma_desc->dma_status; 895 goto found; 896 } 897 } 898 899 dev_dbg(tdc2dev(tdc), "cookie %d not found\n", cookie); 900 dma_desc = NULL; 901 902 found: 903 if (dma_desc && txstate) { 904 residual = dma_desc->bytes_requested - 905 ((dma_desc->bytes_transferred + bytes) % 906 dma_desc->bytes_requested); 907 dma_set_residue(txstate, residual); 908 } 909 910 trace_tegra_dma_tx_status(&tdc->dma_chan, cookie, txstate); 911 spin_unlock_irqrestore(&tdc->lock, flags); 912 return ret; 913 } 914 915 static inline int get_bus_width(struct tegra_dma_channel *tdc, 916 enum dma_slave_buswidth slave_bw) 917 { 918 switch (slave_bw) { 919 case DMA_SLAVE_BUSWIDTH_1_BYTE: 920 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8; 921 case DMA_SLAVE_BUSWIDTH_2_BYTES: 922 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16; 923 case DMA_SLAVE_BUSWIDTH_4_BYTES: 924 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32; 925 case DMA_SLAVE_BUSWIDTH_8_BYTES: 926 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64; 927 default: 928 dev_warn(tdc2dev(tdc), 929 "slave bw is not supported, using 32bits\n"); 930 return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32; 931 } 932 } 933 934 static inline int get_burst_size(struct tegra_dma_channel *tdc, 935 u32 burst_size, enum dma_slave_buswidth slave_bw, int len) 936 { 937 int burst_byte; 938 int burst_ahb_width; 939 940 /* 941 * burst_size from client is in terms of the bus_width. 942 * convert them into AHB memory width which is 4 byte. 943 */ 944 burst_byte = burst_size * slave_bw; 945 burst_ahb_width = burst_byte / 4; 946 947 /* If burst size is 0 then calculate the burst size based on length */ 948 if (!burst_ahb_width) { 949 if (len & 0xF) 950 return TEGRA_APBDMA_AHBSEQ_BURST_1; 951 else if ((len >> 4) & 0x1) 952 return TEGRA_APBDMA_AHBSEQ_BURST_4; 953 else 954 return TEGRA_APBDMA_AHBSEQ_BURST_8; 955 } 956 if (burst_ahb_width < 4) 957 return TEGRA_APBDMA_AHBSEQ_BURST_1; 958 else if (burst_ahb_width < 8) 959 return TEGRA_APBDMA_AHBSEQ_BURST_4; 960 else 961 return TEGRA_APBDMA_AHBSEQ_BURST_8; 962 } 963 964 static int get_transfer_param(struct tegra_dma_channel *tdc, 965 enum dma_transfer_direction direction, unsigned long *apb_addr, 966 unsigned long *apb_seq, unsigned long *csr, unsigned int *burst_size, 967 enum dma_slave_buswidth *slave_bw) 968 { 969 switch (direction) { 970 case DMA_MEM_TO_DEV: 971 *apb_addr = tdc->dma_sconfig.dst_addr; 972 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width); 973 *burst_size = tdc->dma_sconfig.dst_maxburst; 974 *slave_bw = tdc->dma_sconfig.dst_addr_width; 975 *csr = TEGRA_APBDMA_CSR_DIR; 976 return 0; 977 978 case DMA_DEV_TO_MEM: 979 *apb_addr = tdc->dma_sconfig.src_addr; 980 *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width); 981 *burst_size = tdc->dma_sconfig.src_maxburst; 982 *slave_bw = tdc->dma_sconfig.src_addr_width; 983 *csr = 0; 984 return 0; 985 986 default: 987 dev_err(tdc2dev(tdc), "DMA direction is not supported\n"); 988 return -EINVAL; 989 } 990 return -EINVAL; 991 } 992 993 static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc, 994 struct tegra_dma_channel_regs *ch_regs, u32 len) 995 { 996 u32 len_field = (len - 4) & 0xFFFC; 997 998 if (tdc->tdma->chip_data->support_separate_wcount_reg) 999 ch_regs->wcount = len_field; 1000 else 1001 ch_regs->csr |= len_field; 1002 } 1003 1004 static struct dma_async_tx_descriptor *tegra_dma_prep_slave_sg( 1005 struct dma_chan *dc, struct scatterlist *sgl, unsigned int sg_len, 1006 enum dma_transfer_direction direction, unsigned long flags, 1007 void *context) 1008 { 1009 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 1010 struct tegra_dma_desc *dma_desc; 1011 unsigned int i; 1012 struct scatterlist *sg; 1013 unsigned long csr, ahb_seq, apb_ptr, apb_seq; 1014 struct list_head req_list; 1015 struct tegra_dma_sg_req *sg_req = NULL; 1016 u32 burst_size; 1017 enum dma_slave_buswidth slave_bw; 1018 1019 if (!tdc->config_init) { 1020 dev_err(tdc2dev(tdc), "DMA channel is not configured\n"); 1021 return NULL; 1022 } 1023 if (sg_len < 1) { 1024 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len); 1025 return NULL; 1026 } 1027 1028 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr, 1029 &burst_size, &slave_bw) < 0) 1030 return NULL; 1031 1032 INIT_LIST_HEAD(&req_list); 1033 1034 ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB; 1035 ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE << 1036 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT; 1037 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32; 1038 1039 csr |= TEGRA_APBDMA_CSR_ONCE; 1040 1041 if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) { 1042 csr |= TEGRA_APBDMA_CSR_FLOW; 1043 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT; 1044 } 1045 1046 if (flags & DMA_PREP_INTERRUPT) { 1047 csr |= TEGRA_APBDMA_CSR_IE_EOC; 1048 } else { 1049 WARN_ON_ONCE(1); 1050 return NULL; 1051 } 1052 1053 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1; 1054 1055 dma_desc = tegra_dma_desc_get(tdc); 1056 if (!dma_desc) { 1057 dev_err(tdc2dev(tdc), "DMA descriptors not available\n"); 1058 return NULL; 1059 } 1060 INIT_LIST_HEAD(&dma_desc->tx_list); 1061 INIT_LIST_HEAD(&dma_desc->cb_node); 1062 dma_desc->cb_count = 0; 1063 dma_desc->bytes_requested = 0; 1064 dma_desc->bytes_transferred = 0; 1065 dma_desc->dma_status = DMA_IN_PROGRESS; 1066 1067 /* Make transfer requests */ 1068 for_each_sg(sgl, sg, sg_len, i) { 1069 u32 len, mem; 1070 1071 mem = sg_dma_address(sg); 1072 len = sg_dma_len(sg); 1073 1074 if ((len & 3) || (mem & 3) || 1075 (len > tdc->tdma->chip_data->max_dma_count)) { 1076 dev_err(tdc2dev(tdc), 1077 "DMA length/memory address is not supported\n"); 1078 tegra_dma_desc_put(tdc, dma_desc); 1079 return NULL; 1080 } 1081 1082 sg_req = tegra_dma_sg_req_get(tdc); 1083 if (!sg_req) { 1084 dev_err(tdc2dev(tdc), "DMA sg-req not available\n"); 1085 tegra_dma_desc_put(tdc, dma_desc); 1086 return NULL; 1087 } 1088 1089 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len); 1090 dma_desc->bytes_requested += len; 1091 1092 sg_req->ch_regs.apb_ptr = apb_ptr; 1093 sg_req->ch_regs.ahb_ptr = mem; 1094 sg_req->ch_regs.csr = csr; 1095 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len); 1096 sg_req->ch_regs.apb_seq = apb_seq; 1097 sg_req->ch_regs.ahb_seq = ahb_seq; 1098 sg_req->configured = false; 1099 sg_req->last_sg = false; 1100 sg_req->dma_desc = dma_desc; 1101 sg_req->req_len = len; 1102 1103 list_add_tail(&sg_req->node, &dma_desc->tx_list); 1104 } 1105 sg_req->last_sg = true; 1106 if (flags & DMA_CTRL_ACK) 1107 dma_desc->txd.flags = DMA_CTRL_ACK; 1108 1109 /* 1110 * Make sure that mode should not be conflicting with currently 1111 * configured mode. 1112 */ 1113 if (!tdc->isr_handler) { 1114 tdc->isr_handler = handle_once_dma_done; 1115 tdc->cyclic = false; 1116 } else { 1117 if (tdc->cyclic) { 1118 dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n"); 1119 tegra_dma_desc_put(tdc, dma_desc); 1120 return NULL; 1121 } 1122 } 1123 1124 return &dma_desc->txd; 1125 } 1126 1127 static struct dma_async_tx_descriptor *tegra_dma_prep_dma_cyclic( 1128 struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len, 1129 size_t period_len, enum dma_transfer_direction direction, 1130 unsigned long flags) 1131 { 1132 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 1133 struct tegra_dma_desc *dma_desc = NULL; 1134 struct tegra_dma_sg_req *sg_req = NULL; 1135 unsigned long csr, ahb_seq, apb_ptr, apb_seq; 1136 int len; 1137 size_t remain_len; 1138 dma_addr_t mem = buf_addr; 1139 u32 burst_size; 1140 enum dma_slave_buswidth slave_bw; 1141 1142 if (!buf_len || !period_len) { 1143 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n"); 1144 return NULL; 1145 } 1146 1147 if (!tdc->config_init) { 1148 dev_err(tdc2dev(tdc), "DMA slave is not configured\n"); 1149 return NULL; 1150 } 1151 1152 /* 1153 * We allow to take more number of requests till DMA is 1154 * not started. The driver will loop over all requests. 1155 * Once DMA is started then new requests can be queued only after 1156 * terminating the DMA. 1157 */ 1158 if (tdc->busy) { 1159 dev_err(tdc2dev(tdc), "Request not allowed when DMA running\n"); 1160 return NULL; 1161 } 1162 1163 /* 1164 * We only support cycle transfer when buf_len is multiple of 1165 * period_len. 1166 */ 1167 if (buf_len % period_len) { 1168 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n"); 1169 return NULL; 1170 } 1171 1172 len = period_len; 1173 if ((len & 3) || (buf_addr & 3) || 1174 (len > tdc->tdma->chip_data->max_dma_count)) { 1175 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n"); 1176 return NULL; 1177 } 1178 1179 if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr, 1180 &burst_size, &slave_bw) < 0) 1181 return NULL; 1182 1183 ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB; 1184 ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE << 1185 TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT; 1186 ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32; 1187 1188 if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) { 1189 csr |= TEGRA_APBDMA_CSR_FLOW; 1190 csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT; 1191 } 1192 1193 if (flags & DMA_PREP_INTERRUPT) { 1194 csr |= TEGRA_APBDMA_CSR_IE_EOC; 1195 } else { 1196 WARN_ON_ONCE(1); 1197 return NULL; 1198 } 1199 1200 apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1; 1201 1202 dma_desc = tegra_dma_desc_get(tdc); 1203 if (!dma_desc) { 1204 dev_err(tdc2dev(tdc), "not enough descriptors available\n"); 1205 return NULL; 1206 } 1207 1208 INIT_LIST_HEAD(&dma_desc->tx_list); 1209 INIT_LIST_HEAD(&dma_desc->cb_node); 1210 dma_desc->cb_count = 0; 1211 1212 dma_desc->bytes_transferred = 0; 1213 dma_desc->bytes_requested = buf_len; 1214 remain_len = buf_len; 1215 1216 /* Split transfer equal to period size */ 1217 while (remain_len) { 1218 sg_req = tegra_dma_sg_req_get(tdc); 1219 if (!sg_req) { 1220 dev_err(tdc2dev(tdc), "DMA sg-req not available\n"); 1221 tegra_dma_desc_put(tdc, dma_desc); 1222 return NULL; 1223 } 1224 1225 ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len); 1226 sg_req->ch_regs.apb_ptr = apb_ptr; 1227 sg_req->ch_regs.ahb_ptr = mem; 1228 sg_req->ch_regs.csr = csr; 1229 tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len); 1230 sg_req->ch_regs.apb_seq = apb_seq; 1231 sg_req->ch_regs.ahb_seq = ahb_seq; 1232 sg_req->configured = false; 1233 sg_req->last_sg = false; 1234 sg_req->dma_desc = dma_desc; 1235 sg_req->req_len = len; 1236 1237 list_add_tail(&sg_req->node, &dma_desc->tx_list); 1238 remain_len -= len; 1239 mem += len; 1240 } 1241 sg_req->last_sg = true; 1242 if (flags & DMA_CTRL_ACK) 1243 dma_desc->txd.flags = DMA_CTRL_ACK; 1244 1245 /* 1246 * Make sure that mode should not be conflicting with currently 1247 * configured mode. 1248 */ 1249 if (!tdc->isr_handler) { 1250 tdc->isr_handler = handle_cont_sngl_cycle_dma_done; 1251 tdc->cyclic = true; 1252 } else { 1253 if (!tdc->cyclic) { 1254 dev_err(tdc2dev(tdc), "DMA configuration conflict\n"); 1255 tegra_dma_desc_put(tdc, dma_desc); 1256 return NULL; 1257 } 1258 } 1259 1260 return &dma_desc->txd; 1261 } 1262 1263 static int tegra_dma_alloc_chan_resources(struct dma_chan *dc) 1264 { 1265 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 1266 struct tegra_dma *tdma = tdc->tdma; 1267 int ret; 1268 1269 dma_cookie_init(&tdc->dma_chan); 1270 tdc->config_init = false; 1271 1272 ret = pm_runtime_get_sync(tdma->dev); 1273 if (ret < 0) 1274 return ret; 1275 1276 return 0; 1277 } 1278 1279 static void tegra_dma_free_chan_resources(struct dma_chan *dc) 1280 { 1281 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 1282 struct tegra_dma *tdma = tdc->tdma; 1283 struct tegra_dma_desc *dma_desc; 1284 struct tegra_dma_sg_req *sg_req; 1285 struct list_head dma_desc_list; 1286 struct list_head sg_req_list; 1287 unsigned long flags; 1288 1289 INIT_LIST_HEAD(&dma_desc_list); 1290 INIT_LIST_HEAD(&sg_req_list); 1291 1292 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id); 1293 1294 if (tdc->busy) 1295 tegra_dma_terminate_all(dc); 1296 1297 spin_lock_irqsave(&tdc->lock, flags); 1298 list_splice_init(&tdc->pending_sg_req, &sg_req_list); 1299 list_splice_init(&tdc->free_sg_req, &sg_req_list); 1300 list_splice_init(&tdc->free_dma_desc, &dma_desc_list); 1301 INIT_LIST_HEAD(&tdc->cb_desc); 1302 tdc->config_init = false; 1303 tdc->isr_handler = NULL; 1304 spin_unlock_irqrestore(&tdc->lock, flags); 1305 1306 while (!list_empty(&dma_desc_list)) { 1307 dma_desc = list_first_entry(&dma_desc_list, 1308 typeof(*dma_desc), node); 1309 list_del(&dma_desc->node); 1310 kfree(dma_desc); 1311 } 1312 1313 while (!list_empty(&sg_req_list)) { 1314 sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node); 1315 list_del(&sg_req->node); 1316 kfree(sg_req); 1317 } 1318 pm_runtime_put(tdma->dev); 1319 1320 tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID; 1321 } 1322 1323 static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec, 1324 struct of_dma *ofdma) 1325 { 1326 struct tegra_dma *tdma = ofdma->of_dma_data; 1327 struct dma_chan *chan; 1328 struct tegra_dma_channel *tdc; 1329 1330 if (dma_spec->args[0] > TEGRA_APBDMA_CSR_REQ_SEL_MASK) { 1331 dev_err(tdma->dev, "Invalid slave id: %d\n", dma_spec->args[0]); 1332 return NULL; 1333 } 1334 1335 chan = dma_get_any_slave_channel(&tdma->dma_dev); 1336 if (!chan) 1337 return NULL; 1338 1339 tdc = to_tegra_dma_chan(chan); 1340 tdc->slave_id = dma_spec->args[0]; 1341 1342 return chan; 1343 } 1344 1345 /* Tegra20 specific DMA controller information */ 1346 static const struct tegra_dma_chip_data tegra20_dma_chip_data = { 1347 .nr_channels = 16, 1348 .channel_reg_size = 0x20, 1349 .max_dma_count = 1024UL * 64, 1350 .support_channel_pause = false, 1351 .support_separate_wcount_reg = false, 1352 }; 1353 1354 /* Tegra30 specific DMA controller information */ 1355 static const struct tegra_dma_chip_data tegra30_dma_chip_data = { 1356 .nr_channels = 32, 1357 .channel_reg_size = 0x20, 1358 .max_dma_count = 1024UL * 64, 1359 .support_channel_pause = false, 1360 .support_separate_wcount_reg = false, 1361 }; 1362 1363 /* Tegra114 specific DMA controller information */ 1364 static const struct tegra_dma_chip_data tegra114_dma_chip_data = { 1365 .nr_channels = 32, 1366 .channel_reg_size = 0x20, 1367 .max_dma_count = 1024UL * 64, 1368 .support_channel_pause = true, 1369 .support_separate_wcount_reg = false, 1370 }; 1371 1372 /* Tegra148 specific DMA controller information */ 1373 static const struct tegra_dma_chip_data tegra148_dma_chip_data = { 1374 .nr_channels = 32, 1375 .channel_reg_size = 0x40, 1376 .max_dma_count = 1024UL * 64, 1377 .support_channel_pause = true, 1378 .support_separate_wcount_reg = true, 1379 }; 1380 1381 static int tegra_dma_probe(struct platform_device *pdev) 1382 { 1383 struct resource *res; 1384 struct tegra_dma *tdma; 1385 int ret; 1386 int i; 1387 const struct tegra_dma_chip_data *cdata; 1388 1389 cdata = of_device_get_match_data(&pdev->dev); 1390 if (!cdata) { 1391 dev_err(&pdev->dev, "Error: No device match data found\n"); 1392 return -ENODEV; 1393 } 1394 1395 tdma = devm_kzalloc(&pdev->dev, 1396 struct_size(tdma, channels, cdata->nr_channels), 1397 GFP_KERNEL); 1398 if (!tdma) 1399 return -ENOMEM; 1400 1401 tdma->dev = &pdev->dev; 1402 tdma->chip_data = cdata; 1403 platform_set_drvdata(pdev, tdma); 1404 1405 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1406 tdma->base_addr = devm_ioremap_resource(&pdev->dev, res); 1407 if (IS_ERR(tdma->base_addr)) 1408 return PTR_ERR(tdma->base_addr); 1409 1410 tdma->dma_clk = devm_clk_get(&pdev->dev, NULL); 1411 if (IS_ERR(tdma->dma_clk)) { 1412 dev_err(&pdev->dev, "Error: Missing controller clock\n"); 1413 return PTR_ERR(tdma->dma_clk); 1414 } 1415 1416 tdma->rst = devm_reset_control_get(&pdev->dev, "dma"); 1417 if (IS_ERR(tdma->rst)) { 1418 dev_err(&pdev->dev, "Error: Missing reset\n"); 1419 return PTR_ERR(tdma->rst); 1420 } 1421 1422 spin_lock_init(&tdma->global_lock); 1423 1424 pm_runtime_enable(&pdev->dev); 1425 if (!pm_runtime_enabled(&pdev->dev)) 1426 ret = tegra_dma_runtime_resume(&pdev->dev); 1427 else 1428 ret = pm_runtime_get_sync(&pdev->dev); 1429 1430 if (ret < 0) { 1431 pm_runtime_disable(&pdev->dev); 1432 return ret; 1433 } 1434 1435 /* Reset DMA controller */ 1436 reset_control_assert(tdma->rst); 1437 udelay(2); 1438 reset_control_deassert(tdma->rst); 1439 1440 /* Enable global DMA registers */ 1441 tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE); 1442 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0); 1443 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul); 1444 1445 pm_runtime_put(&pdev->dev); 1446 1447 INIT_LIST_HEAD(&tdma->dma_dev.channels); 1448 for (i = 0; i < cdata->nr_channels; i++) { 1449 struct tegra_dma_channel *tdc = &tdma->channels[i]; 1450 1451 tdc->chan_addr = tdma->base_addr + 1452 TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET + 1453 (i * cdata->channel_reg_size); 1454 1455 res = platform_get_resource(pdev, IORESOURCE_IRQ, i); 1456 if (!res) { 1457 ret = -EINVAL; 1458 dev_err(&pdev->dev, "No irq resource for chan %d\n", i); 1459 goto err_irq; 1460 } 1461 tdc->irq = res->start; 1462 snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i); 1463 ret = request_irq(tdc->irq, tegra_dma_isr, 0, tdc->name, tdc); 1464 if (ret) { 1465 dev_err(&pdev->dev, 1466 "request_irq failed with err %d channel %d\n", 1467 ret, i); 1468 goto err_irq; 1469 } 1470 1471 tdc->dma_chan.device = &tdma->dma_dev; 1472 dma_cookie_init(&tdc->dma_chan); 1473 list_add_tail(&tdc->dma_chan.device_node, 1474 &tdma->dma_dev.channels); 1475 tdc->tdma = tdma; 1476 tdc->id = i; 1477 tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID; 1478 1479 tasklet_init(&tdc->tasklet, tegra_dma_tasklet, 1480 (unsigned long)tdc); 1481 spin_lock_init(&tdc->lock); 1482 1483 INIT_LIST_HEAD(&tdc->pending_sg_req); 1484 INIT_LIST_HEAD(&tdc->free_sg_req); 1485 INIT_LIST_HEAD(&tdc->free_dma_desc); 1486 INIT_LIST_HEAD(&tdc->cb_desc); 1487 } 1488 1489 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask); 1490 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask); 1491 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask); 1492 1493 tdma->global_pause_count = 0; 1494 tdma->dma_dev.dev = &pdev->dev; 1495 tdma->dma_dev.device_alloc_chan_resources = 1496 tegra_dma_alloc_chan_resources; 1497 tdma->dma_dev.device_free_chan_resources = 1498 tegra_dma_free_chan_resources; 1499 tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg; 1500 tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic; 1501 tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1502 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1503 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | 1504 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 1505 tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1506 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1507 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | 1508 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 1509 tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 1510 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 1511 tdma->dma_dev.device_config = tegra_dma_slave_config; 1512 tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all; 1513 tdma->dma_dev.device_tx_status = tegra_dma_tx_status; 1514 tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending; 1515 1516 ret = dma_async_device_register(&tdma->dma_dev); 1517 if (ret < 0) { 1518 dev_err(&pdev->dev, 1519 "Tegra20 APB DMA driver registration failed %d\n", ret); 1520 goto err_irq; 1521 } 1522 1523 ret = of_dma_controller_register(pdev->dev.of_node, 1524 tegra_dma_of_xlate, tdma); 1525 if (ret < 0) { 1526 dev_err(&pdev->dev, 1527 "Tegra20 APB DMA OF registration failed %d\n", ret); 1528 goto err_unregister_dma_dev; 1529 } 1530 1531 dev_info(&pdev->dev, "Tegra20 APB DMA driver register %d channels\n", 1532 cdata->nr_channels); 1533 return 0; 1534 1535 err_unregister_dma_dev: 1536 dma_async_device_unregister(&tdma->dma_dev); 1537 err_irq: 1538 while (--i >= 0) { 1539 struct tegra_dma_channel *tdc = &tdma->channels[i]; 1540 1541 free_irq(tdc->irq, tdc); 1542 tasklet_kill(&tdc->tasklet); 1543 } 1544 1545 pm_runtime_disable(&pdev->dev); 1546 if (!pm_runtime_status_suspended(&pdev->dev)) 1547 tegra_dma_runtime_suspend(&pdev->dev); 1548 return ret; 1549 } 1550 1551 static int tegra_dma_remove(struct platform_device *pdev) 1552 { 1553 struct tegra_dma *tdma = platform_get_drvdata(pdev); 1554 int i; 1555 struct tegra_dma_channel *tdc; 1556 1557 dma_async_device_unregister(&tdma->dma_dev); 1558 1559 for (i = 0; i < tdma->chip_data->nr_channels; ++i) { 1560 tdc = &tdma->channels[i]; 1561 free_irq(tdc->irq, tdc); 1562 tasklet_kill(&tdc->tasklet); 1563 } 1564 1565 pm_runtime_disable(&pdev->dev); 1566 if (!pm_runtime_status_suspended(&pdev->dev)) 1567 tegra_dma_runtime_suspend(&pdev->dev); 1568 1569 return 0; 1570 } 1571 1572 static int tegra_dma_runtime_suspend(struct device *dev) 1573 { 1574 struct tegra_dma *tdma = dev_get_drvdata(dev); 1575 int i; 1576 1577 tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL); 1578 for (i = 0; i < tdma->chip_data->nr_channels; i++) { 1579 struct tegra_dma_channel *tdc = &tdma->channels[i]; 1580 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg; 1581 1582 /* Only save the state of DMA channels that are in use */ 1583 if (!tdc->config_init) 1584 continue; 1585 1586 ch_reg->csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR); 1587 ch_reg->ahb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR); 1588 ch_reg->apb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBPTR); 1589 ch_reg->ahb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBSEQ); 1590 ch_reg->apb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBSEQ); 1591 if (tdma->chip_data->support_separate_wcount_reg) 1592 ch_reg->wcount = tdc_read(tdc, 1593 TEGRA_APBDMA_CHAN_WCOUNT); 1594 } 1595 1596 clk_disable_unprepare(tdma->dma_clk); 1597 1598 return 0; 1599 } 1600 1601 static int tegra_dma_runtime_resume(struct device *dev) 1602 { 1603 struct tegra_dma *tdma = dev_get_drvdata(dev); 1604 int i, ret; 1605 1606 ret = clk_prepare_enable(tdma->dma_clk); 1607 if (ret < 0) { 1608 dev_err(dev, "clk_enable failed: %d\n", ret); 1609 return ret; 1610 } 1611 1612 tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen); 1613 tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0); 1614 tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul); 1615 1616 for (i = 0; i < tdma->chip_data->nr_channels; i++) { 1617 struct tegra_dma_channel *tdc = &tdma->channels[i]; 1618 struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg; 1619 1620 /* Only restore the state of DMA channels that are in use */ 1621 if (!tdc->config_init) 1622 continue; 1623 1624 if (tdma->chip_data->support_separate_wcount_reg) 1625 tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, 1626 ch_reg->wcount); 1627 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq); 1628 tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr); 1629 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq); 1630 tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr); 1631 tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, 1632 (ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB)); 1633 } 1634 1635 return 0; 1636 } 1637 1638 static const struct dev_pm_ops tegra_dma_dev_pm_ops = { 1639 SET_RUNTIME_PM_OPS(tegra_dma_runtime_suspend, tegra_dma_runtime_resume, 1640 NULL) 1641 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1642 pm_runtime_force_resume) 1643 }; 1644 1645 static const struct of_device_id tegra_dma_of_match[] = { 1646 { 1647 .compatible = "nvidia,tegra148-apbdma", 1648 .data = &tegra148_dma_chip_data, 1649 }, { 1650 .compatible = "nvidia,tegra114-apbdma", 1651 .data = &tegra114_dma_chip_data, 1652 }, { 1653 .compatible = "nvidia,tegra30-apbdma", 1654 .data = &tegra30_dma_chip_data, 1655 }, { 1656 .compatible = "nvidia,tegra20-apbdma", 1657 .data = &tegra20_dma_chip_data, 1658 }, { 1659 }, 1660 }; 1661 MODULE_DEVICE_TABLE(of, tegra_dma_of_match); 1662 1663 static struct platform_driver tegra_dmac_driver = { 1664 .driver = { 1665 .name = "tegra-apbdma", 1666 .pm = &tegra_dma_dev_pm_ops, 1667 .of_match_table = tegra_dma_of_match, 1668 }, 1669 .probe = tegra_dma_probe, 1670 .remove = tegra_dma_remove, 1671 }; 1672 1673 module_platform_driver(tegra_dmac_driver); 1674 1675 MODULE_ALIAS("platform:tegra20-apbdma"); 1676 MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver"); 1677 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); 1678 MODULE_LICENSE("GPL v2"); 1679