1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * DMA driver for NVIDIA Tegra GPC DMA controller. 4 * 5 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/dmaengine.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/interrupt.h> 12 #include <linux/iommu.h> 13 #include <linux/iopoll.h> 14 #include <linux/minmax.h> 15 #include <linux/module.h> 16 #include <linux/of_device.h> 17 #include <linux/of_dma.h> 18 #include <linux/platform_device.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 #include <dt-bindings/memory/tegra186-mc.h> 22 #include "virt-dma.h" 23 24 /* CSR register */ 25 #define TEGRA_GPCDMA_CHAN_CSR 0x00 26 #define TEGRA_GPCDMA_CSR_ENB BIT(31) 27 #define TEGRA_GPCDMA_CSR_IE_EOC BIT(30) 28 #define TEGRA_GPCDMA_CSR_ONCE BIT(27) 29 30 #define TEGRA_GPCDMA_CSR_FC_MODE GENMASK(25, 24) 31 #define TEGRA_GPCDMA_CSR_FC_MODE_NO_MMIO \ 32 FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 0) 33 #define TEGRA_GPCDMA_CSR_FC_MODE_ONE_MMIO \ 34 FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 1) 35 #define TEGRA_GPCDMA_CSR_FC_MODE_TWO_MMIO \ 36 FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 2) 37 #define TEGRA_GPCDMA_CSR_FC_MODE_FOUR_MMIO \ 38 FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 3) 39 40 #define TEGRA_GPCDMA_CSR_DMA GENMASK(23, 21) 41 #define TEGRA_GPCDMA_CSR_DMA_IO2MEM_NO_FC \ 42 FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 0) 43 #define TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC \ 44 FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 1) 45 #define TEGRA_GPCDMA_CSR_DMA_MEM2IO_NO_FC \ 46 FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 2) 47 #define TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC \ 48 FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 3) 49 #define TEGRA_GPCDMA_CSR_DMA_MEM2MEM \ 50 FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 4) 51 #define TEGRA_GPCDMA_CSR_DMA_FIXED_PAT \ 52 FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 6) 53 54 #define TEGRA_GPCDMA_CSR_REQ_SEL_MASK GENMASK(20, 16) 55 #define TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED \ 56 FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, 4) 57 #define TEGRA_GPCDMA_CSR_IRQ_MASK BIT(15) 58 #define TEGRA_GPCDMA_CSR_WEIGHT GENMASK(13, 10) 59 60 /* STATUS register */ 61 #define TEGRA_GPCDMA_CHAN_STATUS 0x004 62 #define TEGRA_GPCDMA_STATUS_BUSY BIT(31) 63 #define TEGRA_GPCDMA_STATUS_ISE_EOC BIT(30) 64 #define TEGRA_GPCDMA_STATUS_PING_PONG BIT(28) 65 #define TEGRA_GPCDMA_STATUS_DMA_ACTIVITY BIT(27) 66 #define TEGRA_GPCDMA_STATUS_CHANNEL_PAUSE BIT(26) 67 #define TEGRA_GPCDMA_STATUS_CHANNEL_RX BIT(25) 68 #define TEGRA_GPCDMA_STATUS_CHANNEL_TX BIT(24) 69 #define TEGRA_GPCDMA_STATUS_IRQ_INTR_STA BIT(23) 70 #define TEGRA_GPCDMA_STATUS_IRQ_STA BIT(21) 71 #define TEGRA_GPCDMA_STATUS_IRQ_TRIG_STA BIT(20) 72 73 #define TEGRA_GPCDMA_CHAN_CSRE 0x008 74 #define TEGRA_GPCDMA_CHAN_CSRE_PAUSE BIT(31) 75 76 /* Source address */ 77 #define TEGRA_GPCDMA_CHAN_SRC_PTR 0x00C 78 79 /* Destination address */ 80 #define TEGRA_GPCDMA_CHAN_DST_PTR 0x010 81 82 /* High address pointer */ 83 #define TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR 0x014 84 #define TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR GENMASK(7, 0) 85 #define TEGRA_GPCDMA_HIGH_ADDR_DST_PTR GENMASK(23, 16) 86 87 /* MC sequence register */ 88 #define TEGRA_GPCDMA_CHAN_MCSEQ 0x18 89 #define TEGRA_GPCDMA_MCSEQ_DATA_SWAP BIT(31) 90 #define TEGRA_GPCDMA_MCSEQ_REQ_COUNT GENMASK(30, 25) 91 #define TEGRA_GPCDMA_MCSEQ_BURST GENMASK(24, 23) 92 #define TEGRA_GPCDMA_MCSEQ_BURST_2 \ 93 FIELD_PREP(TEGRA_GPCDMA_MCSEQ_BURST, 0) 94 #define TEGRA_GPCDMA_MCSEQ_BURST_16 \ 95 FIELD_PREP(TEGRA_GPCDMA_MCSEQ_BURST, 3) 96 #define TEGRA_GPCDMA_MCSEQ_WRAP1 GENMASK(22, 20) 97 #define TEGRA_GPCDMA_MCSEQ_WRAP0 GENMASK(19, 17) 98 #define TEGRA_GPCDMA_MCSEQ_WRAP_NONE 0 99 100 #define TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK GENMASK(13, 7) 101 #define TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK GENMASK(6, 0) 102 103 /* MMIO sequence register */ 104 #define TEGRA_GPCDMA_CHAN_MMIOSEQ 0x01c 105 #define TEGRA_GPCDMA_MMIOSEQ_DBL_BUF BIT(31) 106 #define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH GENMASK(30, 28) 107 #define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8 \ 108 FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 0) 109 #define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16 \ 110 FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 1) 111 #define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32 \ 112 FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 2) 113 #define TEGRA_GPCDMA_MMIOSEQ_DATA_SWAP BIT(27) 114 #define TEGRA_GPCDMA_MMIOSEQ_BURST_SHIFT 23 115 #define TEGRA_GPCDMA_MMIOSEQ_BURST_MIN 2U 116 #define TEGRA_GPCDMA_MMIOSEQ_BURST_MAX 32U 117 #define TEGRA_GPCDMA_MMIOSEQ_BURST(bs) \ 118 (GENMASK((fls(bs) - 2), 0) << TEGRA_GPCDMA_MMIOSEQ_BURST_SHIFT) 119 #define TEGRA_GPCDMA_MMIOSEQ_MASTER_ID GENMASK(22, 19) 120 #define TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD GENMASK(18, 16) 121 #define TEGRA_GPCDMA_MMIOSEQ_MMIO_PROT GENMASK(8, 7) 122 123 /* Channel WCOUNT */ 124 #define TEGRA_GPCDMA_CHAN_WCOUNT 0x20 125 126 /* Transfer count */ 127 #define TEGRA_GPCDMA_CHAN_XFER_COUNT 0x24 128 129 /* DMA byte count status */ 130 #define TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS 0x28 131 132 /* Error Status Register */ 133 #define TEGRA_GPCDMA_CHAN_ERR_STATUS 0x30 134 #define TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT 8 135 #define TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK 0xF 136 #define TEGRA_GPCDMA_CHAN_ERR_TYPE(err) ( \ 137 ((err) >> TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT) & \ 138 TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK) 139 #define TEGRA_DMA_BM_FIFO_FULL_ERR 0xF 140 #define TEGRA_DMA_PERIPH_FIFO_FULL_ERR 0xE 141 #define TEGRA_DMA_PERIPH_ID_ERR 0xD 142 #define TEGRA_DMA_STREAM_ID_ERR 0xC 143 #define TEGRA_DMA_MC_SLAVE_ERR 0xB 144 #define TEGRA_DMA_MMIO_SLAVE_ERR 0xA 145 146 /* Fixed Pattern */ 147 #define TEGRA_GPCDMA_CHAN_FIXED_PATTERN 0x34 148 149 #define TEGRA_GPCDMA_CHAN_TZ 0x38 150 #define TEGRA_GPCDMA_CHAN_TZ_MMIO_PROT_1 BIT(0) 151 #define TEGRA_GPCDMA_CHAN_TZ_MC_PROT_1 BIT(1) 152 153 #define TEGRA_GPCDMA_CHAN_SPARE 0x3c 154 #define TEGRA_GPCDMA_CHAN_SPARE_EN_LEGACY_FC BIT(16) 155 156 /* 157 * If any burst is in flight and DMA paused then this is the time to complete 158 * on-flight burst and update DMA status register. 159 */ 160 #define TEGRA_GPCDMA_BURST_COMPLETE_TIME 20 161 #define TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT 100 162 163 /* Channel base address offset from GPCDMA base address */ 164 #define TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET 0x20000 165 166 struct tegra_dma; 167 struct tegra_dma_channel; 168 169 /* 170 * tegra_dma_chip_data Tegra chip specific DMA data 171 * @nr_channels: Number of channels available in the controller. 172 * @channel_reg_size: Channel register size. 173 * @max_dma_count: Maximum DMA transfer count supported by DMA controller. 174 * @hw_support_pause: DMA HW engine support pause of the channel. 175 */ 176 struct tegra_dma_chip_data { 177 bool hw_support_pause; 178 unsigned int nr_channels; 179 unsigned int channel_reg_size; 180 unsigned int max_dma_count; 181 int (*terminate)(struct tegra_dma_channel *tdc); 182 }; 183 184 /* DMA channel registers */ 185 struct tegra_dma_channel_regs { 186 u32 csr; 187 u32 src_ptr; 188 u32 dst_ptr; 189 u32 high_addr_ptr; 190 u32 mc_seq; 191 u32 mmio_seq; 192 u32 wcount; 193 u32 fixed_pattern; 194 }; 195 196 /* 197 * tegra_dma_sg_req: DMA request details to configure hardware. This 198 * contains the details for one transfer to configure DMA hw. 199 * The client's request for data transfer can be broken into multiple 200 * sub-transfer as per requester details and hw support. This sub transfer 201 * get added as an array in Tegra DMA desc which manages the transfer details. 202 */ 203 struct tegra_dma_sg_req { 204 unsigned int len; 205 struct tegra_dma_channel_regs ch_regs; 206 }; 207 208 /* 209 * tegra_dma_desc: Tegra DMA descriptors which uses virt_dma_desc to 210 * manage client request and keep track of transfer status, callbacks 211 * and request counts etc. 212 */ 213 struct tegra_dma_desc { 214 bool cyclic; 215 unsigned int bytes_req; 216 unsigned int bytes_xfer; 217 unsigned int sg_idx; 218 unsigned int sg_count; 219 struct virt_dma_desc vd; 220 struct tegra_dma_channel *tdc; 221 struct tegra_dma_sg_req sg_req[]; 222 }; 223 224 /* 225 * tegra_dma_channel: Channel specific information 226 */ 227 struct tegra_dma_channel { 228 bool config_init; 229 char name[30]; 230 enum dma_transfer_direction sid_dir; 231 int id; 232 int irq; 233 int slave_id; 234 struct tegra_dma *tdma; 235 struct virt_dma_chan vc; 236 struct tegra_dma_desc *dma_desc; 237 struct dma_slave_config dma_sconfig; 238 unsigned int stream_id; 239 unsigned long chan_base_offset; 240 }; 241 242 /* 243 * tegra_dma: Tegra DMA specific information 244 */ 245 struct tegra_dma { 246 const struct tegra_dma_chip_data *chip_data; 247 unsigned long sid_m2d_reserved; 248 unsigned long sid_d2m_reserved; 249 void __iomem *base_addr; 250 struct device *dev; 251 struct dma_device dma_dev; 252 struct reset_control *rst; 253 struct tegra_dma_channel channels[]; 254 }; 255 256 static inline void tdc_write(struct tegra_dma_channel *tdc, 257 u32 reg, u32 val) 258 { 259 writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg); 260 } 261 262 static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg) 263 { 264 return readl_relaxed(tdc->tdma->base_addr + tdc->chan_base_offset + reg); 265 } 266 267 static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc) 268 { 269 return container_of(dc, struct tegra_dma_channel, vc.chan); 270 } 271 272 static inline struct tegra_dma_desc *vd_to_tegra_dma_desc(struct virt_dma_desc *vd) 273 { 274 return container_of(vd, struct tegra_dma_desc, vd); 275 } 276 277 static inline struct device *tdc2dev(struct tegra_dma_channel *tdc) 278 { 279 return tdc->vc.chan.device->dev; 280 } 281 282 static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc) 283 { 284 dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n", 285 tdc->id, tdc->name); 286 dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x SRC %x DST %x\n", 287 tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR), 288 tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS), 289 tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE), 290 tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR), 291 tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR) 292 ); 293 dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x BSTA %x\n", 294 tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ), 295 tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ), 296 tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT), 297 tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT), 298 tdc_read(tdc, TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS) 299 ); 300 dev_dbg(tdc2dev(tdc), "DMA ERR_STA %x\n", 301 tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS)); 302 } 303 304 static int tegra_dma_sid_reserve(struct tegra_dma_channel *tdc, 305 enum dma_transfer_direction direction) 306 { 307 struct tegra_dma *tdma = tdc->tdma; 308 int sid = tdc->slave_id; 309 310 if (!is_slave_direction(direction)) 311 return 0; 312 313 switch (direction) { 314 case DMA_MEM_TO_DEV: 315 if (test_and_set_bit(sid, &tdma->sid_m2d_reserved)) { 316 dev_err(tdma->dev, "slave id already in use\n"); 317 return -EINVAL; 318 } 319 break; 320 case DMA_DEV_TO_MEM: 321 if (test_and_set_bit(sid, &tdma->sid_d2m_reserved)) { 322 dev_err(tdma->dev, "slave id already in use\n"); 323 return -EINVAL; 324 } 325 break; 326 default: 327 break; 328 } 329 330 tdc->sid_dir = direction; 331 332 return 0; 333 } 334 335 static void tegra_dma_sid_free(struct tegra_dma_channel *tdc) 336 { 337 struct tegra_dma *tdma = tdc->tdma; 338 int sid = tdc->slave_id; 339 340 switch (tdc->sid_dir) { 341 case DMA_MEM_TO_DEV: 342 clear_bit(sid, &tdma->sid_m2d_reserved); 343 break; 344 case DMA_DEV_TO_MEM: 345 clear_bit(sid, &tdma->sid_d2m_reserved); 346 break; 347 default: 348 break; 349 } 350 351 tdc->sid_dir = DMA_TRANS_NONE; 352 } 353 354 static void tegra_dma_desc_free(struct virt_dma_desc *vd) 355 { 356 kfree(container_of(vd, struct tegra_dma_desc, vd)); 357 } 358 359 static int tegra_dma_slave_config(struct dma_chan *dc, 360 struct dma_slave_config *sconfig) 361 { 362 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 363 364 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig)); 365 tdc->config_init = true; 366 367 return 0; 368 } 369 370 static int tegra_dma_pause(struct tegra_dma_channel *tdc) 371 { 372 int ret; 373 u32 val; 374 375 val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE); 376 val |= TEGRA_GPCDMA_CHAN_CSRE_PAUSE; 377 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val); 378 379 /* Wait until busy bit is de-asserted */ 380 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + 381 tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, 382 val, 383 !(val & TEGRA_GPCDMA_STATUS_BUSY), 384 TEGRA_GPCDMA_BURST_COMPLETE_TIME, 385 TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT); 386 387 if (ret) { 388 dev_err(tdc2dev(tdc), "DMA pause timed out\n"); 389 tegra_dma_dump_chan_regs(tdc); 390 } 391 392 return ret; 393 } 394 395 static int tegra_dma_device_pause(struct dma_chan *dc) 396 { 397 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 398 unsigned long flags; 399 int ret; 400 401 if (!tdc->tdma->chip_data->hw_support_pause) 402 return -ENOSYS; 403 404 spin_lock_irqsave(&tdc->vc.lock, flags); 405 ret = tegra_dma_pause(tdc); 406 spin_unlock_irqrestore(&tdc->vc.lock, flags); 407 408 return ret; 409 } 410 411 static void tegra_dma_resume(struct tegra_dma_channel *tdc) 412 { 413 u32 val; 414 415 val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE); 416 val &= ~TEGRA_GPCDMA_CHAN_CSRE_PAUSE; 417 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val); 418 } 419 420 static int tegra_dma_device_resume(struct dma_chan *dc) 421 { 422 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 423 unsigned long flags; 424 425 if (!tdc->tdma->chip_data->hw_support_pause) 426 return -ENOSYS; 427 428 spin_lock_irqsave(&tdc->vc.lock, flags); 429 tegra_dma_resume(tdc); 430 spin_unlock_irqrestore(&tdc->vc.lock, flags); 431 432 return 0; 433 } 434 435 static void tegra_dma_disable(struct tegra_dma_channel *tdc) 436 { 437 u32 csr, status; 438 439 csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR); 440 441 /* Disable interrupts */ 442 csr &= ~TEGRA_GPCDMA_CSR_IE_EOC; 443 444 /* Disable DMA */ 445 csr &= ~TEGRA_GPCDMA_CSR_ENB; 446 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr); 447 448 /* Clear interrupt status if it is there */ 449 status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS); 450 if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) { 451 dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__); 452 tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, status); 453 } 454 } 455 456 static void tegra_dma_configure_next_sg(struct tegra_dma_channel *tdc) 457 { 458 struct tegra_dma_desc *dma_desc = tdc->dma_desc; 459 struct tegra_dma_channel_regs *ch_regs; 460 int ret; 461 u32 val; 462 463 dma_desc->sg_idx++; 464 465 /* Reset the sg index for cyclic transfers */ 466 if (dma_desc->sg_idx == dma_desc->sg_count) 467 dma_desc->sg_idx = 0; 468 469 /* Configure next transfer immediately after DMA is busy */ 470 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + 471 tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, 472 val, 473 (val & TEGRA_GPCDMA_STATUS_BUSY), 0, 474 TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT); 475 if (ret) 476 return; 477 478 ch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs; 479 480 tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount); 481 tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr); 482 tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr); 483 tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr); 484 485 /* Start DMA */ 486 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 487 ch_regs->csr | TEGRA_GPCDMA_CSR_ENB); 488 } 489 490 static void tegra_dma_start(struct tegra_dma_channel *tdc) 491 { 492 struct tegra_dma_desc *dma_desc = tdc->dma_desc; 493 struct tegra_dma_channel_regs *ch_regs; 494 struct virt_dma_desc *vdesc; 495 496 if (!dma_desc) { 497 vdesc = vchan_next_desc(&tdc->vc); 498 if (!vdesc) 499 return; 500 501 dma_desc = vd_to_tegra_dma_desc(vdesc); 502 list_del(&vdesc->node); 503 dma_desc->tdc = tdc; 504 tdc->dma_desc = dma_desc; 505 506 tegra_dma_resume(tdc); 507 } 508 509 ch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs; 510 511 tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount); 512 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 0); 513 tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr); 514 tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr); 515 tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr); 516 tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern); 517 tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq); 518 tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq); 519 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr); 520 521 /* Start DMA */ 522 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 523 ch_regs->csr | TEGRA_GPCDMA_CSR_ENB); 524 } 525 526 static void tegra_dma_xfer_complete(struct tegra_dma_channel *tdc) 527 { 528 vchan_cookie_complete(&tdc->dma_desc->vd); 529 530 tegra_dma_sid_free(tdc); 531 tdc->dma_desc = NULL; 532 } 533 534 static void tegra_dma_chan_decode_error(struct tegra_dma_channel *tdc, 535 unsigned int err_status) 536 { 537 switch (TEGRA_GPCDMA_CHAN_ERR_TYPE(err_status)) { 538 case TEGRA_DMA_BM_FIFO_FULL_ERR: 539 dev_err(tdc->tdma->dev, 540 "GPCDMA CH%d bm fifo full\n", tdc->id); 541 break; 542 543 case TEGRA_DMA_PERIPH_FIFO_FULL_ERR: 544 dev_err(tdc->tdma->dev, 545 "GPCDMA CH%d peripheral fifo full\n", tdc->id); 546 break; 547 548 case TEGRA_DMA_PERIPH_ID_ERR: 549 dev_err(tdc->tdma->dev, 550 "GPCDMA CH%d illegal peripheral id\n", tdc->id); 551 break; 552 553 case TEGRA_DMA_STREAM_ID_ERR: 554 dev_err(tdc->tdma->dev, 555 "GPCDMA CH%d illegal stream id\n", tdc->id); 556 break; 557 558 case TEGRA_DMA_MC_SLAVE_ERR: 559 dev_err(tdc->tdma->dev, 560 "GPCDMA CH%d mc slave error\n", tdc->id); 561 break; 562 563 case TEGRA_DMA_MMIO_SLAVE_ERR: 564 dev_err(tdc->tdma->dev, 565 "GPCDMA CH%d mmio slave error\n", tdc->id); 566 break; 567 568 default: 569 dev_err(tdc->tdma->dev, 570 "GPCDMA CH%d security violation %x\n", tdc->id, 571 err_status); 572 } 573 } 574 575 static irqreturn_t tegra_dma_isr(int irq, void *dev_id) 576 { 577 struct tegra_dma_channel *tdc = dev_id; 578 struct tegra_dma_desc *dma_desc = tdc->dma_desc; 579 struct tegra_dma_sg_req *sg_req; 580 u32 status; 581 582 /* Check channel error status register */ 583 status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS); 584 if (status) { 585 tegra_dma_chan_decode_error(tdc, status); 586 tegra_dma_dump_chan_regs(tdc); 587 tdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF); 588 } 589 590 spin_lock(&tdc->vc.lock); 591 status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS); 592 if (!(status & TEGRA_GPCDMA_STATUS_ISE_EOC)) 593 goto irq_done; 594 595 tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, 596 TEGRA_GPCDMA_STATUS_ISE_EOC); 597 598 if (!dma_desc) 599 goto irq_done; 600 601 sg_req = dma_desc->sg_req; 602 dma_desc->bytes_xfer += sg_req[dma_desc->sg_idx].len; 603 604 if (dma_desc->cyclic) { 605 vchan_cyclic_callback(&dma_desc->vd); 606 tegra_dma_configure_next_sg(tdc); 607 } else { 608 dma_desc->sg_idx++; 609 if (dma_desc->sg_idx == dma_desc->sg_count) 610 tegra_dma_xfer_complete(tdc); 611 else 612 tegra_dma_start(tdc); 613 } 614 615 irq_done: 616 spin_unlock(&tdc->vc.lock); 617 return IRQ_HANDLED; 618 } 619 620 static void tegra_dma_issue_pending(struct dma_chan *dc) 621 { 622 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 623 unsigned long flags; 624 625 if (tdc->dma_desc) 626 return; 627 628 spin_lock_irqsave(&tdc->vc.lock, flags); 629 if (vchan_issue_pending(&tdc->vc)) 630 tegra_dma_start(tdc); 631 632 /* 633 * For cyclic DMA transfers, program the second 634 * transfer parameters as soon as the first DMA 635 * transfer is started inorder for the DMA 636 * controller to trigger the second transfer 637 * with the correct parameters. 638 */ 639 if (tdc->dma_desc && tdc->dma_desc->cyclic) 640 tegra_dma_configure_next_sg(tdc); 641 642 spin_unlock_irqrestore(&tdc->vc.lock, flags); 643 } 644 645 static int tegra_dma_stop_client(struct tegra_dma_channel *tdc) 646 { 647 int ret; 648 u32 status, csr; 649 650 /* 651 * Change the client associated with the DMA channel 652 * to stop DMA engine from starting any more bursts for 653 * the given client and wait for in flight bursts to complete 654 */ 655 csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR); 656 csr &= ~(TEGRA_GPCDMA_CSR_REQ_SEL_MASK); 657 csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED; 658 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr); 659 660 /* Wait for in flight data transfer to finish */ 661 udelay(TEGRA_GPCDMA_BURST_COMPLETE_TIME); 662 663 /* If TX/RX path is still active wait till it becomes 664 * inactive 665 */ 666 667 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + 668 tdc->chan_base_offset + 669 TEGRA_GPCDMA_CHAN_STATUS, 670 status, 671 !(status & (TEGRA_GPCDMA_STATUS_CHANNEL_TX | 672 TEGRA_GPCDMA_STATUS_CHANNEL_RX)), 673 5, 674 TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT); 675 if (ret) { 676 dev_err(tdc2dev(tdc), "Timeout waiting for DMA burst completion!\n"); 677 tegra_dma_dump_chan_regs(tdc); 678 } 679 680 return ret; 681 } 682 683 static int tegra_dma_terminate_all(struct dma_chan *dc) 684 { 685 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 686 unsigned long flags; 687 LIST_HEAD(head); 688 int err; 689 690 spin_lock_irqsave(&tdc->vc.lock, flags); 691 692 if (tdc->dma_desc) { 693 err = tdc->tdma->chip_data->terminate(tdc); 694 if (err) { 695 spin_unlock_irqrestore(&tdc->vc.lock, flags); 696 return err; 697 } 698 699 tegra_dma_disable(tdc); 700 tdc->dma_desc = NULL; 701 } 702 703 tegra_dma_sid_free(tdc); 704 vchan_get_all_descriptors(&tdc->vc, &head); 705 spin_unlock_irqrestore(&tdc->vc.lock, flags); 706 707 vchan_dma_desc_free_list(&tdc->vc, &head); 708 709 return 0; 710 } 711 712 static int tegra_dma_get_residual(struct tegra_dma_channel *tdc) 713 { 714 struct tegra_dma_desc *dma_desc = tdc->dma_desc; 715 struct tegra_dma_sg_req *sg_req = dma_desc->sg_req; 716 unsigned int bytes_xfer, residual; 717 u32 wcount = 0, status; 718 719 wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT); 720 721 /* 722 * Set wcount = 0 if EOC bit is set. The transfer would have 723 * already completed and the CHAN_XFER_COUNT could have updated 724 * for the next transfer, specifically in case of cyclic transfers. 725 */ 726 status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS); 727 if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) 728 wcount = 0; 729 730 bytes_xfer = dma_desc->bytes_xfer + 731 sg_req[dma_desc->sg_idx].len - (wcount * 4); 732 733 residual = dma_desc->bytes_req - (bytes_xfer % dma_desc->bytes_req); 734 735 return residual; 736 } 737 738 static enum dma_status tegra_dma_tx_status(struct dma_chan *dc, 739 dma_cookie_t cookie, 740 struct dma_tx_state *txstate) 741 { 742 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 743 struct tegra_dma_desc *dma_desc; 744 struct virt_dma_desc *vd; 745 unsigned int residual; 746 unsigned long flags; 747 enum dma_status ret; 748 749 ret = dma_cookie_status(dc, cookie, txstate); 750 if (ret == DMA_COMPLETE) 751 return ret; 752 753 spin_lock_irqsave(&tdc->vc.lock, flags); 754 vd = vchan_find_desc(&tdc->vc, cookie); 755 if (vd) { 756 dma_desc = vd_to_tegra_dma_desc(vd); 757 residual = dma_desc->bytes_req; 758 dma_set_residue(txstate, residual); 759 } else if (tdc->dma_desc && tdc->dma_desc->vd.tx.cookie == cookie) { 760 residual = tegra_dma_get_residual(tdc); 761 dma_set_residue(txstate, residual); 762 } else { 763 dev_err(tdc2dev(tdc), "cookie %d is not found\n", cookie); 764 } 765 spin_unlock_irqrestore(&tdc->vc.lock, flags); 766 767 return ret; 768 } 769 770 static inline int get_bus_width(struct tegra_dma_channel *tdc, 771 enum dma_slave_buswidth slave_bw) 772 { 773 switch (slave_bw) { 774 case DMA_SLAVE_BUSWIDTH_1_BYTE: 775 return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8; 776 case DMA_SLAVE_BUSWIDTH_2_BYTES: 777 return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16; 778 case DMA_SLAVE_BUSWIDTH_4_BYTES: 779 return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32; 780 default: 781 dev_err(tdc2dev(tdc), "given slave bus width is not supported\n"); 782 return -EINVAL; 783 } 784 } 785 786 static unsigned int get_burst_size(struct tegra_dma_channel *tdc, 787 u32 burst_size, enum dma_slave_buswidth slave_bw, 788 int len) 789 { 790 unsigned int burst_mmio_width, burst_byte; 791 792 /* 793 * burst_size from client is in terms of the bus_width. 794 * convert that into words. 795 * If burst_size is not specified from client, then use 796 * len to calculate the optimum burst size 797 */ 798 burst_byte = burst_size ? burst_size * slave_bw : len; 799 burst_mmio_width = burst_byte / 4; 800 801 if (burst_mmio_width < TEGRA_GPCDMA_MMIOSEQ_BURST_MIN) 802 return 0; 803 804 burst_mmio_width = min(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MAX); 805 806 return TEGRA_GPCDMA_MMIOSEQ_BURST(burst_mmio_width); 807 } 808 809 static int get_transfer_param(struct tegra_dma_channel *tdc, 810 enum dma_transfer_direction direction, 811 u32 *apb_addr, 812 u32 *mmio_seq, 813 u32 *csr, 814 unsigned int *burst_size, 815 enum dma_slave_buswidth *slave_bw) 816 { 817 switch (direction) { 818 case DMA_MEM_TO_DEV: 819 *apb_addr = tdc->dma_sconfig.dst_addr; 820 *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width); 821 *burst_size = tdc->dma_sconfig.dst_maxburst; 822 *slave_bw = tdc->dma_sconfig.dst_addr_width; 823 *csr = TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC; 824 return 0; 825 case DMA_DEV_TO_MEM: 826 *apb_addr = tdc->dma_sconfig.src_addr; 827 *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width); 828 *burst_size = tdc->dma_sconfig.src_maxburst; 829 *slave_bw = tdc->dma_sconfig.src_addr_width; 830 *csr = TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC; 831 return 0; 832 default: 833 dev_err(tdc2dev(tdc), "DMA direction is not supported\n"); 834 } 835 836 return -EINVAL; 837 } 838 839 static struct dma_async_tx_descriptor * 840 tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value, 841 size_t len, unsigned long flags) 842 { 843 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 844 unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count; 845 struct tegra_dma_sg_req *sg_req; 846 struct tegra_dma_desc *dma_desc; 847 u32 csr, mc_seq; 848 849 if ((len & 3) || (dest & 3) || len > max_dma_count) { 850 dev_err(tdc2dev(tdc), 851 "DMA length/memory address is not supported\n"); 852 return NULL; 853 } 854 855 /* Set DMA mode to fixed pattern */ 856 csr = TEGRA_GPCDMA_CSR_DMA_FIXED_PAT; 857 /* Enable once or continuous mode */ 858 csr |= TEGRA_GPCDMA_CSR_ONCE; 859 /* Enable IRQ mask */ 860 csr |= TEGRA_GPCDMA_CSR_IRQ_MASK; 861 /* Enable the DMA interrupt */ 862 if (flags & DMA_PREP_INTERRUPT) 863 csr |= TEGRA_GPCDMA_CSR_IE_EOC; 864 /* Configure default priority weight for the channel */ 865 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1); 866 867 mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); 868 /* retain stream-id and clean rest */ 869 mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK; 870 871 /* Set the address wrapping */ 872 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0, 873 TEGRA_GPCDMA_MCSEQ_WRAP_NONE); 874 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1, 875 TEGRA_GPCDMA_MCSEQ_WRAP_NONE); 876 877 /* Program outstanding MC requests */ 878 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1); 879 /* Set burst size */ 880 mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16; 881 882 dma_desc = kzalloc(struct_size(dma_desc, sg_req, 1), GFP_NOWAIT); 883 if (!dma_desc) 884 return NULL; 885 886 dma_desc->bytes_req = len; 887 dma_desc->sg_count = 1; 888 sg_req = dma_desc->sg_req; 889 890 sg_req[0].ch_regs.src_ptr = 0; 891 sg_req[0].ch_regs.dst_ptr = dest; 892 sg_req[0].ch_regs.high_addr_ptr = 893 FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32)); 894 sg_req[0].ch_regs.fixed_pattern = value; 895 /* Word count reg takes value as (N +1) words */ 896 sg_req[0].ch_regs.wcount = ((len - 4) >> 2); 897 sg_req[0].ch_regs.csr = csr; 898 sg_req[0].ch_regs.mmio_seq = 0; 899 sg_req[0].ch_regs.mc_seq = mc_seq; 900 sg_req[0].len = len; 901 902 dma_desc->cyclic = false; 903 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); 904 } 905 906 static struct dma_async_tx_descriptor * 907 tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest, 908 dma_addr_t src, size_t len, unsigned long flags) 909 { 910 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 911 struct tegra_dma_sg_req *sg_req; 912 struct tegra_dma_desc *dma_desc; 913 unsigned int max_dma_count; 914 u32 csr, mc_seq; 915 916 max_dma_count = tdc->tdma->chip_data->max_dma_count; 917 if ((len & 3) || (src & 3) || (dest & 3) || len > max_dma_count) { 918 dev_err(tdc2dev(tdc), 919 "DMA length/memory address is not supported\n"); 920 return NULL; 921 } 922 923 /* Set DMA mode to memory to memory transfer */ 924 csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM; 925 /* Enable once or continuous mode */ 926 csr |= TEGRA_GPCDMA_CSR_ONCE; 927 /* Enable IRQ mask */ 928 csr |= TEGRA_GPCDMA_CSR_IRQ_MASK; 929 /* Enable the DMA interrupt */ 930 if (flags & DMA_PREP_INTERRUPT) 931 csr |= TEGRA_GPCDMA_CSR_IE_EOC; 932 /* Configure default priority weight for the channel */ 933 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1); 934 935 mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); 936 /* retain stream-id and clean rest */ 937 mc_seq &= (TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK) | 938 (TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK); 939 940 /* Set the address wrapping */ 941 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0, 942 TEGRA_GPCDMA_MCSEQ_WRAP_NONE); 943 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1, 944 TEGRA_GPCDMA_MCSEQ_WRAP_NONE); 945 946 /* Program outstanding MC requests */ 947 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1); 948 /* Set burst size */ 949 mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16; 950 951 dma_desc = kzalloc(struct_size(dma_desc, sg_req, 1), GFP_NOWAIT); 952 if (!dma_desc) 953 return NULL; 954 955 dma_desc->bytes_req = len; 956 dma_desc->sg_count = 1; 957 sg_req = dma_desc->sg_req; 958 959 sg_req[0].ch_regs.src_ptr = src; 960 sg_req[0].ch_regs.dst_ptr = dest; 961 sg_req[0].ch_regs.high_addr_ptr = 962 FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32)); 963 sg_req[0].ch_regs.high_addr_ptr |= 964 FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32)); 965 /* Word count reg takes value as (N +1) words */ 966 sg_req[0].ch_regs.wcount = ((len - 4) >> 2); 967 sg_req[0].ch_regs.csr = csr; 968 sg_req[0].ch_regs.mmio_seq = 0; 969 sg_req[0].ch_regs.mc_seq = mc_seq; 970 sg_req[0].len = len; 971 972 dma_desc->cyclic = false; 973 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); 974 } 975 976 static struct dma_async_tx_descriptor * 977 tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl, 978 unsigned int sg_len, enum dma_transfer_direction direction, 979 unsigned long flags, void *context) 980 { 981 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 982 unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count; 983 enum dma_slave_buswidth slave_bw = DMA_SLAVE_BUSWIDTH_UNDEFINED; 984 u32 csr, mc_seq, apb_ptr = 0, mmio_seq = 0; 985 struct tegra_dma_sg_req *sg_req; 986 struct tegra_dma_desc *dma_desc; 987 struct scatterlist *sg; 988 u32 burst_size; 989 unsigned int i; 990 int ret; 991 992 if (!tdc->config_init) { 993 dev_err(tdc2dev(tdc), "DMA channel is not configured\n"); 994 return NULL; 995 } 996 if (sg_len < 1) { 997 dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len); 998 return NULL; 999 } 1000 1001 ret = tegra_dma_sid_reserve(tdc, direction); 1002 if (ret) 1003 return NULL; 1004 1005 ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr, 1006 &burst_size, &slave_bw); 1007 if (ret < 0) 1008 return NULL; 1009 1010 /* Enable once or continuous mode */ 1011 csr |= TEGRA_GPCDMA_CSR_ONCE; 1012 /* Program the slave id in requestor select */ 1013 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id); 1014 /* Enable IRQ mask */ 1015 csr |= TEGRA_GPCDMA_CSR_IRQ_MASK; 1016 /* Configure default priority weight for the channel*/ 1017 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1); 1018 1019 /* Enable the DMA interrupt */ 1020 if (flags & DMA_PREP_INTERRUPT) 1021 csr |= TEGRA_GPCDMA_CSR_IE_EOC; 1022 1023 mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); 1024 /* retain stream-id and clean rest */ 1025 mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK; 1026 1027 /* Set the address wrapping on both MC and MMIO side */ 1028 1029 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0, 1030 TEGRA_GPCDMA_MCSEQ_WRAP_NONE); 1031 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1, 1032 TEGRA_GPCDMA_MCSEQ_WRAP_NONE); 1033 mmio_seq |= FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD, 1); 1034 1035 /* Program 2 MC outstanding requests by default. */ 1036 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1); 1037 1038 /* Setting MC burst size depending on MMIO burst size */ 1039 if (burst_size == 64) 1040 mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16; 1041 else 1042 mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_2; 1043 1044 dma_desc = kzalloc(struct_size(dma_desc, sg_req, sg_len), GFP_NOWAIT); 1045 if (!dma_desc) 1046 return NULL; 1047 1048 dma_desc->sg_count = sg_len; 1049 sg_req = dma_desc->sg_req; 1050 1051 /* Make transfer requests */ 1052 for_each_sg(sgl, sg, sg_len, i) { 1053 u32 len; 1054 dma_addr_t mem; 1055 1056 mem = sg_dma_address(sg); 1057 len = sg_dma_len(sg); 1058 1059 if ((len & 3) || (mem & 3) || len > max_dma_count) { 1060 dev_err(tdc2dev(tdc), 1061 "DMA length/memory address is not supported\n"); 1062 kfree(dma_desc); 1063 return NULL; 1064 } 1065 1066 mmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len); 1067 dma_desc->bytes_req += len; 1068 1069 if (direction == DMA_MEM_TO_DEV) { 1070 sg_req[i].ch_regs.src_ptr = mem; 1071 sg_req[i].ch_regs.dst_ptr = apb_ptr; 1072 sg_req[i].ch_regs.high_addr_ptr = 1073 FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32)); 1074 } else if (direction == DMA_DEV_TO_MEM) { 1075 sg_req[i].ch_regs.src_ptr = apb_ptr; 1076 sg_req[i].ch_regs.dst_ptr = mem; 1077 sg_req[i].ch_regs.high_addr_ptr = 1078 FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32)); 1079 } 1080 1081 /* 1082 * Word count register takes input in words. Writing a value 1083 * of N into word count register means a req of (N+1) words. 1084 */ 1085 sg_req[i].ch_regs.wcount = ((len - 4) >> 2); 1086 sg_req[i].ch_regs.csr = csr; 1087 sg_req[i].ch_regs.mmio_seq = mmio_seq; 1088 sg_req[i].ch_regs.mc_seq = mc_seq; 1089 sg_req[i].len = len; 1090 } 1091 1092 dma_desc->cyclic = false; 1093 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); 1094 } 1095 1096 static struct dma_async_tx_descriptor * 1097 tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len, 1098 size_t period_len, enum dma_transfer_direction direction, 1099 unsigned long flags) 1100 { 1101 enum dma_slave_buswidth slave_bw = DMA_SLAVE_BUSWIDTH_UNDEFINED; 1102 u32 csr, mc_seq, apb_ptr = 0, mmio_seq = 0, burst_size; 1103 unsigned int max_dma_count, len, period_count, i; 1104 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 1105 struct tegra_dma_desc *dma_desc; 1106 struct tegra_dma_sg_req *sg_req; 1107 dma_addr_t mem = buf_addr; 1108 int ret; 1109 1110 if (!buf_len || !period_len) { 1111 dev_err(tdc2dev(tdc), "Invalid buffer/period len\n"); 1112 return NULL; 1113 } 1114 1115 if (!tdc->config_init) { 1116 dev_err(tdc2dev(tdc), "DMA slave is not configured\n"); 1117 return NULL; 1118 } 1119 1120 ret = tegra_dma_sid_reserve(tdc, direction); 1121 if (ret) 1122 return NULL; 1123 1124 /* 1125 * We only support cycle transfer when buf_len is multiple of 1126 * period_len. 1127 */ 1128 if (buf_len % period_len) { 1129 dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n"); 1130 return NULL; 1131 } 1132 1133 len = period_len; 1134 max_dma_count = tdc->tdma->chip_data->max_dma_count; 1135 if ((len & 3) || (buf_addr & 3) || len > max_dma_count) { 1136 dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n"); 1137 return NULL; 1138 } 1139 1140 ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr, 1141 &burst_size, &slave_bw); 1142 if (ret < 0) 1143 return NULL; 1144 1145 /* Enable once or continuous mode */ 1146 csr &= ~TEGRA_GPCDMA_CSR_ONCE; 1147 /* Program the slave id in requestor select */ 1148 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id); 1149 /* Enable IRQ mask */ 1150 csr |= TEGRA_GPCDMA_CSR_IRQ_MASK; 1151 /* Configure default priority weight for the channel*/ 1152 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1); 1153 1154 /* Enable the DMA interrupt */ 1155 if (flags & DMA_PREP_INTERRUPT) 1156 csr |= TEGRA_GPCDMA_CSR_IE_EOC; 1157 1158 mmio_seq |= FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD, 1); 1159 1160 mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); 1161 /* retain stream-id and clean rest */ 1162 mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK; 1163 1164 /* Set the address wrapping on both MC and MMIO side */ 1165 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0, 1166 TEGRA_GPCDMA_MCSEQ_WRAP_NONE); 1167 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1, 1168 TEGRA_GPCDMA_MCSEQ_WRAP_NONE); 1169 1170 /* Program 2 MC outstanding requests by default. */ 1171 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1); 1172 /* Setting MC burst size depending on MMIO burst size */ 1173 if (burst_size == 64) 1174 mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16; 1175 else 1176 mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_2; 1177 1178 period_count = buf_len / period_len; 1179 dma_desc = kzalloc(struct_size(dma_desc, sg_req, period_count), 1180 GFP_NOWAIT); 1181 if (!dma_desc) 1182 return NULL; 1183 1184 dma_desc->bytes_req = buf_len; 1185 dma_desc->sg_count = period_count; 1186 sg_req = dma_desc->sg_req; 1187 1188 /* Split transfer equal to period size */ 1189 for (i = 0; i < period_count; i++) { 1190 mmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len); 1191 if (direction == DMA_MEM_TO_DEV) { 1192 sg_req[i].ch_regs.src_ptr = mem; 1193 sg_req[i].ch_regs.dst_ptr = apb_ptr; 1194 sg_req[i].ch_regs.high_addr_ptr = 1195 FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32)); 1196 } else if (direction == DMA_DEV_TO_MEM) { 1197 sg_req[i].ch_regs.src_ptr = apb_ptr; 1198 sg_req[i].ch_regs.dst_ptr = mem; 1199 sg_req[i].ch_regs.high_addr_ptr = 1200 FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32)); 1201 } 1202 /* 1203 * Word count register takes input in words. Writing a value 1204 * of N into word count register means a req of (N+1) words. 1205 */ 1206 sg_req[i].ch_regs.wcount = ((len - 4) >> 2); 1207 sg_req[i].ch_regs.csr = csr; 1208 sg_req[i].ch_regs.mmio_seq = mmio_seq; 1209 sg_req[i].ch_regs.mc_seq = mc_seq; 1210 sg_req[i].len = len; 1211 1212 mem += len; 1213 } 1214 1215 dma_desc->cyclic = true; 1216 1217 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); 1218 } 1219 1220 static int tegra_dma_alloc_chan_resources(struct dma_chan *dc) 1221 { 1222 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 1223 int ret; 1224 1225 ret = request_irq(tdc->irq, tegra_dma_isr, 0, tdc->name, tdc); 1226 if (ret) { 1227 dev_err(tdc2dev(tdc), "request_irq failed for %s\n", tdc->name); 1228 return ret; 1229 } 1230 1231 dma_cookie_init(&tdc->vc.chan); 1232 tdc->config_init = false; 1233 return 0; 1234 } 1235 1236 static void tegra_dma_chan_synchronize(struct dma_chan *dc) 1237 { 1238 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 1239 1240 synchronize_irq(tdc->irq); 1241 vchan_synchronize(&tdc->vc); 1242 } 1243 1244 static void tegra_dma_free_chan_resources(struct dma_chan *dc) 1245 { 1246 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); 1247 1248 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id); 1249 1250 tegra_dma_terminate_all(dc); 1251 synchronize_irq(tdc->irq); 1252 1253 tasklet_kill(&tdc->vc.task); 1254 tdc->config_init = false; 1255 tdc->slave_id = -1; 1256 tdc->sid_dir = DMA_TRANS_NONE; 1257 free_irq(tdc->irq, tdc); 1258 1259 vchan_free_chan_resources(&tdc->vc); 1260 } 1261 1262 static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec, 1263 struct of_dma *ofdma) 1264 { 1265 struct tegra_dma *tdma = ofdma->of_dma_data; 1266 struct tegra_dma_channel *tdc; 1267 struct dma_chan *chan; 1268 1269 chan = dma_get_any_slave_channel(&tdma->dma_dev); 1270 if (!chan) 1271 return NULL; 1272 1273 tdc = to_tegra_dma_chan(chan); 1274 tdc->slave_id = dma_spec->args[0]; 1275 1276 return chan; 1277 } 1278 1279 static const struct tegra_dma_chip_data tegra186_dma_chip_data = { 1280 .nr_channels = 31, 1281 .channel_reg_size = SZ_64K, 1282 .max_dma_count = SZ_1G, 1283 .hw_support_pause = false, 1284 .terminate = tegra_dma_stop_client, 1285 }; 1286 1287 static const struct tegra_dma_chip_data tegra194_dma_chip_data = { 1288 .nr_channels = 31, 1289 .channel_reg_size = SZ_64K, 1290 .max_dma_count = SZ_1G, 1291 .hw_support_pause = true, 1292 .terminate = tegra_dma_pause, 1293 }; 1294 1295 static const struct of_device_id tegra_dma_of_match[] = { 1296 { 1297 .compatible = "nvidia,tegra186-gpcdma", 1298 .data = &tegra186_dma_chip_data, 1299 }, { 1300 .compatible = "nvidia,tegra194-gpcdma", 1301 .data = &tegra194_dma_chip_data, 1302 }, { 1303 }, 1304 }; 1305 MODULE_DEVICE_TABLE(of, tegra_dma_of_match); 1306 1307 static int tegra_dma_program_sid(struct tegra_dma_channel *tdc, int stream_id) 1308 { 1309 unsigned int reg_val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); 1310 1311 reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK); 1312 reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK); 1313 1314 reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK, stream_id); 1315 reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK, stream_id); 1316 1317 tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, reg_val); 1318 return 0; 1319 } 1320 1321 static int tegra_dma_probe(struct platform_device *pdev) 1322 { 1323 const struct tegra_dma_chip_data *cdata = NULL; 1324 struct iommu_fwspec *iommu_spec; 1325 unsigned int stream_id, i; 1326 struct tegra_dma *tdma; 1327 int ret; 1328 1329 cdata = of_device_get_match_data(&pdev->dev); 1330 1331 tdma = devm_kzalloc(&pdev->dev, 1332 struct_size(tdma, channels, cdata->nr_channels), 1333 GFP_KERNEL); 1334 if (!tdma) 1335 return -ENOMEM; 1336 1337 tdma->dev = &pdev->dev; 1338 tdma->chip_data = cdata; 1339 platform_set_drvdata(pdev, tdma); 1340 1341 tdma->base_addr = devm_platform_ioremap_resource(pdev, 0); 1342 if (IS_ERR(tdma->base_addr)) 1343 return PTR_ERR(tdma->base_addr); 1344 1345 tdma->rst = devm_reset_control_get_exclusive(&pdev->dev, "gpcdma"); 1346 if (IS_ERR(tdma->rst)) { 1347 return dev_err_probe(&pdev->dev, PTR_ERR(tdma->rst), 1348 "Missing controller reset\n"); 1349 } 1350 reset_control_reset(tdma->rst); 1351 1352 tdma->dma_dev.dev = &pdev->dev; 1353 1354 iommu_spec = dev_iommu_fwspec_get(&pdev->dev); 1355 if (!iommu_spec) { 1356 dev_err(&pdev->dev, "Missing iommu stream-id\n"); 1357 return -EINVAL; 1358 } 1359 stream_id = iommu_spec->ids[0] & 0xffff; 1360 1361 INIT_LIST_HEAD(&tdma->dma_dev.channels); 1362 for (i = 0; i < cdata->nr_channels; i++) { 1363 struct tegra_dma_channel *tdc = &tdma->channels[i]; 1364 1365 tdc->irq = platform_get_irq(pdev, i); 1366 if (tdc->irq < 0) 1367 return tdc->irq; 1368 1369 tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET + 1370 i * cdata->channel_reg_size; 1371 snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i); 1372 tdc->tdma = tdma; 1373 tdc->id = i; 1374 tdc->slave_id = -1; 1375 1376 vchan_init(&tdc->vc, &tdma->dma_dev); 1377 tdc->vc.desc_free = tegra_dma_desc_free; 1378 1379 /* program stream-id for this channel */ 1380 tegra_dma_program_sid(tdc, stream_id); 1381 tdc->stream_id = stream_id; 1382 } 1383 1384 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask); 1385 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask); 1386 dma_cap_set(DMA_MEMCPY, tdma->dma_dev.cap_mask); 1387 dma_cap_set(DMA_MEMSET, tdma->dma_dev.cap_mask); 1388 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask); 1389 1390 /* 1391 * Only word aligned transfers are supported. Set the copy 1392 * alignment shift. 1393 */ 1394 tdma->dma_dev.copy_align = 2; 1395 tdma->dma_dev.fill_align = 2; 1396 tdma->dma_dev.device_alloc_chan_resources = 1397 tegra_dma_alloc_chan_resources; 1398 tdma->dma_dev.device_free_chan_resources = 1399 tegra_dma_free_chan_resources; 1400 tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg; 1401 tdma->dma_dev.device_prep_dma_memcpy = tegra_dma_prep_dma_memcpy; 1402 tdma->dma_dev.device_prep_dma_memset = tegra_dma_prep_dma_memset; 1403 tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic; 1404 tdma->dma_dev.device_config = tegra_dma_slave_config; 1405 tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all; 1406 tdma->dma_dev.device_tx_status = tegra_dma_tx_status; 1407 tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending; 1408 tdma->dma_dev.device_pause = tegra_dma_device_pause; 1409 tdma->dma_dev.device_resume = tegra_dma_device_resume; 1410 tdma->dma_dev.device_synchronize = tegra_dma_chan_synchronize; 1411 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 1412 1413 ret = dma_async_device_register(&tdma->dma_dev); 1414 if (ret < 0) { 1415 dev_err_probe(&pdev->dev, ret, 1416 "GPC DMA driver registration failed\n"); 1417 return ret; 1418 } 1419 1420 ret = of_dma_controller_register(pdev->dev.of_node, 1421 tegra_dma_of_xlate, tdma); 1422 if (ret < 0) { 1423 dev_err_probe(&pdev->dev, ret, 1424 "GPC DMA OF registration failed\n"); 1425 1426 dma_async_device_unregister(&tdma->dma_dev); 1427 return ret; 1428 } 1429 1430 dev_info(&pdev->dev, "GPC DMA driver register %d channels\n", 1431 cdata->nr_channels); 1432 1433 return 0; 1434 } 1435 1436 static int tegra_dma_remove(struct platform_device *pdev) 1437 { 1438 struct tegra_dma *tdma = platform_get_drvdata(pdev); 1439 1440 of_dma_controller_free(pdev->dev.of_node); 1441 dma_async_device_unregister(&tdma->dma_dev); 1442 1443 return 0; 1444 } 1445 1446 static int __maybe_unused tegra_dma_pm_suspend(struct device *dev) 1447 { 1448 struct tegra_dma *tdma = dev_get_drvdata(dev); 1449 unsigned int i; 1450 1451 for (i = 0; i < tdma->chip_data->nr_channels; i++) { 1452 struct tegra_dma_channel *tdc = &tdma->channels[i]; 1453 1454 if (tdc->dma_desc) { 1455 dev_err(tdma->dev, "channel %u busy\n", i); 1456 return -EBUSY; 1457 } 1458 } 1459 1460 return 0; 1461 } 1462 1463 static int __maybe_unused tegra_dma_pm_resume(struct device *dev) 1464 { 1465 struct tegra_dma *tdma = dev_get_drvdata(dev); 1466 unsigned int i; 1467 1468 reset_control_reset(tdma->rst); 1469 1470 for (i = 0; i < tdma->chip_data->nr_channels; i++) { 1471 struct tegra_dma_channel *tdc = &tdma->channels[i]; 1472 1473 tegra_dma_program_sid(tdc, tdc->stream_id); 1474 } 1475 1476 return 0; 1477 } 1478 1479 static const struct dev_pm_ops tegra_dma_dev_pm_ops = { 1480 SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume) 1481 }; 1482 1483 static struct platform_driver tegra_dma_driver = { 1484 .driver = { 1485 .name = "tegra-gpcdma", 1486 .pm = &tegra_dma_dev_pm_ops, 1487 .of_match_table = tegra_dma_of_match, 1488 }, 1489 .probe = tegra_dma_probe, 1490 .remove = tegra_dma_remove, 1491 }; 1492 1493 module_platform_driver(tegra_dma_driver); 1494 1495 MODULE_DESCRIPTION("NVIDIA Tegra GPC DMA Controller driver"); 1496 MODULE_AUTHOR("Pavan Kunapuli <pkunapuli@nvidia.com>"); 1497 MODULE_AUTHOR("Rajesh Gumasta <rgumasta@nvidia.com>"); 1498 MODULE_LICENSE("GPL"); 1499