1 /* 2 * Copyright (C) 2013-2014 Allwinner Tech Co., Ltd 3 * Author: Sugar <shuge@allwinnertech.com> 4 * 5 * Copyright (C) 2014 Maxime Ripard 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/dmaengine.h> 17 #include <linux/dmapool.h> 18 #include <linux/interrupt.h> 19 #include <linux/module.h> 20 #include <linux/of_dma.h> 21 #include <linux/of_device.h> 22 #include <linux/platform_device.h> 23 #include <linux/reset.h> 24 #include <linux/slab.h> 25 #include <linux/types.h> 26 27 #include "virt-dma.h" 28 29 /* 30 * Common registers 31 */ 32 #define DMA_IRQ_EN(x) ((x) * 0x04) 33 #define DMA_IRQ_HALF BIT(0) 34 #define DMA_IRQ_PKG BIT(1) 35 #define DMA_IRQ_QUEUE BIT(2) 36 37 #define DMA_IRQ_CHAN_NR 8 38 #define DMA_IRQ_CHAN_WIDTH 4 39 40 41 #define DMA_IRQ_STAT(x) ((x) * 0x04 + 0x10) 42 43 #define DMA_STAT 0x30 44 45 /* 46 * sun8i specific registers 47 */ 48 #define SUN8I_DMA_GATE 0x20 49 #define SUN8I_DMA_GATE_ENABLE 0x4 50 51 /* 52 * Channels specific registers 53 */ 54 #define DMA_CHAN_ENABLE 0x00 55 #define DMA_CHAN_ENABLE_START BIT(0) 56 #define DMA_CHAN_ENABLE_STOP 0 57 58 #define DMA_CHAN_PAUSE 0x04 59 #define DMA_CHAN_PAUSE_PAUSE BIT(1) 60 #define DMA_CHAN_PAUSE_RESUME 0 61 62 #define DMA_CHAN_LLI_ADDR 0x08 63 64 #define DMA_CHAN_CUR_CFG 0x0c 65 #define DMA_CHAN_CFG_SRC_DRQ(x) ((x) & 0x1f) 66 #define DMA_CHAN_CFG_SRC_IO_MODE BIT(5) 67 #define DMA_CHAN_CFG_SRC_LINEAR_MODE (0 << 5) 68 #define DMA_CHAN_CFG_SRC_BURST(x) (((x) & 0x3) << 7) 69 #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9) 70 71 #define DMA_CHAN_CFG_DST_DRQ(x) (DMA_CHAN_CFG_SRC_DRQ(x) << 16) 72 #define DMA_CHAN_CFG_DST_IO_MODE (DMA_CHAN_CFG_SRC_IO_MODE << 16) 73 #define DMA_CHAN_CFG_DST_LINEAR_MODE (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16) 74 #define DMA_CHAN_CFG_DST_BURST(x) (DMA_CHAN_CFG_SRC_BURST(x) << 16) 75 #define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16) 76 77 #define DMA_CHAN_CUR_SRC 0x10 78 79 #define DMA_CHAN_CUR_DST 0x14 80 81 #define DMA_CHAN_CUR_CNT 0x18 82 83 #define DMA_CHAN_CUR_PARA 0x1c 84 85 86 /* 87 * Various hardware related defines 88 */ 89 #define LLI_LAST_ITEM 0xfffff800 90 #define NORMAL_WAIT 8 91 #define DRQ_SDRAM 1 92 93 /* 94 * Hardware channels / ports representation 95 * 96 * The hardware is used in several SoCs, with differing numbers 97 * of channels and endpoints. This structure ties those numbers 98 * to a certain compatible string. 99 */ 100 struct sun6i_dma_config { 101 u32 nr_max_channels; 102 u32 nr_max_requests; 103 u32 nr_max_vchans; 104 }; 105 106 /* 107 * Hardware representation of the LLI 108 * 109 * The hardware will be fed the physical address of this structure, 110 * and read its content in order to start the transfer. 111 */ 112 struct sun6i_dma_lli { 113 u32 cfg; 114 u32 src; 115 u32 dst; 116 u32 len; 117 u32 para; 118 u32 p_lli_next; 119 120 /* 121 * This field is not used by the DMA controller, but will be 122 * used by the CPU to go through the list (mostly for dumping 123 * or freeing it). 124 */ 125 struct sun6i_dma_lli *v_lli_next; 126 }; 127 128 129 struct sun6i_desc { 130 struct virt_dma_desc vd; 131 dma_addr_t p_lli; 132 struct sun6i_dma_lli *v_lli; 133 }; 134 135 struct sun6i_pchan { 136 u32 idx; 137 void __iomem *base; 138 struct sun6i_vchan *vchan; 139 struct sun6i_desc *desc; 140 struct sun6i_desc *done; 141 }; 142 143 struct sun6i_vchan { 144 struct virt_dma_chan vc; 145 struct list_head node; 146 struct dma_slave_config cfg; 147 struct sun6i_pchan *phy; 148 u8 port; 149 u8 irq_type; 150 bool cyclic; 151 }; 152 153 struct sun6i_dma_dev { 154 struct dma_device slave; 155 void __iomem *base; 156 struct clk *clk; 157 int irq; 158 spinlock_t lock; 159 struct reset_control *rstc; 160 struct tasklet_struct task; 161 atomic_t tasklet_shutdown; 162 struct list_head pending; 163 struct dma_pool *pool; 164 struct sun6i_pchan *pchans; 165 struct sun6i_vchan *vchans; 166 const struct sun6i_dma_config *cfg; 167 }; 168 169 static struct device *chan2dev(struct dma_chan *chan) 170 { 171 return &chan->dev->device; 172 } 173 174 static inline struct sun6i_dma_dev *to_sun6i_dma_dev(struct dma_device *d) 175 { 176 return container_of(d, struct sun6i_dma_dev, slave); 177 } 178 179 static inline struct sun6i_vchan *to_sun6i_vchan(struct dma_chan *chan) 180 { 181 return container_of(chan, struct sun6i_vchan, vc.chan); 182 } 183 184 static inline struct sun6i_desc * 185 to_sun6i_desc(struct dma_async_tx_descriptor *tx) 186 { 187 return container_of(tx, struct sun6i_desc, vd.tx); 188 } 189 190 static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev) 191 { 192 dev_dbg(sdev->slave.dev, "Common register:\n" 193 "\tmask0(%04x): 0x%08x\n" 194 "\tmask1(%04x): 0x%08x\n" 195 "\tpend0(%04x): 0x%08x\n" 196 "\tpend1(%04x): 0x%08x\n" 197 "\tstats(%04x): 0x%08x\n", 198 DMA_IRQ_EN(0), readl(sdev->base + DMA_IRQ_EN(0)), 199 DMA_IRQ_EN(1), readl(sdev->base + DMA_IRQ_EN(1)), 200 DMA_IRQ_STAT(0), readl(sdev->base + DMA_IRQ_STAT(0)), 201 DMA_IRQ_STAT(1), readl(sdev->base + DMA_IRQ_STAT(1)), 202 DMA_STAT, readl(sdev->base + DMA_STAT)); 203 } 204 205 static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev, 206 struct sun6i_pchan *pchan) 207 { 208 phys_addr_t reg = virt_to_phys(pchan->base); 209 210 dev_dbg(sdev->slave.dev, "Chan %d reg: %pa\n" 211 "\t___en(%04x): \t0x%08x\n" 212 "\tpause(%04x): \t0x%08x\n" 213 "\tstart(%04x): \t0x%08x\n" 214 "\t__cfg(%04x): \t0x%08x\n" 215 "\t__src(%04x): \t0x%08x\n" 216 "\t__dst(%04x): \t0x%08x\n" 217 "\tcount(%04x): \t0x%08x\n" 218 "\t_para(%04x): \t0x%08x\n\n", 219 pchan->idx, ®, 220 DMA_CHAN_ENABLE, 221 readl(pchan->base + DMA_CHAN_ENABLE), 222 DMA_CHAN_PAUSE, 223 readl(pchan->base + DMA_CHAN_PAUSE), 224 DMA_CHAN_LLI_ADDR, 225 readl(pchan->base + DMA_CHAN_LLI_ADDR), 226 DMA_CHAN_CUR_CFG, 227 readl(pchan->base + DMA_CHAN_CUR_CFG), 228 DMA_CHAN_CUR_SRC, 229 readl(pchan->base + DMA_CHAN_CUR_SRC), 230 DMA_CHAN_CUR_DST, 231 readl(pchan->base + DMA_CHAN_CUR_DST), 232 DMA_CHAN_CUR_CNT, 233 readl(pchan->base + DMA_CHAN_CUR_CNT), 234 DMA_CHAN_CUR_PARA, 235 readl(pchan->base + DMA_CHAN_CUR_PARA)); 236 } 237 238 static inline s8 convert_burst(u32 maxburst) 239 { 240 switch (maxburst) { 241 case 1: 242 return 0; 243 case 8: 244 return 2; 245 default: 246 return -EINVAL; 247 } 248 } 249 250 static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width) 251 { 252 if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) || 253 (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES)) 254 return -EINVAL; 255 256 return addr_width >> 1; 257 } 258 259 static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan) 260 { 261 struct sun6i_desc *txd = pchan->desc; 262 struct sun6i_dma_lli *lli; 263 size_t bytes; 264 dma_addr_t pos; 265 266 pos = readl(pchan->base + DMA_CHAN_LLI_ADDR); 267 bytes = readl(pchan->base + DMA_CHAN_CUR_CNT); 268 269 if (pos == LLI_LAST_ITEM) 270 return bytes; 271 272 for (lli = txd->v_lli; lli; lli = lli->v_lli_next) { 273 if (lli->p_lli_next == pos) { 274 for (lli = lli->v_lli_next; lli; lli = lli->v_lli_next) 275 bytes += lli->len; 276 break; 277 } 278 } 279 280 return bytes; 281 } 282 283 static void *sun6i_dma_lli_add(struct sun6i_dma_lli *prev, 284 struct sun6i_dma_lli *next, 285 dma_addr_t next_phy, 286 struct sun6i_desc *txd) 287 { 288 if ((!prev && !txd) || !next) 289 return NULL; 290 291 if (!prev) { 292 txd->p_lli = next_phy; 293 txd->v_lli = next; 294 } else { 295 prev->p_lli_next = next_phy; 296 prev->v_lli_next = next; 297 } 298 299 next->p_lli_next = LLI_LAST_ITEM; 300 next->v_lli_next = NULL; 301 302 return next; 303 } 304 305 static inline void sun6i_dma_dump_lli(struct sun6i_vchan *vchan, 306 struct sun6i_dma_lli *lli) 307 { 308 phys_addr_t p_lli = virt_to_phys(lli); 309 310 dev_dbg(chan2dev(&vchan->vc.chan), 311 "\n\tdesc: p - %pa v - 0x%p\n" 312 "\t\tc - 0x%08x s - 0x%08x d - 0x%08x\n" 313 "\t\tl - 0x%08x p - 0x%08x n - 0x%08x\n", 314 &p_lli, lli, 315 lli->cfg, lli->src, lli->dst, 316 lli->len, lli->para, lli->p_lli_next); 317 } 318 319 static void sun6i_dma_free_desc(struct virt_dma_desc *vd) 320 { 321 struct sun6i_desc *txd = to_sun6i_desc(&vd->tx); 322 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vd->tx.chan->device); 323 struct sun6i_dma_lli *v_lli, *v_next; 324 dma_addr_t p_lli, p_next; 325 326 if (unlikely(!txd)) 327 return; 328 329 p_lli = txd->p_lli; 330 v_lli = txd->v_lli; 331 332 while (v_lli) { 333 v_next = v_lli->v_lli_next; 334 p_next = v_lli->p_lli_next; 335 336 dma_pool_free(sdev->pool, v_lli, p_lli); 337 338 v_lli = v_next; 339 p_lli = p_next; 340 } 341 342 kfree(txd); 343 } 344 345 static int sun6i_dma_start_desc(struct sun6i_vchan *vchan) 346 { 347 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vchan->vc.chan.device); 348 struct virt_dma_desc *desc = vchan_next_desc(&vchan->vc); 349 struct sun6i_pchan *pchan = vchan->phy; 350 u32 irq_val, irq_reg, irq_offset; 351 352 if (!pchan) 353 return -EAGAIN; 354 355 if (!desc) { 356 pchan->desc = NULL; 357 pchan->done = NULL; 358 return -EAGAIN; 359 } 360 361 list_del(&desc->node); 362 363 pchan->desc = to_sun6i_desc(&desc->tx); 364 pchan->done = NULL; 365 366 sun6i_dma_dump_lli(vchan, pchan->desc->v_lli); 367 368 irq_reg = pchan->idx / DMA_IRQ_CHAN_NR; 369 irq_offset = pchan->idx % DMA_IRQ_CHAN_NR; 370 371 vchan->irq_type = vchan->cyclic ? DMA_IRQ_PKG : DMA_IRQ_QUEUE; 372 373 irq_val = readl(sdev->base + DMA_IRQ_EN(irq_reg)); 374 irq_val &= ~((DMA_IRQ_HALF | DMA_IRQ_PKG | DMA_IRQ_QUEUE) << 375 (irq_offset * DMA_IRQ_CHAN_WIDTH)); 376 irq_val |= vchan->irq_type << (irq_offset * DMA_IRQ_CHAN_WIDTH); 377 writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg)); 378 379 writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR); 380 writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE); 381 382 sun6i_dma_dump_com_regs(sdev); 383 sun6i_dma_dump_chan_regs(sdev, pchan); 384 385 return 0; 386 } 387 388 static void sun6i_dma_tasklet(unsigned long data) 389 { 390 struct sun6i_dma_dev *sdev = (struct sun6i_dma_dev *)data; 391 const struct sun6i_dma_config *cfg = sdev->cfg; 392 struct sun6i_vchan *vchan; 393 struct sun6i_pchan *pchan; 394 unsigned int pchan_alloc = 0; 395 unsigned int pchan_idx; 396 397 list_for_each_entry(vchan, &sdev->slave.channels, vc.chan.device_node) { 398 spin_lock_irq(&vchan->vc.lock); 399 400 pchan = vchan->phy; 401 402 if (pchan && pchan->done) { 403 if (sun6i_dma_start_desc(vchan)) { 404 /* 405 * No current txd associated with this channel 406 */ 407 dev_dbg(sdev->slave.dev, "pchan %u: free\n", 408 pchan->idx); 409 410 /* Mark this channel free */ 411 vchan->phy = NULL; 412 pchan->vchan = NULL; 413 } 414 } 415 spin_unlock_irq(&vchan->vc.lock); 416 } 417 418 spin_lock_irq(&sdev->lock); 419 for (pchan_idx = 0; pchan_idx < cfg->nr_max_channels; pchan_idx++) { 420 pchan = &sdev->pchans[pchan_idx]; 421 422 if (pchan->vchan || list_empty(&sdev->pending)) 423 continue; 424 425 vchan = list_first_entry(&sdev->pending, 426 struct sun6i_vchan, node); 427 428 /* Remove from pending channels */ 429 list_del_init(&vchan->node); 430 pchan_alloc |= BIT(pchan_idx); 431 432 /* Mark this channel allocated */ 433 pchan->vchan = vchan; 434 vchan->phy = pchan; 435 dev_dbg(sdev->slave.dev, "pchan %u: alloc vchan %p\n", 436 pchan->idx, &vchan->vc); 437 } 438 spin_unlock_irq(&sdev->lock); 439 440 for (pchan_idx = 0; pchan_idx < cfg->nr_max_channels; pchan_idx++) { 441 if (!(pchan_alloc & BIT(pchan_idx))) 442 continue; 443 444 pchan = sdev->pchans + pchan_idx; 445 vchan = pchan->vchan; 446 if (vchan) { 447 spin_lock_irq(&vchan->vc.lock); 448 sun6i_dma_start_desc(vchan); 449 spin_unlock_irq(&vchan->vc.lock); 450 } 451 } 452 } 453 454 static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id) 455 { 456 struct sun6i_dma_dev *sdev = dev_id; 457 struct sun6i_vchan *vchan; 458 struct sun6i_pchan *pchan; 459 int i, j, ret = IRQ_NONE; 460 u32 status; 461 462 for (i = 0; i < sdev->cfg->nr_max_channels / DMA_IRQ_CHAN_NR; i++) { 463 status = readl(sdev->base + DMA_IRQ_STAT(i)); 464 if (!status) 465 continue; 466 467 dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n", 468 i ? "high" : "low", status); 469 470 writel(status, sdev->base + DMA_IRQ_STAT(i)); 471 472 for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) { 473 pchan = sdev->pchans + j; 474 vchan = pchan->vchan; 475 if (vchan && (status & vchan->irq_type)) { 476 if (vchan->cyclic) { 477 vchan_cyclic_callback(&pchan->desc->vd); 478 } else { 479 spin_lock(&vchan->vc.lock); 480 vchan_cookie_complete(&pchan->desc->vd); 481 pchan->done = pchan->desc; 482 spin_unlock(&vchan->vc.lock); 483 } 484 } 485 486 status = status >> DMA_IRQ_CHAN_WIDTH; 487 } 488 489 if (!atomic_read(&sdev->tasklet_shutdown)) 490 tasklet_schedule(&sdev->task); 491 ret = IRQ_HANDLED; 492 } 493 494 return ret; 495 } 496 497 static int set_config(struct sun6i_dma_dev *sdev, 498 struct dma_slave_config *sconfig, 499 enum dma_transfer_direction direction, 500 u32 *p_cfg) 501 { 502 s8 src_width, dst_width, src_burst, dst_burst; 503 504 switch (direction) { 505 case DMA_MEM_TO_DEV: 506 src_burst = convert_burst(sconfig->src_maxburst ? 507 sconfig->src_maxburst : 8); 508 src_width = convert_buswidth(sconfig->src_addr_width != 509 DMA_SLAVE_BUSWIDTH_UNDEFINED ? 510 sconfig->src_addr_width : 511 DMA_SLAVE_BUSWIDTH_4_BYTES); 512 dst_burst = convert_burst(sconfig->dst_maxburst); 513 dst_width = convert_buswidth(sconfig->dst_addr_width); 514 break; 515 case DMA_DEV_TO_MEM: 516 src_burst = convert_burst(sconfig->src_maxburst); 517 src_width = convert_buswidth(sconfig->src_addr_width); 518 dst_burst = convert_burst(sconfig->dst_maxburst ? 519 sconfig->dst_maxburst : 8); 520 dst_width = convert_buswidth(sconfig->dst_addr_width != 521 DMA_SLAVE_BUSWIDTH_UNDEFINED ? 522 sconfig->dst_addr_width : 523 DMA_SLAVE_BUSWIDTH_4_BYTES); 524 break; 525 default: 526 return -EINVAL; 527 } 528 529 if (src_burst < 0) 530 return src_burst; 531 if (src_width < 0) 532 return src_width; 533 if (dst_burst < 0) 534 return dst_burst; 535 if (dst_width < 0) 536 return dst_width; 537 538 *p_cfg = DMA_CHAN_CFG_SRC_BURST(src_burst) | 539 DMA_CHAN_CFG_SRC_WIDTH(src_width) | 540 DMA_CHAN_CFG_DST_BURST(dst_burst) | 541 DMA_CHAN_CFG_DST_WIDTH(dst_width); 542 543 return 0; 544 } 545 546 static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy( 547 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 548 size_t len, unsigned long flags) 549 { 550 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); 551 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 552 struct sun6i_dma_lli *v_lli; 553 struct sun6i_desc *txd; 554 dma_addr_t p_lli; 555 s8 burst, width; 556 557 dev_dbg(chan2dev(chan), 558 "%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n", 559 __func__, vchan->vc.chan.chan_id, &dest, &src, len, flags); 560 561 if (!len) 562 return NULL; 563 564 txd = kzalloc(sizeof(*txd), GFP_NOWAIT); 565 if (!txd) 566 return NULL; 567 568 v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli); 569 if (!v_lli) { 570 dev_err(sdev->slave.dev, "Failed to alloc lli memory\n"); 571 goto err_txd_free; 572 } 573 574 v_lli->src = src; 575 v_lli->dst = dest; 576 v_lli->len = len; 577 v_lli->para = NORMAL_WAIT; 578 579 burst = convert_burst(8); 580 width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES); 581 v_lli->cfg = DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | 582 DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | 583 DMA_CHAN_CFG_DST_LINEAR_MODE | 584 DMA_CHAN_CFG_SRC_LINEAR_MODE | 585 DMA_CHAN_CFG_SRC_BURST(burst) | 586 DMA_CHAN_CFG_SRC_WIDTH(width) | 587 DMA_CHAN_CFG_DST_BURST(burst) | 588 DMA_CHAN_CFG_DST_WIDTH(width); 589 590 sun6i_dma_lli_add(NULL, v_lli, p_lli, txd); 591 592 sun6i_dma_dump_lli(vchan, v_lli); 593 594 return vchan_tx_prep(&vchan->vc, &txd->vd, flags); 595 596 err_txd_free: 597 kfree(txd); 598 return NULL; 599 } 600 601 static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( 602 struct dma_chan *chan, struct scatterlist *sgl, 603 unsigned int sg_len, enum dma_transfer_direction dir, 604 unsigned long flags, void *context) 605 { 606 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); 607 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 608 struct dma_slave_config *sconfig = &vchan->cfg; 609 struct sun6i_dma_lli *v_lli, *prev = NULL; 610 struct sun6i_desc *txd; 611 struct scatterlist *sg; 612 dma_addr_t p_lli; 613 u32 lli_cfg; 614 int i, ret; 615 616 if (!sgl) 617 return NULL; 618 619 ret = set_config(sdev, sconfig, dir, &lli_cfg); 620 if (ret) { 621 dev_err(chan2dev(chan), "Invalid DMA configuration\n"); 622 return NULL; 623 } 624 625 txd = kzalloc(sizeof(*txd), GFP_NOWAIT); 626 if (!txd) 627 return NULL; 628 629 for_each_sg(sgl, sg, sg_len, i) { 630 v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli); 631 if (!v_lli) 632 goto err_lli_free; 633 634 v_lli->len = sg_dma_len(sg); 635 v_lli->para = NORMAL_WAIT; 636 637 if (dir == DMA_MEM_TO_DEV) { 638 v_lli->src = sg_dma_address(sg); 639 v_lli->dst = sconfig->dst_addr; 640 v_lli->cfg = lli_cfg | 641 DMA_CHAN_CFG_DST_IO_MODE | 642 DMA_CHAN_CFG_SRC_LINEAR_MODE | 643 DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | 644 DMA_CHAN_CFG_DST_DRQ(vchan->port); 645 646 dev_dbg(chan2dev(chan), 647 "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", 648 __func__, vchan->vc.chan.chan_id, 649 &sconfig->dst_addr, &sg_dma_address(sg), 650 sg_dma_len(sg), flags); 651 652 } else { 653 v_lli->src = sconfig->src_addr; 654 v_lli->dst = sg_dma_address(sg); 655 v_lli->cfg = lli_cfg | 656 DMA_CHAN_CFG_DST_LINEAR_MODE | 657 DMA_CHAN_CFG_SRC_IO_MODE | 658 DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | 659 DMA_CHAN_CFG_SRC_DRQ(vchan->port); 660 661 dev_dbg(chan2dev(chan), 662 "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", 663 __func__, vchan->vc.chan.chan_id, 664 &sg_dma_address(sg), &sconfig->src_addr, 665 sg_dma_len(sg), flags); 666 } 667 668 prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd); 669 } 670 671 dev_dbg(chan2dev(chan), "First: %pad\n", &txd->p_lli); 672 for (prev = txd->v_lli; prev; prev = prev->v_lli_next) 673 sun6i_dma_dump_lli(vchan, prev); 674 675 return vchan_tx_prep(&vchan->vc, &txd->vd, flags); 676 677 err_lli_free: 678 for (prev = txd->v_lli; prev; prev = prev->v_lli_next) 679 dma_pool_free(sdev->pool, prev, virt_to_phys(prev)); 680 kfree(txd); 681 return NULL; 682 } 683 684 static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic( 685 struct dma_chan *chan, 686 dma_addr_t buf_addr, 687 size_t buf_len, 688 size_t period_len, 689 enum dma_transfer_direction dir, 690 unsigned long flags) 691 { 692 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); 693 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 694 struct dma_slave_config *sconfig = &vchan->cfg; 695 struct sun6i_dma_lli *v_lli, *prev = NULL; 696 struct sun6i_desc *txd; 697 dma_addr_t p_lli; 698 u32 lli_cfg; 699 unsigned int i, periods = buf_len / period_len; 700 int ret; 701 702 ret = set_config(sdev, sconfig, dir, &lli_cfg); 703 if (ret) { 704 dev_err(chan2dev(chan), "Invalid DMA configuration\n"); 705 return NULL; 706 } 707 708 txd = kzalloc(sizeof(*txd), GFP_NOWAIT); 709 if (!txd) 710 return NULL; 711 712 for (i = 0; i < periods; i++) { 713 v_lli = dma_pool_alloc(sdev->pool, GFP_NOWAIT, &p_lli); 714 if (!v_lli) { 715 dev_err(sdev->slave.dev, "Failed to alloc lli memory\n"); 716 goto err_lli_free; 717 } 718 719 v_lli->len = period_len; 720 v_lli->para = NORMAL_WAIT; 721 722 if (dir == DMA_MEM_TO_DEV) { 723 v_lli->src = buf_addr + period_len * i; 724 v_lli->dst = sconfig->dst_addr; 725 v_lli->cfg = lli_cfg | 726 DMA_CHAN_CFG_DST_IO_MODE | 727 DMA_CHAN_CFG_SRC_LINEAR_MODE | 728 DMA_CHAN_CFG_SRC_DRQ(DRQ_SDRAM) | 729 DMA_CHAN_CFG_DST_DRQ(vchan->port); 730 } else { 731 v_lli->src = sconfig->src_addr; 732 v_lli->dst = buf_addr + period_len * i; 733 v_lli->cfg = lli_cfg | 734 DMA_CHAN_CFG_DST_LINEAR_MODE | 735 DMA_CHAN_CFG_SRC_IO_MODE | 736 DMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) | 737 DMA_CHAN_CFG_SRC_DRQ(vchan->port); 738 } 739 740 prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd); 741 } 742 743 prev->p_lli_next = txd->p_lli; /* cyclic list */ 744 745 vchan->cyclic = true; 746 747 return vchan_tx_prep(&vchan->vc, &txd->vd, flags); 748 749 err_lli_free: 750 for (prev = txd->v_lli; prev; prev = prev->v_lli_next) 751 dma_pool_free(sdev->pool, prev, virt_to_phys(prev)); 752 kfree(txd); 753 return NULL; 754 } 755 756 static int sun6i_dma_config(struct dma_chan *chan, 757 struct dma_slave_config *config) 758 { 759 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 760 761 memcpy(&vchan->cfg, config, sizeof(*config)); 762 763 return 0; 764 } 765 766 static int sun6i_dma_pause(struct dma_chan *chan) 767 { 768 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); 769 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 770 struct sun6i_pchan *pchan = vchan->phy; 771 772 dev_dbg(chan2dev(chan), "vchan %p: pause\n", &vchan->vc); 773 774 if (pchan) { 775 writel(DMA_CHAN_PAUSE_PAUSE, 776 pchan->base + DMA_CHAN_PAUSE); 777 } else { 778 spin_lock(&sdev->lock); 779 list_del_init(&vchan->node); 780 spin_unlock(&sdev->lock); 781 } 782 783 return 0; 784 } 785 786 static int sun6i_dma_resume(struct dma_chan *chan) 787 { 788 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); 789 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 790 struct sun6i_pchan *pchan = vchan->phy; 791 unsigned long flags; 792 793 dev_dbg(chan2dev(chan), "vchan %p: resume\n", &vchan->vc); 794 795 spin_lock_irqsave(&vchan->vc.lock, flags); 796 797 if (pchan) { 798 writel(DMA_CHAN_PAUSE_RESUME, 799 pchan->base + DMA_CHAN_PAUSE); 800 } else if (!list_empty(&vchan->vc.desc_issued)) { 801 spin_lock(&sdev->lock); 802 list_add_tail(&vchan->node, &sdev->pending); 803 spin_unlock(&sdev->lock); 804 } 805 806 spin_unlock_irqrestore(&vchan->vc.lock, flags); 807 808 return 0; 809 } 810 811 static int sun6i_dma_terminate_all(struct dma_chan *chan) 812 { 813 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); 814 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 815 struct sun6i_pchan *pchan = vchan->phy; 816 unsigned long flags; 817 LIST_HEAD(head); 818 819 spin_lock(&sdev->lock); 820 list_del_init(&vchan->node); 821 spin_unlock(&sdev->lock); 822 823 spin_lock_irqsave(&vchan->vc.lock, flags); 824 825 if (vchan->cyclic) { 826 vchan->cyclic = false; 827 if (pchan && pchan->desc) { 828 struct virt_dma_desc *vd = &pchan->desc->vd; 829 struct virt_dma_chan *vc = &vchan->vc; 830 831 list_add_tail(&vd->node, &vc->desc_completed); 832 } 833 } 834 835 vchan_get_all_descriptors(&vchan->vc, &head); 836 837 if (pchan) { 838 writel(DMA_CHAN_ENABLE_STOP, pchan->base + DMA_CHAN_ENABLE); 839 writel(DMA_CHAN_PAUSE_RESUME, pchan->base + DMA_CHAN_PAUSE); 840 841 vchan->phy = NULL; 842 pchan->vchan = NULL; 843 pchan->desc = NULL; 844 pchan->done = NULL; 845 } 846 847 spin_unlock_irqrestore(&vchan->vc.lock, flags); 848 849 vchan_dma_desc_free_list(&vchan->vc, &head); 850 851 return 0; 852 } 853 854 static enum dma_status sun6i_dma_tx_status(struct dma_chan *chan, 855 dma_cookie_t cookie, 856 struct dma_tx_state *state) 857 { 858 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 859 struct sun6i_pchan *pchan = vchan->phy; 860 struct sun6i_dma_lli *lli; 861 struct virt_dma_desc *vd; 862 struct sun6i_desc *txd; 863 enum dma_status ret; 864 unsigned long flags; 865 size_t bytes = 0; 866 867 ret = dma_cookie_status(chan, cookie, state); 868 if (ret == DMA_COMPLETE || !state) 869 return ret; 870 871 spin_lock_irqsave(&vchan->vc.lock, flags); 872 873 vd = vchan_find_desc(&vchan->vc, cookie); 874 txd = to_sun6i_desc(&vd->tx); 875 876 if (vd) { 877 for (lli = txd->v_lli; lli != NULL; lli = lli->v_lli_next) 878 bytes += lli->len; 879 } else if (!pchan || !pchan->desc) { 880 bytes = 0; 881 } else { 882 bytes = sun6i_get_chan_size(pchan); 883 } 884 885 spin_unlock_irqrestore(&vchan->vc.lock, flags); 886 887 dma_set_residue(state, bytes); 888 889 return ret; 890 } 891 892 static void sun6i_dma_issue_pending(struct dma_chan *chan) 893 { 894 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); 895 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 896 unsigned long flags; 897 898 spin_lock_irqsave(&vchan->vc.lock, flags); 899 900 if (vchan_issue_pending(&vchan->vc)) { 901 spin_lock(&sdev->lock); 902 903 if (!vchan->phy && list_empty(&vchan->node)) { 904 list_add_tail(&vchan->node, &sdev->pending); 905 tasklet_schedule(&sdev->task); 906 dev_dbg(chan2dev(chan), "vchan %p: issued\n", 907 &vchan->vc); 908 } 909 910 spin_unlock(&sdev->lock); 911 } else { 912 dev_dbg(chan2dev(chan), "vchan %p: nothing to issue\n", 913 &vchan->vc); 914 } 915 916 spin_unlock_irqrestore(&vchan->vc.lock, flags); 917 } 918 919 static void sun6i_dma_free_chan_resources(struct dma_chan *chan) 920 { 921 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); 922 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 923 unsigned long flags; 924 925 spin_lock_irqsave(&sdev->lock, flags); 926 list_del_init(&vchan->node); 927 spin_unlock_irqrestore(&sdev->lock, flags); 928 929 vchan_free_chan_resources(&vchan->vc); 930 } 931 932 static struct dma_chan *sun6i_dma_of_xlate(struct of_phandle_args *dma_spec, 933 struct of_dma *ofdma) 934 { 935 struct sun6i_dma_dev *sdev = ofdma->of_dma_data; 936 struct sun6i_vchan *vchan; 937 struct dma_chan *chan; 938 u8 port = dma_spec->args[0]; 939 940 if (port > sdev->cfg->nr_max_requests) 941 return NULL; 942 943 chan = dma_get_any_slave_channel(&sdev->slave); 944 if (!chan) 945 return NULL; 946 947 vchan = to_sun6i_vchan(chan); 948 vchan->port = port; 949 950 return chan; 951 } 952 953 static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev) 954 { 955 /* Disable all interrupts from DMA */ 956 writel(0, sdev->base + DMA_IRQ_EN(0)); 957 writel(0, sdev->base + DMA_IRQ_EN(1)); 958 959 /* Prevent spurious interrupts from scheduling the tasklet */ 960 atomic_inc(&sdev->tasklet_shutdown); 961 962 /* Make sure we won't have any further interrupts */ 963 devm_free_irq(sdev->slave.dev, sdev->irq, sdev); 964 965 /* Actually prevent the tasklet from being scheduled */ 966 tasklet_kill(&sdev->task); 967 } 968 969 static inline void sun6i_dma_free(struct sun6i_dma_dev *sdev) 970 { 971 int i; 972 973 for (i = 0; i < sdev->cfg->nr_max_vchans; i++) { 974 struct sun6i_vchan *vchan = &sdev->vchans[i]; 975 976 list_del(&vchan->vc.chan.device_node); 977 tasklet_kill(&vchan->vc.task); 978 } 979 } 980 981 /* 982 * For A31: 983 * 984 * There's 16 physical channels that can work in parallel. 985 * 986 * However we have 30 different endpoints for our requests. 987 * 988 * Since the channels are able to handle only an unidirectional 989 * transfer, we need to allocate more virtual channels so that 990 * everyone can grab one channel. 991 * 992 * Some devices can't work in both direction (mostly because it 993 * wouldn't make sense), so we have a bit fewer virtual channels than 994 * 2 channels per endpoints. 995 */ 996 997 static struct sun6i_dma_config sun6i_a31_dma_cfg = { 998 .nr_max_channels = 16, 999 .nr_max_requests = 30, 1000 .nr_max_vchans = 53, 1001 }; 1002 1003 /* 1004 * The A23 only has 8 physical channels, a maximum DRQ port id of 24, 1005 * and a total of 37 usable source and destination endpoints. 1006 */ 1007 1008 static struct sun6i_dma_config sun8i_a23_dma_cfg = { 1009 .nr_max_channels = 8, 1010 .nr_max_requests = 24, 1011 .nr_max_vchans = 37, 1012 }; 1013 1014 static struct sun6i_dma_config sun8i_a83t_dma_cfg = { 1015 .nr_max_channels = 8, 1016 .nr_max_requests = 28, 1017 .nr_max_vchans = 39, 1018 }; 1019 1020 /* 1021 * The H3 has 12 physical channels, a maximum DRQ port id of 27, 1022 * and a total of 34 usable source and destination endpoints. 1023 */ 1024 1025 static struct sun6i_dma_config sun8i_h3_dma_cfg = { 1026 .nr_max_channels = 12, 1027 .nr_max_requests = 27, 1028 .nr_max_vchans = 34, 1029 }; 1030 1031 static const struct of_device_id sun6i_dma_match[] = { 1032 { .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg }, 1033 { .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg }, 1034 { .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg }, 1035 { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg }, 1036 { /* sentinel */ } 1037 }; 1038 MODULE_DEVICE_TABLE(of, sun6i_dma_match); 1039 1040 static int sun6i_dma_probe(struct platform_device *pdev) 1041 { 1042 const struct of_device_id *device; 1043 struct sun6i_dma_dev *sdc; 1044 struct resource *res; 1045 int ret, i; 1046 1047 sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL); 1048 if (!sdc) 1049 return -ENOMEM; 1050 1051 device = of_match_device(sun6i_dma_match, &pdev->dev); 1052 if (!device) 1053 return -ENODEV; 1054 sdc->cfg = device->data; 1055 1056 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1057 sdc->base = devm_ioremap_resource(&pdev->dev, res); 1058 if (IS_ERR(sdc->base)) 1059 return PTR_ERR(sdc->base); 1060 1061 sdc->irq = platform_get_irq(pdev, 0); 1062 if (sdc->irq < 0) { 1063 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 1064 return sdc->irq; 1065 } 1066 1067 sdc->clk = devm_clk_get(&pdev->dev, NULL); 1068 if (IS_ERR(sdc->clk)) { 1069 dev_err(&pdev->dev, "No clock specified\n"); 1070 return PTR_ERR(sdc->clk); 1071 } 1072 1073 sdc->rstc = devm_reset_control_get(&pdev->dev, NULL); 1074 if (IS_ERR(sdc->rstc)) { 1075 dev_err(&pdev->dev, "No reset controller specified\n"); 1076 return PTR_ERR(sdc->rstc); 1077 } 1078 1079 sdc->pool = dmam_pool_create(dev_name(&pdev->dev), &pdev->dev, 1080 sizeof(struct sun6i_dma_lli), 4, 0); 1081 if (!sdc->pool) { 1082 dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); 1083 return -ENOMEM; 1084 } 1085 1086 platform_set_drvdata(pdev, sdc); 1087 INIT_LIST_HEAD(&sdc->pending); 1088 spin_lock_init(&sdc->lock); 1089 1090 dma_cap_set(DMA_PRIVATE, sdc->slave.cap_mask); 1091 dma_cap_set(DMA_MEMCPY, sdc->slave.cap_mask); 1092 dma_cap_set(DMA_SLAVE, sdc->slave.cap_mask); 1093 dma_cap_set(DMA_CYCLIC, sdc->slave.cap_mask); 1094 1095 INIT_LIST_HEAD(&sdc->slave.channels); 1096 sdc->slave.device_free_chan_resources = sun6i_dma_free_chan_resources; 1097 sdc->slave.device_tx_status = sun6i_dma_tx_status; 1098 sdc->slave.device_issue_pending = sun6i_dma_issue_pending; 1099 sdc->slave.device_prep_slave_sg = sun6i_dma_prep_slave_sg; 1100 sdc->slave.device_prep_dma_memcpy = sun6i_dma_prep_dma_memcpy; 1101 sdc->slave.device_prep_dma_cyclic = sun6i_dma_prep_dma_cyclic; 1102 sdc->slave.copy_align = DMAENGINE_ALIGN_4_BYTES; 1103 sdc->slave.device_config = sun6i_dma_config; 1104 sdc->slave.device_pause = sun6i_dma_pause; 1105 sdc->slave.device_resume = sun6i_dma_resume; 1106 sdc->slave.device_terminate_all = sun6i_dma_terminate_all; 1107 sdc->slave.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1108 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1109 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 1110 sdc->slave.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1111 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1112 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 1113 sdc->slave.directions = BIT(DMA_DEV_TO_MEM) | 1114 BIT(DMA_MEM_TO_DEV); 1115 sdc->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 1116 sdc->slave.dev = &pdev->dev; 1117 1118 sdc->pchans = devm_kcalloc(&pdev->dev, sdc->cfg->nr_max_channels, 1119 sizeof(struct sun6i_pchan), GFP_KERNEL); 1120 if (!sdc->pchans) 1121 return -ENOMEM; 1122 1123 sdc->vchans = devm_kcalloc(&pdev->dev, sdc->cfg->nr_max_vchans, 1124 sizeof(struct sun6i_vchan), GFP_KERNEL); 1125 if (!sdc->vchans) 1126 return -ENOMEM; 1127 1128 tasklet_init(&sdc->task, sun6i_dma_tasklet, (unsigned long)sdc); 1129 1130 for (i = 0; i < sdc->cfg->nr_max_channels; i++) { 1131 struct sun6i_pchan *pchan = &sdc->pchans[i]; 1132 1133 pchan->idx = i; 1134 pchan->base = sdc->base + 0x100 + i * 0x40; 1135 } 1136 1137 for (i = 0; i < sdc->cfg->nr_max_vchans; i++) { 1138 struct sun6i_vchan *vchan = &sdc->vchans[i]; 1139 1140 INIT_LIST_HEAD(&vchan->node); 1141 vchan->vc.desc_free = sun6i_dma_free_desc; 1142 vchan_init(&vchan->vc, &sdc->slave); 1143 } 1144 1145 ret = reset_control_deassert(sdc->rstc); 1146 if (ret) { 1147 dev_err(&pdev->dev, "Couldn't deassert the device from reset\n"); 1148 goto err_chan_free; 1149 } 1150 1151 ret = clk_prepare_enable(sdc->clk); 1152 if (ret) { 1153 dev_err(&pdev->dev, "Couldn't enable the clock\n"); 1154 goto err_reset_assert; 1155 } 1156 1157 ret = devm_request_irq(&pdev->dev, sdc->irq, sun6i_dma_interrupt, 0, 1158 dev_name(&pdev->dev), sdc); 1159 if (ret) { 1160 dev_err(&pdev->dev, "Cannot request IRQ\n"); 1161 goto err_clk_disable; 1162 } 1163 1164 ret = dma_async_device_register(&sdc->slave); 1165 if (ret) { 1166 dev_warn(&pdev->dev, "Failed to register DMA engine device\n"); 1167 goto err_irq_disable; 1168 } 1169 1170 ret = of_dma_controller_register(pdev->dev.of_node, sun6i_dma_of_xlate, 1171 sdc); 1172 if (ret) { 1173 dev_err(&pdev->dev, "of_dma_controller_register failed\n"); 1174 goto err_dma_unregister; 1175 } 1176 1177 /* 1178 * sun8i variant requires us to toggle a dma gating register, 1179 * as seen in Allwinner's SDK. This register is not documented 1180 * in the A23 user manual. 1181 */ 1182 if (of_device_is_compatible(pdev->dev.of_node, 1183 "allwinner,sun8i-a23-dma")) 1184 writel(SUN8I_DMA_GATE_ENABLE, sdc->base + SUN8I_DMA_GATE); 1185 1186 return 0; 1187 1188 err_dma_unregister: 1189 dma_async_device_unregister(&sdc->slave); 1190 err_irq_disable: 1191 sun6i_kill_tasklet(sdc); 1192 err_clk_disable: 1193 clk_disable_unprepare(sdc->clk); 1194 err_reset_assert: 1195 reset_control_assert(sdc->rstc); 1196 err_chan_free: 1197 sun6i_dma_free(sdc); 1198 return ret; 1199 } 1200 1201 static int sun6i_dma_remove(struct platform_device *pdev) 1202 { 1203 struct sun6i_dma_dev *sdc = platform_get_drvdata(pdev); 1204 1205 of_dma_controller_free(pdev->dev.of_node); 1206 dma_async_device_unregister(&sdc->slave); 1207 1208 sun6i_kill_tasklet(sdc); 1209 1210 clk_disable_unprepare(sdc->clk); 1211 reset_control_assert(sdc->rstc); 1212 1213 sun6i_dma_free(sdc); 1214 1215 return 0; 1216 } 1217 1218 static struct platform_driver sun6i_dma_driver = { 1219 .probe = sun6i_dma_probe, 1220 .remove = sun6i_dma_remove, 1221 .driver = { 1222 .name = "sun6i-dma", 1223 .of_match_table = sun6i_dma_match, 1224 }, 1225 }; 1226 module_platform_driver(sun6i_dma_driver); 1227 1228 MODULE_DESCRIPTION("Allwinner A31 DMA Controller Driver"); 1229 MODULE_AUTHOR("Sugar <shuge@allwinnertech.com>"); 1230 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1231 MODULE_LICENSE("GPL"); 1232