1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 4 * Copyright (C) STMicroelectronics SA 2017 5 * Author(s): M'boumba Cedric Madianga <cedric.madianga@gmail.com> 6 * Pierre-Yves Mordret <pierre-yves.mordret@st.com> 7 * 8 * DMA Router driver for STM32 DMA MUX 9 * 10 * Based on TI DMA Crossbar driver 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/err.h> 16 #include <linux/init.h> 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 #include <linux/of_dma.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/reset.h> 22 #include <linux/slab.h> 23 #include <linux/spinlock.h> 24 25 #define STM32_DMAMUX_CCR(x) (0x4 * (x)) 26 #define STM32_DMAMUX_MAX_DMA_REQUESTS 32 27 #define STM32_DMAMUX_MAX_REQUESTS 255 28 29 struct stm32_dmamux { 30 u32 master; 31 u32 request; 32 u32 chan_id; 33 }; 34 35 struct stm32_dmamux_data { 36 struct dma_router dmarouter; 37 struct clk *clk; 38 void __iomem *iomem; 39 u32 dma_requests; /* Number of DMA requests connected to DMAMUX */ 40 u32 dmamux_requests; /* Number of DMA requests routed toward DMAs */ 41 spinlock_t lock; /* Protects register access */ 42 DECLARE_BITMAP(dma_inuse, STM32_DMAMUX_MAX_DMA_REQUESTS); /* Used DMA channel */ 43 u32 ccr[STM32_DMAMUX_MAX_DMA_REQUESTS]; /* Used to backup CCR register 44 * in suspend 45 */ 46 u32 dma_reqs[]; /* Number of DMA Request per DMA masters. 47 * [0] holds number of DMA Masters. 48 * To be kept at very end of this structure 49 */ 50 }; 51 52 static inline u32 stm32_dmamux_read(void __iomem *iomem, u32 reg) 53 { 54 return readl_relaxed(iomem + reg); 55 } 56 57 static inline void stm32_dmamux_write(void __iomem *iomem, u32 reg, u32 val) 58 { 59 writel_relaxed(val, iomem + reg); 60 } 61 62 static void stm32_dmamux_free(struct device *dev, void *route_data) 63 { 64 struct stm32_dmamux_data *dmamux = dev_get_drvdata(dev); 65 struct stm32_dmamux *mux = route_data; 66 unsigned long flags; 67 68 /* Clear dma request */ 69 spin_lock_irqsave(&dmamux->lock, flags); 70 71 stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id), 0); 72 clear_bit(mux->chan_id, dmamux->dma_inuse); 73 74 pm_runtime_put_sync(dev); 75 76 spin_unlock_irqrestore(&dmamux->lock, flags); 77 78 dev_dbg(dev, "Unmapping DMAMUX(%u) to DMA%u(%u)\n", 79 mux->request, mux->master, mux->chan_id); 80 81 kfree(mux); 82 } 83 84 static void *stm32_dmamux_route_allocate(struct of_phandle_args *dma_spec, 85 struct of_dma *ofdma) 86 { 87 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); 88 struct stm32_dmamux_data *dmamux = platform_get_drvdata(pdev); 89 struct stm32_dmamux *mux; 90 u32 i, min, max; 91 int ret; 92 unsigned long flags; 93 94 if (dma_spec->args_count != 3) { 95 dev_err(&pdev->dev, "invalid number of dma mux args\n"); 96 return ERR_PTR(-EINVAL); 97 } 98 99 if (dma_spec->args[0] > dmamux->dmamux_requests) { 100 dev_err(&pdev->dev, "invalid mux request number: %d\n", 101 dma_spec->args[0]); 102 return ERR_PTR(-EINVAL); 103 } 104 105 mux = kzalloc(sizeof(*mux), GFP_KERNEL); 106 if (!mux) 107 return ERR_PTR(-ENOMEM); 108 109 spin_lock_irqsave(&dmamux->lock, flags); 110 mux->chan_id = find_first_zero_bit(dmamux->dma_inuse, 111 dmamux->dma_requests); 112 113 if (mux->chan_id == dmamux->dma_requests) { 114 spin_unlock_irqrestore(&dmamux->lock, flags); 115 dev_err(&pdev->dev, "Run out of free DMA requests\n"); 116 ret = -ENOMEM; 117 goto error_chan_id; 118 } 119 set_bit(mux->chan_id, dmamux->dma_inuse); 120 spin_unlock_irqrestore(&dmamux->lock, flags); 121 122 /* Look for DMA Master */ 123 for (i = 1, min = 0, max = dmamux->dma_reqs[i]; 124 i <= dmamux->dma_reqs[0]; 125 min += dmamux->dma_reqs[i], max += dmamux->dma_reqs[++i]) 126 if (mux->chan_id < max) 127 break; 128 mux->master = i - 1; 129 130 /* The of_node_put() will be done in of_dma_router_xlate function */ 131 dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", i - 1); 132 if (!dma_spec->np) { 133 dev_err(&pdev->dev, "can't get dma master\n"); 134 ret = -EINVAL; 135 goto error; 136 } 137 138 /* Set dma request */ 139 spin_lock_irqsave(&dmamux->lock, flags); 140 ret = pm_runtime_resume_and_get(&pdev->dev); 141 if (ret < 0) { 142 spin_unlock_irqrestore(&dmamux->lock, flags); 143 goto error; 144 } 145 spin_unlock_irqrestore(&dmamux->lock, flags); 146 147 mux->request = dma_spec->args[0]; 148 149 /* craft DMA spec */ 150 dma_spec->args[3] = dma_spec->args[2] | mux->chan_id << 16; 151 dma_spec->args[2] = dma_spec->args[1]; 152 dma_spec->args[1] = 0; 153 dma_spec->args[0] = mux->chan_id - min; 154 dma_spec->args_count = 4; 155 156 stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id), 157 mux->request); 158 dev_dbg(&pdev->dev, "Mapping DMAMUX(%u) to DMA%u(%u)\n", 159 mux->request, mux->master, mux->chan_id); 160 161 return mux; 162 163 error: 164 clear_bit(mux->chan_id, dmamux->dma_inuse); 165 166 error_chan_id: 167 kfree(mux); 168 return ERR_PTR(ret); 169 } 170 171 static const struct of_device_id stm32_stm32dma_master_match[] __maybe_unused = { 172 { .compatible = "st,stm32-dma", }, 173 {}, 174 }; 175 176 static int stm32_dmamux_probe(struct platform_device *pdev) 177 { 178 struct device_node *node = pdev->dev.of_node; 179 const struct of_device_id *match; 180 struct device_node *dma_node; 181 struct stm32_dmamux_data *stm32_dmamux; 182 void __iomem *iomem; 183 struct reset_control *rst; 184 int i, count, ret; 185 u32 dma_req; 186 187 if (!node) 188 return -ENODEV; 189 190 count = device_property_count_u32(&pdev->dev, "dma-masters"); 191 if (count < 0) { 192 dev_err(&pdev->dev, "Can't get DMA master(s) node\n"); 193 return -ENODEV; 194 } 195 196 stm32_dmamux = devm_kzalloc(&pdev->dev, sizeof(*stm32_dmamux) + 197 sizeof(u32) * (count + 1), GFP_KERNEL); 198 if (!stm32_dmamux) 199 return -ENOMEM; 200 201 dma_req = 0; 202 for (i = 1; i <= count; i++) { 203 dma_node = of_parse_phandle(node, "dma-masters", i - 1); 204 205 match = of_match_node(stm32_stm32dma_master_match, dma_node); 206 if (!match) { 207 dev_err(&pdev->dev, "DMA master is not supported\n"); 208 of_node_put(dma_node); 209 return -EINVAL; 210 } 211 212 if (of_property_read_u32(dma_node, "dma-requests", 213 &stm32_dmamux->dma_reqs[i])) { 214 dev_info(&pdev->dev, 215 "Missing MUX output information, using %u.\n", 216 STM32_DMAMUX_MAX_DMA_REQUESTS); 217 stm32_dmamux->dma_reqs[i] = 218 STM32_DMAMUX_MAX_DMA_REQUESTS; 219 } 220 dma_req += stm32_dmamux->dma_reqs[i]; 221 of_node_put(dma_node); 222 } 223 224 if (dma_req > STM32_DMAMUX_MAX_DMA_REQUESTS) { 225 dev_err(&pdev->dev, "Too many DMA Master Requests to manage\n"); 226 return -ENODEV; 227 } 228 229 stm32_dmamux->dma_requests = dma_req; 230 stm32_dmamux->dma_reqs[0] = count; 231 232 if (device_property_read_u32(&pdev->dev, "dma-requests", 233 &stm32_dmamux->dmamux_requests)) { 234 stm32_dmamux->dmamux_requests = STM32_DMAMUX_MAX_REQUESTS; 235 dev_warn(&pdev->dev, "DMAMUX defaulting on %u requests\n", 236 stm32_dmamux->dmamux_requests); 237 } 238 pm_runtime_get_noresume(&pdev->dev); 239 240 iomem = devm_platform_ioremap_resource(pdev, 0); 241 if (IS_ERR(iomem)) 242 return PTR_ERR(iomem); 243 244 spin_lock_init(&stm32_dmamux->lock); 245 246 stm32_dmamux->clk = devm_clk_get(&pdev->dev, NULL); 247 if (IS_ERR(stm32_dmamux->clk)) 248 return dev_err_probe(&pdev->dev, PTR_ERR(stm32_dmamux->clk), 249 "Missing clock controller\n"); 250 251 ret = clk_prepare_enable(stm32_dmamux->clk); 252 if (ret < 0) { 253 dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret); 254 return ret; 255 } 256 257 rst = devm_reset_control_get(&pdev->dev, NULL); 258 if (IS_ERR(rst)) { 259 ret = PTR_ERR(rst); 260 if (ret == -EPROBE_DEFER) 261 goto err_clk; 262 } else if (count > 1) { /* Don't reset if there is only one dma-master */ 263 reset_control_assert(rst); 264 udelay(2); 265 reset_control_deassert(rst); 266 } 267 268 stm32_dmamux->iomem = iomem; 269 stm32_dmamux->dmarouter.dev = &pdev->dev; 270 stm32_dmamux->dmarouter.route_free = stm32_dmamux_free; 271 272 platform_set_drvdata(pdev, stm32_dmamux); 273 pm_runtime_set_active(&pdev->dev); 274 pm_runtime_enable(&pdev->dev); 275 276 pm_runtime_get_noresume(&pdev->dev); 277 278 /* Reset the dmamux */ 279 for (i = 0; i < stm32_dmamux->dma_requests; i++) 280 stm32_dmamux_write(stm32_dmamux->iomem, STM32_DMAMUX_CCR(i), 0); 281 282 pm_runtime_put(&pdev->dev); 283 284 ret = of_dma_router_register(node, stm32_dmamux_route_allocate, 285 &stm32_dmamux->dmarouter); 286 if (ret) 287 goto pm_disable; 288 289 return 0; 290 291 pm_disable: 292 pm_runtime_disable(&pdev->dev); 293 err_clk: 294 clk_disable_unprepare(stm32_dmamux->clk); 295 296 return ret; 297 } 298 299 #ifdef CONFIG_PM 300 static int stm32_dmamux_runtime_suspend(struct device *dev) 301 { 302 struct platform_device *pdev = to_platform_device(dev); 303 struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev); 304 305 clk_disable_unprepare(stm32_dmamux->clk); 306 307 return 0; 308 } 309 310 static int stm32_dmamux_runtime_resume(struct device *dev) 311 { 312 struct platform_device *pdev = to_platform_device(dev); 313 struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev); 314 int ret; 315 316 ret = clk_prepare_enable(stm32_dmamux->clk); 317 if (ret) { 318 dev_err(&pdev->dev, "failed to prepare_enable clock\n"); 319 return ret; 320 } 321 322 return 0; 323 } 324 #endif 325 326 #ifdef CONFIG_PM_SLEEP 327 static int stm32_dmamux_suspend(struct device *dev) 328 { 329 struct platform_device *pdev = to_platform_device(dev); 330 struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev); 331 int i, ret; 332 333 ret = pm_runtime_resume_and_get(dev); 334 if (ret < 0) 335 return ret; 336 337 for (i = 0; i < stm32_dmamux->dma_requests; i++) 338 stm32_dmamux->ccr[i] = stm32_dmamux_read(stm32_dmamux->iomem, 339 STM32_DMAMUX_CCR(i)); 340 341 pm_runtime_put_sync(dev); 342 343 pm_runtime_force_suspend(dev); 344 345 return 0; 346 } 347 348 static int stm32_dmamux_resume(struct device *dev) 349 { 350 struct platform_device *pdev = to_platform_device(dev); 351 struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev); 352 int i, ret; 353 354 ret = pm_runtime_force_resume(dev); 355 if (ret < 0) 356 return ret; 357 358 ret = pm_runtime_resume_and_get(dev); 359 if (ret < 0) 360 return ret; 361 362 for (i = 0; i < stm32_dmamux->dma_requests; i++) 363 stm32_dmamux_write(stm32_dmamux->iomem, STM32_DMAMUX_CCR(i), 364 stm32_dmamux->ccr[i]); 365 366 pm_runtime_put_sync(dev); 367 368 return 0; 369 } 370 #endif 371 372 static const struct dev_pm_ops stm32_dmamux_pm_ops = { 373 SET_SYSTEM_SLEEP_PM_OPS(stm32_dmamux_suspend, stm32_dmamux_resume) 374 SET_RUNTIME_PM_OPS(stm32_dmamux_runtime_suspend, 375 stm32_dmamux_runtime_resume, NULL) 376 }; 377 378 static const struct of_device_id stm32_dmamux_match[] = { 379 { .compatible = "st,stm32h7-dmamux" }, 380 {}, 381 }; 382 383 static struct platform_driver stm32_dmamux_driver = { 384 .probe = stm32_dmamux_probe, 385 .driver = { 386 .name = "stm32-dmamux", 387 .of_match_table = stm32_dmamux_match, 388 .pm = &stm32_dmamux_pm_ops, 389 }, 390 }; 391 392 static int __init stm32_dmamux_init(void) 393 { 394 return platform_driver_register(&stm32_dmamux_driver); 395 } 396 arch_initcall(stm32_dmamux_init); 397 398 MODULE_DESCRIPTION("DMA Router driver for STM32 DMA MUX"); 399 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>"); 400 MODULE_AUTHOR("Pierre-Yves Mordret <pierre-yves.mordret@st.com>"); 401