1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for STM32 DMA controller 4 * 5 * Inspired by dma-jz4740.c and tegra20-apb-dma.c 6 * 7 * Copyright (C) M'boumba Cedric Madianga 2015 8 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 9 * Pierre-Yves Mordret <pierre-yves.mordret@st.com> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dmaengine.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/err.h> 17 #include <linux/init.h> 18 #include <linux/iopoll.h> 19 #include <linux/jiffies.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/of_dma.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/reset.h> 28 #include <linux/sched.h> 29 #include <linux/slab.h> 30 31 #include "virt-dma.h" 32 33 #define STM32_DMA_LISR 0x0000 /* DMA Low Int Status Reg */ 34 #define STM32_DMA_HISR 0x0004 /* DMA High Int Status Reg */ 35 #define STM32_DMA_LIFCR 0x0008 /* DMA Low Int Flag Clear Reg */ 36 #define STM32_DMA_HIFCR 0x000c /* DMA High Int Flag Clear Reg */ 37 #define STM32_DMA_TCI BIT(5) /* Transfer Complete Interrupt */ 38 #define STM32_DMA_HTI BIT(4) /* Half Transfer Interrupt */ 39 #define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */ 40 #define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */ 41 #define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */ 42 #define STM32_DMA_MASKI (STM32_DMA_TCI \ 43 | STM32_DMA_TEI \ 44 | STM32_DMA_DMEI \ 45 | STM32_DMA_FEI) 46 47 /* DMA Stream x Configuration Register */ 48 #define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */ 49 #define STM32_DMA_SCR_REQ(n) ((n & 0x7) << 25) 50 #define STM32_DMA_SCR_MBURST_MASK GENMASK(24, 23) 51 #define STM32_DMA_SCR_MBURST(n) ((n & 0x3) << 23) 52 #define STM32_DMA_SCR_PBURST_MASK GENMASK(22, 21) 53 #define STM32_DMA_SCR_PBURST(n) ((n & 0x3) << 21) 54 #define STM32_DMA_SCR_PL_MASK GENMASK(17, 16) 55 #define STM32_DMA_SCR_PL(n) ((n & 0x3) << 16) 56 #define STM32_DMA_SCR_MSIZE_MASK GENMASK(14, 13) 57 #define STM32_DMA_SCR_MSIZE(n) ((n & 0x3) << 13) 58 #define STM32_DMA_SCR_PSIZE_MASK GENMASK(12, 11) 59 #define STM32_DMA_SCR_PSIZE(n) ((n & 0x3) << 11) 60 #define STM32_DMA_SCR_PSIZE_GET(n) ((n & STM32_DMA_SCR_PSIZE_MASK) >> 11) 61 #define STM32_DMA_SCR_DIR_MASK GENMASK(7, 6) 62 #define STM32_DMA_SCR_DIR(n) ((n & 0x3) << 6) 63 #define STM32_DMA_SCR_TRBUFF BIT(20) /* Bufferable transfer for USART/UART */ 64 #define STM32_DMA_SCR_CT BIT(19) /* Target in double buffer */ 65 #define STM32_DMA_SCR_DBM BIT(18) /* Double Buffer Mode */ 66 #define STM32_DMA_SCR_PINCOS BIT(15) /* Peripheral inc offset size */ 67 #define STM32_DMA_SCR_MINC BIT(10) /* Memory increment mode */ 68 #define STM32_DMA_SCR_PINC BIT(9) /* Peripheral increment mode */ 69 #define STM32_DMA_SCR_CIRC BIT(8) /* Circular mode */ 70 #define STM32_DMA_SCR_PFCTRL BIT(5) /* Peripheral Flow Controller */ 71 #define STM32_DMA_SCR_TCIE BIT(4) /* Transfer Complete Int Enable 72 */ 73 #define STM32_DMA_SCR_TEIE BIT(2) /* Transfer Error Int Enable */ 74 #define STM32_DMA_SCR_DMEIE BIT(1) /* Direct Mode Err Int Enable */ 75 #define STM32_DMA_SCR_EN BIT(0) /* Stream Enable */ 76 #define STM32_DMA_SCR_CFG_MASK (STM32_DMA_SCR_PINC \ 77 | STM32_DMA_SCR_MINC \ 78 | STM32_DMA_SCR_PINCOS \ 79 | STM32_DMA_SCR_PL_MASK) 80 #define STM32_DMA_SCR_IRQ_MASK (STM32_DMA_SCR_TCIE \ 81 | STM32_DMA_SCR_TEIE \ 82 | STM32_DMA_SCR_DMEIE) 83 84 /* DMA Stream x number of data register */ 85 #define STM32_DMA_SNDTR(x) (0x0014 + 0x18 * (x)) 86 87 /* DMA stream peripheral address register */ 88 #define STM32_DMA_SPAR(x) (0x0018 + 0x18 * (x)) 89 90 /* DMA stream x memory 0 address register */ 91 #define STM32_DMA_SM0AR(x) (0x001c + 0x18 * (x)) 92 93 /* DMA stream x memory 1 address register */ 94 #define STM32_DMA_SM1AR(x) (0x0020 + 0x18 * (x)) 95 96 /* DMA stream x FIFO control register */ 97 #define STM32_DMA_SFCR(x) (0x0024 + 0x18 * (x)) 98 #define STM32_DMA_SFCR_FTH_MASK GENMASK(1, 0) 99 #define STM32_DMA_SFCR_FTH(n) (n & STM32_DMA_SFCR_FTH_MASK) 100 #define STM32_DMA_SFCR_FEIE BIT(7) /* FIFO error interrupt enable */ 101 #define STM32_DMA_SFCR_DMDIS BIT(2) /* Direct mode disable */ 102 #define STM32_DMA_SFCR_MASK (STM32_DMA_SFCR_FEIE \ 103 | STM32_DMA_SFCR_DMDIS) 104 105 /* DMA direction */ 106 #define STM32_DMA_DEV_TO_MEM 0x00 107 #define STM32_DMA_MEM_TO_DEV 0x01 108 #define STM32_DMA_MEM_TO_MEM 0x02 109 110 /* DMA priority level */ 111 #define STM32_DMA_PRIORITY_LOW 0x00 112 #define STM32_DMA_PRIORITY_MEDIUM 0x01 113 #define STM32_DMA_PRIORITY_HIGH 0x02 114 #define STM32_DMA_PRIORITY_VERY_HIGH 0x03 115 116 /* DMA FIFO threshold selection */ 117 #define STM32_DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00 118 #define STM32_DMA_FIFO_THRESHOLD_HALFFULL 0x01 119 #define STM32_DMA_FIFO_THRESHOLD_3QUARTERSFULL 0x02 120 #define STM32_DMA_FIFO_THRESHOLD_FULL 0x03 121 #define STM32_DMA_FIFO_THRESHOLD_NONE 0x04 122 123 #define STM32_DMA_MAX_DATA_ITEMS 0xffff 124 /* 125 * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter 126 * gather at boundary. Thus it's safer to round down this value on FIFO 127 * size (16 Bytes) 128 */ 129 #define STM32_DMA_ALIGNED_MAX_DATA_ITEMS \ 130 ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16) 131 #define STM32_DMA_MAX_CHANNELS 0x08 132 #define STM32_DMA_MAX_REQUEST_ID 0x08 133 #define STM32_DMA_MAX_DATA_PARAM 0x03 134 #define STM32_DMA_FIFO_SIZE 16 /* FIFO is 16 bytes */ 135 #define STM32_DMA_MIN_BURST 4 136 #define STM32_DMA_MAX_BURST 16 137 138 /* DMA Features */ 139 #define STM32_DMA_THRESHOLD_FTR_MASK GENMASK(1, 0) 140 #define STM32_DMA_THRESHOLD_FTR_GET(n) ((n) & STM32_DMA_THRESHOLD_FTR_MASK) 141 #define STM32_DMA_DIRECT_MODE_MASK BIT(2) 142 #define STM32_DMA_DIRECT_MODE_GET(n) (((n) & STM32_DMA_DIRECT_MODE_MASK) >> 2) 143 #define STM32_DMA_ALT_ACK_MODE_MASK BIT(4) 144 #define STM32_DMA_ALT_ACK_MODE_GET(n) (((n) & STM32_DMA_ALT_ACK_MODE_MASK) >> 4) 145 146 enum stm32_dma_width { 147 STM32_DMA_BYTE, 148 STM32_DMA_HALF_WORD, 149 STM32_DMA_WORD, 150 }; 151 152 enum stm32_dma_burst_size { 153 STM32_DMA_BURST_SINGLE, 154 STM32_DMA_BURST_INCR4, 155 STM32_DMA_BURST_INCR8, 156 STM32_DMA_BURST_INCR16, 157 }; 158 159 /** 160 * struct stm32_dma_cfg - STM32 DMA custom configuration 161 * @channel_id: channel ID 162 * @request_line: DMA request 163 * @stream_config: 32bit mask specifying the DMA channel configuration 164 * @features: 32bit mask specifying the DMA Feature list 165 */ 166 struct stm32_dma_cfg { 167 u32 channel_id; 168 u32 request_line; 169 u32 stream_config; 170 u32 features; 171 }; 172 173 struct stm32_dma_chan_reg { 174 u32 dma_lisr; 175 u32 dma_hisr; 176 u32 dma_lifcr; 177 u32 dma_hifcr; 178 u32 dma_scr; 179 u32 dma_sndtr; 180 u32 dma_spar; 181 u32 dma_sm0ar; 182 u32 dma_sm1ar; 183 u32 dma_sfcr; 184 }; 185 186 struct stm32_dma_sg_req { 187 u32 len; 188 struct stm32_dma_chan_reg chan_reg; 189 }; 190 191 struct stm32_dma_desc { 192 struct virt_dma_desc vdesc; 193 bool cyclic; 194 u32 num_sgs; 195 struct stm32_dma_sg_req sg_req[]; 196 }; 197 198 struct stm32_dma_chan { 199 struct virt_dma_chan vchan; 200 bool config_init; 201 bool busy; 202 u32 id; 203 u32 irq; 204 struct stm32_dma_desc *desc; 205 u32 next_sg; 206 struct dma_slave_config dma_sconfig; 207 struct stm32_dma_chan_reg chan_reg; 208 u32 threshold; 209 u32 mem_burst; 210 u32 mem_width; 211 }; 212 213 struct stm32_dma_device { 214 struct dma_device ddev; 215 void __iomem *base; 216 struct clk *clk; 217 bool mem2mem; 218 struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS]; 219 }; 220 221 static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan) 222 { 223 return container_of(chan->vchan.chan.device, struct stm32_dma_device, 224 ddev); 225 } 226 227 static struct stm32_dma_chan *to_stm32_dma_chan(struct dma_chan *c) 228 { 229 return container_of(c, struct stm32_dma_chan, vchan.chan); 230 } 231 232 static struct stm32_dma_desc *to_stm32_dma_desc(struct virt_dma_desc *vdesc) 233 { 234 return container_of(vdesc, struct stm32_dma_desc, vdesc); 235 } 236 237 static struct device *chan2dev(struct stm32_dma_chan *chan) 238 { 239 return &chan->vchan.chan.dev->device; 240 } 241 242 static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg) 243 { 244 return readl_relaxed(dmadev->base + reg); 245 } 246 247 static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val) 248 { 249 writel_relaxed(val, dmadev->base + reg); 250 } 251 252 static int stm32_dma_get_width(struct stm32_dma_chan *chan, 253 enum dma_slave_buswidth width) 254 { 255 switch (width) { 256 case DMA_SLAVE_BUSWIDTH_1_BYTE: 257 return STM32_DMA_BYTE; 258 case DMA_SLAVE_BUSWIDTH_2_BYTES: 259 return STM32_DMA_HALF_WORD; 260 case DMA_SLAVE_BUSWIDTH_4_BYTES: 261 return STM32_DMA_WORD; 262 default: 263 dev_err(chan2dev(chan), "Dma bus width not supported\n"); 264 return -EINVAL; 265 } 266 } 267 268 static enum dma_slave_buswidth stm32_dma_get_max_width(u32 buf_len, 269 dma_addr_t buf_addr, 270 u32 threshold) 271 { 272 enum dma_slave_buswidth max_width; 273 274 if (threshold == STM32_DMA_FIFO_THRESHOLD_FULL) 275 max_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 276 else 277 max_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 278 279 while ((buf_len < max_width || buf_len % max_width) && 280 max_width > DMA_SLAVE_BUSWIDTH_1_BYTE) 281 max_width = max_width >> 1; 282 283 if (buf_addr & (max_width - 1)) 284 max_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 285 286 return max_width; 287 } 288 289 static bool stm32_dma_fifo_threshold_is_allowed(u32 burst, u32 threshold, 290 enum dma_slave_buswidth width) 291 { 292 u32 remaining; 293 294 if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE) 295 return false; 296 297 if (width != DMA_SLAVE_BUSWIDTH_UNDEFINED) { 298 if (burst != 0) { 299 /* 300 * If number of beats fit in several whole bursts 301 * this configuration is allowed. 302 */ 303 remaining = ((STM32_DMA_FIFO_SIZE / width) * 304 (threshold + 1) / 4) % burst; 305 306 if (remaining == 0) 307 return true; 308 } else { 309 return true; 310 } 311 } 312 313 return false; 314 } 315 316 static bool stm32_dma_is_burst_possible(u32 buf_len, u32 threshold) 317 { 318 /* If FIFO direct mode, burst is not possible */ 319 if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE) 320 return false; 321 322 /* 323 * Buffer or period length has to be aligned on FIFO depth. 324 * Otherwise bytes may be stuck within FIFO at buffer or period 325 * length. 326 */ 327 return ((buf_len % ((threshold + 1) * 4)) == 0); 328 } 329 330 static u32 stm32_dma_get_best_burst(u32 buf_len, u32 max_burst, u32 threshold, 331 enum dma_slave_buswidth width) 332 { 333 u32 best_burst = max_burst; 334 335 if (best_burst == 1 || !stm32_dma_is_burst_possible(buf_len, threshold)) 336 return 0; 337 338 while ((buf_len < best_burst * width && best_burst > 1) || 339 !stm32_dma_fifo_threshold_is_allowed(best_burst, threshold, 340 width)) { 341 if (best_burst > STM32_DMA_MIN_BURST) 342 best_burst = best_burst >> 1; 343 else 344 best_burst = 0; 345 } 346 347 return best_burst; 348 } 349 350 static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst) 351 { 352 switch (maxburst) { 353 case 0: 354 case 1: 355 return STM32_DMA_BURST_SINGLE; 356 case 4: 357 return STM32_DMA_BURST_INCR4; 358 case 8: 359 return STM32_DMA_BURST_INCR8; 360 case 16: 361 return STM32_DMA_BURST_INCR16; 362 default: 363 dev_err(chan2dev(chan), "Dma burst size not supported\n"); 364 return -EINVAL; 365 } 366 } 367 368 static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan, 369 u32 src_burst, u32 dst_burst) 370 { 371 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK; 372 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE; 373 374 if (!src_burst && !dst_burst) { 375 /* Using direct mode */ 376 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE; 377 } else { 378 /* Using FIFO mode */ 379 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; 380 } 381 } 382 383 static int stm32_dma_slave_config(struct dma_chan *c, 384 struct dma_slave_config *config) 385 { 386 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 387 388 memcpy(&chan->dma_sconfig, config, sizeof(*config)); 389 390 chan->config_init = true; 391 392 return 0; 393 } 394 395 static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan) 396 { 397 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 398 u32 flags, dma_isr; 399 400 /* 401 * Read "flags" from DMA_xISR register corresponding to the selected 402 * DMA channel at the correct bit offset inside that register. 403 * 404 * If (ch % 4) is 2 or 3, left shift the mask by 16 bits. 405 * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. 406 */ 407 408 if (chan->id & 4) 409 dma_isr = stm32_dma_read(dmadev, STM32_DMA_HISR); 410 else 411 dma_isr = stm32_dma_read(dmadev, STM32_DMA_LISR); 412 413 flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); 414 415 return flags & STM32_DMA_MASKI; 416 } 417 418 static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags) 419 { 420 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 421 u32 dma_ifcr; 422 423 /* 424 * Write "flags" to the DMA_xIFCR register corresponding to the selected 425 * DMA channel at the correct bit offset inside that register. 426 * 427 * If (ch % 4) is 2 or 3, left shift the mask by 16 bits. 428 * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. 429 */ 430 flags &= STM32_DMA_MASKI; 431 dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); 432 433 if (chan->id & 4) 434 stm32_dma_write(dmadev, STM32_DMA_HIFCR, dma_ifcr); 435 else 436 stm32_dma_write(dmadev, STM32_DMA_LIFCR, dma_ifcr); 437 } 438 439 static int stm32_dma_disable_chan(struct stm32_dma_chan *chan) 440 { 441 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 442 u32 dma_scr, id, reg; 443 444 id = chan->id; 445 reg = STM32_DMA_SCR(id); 446 dma_scr = stm32_dma_read(dmadev, reg); 447 448 if (dma_scr & STM32_DMA_SCR_EN) { 449 dma_scr &= ~STM32_DMA_SCR_EN; 450 stm32_dma_write(dmadev, reg, dma_scr); 451 452 return readl_relaxed_poll_timeout_atomic(dmadev->base + reg, 453 dma_scr, !(dma_scr & STM32_DMA_SCR_EN), 454 10, 1000000); 455 } 456 457 return 0; 458 } 459 460 static void stm32_dma_stop(struct stm32_dma_chan *chan) 461 { 462 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 463 u32 dma_scr, dma_sfcr, status; 464 int ret; 465 466 /* Disable interrupts */ 467 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 468 dma_scr &= ~STM32_DMA_SCR_IRQ_MASK; 469 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); 470 dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); 471 dma_sfcr &= ~STM32_DMA_SFCR_FEIE; 472 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr); 473 474 /* Disable DMA */ 475 ret = stm32_dma_disable_chan(chan); 476 if (ret < 0) 477 return; 478 479 /* Clear interrupt status if it is there */ 480 status = stm32_dma_irq_status(chan); 481 if (status) { 482 dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n", 483 __func__, status); 484 stm32_dma_irq_clear(chan, status); 485 } 486 487 chan->busy = false; 488 } 489 490 static int stm32_dma_terminate_all(struct dma_chan *c) 491 { 492 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 493 unsigned long flags; 494 LIST_HEAD(head); 495 496 spin_lock_irqsave(&chan->vchan.lock, flags); 497 498 if (chan->desc) { 499 dma_cookie_complete(&chan->desc->vdesc.tx); 500 vchan_terminate_vdesc(&chan->desc->vdesc); 501 if (chan->busy) 502 stm32_dma_stop(chan); 503 chan->desc = NULL; 504 } 505 506 vchan_get_all_descriptors(&chan->vchan, &head); 507 spin_unlock_irqrestore(&chan->vchan.lock, flags); 508 vchan_dma_desc_free_list(&chan->vchan, &head); 509 510 return 0; 511 } 512 513 static void stm32_dma_synchronize(struct dma_chan *c) 514 { 515 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 516 517 vchan_synchronize(&chan->vchan); 518 } 519 520 static void stm32_dma_dump_reg(struct stm32_dma_chan *chan) 521 { 522 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 523 u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 524 u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); 525 u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id)); 526 u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id)); 527 u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id)); 528 u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); 529 530 dev_dbg(chan2dev(chan), "SCR: 0x%08x\n", scr); 531 dev_dbg(chan2dev(chan), "NDTR: 0x%08x\n", ndtr); 532 dev_dbg(chan2dev(chan), "SPAR: 0x%08x\n", spar); 533 dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar); 534 dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar); 535 dev_dbg(chan2dev(chan), "SFCR: 0x%08x\n", sfcr); 536 } 537 538 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan); 539 540 static void stm32_dma_start_transfer(struct stm32_dma_chan *chan) 541 { 542 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 543 struct virt_dma_desc *vdesc; 544 struct stm32_dma_sg_req *sg_req; 545 struct stm32_dma_chan_reg *reg; 546 u32 status; 547 int ret; 548 549 ret = stm32_dma_disable_chan(chan); 550 if (ret < 0) 551 return; 552 553 if (!chan->desc) { 554 vdesc = vchan_next_desc(&chan->vchan); 555 if (!vdesc) 556 return; 557 558 list_del(&vdesc->node); 559 560 chan->desc = to_stm32_dma_desc(vdesc); 561 chan->next_sg = 0; 562 } 563 564 if (chan->next_sg == chan->desc->num_sgs) 565 chan->next_sg = 0; 566 567 sg_req = &chan->desc->sg_req[chan->next_sg]; 568 reg = &sg_req->chan_reg; 569 570 reg->dma_scr &= ~STM32_DMA_SCR_EN; 571 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); 572 stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar); 573 stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar); 574 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr); 575 stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar); 576 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr); 577 578 chan->next_sg++; 579 580 /* Clear interrupt status if it is there */ 581 status = stm32_dma_irq_status(chan); 582 if (status) 583 stm32_dma_irq_clear(chan, status); 584 585 if (chan->desc->cyclic) 586 stm32_dma_configure_next_sg(chan); 587 588 stm32_dma_dump_reg(chan); 589 590 /* Start DMA */ 591 reg->dma_scr |= STM32_DMA_SCR_EN; 592 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); 593 594 chan->busy = true; 595 596 dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan); 597 } 598 599 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan) 600 { 601 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 602 struct stm32_dma_sg_req *sg_req; 603 u32 dma_scr, dma_sm0ar, dma_sm1ar, id; 604 605 id = chan->id; 606 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); 607 608 if (dma_scr & STM32_DMA_SCR_DBM) { 609 if (chan->next_sg == chan->desc->num_sgs) 610 chan->next_sg = 0; 611 612 sg_req = &chan->desc->sg_req[chan->next_sg]; 613 614 if (dma_scr & STM32_DMA_SCR_CT) { 615 dma_sm0ar = sg_req->chan_reg.dma_sm0ar; 616 stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar); 617 dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n", 618 stm32_dma_read(dmadev, STM32_DMA_SM0AR(id))); 619 } else { 620 dma_sm1ar = sg_req->chan_reg.dma_sm1ar; 621 stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar); 622 dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n", 623 stm32_dma_read(dmadev, STM32_DMA_SM1AR(id))); 624 } 625 } 626 } 627 628 static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan) 629 { 630 if (chan->desc) { 631 if (chan->desc->cyclic) { 632 vchan_cyclic_callback(&chan->desc->vdesc); 633 chan->next_sg++; 634 stm32_dma_configure_next_sg(chan); 635 } else { 636 chan->busy = false; 637 if (chan->next_sg == chan->desc->num_sgs) { 638 vchan_cookie_complete(&chan->desc->vdesc); 639 chan->desc = NULL; 640 } 641 stm32_dma_start_transfer(chan); 642 } 643 } 644 } 645 646 static irqreturn_t stm32_dma_chan_irq(int irq, void *devid) 647 { 648 struct stm32_dma_chan *chan = devid; 649 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 650 u32 status, scr, sfcr; 651 652 spin_lock(&chan->vchan.lock); 653 654 status = stm32_dma_irq_status(chan); 655 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 656 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); 657 658 if (status & STM32_DMA_FEI) { 659 stm32_dma_irq_clear(chan, STM32_DMA_FEI); 660 status &= ~STM32_DMA_FEI; 661 if (sfcr & STM32_DMA_SFCR_FEIE) { 662 if (!(scr & STM32_DMA_SCR_EN) && 663 !(status & STM32_DMA_TCI)) 664 dev_err(chan2dev(chan), "FIFO Error\n"); 665 else 666 dev_dbg(chan2dev(chan), "FIFO over/underrun\n"); 667 } 668 } 669 if (status & STM32_DMA_DMEI) { 670 stm32_dma_irq_clear(chan, STM32_DMA_DMEI); 671 status &= ~STM32_DMA_DMEI; 672 if (sfcr & STM32_DMA_SCR_DMEIE) 673 dev_dbg(chan2dev(chan), "Direct mode overrun\n"); 674 } 675 676 if (status & STM32_DMA_TCI) { 677 stm32_dma_irq_clear(chan, STM32_DMA_TCI); 678 if (scr & STM32_DMA_SCR_TCIE) 679 stm32_dma_handle_chan_done(chan); 680 status &= ~STM32_DMA_TCI; 681 } 682 683 if (status & STM32_DMA_HTI) { 684 stm32_dma_irq_clear(chan, STM32_DMA_HTI); 685 status &= ~STM32_DMA_HTI; 686 } 687 688 if (status) { 689 stm32_dma_irq_clear(chan, status); 690 dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status); 691 if (!(scr & STM32_DMA_SCR_EN)) 692 dev_err(chan2dev(chan), "chan disabled by HW\n"); 693 } 694 695 spin_unlock(&chan->vchan.lock); 696 697 return IRQ_HANDLED; 698 } 699 700 static void stm32_dma_issue_pending(struct dma_chan *c) 701 { 702 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 703 unsigned long flags; 704 705 spin_lock_irqsave(&chan->vchan.lock, flags); 706 if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) { 707 dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan); 708 stm32_dma_start_transfer(chan); 709 710 } 711 spin_unlock_irqrestore(&chan->vchan.lock, flags); 712 } 713 714 static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan, 715 enum dma_transfer_direction direction, 716 enum dma_slave_buswidth *buswidth, 717 u32 buf_len, dma_addr_t buf_addr) 718 { 719 enum dma_slave_buswidth src_addr_width, dst_addr_width; 720 int src_bus_width, dst_bus_width; 721 int src_burst_size, dst_burst_size; 722 u32 src_maxburst, dst_maxburst, src_best_burst, dst_best_burst; 723 u32 dma_scr, fifoth; 724 725 src_addr_width = chan->dma_sconfig.src_addr_width; 726 dst_addr_width = chan->dma_sconfig.dst_addr_width; 727 src_maxburst = chan->dma_sconfig.src_maxburst; 728 dst_maxburst = chan->dma_sconfig.dst_maxburst; 729 fifoth = chan->threshold; 730 731 switch (direction) { 732 case DMA_MEM_TO_DEV: 733 /* Set device data size */ 734 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width); 735 if (dst_bus_width < 0) 736 return dst_bus_width; 737 738 /* Set device burst size */ 739 dst_best_burst = stm32_dma_get_best_burst(buf_len, 740 dst_maxburst, 741 fifoth, 742 dst_addr_width); 743 744 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst); 745 if (dst_burst_size < 0) 746 return dst_burst_size; 747 748 /* Set memory data size */ 749 src_addr_width = stm32_dma_get_max_width(buf_len, buf_addr, 750 fifoth); 751 chan->mem_width = src_addr_width; 752 src_bus_width = stm32_dma_get_width(chan, src_addr_width); 753 if (src_bus_width < 0) 754 return src_bus_width; 755 756 /* 757 * Set memory burst size - burst not possible if address is not aligned on 758 * the address boundary equal to the size of the transfer 759 */ 760 if (buf_addr & (buf_len - 1)) 761 src_maxburst = 1; 762 else 763 src_maxburst = STM32_DMA_MAX_BURST; 764 src_best_burst = stm32_dma_get_best_burst(buf_len, 765 src_maxburst, 766 fifoth, 767 src_addr_width); 768 src_burst_size = stm32_dma_get_burst(chan, src_best_burst); 769 if (src_burst_size < 0) 770 return src_burst_size; 771 772 dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_DEV) | 773 STM32_DMA_SCR_PSIZE(dst_bus_width) | 774 STM32_DMA_SCR_MSIZE(src_bus_width) | 775 STM32_DMA_SCR_PBURST(dst_burst_size) | 776 STM32_DMA_SCR_MBURST(src_burst_size); 777 778 /* Set FIFO threshold */ 779 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; 780 if (fifoth != STM32_DMA_FIFO_THRESHOLD_NONE) 781 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth); 782 783 /* Set peripheral address */ 784 chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr; 785 *buswidth = dst_addr_width; 786 break; 787 788 case DMA_DEV_TO_MEM: 789 /* Set device data size */ 790 src_bus_width = stm32_dma_get_width(chan, src_addr_width); 791 if (src_bus_width < 0) 792 return src_bus_width; 793 794 /* Set device burst size */ 795 src_best_burst = stm32_dma_get_best_burst(buf_len, 796 src_maxburst, 797 fifoth, 798 src_addr_width); 799 chan->mem_burst = src_best_burst; 800 src_burst_size = stm32_dma_get_burst(chan, src_best_burst); 801 if (src_burst_size < 0) 802 return src_burst_size; 803 804 /* Set memory data size */ 805 dst_addr_width = stm32_dma_get_max_width(buf_len, buf_addr, 806 fifoth); 807 chan->mem_width = dst_addr_width; 808 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width); 809 if (dst_bus_width < 0) 810 return dst_bus_width; 811 812 /* 813 * Set memory burst size - burst not possible if address is not aligned on 814 * the address boundary equal to the size of the transfer 815 */ 816 if (buf_addr & (buf_len - 1)) 817 dst_maxburst = 1; 818 else 819 dst_maxburst = STM32_DMA_MAX_BURST; 820 dst_best_burst = stm32_dma_get_best_burst(buf_len, 821 dst_maxburst, 822 fifoth, 823 dst_addr_width); 824 chan->mem_burst = dst_best_burst; 825 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst); 826 if (dst_burst_size < 0) 827 return dst_burst_size; 828 829 dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_DEV_TO_MEM) | 830 STM32_DMA_SCR_PSIZE(src_bus_width) | 831 STM32_DMA_SCR_MSIZE(dst_bus_width) | 832 STM32_DMA_SCR_PBURST(src_burst_size) | 833 STM32_DMA_SCR_MBURST(dst_burst_size); 834 835 /* Set FIFO threshold */ 836 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; 837 if (fifoth != STM32_DMA_FIFO_THRESHOLD_NONE) 838 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth); 839 840 /* Set peripheral address */ 841 chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr; 842 *buswidth = chan->dma_sconfig.src_addr_width; 843 break; 844 845 default: 846 dev_err(chan2dev(chan), "Dma direction is not supported\n"); 847 return -EINVAL; 848 } 849 850 stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst); 851 852 /* Set DMA control register */ 853 chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK | 854 STM32_DMA_SCR_PSIZE_MASK | STM32_DMA_SCR_MSIZE_MASK | 855 STM32_DMA_SCR_PBURST_MASK | STM32_DMA_SCR_MBURST_MASK); 856 chan->chan_reg.dma_scr |= dma_scr; 857 858 return 0; 859 } 860 861 static void stm32_dma_clear_reg(struct stm32_dma_chan_reg *regs) 862 { 863 memset(regs, 0, sizeof(struct stm32_dma_chan_reg)); 864 } 865 866 static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg( 867 struct dma_chan *c, struct scatterlist *sgl, 868 u32 sg_len, enum dma_transfer_direction direction, 869 unsigned long flags, void *context) 870 { 871 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 872 struct stm32_dma_desc *desc; 873 struct scatterlist *sg; 874 enum dma_slave_buswidth buswidth; 875 u32 nb_data_items; 876 int i, ret; 877 878 if (!chan->config_init) { 879 dev_err(chan2dev(chan), "dma channel is not configured\n"); 880 return NULL; 881 } 882 883 if (sg_len < 1) { 884 dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len); 885 return NULL; 886 } 887 888 desc = kzalloc(struct_size(desc, sg_req, sg_len), GFP_NOWAIT); 889 if (!desc) 890 return NULL; 891 892 /* Set peripheral flow controller */ 893 if (chan->dma_sconfig.device_fc) 894 chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL; 895 else 896 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; 897 898 for_each_sg(sgl, sg, sg_len, i) { 899 ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, 900 sg_dma_len(sg), 901 sg_dma_address(sg)); 902 if (ret < 0) 903 goto err; 904 905 desc->sg_req[i].len = sg_dma_len(sg); 906 907 nb_data_items = desc->sg_req[i].len / buswidth; 908 if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) { 909 dev_err(chan2dev(chan), "nb items not supported\n"); 910 goto err; 911 } 912 913 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); 914 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; 915 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; 916 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; 917 desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg); 918 desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg); 919 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items; 920 } 921 922 desc->num_sgs = sg_len; 923 desc->cyclic = false; 924 925 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); 926 927 err: 928 kfree(desc); 929 return NULL; 930 } 931 932 static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic( 933 struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len, 934 size_t period_len, enum dma_transfer_direction direction, 935 unsigned long flags) 936 { 937 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 938 struct stm32_dma_desc *desc; 939 enum dma_slave_buswidth buswidth; 940 u32 num_periods, nb_data_items; 941 int i, ret; 942 943 if (!buf_len || !period_len) { 944 dev_err(chan2dev(chan), "Invalid buffer/period len\n"); 945 return NULL; 946 } 947 948 if (!chan->config_init) { 949 dev_err(chan2dev(chan), "dma channel is not configured\n"); 950 return NULL; 951 } 952 953 if (buf_len % period_len) { 954 dev_err(chan2dev(chan), "buf_len not multiple of period_len\n"); 955 return NULL; 956 } 957 958 /* 959 * We allow to take more number of requests till DMA is 960 * not started. The driver will loop over all requests. 961 * Once DMA is started then new requests can be queued only after 962 * terminating the DMA. 963 */ 964 if (chan->busy) { 965 dev_err(chan2dev(chan), "Request not allowed when dma busy\n"); 966 return NULL; 967 } 968 969 ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len, 970 buf_addr); 971 if (ret < 0) 972 return NULL; 973 974 nb_data_items = period_len / buswidth; 975 if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) { 976 dev_err(chan2dev(chan), "number of items not supported\n"); 977 return NULL; 978 } 979 980 /* Enable Circular mode or double buffer mode */ 981 if (buf_len == period_len) 982 chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC; 983 else 984 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM; 985 986 /* Clear periph ctrl if client set it */ 987 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; 988 989 num_periods = buf_len / period_len; 990 991 desc = kzalloc(struct_size(desc, sg_req, num_periods), GFP_NOWAIT); 992 if (!desc) 993 return NULL; 994 995 for (i = 0; i < num_periods; i++) { 996 desc->sg_req[i].len = period_len; 997 998 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); 999 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; 1000 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; 1001 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; 1002 desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr; 1003 desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr; 1004 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items; 1005 buf_addr += period_len; 1006 } 1007 1008 desc->num_sgs = num_periods; 1009 desc->cyclic = true; 1010 1011 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); 1012 } 1013 1014 static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy( 1015 struct dma_chan *c, dma_addr_t dest, 1016 dma_addr_t src, size_t len, unsigned long flags) 1017 { 1018 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1019 enum dma_slave_buswidth max_width; 1020 struct stm32_dma_desc *desc; 1021 size_t xfer_count, offset; 1022 u32 num_sgs, best_burst, dma_burst, threshold; 1023 int i; 1024 1025 num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS); 1026 desc = kzalloc(struct_size(desc, sg_req, num_sgs), GFP_NOWAIT); 1027 if (!desc) 1028 return NULL; 1029 1030 threshold = chan->threshold; 1031 1032 for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) { 1033 xfer_count = min_t(size_t, len - offset, 1034 STM32_DMA_ALIGNED_MAX_DATA_ITEMS); 1035 1036 /* Compute best burst size */ 1037 max_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1038 best_burst = stm32_dma_get_best_burst(len, STM32_DMA_MAX_BURST, 1039 threshold, max_width); 1040 dma_burst = stm32_dma_get_burst(chan, best_burst); 1041 1042 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); 1043 desc->sg_req[i].chan_reg.dma_scr = 1044 STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_MEM) | 1045 STM32_DMA_SCR_PBURST(dma_burst) | 1046 STM32_DMA_SCR_MBURST(dma_burst) | 1047 STM32_DMA_SCR_MINC | 1048 STM32_DMA_SCR_PINC | 1049 STM32_DMA_SCR_TCIE | 1050 STM32_DMA_SCR_TEIE; 1051 desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; 1052 desc->sg_req[i].chan_reg.dma_sfcr |= 1053 STM32_DMA_SFCR_FTH(threshold); 1054 desc->sg_req[i].chan_reg.dma_spar = src + offset; 1055 desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset; 1056 desc->sg_req[i].chan_reg.dma_sndtr = xfer_count; 1057 desc->sg_req[i].len = xfer_count; 1058 } 1059 1060 desc->num_sgs = num_sgs; 1061 desc->cyclic = false; 1062 1063 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); 1064 } 1065 1066 static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan) 1067 { 1068 u32 dma_scr, width, ndtr; 1069 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 1070 1071 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 1072 width = STM32_DMA_SCR_PSIZE_GET(dma_scr); 1073 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); 1074 1075 return ndtr << width; 1076 } 1077 1078 /** 1079 * stm32_dma_is_current_sg - check that expected sg_req is currently transferred 1080 * @chan: dma channel 1081 * 1082 * This function called when IRQ are disable, checks that the hardware has not 1083 * switched on the next transfer in double buffer mode. The test is done by 1084 * comparing the next_sg memory address with the hardware related register 1085 * (based on CT bit value). 1086 * 1087 * Returns true if expected current transfer is still running or double 1088 * buffer mode is not activated. 1089 */ 1090 static bool stm32_dma_is_current_sg(struct stm32_dma_chan *chan) 1091 { 1092 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 1093 struct stm32_dma_sg_req *sg_req; 1094 u32 dma_scr, dma_smar, id; 1095 1096 id = chan->id; 1097 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); 1098 1099 if (!(dma_scr & STM32_DMA_SCR_DBM)) 1100 return true; 1101 1102 sg_req = &chan->desc->sg_req[chan->next_sg]; 1103 1104 if (dma_scr & STM32_DMA_SCR_CT) { 1105 dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)); 1106 return (dma_smar == sg_req->chan_reg.dma_sm0ar); 1107 } 1108 1109 dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)); 1110 1111 return (dma_smar == sg_req->chan_reg.dma_sm1ar); 1112 } 1113 1114 static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan, 1115 struct stm32_dma_desc *desc, 1116 u32 next_sg) 1117 { 1118 u32 modulo, burst_size; 1119 u32 residue; 1120 u32 n_sg = next_sg; 1121 struct stm32_dma_sg_req *sg_req = &chan->desc->sg_req[chan->next_sg]; 1122 int i; 1123 1124 /* 1125 * Calculate the residue means compute the descriptors 1126 * information: 1127 * - the sg_req currently transferred 1128 * - the Hardware remaining position in this sg (NDTR bits field). 1129 * 1130 * A race condition may occur if DMA is running in cyclic or double 1131 * buffer mode, since the DMA register are automatically reloaded at end 1132 * of period transfer. The hardware may have switched to the next 1133 * transfer (CT bit updated) just before the position (SxNDTR reg) is 1134 * read. 1135 * In this case the SxNDTR reg could (or not) correspond to the new 1136 * transfer position, and not the expected one. 1137 * The strategy implemented in the stm32 driver is to: 1138 * - read the SxNDTR register 1139 * - crosscheck that hardware is still in current transfer. 1140 * In case of switch, we can assume that the DMA is at the beginning of 1141 * the next transfer. So we approximate the residue in consequence, by 1142 * pointing on the beginning of next transfer. 1143 * 1144 * This race condition doesn't apply for none cyclic mode, as double 1145 * buffer is not used. In such situation registers are updated by the 1146 * software. 1147 */ 1148 1149 residue = stm32_dma_get_remaining_bytes(chan); 1150 1151 if (!stm32_dma_is_current_sg(chan)) { 1152 n_sg++; 1153 if (n_sg == chan->desc->num_sgs) 1154 n_sg = 0; 1155 residue = sg_req->len; 1156 } 1157 1158 /* 1159 * In cyclic mode, for the last period, residue = remaining bytes 1160 * from NDTR, 1161 * else for all other periods in cyclic mode, and in sg mode, 1162 * residue = remaining bytes from NDTR + remaining 1163 * periods/sg to be transferred 1164 */ 1165 if (!chan->desc->cyclic || n_sg != 0) 1166 for (i = n_sg; i < desc->num_sgs; i++) 1167 residue += desc->sg_req[i].len; 1168 1169 if (!chan->mem_burst) 1170 return residue; 1171 1172 burst_size = chan->mem_burst * chan->mem_width; 1173 modulo = residue % burst_size; 1174 if (modulo) 1175 residue = residue - modulo + burst_size; 1176 1177 return residue; 1178 } 1179 1180 static enum dma_status stm32_dma_tx_status(struct dma_chan *c, 1181 dma_cookie_t cookie, 1182 struct dma_tx_state *state) 1183 { 1184 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1185 struct virt_dma_desc *vdesc; 1186 enum dma_status status; 1187 unsigned long flags; 1188 u32 residue = 0; 1189 1190 status = dma_cookie_status(c, cookie, state); 1191 if (status == DMA_COMPLETE || !state) 1192 return status; 1193 1194 spin_lock_irqsave(&chan->vchan.lock, flags); 1195 vdesc = vchan_find_desc(&chan->vchan, cookie); 1196 if (chan->desc && cookie == chan->desc->vdesc.tx.cookie) 1197 residue = stm32_dma_desc_residue(chan, chan->desc, 1198 chan->next_sg); 1199 else if (vdesc) 1200 residue = stm32_dma_desc_residue(chan, 1201 to_stm32_dma_desc(vdesc), 0); 1202 dma_set_residue(state, residue); 1203 1204 spin_unlock_irqrestore(&chan->vchan.lock, flags); 1205 1206 return status; 1207 } 1208 1209 static int stm32_dma_alloc_chan_resources(struct dma_chan *c) 1210 { 1211 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1212 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 1213 int ret; 1214 1215 chan->config_init = false; 1216 1217 ret = pm_runtime_resume_and_get(dmadev->ddev.dev); 1218 if (ret < 0) 1219 return ret; 1220 1221 ret = stm32_dma_disable_chan(chan); 1222 if (ret < 0) 1223 pm_runtime_put(dmadev->ddev.dev); 1224 1225 return ret; 1226 } 1227 1228 static void stm32_dma_free_chan_resources(struct dma_chan *c) 1229 { 1230 struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1231 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 1232 unsigned long flags; 1233 1234 dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id); 1235 1236 if (chan->busy) { 1237 spin_lock_irqsave(&chan->vchan.lock, flags); 1238 stm32_dma_stop(chan); 1239 chan->desc = NULL; 1240 spin_unlock_irqrestore(&chan->vchan.lock, flags); 1241 } 1242 1243 pm_runtime_put(dmadev->ddev.dev); 1244 1245 vchan_free_chan_resources(to_virt_chan(c)); 1246 stm32_dma_clear_reg(&chan->chan_reg); 1247 chan->threshold = 0; 1248 } 1249 1250 static void stm32_dma_desc_free(struct virt_dma_desc *vdesc) 1251 { 1252 kfree(container_of(vdesc, struct stm32_dma_desc, vdesc)); 1253 } 1254 1255 static void stm32_dma_set_config(struct stm32_dma_chan *chan, 1256 struct stm32_dma_cfg *cfg) 1257 { 1258 stm32_dma_clear_reg(&chan->chan_reg); 1259 1260 chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK; 1261 chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line); 1262 1263 /* Enable Interrupts */ 1264 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE; 1265 1266 chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features); 1267 if (STM32_DMA_DIRECT_MODE_GET(cfg->features)) 1268 chan->threshold = STM32_DMA_FIFO_THRESHOLD_NONE; 1269 if (STM32_DMA_ALT_ACK_MODE_GET(cfg->features)) 1270 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TRBUFF; 1271 } 1272 1273 static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec, 1274 struct of_dma *ofdma) 1275 { 1276 struct stm32_dma_device *dmadev = ofdma->of_dma_data; 1277 struct device *dev = dmadev->ddev.dev; 1278 struct stm32_dma_cfg cfg; 1279 struct stm32_dma_chan *chan; 1280 struct dma_chan *c; 1281 1282 if (dma_spec->args_count < 4) { 1283 dev_err(dev, "Bad number of cells\n"); 1284 return NULL; 1285 } 1286 1287 cfg.channel_id = dma_spec->args[0]; 1288 cfg.request_line = dma_spec->args[1]; 1289 cfg.stream_config = dma_spec->args[2]; 1290 cfg.features = dma_spec->args[3]; 1291 1292 if (cfg.channel_id >= STM32_DMA_MAX_CHANNELS || 1293 cfg.request_line >= STM32_DMA_MAX_REQUEST_ID) { 1294 dev_err(dev, "Bad channel and/or request id\n"); 1295 return NULL; 1296 } 1297 1298 chan = &dmadev->chan[cfg.channel_id]; 1299 1300 c = dma_get_slave_channel(&chan->vchan.chan); 1301 if (!c) { 1302 dev_err(dev, "No more channels available\n"); 1303 return NULL; 1304 } 1305 1306 stm32_dma_set_config(chan, &cfg); 1307 1308 return c; 1309 } 1310 1311 static const struct of_device_id stm32_dma_of_match[] = { 1312 { .compatible = "st,stm32-dma", }, 1313 { /* sentinel */ }, 1314 }; 1315 MODULE_DEVICE_TABLE(of, stm32_dma_of_match); 1316 1317 static int stm32_dma_probe(struct platform_device *pdev) 1318 { 1319 struct stm32_dma_chan *chan; 1320 struct stm32_dma_device *dmadev; 1321 struct dma_device *dd; 1322 const struct of_device_id *match; 1323 struct resource *res; 1324 struct reset_control *rst; 1325 int i, ret; 1326 1327 match = of_match_device(stm32_dma_of_match, &pdev->dev); 1328 if (!match) { 1329 dev_err(&pdev->dev, "Error: No device match found\n"); 1330 return -ENODEV; 1331 } 1332 1333 dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL); 1334 if (!dmadev) 1335 return -ENOMEM; 1336 1337 dd = &dmadev->ddev; 1338 1339 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1340 dmadev->base = devm_ioremap_resource(&pdev->dev, res); 1341 if (IS_ERR(dmadev->base)) 1342 return PTR_ERR(dmadev->base); 1343 1344 dmadev->clk = devm_clk_get(&pdev->dev, NULL); 1345 if (IS_ERR(dmadev->clk)) 1346 return dev_err_probe(&pdev->dev, PTR_ERR(dmadev->clk), "Can't get clock\n"); 1347 1348 ret = clk_prepare_enable(dmadev->clk); 1349 if (ret < 0) { 1350 dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret); 1351 return ret; 1352 } 1353 1354 dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node, 1355 "st,mem2mem"); 1356 1357 rst = devm_reset_control_get(&pdev->dev, NULL); 1358 if (IS_ERR(rst)) { 1359 ret = PTR_ERR(rst); 1360 if (ret == -EPROBE_DEFER) 1361 goto clk_free; 1362 } else { 1363 reset_control_assert(rst); 1364 udelay(2); 1365 reset_control_deassert(rst); 1366 } 1367 1368 dma_set_max_seg_size(&pdev->dev, STM32_DMA_ALIGNED_MAX_DATA_ITEMS); 1369 1370 dma_cap_set(DMA_SLAVE, dd->cap_mask); 1371 dma_cap_set(DMA_PRIVATE, dd->cap_mask); 1372 dma_cap_set(DMA_CYCLIC, dd->cap_mask); 1373 dd->device_alloc_chan_resources = stm32_dma_alloc_chan_resources; 1374 dd->device_free_chan_resources = stm32_dma_free_chan_resources; 1375 dd->device_tx_status = stm32_dma_tx_status; 1376 dd->device_issue_pending = stm32_dma_issue_pending; 1377 dd->device_prep_slave_sg = stm32_dma_prep_slave_sg; 1378 dd->device_prep_dma_cyclic = stm32_dma_prep_dma_cyclic; 1379 dd->device_config = stm32_dma_slave_config; 1380 dd->device_terminate_all = stm32_dma_terminate_all; 1381 dd->device_synchronize = stm32_dma_synchronize; 1382 dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1383 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1384 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 1385 dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1386 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1387 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 1388 dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 1389 dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 1390 dd->copy_align = DMAENGINE_ALIGN_32_BYTES; 1391 dd->max_burst = STM32_DMA_MAX_BURST; 1392 dd->descriptor_reuse = true; 1393 dd->dev = &pdev->dev; 1394 INIT_LIST_HEAD(&dd->channels); 1395 1396 if (dmadev->mem2mem) { 1397 dma_cap_set(DMA_MEMCPY, dd->cap_mask); 1398 dd->device_prep_dma_memcpy = stm32_dma_prep_dma_memcpy; 1399 dd->directions |= BIT(DMA_MEM_TO_MEM); 1400 } 1401 1402 for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) { 1403 chan = &dmadev->chan[i]; 1404 chan->id = i; 1405 chan->vchan.desc_free = stm32_dma_desc_free; 1406 vchan_init(&chan->vchan, dd); 1407 } 1408 1409 ret = dma_async_device_register(dd); 1410 if (ret) 1411 goto clk_free; 1412 1413 for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) { 1414 chan = &dmadev->chan[i]; 1415 ret = platform_get_irq(pdev, i); 1416 if (ret < 0) 1417 goto err_unregister; 1418 chan->irq = ret; 1419 1420 ret = devm_request_irq(&pdev->dev, chan->irq, 1421 stm32_dma_chan_irq, 0, 1422 dev_name(chan2dev(chan)), chan); 1423 if (ret) { 1424 dev_err(&pdev->dev, 1425 "request_irq failed with err %d channel %d\n", 1426 ret, i); 1427 goto err_unregister; 1428 } 1429 } 1430 1431 ret = of_dma_controller_register(pdev->dev.of_node, 1432 stm32_dma_of_xlate, dmadev); 1433 if (ret < 0) { 1434 dev_err(&pdev->dev, 1435 "STM32 DMA DMA OF registration failed %d\n", ret); 1436 goto err_unregister; 1437 } 1438 1439 platform_set_drvdata(pdev, dmadev); 1440 1441 pm_runtime_set_active(&pdev->dev); 1442 pm_runtime_enable(&pdev->dev); 1443 pm_runtime_get_noresume(&pdev->dev); 1444 pm_runtime_put(&pdev->dev); 1445 1446 dev_info(&pdev->dev, "STM32 DMA driver registered\n"); 1447 1448 return 0; 1449 1450 err_unregister: 1451 dma_async_device_unregister(dd); 1452 clk_free: 1453 clk_disable_unprepare(dmadev->clk); 1454 1455 return ret; 1456 } 1457 1458 #ifdef CONFIG_PM 1459 static int stm32_dma_runtime_suspend(struct device *dev) 1460 { 1461 struct stm32_dma_device *dmadev = dev_get_drvdata(dev); 1462 1463 clk_disable_unprepare(dmadev->clk); 1464 1465 return 0; 1466 } 1467 1468 static int stm32_dma_runtime_resume(struct device *dev) 1469 { 1470 struct stm32_dma_device *dmadev = dev_get_drvdata(dev); 1471 int ret; 1472 1473 ret = clk_prepare_enable(dmadev->clk); 1474 if (ret) { 1475 dev_err(dev, "failed to prepare_enable clock\n"); 1476 return ret; 1477 } 1478 1479 return 0; 1480 } 1481 #endif 1482 1483 #ifdef CONFIG_PM_SLEEP 1484 static int stm32_dma_suspend(struct device *dev) 1485 { 1486 struct stm32_dma_device *dmadev = dev_get_drvdata(dev); 1487 int id, ret, scr; 1488 1489 ret = pm_runtime_resume_and_get(dev); 1490 if (ret < 0) 1491 return ret; 1492 1493 for (id = 0; id < STM32_DMA_MAX_CHANNELS; id++) { 1494 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); 1495 if (scr & STM32_DMA_SCR_EN) { 1496 dev_warn(dev, "Suspend is prevented by Chan %i\n", id); 1497 return -EBUSY; 1498 } 1499 } 1500 1501 pm_runtime_put_sync(dev); 1502 1503 pm_runtime_force_suspend(dev); 1504 1505 return 0; 1506 } 1507 1508 static int stm32_dma_resume(struct device *dev) 1509 { 1510 return pm_runtime_force_resume(dev); 1511 } 1512 #endif 1513 1514 static const struct dev_pm_ops stm32_dma_pm_ops = { 1515 SET_SYSTEM_SLEEP_PM_OPS(stm32_dma_suspend, stm32_dma_resume) 1516 SET_RUNTIME_PM_OPS(stm32_dma_runtime_suspend, 1517 stm32_dma_runtime_resume, NULL) 1518 }; 1519 1520 static struct platform_driver stm32_dma_driver = { 1521 .driver = { 1522 .name = "stm32-dma", 1523 .of_match_table = stm32_dma_of_match, 1524 .pm = &stm32_dma_pm_ops, 1525 }, 1526 .probe = stm32_dma_probe, 1527 }; 1528 1529 static int __init stm32_dma_init(void) 1530 { 1531 return platform_driver_register(&stm32_dma_driver); 1532 } 1533 subsys_initcall(stm32_dma_init); 1534