1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Driver for STM32 DMA controller
4 *
5 * Inspired by dma-jz4740.c and tegra20-apb-dma.c
6 *
7 * Copyright (C) M'boumba Cedric Madianga 2015
8 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
9 * Pierre-Yves Mordret <pierre-yves.mordret@st.com>
10 */
11
12 #include <linux/bitfield.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/err.h>
18 #include <linux/init.h>
19 #include <linux/iopoll.h>
20 #include <linux/jiffies.h>
21 #include <linux/list.h>
22 #include <linux/module.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/of_dma.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/reset.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31
32 #include "virt-dma.h"
33
34 #define STM32_DMA_LISR 0x0000 /* DMA Low Int Status Reg */
35 #define STM32_DMA_HISR 0x0004 /* DMA High Int Status Reg */
36 #define STM32_DMA_ISR(n) (((n) & 4) ? STM32_DMA_HISR : STM32_DMA_LISR)
37 #define STM32_DMA_LIFCR 0x0008 /* DMA Low Int Flag Clear Reg */
38 #define STM32_DMA_HIFCR 0x000c /* DMA High Int Flag Clear Reg */
39 #define STM32_DMA_IFCR(n) (((n) & 4) ? STM32_DMA_HIFCR : STM32_DMA_LIFCR)
40 #define STM32_DMA_TCI BIT(5) /* Transfer Complete Interrupt */
41 #define STM32_DMA_HTI BIT(4) /* Half Transfer Interrupt */
42 #define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */
43 #define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */
44 #define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */
45 #define STM32_DMA_MASKI (STM32_DMA_TCI \
46 | STM32_DMA_TEI \
47 | STM32_DMA_DMEI \
48 | STM32_DMA_FEI)
49 /*
50 * If (chan->id % 4) is 2 or 3, left shift the mask by 16 bits;
51 * if (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits.
52 */
53 #define STM32_DMA_FLAGS_SHIFT(n) ({ typeof(n) (_n) = (n); \
54 (((_n) & 2) << 3) | (((_n) & 1) * 6); })
55
56 /* DMA Stream x Configuration Register */
57 #define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */
58 #define STM32_DMA_SCR_REQ_MASK GENMASK(27, 25)
59 #define STM32_DMA_SCR_MBURST_MASK GENMASK(24, 23)
60 #define STM32_DMA_SCR_PBURST_MASK GENMASK(22, 21)
61 #define STM32_DMA_SCR_PL_MASK GENMASK(17, 16)
62 #define STM32_DMA_SCR_MSIZE_MASK GENMASK(14, 13)
63 #define STM32_DMA_SCR_PSIZE_MASK GENMASK(12, 11)
64 #define STM32_DMA_SCR_DIR_MASK GENMASK(7, 6)
65 #define STM32_DMA_SCR_TRBUFF BIT(20) /* Bufferable transfer for USART/UART */
66 #define STM32_DMA_SCR_CT BIT(19) /* Target in double buffer */
67 #define STM32_DMA_SCR_DBM BIT(18) /* Double Buffer Mode */
68 #define STM32_DMA_SCR_PINCOS BIT(15) /* Peripheral inc offset size */
69 #define STM32_DMA_SCR_MINC BIT(10) /* Memory increment mode */
70 #define STM32_DMA_SCR_PINC BIT(9) /* Peripheral increment mode */
71 #define STM32_DMA_SCR_CIRC BIT(8) /* Circular mode */
72 #define STM32_DMA_SCR_PFCTRL BIT(5) /* Peripheral Flow Controller */
73 #define STM32_DMA_SCR_TCIE BIT(4) /* Transfer Complete Int Enable
74 */
75 #define STM32_DMA_SCR_TEIE BIT(2) /* Transfer Error Int Enable */
76 #define STM32_DMA_SCR_DMEIE BIT(1) /* Direct Mode Err Int Enable */
77 #define STM32_DMA_SCR_EN BIT(0) /* Stream Enable */
78 #define STM32_DMA_SCR_CFG_MASK (STM32_DMA_SCR_PINC \
79 | STM32_DMA_SCR_MINC \
80 | STM32_DMA_SCR_PINCOS \
81 | STM32_DMA_SCR_PL_MASK)
82 #define STM32_DMA_SCR_IRQ_MASK (STM32_DMA_SCR_TCIE \
83 | STM32_DMA_SCR_TEIE \
84 | STM32_DMA_SCR_DMEIE)
85
86 /* DMA Stream x number of data register */
87 #define STM32_DMA_SNDTR(x) (0x0014 + 0x18 * (x))
88
89 /* DMA stream peripheral address register */
90 #define STM32_DMA_SPAR(x) (0x0018 + 0x18 * (x))
91
92 /* DMA stream x memory 0 address register */
93 #define STM32_DMA_SM0AR(x) (0x001c + 0x18 * (x))
94
95 /* DMA stream x memory 1 address register */
96 #define STM32_DMA_SM1AR(x) (0x0020 + 0x18 * (x))
97
98 /* DMA stream x FIFO control register */
99 #define STM32_DMA_SFCR(x) (0x0024 + 0x18 * (x))
100 #define STM32_DMA_SFCR_FTH_MASK GENMASK(1, 0)
101 #define STM32_DMA_SFCR_FEIE BIT(7) /* FIFO error interrupt enable */
102 #define STM32_DMA_SFCR_DMDIS BIT(2) /* Direct mode disable */
103 #define STM32_DMA_SFCR_MASK (STM32_DMA_SFCR_FEIE \
104 | STM32_DMA_SFCR_DMDIS)
105
106 /* DMA direction */
107 #define STM32_DMA_DEV_TO_MEM 0x00
108 #define STM32_DMA_MEM_TO_DEV 0x01
109 #define STM32_DMA_MEM_TO_MEM 0x02
110
111 /* DMA priority level */
112 #define STM32_DMA_PRIORITY_LOW 0x00
113 #define STM32_DMA_PRIORITY_MEDIUM 0x01
114 #define STM32_DMA_PRIORITY_HIGH 0x02
115 #define STM32_DMA_PRIORITY_VERY_HIGH 0x03
116
117 /* DMA FIFO threshold selection */
118 #define STM32_DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00
119 #define STM32_DMA_FIFO_THRESHOLD_HALFFULL 0x01
120 #define STM32_DMA_FIFO_THRESHOLD_3QUARTERSFULL 0x02
121 #define STM32_DMA_FIFO_THRESHOLD_FULL 0x03
122 #define STM32_DMA_FIFO_THRESHOLD_NONE 0x04
123
124 #define STM32_DMA_MAX_DATA_ITEMS 0xffff
125 /*
126 * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter
127 * gather at boundary. Thus it's safer to round down this value on FIFO
128 * size (16 Bytes)
129 */
130 #define STM32_DMA_ALIGNED_MAX_DATA_ITEMS \
131 ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16)
132 #define STM32_DMA_MAX_CHANNELS 0x08
133 #define STM32_DMA_MAX_REQUEST_ID 0x08
134 #define STM32_DMA_MAX_DATA_PARAM 0x03
135 #define STM32_DMA_FIFO_SIZE 16 /* FIFO is 16 bytes */
136 #define STM32_DMA_MIN_BURST 4
137 #define STM32_DMA_MAX_BURST 16
138
139 /* DMA Features */
140 #define STM32_DMA_THRESHOLD_FTR_MASK GENMASK(1, 0)
141 #define STM32_DMA_DIRECT_MODE_MASK BIT(2)
142 #define STM32_DMA_ALT_ACK_MODE_MASK BIT(4)
143 #define STM32_DMA_MDMA_STREAM_ID_MASK GENMASK(19, 16)
144
145 enum stm32_dma_width {
146 STM32_DMA_BYTE,
147 STM32_DMA_HALF_WORD,
148 STM32_DMA_WORD,
149 };
150
151 enum stm32_dma_burst_size {
152 STM32_DMA_BURST_SINGLE,
153 STM32_DMA_BURST_INCR4,
154 STM32_DMA_BURST_INCR8,
155 STM32_DMA_BURST_INCR16,
156 };
157
158 /**
159 * struct stm32_dma_cfg - STM32 DMA custom configuration
160 * @channel_id: channel ID
161 * @request_line: DMA request
162 * @stream_config: 32bit mask specifying the DMA channel configuration
163 * @features: 32bit mask specifying the DMA Feature list
164 */
165 struct stm32_dma_cfg {
166 u32 channel_id;
167 u32 request_line;
168 u32 stream_config;
169 u32 features;
170 };
171
172 struct stm32_dma_chan_reg {
173 u32 dma_lisr;
174 u32 dma_hisr;
175 u32 dma_lifcr;
176 u32 dma_hifcr;
177 u32 dma_scr;
178 u32 dma_sndtr;
179 u32 dma_spar;
180 u32 dma_sm0ar;
181 u32 dma_sm1ar;
182 u32 dma_sfcr;
183 };
184
185 struct stm32_dma_sg_req {
186 u32 len;
187 struct stm32_dma_chan_reg chan_reg;
188 };
189
190 struct stm32_dma_desc {
191 struct virt_dma_desc vdesc;
192 bool cyclic;
193 u32 num_sgs;
194 struct stm32_dma_sg_req sg_req[];
195 };
196
197 /**
198 * struct stm32_dma_mdma_config - STM32 DMA MDMA configuration
199 * @stream_id: DMA request to trigger STM32 MDMA transfer
200 * @ifcr: DMA interrupt flag clear register address,
201 * used by STM32 MDMA to clear DMA Transfer Complete flag
202 * @tcf: DMA Transfer Complete flag
203 */
204 struct stm32_dma_mdma_config {
205 u32 stream_id;
206 u32 ifcr;
207 u32 tcf;
208 };
209
210 struct stm32_dma_chan {
211 struct virt_dma_chan vchan;
212 bool config_init;
213 bool busy;
214 u32 id;
215 u32 irq;
216 struct stm32_dma_desc *desc;
217 u32 next_sg;
218 struct dma_slave_config dma_sconfig;
219 struct stm32_dma_chan_reg chan_reg;
220 u32 threshold;
221 u32 mem_burst;
222 u32 mem_width;
223 enum dma_status status;
224 bool trig_mdma;
225 struct stm32_dma_mdma_config mdma_config;
226 };
227
228 struct stm32_dma_device {
229 struct dma_device ddev;
230 void __iomem *base;
231 struct clk *clk;
232 bool mem2mem;
233 struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS];
234 };
235
stm32_dma_get_dev(struct stm32_dma_chan * chan)236 static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan)
237 {
238 return container_of(chan->vchan.chan.device, struct stm32_dma_device,
239 ddev);
240 }
241
to_stm32_dma_chan(struct dma_chan * c)242 static struct stm32_dma_chan *to_stm32_dma_chan(struct dma_chan *c)
243 {
244 return container_of(c, struct stm32_dma_chan, vchan.chan);
245 }
246
to_stm32_dma_desc(struct virt_dma_desc * vdesc)247 static struct stm32_dma_desc *to_stm32_dma_desc(struct virt_dma_desc *vdesc)
248 {
249 return container_of(vdesc, struct stm32_dma_desc, vdesc);
250 }
251
chan2dev(struct stm32_dma_chan * chan)252 static struct device *chan2dev(struct stm32_dma_chan *chan)
253 {
254 return &chan->vchan.chan.dev->device;
255 }
256
stm32_dma_read(struct stm32_dma_device * dmadev,u32 reg)257 static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg)
258 {
259 return readl_relaxed(dmadev->base + reg);
260 }
261
stm32_dma_write(struct stm32_dma_device * dmadev,u32 reg,u32 val)262 static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val)
263 {
264 writel_relaxed(val, dmadev->base + reg);
265 }
266
stm32_dma_get_width(struct stm32_dma_chan * chan,enum dma_slave_buswidth width)267 static int stm32_dma_get_width(struct stm32_dma_chan *chan,
268 enum dma_slave_buswidth width)
269 {
270 switch (width) {
271 case DMA_SLAVE_BUSWIDTH_1_BYTE:
272 return STM32_DMA_BYTE;
273 case DMA_SLAVE_BUSWIDTH_2_BYTES:
274 return STM32_DMA_HALF_WORD;
275 case DMA_SLAVE_BUSWIDTH_4_BYTES:
276 return STM32_DMA_WORD;
277 default:
278 dev_err(chan2dev(chan), "Dma bus width not supported\n");
279 return -EINVAL;
280 }
281 }
282
stm32_dma_get_max_width(u32 buf_len,dma_addr_t buf_addr,u32 threshold)283 static enum dma_slave_buswidth stm32_dma_get_max_width(u32 buf_len,
284 dma_addr_t buf_addr,
285 u32 threshold)
286 {
287 enum dma_slave_buswidth max_width;
288
289 if (threshold == STM32_DMA_FIFO_THRESHOLD_FULL)
290 max_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
291 else
292 max_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
293
294 while ((buf_len < max_width || buf_len % max_width) &&
295 max_width > DMA_SLAVE_BUSWIDTH_1_BYTE)
296 max_width = max_width >> 1;
297
298 if (buf_addr & (max_width - 1))
299 max_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
300
301 return max_width;
302 }
303
stm32_dma_fifo_threshold_is_allowed(u32 burst,u32 threshold,enum dma_slave_buswidth width)304 static bool stm32_dma_fifo_threshold_is_allowed(u32 burst, u32 threshold,
305 enum dma_slave_buswidth width)
306 {
307 u32 remaining;
308
309 if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE)
310 return false;
311
312 if (width != DMA_SLAVE_BUSWIDTH_UNDEFINED) {
313 if (burst != 0) {
314 /*
315 * If number of beats fit in several whole bursts
316 * this configuration is allowed.
317 */
318 remaining = ((STM32_DMA_FIFO_SIZE / width) *
319 (threshold + 1) / 4) % burst;
320
321 if (remaining == 0)
322 return true;
323 } else {
324 return true;
325 }
326 }
327
328 return false;
329 }
330
stm32_dma_is_burst_possible(u32 buf_len,u32 threshold)331 static bool stm32_dma_is_burst_possible(u32 buf_len, u32 threshold)
332 {
333 /* If FIFO direct mode, burst is not possible */
334 if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE)
335 return false;
336
337 /*
338 * Buffer or period length has to be aligned on FIFO depth.
339 * Otherwise bytes may be stuck within FIFO at buffer or period
340 * length.
341 */
342 return ((buf_len % ((threshold + 1) * 4)) == 0);
343 }
344
stm32_dma_get_best_burst(u32 buf_len,u32 max_burst,u32 threshold,enum dma_slave_buswidth width)345 static u32 stm32_dma_get_best_burst(u32 buf_len, u32 max_burst, u32 threshold,
346 enum dma_slave_buswidth width)
347 {
348 u32 best_burst = max_burst;
349
350 if (best_burst == 1 || !stm32_dma_is_burst_possible(buf_len, threshold))
351 return 0;
352
353 while ((buf_len < best_burst * width && best_burst > 1) ||
354 !stm32_dma_fifo_threshold_is_allowed(best_burst, threshold,
355 width)) {
356 if (best_burst > STM32_DMA_MIN_BURST)
357 best_burst = best_burst >> 1;
358 else
359 best_burst = 0;
360 }
361
362 return best_burst;
363 }
364
stm32_dma_get_burst(struct stm32_dma_chan * chan,u32 maxburst)365 static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst)
366 {
367 switch (maxburst) {
368 case 0:
369 case 1:
370 return STM32_DMA_BURST_SINGLE;
371 case 4:
372 return STM32_DMA_BURST_INCR4;
373 case 8:
374 return STM32_DMA_BURST_INCR8;
375 case 16:
376 return STM32_DMA_BURST_INCR16;
377 default:
378 dev_err(chan2dev(chan), "Dma burst size not supported\n");
379 return -EINVAL;
380 }
381 }
382
stm32_dma_set_fifo_config(struct stm32_dma_chan * chan,u32 src_burst,u32 dst_burst)383 static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan,
384 u32 src_burst, u32 dst_burst)
385 {
386 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK;
387 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE;
388
389 if (!src_burst && !dst_burst) {
390 /* Using direct mode */
391 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE;
392 } else {
393 /* Using FIFO mode */
394 chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
395 }
396 }
397
stm32_dma_slave_config(struct dma_chan * c,struct dma_slave_config * config)398 static int stm32_dma_slave_config(struct dma_chan *c,
399 struct dma_slave_config *config)
400 {
401 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
402
403 memcpy(&chan->dma_sconfig, config, sizeof(*config));
404
405 /* Check if user is requesting DMA to trigger STM32 MDMA */
406 if (config->peripheral_size) {
407 config->peripheral_config = &chan->mdma_config;
408 config->peripheral_size = sizeof(chan->mdma_config);
409 chan->trig_mdma = true;
410 }
411
412 chan->config_init = true;
413
414 return 0;
415 }
416
stm32_dma_irq_status(struct stm32_dma_chan * chan)417 static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan)
418 {
419 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
420 u32 flags, dma_isr;
421
422 /*
423 * Read "flags" from DMA_xISR register corresponding to the selected
424 * DMA channel at the correct bit offset inside that register.
425 */
426
427 dma_isr = stm32_dma_read(dmadev, STM32_DMA_ISR(chan->id));
428 flags = dma_isr >> STM32_DMA_FLAGS_SHIFT(chan->id);
429
430 return flags & STM32_DMA_MASKI;
431 }
432
stm32_dma_irq_clear(struct stm32_dma_chan * chan,u32 flags)433 static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags)
434 {
435 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
436 u32 dma_ifcr;
437
438 /*
439 * Write "flags" to the DMA_xIFCR register corresponding to the selected
440 * DMA channel at the correct bit offset inside that register.
441 */
442 flags &= STM32_DMA_MASKI;
443 dma_ifcr = flags << STM32_DMA_FLAGS_SHIFT(chan->id);
444
445 stm32_dma_write(dmadev, STM32_DMA_IFCR(chan->id), dma_ifcr);
446 }
447
stm32_dma_disable_chan(struct stm32_dma_chan * chan)448 static int stm32_dma_disable_chan(struct stm32_dma_chan *chan)
449 {
450 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
451 u32 dma_scr, id, reg;
452
453 id = chan->id;
454 reg = STM32_DMA_SCR(id);
455 dma_scr = stm32_dma_read(dmadev, reg);
456
457 if (dma_scr & STM32_DMA_SCR_EN) {
458 dma_scr &= ~STM32_DMA_SCR_EN;
459 stm32_dma_write(dmadev, reg, dma_scr);
460
461 return readl_relaxed_poll_timeout_atomic(dmadev->base + reg,
462 dma_scr, !(dma_scr & STM32_DMA_SCR_EN),
463 10, 1000000);
464 }
465
466 return 0;
467 }
468
stm32_dma_stop(struct stm32_dma_chan * chan)469 static void stm32_dma_stop(struct stm32_dma_chan *chan)
470 {
471 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
472 u32 dma_scr, dma_sfcr, status;
473 int ret;
474
475 /* Disable interrupts */
476 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
477 dma_scr &= ~STM32_DMA_SCR_IRQ_MASK;
478 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
479 dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
480 dma_sfcr &= ~STM32_DMA_SFCR_FEIE;
481 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr);
482
483 /* Disable DMA */
484 ret = stm32_dma_disable_chan(chan);
485 if (ret < 0)
486 return;
487
488 /* Clear interrupt status if it is there */
489 status = stm32_dma_irq_status(chan);
490 if (status) {
491 dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n",
492 __func__, status);
493 stm32_dma_irq_clear(chan, status);
494 }
495
496 chan->busy = false;
497 chan->status = DMA_COMPLETE;
498 }
499
stm32_dma_terminate_all(struct dma_chan * c)500 static int stm32_dma_terminate_all(struct dma_chan *c)
501 {
502 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
503 unsigned long flags;
504 LIST_HEAD(head);
505
506 spin_lock_irqsave(&chan->vchan.lock, flags);
507
508 if (chan->desc) {
509 dma_cookie_complete(&chan->desc->vdesc.tx);
510 vchan_terminate_vdesc(&chan->desc->vdesc);
511 if (chan->busy)
512 stm32_dma_stop(chan);
513 chan->desc = NULL;
514 }
515
516 vchan_get_all_descriptors(&chan->vchan, &head);
517 spin_unlock_irqrestore(&chan->vchan.lock, flags);
518 vchan_dma_desc_free_list(&chan->vchan, &head);
519
520 return 0;
521 }
522
stm32_dma_synchronize(struct dma_chan * c)523 static void stm32_dma_synchronize(struct dma_chan *c)
524 {
525 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
526
527 vchan_synchronize(&chan->vchan);
528 }
529
stm32_dma_dump_reg(struct stm32_dma_chan * chan)530 static void stm32_dma_dump_reg(struct stm32_dma_chan *chan)
531 {
532 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
533 u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
534 u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
535 u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id));
536 u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id));
537 u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id));
538 u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
539
540 dev_dbg(chan2dev(chan), "SCR: 0x%08x\n", scr);
541 dev_dbg(chan2dev(chan), "NDTR: 0x%08x\n", ndtr);
542 dev_dbg(chan2dev(chan), "SPAR: 0x%08x\n", spar);
543 dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar);
544 dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar);
545 dev_dbg(chan2dev(chan), "SFCR: 0x%08x\n", sfcr);
546 }
547
stm32_dma_sg_inc(struct stm32_dma_chan * chan)548 static void stm32_dma_sg_inc(struct stm32_dma_chan *chan)
549 {
550 chan->next_sg++;
551 if (chan->desc->cyclic && (chan->next_sg == chan->desc->num_sgs))
552 chan->next_sg = 0;
553 }
554
555 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan);
556
stm32_dma_start_transfer(struct stm32_dma_chan * chan)557 static void stm32_dma_start_transfer(struct stm32_dma_chan *chan)
558 {
559 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
560 struct virt_dma_desc *vdesc;
561 struct stm32_dma_sg_req *sg_req;
562 struct stm32_dma_chan_reg *reg;
563 u32 status;
564 int ret;
565
566 ret = stm32_dma_disable_chan(chan);
567 if (ret < 0)
568 return;
569
570 if (!chan->desc) {
571 vdesc = vchan_next_desc(&chan->vchan);
572 if (!vdesc)
573 return;
574
575 list_del(&vdesc->node);
576
577 chan->desc = to_stm32_dma_desc(vdesc);
578 chan->next_sg = 0;
579 }
580
581 if (chan->next_sg == chan->desc->num_sgs)
582 chan->next_sg = 0;
583
584 sg_req = &chan->desc->sg_req[chan->next_sg];
585 reg = &sg_req->chan_reg;
586
587 /* When DMA triggers STM32 MDMA, DMA Transfer Complete is managed by STM32 MDMA */
588 if (chan->trig_mdma && chan->dma_sconfig.direction != DMA_MEM_TO_DEV)
589 reg->dma_scr &= ~STM32_DMA_SCR_TCIE;
590
591 reg->dma_scr &= ~STM32_DMA_SCR_EN;
592 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
593 stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar);
594 stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar);
595 stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr);
596 stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar);
597 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr);
598
599 stm32_dma_sg_inc(chan);
600
601 /* Clear interrupt status if it is there */
602 status = stm32_dma_irq_status(chan);
603 if (status)
604 stm32_dma_irq_clear(chan, status);
605
606 if (chan->desc->cyclic)
607 stm32_dma_configure_next_sg(chan);
608
609 stm32_dma_dump_reg(chan);
610
611 /* Start DMA */
612 chan->busy = true;
613 chan->status = DMA_IN_PROGRESS;
614 reg->dma_scr |= STM32_DMA_SCR_EN;
615 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr);
616
617 dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan);
618 }
619
stm32_dma_configure_next_sg(struct stm32_dma_chan * chan)620 static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan)
621 {
622 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
623 struct stm32_dma_sg_req *sg_req;
624 u32 dma_scr, dma_sm0ar, dma_sm1ar, id;
625
626 id = chan->id;
627 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
628
629 sg_req = &chan->desc->sg_req[chan->next_sg];
630
631 if (dma_scr & STM32_DMA_SCR_CT) {
632 dma_sm0ar = sg_req->chan_reg.dma_sm0ar;
633 stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar);
634 dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n",
635 stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)));
636 } else {
637 dma_sm1ar = sg_req->chan_reg.dma_sm1ar;
638 stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar);
639 dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n",
640 stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)));
641 }
642 }
643
stm32_dma_handle_chan_paused(struct stm32_dma_chan * chan)644 static void stm32_dma_handle_chan_paused(struct stm32_dma_chan *chan)
645 {
646 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
647 u32 dma_scr;
648
649 /*
650 * Read and store current remaining data items and peripheral/memory addresses to be
651 * updated on resume
652 */
653 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
654 /*
655 * Transfer can be paused while between a previous resume and reconfiguration on transfer
656 * complete. If transfer is cyclic and CIRC and DBM have been deactivated for resume, need
657 * to set it here in SCR backup to ensure a good reconfiguration on transfer complete.
658 */
659 if (chan->desc && chan->desc->cyclic) {
660 if (chan->desc->num_sgs == 1)
661 dma_scr |= STM32_DMA_SCR_CIRC;
662 else
663 dma_scr |= STM32_DMA_SCR_DBM;
664 }
665 chan->chan_reg.dma_scr = dma_scr;
666
667 /*
668 * Need to temporarily deactivate CIRC/DBM until next Transfer Complete interrupt, otherwise
669 * on resume NDTR autoreload value will be wrong (lower than the initial period length)
670 */
671 if (chan->desc && chan->desc->cyclic) {
672 dma_scr &= ~(STM32_DMA_SCR_DBM | STM32_DMA_SCR_CIRC);
673 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
674 }
675
676 chan->chan_reg.dma_sndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
677
678 chan->status = DMA_PAUSED;
679
680 dev_dbg(chan2dev(chan), "vchan %pK: paused\n", &chan->vchan);
681 }
682
stm32_dma_post_resume_reconfigure(struct stm32_dma_chan * chan)683 static void stm32_dma_post_resume_reconfigure(struct stm32_dma_chan *chan)
684 {
685 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
686 struct stm32_dma_sg_req *sg_req;
687 u32 dma_scr, status, id;
688
689 id = chan->id;
690 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
691
692 /* Clear interrupt status if it is there */
693 status = stm32_dma_irq_status(chan);
694 if (status)
695 stm32_dma_irq_clear(chan, status);
696
697 if (!chan->next_sg)
698 sg_req = &chan->desc->sg_req[chan->desc->num_sgs - 1];
699 else
700 sg_req = &chan->desc->sg_req[chan->next_sg - 1];
701
702 /* Reconfigure NDTR with the initial value */
703 stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), sg_req->chan_reg.dma_sndtr);
704
705 /* Restore SPAR */
706 stm32_dma_write(dmadev, STM32_DMA_SPAR(id), sg_req->chan_reg.dma_spar);
707
708 /* Restore SM0AR/SM1AR whatever DBM/CT as they may have been modified */
709 stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), sg_req->chan_reg.dma_sm0ar);
710 stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), sg_req->chan_reg.dma_sm1ar);
711
712 /* Reactivate CIRC/DBM if needed */
713 if (chan->chan_reg.dma_scr & STM32_DMA_SCR_DBM) {
714 dma_scr |= STM32_DMA_SCR_DBM;
715 /* Restore CT */
716 if (chan->chan_reg.dma_scr & STM32_DMA_SCR_CT)
717 dma_scr &= ~STM32_DMA_SCR_CT;
718 else
719 dma_scr |= STM32_DMA_SCR_CT;
720 } else if (chan->chan_reg.dma_scr & STM32_DMA_SCR_CIRC) {
721 dma_scr |= STM32_DMA_SCR_CIRC;
722 }
723 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
724
725 stm32_dma_configure_next_sg(chan);
726
727 stm32_dma_dump_reg(chan);
728
729 dma_scr |= STM32_DMA_SCR_EN;
730 stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr);
731
732 dev_dbg(chan2dev(chan), "vchan %pK: reconfigured after pause/resume\n", &chan->vchan);
733 }
734
stm32_dma_handle_chan_done(struct stm32_dma_chan * chan,u32 scr)735 static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan, u32 scr)
736 {
737 if (!chan->desc)
738 return;
739
740 if (chan->desc->cyclic) {
741 vchan_cyclic_callback(&chan->desc->vdesc);
742 if (chan->trig_mdma)
743 return;
744 stm32_dma_sg_inc(chan);
745 /* cyclic while CIRC/DBM disable => post resume reconfiguration needed */
746 if (!(scr & (STM32_DMA_SCR_CIRC | STM32_DMA_SCR_DBM)))
747 stm32_dma_post_resume_reconfigure(chan);
748 else if (scr & STM32_DMA_SCR_DBM)
749 stm32_dma_configure_next_sg(chan);
750 } else {
751 chan->busy = false;
752 chan->status = DMA_COMPLETE;
753 if (chan->next_sg == chan->desc->num_sgs) {
754 vchan_cookie_complete(&chan->desc->vdesc);
755 chan->desc = NULL;
756 }
757 stm32_dma_start_transfer(chan);
758 }
759 }
760
stm32_dma_chan_irq(int irq,void * devid)761 static irqreturn_t stm32_dma_chan_irq(int irq, void *devid)
762 {
763 struct stm32_dma_chan *chan = devid;
764 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
765 u32 status, scr, sfcr;
766
767 spin_lock(&chan->vchan.lock);
768
769 status = stm32_dma_irq_status(chan);
770 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
771 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id));
772
773 if (status & STM32_DMA_FEI) {
774 stm32_dma_irq_clear(chan, STM32_DMA_FEI);
775 status &= ~STM32_DMA_FEI;
776 if (sfcr & STM32_DMA_SFCR_FEIE) {
777 if (!(scr & STM32_DMA_SCR_EN) &&
778 !(status & STM32_DMA_TCI))
779 dev_err(chan2dev(chan), "FIFO Error\n");
780 else
781 dev_dbg(chan2dev(chan), "FIFO over/underrun\n");
782 }
783 }
784 if (status & STM32_DMA_DMEI) {
785 stm32_dma_irq_clear(chan, STM32_DMA_DMEI);
786 status &= ~STM32_DMA_DMEI;
787 if (sfcr & STM32_DMA_SCR_DMEIE)
788 dev_dbg(chan2dev(chan), "Direct mode overrun\n");
789 }
790
791 if (status & STM32_DMA_TCI) {
792 stm32_dma_irq_clear(chan, STM32_DMA_TCI);
793 if (scr & STM32_DMA_SCR_TCIE) {
794 if (chan->status != DMA_PAUSED)
795 stm32_dma_handle_chan_done(chan, scr);
796 }
797 status &= ~STM32_DMA_TCI;
798 }
799
800 if (status & STM32_DMA_HTI) {
801 stm32_dma_irq_clear(chan, STM32_DMA_HTI);
802 status &= ~STM32_DMA_HTI;
803 }
804
805 if (status) {
806 stm32_dma_irq_clear(chan, status);
807 dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);
808 if (!(scr & STM32_DMA_SCR_EN))
809 dev_err(chan2dev(chan), "chan disabled by HW\n");
810 }
811
812 spin_unlock(&chan->vchan.lock);
813
814 return IRQ_HANDLED;
815 }
816
stm32_dma_issue_pending(struct dma_chan * c)817 static void stm32_dma_issue_pending(struct dma_chan *c)
818 {
819 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
820 unsigned long flags;
821
822 spin_lock_irqsave(&chan->vchan.lock, flags);
823 if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) {
824 dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan);
825 stm32_dma_start_transfer(chan);
826
827 }
828 spin_unlock_irqrestore(&chan->vchan.lock, flags);
829 }
830
stm32_dma_pause(struct dma_chan * c)831 static int stm32_dma_pause(struct dma_chan *c)
832 {
833 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
834 unsigned long flags;
835 int ret;
836
837 if (chan->status != DMA_IN_PROGRESS)
838 return -EPERM;
839
840 spin_lock_irqsave(&chan->vchan.lock, flags);
841
842 ret = stm32_dma_disable_chan(chan);
843 if (!ret)
844 stm32_dma_handle_chan_paused(chan);
845
846 spin_unlock_irqrestore(&chan->vchan.lock, flags);
847
848 return ret;
849 }
850
stm32_dma_resume(struct dma_chan * c)851 static int stm32_dma_resume(struct dma_chan *c)
852 {
853 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
854 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
855 struct stm32_dma_chan_reg chan_reg = chan->chan_reg;
856 u32 id = chan->id, scr, ndtr, offset, spar, sm0ar, sm1ar;
857 struct stm32_dma_sg_req *sg_req;
858 unsigned long flags;
859
860 if (chan->status != DMA_PAUSED)
861 return -EPERM;
862
863 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
864 if (WARN_ON(scr & STM32_DMA_SCR_EN))
865 return -EPERM;
866
867 spin_lock_irqsave(&chan->vchan.lock, flags);
868
869 /* sg_reg[prev_sg] contains original ndtr, sm0ar and sm1ar before pausing the transfer */
870 if (!chan->next_sg)
871 sg_req = &chan->desc->sg_req[chan->desc->num_sgs - 1];
872 else
873 sg_req = &chan->desc->sg_req[chan->next_sg - 1];
874
875 ndtr = sg_req->chan_reg.dma_sndtr;
876 offset = (ndtr - chan_reg.dma_sndtr);
877 offset <<= FIELD_GET(STM32_DMA_SCR_PSIZE_MASK, chan_reg.dma_scr);
878 spar = sg_req->chan_reg.dma_spar;
879 sm0ar = sg_req->chan_reg.dma_sm0ar;
880 sm1ar = sg_req->chan_reg.dma_sm1ar;
881
882 /*
883 * The peripheral and/or memory addresses have to be updated in order to adjust the
884 * address pointers. Need to check increment.
885 */
886 if (chan_reg.dma_scr & STM32_DMA_SCR_PINC)
887 stm32_dma_write(dmadev, STM32_DMA_SPAR(id), spar + offset);
888 else
889 stm32_dma_write(dmadev, STM32_DMA_SPAR(id), spar);
890
891 if (!(chan_reg.dma_scr & STM32_DMA_SCR_MINC))
892 offset = 0;
893
894 /*
895 * In case of DBM, the current target could be SM1AR.
896 * Need to temporarily deactivate CIRC/DBM to finish the current transfer, so
897 * SM0AR becomes the current target and must be updated with SM1AR + offset if CT=1.
898 */
899 if ((chan_reg.dma_scr & STM32_DMA_SCR_DBM) && (chan_reg.dma_scr & STM32_DMA_SCR_CT))
900 stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), sm1ar + offset);
901 else
902 stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), sm0ar + offset);
903
904 /* NDTR must be restored otherwise internal HW counter won't be correctly reset */
905 stm32_dma_write(dmadev, STM32_DMA_SNDTR(id), chan_reg.dma_sndtr);
906
907 /*
908 * Need to temporarily deactivate CIRC/DBM until next Transfer Complete interrupt,
909 * otherwise NDTR autoreload value will be wrong (lower than the initial period length)
910 */
911 if (chan_reg.dma_scr & (STM32_DMA_SCR_CIRC | STM32_DMA_SCR_DBM))
912 chan_reg.dma_scr &= ~(STM32_DMA_SCR_CIRC | STM32_DMA_SCR_DBM);
913
914 if (chan_reg.dma_scr & STM32_DMA_SCR_DBM)
915 stm32_dma_configure_next_sg(chan);
916
917 stm32_dma_dump_reg(chan);
918
919 /* The stream may then be re-enabled to restart transfer from the point it was stopped */
920 chan->status = DMA_IN_PROGRESS;
921 chan_reg.dma_scr |= STM32_DMA_SCR_EN;
922 stm32_dma_write(dmadev, STM32_DMA_SCR(id), chan_reg.dma_scr);
923
924 spin_unlock_irqrestore(&chan->vchan.lock, flags);
925
926 dev_dbg(chan2dev(chan), "vchan %pK: resumed\n", &chan->vchan);
927
928 return 0;
929 }
930
stm32_dma_set_xfer_param(struct stm32_dma_chan * chan,enum dma_transfer_direction direction,enum dma_slave_buswidth * buswidth,u32 buf_len,dma_addr_t buf_addr)931 static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan,
932 enum dma_transfer_direction direction,
933 enum dma_slave_buswidth *buswidth,
934 u32 buf_len, dma_addr_t buf_addr)
935 {
936 enum dma_slave_buswidth src_addr_width, dst_addr_width;
937 int src_bus_width, dst_bus_width;
938 int src_burst_size, dst_burst_size;
939 u32 src_maxburst, dst_maxburst, src_best_burst, dst_best_burst;
940 u32 dma_scr, fifoth;
941
942 src_addr_width = chan->dma_sconfig.src_addr_width;
943 dst_addr_width = chan->dma_sconfig.dst_addr_width;
944 src_maxburst = chan->dma_sconfig.src_maxburst;
945 dst_maxburst = chan->dma_sconfig.dst_maxburst;
946 fifoth = chan->threshold;
947
948 switch (direction) {
949 case DMA_MEM_TO_DEV:
950 /* Set device data size */
951 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
952 if (dst_bus_width < 0)
953 return dst_bus_width;
954
955 /* Set device burst size */
956 dst_best_burst = stm32_dma_get_best_burst(buf_len,
957 dst_maxburst,
958 fifoth,
959 dst_addr_width);
960
961 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
962 if (dst_burst_size < 0)
963 return dst_burst_size;
964
965 /* Set memory data size */
966 src_addr_width = stm32_dma_get_max_width(buf_len, buf_addr,
967 fifoth);
968 chan->mem_width = src_addr_width;
969 src_bus_width = stm32_dma_get_width(chan, src_addr_width);
970 if (src_bus_width < 0)
971 return src_bus_width;
972
973 /*
974 * Set memory burst size - burst not possible if address is not aligned on
975 * the address boundary equal to the size of the transfer
976 */
977 if (buf_addr & (buf_len - 1))
978 src_maxburst = 1;
979 else
980 src_maxburst = STM32_DMA_MAX_BURST;
981 src_best_burst = stm32_dma_get_best_burst(buf_len,
982 src_maxburst,
983 fifoth,
984 src_addr_width);
985 src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
986 if (src_burst_size < 0)
987 return src_burst_size;
988
989 dma_scr = FIELD_PREP(STM32_DMA_SCR_DIR_MASK, STM32_DMA_MEM_TO_DEV) |
990 FIELD_PREP(STM32_DMA_SCR_PSIZE_MASK, dst_bus_width) |
991 FIELD_PREP(STM32_DMA_SCR_MSIZE_MASK, src_bus_width) |
992 FIELD_PREP(STM32_DMA_SCR_PBURST_MASK, dst_burst_size) |
993 FIELD_PREP(STM32_DMA_SCR_MBURST_MASK, src_burst_size);
994
995 /* Set FIFO threshold */
996 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
997 if (fifoth != STM32_DMA_FIFO_THRESHOLD_NONE)
998 chan->chan_reg.dma_sfcr |= FIELD_PREP(STM32_DMA_SFCR_FTH_MASK, fifoth);
999
1000 /* Set peripheral address */
1001 chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr;
1002 *buswidth = dst_addr_width;
1003 break;
1004
1005 case DMA_DEV_TO_MEM:
1006 /* Set device data size */
1007 src_bus_width = stm32_dma_get_width(chan, src_addr_width);
1008 if (src_bus_width < 0)
1009 return src_bus_width;
1010
1011 /* Set device burst size */
1012 src_best_burst = stm32_dma_get_best_burst(buf_len,
1013 src_maxburst,
1014 fifoth,
1015 src_addr_width);
1016 chan->mem_burst = src_best_burst;
1017 src_burst_size = stm32_dma_get_burst(chan, src_best_burst);
1018 if (src_burst_size < 0)
1019 return src_burst_size;
1020
1021 /* Set memory data size */
1022 dst_addr_width = stm32_dma_get_max_width(buf_len, buf_addr,
1023 fifoth);
1024 chan->mem_width = dst_addr_width;
1025 dst_bus_width = stm32_dma_get_width(chan, dst_addr_width);
1026 if (dst_bus_width < 0)
1027 return dst_bus_width;
1028
1029 /*
1030 * Set memory burst size - burst not possible if address is not aligned on
1031 * the address boundary equal to the size of the transfer
1032 */
1033 if (buf_addr & (buf_len - 1))
1034 dst_maxburst = 1;
1035 else
1036 dst_maxburst = STM32_DMA_MAX_BURST;
1037 dst_best_burst = stm32_dma_get_best_burst(buf_len,
1038 dst_maxburst,
1039 fifoth,
1040 dst_addr_width);
1041 chan->mem_burst = dst_best_burst;
1042 dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst);
1043 if (dst_burst_size < 0)
1044 return dst_burst_size;
1045
1046 dma_scr = FIELD_PREP(STM32_DMA_SCR_DIR_MASK, STM32_DMA_DEV_TO_MEM) |
1047 FIELD_PREP(STM32_DMA_SCR_PSIZE_MASK, src_bus_width) |
1048 FIELD_PREP(STM32_DMA_SCR_MSIZE_MASK, dst_bus_width) |
1049 FIELD_PREP(STM32_DMA_SCR_PBURST_MASK, src_burst_size) |
1050 FIELD_PREP(STM32_DMA_SCR_MBURST_MASK, dst_burst_size);
1051
1052 /* Set FIFO threshold */
1053 chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK;
1054 if (fifoth != STM32_DMA_FIFO_THRESHOLD_NONE)
1055 chan->chan_reg.dma_sfcr |= FIELD_PREP(STM32_DMA_SFCR_FTH_MASK, fifoth);
1056
1057 /* Set peripheral address */
1058 chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr;
1059 *buswidth = chan->dma_sconfig.src_addr_width;
1060 break;
1061
1062 default:
1063 dev_err(chan2dev(chan), "Dma direction is not supported\n");
1064 return -EINVAL;
1065 }
1066
1067 stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst);
1068
1069 /* Set DMA control register */
1070 chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK |
1071 STM32_DMA_SCR_PSIZE_MASK | STM32_DMA_SCR_MSIZE_MASK |
1072 STM32_DMA_SCR_PBURST_MASK | STM32_DMA_SCR_MBURST_MASK);
1073 chan->chan_reg.dma_scr |= dma_scr;
1074
1075 return 0;
1076 }
1077
stm32_dma_clear_reg(struct stm32_dma_chan_reg * regs)1078 static void stm32_dma_clear_reg(struct stm32_dma_chan_reg *regs)
1079 {
1080 memset(regs, 0, sizeof(struct stm32_dma_chan_reg));
1081 }
1082
stm32_dma_prep_slave_sg(struct dma_chan * c,struct scatterlist * sgl,u32 sg_len,enum dma_transfer_direction direction,unsigned long flags,void * context)1083 static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg(
1084 struct dma_chan *c, struct scatterlist *sgl,
1085 u32 sg_len, enum dma_transfer_direction direction,
1086 unsigned long flags, void *context)
1087 {
1088 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1089 struct stm32_dma_desc *desc;
1090 struct scatterlist *sg;
1091 enum dma_slave_buswidth buswidth;
1092 u32 nb_data_items;
1093 int i, ret;
1094
1095 if (!chan->config_init) {
1096 dev_err(chan2dev(chan), "dma channel is not configured\n");
1097 return NULL;
1098 }
1099
1100 if (sg_len < 1) {
1101 dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len);
1102 return NULL;
1103 }
1104
1105 desc = kzalloc(struct_size(desc, sg_req, sg_len), GFP_NOWAIT);
1106 if (!desc)
1107 return NULL;
1108
1109 /* Set peripheral flow controller */
1110 if (chan->dma_sconfig.device_fc)
1111 chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL;
1112 else
1113 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
1114
1115 /* Activate Double Buffer Mode if DMA triggers STM32 MDMA and more than 1 sg */
1116 if (chan->trig_mdma && sg_len > 1) {
1117 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;
1118 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_CT;
1119 }
1120
1121 for_each_sg(sgl, sg, sg_len, i) {
1122 ret = stm32_dma_set_xfer_param(chan, direction, &buswidth,
1123 sg_dma_len(sg),
1124 sg_dma_address(sg));
1125 if (ret < 0)
1126 goto err;
1127
1128 desc->sg_req[i].len = sg_dma_len(sg);
1129
1130 nb_data_items = desc->sg_req[i].len / buswidth;
1131 if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) {
1132 dev_err(chan2dev(chan), "nb items not supported\n");
1133 goto err;
1134 }
1135
1136 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
1137 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
1138 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
1139 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
1140 desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg);
1141 desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg);
1142 if (chan->trig_mdma)
1143 desc->sg_req[i].chan_reg.dma_sm1ar += sg_dma_len(sg);
1144 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
1145 }
1146
1147 desc->num_sgs = sg_len;
1148 desc->cyclic = false;
1149
1150 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
1151
1152 err:
1153 kfree(desc);
1154 return NULL;
1155 }
1156
stm32_dma_prep_dma_cyclic(struct dma_chan * c,dma_addr_t buf_addr,size_t buf_len,size_t period_len,enum dma_transfer_direction direction,unsigned long flags)1157 static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic(
1158 struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
1159 size_t period_len, enum dma_transfer_direction direction,
1160 unsigned long flags)
1161 {
1162 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1163 struct stm32_dma_desc *desc;
1164 enum dma_slave_buswidth buswidth;
1165 u32 num_periods, nb_data_items;
1166 int i, ret;
1167
1168 if (!buf_len || !period_len) {
1169 dev_err(chan2dev(chan), "Invalid buffer/period len\n");
1170 return NULL;
1171 }
1172
1173 if (!chan->config_init) {
1174 dev_err(chan2dev(chan), "dma channel is not configured\n");
1175 return NULL;
1176 }
1177
1178 if (buf_len % period_len) {
1179 dev_err(chan2dev(chan), "buf_len not multiple of period_len\n");
1180 return NULL;
1181 }
1182
1183 /*
1184 * We allow to take more number of requests till DMA is
1185 * not started. The driver will loop over all requests.
1186 * Once DMA is started then new requests can be queued only after
1187 * terminating the DMA.
1188 */
1189 if (chan->busy) {
1190 dev_err(chan2dev(chan), "Request not allowed when dma busy\n");
1191 return NULL;
1192 }
1193
1194 ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len,
1195 buf_addr);
1196 if (ret < 0)
1197 return NULL;
1198
1199 nb_data_items = period_len / buswidth;
1200 if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) {
1201 dev_err(chan2dev(chan), "number of items not supported\n");
1202 return NULL;
1203 }
1204
1205 /* Enable Circular mode or double buffer mode */
1206 if (buf_len == period_len) {
1207 chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC;
1208 } else {
1209 chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM;
1210 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_CT;
1211 }
1212
1213 /* Clear periph ctrl if client set it */
1214 chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL;
1215
1216 num_periods = buf_len / period_len;
1217
1218 desc = kzalloc(struct_size(desc, sg_req, num_periods), GFP_NOWAIT);
1219 if (!desc)
1220 return NULL;
1221
1222 for (i = 0; i < num_periods; i++) {
1223 desc->sg_req[i].len = period_len;
1224
1225 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
1226 desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr;
1227 desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr;
1228 desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar;
1229 desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr;
1230 desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr;
1231 if (chan->trig_mdma)
1232 desc->sg_req[i].chan_reg.dma_sm1ar += period_len;
1233 desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items;
1234 if (!chan->trig_mdma)
1235 buf_addr += period_len;
1236 }
1237
1238 desc->num_sgs = num_periods;
1239 desc->cyclic = true;
1240
1241 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
1242 }
1243
stm32_dma_prep_dma_memcpy(struct dma_chan * c,dma_addr_t dest,dma_addr_t src,size_t len,unsigned long flags)1244 static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy(
1245 struct dma_chan *c, dma_addr_t dest,
1246 dma_addr_t src, size_t len, unsigned long flags)
1247 {
1248 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1249 enum dma_slave_buswidth max_width;
1250 struct stm32_dma_desc *desc;
1251 size_t xfer_count, offset;
1252 u32 num_sgs, best_burst, threshold;
1253 int dma_burst, i;
1254
1255 num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
1256 desc = kzalloc(struct_size(desc, sg_req, num_sgs), GFP_NOWAIT);
1257 if (!desc)
1258 return NULL;
1259
1260 threshold = chan->threshold;
1261
1262 for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) {
1263 xfer_count = min_t(size_t, len - offset,
1264 STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
1265
1266 /* Compute best burst size */
1267 max_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1268 best_burst = stm32_dma_get_best_burst(len, STM32_DMA_MAX_BURST,
1269 threshold, max_width);
1270 dma_burst = stm32_dma_get_burst(chan, best_burst);
1271 if (dma_burst < 0) {
1272 kfree(desc);
1273 return NULL;
1274 }
1275
1276 stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
1277 desc->sg_req[i].chan_reg.dma_scr =
1278 FIELD_PREP(STM32_DMA_SCR_DIR_MASK, STM32_DMA_MEM_TO_MEM) |
1279 FIELD_PREP(STM32_DMA_SCR_PBURST_MASK, dma_burst) |
1280 FIELD_PREP(STM32_DMA_SCR_MBURST_MASK, dma_burst) |
1281 STM32_DMA_SCR_MINC |
1282 STM32_DMA_SCR_PINC |
1283 STM32_DMA_SCR_TCIE |
1284 STM32_DMA_SCR_TEIE;
1285 desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK;
1286 desc->sg_req[i].chan_reg.dma_sfcr |= FIELD_PREP(STM32_DMA_SFCR_FTH_MASK, threshold);
1287 desc->sg_req[i].chan_reg.dma_spar = src + offset;
1288 desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset;
1289 desc->sg_req[i].chan_reg.dma_sndtr = xfer_count;
1290 desc->sg_req[i].len = xfer_count;
1291 }
1292
1293 desc->num_sgs = num_sgs;
1294 desc->cyclic = false;
1295
1296 return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
1297 }
1298
stm32_dma_get_remaining_bytes(struct stm32_dma_chan * chan)1299 static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan)
1300 {
1301 u32 dma_scr, width, ndtr;
1302 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1303
1304 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
1305 width = FIELD_GET(STM32_DMA_SCR_PSIZE_MASK, dma_scr);
1306 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id));
1307
1308 return ndtr << width;
1309 }
1310
1311 /**
1312 * stm32_dma_is_current_sg - check that expected sg_req is currently transferred
1313 * @chan: dma channel
1314 *
1315 * This function called when IRQ are disable, checks that the hardware has not
1316 * switched on the next transfer in double buffer mode. The test is done by
1317 * comparing the next_sg memory address with the hardware related register
1318 * (based on CT bit value).
1319 *
1320 * Returns true if expected current transfer is still running or double
1321 * buffer mode is not activated.
1322 */
stm32_dma_is_current_sg(struct stm32_dma_chan * chan)1323 static bool stm32_dma_is_current_sg(struct stm32_dma_chan *chan)
1324 {
1325 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1326 struct stm32_dma_sg_req *sg_req;
1327 u32 dma_scr, dma_smar, id, period_len;
1328
1329 id = chan->id;
1330 dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
1331
1332 /* In cyclic CIRC but not DBM, CT is not used */
1333 if (!(dma_scr & STM32_DMA_SCR_DBM))
1334 return true;
1335
1336 sg_req = &chan->desc->sg_req[chan->next_sg];
1337 period_len = sg_req->len;
1338
1339 /* DBM - take care of a previous pause/resume not yet post reconfigured */
1340 if (dma_scr & STM32_DMA_SCR_CT) {
1341 dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(id));
1342 /*
1343 * If transfer has been pause/resumed,
1344 * SM0AR is in the range of [SM0AR:SM0AR+period_len]
1345 */
1346 return (dma_smar >= sg_req->chan_reg.dma_sm0ar &&
1347 dma_smar < sg_req->chan_reg.dma_sm0ar + period_len);
1348 }
1349
1350 dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(id));
1351 /*
1352 * If transfer has been pause/resumed,
1353 * SM1AR is in the range of [SM1AR:SM1AR+period_len]
1354 */
1355 return (dma_smar >= sg_req->chan_reg.dma_sm1ar &&
1356 dma_smar < sg_req->chan_reg.dma_sm1ar + period_len);
1357 }
1358
stm32_dma_desc_residue(struct stm32_dma_chan * chan,struct stm32_dma_desc * desc,u32 next_sg)1359 static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan,
1360 struct stm32_dma_desc *desc,
1361 u32 next_sg)
1362 {
1363 u32 modulo, burst_size;
1364 u32 residue;
1365 u32 n_sg = next_sg;
1366 struct stm32_dma_sg_req *sg_req = &chan->desc->sg_req[chan->next_sg];
1367 int i;
1368
1369 /*
1370 * Calculate the residue means compute the descriptors
1371 * information:
1372 * - the sg_req currently transferred
1373 * - the Hardware remaining position in this sg (NDTR bits field).
1374 *
1375 * A race condition may occur if DMA is running in cyclic or double
1376 * buffer mode, since the DMA register are automatically reloaded at end
1377 * of period transfer. The hardware may have switched to the next
1378 * transfer (CT bit updated) just before the position (SxNDTR reg) is
1379 * read.
1380 * In this case the SxNDTR reg could (or not) correspond to the new
1381 * transfer position, and not the expected one.
1382 * The strategy implemented in the stm32 driver is to:
1383 * - read the SxNDTR register
1384 * - crosscheck that hardware is still in current transfer.
1385 * In case of switch, we can assume that the DMA is at the beginning of
1386 * the next transfer. So we approximate the residue in consequence, by
1387 * pointing on the beginning of next transfer.
1388 *
1389 * This race condition doesn't apply for none cyclic mode, as double
1390 * buffer is not used. In such situation registers are updated by the
1391 * software.
1392 */
1393
1394 residue = stm32_dma_get_remaining_bytes(chan);
1395
1396 if ((chan->desc->cyclic || chan->trig_mdma) && !stm32_dma_is_current_sg(chan)) {
1397 n_sg++;
1398 if (n_sg == chan->desc->num_sgs)
1399 n_sg = 0;
1400 if (!chan->trig_mdma)
1401 residue = sg_req->len;
1402 }
1403
1404 /*
1405 * In cyclic mode, for the last period, residue = remaining bytes
1406 * from NDTR,
1407 * else for all other periods in cyclic mode, and in sg mode,
1408 * residue = remaining bytes from NDTR + remaining
1409 * periods/sg to be transferred
1410 */
1411 if ((!chan->desc->cyclic && !chan->trig_mdma) || n_sg != 0)
1412 for (i = n_sg; i < desc->num_sgs; i++)
1413 residue += desc->sg_req[i].len;
1414
1415 if (!chan->mem_burst)
1416 return residue;
1417
1418 burst_size = chan->mem_burst * chan->mem_width;
1419 modulo = residue % burst_size;
1420 if (modulo)
1421 residue = residue - modulo + burst_size;
1422
1423 return residue;
1424 }
1425
stm32_dma_tx_status(struct dma_chan * c,dma_cookie_t cookie,struct dma_tx_state * state)1426 static enum dma_status stm32_dma_tx_status(struct dma_chan *c,
1427 dma_cookie_t cookie,
1428 struct dma_tx_state *state)
1429 {
1430 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1431 struct virt_dma_desc *vdesc;
1432 enum dma_status status;
1433 unsigned long flags;
1434 u32 residue = 0;
1435
1436 status = dma_cookie_status(c, cookie, state);
1437 if (status == DMA_COMPLETE)
1438 return status;
1439
1440 status = chan->status;
1441
1442 if (!state)
1443 return status;
1444
1445 spin_lock_irqsave(&chan->vchan.lock, flags);
1446 vdesc = vchan_find_desc(&chan->vchan, cookie);
1447 if (chan->desc && cookie == chan->desc->vdesc.tx.cookie)
1448 residue = stm32_dma_desc_residue(chan, chan->desc,
1449 chan->next_sg);
1450 else if (vdesc)
1451 residue = stm32_dma_desc_residue(chan,
1452 to_stm32_dma_desc(vdesc), 0);
1453 dma_set_residue(state, residue);
1454
1455 spin_unlock_irqrestore(&chan->vchan.lock, flags);
1456
1457 return status;
1458 }
1459
stm32_dma_alloc_chan_resources(struct dma_chan * c)1460 static int stm32_dma_alloc_chan_resources(struct dma_chan *c)
1461 {
1462 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1463 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1464 int ret;
1465
1466 chan->config_init = false;
1467
1468 ret = pm_runtime_resume_and_get(dmadev->ddev.dev);
1469 if (ret < 0)
1470 return ret;
1471
1472 ret = stm32_dma_disable_chan(chan);
1473 if (ret < 0)
1474 pm_runtime_put(dmadev->ddev.dev);
1475
1476 return ret;
1477 }
1478
stm32_dma_free_chan_resources(struct dma_chan * c)1479 static void stm32_dma_free_chan_resources(struct dma_chan *c)
1480 {
1481 struct stm32_dma_chan *chan = to_stm32_dma_chan(c);
1482 struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan);
1483 unsigned long flags;
1484
1485 dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id);
1486
1487 if (chan->busy) {
1488 spin_lock_irqsave(&chan->vchan.lock, flags);
1489 stm32_dma_stop(chan);
1490 chan->desc = NULL;
1491 spin_unlock_irqrestore(&chan->vchan.lock, flags);
1492 }
1493
1494 pm_runtime_put(dmadev->ddev.dev);
1495
1496 vchan_free_chan_resources(to_virt_chan(c));
1497 stm32_dma_clear_reg(&chan->chan_reg);
1498 chan->threshold = 0;
1499 }
1500
stm32_dma_desc_free(struct virt_dma_desc * vdesc)1501 static void stm32_dma_desc_free(struct virt_dma_desc *vdesc)
1502 {
1503 kfree(container_of(vdesc, struct stm32_dma_desc, vdesc));
1504 }
1505
stm32_dma_set_config(struct stm32_dma_chan * chan,struct stm32_dma_cfg * cfg)1506 static void stm32_dma_set_config(struct stm32_dma_chan *chan,
1507 struct stm32_dma_cfg *cfg)
1508 {
1509 stm32_dma_clear_reg(&chan->chan_reg);
1510
1511 chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK;
1512 chan->chan_reg.dma_scr |= FIELD_PREP(STM32_DMA_SCR_REQ_MASK, cfg->request_line);
1513
1514 /* Enable Interrupts */
1515 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE;
1516
1517 chan->threshold = FIELD_GET(STM32_DMA_THRESHOLD_FTR_MASK, cfg->features);
1518 if (FIELD_GET(STM32_DMA_DIRECT_MODE_MASK, cfg->features))
1519 chan->threshold = STM32_DMA_FIFO_THRESHOLD_NONE;
1520 if (FIELD_GET(STM32_DMA_ALT_ACK_MODE_MASK, cfg->features))
1521 chan->chan_reg.dma_scr |= STM32_DMA_SCR_TRBUFF;
1522 chan->mdma_config.stream_id = FIELD_GET(STM32_DMA_MDMA_STREAM_ID_MASK, cfg->features);
1523 }
1524
stm32_dma_of_xlate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)1525 static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec,
1526 struct of_dma *ofdma)
1527 {
1528 struct stm32_dma_device *dmadev = ofdma->of_dma_data;
1529 struct device *dev = dmadev->ddev.dev;
1530 struct stm32_dma_cfg cfg;
1531 struct stm32_dma_chan *chan;
1532 struct dma_chan *c;
1533
1534 if (dma_spec->args_count < 4) {
1535 dev_err(dev, "Bad number of cells\n");
1536 return NULL;
1537 }
1538
1539 cfg.channel_id = dma_spec->args[0];
1540 cfg.request_line = dma_spec->args[1];
1541 cfg.stream_config = dma_spec->args[2];
1542 cfg.features = dma_spec->args[3];
1543
1544 if (cfg.channel_id >= STM32_DMA_MAX_CHANNELS ||
1545 cfg.request_line >= STM32_DMA_MAX_REQUEST_ID) {
1546 dev_err(dev, "Bad channel and/or request id\n");
1547 return NULL;
1548 }
1549
1550 chan = &dmadev->chan[cfg.channel_id];
1551
1552 c = dma_get_slave_channel(&chan->vchan.chan);
1553 if (!c) {
1554 dev_err(dev, "No more channels available\n");
1555 return NULL;
1556 }
1557
1558 stm32_dma_set_config(chan, &cfg);
1559
1560 return c;
1561 }
1562
1563 static const struct of_device_id stm32_dma_of_match[] = {
1564 { .compatible = "st,stm32-dma", },
1565 { /* sentinel */ },
1566 };
1567 MODULE_DEVICE_TABLE(of, stm32_dma_of_match);
1568
stm32_dma_probe(struct platform_device * pdev)1569 static int stm32_dma_probe(struct platform_device *pdev)
1570 {
1571 struct stm32_dma_chan *chan;
1572 struct stm32_dma_device *dmadev;
1573 struct dma_device *dd;
1574 const struct of_device_id *match;
1575 struct resource *res;
1576 struct reset_control *rst;
1577 int i, ret;
1578
1579 match = of_match_device(stm32_dma_of_match, &pdev->dev);
1580 if (!match) {
1581 dev_err(&pdev->dev, "Error: No device match found\n");
1582 return -ENODEV;
1583 }
1584
1585 dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
1586 if (!dmadev)
1587 return -ENOMEM;
1588
1589 dd = &dmadev->ddev;
1590
1591 dmadev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1592 if (IS_ERR(dmadev->base))
1593 return PTR_ERR(dmadev->base);
1594
1595 dmadev->clk = devm_clk_get(&pdev->dev, NULL);
1596 if (IS_ERR(dmadev->clk))
1597 return dev_err_probe(&pdev->dev, PTR_ERR(dmadev->clk), "Can't get clock\n");
1598
1599 ret = clk_prepare_enable(dmadev->clk);
1600 if (ret < 0) {
1601 dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret);
1602 return ret;
1603 }
1604
1605 dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node,
1606 "st,mem2mem");
1607
1608 rst = devm_reset_control_get(&pdev->dev, NULL);
1609 if (IS_ERR(rst)) {
1610 ret = PTR_ERR(rst);
1611 if (ret == -EPROBE_DEFER)
1612 goto clk_free;
1613 } else {
1614 reset_control_assert(rst);
1615 udelay(2);
1616 reset_control_deassert(rst);
1617 }
1618
1619 dma_set_max_seg_size(&pdev->dev, STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
1620
1621 dma_cap_set(DMA_SLAVE, dd->cap_mask);
1622 dma_cap_set(DMA_PRIVATE, dd->cap_mask);
1623 dma_cap_set(DMA_CYCLIC, dd->cap_mask);
1624 dd->device_alloc_chan_resources = stm32_dma_alloc_chan_resources;
1625 dd->device_free_chan_resources = stm32_dma_free_chan_resources;
1626 dd->device_tx_status = stm32_dma_tx_status;
1627 dd->device_issue_pending = stm32_dma_issue_pending;
1628 dd->device_prep_slave_sg = stm32_dma_prep_slave_sg;
1629 dd->device_prep_dma_cyclic = stm32_dma_prep_dma_cyclic;
1630 dd->device_config = stm32_dma_slave_config;
1631 dd->device_pause = stm32_dma_pause;
1632 dd->device_resume = stm32_dma_resume;
1633 dd->device_terminate_all = stm32_dma_terminate_all;
1634 dd->device_synchronize = stm32_dma_synchronize;
1635 dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1636 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1637 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1638 dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
1639 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
1640 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1641 dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1642 dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1643 dd->copy_align = DMAENGINE_ALIGN_32_BYTES;
1644 dd->max_burst = STM32_DMA_MAX_BURST;
1645 dd->max_sg_burst = STM32_DMA_ALIGNED_MAX_DATA_ITEMS;
1646 dd->descriptor_reuse = true;
1647 dd->dev = &pdev->dev;
1648 INIT_LIST_HEAD(&dd->channels);
1649
1650 if (dmadev->mem2mem) {
1651 dma_cap_set(DMA_MEMCPY, dd->cap_mask);
1652 dd->device_prep_dma_memcpy = stm32_dma_prep_dma_memcpy;
1653 dd->directions |= BIT(DMA_MEM_TO_MEM);
1654 }
1655
1656 for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
1657 chan = &dmadev->chan[i];
1658 chan->id = i;
1659 chan->vchan.desc_free = stm32_dma_desc_free;
1660 vchan_init(&chan->vchan, dd);
1661
1662 chan->mdma_config.ifcr = res->start;
1663 chan->mdma_config.ifcr += STM32_DMA_IFCR(chan->id);
1664
1665 chan->mdma_config.tcf = STM32_DMA_TCI;
1666 chan->mdma_config.tcf <<= STM32_DMA_FLAGS_SHIFT(chan->id);
1667 }
1668
1669 ret = dma_async_device_register(dd);
1670 if (ret)
1671 goto clk_free;
1672
1673 for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) {
1674 chan = &dmadev->chan[i];
1675 ret = platform_get_irq(pdev, i);
1676 if (ret < 0)
1677 goto err_unregister;
1678 chan->irq = ret;
1679
1680 ret = devm_request_irq(&pdev->dev, chan->irq,
1681 stm32_dma_chan_irq, 0,
1682 dev_name(chan2dev(chan)), chan);
1683 if (ret) {
1684 dev_err(&pdev->dev,
1685 "request_irq failed with err %d channel %d\n",
1686 ret, i);
1687 goto err_unregister;
1688 }
1689 }
1690
1691 ret = of_dma_controller_register(pdev->dev.of_node,
1692 stm32_dma_of_xlate, dmadev);
1693 if (ret < 0) {
1694 dev_err(&pdev->dev,
1695 "STM32 DMA DMA OF registration failed %d\n", ret);
1696 goto err_unregister;
1697 }
1698
1699 platform_set_drvdata(pdev, dmadev);
1700
1701 pm_runtime_set_active(&pdev->dev);
1702 pm_runtime_enable(&pdev->dev);
1703 pm_runtime_get_noresume(&pdev->dev);
1704 pm_runtime_put(&pdev->dev);
1705
1706 dev_info(&pdev->dev, "STM32 DMA driver registered\n");
1707
1708 return 0;
1709
1710 err_unregister:
1711 dma_async_device_unregister(dd);
1712 clk_free:
1713 clk_disable_unprepare(dmadev->clk);
1714
1715 return ret;
1716 }
1717
1718 #ifdef CONFIG_PM
stm32_dma_runtime_suspend(struct device * dev)1719 static int stm32_dma_runtime_suspend(struct device *dev)
1720 {
1721 struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1722
1723 clk_disable_unprepare(dmadev->clk);
1724
1725 return 0;
1726 }
1727
stm32_dma_runtime_resume(struct device * dev)1728 static int stm32_dma_runtime_resume(struct device *dev)
1729 {
1730 struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1731 int ret;
1732
1733 ret = clk_prepare_enable(dmadev->clk);
1734 if (ret) {
1735 dev_err(dev, "failed to prepare_enable clock\n");
1736 return ret;
1737 }
1738
1739 return 0;
1740 }
1741 #endif
1742
1743 #ifdef CONFIG_PM_SLEEP
stm32_dma_pm_suspend(struct device * dev)1744 static int stm32_dma_pm_suspend(struct device *dev)
1745 {
1746 struct stm32_dma_device *dmadev = dev_get_drvdata(dev);
1747 int id, ret, scr;
1748
1749 ret = pm_runtime_resume_and_get(dev);
1750 if (ret < 0)
1751 return ret;
1752
1753 for (id = 0; id < STM32_DMA_MAX_CHANNELS; id++) {
1754 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id));
1755 if (scr & STM32_DMA_SCR_EN) {
1756 dev_warn(dev, "Suspend is prevented by Chan %i\n", id);
1757 return -EBUSY;
1758 }
1759 }
1760
1761 pm_runtime_put_sync(dev);
1762
1763 pm_runtime_force_suspend(dev);
1764
1765 return 0;
1766 }
1767
stm32_dma_pm_resume(struct device * dev)1768 static int stm32_dma_pm_resume(struct device *dev)
1769 {
1770 return pm_runtime_force_resume(dev);
1771 }
1772 #endif
1773
1774 static const struct dev_pm_ops stm32_dma_pm_ops = {
1775 SET_SYSTEM_SLEEP_PM_OPS(stm32_dma_pm_suspend, stm32_dma_pm_resume)
1776 SET_RUNTIME_PM_OPS(stm32_dma_runtime_suspend,
1777 stm32_dma_runtime_resume, NULL)
1778 };
1779
1780 static struct platform_driver stm32_dma_driver = {
1781 .driver = {
1782 .name = "stm32-dma",
1783 .of_match_table = stm32_dma_of_match,
1784 .pm = &stm32_dma_pm_ops,
1785 },
1786 .probe = stm32_dma_probe,
1787 };
1788
stm32_dma_init(void)1789 static int __init stm32_dma_init(void)
1790 {
1791 return platform_driver_register(&stm32_dma_driver);
1792 }
1793 subsys_initcall(stm32_dma_init);
1794