1d8b46839SM'boumba Cedric Madianga /* 2d8b46839SM'boumba Cedric Madianga * Driver for STM32 DMA controller 3d8b46839SM'boumba Cedric Madianga * 4d8b46839SM'boumba Cedric Madianga * Inspired by dma-jz4740.c and tegra20-apb-dma.c 5d8b46839SM'boumba Cedric Madianga * 6d8b46839SM'boumba Cedric Madianga * Copyright (C) M'boumba Cedric Madianga 2015 7d8b46839SM'boumba Cedric Madianga * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 8a2b6103bSPierre Yves MORDRET * Pierre-Yves Mordret <pierre-yves.mordret@st.com> 9d8b46839SM'boumba Cedric Madianga * 10d8b46839SM'boumba Cedric Madianga * License terms: GNU General Public License (GPL), version 2 11d8b46839SM'boumba Cedric Madianga */ 12d8b46839SM'boumba Cedric Madianga 13d8b46839SM'boumba Cedric Madianga #include <linux/clk.h> 14d8b46839SM'boumba Cedric Madianga #include <linux/delay.h> 15d8b46839SM'boumba Cedric Madianga #include <linux/dmaengine.h> 16d8b46839SM'boumba Cedric Madianga #include <linux/dma-mapping.h> 17d8b46839SM'boumba Cedric Madianga #include <linux/err.h> 18d8b46839SM'boumba Cedric Madianga #include <linux/init.h> 19d8b46839SM'boumba Cedric Madianga #include <linux/jiffies.h> 20d8b46839SM'boumba Cedric Madianga #include <linux/list.h> 21d8b46839SM'boumba Cedric Madianga #include <linux/module.h> 22d8b46839SM'boumba Cedric Madianga #include <linux/of.h> 23d8b46839SM'boumba Cedric Madianga #include <linux/of_device.h> 24d8b46839SM'boumba Cedric Madianga #include <linux/of_dma.h> 25d8b46839SM'boumba Cedric Madianga #include <linux/platform_device.h> 2648bc73baSPierre-Yves MORDRET #include <linux/pm_runtime.h> 27d8b46839SM'boumba Cedric Madianga #include <linux/reset.h> 28d8b46839SM'boumba Cedric Madianga #include <linux/sched.h> 29d8b46839SM'boumba Cedric Madianga #include <linux/slab.h> 30d8b46839SM'boumba Cedric Madianga 31d8b46839SM'boumba Cedric Madianga #include "virt-dma.h" 32d8b46839SM'boumba Cedric Madianga 33d8b46839SM'boumba Cedric Madianga #define STM32_DMA_LISR 0x0000 /* DMA Low Int Status Reg */ 34d8b46839SM'boumba Cedric Madianga #define STM32_DMA_HISR 0x0004 /* DMA High Int Status Reg */ 35d8b46839SM'boumba Cedric Madianga #define STM32_DMA_LIFCR 0x0008 /* DMA Low Int Flag Clear Reg */ 36d8b46839SM'boumba Cedric Madianga #define STM32_DMA_HIFCR 0x000c /* DMA High Int Flag Clear Reg */ 37d8b46839SM'boumba Cedric Madianga #define STM32_DMA_TCI BIT(5) /* Transfer Complete Interrupt */ 38c2d86b1cSPierre Yves MORDRET #define STM32_DMA_HTI BIT(4) /* Half Transfer Interrupt */ 39d8b46839SM'boumba Cedric Madianga #define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */ 40d8b46839SM'boumba Cedric Madianga #define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */ 41d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */ 429df3bd55SPierre Yves MORDRET #define STM32_DMA_MASKI (STM32_DMA_TCI \ 439df3bd55SPierre Yves MORDRET | STM32_DMA_TEI \ 449df3bd55SPierre Yves MORDRET | STM32_DMA_DMEI \ 459df3bd55SPierre Yves MORDRET | STM32_DMA_FEI) 46d8b46839SM'boumba Cedric Madianga 47d8b46839SM'boumba Cedric Madianga /* DMA Stream x Configuration Register */ 48d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */ 49d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_REQ(n) ((n & 0x7) << 25) 50d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MBURST_MASK GENMASK(24, 23) 51d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MBURST(n) ((n & 0x3) << 23) 52d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PBURST_MASK GENMASK(22, 21) 53d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PBURST(n) ((n & 0x3) << 21) 54d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PL_MASK GENMASK(17, 16) 55d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PL(n) ((n & 0x3) << 16) 56d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MSIZE_MASK GENMASK(14, 13) 57d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MSIZE(n) ((n & 0x3) << 13) 58d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PSIZE_MASK GENMASK(12, 11) 59d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PSIZE(n) ((n & 0x3) << 11) 60d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PSIZE_GET(n) ((n & STM32_DMA_SCR_PSIZE_MASK) >> 11) 61d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_DIR_MASK GENMASK(7, 6) 62d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_DIR(n) ((n & 0x3) << 6) 63d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_CT BIT(19) /* Target in double buffer */ 64d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_DBM BIT(18) /* Double Buffer Mode */ 65d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PINCOS BIT(15) /* Peripheral inc offset size */ 66d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MINC BIT(10) /* Memory increment mode */ 67d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PINC BIT(9) /* Peripheral increment mode */ 68d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_CIRC BIT(8) /* Circular mode */ 69d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PFCTRL BIT(5) /* Peripheral Flow Controller */ 70249d5531SPierre Yves MORDRET #define STM32_DMA_SCR_TCIE BIT(4) /* Transfer Complete Int Enable 71249d5531SPierre Yves MORDRET */ 72d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_TEIE BIT(2) /* Transfer Error Int Enable */ 73d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_DMEIE BIT(1) /* Direct Mode Err Int Enable */ 74d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_EN BIT(0) /* Stream Enable */ 75d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_CFG_MASK (STM32_DMA_SCR_PINC \ 76d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_MINC \ 77d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_PINCOS \ 78d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_PL_MASK) 79d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_IRQ_MASK (STM32_DMA_SCR_TCIE \ 80d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_TEIE \ 81d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_DMEIE) 82d8b46839SM'boumba Cedric Madianga 83d8b46839SM'boumba Cedric Madianga /* DMA Stream x number of data register */ 84d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SNDTR(x) (0x0014 + 0x18 * (x)) 85d8b46839SM'boumba Cedric Madianga 86d8b46839SM'boumba Cedric Madianga /* DMA stream peripheral address register */ 87d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SPAR(x) (0x0018 + 0x18 * (x)) 88d8b46839SM'boumba Cedric Madianga 89d8b46839SM'boumba Cedric Madianga /* DMA stream x memory 0 address register */ 90d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SM0AR(x) (0x001c + 0x18 * (x)) 91d8b46839SM'boumba Cedric Madianga 92d8b46839SM'boumba Cedric Madianga /* DMA stream x memory 1 address register */ 93d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SM1AR(x) (0x0020 + 0x18 * (x)) 94d8b46839SM'boumba Cedric Madianga 95d8b46839SM'boumba Cedric Madianga /* DMA stream x FIFO control register */ 96d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR(x) (0x0024 + 0x18 * (x)) 97d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_FTH_MASK GENMASK(1, 0) 98d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_FTH(n) (n & STM32_DMA_SFCR_FTH_MASK) 99d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_FEIE BIT(7) /* FIFO error interrupt enable */ 100d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_DMDIS BIT(2) /* Direct mode disable */ 101d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_MASK (STM32_DMA_SFCR_FEIE \ 102d8b46839SM'boumba Cedric Madianga | STM32_DMA_SFCR_DMDIS) 103d8b46839SM'boumba Cedric Madianga 104d8b46839SM'boumba Cedric Madianga /* DMA direction */ 105d8b46839SM'boumba Cedric Madianga #define STM32_DMA_DEV_TO_MEM 0x00 106d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MEM_TO_DEV 0x01 107d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MEM_TO_MEM 0x02 108d8b46839SM'boumba Cedric Madianga 109d8b46839SM'boumba Cedric Madianga /* DMA priority level */ 110d8b46839SM'boumba Cedric Madianga #define STM32_DMA_PRIORITY_LOW 0x00 111d8b46839SM'boumba Cedric Madianga #define STM32_DMA_PRIORITY_MEDIUM 0x01 112d8b46839SM'boumba Cedric Madianga #define STM32_DMA_PRIORITY_HIGH 0x02 113d8b46839SM'boumba Cedric Madianga #define STM32_DMA_PRIORITY_VERY_HIGH 0x03 114d8b46839SM'boumba Cedric Madianga 115d8b46839SM'boumba Cedric Madianga /* DMA FIFO threshold selection */ 116d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00 117d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FIFO_THRESHOLD_HALFFULL 0x01 118d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FIFO_THRESHOLD_3QUARTERSFULL 0x02 119d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FIFO_THRESHOLD_FULL 0x03 120d8b46839SM'boumba Cedric Madianga 121d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MAX_DATA_ITEMS 0xffff 12280a76952SPierre Yves MORDRET /* 12380a76952SPierre Yves MORDRET * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter 12480a76952SPierre Yves MORDRET * gather at boundary. Thus it's safer to round down this value on FIFO 12580a76952SPierre Yves MORDRET * size (16 Bytes) 12680a76952SPierre Yves MORDRET */ 12780a76952SPierre Yves MORDRET #define STM32_DMA_ALIGNED_MAX_DATA_ITEMS \ 12880a76952SPierre Yves MORDRET ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16) 129d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MAX_CHANNELS 0x08 130d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MAX_REQUEST_ID 0x08 131d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MAX_DATA_PARAM 0x03 132a2b6103bSPierre Yves MORDRET #define STM32_DMA_FIFO_SIZE 16 /* FIFO is 16 bytes */ 133a2b6103bSPierre Yves MORDRET #define STM32_DMA_MIN_BURST 4 134276b0046SM'boumba Cedric Madianga #define STM32_DMA_MAX_BURST 16 135d8b46839SM'boumba Cedric Madianga 136951f44cbSPierre Yves MORDRET /* DMA Features */ 137951f44cbSPierre Yves MORDRET #define STM32_DMA_THRESHOLD_FTR_MASK GENMASK(1, 0) 138951f44cbSPierre Yves MORDRET #define STM32_DMA_THRESHOLD_FTR_GET(n) ((n) & STM32_DMA_THRESHOLD_FTR_MASK) 139951f44cbSPierre Yves MORDRET 140d8b46839SM'boumba Cedric Madianga enum stm32_dma_width { 141d8b46839SM'boumba Cedric Madianga STM32_DMA_BYTE, 142d8b46839SM'boumba Cedric Madianga STM32_DMA_HALF_WORD, 143d8b46839SM'boumba Cedric Madianga STM32_DMA_WORD, 144d8b46839SM'boumba Cedric Madianga }; 145d8b46839SM'boumba Cedric Madianga 146d8b46839SM'boumba Cedric Madianga enum stm32_dma_burst_size { 147d8b46839SM'boumba Cedric Madianga STM32_DMA_BURST_SINGLE, 148d8b46839SM'boumba Cedric Madianga STM32_DMA_BURST_INCR4, 149d8b46839SM'boumba Cedric Madianga STM32_DMA_BURST_INCR8, 150d8b46839SM'boumba Cedric Madianga STM32_DMA_BURST_INCR16, 151d8b46839SM'boumba Cedric Madianga }; 152d8b46839SM'boumba Cedric Madianga 153951f44cbSPierre Yves MORDRET /** 154951f44cbSPierre Yves MORDRET * struct stm32_dma_cfg - STM32 DMA custom configuration 155951f44cbSPierre Yves MORDRET * @channel_id: channel ID 156951f44cbSPierre Yves MORDRET * @request_line: DMA request 157951f44cbSPierre Yves MORDRET * @stream_config: 32bit mask specifying the DMA channel configuration 158951f44cbSPierre Yves MORDRET * @features: 32bit mask specifying the DMA Feature list 159951f44cbSPierre Yves MORDRET */ 160d8b46839SM'boumba Cedric Madianga struct stm32_dma_cfg { 161d8b46839SM'boumba Cedric Madianga u32 channel_id; 162d8b46839SM'boumba Cedric Madianga u32 request_line; 163d8b46839SM'boumba Cedric Madianga u32 stream_config; 164951f44cbSPierre Yves MORDRET u32 features; 165d8b46839SM'boumba Cedric Madianga }; 166d8b46839SM'boumba Cedric Madianga 167d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan_reg { 168d8b46839SM'boumba Cedric Madianga u32 dma_lisr; 169d8b46839SM'boumba Cedric Madianga u32 dma_hisr; 170d8b46839SM'boumba Cedric Madianga u32 dma_lifcr; 171d8b46839SM'boumba Cedric Madianga u32 dma_hifcr; 172d8b46839SM'boumba Cedric Madianga u32 dma_scr; 173d8b46839SM'boumba Cedric Madianga u32 dma_sndtr; 174d8b46839SM'boumba Cedric Madianga u32 dma_spar; 175d8b46839SM'boumba Cedric Madianga u32 dma_sm0ar; 176d8b46839SM'boumba Cedric Madianga u32 dma_sm1ar; 177d8b46839SM'boumba Cedric Madianga u32 dma_sfcr; 178d8b46839SM'boumba Cedric Madianga }; 179d8b46839SM'boumba Cedric Madianga 180d8b46839SM'boumba Cedric Madianga struct stm32_dma_sg_req { 181d8b46839SM'boumba Cedric Madianga u32 len; 182d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan_reg chan_reg; 183d8b46839SM'boumba Cedric Madianga }; 184d8b46839SM'boumba Cedric Madianga 185d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc { 186d8b46839SM'boumba Cedric Madianga struct virt_dma_desc vdesc; 187d8b46839SM'boumba Cedric Madianga bool cyclic; 188d8b46839SM'boumba Cedric Madianga u32 num_sgs; 189d8b46839SM'boumba Cedric Madianga struct stm32_dma_sg_req sg_req[]; 190d8b46839SM'boumba Cedric Madianga }; 191d8b46839SM'boumba Cedric Madianga 192d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan { 193d8b46839SM'boumba Cedric Madianga struct virt_dma_chan vchan; 194d8b46839SM'boumba Cedric Madianga bool config_init; 195d8b46839SM'boumba Cedric Madianga bool busy; 196d8b46839SM'boumba Cedric Madianga u32 id; 197d8b46839SM'boumba Cedric Madianga u32 irq; 198d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc; 199d8b46839SM'boumba Cedric Madianga u32 next_sg; 200d8b46839SM'boumba Cedric Madianga struct dma_slave_config dma_sconfig; 201d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan_reg chan_reg; 202951f44cbSPierre Yves MORDRET u32 threshold; 203a2b6103bSPierre Yves MORDRET u32 mem_burst; 204a2b6103bSPierre Yves MORDRET u32 mem_width; 205d8b46839SM'boumba Cedric Madianga }; 206d8b46839SM'boumba Cedric Madianga 207d8b46839SM'boumba Cedric Madianga struct stm32_dma_device { 208d8b46839SM'boumba Cedric Madianga struct dma_device ddev; 209d8b46839SM'boumba Cedric Madianga void __iomem *base; 210d8b46839SM'boumba Cedric Madianga struct clk *clk; 211d8b46839SM'boumba Cedric Madianga struct reset_control *rst; 212d8b46839SM'boumba Cedric Madianga bool mem2mem; 213d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS]; 214d8b46839SM'boumba Cedric Madianga }; 215d8b46839SM'boumba Cedric Madianga 216d8b46839SM'boumba Cedric Madianga static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan) 217d8b46839SM'boumba Cedric Madianga { 218d8b46839SM'boumba Cedric Madianga return container_of(chan->vchan.chan.device, struct stm32_dma_device, 219d8b46839SM'boumba Cedric Madianga ddev); 220d8b46839SM'boumba Cedric Madianga } 221d8b46839SM'boumba Cedric Madianga 222d8b46839SM'boumba Cedric Madianga static struct stm32_dma_chan *to_stm32_dma_chan(struct dma_chan *c) 223d8b46839SM'boumba Cedric Madianga { 224d8b46839SM'boumba Cedric Madianga return container_of(c, struct stm32_dma_chan, vchan.chan); 225d8b46839SM'boumba Cedric Madianga } 226d8b46839SM'boumba Cedric Madianga 227d8b46839SM'boumba Cedric Madianga static struct stm32_dma_desc *to_stm32_dma_desc(struct virt_dma_desc *vdesc) 228d8b46839SM'boumba Cedric Madianga { 229d8b46839SM'boumba Cedric Madianga return container_of(vdesc, struct stm32_dma_desc, vdesc); 230d8b46839SM'boumba Cedric Madianga } 231d8b46839SM'boumba Cedric Madianga 232d8b46839SM'boumba Cedric Madianga static struct device *chan2dev(struct stm32_dma_chan *chan) 233d8b46839SM'boumba Cedric Madianga { 234d8b46839SM'boumba Cedric Madianga return &chan->vchan.chan.dev->device; 235d8b46839SM'boumba Cedric Madianga } 236d8b46839SM'boumba Cedric Madianga 237d8b46839SM'boumba Cedric Madianga static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg) 238d8b46839SM'boumba Cedric Madianga { 239d8b46839SM'boumba Cedric Madianga return readl_relaxed(dmadev->base + reg); 240d8b46839SM'boumba Cedric Madianga } 241d8b46839SM'boumba Cedric Madianga 242d8b46839SM'boumba Cedric Madianga static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val) 243d8b46839SM'boumba Cedric Madianga { 244d8b46839SM'boumba Cedric Madianga writel_relaxed(val, dmadev->base + reg); 245d8b46839SM'boumba Cedric Madianga } 246d8b46839SM'boumba Cedric Madianga 247d8b46839SM'boumba Cedric Madianga static struct stm32_dma_desc *stm32_dma_alloc_desc(u32 num_sgs) 248d8b46839SM'boumba Cedric Madianga { 249d8b46839SM'boumba Cedric Madianga return kzalloc(sizeof(struct stm32_dma_desc) + 250d8b46839SM'boumba Cedric Madianga sizeof(struct stm32_dma_sg_req) * num_sgs, GFP_NOWAIT); 251d8b46839SM'boumba Cedric Madianga } 252d8b46839SM'boumba Cedric Madianga 253d8b46839SM'boumba Cedric Madianga static int stm32_dma_get_width(struct stm32_dma_chan *chan, 254d8b46839SM'boumba Cedric Madianga enum dma_slave_buswidth width) 255d8b46839SM'boumba Cedric Madianga { 256d8b46839SM'boumba Cedric Madianga switch (width) { 257d8b46839SM'boumba Cedric Madianga case DMA_SLAVE_BUSWIDTH_1_BYTE: 258d8b46839SM'boumba Cedric Madianga return STM32_DMA_BYTE; 259d8b46839SM'boumba Cedric Madianga case DMA_SLAVE_BUSWIDTH_2_BYTES: 260d8b46839SM'boumba Cedric Madianga return STM32_DMA_HALF_WORD; 261d8b46839SM'boumba Cedric Madianga case DMA_SLAVE_BUSWIDTH_4_BYTES: 262d8b46839SM'boumba Cedric Madianga return STM32_DMA_WORD; 263d8b46839SM'boumba Cedric Madianga default: 264d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Dma bus width not supported\n"); 265d8b46839SM'boumba Cedric Madianga return -EINVAL; 266d8b46839SM'boumba Cedric Madianga } 267d8b46839SM'boumba Cedric Madianga } 268d8b46839SM'boumba Cedric Madianga 269a2b6103bSPierre Yves MORDRET static enum dma_slave_buswidth stm32_dma_get_max_width(u32 buf_len, 270a2b6103bSPierre Yves MORDRET u32 threshold) 271a2b6103bSPierre Yves MORDRET { 272a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth max_width; 273a2b6103bSPierre Yves MORDRET 274a2b6103bSPierre Yves MORDRET if (threshold == STM32_DMA_FIFO_THRESHOLD_FULL) 275a2b6103bSPierre Yves MORDRET max_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 276a2b6103bSPierre Yves MORDRET else 277a2b6103bSPierre Yves MORDRET max_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 278a2b6103bSPierre Yves MORDRET 279a2b6103bSPierre Yves MORDRET while ((buf_len < max_width || buf_len % max_width) && 280a2b6103bSPierre Yves MORDRET max_width > DMA_SLAVE_BUSWIDTH_1_BYTE) 281a2b6103bSPierre Yves MORDRET max_width = max_width >> 1; 282a2b6103bSPierre Yves MORDRET 283a2b6103bSPierre Yves MORDRET return max_width; 284a2b6103bSPierre Yves MORDRET } 285a2b6103bSPierre Yves MORDRET 286a2b6103bSPierre Yves MORDRET static bool stm32_dma_fifo_threshold_is_allowed(u32 burst, u32 threshold, 287a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth width) 288a2b6103bSPierre Yves MORDRET { 289a2b6103bSPierre Yves MORDRET u32 remaining; 290a2b6103bSPierre Yves MORDRET 291a2b6103bSPierre Yves MORDRET if (width != DMA_SLAVE_BUSWIDTH_UNDEFINED) { 292a2b6103bSPierre Yves MORDRET if (burst != 0) { 293a2b6103bSPierre Yves MORDRET /* 294a2b6103bSPierre Yves MORDRET * If number of beats fit in several whole bursts 295a2b6103bSPierre Yves MORDRET * this configuration is allowed. 296a2b6103bSPierre Yves MORDRET */ 297a2b6103bSPierre Yves MORDRET remaining = ((STM32_DMA_FIFO_SIZE / width) * 298a2b6103bSPierre Yves MORDRET (threshold + 1) / 4) % burst; 299a2b6103bSPierre Yves MORDRET 300a2b6103bSPierre Yves MORDRET if (remaining == 0) 301a2b6103bSPierre Yves MORDRET return true; 302a2b6103bSPierre Yves MORDRET } else { 303a2b6103bSPierre Yves MORDRET return true; 304a2b6103bSPierre Yves MORDRET } 305a2b6103bSPierre Yves MORDRET } 306a2b6103bSPierre Yves MORDRET 307a2b6103bSPierre Yves MORDRET return false; 308a2b6103bSPierre Yves MORDRET } 309a2b6103bSPierre Yves MORDRET 310a2b6103bSPierre Yves MORDRET static bool stm32_dma_is_burst_possible(u32 buf_len, u32 threshold) 311a2b6103bSPierre Yves MORDRET { 312cc832dc8SPierre-Yves MORDRET /* 313cc832dc8SPierre-Yves MORDRET * Buffer or period length has to be aligned on FIFO depth. 314cc832dc8SPierre-Yves MORDRET * Otherwise bytes may be stuck within FIFO at buffer or period 315cc832dc8SPierre-Yves MORDRET * length. 316cc832dc8SPierre-Yves MORDRET */ 317cc832dc8SPierre-Yves MORDRET return ((buf_len % ((threshold + 1) * 4)) == 0); 318a2b6103bSPierre Yves MORDRET } 319a2b6103bSPierre Yves MORDRET 320a2b6103bSPierre Yves MORDRET static u32 stm32_dma_get_best_burst(u32 buf_len, u32 max_burst, u32 threshold, 321a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth width) 322a2b6103bSPierre Yves MORDRET { 323a2b6103bSPierre Yves MORDRET u32 best_burst = max_burst; 324a2b6103bSPierre Yves MORDRET 325a2b6103bSPierre Yves MORDRET if (best_burst == 1 || !stm32_dma_is_burst_possible(buf_len, threshold)) 326a2b6103bSPierre Yves MORDRET return 0; 327a2b6103bSPierre Yves MORDRET 328a2b6103bSPierre Yves MORDRET while ((buf_len < best_burst * width && best_burst > 1) || 329a2b6103bSPierre Yves MORDRET !stm32_dma_fifo_threshold_is_allowed(best_burst, threshold, 330a2b6103bSPierre Yves MORDRET width)) { 331a2b6103bSPierre Yves MORDRET if (best_burst > STM32_DMA_MIN_BURST) 332a2b6103bSPierre Yves MORDRET best_burst = best_burst >> 1; 333a2b6103bSPierre Yves MORDRET else 334a2b6103bSPierre Yves MORDRET best_burst = 0; 335a2b6103bSPierre Yves MORDRET } 336a2b6103bSPierre Yves MORDRET 337a2b6103bSPierre Yves MORDRET return best_burst; 338a2b6103bSPierre Yves MORDRET } 339a2b6103bSPierre Yves MORDRET 340d8b46839SM'boumba Cedric Madianga static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst) 341d8b46839SM'boumba Cedric Madianga { 342d8b46839SM'boumba Cedric Madianga switch (maxburst) { 343d8b46839SM'boumba Cedric Madianga case 0: 344d8b46839SM'boumba Cedric Madianga case 1: 345d8b46839SM'boumba Cedric Madianga return STM32_DMA_BURST_SINGLE; 346d8b46839SM'boumba Cedric Madianga case 4: 347d8b46839SM'boumba Cedric Madianga return STM32_DMA_BURST_INCR4; 348d8b46839SM'boumba Cedric Madianga case 8: 349d8b46839SM'boumba Cedric Madianga return STM32_DMA_BURST_INCR8; 350d8b46839SM'boumba Cedric Madianga case 16: 351d8b46839SM'boumba Cedric Madianga return STM32_DMA_BURST_INCR16; 352d8b46839SM'boumba Cedric Madianga default: 353d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Dma burst size not supported\n"); 354d8b46839SM'boumba Cedric Madianga return -EINVAL; 355d8b46839SM'boumba Cedric Madianga } 356d8b46839SM'boumba Cedric Madianga } 357d8b46839SM'boumba Cedric Madianga 358d8b46839SM'boumba Cedric Madianga static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan, 359a2b6103bSPierre Yves MORDRET u32 src_burst, u32 dst_burst) 360d8b46839SM'boumba Cedric Madianga { 361d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK; 362d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE; 363d8b46839SM'boumba Cedric Madianga 364a2b6103bSPierre Yves MORDRET if (!src_burst && !dst_burst) { 365d8b46839SM'boumba Cedric Madianga /* Using direct mode */ 366d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE; 367d8b46839SM'boumba Cedric Madianga } else { 368d8b46839SM'boumba Cedric Madianga /* Using FIFO mode */ 369d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; 370d8b46839SM'boumba Cedric Madianga } 371d8b46839SM'boumba Cedric Madianga } 372d8b46839SM'boumba Cedric Madianga 373d8b46839SM'boumba Cedric Madianga static int stm32_dma_slave_config(struct dma_chan *c, 374d8b46839SM'boumba Cedric Madianga struct dma_slave_config *config) 375d8b46839SM'boumba Cedric Madianga { 376d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 377d8b46839SM'boumba Cedric Madianga 378d8b46839SM'boumba Cedric Madianga memcpy(&chan->dma_sconfig, config, sizeof(*config)); 379d8b46839SM'boumba Cedric Madianga 380d8b46839SM'boumba Cedric Madianga chan->config_init = true; 381d8b46839SM'boumba Cedric Madianga 382d8b46839SM'boumba Cedric Madianga return 0; 383d8b46839SM'boumba Cedric Madianga } 384d8b46839SM'boumba Cedric Madianga 385d8b46839SM'boumba Cedric Madianga static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan) 386d8b46839SM'boumba Cedric Madianga { 387d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 388d8b46839SM'boumba Cedric Madianga u32 flags, dma_isr; 389d8b46839SM'boumba Cedric Madianga 390d8b46839SM'boumba Cedric Madianga /* 391d8b46839SM'boumba Cedric Madianga * Read "flags" from DMA_xISR register corresponding to the selected 392d8b46839SM'boumba Cedric Madianga * DMA channel at the correct bit offset inside that register. 393d8b46839SM'boumba Cedric Madianga * 394d8b46839SM'boumba Cedric Madianga * If (ch % 4) is 2 or 3, left shift the mask by 16 bits. 395d8b46839SM'boumba Cedric Madianga * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. 396d8b46839SM'boumba Cedric Madianga */ 397d8b46839SM'boumba Cedric Madianga 398d8b46839SM'boumba Cedric Madianga if (chan->id & 4) 399d8b46839SM'boumba Cedric Madianga dma_isr = stm32_dma_read(dmadev, STM32_DMA_HISR); 400d8b46839SM'boumba Cedric Madianga else 401d8b46839SM'boumba Cedric Madianga dma_isr = stm32_dma_read(dmadev, STM32_DMA_LISR); 402d8b46839SM'boumba Cedric Madianga 403d8b46839SM'boumba Cedric Madianga flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); 404d8b46839SM'boumba Cedric Madianga 4059df3bd55SPierre Yves MORDRET return flags & STM32_DMA_MASKI; 406d8b46839SM'boumba Cedric Madianga } 407d8b46839SM'boumba Cedric Madianga 408d8b46839SM'boumba Cedric Madianga static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags) 409d8b46839SM'boumba Cedric Madianga { 410d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 411d8b46839SM'boumba Cedric Madianga u32 dma_ifcr; 412d8b46839SM'boumba Cedric Madianga 413d8b46839SM'boumba Cedric Madianga /* 414d8b46839SM'boumba Cedric Madianga * Write "flags" to the DMA_xIFCR register corresponding to the selected 415d8b46839SM'boumba Cedric Madianga * DMA channel at the correct bit offset inside that register. 416d8b46839SM'boumba Cedric Madianga * 417d8b46839SM'boumba Cedric Madianga * If (ch % 4) is 2 or 3, left shift the mask by 16 bits. 418d8b46839SM'boumba Cedric Madianga * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. 419d8b46839SM'boumba Cedric Madianga */ 4209df3bd55SPierre Yves MORDRET flags &= STM32_DMA_MASKI; 421d8b46839SM'boumba Cedric Madianga dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); 422d8b46839SM'boumba Cedric Madianga 423d8b46839SM'boumba Cedric Madianga if (chan->id & 4) 424d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_HIFCR, dma_ifcr); 425d8b46839SM'boumba Cedric Madianga else 426d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_LIFCR, dma_ifcr); 427d8b46839SM'boumba Cedric Madianga } 428d8b46839SM'boumba Cedric Madianga 429d8b46839SM'boumba Cedric Madianga static int stm32_dma_disable_chan(struct stm32_dma_chan *chan) 430d8b46839SM'boumba Cedric Madianga { 431d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 432d8b46839SM'boumba Cedric Madianga unsigned long timeout = jiffies + msecs_to_jiffies(5000); 433d8b46839SM'boumba Cedric Madianga u32 dma_scr, id; 434d8b46839SM'boumba Cedric Madianga 435d8b46839SM'boumba Cedric Madianga id = chan->id; 436d8b46839SM'boumba Cedric Madianga dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); 437d8b46839SM'boumba Cedric Madianga 438d8b46839SM'boumba Cedric Madianga if (dma_scr & STM32_DMA_SCR_EN) { 439d8b46839SM'boumba Cedric Madianga dma_scr &= ~STM32_DMA_SCR_EN; 440d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SCR(id), dma_scr); 441d8b46839SM'boumba Cedric Madianga 442d8b46839SM'boumba Cedric Madianga do { 443d8b46839SM'boumba Cedric Madianga dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); 444d8b46839SM'boumba Cedric Madianga dma_scr &= STM32_DMA_SCR_EN; 445d8b46839SM'boumba Cedric Madianga if (!dma_scr) 446d8b46839SM'boumba Cedric Madianga break; 447d8b46839SM'boumba Cedric Madianga 448d8b46839SM'boumba Cedric Madianga if (time_after_eq(jiffies, timeout)) { 449d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "%s: timeout!\n", 450d8b46839SM'boumba Cedric Madianga __func__); 451d8b46839SM'boumba Cedric Madianga return -EBUSY; 452d8b46839SM'boumba Cedric Madianga } 453d8b46839SM'boumba Cedric Madianga cond_resched(); 454d8b46839SM'boumba Cedric Madianga } while (1); 455d8b46839SM'boumba Cedric Madianga } 456d8b46839SM'boumba Cedric Madianga 457d8b46839SM'boumba Cedric Madianga return 0; 458d8b46839SM'boumba Cedric Madianga } 459d8b46839SM'boumba Cedric Madianga 460d8b46839SM'boumba Cedric Madianga static void stm32_dma_stop(struct stm32_dma_chan *chan) 461d8b46839SM'boumba Cedric Madianga { 462d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 463d8b46839SM'boumba Cedric Madianga u32 dma_scr, dma_sfcr, status; 464d8b46839SM'boumba Cedric Madianga int ret; 465d8b46839SM'boumba Cedric Madianga 466d8b46839SM'boumba Cedric Madianga /* Disable interrupts */ 467d8b46839SM'boumba Cedric Madianga dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 468d8b46839SM'boumba Cedric Madianga dma_scr &= ~STM32_DMA_SCR_IRQ_MASK; 469d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); 470d8b46839SM'boumba Cedric Madianga dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); 471d8b46839SM'boumba Cedric Madianga dma_sfcr &= ~STM32_DMA_SFCR_FEIE; 472d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr); 473d8b46839SM'boumba Cedric Madianga 474d8b46839SM'boumba Cedric Madianga /* Disable DMA */ 475d8b46839SM'boumba Cedric Madianga ret = stm32_dma_disable_chan(chan); 476d8b46839SM'boumba Cedric Madianga if (ret < 0) 477d8b46839SM'boumba Cedric Madianga return; 478d8b46839SM'boumba Cedric Madianga 479d8b46839SM'boumba Cedric Madianga /* Clear interrupt status if it is there */ 480d8b46839SM'boumba Cedric Madianga status = stm32_dma_irq_status(chan); 481d8b46839SM'boumba Cedric Madianga if (status) { 482d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n", 483d8b46839SM'boumba Cedric Madianga __func__, status); 484d8b46839SM'boumba Cedric Madianga stm32_dma_irq_clear(chan, status); 485d8b46839SM'boumba Cedric Madianga } 486d8b46839SM'boumba Cedric Madianga 487d8b46839SM'boumba Cedric Madianga chan->busy = false; 488d8b46839SM'boumba Cedric Madianga } 489d8b46839SM'boumba Cedric Madianga 490d8b46839SM'boumba Cedric Madianga static int stm32_dma_terminate_all(struct dma_chan *c) 491d8b46839SM'boumba Cedric Madianga { 492d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 493d8b46839SM'boumba Cedric Madianga unsigned long flags; 494d8b46839SM'boumba Cedric Madianga LIST_HEAD(head); 495d8b46839SM'boumba Cedric Madianga 496d8b46839SM'boumba Cedric Madianga spin_lock_irqsave(&chan->vchan.lock, flags); 497d8b46839SM'boumba Cedric Madianga 498d8b46839SM'boumba Cedric Madianga if (chan->busy) { 499d8b46839SM'boumba Cedric Madianga stm32_dma_stop(chan); 500d8b46839SM'boumba Cedric Madianga chan->desc = NULL; 501d8b46839SM'boumba Cedric Madianga } 502d8b46839SM'boumba Cedric Madianga 503d8b46839SM'boumba Cedric Madianga vchan_get_all_descriptors(&chan->vchan, &head); 504d8b46839SM'boumba Cedric Madianga spin_unlock_irqrestore(&chan->vchan.lock, flags); 505d8b46839SM'boumba Cedric Madianga vchan_dma_desc_free_list(&chan->vchan, &head); 506d8b46839SM'boumba Cedric Madianga 507d8b46839SM'boumba Cedric Madianga return 0; 508d8b46839SM'boumba Cedric Madianga } 509d8b46839SM'boumba Cedric Madianga 510dc808675SM'boumba Cedric Madianga static void stm32_dma_synchronize(struct dma_chan *c) 511dc808675SM'boumba Cedric Madianga { 512dc808675SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 513dc808675SM'boumba Cedric Madianga 514dc808675SM'boumba Cedric Madianga vchan_synchronize(&chan->vchan); 515dc808675SM'boumba Cedric Madianga } 516dc808675SM'boumba Cedric Madianga 517d8b46839SM'boumba Cedric Madianga static void stm32_dma_dump_reg(struct stm32_dma_chan *chan) 518d8b46839SM'boumba Cedric Madianga { 519d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 520d8b46839SM'boumba Cedric Madianga u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 521d8b46839SM'boumba Cedric Madianga u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); 522d8b46839SM'boumba Cedric Madianga u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id)); 523d8b46839SM'boumba Cedric Madianga u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id)); 524d8b46839SM'boumba Cedric Madianga u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id)); 525d8b46839SM'boumba Cedric Madianga u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); 526d8b46839SM'boumba Cedric Madianga 527d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SCR: 0x%08x\n", scr); 528d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "NDTR: 0x%08x\n", ndtr); 529d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SPAR: 0x%08x\n", spar); 530d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar); 531d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar); 532d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SFCR: 0x%08x\n", sfcr); 533d8b46839SM'boumba Cedric Madianga } 534d8b46839SM'boumba Cedric Madianga 535e57cb3b3SPierre Yves MORDRET static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan); 536e57cb3b3SPierre Yves MORDRET 5378d1b76f0SM'boumba Cedric Madianga static void stm32_dma_start_transfer(struct stm32_dma_chan *chan) 538d8b46839SM'boumba Cedric Madianga { 539d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 540d8b46839SM'boumba Cedric Madianga struct virt_dma_desc *vdesc; 541d8b46839SM'boumba Cedric Madianga struct stm32_dma_sg_req *sg_req; 542d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan_reg *reg; 543d8b46839SM'boumba Cedric Madianga u32 status; 544d8b46839SM'boumba Cedric Madianga int ret; 545d8b46839SM'boumba Cedric Madianga 546d8b46839SM'boumba Cedric Madianga ret = stm32_dma_disable_chan(chan); 547d8b46839SM'boumba Cedric Madianga if (ret < 0) 5488d1b76f0SM'boumba Cedric Madianga return; 549d8b46839SM'boumba Cedric Madianga 550d8b46839SM'boumba Cedric Madianga if (!chan->desc) { 551d8b46839SM'boumba Cedric Madianga vdesc = vchan_next_desc(&chan->vchan); 552d8b46839SM'boumba Cedric Madianga if (!vdesc) 5538d1b76f0SM'boumba Cedric Madianga return; 554d8b46839SM'boumba Cedric Madianga 555d8b46839SM'boumba Cedric Madianga chan->desc = to_stm32_dma_desc(vdesc); 556d8b46839SM'boumba Cedric Madianga chan->next_sg = 0; 557d8b46839SM'boumba Cedric Madianga } 558d8b46839SM'boumba Cedric Madianga 559d8b46839SM'boumba Cedric Madianga if (chan->next_sg == chan->desc->num_sgs) 560d8b46839SM'boumba Cedric Madianga chan->next_sg = 0; 561d8b46839SM'boumba Cedric Madianga 562d8b46839SM'boumba Cedric Madianga sg_req = &chan->desc->sg_req[chan->next_sg]; 563d8b46839SM'boumba Cedric Madianga reg = &sg_req->chan_reg; 564d8b46839SM'boumba Cedric Madianga 565d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); 566d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar); 567d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar); 568d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr); 569d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar); 570d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr); 571d8b46839SM'boumba Cedric Madianga 572d8b46839SM'boumba Cedric Madianga chan->next_sg++; 573d8b46839SM'boumba Cedric Madianga 574d8b46839SM'boumba Cedric Madianga /* Clear interrupt status if it is there */ 575d8b46839SM'boumba Cedric Madianga status = stm32_dma_irq_status(chan); 576d8b46839SM'boumba Cedric Madianga if (status) 577d8b46839SM'boumba Cedric Madianga stm32_dma_irq_clear(chan, status); 578d8b46839SM'boumba Cedric Madianga 579e57cb3b3SPierre Yves MORDRET if (chan->desc->cyclic) 580e57cb3b3SPierre Yves MORDRET stm32_dma_configure_next_sg(chan); 581e57cb3b3SPierre Yves MORDRET 582d8b46839SM'boumba Cedric Madianga stm32_dma_dump_reg(chan); 583d8b46839SM'boumba Cedric Madianga 584d8b46839SM'boumba Cedric Madianga /* Start DMA */ 585d8b46839SM'boumba Cedric Madianga reg->dma_scr |= STM32_DMA_SCR_EN; 586d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); 587d8b46839SM'boumba Cedric Madianga 588d8b46839SM'boumba Cedric Madianga chan->busy = true; 589d8b46839SM'boumba Cedric Madianga 59090ec93cbSBenjamin Gaignard dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan); 591d8b46839SM'boumba Cedric Madianga } 592d8b46839SM'boumba Cedric Madianga 593d8b46839SM'boumba Cedric Madianga static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan) 594d8b46839SM'boumba Cedric Madianga { 595d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 596d8b46839SM'boumba Cedric Madianga struct stm32_dma_sg_req *sg_req; 597d8b46839SM'boumba Cedric Madianga u32 dma_scr, dma_sm0ar, dma_sm1ar, id; 598d8b46839SM'boumba Cedric Madianga 599d8b46839SM'boumba Cedric Madianga id = chan->id; 600d8b46839SM'boumba Cedric Madianga dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); 601d8b46839SM'boumba Cedric Madianga 602d8b46839SM'boumba Cedric Madianga if (dma_scr & STM32_DMA_SCR_DBM) { 603d8b46839SM'boumba Cedric Madianga if (chan->next_sg == chan->desc->num_sgs) 604d8b46839SM'boumba Cedric Madianga chan->next_sg = 0; 605d8b46839SM'boumba Cedric Madianga 606d8b46839SM'boumba Cedric Madianga sg_req = &chan->desc->sg_req[chan->next_sg]; 607d8b46839SM'boumba Cedric Madianga 608d8b46839SM'boumba Cedric Madianga if (dma_scr & STM32_DMA_SCR_CT) { 609d8b46839SM'boumba Cedric Madianga dma_sm0ar = sg_req->chan_reg.dma_sm0ar; 610d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar); 611d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n", 612d8b46839SM'boumba Cedric Madianga stm32_dma_read(dmadev, STM32_DMA_SM0AR(id))); 613d8b46839SM'boumba Cedric Madianga } else { 614d8b46839SM'boumba Cedric Madianga dma_sm1ar = sg_req->chan_reg.dma_sm1ar; 615d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar); 616d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n", 617d8b46839SM'boumba Cedric Madianga stm32_dma_read(dmadev, STM32_DMA_SM1AR(id))); 618d8b46839SM'boumba Cedric Madianga } 619d8b46839SM'boumba Cedric Madianga } 620d8b46839SM'boumba Cedric Madianga } 621d8b46839SM'boumba Cedric Madianga 622d8b46839SM'boumba Cedric Madianga static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan) 623d8b46839SM'boumba Cedric Madianga { 624d8b46839SM'boumba Cedric Madianga if (chan->desc) { 625d8b46839SM'boumba Cedric Madianga if (chan->desc->cyclic) { 626d8b46839SM'boumba Cedric Madianga vchan_cyclic_callback(&chan->desc->vdesc); 6272b12c558SM'boumba Cedric Madianga chan->next_sg++; 628d8b46839SM'boumba Cedric Madianga stm32_dma_configure_next_sg(chan); 629d8b46839SM'boumba Cedric Madianga } else { 630d8b46839SM'boumba Cedric Madianga chan->busy = false; 631d8b46839SM'boumba Cedric Madianga if (chan->next_sg == chan->desc->num_sgs) { 632d8b46839SM'boumba Cedric Madianga list_del(&chan->desc->vdesc.node); 633d8b46839SM'boumba Cedric Madianga vchan_cookie_complete(&chan->desc->vdesc); 634d8b46839SM'boumba Cedric Madianga chan->desc = NULL; 635d8b46839SM'boumba Cedric Madianga } 636d8b46839SM'boumba Cedric Madianga stm32_dma_start_transfer(chan); 637d8b46839SM'boumba Cedric Madianga } 638d8b46839SM'boumba Cedric Madianga } 639d8b46839SM'boumba Cedric Madianga } 640d8b46839SM'boumba Cedric Madianga 641d8b46839SM'boumba Cedric Madianga static irqreturn_t stm32_dma_chan_irq(int irq, void *devid) 642d8b46839SM'boumba Cedric Madianga { 643d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = devid; 644d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 645ca4c72c0SPierre-Yves MORDRET u32 status, scr, sfcr; 646d8b46839SM'boumba Cedric Madianga 647d8b46839SM'boumba Cedric Madianga spin_lock(&chan->vchan.lock); 648d8b46839SM'boumba Cedric Madianga 649d8b46839SM'boumba Cedric Madianga status = stm32_dma_irq_status(chan); 650d8b46839SM'boumba Cedric Madianga scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 651ca4c72c0SPierre-Yves MORDRET sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); 652d8b46839SM'boumba Cedric Madianga 653c2d86b1cSPierre Yves MORDRET if (status & STM32_DMA_TCI) { 654d8b46839SM'boumba Cedric Madianga stm32_dma_irq_clear(chan, STM32_DMA_TCI); 655c2d86b1cSPierre Yves MORDRET if (scr & STM32_DMA_SCR_TCIE) 656d8b46839SM'boumba Cedric Madianga stm32_dma_handle_chan_done(chan); 657c2d86b1cSPierre Yves MORDRET status &= ~STM32_DMA_TCI; 658c2d86b1cSPierre Yves MORDRET } 659c2d86b1cSPierre Yves MORDRET if (status & STM32_DMA_HTI) { 660c2d86b1cSPierre Yves MORDRET stm32_dma_irq_clear(chan, STM32_DMA_HTI); 661c2d86b1cSPierre Yves MORDRET status &= ~STM32_DMA_HTI; 662c2d86b1cSPierre Yves MORDRET } 663c2d86b1cSPierre Yves MORDRET if (status & STM32_DMA_FEI) { 664c2d86b1cSPierre Yves MORDRET stm32_dma_irq_clear(chan, STM32_DMA_FEI); 665c2d86b1cSPierre Yves MORDRET status &= ~STM32_DMA_FEI; 666ca4c72c0SPierre-Yves MORDRET if (sfcr & STM32_DMA_SFCR_FEIE) { 667c2d86b1cSPierre Yves MORDRET if (!(scr & STM32_DMA_SCR_EN)) 668c2d86b1cSPierre Yves MORDRET dev_err(chan2dev(chan), "FIFO Error\n"); 669c2d86b1cSPierre Yves MORDRET else 670c2d86b1cSPierre Yves MORDRET dev_dbg(chan2dev(chan), "FIFO over/underrun\n"); 671c2d86b1cSPierre Yves MORDRET } 672ca4c72c0SPierre-Yves MORDRET } 673c2d86b1cSPierre Yves MORDRET if (status) { 674d8b46839SM'boumba Cedric Madianga stm32_dma_irq_clear(chan, status); 675d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status); 676c2d86b1cSPierre Yves MORDRET if (!(scr & STM32_DMA_SCR_EN)) 677c2d86b1cSPierre Yves MORDRET dev_err(chan2dev(chan), "chan disabled by HW\n"); 678d8b46839SM'boumba Cedric Madianga } 679d8b46839SM'boumba Cedric Madianga 680d8b46839SM'boumba Cedric Madianga spin_unlock(&chan->vchan.lock); 681d8b46839SM'boumba Cedric Madianga 682d8b46839SM'boumba Cedric Madianga return IRQ_HANDLED; 683d8b46839SM'boumba Cedric Madianga } 684d8b46839SM'boumba Cedric Madianga 685d8b46839SM'boumba Cedric Madianga static void stm32_dma_issue_pending(struct dma_chan *c) 686d8b46839SM'boumba Cedric Madianga { 687d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 688d8b46839SM'boumba Cedric Madianga unsigned long flags; 689d8b46839SM'boumba Cedric Madianga 690d8b46839SM'boumba Cedric Madianga spin_lock_irqsave(&chan->vchan.lock, flags); 6918d1b76f0SM'boumba Cedric Madianga if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) { 69290ec93cbSBenjamin Gaignard dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan); 6938d1b76f0SM'boumba Cedric Madianga stm32_dma_start_transfer(chan); 694e57cb3b3SPierre Yves MORDRET 695d8b46839SM'boumba Cedric Madianga } 696d8b46839SM'boumba Cedric Madianga spin_unlock_irqrestore(&chan->vchan.lock, flags); 697d8b46839SM'boumba Cedric Madianga } 698d8b46839SM'boumba Cedric Madianga 699d8b46839SM'boumba Cedric Madianga static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan, 700d8b46839SM'boumba Cedric Madianga enum dma_transfer_direction direction, 701a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth *buswidth, 702a2b6103bSPierre Yves MORDRET u32 buf_len) 703d8b46839SM'boumba Cedric Madianga { 704d8b46839SM'boumba Cedric Madianga enum dma_slave_buswidth src_addr_width, dst_addr_width; 705d8b46839SM'boumba Cedric Madianga int src_bus_width, dst_bus_width; 706d8b46839SM'boumba Cedric Madianga int src_burst_size, dst_burst_size; 707a2b6103bSPierre Yves MORDRET u32 src_maxburst, dst_maxburst, src_best_burst, dst_best_burst; 708a2b6103bSPierre Yves MORDRET u32 dma_scr, threshold; 709d8b46839SM'boumba Cedric Madianga 710d8b46839SM'boumba Cedric Madianga src_addr_width = chan->dma_sconfig.src_addr_width; 711d8b46839SM'boumba Cedric Madianga dst_addr_width = chan->dma_sconfig.dst_addr_width; 712d8b46839SM'boumba Cedric Madianga src_maxburst = chan->dma_sconfig.src_maxburst; 713d8b46839SM'boumba Cedric Madianga dst_maxburst = chan->dma_sconfig.dst_maxburst; 714a2b6103bSPierre Yves MORDRET threshold = chan->threshold; 715d8b46839SM'boumba Cedric Madianga 716d8b46839SM'boumba Cedric Madianga switch (direction) { 717d8b46839SM'boumba Cedric Madianga case DMA_MEM_TO_DEV: 718a2b6103bSPierre Yves MORDRET /* Set device data size */ 719d8b46839SM'boumba Cedric Madianga dst_bus_width = stm32_dma_get_width(chan, dst_addr_width); 720d8b46839SM'boumba Cedric Madianga if (dst_bus_width < 0) 721d8b46839SM'boumba Cedric Madianga return dst_bus_width; 722d8b46839SM'boumba Cedric Madianga 723a2b6103bSPierre Yves MORDRET /* Set device burst size */ 724a2b6103bSPierre Yves MORDRET dst_best_burst = stm32_dma_get_best_burst(buf_len, 725a2b6103bSPierre Yves MORDRET dst_maxburst, 726a2b6103bSPierre Yves MORDRET threshold, 727a2b6103bSPierre Yves MORDRET dst_addr_width); 728a2b6103bSPierre Yves MORDRET 729a2b6103bSPierre Yves MORDRET dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst); 730d8b46839SM'boumba Cedric Madianga if (dst_burst_size < 0) 731d8b46839SM'boumba Cedric Madianga return dst_burst_size; 732d8b46839SM'boumba Cedric Madianga 733a2b6103bSPierre Yves MORDRET /* Set memory data size */ 734a2b6103bSPierre Yves MORDRET src_addr_width = stm32_dma_get_max_width(buf_len, threshold); 735a2b6103bSPierre Yves MORDRET chan->mem_width = src_addr_width; 736d8b46839SM'boumba Cedric Madianga src_bus_width = stm32_dma_get_width(chan, src_addr_width); 737d8b46839SM'boumba Cedric Madianga if (src_bus_width < 0) 738d8b46839SM'boumba Cedric Madianga return src_bus_width; 739d8b46839SM'boumba Cedric Madianga 740a2b6103bSPierre Yves MORDRET /* Set memory burst size */ 741a2b6103bSPierre Yves MORDRET src_maxburst = STM32_DMA_MAX_BURST; 742a2b6103bSPierre Yves MORDRET src_best_burst = stm32_dma_get_best_burst(buf_len, 743a2b6103bSPierre Yves MORDRET src_maxburst, 744a2b6103bSPierre Yves MORDRET threshold, 745a2b6103bSPierre Yves MORDRET src_addr_width); 746a2b6103bSPierre Yves MORDRET src_burst_size = stm32_dma_get_burst(chan, src_best_burst); 747d8b46839SM'boumba Cedric Madianga if (src_burst_size < 0) 748d8b46839SM'boumba Cedric Madianga return src_burst_size; 749d8b46839SM'boumba Cedric Madianga 750d8b46839SM'boumba Cedric Madianga dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_DEV) | 751d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PSIZE(dst_bus_width) | 752d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MSIZE(src_bus_width) | 753d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PBURST(dst_burst_size) | 754d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MBURST(src_burst_size); 755d8b46839SM'boumba Cedric Madianga 756a2b6103bSPierre Yves MORDRET /* Set FIFO threshold */ 757a2b6103bSPierre Yves MORDRET chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; 758a2b6103bSPierre Yves MORDRET chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold); 759a2b6103bSPierre Yves MORDRET 760a2b6103bSPierre Yves MORDRET /* Set peripheral address */ 761d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr; 762d8b46839SM'boumba Cedric Madianga *buswidth = dst_addr_width; 763d8b46839SM'boumba Cedric Madianga break; 764d8b46839SM'boumba Cedric Madianga 765d8b46839SM'boumba Cedric Madianga case DMA_DEV_TO_MEM: 766a2b6103bSPierre Yves MORDRET /* Set device data size */ 767d8b46839SM'boumba Cedric Madianga src_bus_width = stm32_dma_get_width(chan, src_addr_width); 768d8b46839SM'boumba Cedric Madianga if (src_bus_width < 0) 769d8b46839SM'boumba Cedric Madianga return src_bus_width; 770d8b46839SM'boumba Cedric Madianga 771a2b6103bSPierre Yves MORDRET /* Set device burst size */ 772a2b6103bSPierre Yves MORDRET src_best_burst = stm32_dma_get_best_burst(buf_len, 773a2b6103bSPierre Yves MORDRET src_maxburst, 774a2b6103bSPierre Yves MORDRET threshold, 775a2b6103bSPierre Yves MORDRET src_addr_width); 776a2b6103bSPierre Yves MORDRET chan->mem_burst = src_best_burst; 777a2b6103bSPierre Yves MORDRET src_burst_size = stm32_dma_get_burst(chan, src_best_burst); 778d8b46839SM'boumba Cedric Madianga if (src_burst_size < 0) 779d8b46839SM'boumba Cedric Madianga return src_burst_size; 780d8b46839SM'boumba Cedric Madianga 781a2b6103bSPierre Yves MORDRET /* Set memory data size */ 782a2b6103bSPierre Yves MORDRET dst_addr_width = stm32_dma_get_max_width(buf_len, threshold); 783a2b6103bSPierre Yves MORDRET chan->mem_width = dst_addr_width; 784d8b46839SM'boumba Cedric Madianga dst_bus_width = stm32_dma_get_width(chan, dst_addr_width); 785d8b46839SM'boumba Cedric Madianga if (dst_bus_width < 0) 786d8b46839SM'boumba Cedric Madianga return dst_bus_width; 787d8b46839SM'boumba Cedric Madianga 788a2b6103bSPierre Yves MORDRET /* Set memory burst size */ 789a2b6103bSPierre Yves MORDRET dst_maxburst = STM32_DMA_MAX_BURST; 790a2b6103bSPierre Yves MORDRET dst_best_burst = stm32_dma_get_best_burst(buf_len, 791a2b6103bSPierre Yves MORDRET dst_maxburst, 792a2b6103bSPierre Yves MORDRET threshold, 793a2b6103bSPierre Yves MORDRET dst_addr_width); 794a2b6103bSPierre Yves MORDRET chan->mem_burst = dst_best_burst; 795a2b6103bSPierre Yves MORDRET dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst); 796d8b46839SM'boumba Cedric Madianga if (dst_burst_size < 0) 797d8b46839SM'boumba Cedric Madianga return dst_burst_size; 798d8b46839SM'boumba Cedric Madianga 799d8b46839SM'boumba Cedric Madianga dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_DEV_TO_MEM) | 800d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PSIZE(src_bus_width) | 801d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MSIZE(dst_bus_width) | 802d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PBURST(src_burst_size) | 803d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MBURST(dst_burst_size); 804d8b46839SM'boumba Cedric Madianga 805a2b6103bSPierre Yves MORDRET /* Set FIFO threshold */ 806a2b6103bSPierre Yves MORDRET chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; 807a2b6103bSPierre Yves MORDRET chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold); 808a2b6103bSPierre Yves MORDRET 809a2b6103bSPierre Yves MORDRET /* Set peripheral address */ 810d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr; 811d8b46839SM'boumba Cedric Madianga *buswidth = chan->dma_sconfig.src_addr_width; 812d8b46839SM'boumba Cedric Madianga break; 813d8b46839SM'boumba Cedric Madianga 814d8b46839SM'boumba Cedric Madianga default: 815d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Dma direction is not supported\n"); 816d8b46839SM'boumba Cedric Madianga return -EINVAL; 817d8b46839SM'boumba Cedric Madianga } 818d8b46839SM'boumba Cedric Madianga 819a2b6103bSPierre Yves MORDRET stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst); 820d8b46839SM'boumba Cedric Madianga 821a2b6103bSPierre Yves MORDRET /* Set DMA control register */ 822d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK | 823d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PSIZE_MASK | STM32_DMA_SCR_MSIZE_MASK | 824d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PBURST_MASK | STM32_DMA_SCR_MBURST_MASK); 825d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= dma_scr; 826d8b46839SM'boumba Cedric Madianga 827d8b46839SM'boumba Cedric Madianga return 0; 828d8b46839SM'boumba Cedric Madianga } 829d8b46839SM'boumba Cedric Madianga 830d8b46839SM'boumba Cedric Madianga static void stm32_dma_clear_reg(struct stm32_dma_chan_reg *regs) 831d8b46839SM'boumba Cedric Madianga { 832d8b46839SM'boumba Cedric Madianga memset(regs, 0, sizeof(struct stm32_dma_chan_reg)); 833d8b46839SM'boumba Cedric Madianga } 834d8b46839SM'boumba Cedric Madianga 835d8b46839SM'boumba Cedric Madianga static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg( 836d8b46839SM'boumba Cedric Madianga struct dma_chan *c, struct scatterlist *sgl, 837d8b46839SM'boumba Cedric Madianga u32 sg_len, enum dma_transfer_direction direction, 838d8b46839SM'boumba Cedric Madianga unsigned long flags, void *context) 839d8b46839SM'boumba Cedric Madianga { 840d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 841d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc; 842d8b46839SM'boumba Cedric Madianga struct scatterlist *sg; 843d8b46839SM'boumba Cedric Madianga enum dma_slave_buswidth buswidth; 844d8b46839SM'boumba Cedric Madianga u32 nb_data_items; 845d8b46839SM'boumba Cedric Madianga int i, ret; 846d8b46839SM'boumba Cedric Madianga 847d8b46839SM'boumba Cedric Madianga if (!chan->config_init) { 848d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "dma channel is not configured\n"); 849d8b46839SM'boumba Cedric Madianga return NULL; 850d8b46839SM'boumba Cedric Madianga } 851d8b46839SM'boumba Cedric Madianga 852d8b46839SM'boumba Cedric Madianga if (sg_len < 1) { 853d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len); 854d8b46839SM'boumba Cedric Madianga return NULL; 855d8b46839SM'boumba Cedric Madianga } 856d8b46839SM'boumba Cedric Madianga 857d8b46839SM'boumba Cedric Madianga desc = stm32_dma_alloc_desc(sg_len); 858d8b46839SM'boumba Cedric Madianga if (!desc) 859d8b46839SM'boumba Cedric Madianga return NULL; 860d8b46839SM'boumba Cedric Madianga 861d8b46839SM'boumba Cedric Madianga /* Set peripheral flow controller */ 862d8b46839SM'boumba Cedric Madianga if (chan->dma_sconfig.device_fc) 863d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL; 864d8b46839SM'boumba Cedric Madianga else 865d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; 866d8b46839SM'boumba Cedric Madianga 867d8b46839SM'boumba Cedric Madianga for_each_sg(sgl, sg, sg_len, i) { 868a2b6103bSPierre Yves MORDRET ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, 869a2b6103bSPierre Yves MORDRET sg_dma_len(sg)); 870a2b6103bSPierre Yves MORDRET if (ret < 0) 871a2b6103bSPierre Yves MORDRET goto err; 872a2b6103bSPierre Yves MORDRET 873d8b46839SM'boumba Cedric Madianga desc->sg_req[i].len = sg_dma_len(sg); 874d8b46839SM'boumba Cedric Madianga 875d8b46839SM'boumba Cedric Madianga nb_data_items = desc->sg_req[i].len / buswidth; 87680a76952SPierre Yves MORDRET if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) { 877d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "nb items not supported\n"); 878d8b46839SM'boumba Cedric Madianga goto err; 879d8b46839SM'boumba Cedric Madianga } 880d8b46839SM'boumba Cedric Madianga 881d8b46839SM'boumba Cedric Madianga stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); 882d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; 883d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; 884d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; 885d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg); 886d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg); 887d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items; 888d8b46839SM'boumba Cedric Madianga } 889d8b46839SM'boumba Cedric Madianga 890d8b46839SM'boumba Cedric Madianga desc->num_sgs = sg_len; 891d8b46839SM'boumba Cedric Madianga desc->cyclic = false; 892d8b46839SM'boumba Cedric Madianga 893d8b46839SM'boumba Cedric Madianga return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); 894d8b46839SM'boumba Cedric Madianga 895d8b46839SM'boumba Cedric Madianga err: 896d8b46839SM'boumba Cedric Madianga kfree(desc); 897d8b46839SM'boumba Cedric Madianga return NULL; 898d8b46839SM'boumba Cedric Madianga } 899d8b46839SM'boumba Cedric Madianga 900d8b46839SM'boumba Cedric Madianga static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic( 901d8b46839SM'boumba Cedric Madianga struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len, 902d8b46839SM'boumba Cedric Madianga size_t period_len, enum dma_transfer_direction direction, 903d8b46839SM'boumba Cedric Madianga unsigned long flags) 904d8b46839SM'boumba Cedric Madianga { 905d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 906d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc; 907d8b46839SM'boumba Cedric Madianga enum dma_slave_buswidth buswidth; 908d8b46839SM'boumba Cedric Madianga u32 num_periods, nb_data_items; 909d8b46839SM'boumba Cedric Madianga int i, ret; 910d8b46839SM'boumba Cedric Madianga 911d8b46839SM'boumba Cedric Madianga if (!buf_len || !period_len) { 912d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Invalid buffer/period len\n"); 913d8b46839SM'boumba Cedric Madianga return NULL; 914d8b46839SM'boumba Cedric Madianga } 915d8b46839SM'boumba Cedric Madianga 916d8b46839SM'boumba Cedric Madianga if (!chan->config_init) { 917d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "dma channel is not configured\n"); 918d8b46839SM'boumba Cedric Madianga return NULL; 919d8b46839SM'boumba Cedric Madianga } 920d8b46839SM'boumba Cedric Madianga 921d8b46839SM'boumba Cedric Madianga if (buf_len % period_len) { 922d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "buf_len not multiple of period_len\n"); 923d8b46839SM'boumba Cedric Madianga return NULL; 924d8b46839SM'boumba Cedric Madianga } 925d8b46839SM'boumba Cedric Madianga 926d8b46839SM'boumba Cedric Madianga /* 927d8b46839SM'boumba Cedric Madianga * We allow to take more number of requests till DMA is 928d8b46839SM'boumba Cedric Madianga * not started. The driver will loop over all requests. 929d8b46839SM'boumba Cedric Madianga * Once DMA is started then new requests can be queued only after 930d8b46839SM'boumba Cedric Madianga * terminating the DMA. 931d8b46839SM'boumba Cedric Madianga */ 932d8b46839SM'boumba Cedric Madianga if (chan->busy) { 933d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Request not allowed when dma busy\n"); 934d8b46839SM'boumba Cedric Madianga return NULL; 935d8b46839SM'boumba Cedric Madianga } 936d8b46839SM'boumba Cedric Madianga 937a2b6103bSPierre Yves MORDRET ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len); 938d8b46839SM'boumba Cedric Madianga if (ret < 0) 939d8b46839SM'boumba Cedric Madianga return NULL; 940d8b46839SM'boumba Cedric Madianga 941d8b46839SM'boumba Cedric Madianga nb_data_items = period_len / buswidth; 94280a76952SPierre Yves MORDRET if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) { 943d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "number of items not supported\n"); 944d8b46839SM'boumba Cedric Madianga return NULL; 945d8b46839SM'boumba Cedric Madianga } 946d8b46839SM'boumba Cedric Madianga 947d8b46839SM'boumba Cedric Madianga /* Enable Circular mode or double buffer mode */ 948d8b46839SM'boumba Cedric Madianga if (buf_len == period_len) 949d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC; 950d8b46839SM'boumba Cedric Madianga else 951d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM; 952d8b46839SM'boumba Cedric Madianga 953d8b46839SM'boumba Cedric Madianga /* Clear periph ctrl if client set it */ 954d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; 955d8b46839SM'boumba Cedric Madianga 956d8b46839SM'boumba Cedric Madianga num_periods = buf_len / period_len; 957d8b46839SM'boumba Cedric Madianga 958d8b46839SM'boumba Cedric Madianga desc = stm32_dma_alloc_desc(num_periods); 959d8b46839SM'boumba Cedric Madianga if (!desc) 960d8b46839SM'boumba Cedric Madianga return NULL; 961d8b46839SM'boumba Cedric Madianga 962d8b46839SM'boumba Cedric Madianga for (i = 0; i < num_periods; i++) { 963d8b46839SM'boumba Cedric Madianga desc->sg_req[i].len = period_len; 964d8b46839SM'boumba Cedric Madianga 965d8b46839SM'boumba Cedric Madianga stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); 966d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; 967d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; 968d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; 969d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr; 970d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr; 971d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items; 972d8b46839SM'boumba Cedric Madianga buf_addr += period_len; 973d8b46839SM'boumba Cedric Madianga } 974d8b46839SM'boumba Cedric Madianga 975d8b46839SM'boumba Cedric Madianga desc->num_sgs = num_periods; 976d8b46839SM'boumba Cedric Madianga desc->cyclic = true; 977d8b46839SM'boumba Cedric Madianga 978d8b46839SM'boumba Cedric Madianga return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); 979d8b46839SM'boumba Cedric Madianga } 980d8b46839SM'boumba Cedric Madianga 981d8b46839SM'boumba Cedric Madianga static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy( 982d8b46839SM'boumba Cedric Madianga struct dma_chan *c, dma_addr_t dest, 983d8b46839SM'boumba Cedric Madianga dma_addr_t src, size_t len, unsigned long flags) 984d8b46839SM'boumba Cedric Madianga { 985d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 986a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth max_width; 987d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc; 988d8b46839SM'boumba Cedric Madianga size_t xfer_count, offset; 989a2b6103bSPierre Yves MORDRET u32 num_sgs, best_burst, dma_burst, threshold; 990d8b46839SM'boumba Cedric Madianga int i; 991d8b46839SM'boumba Cedric Madianga 99280a76952SPierre Yves MORDRET num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS); 993d8b46839SM'boumba Cedric Madianga desc = stm32_dma_alloc_desc(num_sgs); 994d8b46839SM'boumba Cedric Madianga if (!desc) 995d8b46839SM'boumba Cedric Madianga return NULL; 996d8b46839SM'boumba Cedric Madianga 997a2b6103bSPierre Yves MORDRET threshold = chan->threshold; 998a2b6103bSPierre Yves MORDRET 999d8b46839SM'boumba Cedric Madianga for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) { 1000d8b46839SM'boumba Cedric Madianga xfer_count = min_t(size_t, len - offset, 100180a76952SPierre Yves MORDRET STM32_DMA_ALIGNED_MAX_DATA_ITEMS); 1002d8b46839SM'boumba Cedric Madianga 1003a2b6103bSPierre Yves MORDRET /* Compute best burst size */ 1004a2b6103bSPierre Yves MORDRET max_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1005a2b6103bSPierre Yves MORDRET best_burst = stm32_dma_get_best_burst(len, STM32_DMA_MAX_BURST, 1006a2b6103bSPierre Yves MORDRET threshold, max_width); 1007a2b6103bSPierre Yves MORDRET dma_burst = stm32_dma_get_burst(chan, best_burst); 1008d8b46839SM'boumba Cedric Madianga 1009d8b46839SM'boumba Cedric Madianga stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); 1010d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_scr = 1011d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_MEM) | 1012a2b6103bSPierre Yves MORDRET STM32_DMA_SCR_PBURST(dma_burst) | 1013a2b6103bSPierre Yves MORDRET STM32_DMA_SCR_MBURST(dma_burst) | 1014d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MINC | 1015d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PINC | 1016d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_TCIE | 1017d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_TEIE; 1018a2b6103bSPierre Yves MORDRET desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; 1019a2b6103bSPierre Yves MORDRET desc->sg_req[i].chan_reg.dma_sfcr |= 1020a2b6103bSPierre Yves MORDRET STM32_DMA_SFCR_FTH(threshold); 1021d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_spar = src + offset; 1022d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset; 1023d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sndtr = xfer_count; 1024a2b6103bSPierre Yves MORDRET desc->sg_req[i].len = xfer_count; 1025d8b46839SM'boumba Cedric Madianga } 1026d8b46839SM'boumba Cedric Madianga 1027d8b46839SM'boumba Cedric Madianga desc->num_sgs = num_sgs; 1028d8b46839SM'boumba Cedric Madianga desc->cyclic = false; 1029d8b46839SM'boumba Cedric Madianga 1030d8b46839SM'boumba Cedric Madianga return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); 1031d8b46839SM'boumba Cedric Madianga } 1032d8b46839SM'boumba Cedric Madianga 10332b12c558SM'boumba Cedric Madianga static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan) 10342b12c558SM'boumba Cedric Madianga { 10352b12c558SM'boumba Cedric Madianga u32 dma_scr, width, ndtr; 10362b12c558SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 10372b12c558SM'boumba Cedric Madianga 10382b12c558SM'boumba Cedric Madianga dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 10392b12c558SM'boumba Cedric Madianga width = STM32_DMA_SCR_PSIZE_GET(dma_scr); 10402b12c558SM'boumba Cedric Madianga ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); 10412b12c558SM'boumba Cedric Madianga 10422b12c558SM'boumba Cedric Madianga return ndtr << width; 10432b12c558SM'boumba Cedric Madianga } 10442b12c558SM'boumba Cedric Madianga 1045d8b46839SM'boumba Cedric Madianga static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan, 1046d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc, 1047d8b46839SM'boumba Cedric Madianga u32 next_sg) 1048d8b46839SM'boumba Cedric Madianga { 1049a2b6103bSPierre Yves MORDRET u32 modulo, burst_size; 10502b12c558SM'boumba Cedric Madianga u32 residue = 0; 1051d8b46839SM'boumba Cedric Madianga int i; 1052d8b46839SM'boumba Cedric Madianga 10532b12c558SM'boumba Cedric Madianga /* 10542b12c558SM'boumba Cedric Madianga * In cyclic mode, for the last period, residue = remaining bytes from 10552b12c558SM'boumba Cedric Madianga * NDTR 10562b12c558SM'boumba Cedric Madianga */ 1057a2b6103bSPierre Yves MORDRET if (chan->desc->cyclic && next_sg == 0) { 1058a2b6103bSPierre Yves MORDRET residue = stm32_dma_get_remaining_bytes(chan); 1059a2b6103bSPierre Yves MORDRET goto end; 1060a2b6103bSPierre Yves MORDRET } 1061d8b46839SM'boumba Cedric Madianga 10622b12c558SM'boumba Cedric Madianga /* 10632b12c558SM'boumba Cedric Madianga * For all other periods in cyclic mode, and in sg mode, 10642b12c558SM'boumba Cedric Madianga * residue = remaining bytes from NDTR + remaining periods/sg to be 10652b12c558SM'boumba Cedric Madianga * transferred 10662b12c558SM'boumba Cedric Madianga */ 1067d8b46839SM'boumba Cedric Madianga for (i = next_sg; i < desc->num_sgs; i++) 1068d8b46839SM'boumba Cedric Madianga residue += desc->sg_req[i].len; 10692b12c558SM'boumba Cedric Madianga residue += stm32_dma_get_remaining_bytes(chan); 1070d8b46839SM'boumba Cedric Madianga 1071a2b6103bSPierre Yves MORDRET end: 1072a2b6103bSPierre Yves MORDRET if (!chan->mem_burst) 1073a2b6103bSPierre Yves MORDRET return residue; 1074a2b6103bSPierre Yves MORDRET 1075a2b6103bSPierre Yves MORDRET burst_size = chan->mem_burst * chan->mem_width; 1076a2b6103bSPierre Yves MORDRET modulo = residue % burst_size; 1077a2b6103bSPierre Yves MORDRET if (modulo) 1078a2b6103bSPierre Yves MORDRET residue = residue - modulo + burst_size; 1079a2b6103bSPierre Yves MORDRET 1080d8b46839SM'boumba Cedric Madianga return residue; 1081d8b46839SM'boumba Cedric Madianga } 1082d8b46839SM'boumba Cedric Madianga 1083d8b46839SM'boumba Cedric Madianga static enum dma_status stm32_dma_tx_status(struct dma_chan *c, 1084d8b46839SM'boumba Cedric Madianga dma_cookie_t cookie, 1085d8b46839SM'boumba Cedric Madianga struct dma_tx_state *state) 1086d8b46839SM'boumba Cedric Madianga { 1087d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1088d8b46839SM'boumba Cedric Madianga struct virt_dma_desc *vdesc; 1089d8b46839SM'boumba Cedric Madianga enum dma_status status; 1090d8b46839SM'boumba Cedric Madianga unsigned long flags; 109157b5a321SM'boumba Cedric Madianga u32 residue = 0; 1092d8b46839SM'boumba Cedric Madianga 1093d8b46839SM'boumba Cedric Madianga status = dma_cookie_status(c, cookie, state); 1094249d5531SPierre Yves MORDRET if (status == DMA_COMPLETE || !state) 1095d8b46839SM'boumba Cedric Madianga return status; 1096d8b46839SM'boumba Cedric Madianga 1097d8b46839SM'boumba Cedric Madianga spin_lock_irqsave(&chan->vchan.lock, flags); 1098d8b46839SM'boumba Cedric Madianga vdesc = vchan_find_desc(&chan->vchan, cookie); 109957b5a321SM'boumba Cedric Madianga if (chan->desc && cookie == chan->desc->vdesc.tx.cookie) 1100d8b46839SM'boumba Cedric Madianga residue = stm32_dma_desc_residue(chan, chan->desc, 1101d8b46839SM'boumba Cedric Madianga chan->next_sg); 110257b5a321SM'boumba Cedric Madianga else if (vdesc) 1103d8b46839SM'boumba Cedric Madianga residue = stm32_dma_desc_residue(chan, 1104d8b46839SM'boumba Cedric Madianga to_stm32_dma_desc(vdesc), 0); 1105d8b46839SM'boumba Cedric Madianga dma_set_residue(state, residue); 1106d8b46839SM'boumba Cedric Madianga 1107d8b46839SM'boumba Cedric Madianga spin_unlock_irqrestore(&chan->vchan.lock, flags); 1108d8b46839SM'boumba Cedric Madianga 1109d8b46839SM'boumba Cedric Madianga return status; 1110d8b46839SM'boumba Cedric Madianga } 1111d8b46839SM'boumba Cedric Madianga 1112d8b46839SM'boumba Cedric Madianga static int stm32_dma_alloc_chan_resources(struct dma_chan *c) 1113d8b46839SM'boumba Cedric Madianga { 1114d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1115d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 1116d8b46839SM'boumba Cedric Madianga int ret; 1117d8b46839SM'boumba Cedric Madianga 1118d8b46839SM'boumba Cedric Madianga chan->config_init = false; 111948bc73baSPierre-Yves MORDRET 112048bc73baSPierre-Yves MORDRET ret = pm_runtime_get_sync(dmadev->ddev.dev); 112148bc73baSPierre-Yves MORDRET if (ret < 0) 1122d8b46839SM'boumba Cedric Madianga return ret; 1123d8b46839SM'boumba Cedric Madianga 1124d8b46839SM'boumba Cedric Madianga ret = stm32_dma_disable_chan(chan); 1125d8b46839SM'boumba Cedric Madianga if (ret < 0) 112648bc73baSPierre-Yves MORDRET pm_runtime_put(dmadev->ddev.dev); 1127d8b46839SM'boumba Cedric Madianga 1128d8b46839SM'boumba Cedric Madianga return ret; 1129d8b46839SM'boumba Cedric Madianga } 1130d8b46839SM'boumba Cedric Madianga 1131d8b46839SM'boumba Cedric Madianga static void stm32_dma_free_chan_resources(struct dma_chan *c) 1132d8b46839SM'boumba Cedric Madianga { 1133d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1134d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 1135d8b46839SM'boumba Cedric Madianga unsigned long flags; 1136d8b46839SM'boumba Cedric Madianga 1137d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id); 1138d8b46839SM'boumba Cedric Madianga 1139d8b46839SM'boumba Cedric Madianga if (chan->busy) { 1140d8b46839SM'boumba Cedric Madianga spin_lock_irqsave(&chan->vchan.lock, flags); 1141d8b46839SM'boumba Cedric Madianga stm32_dma_stop(chan); 1142d8b46839SM'boumba Cedric Madianga chan->desc = NULL; 1143d8b46839SM'boumba Cedric Madianga spin_unlock_irqrestore(&chan->vchan.lock, flags); 1144d8b46839SM'boumba Cedric Madianga } 1145d8b46839SM'boumba Cedric Madianga 114648bc73baSPierre-Yves MORDRET pm_runtime_put(dmadev->ddev.dev); 1147d8b46839SM'boumba Cedric Madianga 1148d8b46839SM'boumba Cedric Madianga vchan_free_chan_resources(to_virt_chan(c)); 1149d8b46839SM'boumba Cedric Madianga } 1150d8b46839SM'boumba Cedric Madianga 1151d8b46839SM'boumba Cedric Madianga static void stm32_dma_desc_free(struct virt_dma_desc *vdesc) 1152d8b46839SM'boumba Cedric Madianga { 1153d8b46839SM'boumba Cedric Madianga kfree(container_of(vdesc, struct stm32_dma_desc, vdesc)); 1154d8b46839SM'boumba Cedric Madianga } 1155d8b46839SM'boumba Cedric Madianga 1156e97adb49SVinod Koul static void stm32_dma_set_config(struct stm32_dma_chan *chan, 1157d8b46839SM'boumba Cedric Madianga struct stm32_dma_cfg *cfg) 1158d8b46839SM'boumba Cedric Madianga { 1159d8b46839SM'boumba Cedric Madianga stm32_dma_clear_reg(&chan->chan_reg); 1160d8b46839SM'boumba Cedric Madianga 1161d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK; 1162d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line); 1163d8b46839SM'boumba Cedric Madianga 1164d8b46839SM'boumba Cedric Madianga /* Enable Interrupts */ 1165d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE; 1166d8b46839SM'boumba Cedric Madianga 1167951f44cbSPierre Yves MORDRET chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features); 1168d8b46839SM'boumba Cedric Madianga } 1169d8b46839SM'boumba Cedric Madianga 1170d8b46839SM'boumba Cedric Madianga static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec, 1171d8b46839SM'boumba Cedric Madianga struct of_dma *ofdma) 1172d8b46839SM'boumba Cedric Madianga { 1173d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = ofdma->of_dma_data; 11745df4eb45SM'boumba Cedric Madianga struct device *dev = dmadev->ddev.dev; 1175d8b46839SM'boumba Cedric Madianga struct stm32_dma_cfg cfg; 1176d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan; 1177d8b46839SM'boumba Cedric Madianga struct dma_chan *c; 1178d8b46839SM'boumba Cedric Madianga 11795df4eb45SM'boumba Cedric Madianga if (dma_spec->args_count < 4) { 11805df4eb45SM'boumba Cedric Madianga dev_err(dev, "Bad number of cells\n"); 1181d8b46839SM'boumba Cedric Madianga return NULL; 11825df4eb45SM'boumba Cedric Madianga } 1183d8b46839SM'boumba Cedric Madianga 1184d8b46839SM'boumba Cedric Madianga cfg.channel_id = dma_spec->args[0]; 1185d8b46839SM'boumba Cedric Madianga cfg.request_line = dma_spec->args[1]; 1186d8b46839SM'boumba Cedric Madianga cfg.stream_config = dma_spec->args[2]; 1187951f44cbSPierre Yves MORDRET cfg.features = dma_spec->args[3]; 1188d8b46839SM'boumba Cedric Madianga 1189249d5531SPierre Yves MORDRET if (cfg.channel_id >= STM32_DMA_MAX_CHANNELS || 1190249d5531SPierre Yves MORDRET cfg.request_line >= STM32_DMA_MAX_REQUEST_ID) { 11915df4eb45SM'boumba Cedric Madianga dev_err(dev, "Bad channel and/or request id\n"); 1192d8b46839SM'boumba Cedric Madianga return NULL; 11935df4eb45SM'boumba Cedric Madianga } 1194d8b46839SM'boumba Cedric Madianga 1195d8b46839SM'boumba Cedric Madianga chan = &dmadev->chan[cfg.channel_id]; 1196d8b46839SM'boumba Cedric Madianga 1197d8b46839SM'boumba Cedric Madianga c = dma_get_slave_channel(&chan->vchan.chan); 11985df4eb45SM'boumba Cedric Madianga if (!c) { 1199041cf7e0SColin Ian King dev_err(dev, "No more channels available\n"); 12005df4eb45SM'boumba Cedric Madianga return NULL; 12015df4eb45SM'boumba Cedric Madianga } 12025df4eb45SM'boumba Cedric Madianga 1203d8b46839SM'boumba Cedric Madianga stm32_dma_set_config(chan, &cfg); 1204d8b46839SM'boumba Cedric Madianga 1205d8b46839SM'boumba Cedric Madianga return c; 1206d8b46839SM'boumba Cedric Madianga } 1207d8b46839SM'boumba Cedric Madianga 1208d8b46839SM'boumba Cedric Madianga static const struct of_device_id stm32_dma_of_match[] = { 1209d8b46839SM'boumba Cedric Madianga { .compatible = "st,stm32-dma", }, 1210d8b46839SM'boumba Cedric Madianga { /* sentinel */ }, 1211d8b46839SM'boumba Cedric Madianga }; 1212d8b46839SM'boumba Cedric Madianga MODULE_DEVICE_TABLE(of, stm32_dma_of_match); 1213d8b46839SM'boumba Cedric Madianga 1214d8b46839SM'boumba Cedric Madianga static int stm32_dma_probe(struct platform_device *pdev) 1215d8b46839SM'boumba Cedric Madianga { 1216d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan; 1217d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev; 1218d8b46839SM'boumba Cedric Madianga struct dma_device *dd; 1219d8b46839SM'boumba Cedric Madianga const struct of_device_id *match; 1220d8b46839SM'boumba Cedric Madianga struct resource *res; 1221d8b46839SM'boumba Cedric Madianga int i, ret; 1222d8b46839SM'boumba Cedric Madianga 1223d8b46839SM'boumba Cedric Madianga match = of_match_device(stm32_dma_of_match, &pdev->dev); 1224d8b46839SM'boumba Cedric Madianga if (!match) { 1225d8b46839SM'boumba Cedric Madianga dev_err(&pdev->dev, "Error: No device match found\n"); 1226d8b46839SM'boumba Cedric Madianga return -ENODEV; 1227d8b46839SM'boumba Cedric Madianga } 1228d8b46839SM'boumba Cedric Madianga 1229d8b46839SM'boumba Cedric Madianga dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL); 1230d8b46839SM'boumba Cedric Madianga if (!dmadev) 1231d8b46839SM'boumba Cedric Madianga return -ENOMEM; 1232d8b46839SM'boumba Cedric Madianga 1233d8b46839SM'boumba Cedric Madianga dd = &dmadev->ddev; 1234d8b46839SM'boumba Cedric Madianga 1235d8b46839SM'boumba Cedric Madianga res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1236d8b46839SM'boumba Cedric Madianga dmadev->base = devm_ioremap_resource(&pdev->dev, res); 1237d8b46839SM'boumba Cedric Madianga if (IS_ERR(dmadev->base)) 1238d8b46839SM'boumba Cedric Madianga return PTR_ERR(dmadev->base); 1239d8b46839SM'boumba Cedric Madianga 1240d8b46839SM'boumba Cedric Madianga dmadev->clk = devm_clk_get(&pdev->dev, NULL); 1241d8b46839SM'boumba Cedric Madianga if (IS_ERR(dmadev->clk)) { 1242d8b46839SM'boumba Cedric Madianga dev_err(&pdev->dev, "Error: Missing controller clock\n"); 1243d8b46839SM'boumba Cedric Madianga return PTR_ERR(dmadev->clk); 1244d8b46839SM'boumba Cedric Madianga } 1245d8b46839SM'boumba Cedric Madianga 124648bc73baSPierre-Yves MORDRET ret = clk_prepare_enable(dmadev->clk); 124748bc73baSPierre-Yves MORDRET if (ret < 0) { 124848bc73baSPierre-Yves MORDRET dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret); 124948bc73baSPierre-Yves MORDRET return ret; 125048bc73baSPierre-Yves MORDRET } 125148bc73baSPierre-Yves MORDRET 1252d8b46839SM'boumba Cedric Madianga dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node, 1253d8b46839SM'boumba Cedric Madianga "st,mem2mem"); 1254d8b46839SM'boumba Cedric Madianga 1255d8b46839SM'boumba Cedric Madianga dmadev->rst = devm_reset_control_get(&pdev->dev, NULL); 1256d8b46839SM'boumba Cedric Madianga if (!IS_ERR(dmadev->rst)) { 1257d8b46839SM'boumba Cedric Madianga reset_control_assert(dmadev->rst); 1258d8b46839SM'boumba Cedric Madianga udelay(2); 1259d8b46839SM'boumba Cedric Madianga reset_control_deassert(dmadev->rst); 1260d8b46839SM'boumba Cedric Madianga } 1261d8b46839SM'boumba Cedric Madianga 1262d8b46839SM'boumba Cedric Madianga dma_cap_set(DMA_SLAVE, dd->cap_mask); 1263d8b46839SM'boumba Cedric Madianga dma_cap_set(DMA_PRIVATE, dd->cap_mask); 1264d8b46839SM'boumba Cedric Madianga dma_cap_set(DMA_CYCLIC, dd->cap_mask); 1265d8b46839SM'boumba Cedric Madianga dd->device_alloc_chan_resources = stm32_dma_alloc_chan_resources; 1266d8b46839SM'boumba Cedric Madianga dd->device_free_chan_resources = stm32_dma_free_chan_resources; 1267d8b46839SM'boumba Cedric Madianga dd->device_tx_status = stm32_dma_tx_status; 1268d8b46839SM'boumba Cedric Madianga dd->device_issue_pending = stm32_dma_issue_pending; 1269d8b46839SM'boumba Cedric Madianga dd->device_prep_slave_sg = stm32_dma_prep_slave_sg; 1270d8b46839SM'boumba Cedric Madianga dd->device_prep_dma_cyclic = stm32_dma_prep_dma_cyclic; 1271d8b46839SM'boumba Cedric Madianga dd->device_config = stm32_dma_slave_config; 1272d8b46839SM'boumba Cedric Madianga dd->device_terminate_all = stm32_dma_terminate_all; 1273dc808675SM'boumba Cedric Madianga dd->device_synchronize = stm32_dma_synchronize; 1274d8b46839SM'boumba Cedric Madianga dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1275d8b46839SM'boumba Cedric Madianga BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1276d8b46839SM'boumba Cedric Madianga BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 1277d8b46839SM'boumba Cedric Madianga dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1278d8b46839SM'boumba Cedric Madianga BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1279d8b46839SM'boumba Cedric Madianga BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 1280d8b46839SM'boumba Cedric Madianga dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 1281d8b46839SM'boumba Cedric Madianga dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 1282276b0046SM'boumba Cedric Madianga dd->max_burst = STM32_DMA_MAX_BURST; 1283d8b46839SM'boumba Cedric Madianga dd->dev = &pdev->dev; 1284d8b46839SM'boumba Cedric Madianga INIT_LIST_HEAD(&dd->channels); 1285d8b46839SM'boumba Cedric Madianga 1286d8b46839SM'boumba Cedric Madianga if (dmadev->mem2mem) { 1287d8b46839SM'boumba Cedric Madianga dma_cap_set(DMA_MEMCPY, dd->cap_mask); 1288d8b46839SM'boumba Cedric Madianga dd->device_prep_dma_memcpy = stm32_dma_prep_dma_memcpy; 1289d8b46839SM'boumba Cedric Madianga dd->directions |= BIT(DMA_MEM_TO_MEM); 1290d8b46839SM'boumba Cedric Madianga } 1291d8b46839SM'boumba Cedric Madianga 1292d8b46839SM'boumba Cedric Madianga for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) { 1293d8b46839SM'boumba Cedric Madianga chan = &dmadev->chan[i]; 1294d8b46839SM'boumba Cedric Madianga chan->id = i; 1295d8b46839SM'boumba Cedric Madianga chan->vchan.desc_free = stm32_dma_desc_free; 1296d8b46839SM'boumba Cedric Madianga vchan_init(&chan->vchan, dd); 1297d8b46839SM'boumba Cedric Madianga } 1298d8b46839SM'boumba Cedric Madianga 1299d8b46839SM'boumba Cedric Madianga ret = dma_async_device_register(dd); 1300d8b46839SM'boumba Cedric Madianga if (ret) 130148bc73baSPierre-Yves MORDRET goto clk_free; 1302d8b46839SM'boumba Cedric Madianga 1303d8b46839SM'boumba Cedric Madianga for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) { 1304d8b46839SM'boumba Cedric Madianga chan = &dmadev->chan[i]; 1305f4fd2ec0SFabien Dessenne chan->irq = platform_get_irq(pdev, i); 1306f4fd2ec0SFabien Dessenne if (chan->irq < 0) { 1307f4fd2ec0SFabien Dessenne ret = chan->irq; 1308f4fd2ec0SFabien Dessenne if (ret != -EPROBE_DEFER) 1309f4fd2ec0SFabien Dessenne dev_err(&pdev->dev, 1310f4fd2ec0SFabien Dessenne "No irq resource for chan %d\n", i); 1311d8b46839SM'boumba Cedric Madianga goto err_unregister; 1312d8b46839SM'boumba Cedric Madianga } 1313d8b46839SM'boumba Cedric Madianga ret = devm_request_irq(&pdev->dev, chan->irq, 1314d8b46839SM'boumba Cedric Madianga stm32_dma_chan_irq, 0, 1315d8b46839SM'boumba Cedric Madianga dev_name(chan2dev(chan)), chan); 1316d8b46839SM'boumba Cedric Madianga if (ret) { 1317d8b46839SM'boumba Cedric Madianga dev_err(&pdev->dev, 1318d8b46839SM'boumba Cedric Madianga "request_irq failed with err %d channel %d\n", 1319d8b46839SM'boumba Cedric Madianga ret, i); 1320d8b46839SM'boumba Cedric Madianga goto err_unregister; 1321d8b46839SM'boumba Cedric Madianga } 1322d8b46839SM'boumba Cedric Madianga } 1323d8b46839SM'boumba Cedric Madianga 1324d8b46839SM'boumba Cedric Madianga ret = of_dma_controller_register(pdev->dev.of_node, 1325d8b46839SM'boumba Cedric Madianga stm32_dma_of_xlate, dmadev); 1326d8b46839SM'boumba Cedric Madianga if (ret < 0) { 1327d8b46839SM'boumba Cedric Madianga dev_err(&pdev->dev, 1328d8b46839SM'boumba Cedric Madianga "STM32 DMA DMA OF registration failed %d\n", ret); 1329d8b46839SM'boumba Cedric Madianga goto err_unregister; 1330d8b46839SM'boumba Cedric Madianga } 1331d8b46839SM'boumba Cedric Madianga 1332d8b46839SM'boumba Cedric Madianga platform_set_drvdata(pdev, dmadev); 1333d8b46839SM'boumba Cedric Madianga 133448bc73baSPierre-Yves MORDRET pm_runtime_set_active(&pdev->dev); 133548bc73baSPierre-Yves MORDRET pm_runtime_enable(&pdev->dev); 133648bc73baSPierre-Yves MORDRET pm_runtime_get_noresume(&pdev->dev); 133748bc73baSPierre-Yves MORDRET pm_runtime_put(&pdev->dev); 133848bc73baSPierre-Yves MORDRET 1339d8b46839SM'boumba Cedric Madianga dev_info(&pdev->dev, "STM32 DMA driver registered\n"); 1340d8b46839SM'boumba Cedric Madianga 1341d8b46839SM'boumba Cedric Madianga return 0; 1342d8b46839SM'boumba Cedric Madianga 1343d8b46839SM'boumba Cedric Madianga err_unregister: 1344d8b46839SM'boumba Cedric Madianga dma_async_device_unregister(dd); 134548bc73baSPierre-Yves MORDRET clk_free: 134648bc73baSPierre-Yves MORDRET clk_disable_unprepare(dmadev->clk); 1347d8b46839SM'boumba Cedric Madianga 1348d8b46839SM'boumba Cedric Madianga return ret; 1349d8b46839SM'boumba Cedric Madianga } 1350d8b46839SM'boumba Cedric Madianga 135148bc73baSPierre-Yves MORDRET #ifdef CONFIG_PM 135248bc73baSPierre-Yves MORDRET static int stm32_dma_runtime_suspend(struct device *dev) 135348bc73baSPierre-Yves MORDRET { 135448bc73baSPierre-Yves MORDRET struct stm32_dma_device *dmadev = dev_get_drvdata(dev); 135548bc73baSPierre-Yves MORDRET 135648bc73baSPierre-Yves MORDRET clk_disable_unprepare(dmadev->clk); 135748bc73baSPierre-Yves MORDRET 135848bc73baSPierre-Yves MORDRET return 0; 135948bc73baSPierre-Yves MORDRET } 136048bc73baSPierre-Yves MORDRET 136148bc73baSPierre-Yves MORDRET static int stm32_dma_runtime_resume(struct device *dev) 136248bc73baSPierre-Yves MORDRET { 136348bc73baSPierre-Yves MORDRET struct stm32_dma_device *dmadev = dev_get_drvdata(dev); 136448bc73baSPierre-Yves MORDRET int ret; 136548bc73baSPierre-Yves MORDRET 136648bc73baSPierre-Yves MORDRET ret = clk_prepare_enable(dmadev->clk); 136748bc73baSPierre-Yves MORDRET if (ret) { 136848bc73baSPierre-Yves MORDRET dev_err(dev, "failed to prepare_enable clock\n"); 136948bc73baSPierre-Yves MORDRET return ret; 137048bc73baSPierre-Yves MORDRET } 137148bc73baSPierre-Yves MORDRET 137248bc73baSPierre-Yves MORDRET return 0; 137348bc73baSPierre-Yves MORDRET } 137448bc73baSPierre-Yves MORDRET #endif 137548bc73baSPierre-Yves MORDRET 137648bc73baSPierre-Yves MORDRET static const struct dev_pm_ops stm32_dma_pm_ops = { 137748bc73baSPierre-Yves MORDRET SET_RUNTIME_PM_OPS(stm32_dma_runtime_suspend, 137848bc73baSPierre-Yves MORDRET stm32_dma_runtime_resume, NULL) 137948bc73baSPierre-Yves MORDRET }; 138048bc73baSPierre-Yves MORDRET 1381d8b46839SM'boumba Cedric Madianga static struct platform_driver stm32_dma_driver = { 1382d8b46839SM'boumba Cedric Madianga .driver = { 1383d8b46839SM'boumba Cedric Madianga .name = "stm32-dma", 1384d8b46839SM'boumba Cedric Madianga .of_match_table = stm32_dma_of_match, 138548bc73baSPierre-Yves MORDRET .pm = &stm32_dma_pm_ops, 1386d8b46839SM'boumba Cedric Madianga }, 1387d8b46839SM'boumba Cedric Madianga }; 1388d8b46839SM'boumba Cedric Madianga 1389d8b46839SM'boumba Cedric Madianga static int __init stm32_dma_init(void) 1390d8b46839SM'boumba Cedric Madianga { 1391d8b46839SM'boumba Cedric Madianga return platform_driver_probe(&stm32_dma_driver, stm32_dma_probe); 1392d8b46839SM'boumba Cedric Madianga } 1393d8b46839SM'boumba Cedric Madianga subsys_initcall(stm32_dma_init); 1394