1af873fceSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2d8b46839SM'boumba Cedric Madianga /* 3d8b46839SM'boumba Cedric Madianga * Driver for STM32 DMA controller 4d8b46839SM'boumba Cedric Madianga * 5d8b46839SM'boumba Cedric Madianga * Inspired by dma-jz4740.c and tegra20-apb-dma.c 6d8b46839SM'boumba Cedric Madianga * 7d8b46839SM'boumba Cedric Madianga * Copyright (C) M'boumba Cedric Madianga 2015 8d8b46839SM'boumba Cedric Madianga * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 9a2b6103bSPierre Yves MORDRET * Pierre-Yves Mordret <pierre-yves.mordret@st.com> 10d8b46839SM'boumba Cedric Madianga */ 11d8b46839SM'boumba Cedric Madianga 12d8b46839SM'boumba Cedric Madianga #include <linux/clk.h> 13d8b46839SM'boumba Cedric Madianga #include <linux/delay.h> 14d8b46839SM'boumba Cedric Madianga #include <linux/dmaengine.h> 15d8b46839SM'boumba Cedric Madianga #include <linux/dma-mapping.h> 16d8b46839SM'boumba Cedric Madianga #include <linux/err.h> 17d8b46839SM'boumba Cedric Madianga #include <linux/init.h> 18d8b46839SM'boumba Cedric Madianga #include <linux/jiffies.h> 19d8b46839SM'boumba Cedric Madianga #include <linux/list.h> 20d8b46839SM'boumba Cedric Madianga #include <linux/module.h> 21d8b46839SM'boumba Cedric Madianga #include <linux/of.h> 22d8b46839SM'boumba Cedric Madianga #include <linux/of_device.h> 23d8b46839SM'boumba Cedric Madianga #include <linux/of_dma.h> 24d8b46839SM'boumba Cedric Madianga #include <linux/platform_device.h> 2548bc73baSPierre-Yves MORDRET #include <linux/pm_runtime.h> 26d8b46839SM'boumba Cedric Madianga #include <linux/reset.h> 27d8b46839SM'boumba Cedric Madianga #include <linux/sched.h> 28d8b46839SM'boumba Cedric Madianga #include <linux/slab.h> 29d8b46839SM'boumba Cedric Madianga 30d8b46839SM'boumba Cedric Madianga #include "virt-dma.h" 31d8b46839SM'boumba Cedric Madianga 32d8b46839SM'boumba Cedric Madianga #define STM32_DMA_LISR 0x0000 /* DMA Low Int Status Reg */ 33d8b46839SM'boumba Cedric Madianga #define STM32_DMA_HISR 0x0004 /* DMA High Int Status Reg */ 34d8b46839SM'boumba Cedric Madianga #define STM32_DMA_LIFCR 0x0008 /* DMA Low Int Flag Clear Reg */ 35d8b46839SM'boumba Cedric Madianga #define STM32_DMA_HIFCR 0x000c /* DMA High Int Flag Clear Reg */ 36d8b46839SM'boumba Cedric Madianga #define STM32_DMA_TCI BIT(5) /* Transfer Complete Interrupt */ 37c2d86b1cSPierre Yves MORDRET #define STM32_DMA_HTI BIT(4) /* Half Transfer Interrupt */ 38d8b46839SM'boumba Cedric Madianga #define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */ 39d8b46839SM'boumba Cedric Madianga #define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */ 40d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */ 419df3bd55SPierre Yves MORDRET #define STM32_DMA_MASKI (STM32_DMA_TCI \ 429df3bd55SPierre Yves MORDRET | STM32_DMA_TEI \ 439df3bd55SPierre Yves MORDRET | STM32_DMA_DMEI \ 449df3bd55SPierre Yves MORDRET | STM32_DMA_FEI) 45d8b46839SM'boumba Cedric Madianga 46d8b46839SM'boumba Cedric Madianga /* DMA Stream x Configuration Register */ 47d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */ 48d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_REQ(n) ((n & 0x7) << 25) 49d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MBURST_MASK GENMASK(24, 23) 50d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MBURST(n) ((n & 0x3) << 23) 51d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PBURST_MASK GENMASK(22, 21) 52d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PBURST(n) ((n & 0x3) << 21) 53d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PL_MASK GENMASK(17, 16) 54d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PL(n) ((n & 0x3) << 16) 55d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MSIZE_MASK GENMASK(14, 13) 56d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MSIZE(n) ((n & 0x3) << 13) 57d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PSIZE_MASK GENMASK(12, 11) 58d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PSIZE(n) ((n & 0x3) << 11) 59d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PSIZE_GET(n) ((n & STM32_DMA_SCR_PSIZE_MASK) >> 11) 60d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_DIR_MASK GENMASK(7, 6) 61d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_DIR(n) ((n & 0x3) << 6) 62d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_CT BIT(19) /* Target in double buffer */ 63d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_DBM BIT(18) /* Double Buffer Mode */ 64d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PINCOS BIT(15) /* Peripheral inc offset size */ 65d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MINC BIT(10) /* Memory increment mode */ 66d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PINC BIT(9) /* Peripheral increment mode */ 67d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_CIRC BIT(8) /* Circular mode */ 68d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PFCTRL BIT(5) /* Peripheral Flow Controller */ 69249d5531SPierre Yves MORDRET #define STM32_DMA_SCR_TCIE BIT(4) /* Transfer Complete Int Enable 70249d5531SPierre Yves MORDRET */ 71d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_TEIE BIT(2) /* Transfer Error Int Enable */ 72d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_DMEIE BIT(1) /* Direct Mode Err Int Enable */ 73d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_EN BIT(0) /* Stream Enable */ 74d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_CFG_MASK (STM32_DMA_SCR_PINC \ 75d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_MINC \ 76d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_PINCOS \ 77d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_PL_MASK) 78d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_IRQ_MASK (STM32_DMA_SCR_TCIE \ 79d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_TEIE \ 80d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_DMEIE) 81d8b46839SM'boumba Cedric Madianga 82d8b46839SM'boumba Cedric Madianga /* DMA Stream x number of data register */ 83d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SNDTR(x) (0x0014 + 0x18 * (x)) 84d8b46839SM'boumba Cedric Madianga 85d8b46839SM'boumba Cedric Madianga /* DMA stream peripheral address register */ 86d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SPAR(x) (0x0018 + 0x18 * (x)) 87d8b46839SM'boumba Cedric Madianga 88d8b46839SM'boumba Cedric Madianga /* DMA stream x memory 0 address register */ 89d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SM0AR(x) (0x001c + 0x18 * (x)) 90d8b46839SM'boumba Cedric Madianga 91d8b46839SM'boumba Cedric Madianga /* DMA stream x memory 1 address register */ 92d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SM1AR(x) (0x0020 + 0x18 * (x)) 93d8b46839SM'boumba Cedric Madianga 94d8b46839SM'boumba Cedric Madianga /* DMA stream x FIFO control register */ 95d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR(x) (0x0024 + 0x18 * (x)) 96d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_FTH_MASK GENMASK(1, 0) 97d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_FTH(n) (n & STM32_DMA_SFCR_FTH_MASK) 98d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_FEIE BIT(7) /* FIFO error interrupt enable */ 99d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_DMDIS BIT(2) /* Direct mode disable */ 100d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_MASK (STM32_DMA_SFCR_FEIE \ 101d8b46839SM'boumba Cedric Madianga | STM32_DMA_SFCR_DMDIS) 102d8b46839SM'boumba Cedric Madianga 103d8b46839SM'boumba Cedric Madianga /* DMA direction */ 104d8b46839SM'boumba Cedric Madianga #define STM32_DMA_DEV_TO_MEM 0x00 105d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MEM_TO_DEV 0x01 106d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MEM_TO_MEM 0x02 107d8b46839SM'boumba Cedric Madianga 108d8b46839SM'boumba Cedric Madianga /* DMA priority level */ 109d8b46839SM'boumba Cedric Madianga #define STM32_DMA_PRIORITY_LOW 0x00 110d8b46839SM'boumba Cedric Madianga #define STM32_DMA_PRIORITY_MEDIUM 0x01 111d8b46839SM'boumba Cedric Madianga #define STM32_DMA_PRIORITY_HIGH 0x02 112d8b46839SM'boumba Cedric Madianga #define STM32_DMA_PRIORITY_VERY_HIGH 0x03 113d8b46839SM'boumba Cedric Madianga 114d8b46839SM'boumba Cedric Madianga /* DMA FIFO threshold selection */ 115d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00 116d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FIFO_THRESHOLD_HALFFULL 0x01 117d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FIFO_THRESHOLD_3QUARTERSFULL 0x02 118d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FIFO_THRESHOLD_FULL 0x03 119d8b46839SM'boumba Cedric Madianga 120d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MAX_DATA_ITEMS 0xffff 12180a76952SPierre Yves MORDRET /* 12280a76952SPierre Yves MORDRET * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter 12380a76952SPierre Yves MORDRET * gather at boundary. Thus it's safer to round down this value on FIFO 12480a76952SPierre Yves MORDRET * size (16 Bytes) 12580a76952SPierre Yves MORDRET */ 12680a76952SPierre Yves MORDRET #define STM32_DMA_ALIGNED_MAX_DATA_ITEMS \ 12780a76952SPierre Yves MORDRET ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16) 128d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MAX_CHANNELS 0x08 129d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MAX_REQUEST_ID 0x08 130d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MAX_DATA_PARAM 0x03 131a2b6103bSPierre Yves MORDRET #define STM32_DMA_FIFO_SIZE 16 /* FIFO is 16 bytes */ 132a2b6103bSPierre Yves MORDRET #define STM32_DMA_MIN_BURST 4 133276b0046SM'boumba Cedric Madianga #define STM32_DMA_MAX_BURST 16 134d8b46839SM'boumba Cedric Madianga 135951f44cbSPierre Yves MORDRET /* DMA Features */ 136951f44cbSPierre Yves MORDRET #define STM32_DMA_THRESHOLD_FTR_MASK GENMASK(1, 0) 137951f44cbSPierre Yves MORDRET #define STM32_DMA_THRESHOLD_FTR_GET(n) ((n) & STM32_DMA_THRESHOLD_FTR_MASK) 138951f44cbSPierre Yves MORDRET 139d8b46839SM'boumba Cedric Madianga enum stm32_dma_width { 140d8b46839SM'boumba Cedric Madianga STM32_DMA_BYTE, 141d8b46839SM'boumba Cedric Madianga STM32_DMA_HALF_WORD, 142d8b46839SM'boumba Cedric Madianga STM32_DMA_WORD, 143d8b46839SM'boumba Cedric Madianga }; 144d8b46839SM'boumba Cedric Madianga 145d8b46839SM'boumba Cedric Madianga enum stm32_dma_burst_size { 146d8b46839SM'boumba Cedric Madianga STM32_DMA_BURST_SINGLE, 147d8b46839SM'boumba Cedric Madianga STM32_DMA_BURST_INCR4, 148d8b46839SM'boumba Cedric Madianga STM32_DMA_BURST_INCR8, 149d8b46839SM'boumba Cedric Madianga STM32_DMA_BURST_INCR16, 150d8b46839SM'boumba Cedric Madianga }; 151d8b46839SM'boumba Cedric Madianga 152951f44cbSPierre Yves MORDRET /** 153951f44cbSPierre Yves MORDRET * struct stm32_dma_cfg - STM32 DMA custom configuration 154951f44cbSPierre Yves MORDRET * @channel_id: channel ID 155951f44cbSPierre Yves MORDRET * @request_line: DMA request 156951f44cbSPierre Yves MORDRET * @stream_config: 32bit mask specifying the DMA channel configuration 157951f44cbSPierre Yves MORDRET * @features: 32bit mask specifying the DMA Feature list 158951f44cbSPierre Yves MORDRET */ 159d8b46839SM'boumba Cedric Madianga struct stm32_dma_cfg { 160d8b46839SM'boumba Cedric Madianga u32 channel_id; 161d8b46839SM'boumba Cedric Madianga u32 request_line; 162d8b46839SM'boumba Cedric Madianga u32 stream_config; 163951f44cbSPierre Yves MORDRET u32 features; 164d8b46839SM'boumba Cedric Madianga }; 165d8b46839SM'boumba Cedric Madianga 166d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan_reg { 167d8b46839SM'boumba Cedric Madianga u32 dma_lisr; 168d8b46839SM'boumba Cedric Madianga u32 dma_hisr; 169d8b46839SM'boumba Cedric Madianga u32 dma_lifcr; 170d8b46839SM'boumba Cedric Madianga u32 dma_hifcr; 171d8b46839SM'boumba Cedric Madianga u32 dma_scr; 172d8b46839SM'boumba Cedric Madianga u32 dma_sndtr; 173d8b46839SM'boumba Cedric Madianga u32 dma_spar; 174d8b46839SM'boumba Cedric Madianga u32 dma_sm0ar; 175d8b46839SM'boumba Cedric Madianga u32 dma_sm1ar; 176d8b46839SM'boumba Cedric Madianga u32 dma_sfcr; 177d8b46839SM'boumba Cedric Madianga }; 178d8b46839SM'boumba Cedric Madianga 179d8b46839SM'boumba Cedric Madianga struct stm32_dma_sg_req { 180d8b46839SM'boumba Cedric Madianga u32 len; 181d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan_reg chan_reg; 182d8b46839SM'boumba Cedric Madianga }; 183d8b46839SM'boumba Cedric Madianga 184d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc { 185d8b46839SM'boumba Cedric Madianga struct virt_dma_desc vdesc; 186d8b46839SM'boumba Cedric Madianga bool cyclic; 187d8b46839SM'boumba Cedric Madianga u32 num_sgs; 188d8b46839SM'boumba Cedric Madianga struct stm32_dma_sg_req sg_req[]; 189d8b46839SM'boumba Cedric Madianga }; 190d8b46839SM'boumba Cedric Madianga 191d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan { 192d8b46839SM'boumba Cedric Madianga struct virt_dma_chan vchan; 193d8b46839SM'boumba Cedric Madianga bool config_init; 194d8b46839SM'boumba Cedric Madianga bool busy; 195d8b46839SM'boumba Cedric Madianga u32 id; 196d8b46839SM'boumba Cedric Madianga u32 irq; 197d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc; 198d8b46839SM'boumba Cedric Madianga u32 next_sg; 199d8b46839SM'boumba Cedric Madianga struct dma_slave_config dma_sconfig; 200d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan_reg chan_reg; 201951f44cbSPierre Yves MORDRET u32 threshold; 202a2b6103bSPierre Yves MORDRET u32 mem_burst; 203a2b6103bSPierre Yves MORDRET u32 mem_width; 204d8b46839SM'boumba Cedric Madianga }; 205d8b46839SM'boumba Cedric Madianga 206d8b46839SM'boumba Cedric Madianga struct stm32_dma_device { 207d8b46839SM'boumba Cedric Madianga struct dma_device ddev; 208d8b46839SM'boumba Cedric Madianga void __iomem *base; 209d8b46839SM'boumba Cedric Madianga struct clk *clk; 210d8b46839SM'boumba Cedric Madianga struct reset_control *rst; 211d8b46839SM'boumba Cedric Madianga bool mem2mem; 212d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS]; 213d8b46839SM'boumba Cedric Madianga }; 214d8b46839SM'boumba Cedric Madianga 215d8b46839SM'boumba Cedric Madianga static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan) 216d8b46839SM'boumba Cedric Madianga { 217d8b46839SM'boumba Cedric Madianga return container_of(chan->vchan.chan.device, struct stm32_dma_device, 218d8b46839SM'boumba Cedric Madianga ddev); 219d8b46839SM'boumba Cedric Madianga } 220d8b46839SM'boumba Cedric Madianga 221d8b46839SM'boumba Cedric Madianga static struct stm32_dma_chan *to_stm32_dma_chan(struct dma_chan *c) 222d8b46839SM'boumba Cedric Madianga { 223d8b46839SM'boumba Cedric Madianga return container_of(c, struct stm32_dma_chan, vchan.chan); 224d8b46839SM'boumba Cedric Madianga } 225d8b46839SM'boumba Cedric Madianga 226d8b46839SM'boumba Cedric Madianga static struct stm32_dma_desc *to_stm32_dma_desc(struct virt_dma_desc *vdesc) 227d8b46839SM'boumba Cedric Madianga { 228d8b46839SM'boumba Cedric Madianga return container_of(vdesc, struct stm32_dma_desc, vdesc); 229d8b46839SM'boumba Cedric Madianga } 230d8b46839SM'boumba Cedric Madianga 231d8b46839SM'boumba Cedric Madianga static struct device *chan2dev(struct stm32_dma_chan *chan) 232d8b46839SM'boumba Cedric Madianga { 233d8b46839SM'boumba Cedric Madianga return &chan->vchan.chan.dev->device; 234d8b46839SM'boumba Cedric Madianga } 235d8b46839SM'boumba Cedric Madianga 236d8b46839SM'boumba Cedric Madianga static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg) 237d8b46839SM'boumba Cedric Madianga { 238d8b46839SM'boumba Cedric Madianga return readl_relaxed(dmadev->base + reg); 239d8b46839SM'boumba Cedric Madianga } 240d8b46839SM'boumba Cedric Madianga 241d8b46839SM'boumba Cedric Madianga static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val) 242d8b46839SM'boumba Cedric Madianga { 243d8b46839SM'boumba Cedric Madianga writel_relaxed(val, dmadev->base + reg); 244d8b46839SM'boumba Cedric Madianga } 245d8b46839SM'boumba Cedric Madianga 246d8b46839SM'boumba Cedric Madianga static struct stm32_dma_desc *stm32_dma_alloc_desc(u32 num_sgs) 247d8b46839SM'boumba Cedric Madianga { 248d8b46839SM'boumba Cedric Madianga return kzalloc(sizeof(struct stm32_dma_desc) + 249d8b46839SM'boumba Cedric Madianga sizeof(struct stm32_dma_sg_req) * num_sgs, GFP_NOWAIT); 250d8b46839SM'boumba Cedric Madianga } 251d8b46839SM'boumba Cedric Madianga 252d8b46839SM'boumba Cedric Madianga static int stm32_dma_get_width(struct stm32_dma_chan *chan, 253d8b46839SM'boumba Cedric Madianga enum dma_slave_buswidth width) 254d8b46839SM'boumba Cedric Madianga { 255d8b46839SM'boumba Cedric Madianga switch (width) { 256d8b46839SM'boumba Cedric Madianga case DMA_SLAVE_BUSWIDTH_1_BYTE: 257d8b46839SM'boumba Cedric Madianga return STM32_DMA_BYTE; 258d8b46839SM'boumba Cedric Madianga case DMA_SLAVE_BUSWIDTH_2_BYTES: 259d8b46839SM'boumba Cedric Madianga return STM32_DMA_HALF_WORD; 260d8b46839SM'boumba Cedric Madianga case DMA_SLAVE_BUSWIDTH_4_BYTES: 261d8b46839SM'boumba Cedric Madianga return STM32_DMA_WORD; 262d8b46839SM'boumba Cedric Madianga default: 263d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Dma bus width not supported\n"); 264d8b46839SM'boumba Cedric Madianga return -EINVAL; 265d8b46839SM'boumba Cedric Madianga } 266d8b46839SM'boumba Cedric Madianga } 267d8b46839SM'boumba Cedric Madianga 268a2b6103bSPierre Yves MORDRET static enum dma_slave_buswidth stm32_dma_get_max_width(u32 buf_len, 269a2b6103bSPierre Yves MORDRET u32 threshold) 270a2b6103bSPierre Yves MORDRET { 271a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth max_width; 272a2b6103bSPierre Yves MORDRET 273a2b6103bSPierre Yves MORDRET if (threshold == STM32_DMA_FIFO_THRESHOLD_FULL) 274a2b6103bSPierre Yves MORDRET max_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 275a2b6103bSPierre Yves MORDRET else 276a2b6103bSPierre Yves MORDRET max_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 277a2b6103bSPierre Yves MORDRET 278a2b6103bSPierre Yves MORDRET while ((buf_len < max_width || buf_len % max_width) && 279a2b6103bSPierre Yves MORDRET max_width > DMA_SLAVE_BUSWIDTH_1_BYTE) 280a2b6103bSPierre Yves MORDRET max_width = max_width >> 1; 281a2b6103bSPierre Yves MORDRET 282a2b6103bSPierre Yves MORDRET return max_width; 283a2b6103bSPierre Yves MORDRET } 284a2b6103bSPierre Yves MORDRET 285a2b6103bSPierre Yves MORDRET static bool stm32_dma_fifo_threshold_is_allowed(u32 burst, u32 threshold, 286a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth width) 287a2b6103bSPierre Yves MORDRET { 288a2b6103bSPierre Yves MORDRET u32 remaining; 289a2b6103bSPierre Yves MORDRET 290a2b6103bSPierre Yves MORDRET if (width != DMA_SLAVE_BUSWIDTH_UNDEFINED) { 291a2b6103bSPierre Yves MORDRET if (burst != 0) { 292a2b6103bSPierre Yves MORDRET /* 293a2b6103bSPierre Yves MORDRET * If number of beats fit in several whole bursts 294a2b6103bSPierre Yves MORDRET * this configuration is allowed. 295a2b6103bSPierre Yves MORDRET */ 296a2b6103bSPierre Yves MORDRET remaining = ((STM32_DMA_FIFO_SIZE / width) * 297a2b6103bSPierre Yves MORDRET (threshold + 1) / 4) % burst; 298a2b6103bSPierre Yves MORDRET 299a2b6103bSPierre Yves MORDRET if (remaining == 0) 300a2b6103bSPierre Yves MORDRET return true; 301a2b6103bSPierre Yves MORDRET } else { 302a2b6103bSPierre Yves MORDRET return true; 303a2b6103bSPierre Yves MORDRET } 304a2b6103bSPierre Yves MORDRET } 305a2b6103bSPierre Yves MORDRET 306a2b6103bSPierre Yves MORDRET return false; 307a2b6103bSPierre Yves MORDRET } 308a2b6103bSPierre Yves MORDRET 309a2b6103bSPierre Yves MORDRET static bool stm32_dma_is_burst_possible(u32 buf_len, u32 threshold) 310a2b6103bSPierre Yves MORDRET { 311cc832dc8SPierre-Yves MORDRET /* 312cc832dc8SPierre-Yves MORDRET * Buffer or period length has to be aligned on FIFO depth. 313cc832dc8SPierre-Yves MORDRET * Otherwise bytes may be stuck within FIFO at buffer or period 314cc832dc8SPierre-Yves MORDRET * length. 315cc832dc8SPierre-Yves MORDRET */ 316cc832dc8SPierre-Yves MORDRET return ((buf_len % ((threshold + 1) * 4)) == 0); 317a2b6103bSPierre Yves MORDRET } 318a2b6103bSPierre Yves MORDRET 319a2b6103bSPierre Yves MORDRET static u32 stm32_dma_get_best_burst(u32 buf_len, u32 max_burst, u32 threshold, 320a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth width) 321a2b6103bSPierre Yves MORDRET { 322a2b6103bSPierre Yves MORDRET u32 best_burst = max_burst; 323a2b6103bSPierre Yves MORDRET 324a2b6103bSPierre Yves MORDRET if (best_burst == 1 || !stm32_dma_is_burst_possible(buf_len, threshold)) 325a2b6103bSPierre Yves MORDRET return 0; 326a2b6103bSPierre Yves MORDRET 327a2b6103bSPierre Yves MORDRET while ((buf_len < best_burst * width && best_burst > 1) || 328a2b6103bSPierre Yves MORDRET !stm32_dma_fifo_threshold_is_allowed(best_burst, threshold, 329a2b6103bSPierre Yves MORDRET width)) { 330a2b6103bSPierre Yves MORDRET if (best_burst > STM32_DMA_MIN_BURST) 331a2b6103bSPierre Yves MORDRET best_burst = best_burst >> 1; 332a2b6103bSPierre Yves MORDRET else 333a2b6103bSPierre Yves MORDRET best_burst = 0; 334a2b6103bSPierre Yves MORDRET } 335a2b6103bSPierre Yves MORDRET 336a2b6103bSPierre Yves MORDRET return best_burst; 337a2b6103bSPierre Yves MORDRET } 338a2b6103bSPierre Yves MORDRET 339d8b46839SM'boumba Cedric Madianga static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst) 340d8b46839SM'boumba Cedric Madianga { 341d8b46839SM'boumba Cedric Madianga switch (maxburst) { 342d8b46839SM'boumba Cedric Madianga case 0: 343d8b46839SM'boumba Cedric Madianga case 1: 344d8b46839SM'boumba Cedric Madianga return STM32_DMA_BURST_SINGLE; 345d8b46839SM'boumba Cedric Madianga case 4: 346d8b46839SM'boumba Cedric Madianga return STM32_DMA_BURST_INCR4; 347d8b46839SM'boumba Cedric Madianga case 8: 348d8b46839SM'boumba Cedric Madianga return STM32_DMA_BURST_INCR8; 349d8b46839SM'boumba Cedric Madianga case 16: 350d8b46839SM'boumba Cedric Madianga return STM32_DMA_BURST_INCR16; 351d8b46839SM'boumba Cedric Madianga default: 352d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Dma burst size not supported\n"); 353d8b46839SM'boumba Cedric Madianga return -EINVAL; 354d8b46839SM'boumba Cedric Madianga } 355d8b46839SM'boumba Cedric Madianga } 356d8b46839SM'boumba Cedric Madianga 357d8b46839SM'boumba Cedric Madianga static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan, 358a2b6103bSPierre Yves MORDRET u32 src_burst, u32 dst_burst) 359d8b46839SM'boumba Cedric Madianga { 360d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK; 361d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE; 362d8b46839SM'boumba Cedric Madianga 363a2b6103bSPierre Yves MORDRET if (!src_burst && !dst_burst) { 364d8b46839SM'boumba Cedric Madianga /* Using direct mode */ 365d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE; 366d8b46839SM'boumba Cedric Madianga } else { 367d8b46839SM'boumba Cedric Madianga /* Using FIFO mode */ 368d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; 369d8b46839SM'boumba Cedric Madianga } 370d8b46839SM'boumba Cedric Madianga } 371d8b46839SM'boumba Cedric Madianga 372d8b46839SM'boumba Cedric Madianga static int stm32_dma_slave_config(struct dma_chan *c, 373d8b46839SM'boumba Cedric Madianga struct dma_slave_config *config) 374d8b46839SM'boumba Cedric Madianga { 375d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 376d8b46839SM'boumba Cedric Madianga 377d8b46839SM'boumba Cedric Madianga memcpy(&chan->dma_sconfig, config, sizeof(*config)); 378d8b46839SM'boumba Cedric Madianga 379d8b46839SM'boumba Cedric Madianga chan->config_init = true; 380d8b46839SM'boumba Cedric Madianga 381d8b46839SM'boumba Cedric Madianga return 0; 382d8b46839SM'boumba Cedric Madianga } 383d8b46839SM'boumba Cedric Madianga 384d8b46839SM'boumba Cedric Madianga static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan) 385d8b46839SM'boumba Cedric Madianga { 386d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 387d8b46839SM'boumba Cedric Madianga u32 flags, dma_isr; 388d8b46839SM'boumba Cedric Madianga 389d8b46839SM'boumba Cedric Madianga /* 390d8b46839SM'boumba Cedric Madianga * Read "flags" from DMA_xISR register corresponding to the selected 391d8b46839SM'boumba Cedric Madianga * DMA channel at the correct bit offset inside that register. 392d8b46839SM'boumba Cedric Madianga * 393d8b46839SM'boumba Cedric Madianga * If (ch % 4) is 2 or 3, left shift the mask by 16 bits. 394d8b46839SM'boumba Cedric Madianga * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. 395d8b46839SM'boumba Cedric Madianga */ 396d8b46839SM'boumba Cedric Madianga 397d8b46839SM'boumba Cedric Madianga if (chan->id & 4) 398d8b46839SM'boumba Cedric Madianga dma_isr = stm32_dma_read(dmadev, STM32_DMA_HISR); 399d8b46839SM'boumba Cedric Madianga else 400d8b46839SM'boumba Cedric Madianga dma_isr = stm32_dma_read(dmadev, STM32_DMA_LISR); 401d8b46839SM'boumba Cedric Madianga 402d8b46839SM'boumba Cedric Madianga flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); 403d8b46839SM'boumba Cedric Madianga 4049df3bd55SPierre Yves MORDRET return flags & STM32_DMA_MASKI; 405d8b46839SM'boumba Cedric Madianga } 406d8b46839SM'boumba Cedric Madianga 407d8b46839SM'boumba Cedric Madianga static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags) 408d8b46839SM'boumba Cedric Madianga { 409d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 410d8b46839SM'boumba Cedric Madianga u32 dma_ifcr; 411d8b46839SM'boumba Cedric Madianga 412d8b46839SM'boumba Cedric Madianga /* 413d8b46839SM'boumba Cedric Madianga * Write "flags" to the DMA_xIFCR register corresponding to the selected 414d8b46839SM'boumba Cedric Madianga * DMA channel at the correct bit offset inside that register. 415d8b46839SM'boumba Cedric Madianga * 416d8b46839SM'boumba Cedric Madianga * If (ch % 4) is 2 or 3, left shift the mask by 16 bits. 417d8b46839SM'boumba Cedric Madianga * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. 418d8b46839SM'boumba Cedric Madianga */ 4199df3bd55SPierre Yves MORDRET flags &= STM32_DMA_MASKI; 420d8b46839SM'boumba Cedric Madianga dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); 421d8b46839SM'boumba Cedric Madianga 422d8b46839SM'boumba Cedric Madianga if (chan->id & 4) 423d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_HIFCR, dma_ifcr); 424d8b46839SM'boumba Cedric Madianga else 425d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_LIFCR, dma_ifcr); 426d8b46839SM'boumba Cedric Madianga } 427d8b46839SM'boumba Cedric Madianga 428d8b46839SM'boumba Cedric Madianga static int stm32_dma_disable_chan(struct stm32_dma_chan *chan) 429d8b46839SM'boumba Cedric Madianga { 430d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 431d8b46839SM'boumba Cedric Madianga unsigned long timeout = jiffies + msecs_to_jiffies(5000); 432d8b46839SM'boumba Cedric Madianga u32 dma_scr, id; 433d8b46839SM'boumba Cedric Madianga 434d8b46839SM'boumba Cedric Madianga id = chan->id; 435d8b46839SM'boumba Cedric Madianga dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); 436d8b46839SM'boumba Cedric Madianga 437d8b46839SM'boumba Cedric Madianga if (dma_scr & STM32_DMA_SCR_EN) { 438d8b46839SM'boumba Cedric Madianga dma_scr &= ~STM32_DMA_SCR_EN; 439d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SCR(id), dma_scr); 440d8b46839SM'boumba Cedric Madianga 441d8b46839SM'boumba Cedric Madianga do { 442d8b46839SM'boumba Cedric Madianga dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); 443d8b46839SM'boumba Cedric Madianga dma_scr &= STM32_DMA_SCR_EN; 444d8b46839SM'boumba Cedric Madianga if (!dma_scr) 445d8b46839SM'boumba Cedric Madianga break; 446d8b46839SM'boumba Cedric Madianga 447d8b46839SM'boumba Cedric Madianga if (time_after_eq(jiffies, timeout)) { 448d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "%s: timeout!\n", 449d8b46839SM'boumba Cedric Madianga __func__); 450d8b46839SM'boumba Cedric Madianga return -EBUSY; 451d8b46839SM'boumba Cedric Madianga } 452d8b46839SM'boumba Cedric Madianga cond_resched(); 453d8b46839SM'boumba Cedric Madianga } while (1); 454d8b46839SM'boumba Cedric Madianga } 455d8b46839SM'boumba Cedric Madianga 456d8b46839SM'boumba Cedric Madianga return 0; 457d8b46839SM'boumba Cedric Madianga } 458d8b46839SM'boumba Cedric Madianga 459d8b46839SM'boumba Cedric Madianga static void stm32_dma_stop(struct stm32_dma_chan *chan) 460d8b46839SM'boumba Cedric Madianga { 461d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 462d8b46839SM'boumba Cedric Madianga u32 dma_scr, dma_sfcr, status; 463d8b46839SM'boumba Cedric Madianga int ret; 464d8b46839SM'boumba Cedric Madianga 465d8b46839SM'boumba Cedric Madianga /* Disable interrupts */ 466d8b46839SM'boumba Cedric Madianga dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 467d8b46839SM'boumba Cedric Madianga dma_scr &= ~STM32_DMA_SCR_IRQ_MASK; 468d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); 469d8b46839SM'boumba Cedric Madianga dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); 470d8b46839SM'boumba Cedric Madianga dma_sfcr &= ~STM32_DMA_SFCR_FEIE; 471d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr); 472d8b46839SM'boumba Cedric Madianga 473d8b46839SM'boumba Cedric Madianga /* Disable DMA */ 474d8b46839SM'boumba Cedric Madianga ret = stm32_dma_disable_chan(chan); 475d8b46839SM'boumba Cedric Madianga if (ret < 0) 476d8b46839SM'boumba Cedric Madianga return; 477d8b46839SM'boumba Cedric Madianga 478d8b46839SM'boumba Cedric Madianga /* Clear interrupt status if it is there */ 479d8b46839SM'boumba Cedric Madianga status = stm32_dma_irq_status(chan); 480d8b46839SM'boumba Cedric Madianga if (status) { 481d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n", 482d8b46839SM'boumba Cedric Madianga __func__, status); 483d8b46839SM'boumba Cedric Madianga stm32_dma_irq_clear(chan, status); 484d8b46839SM'boumba Cedric Madianga } 485d8b46839SM'boumba Cedric Madianga 486d8b46839SM'boumba Cedric Madianga chan->busy = false; 487d8b46839SM'boumba Cedric Madianga } 488d8b46839SM'boumba Cedric Madianga 489d8b46839SM'boumba Cedric Madianga static int stm32_dma_terminate_all(struct dma_chan *c) 490d8b46839SM'boumba Cedric Madianga { 491d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 492d8b46839SM'boumba Cedric Madianga unsigned long flags; 493d8b46839SM'boumba Cedric Madianga LIST_HEAD(head); 494d8b46839SM'boumba Cedric Madianga 495d8b46839SM'boumba Cedric Madianga spin_lock_irqsave(&chan->vchan.lock, flags); 496d8b46839SM'boumba Cedric Madianga 497d8b46839SM'boumba Cedric Madianga if (chan->busy) { 498d8b46839SM'boumba Cedric Madianga stm32_dma_stop(chan); 499d8b46839SM'boumba Cedric Madianga chan->desc = NULL; 500d8b46839SM'boumba Cedric Madianga } 501d8b46839SM'boumba Cedric Madianga 502d8b46839SM'boumba Cedric Madianga vchan_get_all_descriptors(&chan->vchan, &head); 503d8b46839SM'boumba Cedric Madianga spin_unlock_irqrestore(&chan->vchan.lock, flags); 504d8b46839SM'boumba Cedric Madianga vchan_dma_desc_free_list(&chan->vchan, &head); 505d8b46839SM'boumba Cedric Madianga 506d8b46839SM'boumba Cedric Madianga return 0; 507d8b46839SM'boumba Cedric Madianga } 508d8b46839SM'boumba Cedric Madianga 509dc808675SM'boumba Cedric Madianga static void stm32_dma_synchronize(struct dma_chan *c) 510dc808675SM'boumba Cedric Madianga { 511dc808675SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 512dc808675SM'boumba Cedric Madianga 513dc808675SM'boumba Cedric Madianga vchan_synchronize(&chan->vchan); 514dc808675SM'boumba Cedric Madianga } 515dc808675SM'boumba Cedric Madianga 516d8b46839SM'boumba Cedric Madianga static void stm32_dma_dump_reg(struct stm32_dma_chan *chan) 517d8b46839SM'boumba Cedric Madianga { 518d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 519d8b46839SM'boumba Cedric Madianga u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 520d8b46839SM'boumba Cedric Madianga u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); 521d8b46839SM'boumba Cedric Madianga u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id)); 522d8b46839SM'boumba Cedric Madianga u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id)); 523d8b46839SM'boumba Cedric Madianga u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id)); 524d8b46839SM'boumba Cedric Madianga u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); 525d8b46839SM'boumba Cedric Madianga 526d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SCR: 0x%08x\n", scr); 527d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "NDTR: 0x%08x\n", ndtr); 528d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SPAR: 0x%08x\n", spar); 529d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar); 530d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar); 531d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SFCR: 0x%08x\n", sfcr); 532d8b46839SM'boumba Cedric Madianga } 533d8b46839SM'boumba Cedric Madianga 534e57cb3b3SPierre Yves MORDRET static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan); 535e57cb3b3SPierre Yves MORDRET 5368d1b76f0SM'boumba Cedric Madianga static void stm32_dma_start_transfer(struct stm32_dma_chan *chan) 537d8b46839SM'boumba Cedric Madianga { 538d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 539d8b46839SM'boumba Cedric Madianga struct virt_dma_desc *vdesc; 540d8b46839SM'boumba Cedric Madianga struct stm32_dma_sg_req *sg_req; 541d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan_reg *reg; 542d8b46839SM'boumba Cedric Madianga u32 status; 543d8b46839SM'boumba Cedric Madianga int ret; 544d8b46839SM'boumba Cedric Madianga 545d8b46839SM'boumba Cedric Madianga ret = stm32_dma_disable_chan(chan); 546d8b46839SM'boumba Cedric Madianga if (ret < 0) 5478d1b76f0SM'boumba Cedric Madianga return; 548d8b46839SM'boumba Cedric Madianga 549d8b46839SM'boumba Cedric Madianga if (!chan->desc) { 550d8b46839SM'boumba Cedric Madianga vdesc = vchan_next_desc(&chan->vchan); 551d8b46839SM'boumba Cedric Madianga if (!vdesc) 5528d1b76f0SM'boumba Cedric Madianga return; 553d8b46839SM'boumba Cedric Madianga 554d8b46839SM'boumba Cedric Madianga chan->desc = to_stm32_dma_desc(vdesc); 555d8b46839SM'boumba Cedric Madianga chan->next_sg = 0; 556d8b46839SM'boumba Cedric Madianga } 557d8b46839SM'boumba Cedric Madianga 558d8b46839SM'boumba Cedric Madianga if (chan->next_sg == chan->desc->num_sgs) 559d8b46839SM'boumba Cedric Madianga chan->next_sg = 0; 560d8b46839SM'boumba Cedric Madianga 561d8b46839SM'boumba Cedric Madianga sg_req = &chan->desc->sg_req[chan->next_sg]; 562d8b46839SM'boumba Cedric Madianga reg = &sg_req->chan_reg; 563d8b46839SM'boumba Cedric Madianga 564d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); 565d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar); 566d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar); 567d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr); 568d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar); 569d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr); 570d8b46839SM'boumba Cedric Madianga 571d8b46839SM'boumba Cedric Madianga chan->next_sg++; 572d8b46839SM'boumba Cedric Madianga 573d8b46839SM'boumba Cedric Madianga /* Clear interrupt status if it is there */ 574d8b46839SM'boumba Cedric Madianga status = stm32_dma_irq_status(chan); 575d8b46839SM'boumba Cedric Madianga if (status) 576d8b46839SM'boumba Cedric Madianga stm32_dma_irq_clear(chan, status); 577d8b46839SM'boumba Cedric Madianga 578e57cb3b3SPierre Yves MORDRET if (chan->desc->cyclic) 579e57cb3b3SPierre Yves MORDRET stm32_dma_configure_next_sg(chan); 580e57cb3b3SPierre Yves MORDRET 581d8b46839SM'boumba Cedric Madianga stm32_dma_dump_reg(chan); 582d8b46839SM'boumba Cedric Madianga 583d8b46839SM'boumba Cedric Madianga /* Start DMA */ 584d8b46839SM'boumba Cedric Madianga reg->dma_scr |= STM32_DMA_SCR_EN; 585d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); 586d8b46839SM'boumba Cedric Madianga 587d8b46839SM'boumba Cedric Madianga chan->busy = true; 588d8b46839SM'boumba Cedric Madianga 58990ec93cbSBenjamin Gaignard dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan); 590d8b46839SM'boumba Cedric Madianga } 591d8b46839SM'boumba Cedric Madianga 592d8b46839SM'boumba Cedric Madianga static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan) 593d8b46839SM'boumba Cedric Madianga { 594d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 595d8b46839SM'boumba Cedric Madianga struct stm32_dma_sg_req *sg_req; 596d8b46839SM'boumba Cedric Madianga u32 dma_scr, dma_sm0ar, dma_sm1ar, id; 597d8b46839SM'boumba Cedric Madianga 598d8b46839SM'boumba Cedric Madianga id = chan->id; 599d8b46839SM'boumba Cedric Madianga dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); 600d8b46839SM'boumba Cedric Madianga 601d8b46839SM'boumba Cedric Madianga if (dma_scr & STM32_DMA_SCR_DBM) { 602d8b46839SM'boumba Cedric Madianga if (chan->next_sg == chan->desc->num_sgs) 603d8b46839SM'boumba Cedric Madianga chan->next_sg = 0; 604d8b46839SM'boumba Cedric Madianga 605d8b46839SM'boumba Cedric Madianga sg_req = &chan->desc->sg_req[chan->next_sg]; 606d8b46839SM'boumba Cedric Madianga 607d8b46839SM'boumba Cedric Madianga if (dma_scr & STM32_DMA_SCR_CT) { 608d8b46839SM'boumba Cedric Madianga dma_sm0ar = sg_req->chan_reg.dma_sm0ar; 609d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar); 610d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n", 611d8b46839SM'boumba Cedric Madianga stm32_dma_read(dmadev, STM32_DMA_SM0AR(id))); 612d8b46839SM'boumba Cedric Madianga } else { 613d8b46839SM'boumba Cedric Madianga dma_sm1ar = sg_req->chan_reg.dma_sm1ar; 614d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar); 615d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n", 616d8b46839SM'boumba Cedric Madianga stm32_dma_read(dmadev, STM32_DMA_SM1AR(id))); 617d8b46839SM'boumba Cedric Madianga } 618d8b46839SM'boumba Cedric Madianga } 619d8b46839SM'boumba Cedric Madianga } 620d8b46839SM'boumba Cedric Madianga 621d8b46839SM'boumba Cedric Madianga static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan) 622d8b46839SM'boumba Cedric Madianga { 623d8b46839SM'boumba Cedric Madianga if (chan->desc) { 624d8b46839SM'boumba Cedric Madianga if (chan->desc->cyclic) { 625d8b46839SM'boumba Cedric Madianga vchan_cyclic_callback(&chan->desc->vdesc); 6262b12c558SM'boumba Cedric Madianga chan->next_sg++; 627d8b46839SM'boumba Cedric Madianga stm32_dma_configure_next_sg(chan); 628d8b46839SM'boumba Cedric Madianga } else { 629d8b46839SM'boumba Cedric Madianga chan->busy = false; 630d8b46839SM'boumba Cedric Madianga if (chan->next_sg == chan->desc->num_sgs) { 631d8b46839SM'boumba Cedric Madianga list_del(&chan->desc->vdesc.node); 632d8b46839SM'boumba Cedric Madianga vchan_cookie_complete(&chan->desc->vdesc); 633d8b46839SM'boumba Cedric Madianga chan->desc = NULL; 634d8b46839SM'boumba Cedric Madianga } 635d8b46839SM'boumba Cedric Madianga stm32_dma_start_transfer(chan); 636d8b46839SM'boumba Cedric Madianga } 637d8b46839SM'boumba Cedric Madianga } 638d8b46839SM'boumba Cedric Madianga } 639d8b46839SM'boumba Cedric Madianga 640d8b46839SM'boumba Cedric Madianga static irqreturn_t stm32_dma_chan_irq(int irq, void *devid) 641d8b46839SM'boumba Cedric Madianga { 642d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = devid; 643d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 644ca4c72c0SPierre-Yves MORDRET u32 status, scr, sfcr; 645d8b46839SM'boumba Cedric Madianga 646d8b46839SM'boumba Cedric Madianga spin_lock(&chan->vchan.lock); 647d8b46839SM'boumba Cedric Madianga 648d8b46839SM'boumba Cedric Madianga status = stm32_dma_irq_status(chan); 649d8b46839SM'boumba Cedric Madianga scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 650ca4c72c0SPierre-Yves MORDRET sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); 651d8b46839SM'boumba Cedric Madianga 652c2d86b1cSPierre Yves MORDRET if (status & STM32_DMA_TCI) { 653d8b46839SM'boumba Cedric Madianga stm32_dma_irq_clear(chan, STM32_DMA_TCI); 654c2d86b1cSPierre Yves MORDRET if (scr & STM32_DMA_SCR_TCIE) 655d8b46839SM'boumba Cedric Madianga stm32_dma_handle_chan_done(chan); 656c2d86b1cSPierre Yves MORDRET status &= ~STM32_DMA_TCI; 657c2d86b1cSPierre Yves MORDRET } 658c2d86b1cSPierre Yves MORDRET if (status & STM32_DMA_HTI) { 659c2d86b1cSPierre Yves MORDRET stm32_dma_irq_clear(chan, STM32_DMA_HTI); 660c2d86b1cSPierre Yves MORDRET status &= ~STM32_DMA_HTI; 661c2d86b1cSPierre Yves MORDRET } 662c2d86b1cSPierre Yves MORDRET if (status & STM32_DMA_FEI) { 663c2d86b1cSPierre Yves MORDRET stm32_dma_irq_clear(chan, STM32_DMA_FEI); 664c2d86b1cSPierre Yves MORDRET status &= ~STM32_DMA_FEI; 665ca4c72c0SPierre-Yves MORDRET if (sfcr & STM32_DMA_SFCR_FEIE) { 666c2d86b1cSPierre Yves MORDRET if (!(scr & STM32_DMA_SCR_EN)) 667c2d86b1cSPierre Yves MORDRET dev_err(chan2dev(chan), "FIFO Error\n"); 668c2d86b1cSPierre Yves MORDRET else 669c2d86b1cSPierre Yves MORDRET dev_dbg(chan2dev(chan), "FIFO over/underrun\n"); 670c2d86b1cSPierre Yves MORDRET } 671ca4c72c0SPierre-Yves MORDRET } 672c2d86b1cSPierre Yves MORDRET if (status) { 673d8b46839SM'boumba Cedric Madianga stm32_dma_irq_clear(chan, status); 674d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status); 675c2d86b1cSPierre Yves MORDRET if (!(scr & STM32_DMA_SCR_EN)) 676c2d86b1cSPierre Yves MORDRET dev_err(chan2dev(chan), "chan disabled by HW\n"); 677d8b46839SM'boumba Cedric Madianga } 678d8b46839SM'boumba Cedric Madianga 679d8b46839SM'boumba Cedric Madianga spin_unlock(&chan->vchan.lock); 680d8b46839SM'boumba Cedric Madianga 681d8b46839SM'boumba Cedric Madianga return IRQ_HANDLED; 682d8b46839SM'boumba Cedric Madianga } 683d8b46839SM'boumba Cedric Madianga 684d8b46839SM'boumba Cedric Madianga static void stm32_dma_issue_pending(struct dma_chan *c) 685d8b46839SM'boumba Cedric Madianga { 686d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 687d8b46839SM'boumba Cedric Madianga unsigned long flags; 688d8b46839SM'boumba Cedric Madianga 689d8b46839SM'boumba Cedric Madianga spin_lock_irqsave(&chan->vchan.lock, flags); 6908d1b76f0SM'boumba Cedric Madianga if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) { 69190ec93cbSBenjamin Gaignard dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan); 6928d1b76f0SM'boumba Cedric Madianga stm32_dma_start_transfer(chan); 693e57cb3b3SPierre Yves MORDRET 694d8b46839SM'boumba Cedric Madianga } 695d8b46839SM'boumba Cedric Madianga spin_unlock_irqrestore(&chan->vchan.lock, flags); 696d8b46839SM'boumba Cedric Madianga } 697d8b46839SM'boumba Cedric Madianga 698d8b46839SM'boumba Cedric Madianga static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan, 699d8b46839SM'boumba Cedric Madianga enum dma_transfer_direction direction, 700a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth *buswidth, 701a2b6103bSPierre Yves MORDRET u32 buf_len) 702d8b46839SM'boumba Cedric Madianga { 703d8b46839SM'boumba Cedric Madianga enum dma_slave_buswidth src_addr_width, dst_addr_width; 704d8b46839SM'boumba Cedric Madianga int src_bus_width, dst_bus_width; 705d8b46839SM'boumba Cedric Madianga int src_burst_size, dst_burst_size; 706a2b6103bSPierre Yves MORDRET u32 src_maxburst, dst_maxburst, src_best_burst, dst_best_burst; 707a2b6103bSPierre Yves MORDRET u32 dma_scr, threshold; 708d8b46839SM'boumba Cedric Madianga 709d8b46839SM'boumba Cedric Madianga src_addr_width = chan->dma_sconfig.src_addr_width; 710d8b46839SM'boumba Cedric Madianga dst_addr_width = chan->dma_sconfig.dst_addr_width; 711d8b46839SM'boumba Cedric Madianga src_maxburst = chan->dma_sconfig.src_maxburst; 712d8b46839SM'boumba Cedric Madianga dst_maxburst = chan->dma_sconfig.dst_maxburst; 713a2b6103bSPierre Yves MORDRET threshold = chan->threshold; 714d8b46839SM'boumba Cedric Madianga 715d8b46839SM'boumba Cedric Madianga switch (direction) { 716d8b46839SM'boumba Cedric Madianga case DMA_MEM_TO_DEV: 717a2b6103bSPierre Yves MORDRET /* Set device data size */ 718d8b46839SM'boumba Cedric Madianga dst_bus_width = stm32_dma_get_width(chan, dst_addr_width); 719d8b46839SM'boumba Cedric Madianga if (dst_bus_width < 0) 720d8b46839SM'boumba Cedric Madianga return dst_bus_width; 721d8b46839SM'boumba Cedric Madianga 722a2b6103bSPierre Yves MORDRET /* Set device burst size */ 723a2b6103bSPierre Yves MORDRET dst_best_burst = stm32_dma_get_best_burst(buf_len, 724a2b6103bSPierre Yves MORDRET dst_maxburst, 725a2b6103bSPierre Yves MORDRET threshold, 726a2b6103bSPierre Yves MORDRET dst_addr_width); 727a2b6103bSPierre Yves MORDRET 728a2b6103bSPierre Yves MORDRET dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst); 729d8b46839SM'boumba Cedric Madianga if (dst_burst_size < 0) 730d8b46839SM'boumba Cedric Madianga return dst_burst_size; 731d8b46839SM'boumba Cedric Madianga 732a2b6103bSPierre Yves MORDRET /* Set memory data size */ 733a2b6103bSPierre Yves MORDRET src_addr_width = stm32_dma_get_max_width(buf_len, threshold); 734a2b6103bSPierre Yves MORDRET chan->mem_width = src_addr_width; 735d8b46839SM'boumba Cedric Madianga src_bus_width = stm32_dma_get_width(chan, src_addr_width); 736d8b46839SM'boumba Cedric Madianga if (src_bus_width < 0) 737d8b46839SM'boumba Cedric Madianga return src_bus_width; 738d8b46839SM'boumba Cedric Madianga 739a2b6103bSPierre Yves MORDRET /* Set memory burst size */ 740a2b6103bSPierre Yves MORDRET src_maxburst = STM32_DMA_MAX_BURST; 741a2b6103bSPierre Yves MORDRET src_best_burst = stm32_dma_get_best_burst(buf_len, 742a2b6103bSPierre Yves MORDRET src_maxburst, 743a2b6103bSPierre Yves MORDRET threshold, 744a2b6103bSPierre Yves MORDRET src_addr_width); 745a2b6103bSPierre Yves MORDRET src_burst_size = stm32_dma_get_burst(chan, src_best_burst); 746d8b46839SM'boumba Cedric Madianga if (src_burst_size < 0) 747d8b46839SM'boumba Cedric Madianga return src_burst_size; 748d8b46839SM'boumba Cedric Madianga 749d8b46839SM'boumba Cedric Madianga dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_DEV) | 750d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PSIZE(dst_bus_width) | 751d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MSIZE(src_bus_width) | 752d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PBURST(dst_burst_size) | 753d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MBURST(src_burst_size); 754d8b46839SM'boumba Cedric Madianga 755a2b6103bSPierre Yves MORDRET /* Set FIFO threshold */ 756a2b6103bSPierre Yves MORDRET chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; 757a2b6103bSPierre Yves MORDRET chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold); 758a2b6103bSPierre Yves MORDRET 759a2b6103bSPierre Yves MORDRET /* Set peripheral address */ 760d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr; 761d8b46839SM'boumba Cedric Madianga *buswidth = dst_addr_width; 762d8b46839SM'boumba Cedric Madianga break; 763d8b46839SM'boumba Cedric Madianga 764d8b46839SM'boumba Cedric Madianga case DMA_DEV_TO_MEM: 765a2b6103bSPierre Yves MORDRET /* Set device data size */ 766d8b46839SM'boumba Cedric Madianga src_bus_width = stm32_dma_get_width(chan, src_addr_width); 767d8b46839SM'boumba Cedric Madianga if (src_bus_width < 0) 768d8b46839SM'boumba Cedric Madianga return src_bus_width; 769d8b46839SM'boumba Cedric Madianga 770a2b6103bSPierre Yves MORDRET /* Set device burst size */ 771a2b6103bSPierre Yves MORDRET src_best_burst = stm32_dma_get_best_burst(buf_len, 772a2b6103bSPierre Yves MORDRET src_maxburst, 773a2b6103bSPierre Yves MORDRET threshold, 774a2b6103bSPierre Yves MORDRET src_addr_width); 775a2b6103bSPierre Yves MORDRET chan->mem_burst = src_best_burst; 776a2b6103bSPierre Yves MORDRET src_burst_size = stm32_dma_get_burst(chan, src_best_burst); 777d8b46839SM'boumba Cedric Madianga if (src_burst_size < 0) 778d8b46839SM'boumba Cedric Madianga return src_burst_size; 779d8b46839SM'boumba Cedric Madianga 780a2b6103bSPierre Yves MORDRET /* Set memory data size */ 781a2b6103bSPierre Yves MORDRET dst_addr_width = stm32_dma_get_max_width(buf_len, threshold); 782a2b6103bSPierre Yves MORDRET chan->mem_width = dst_addr_width; 783d8b46839SM'boumba Cedric Madianga dst_bus_width = stm32_dma_get_width(chan, dst_addr_width); 784d8b46839SM'boumba Cedric Madianga if (dst_bus_width < 0) 785d8b46839SM'boumba Cedric Madianga return dst_bus_width; 786d8b46839SM'boumba Cedric Madianga 787a2b6103bSPierre Yves MORDRET /* Set memory burst size */ 788a2b6103bSPierre Yves MORDRET dst_maxburst = STM32_DMA_MAX_BURST; 789a2b6103bSPierre Yves MORDRET dst_best_burst = stm32_dma_get_best_burst(buf_len, 790a2b6103bSPierre Yves MORDRET dst_maxburst, 791a2b6103bSPierre Yves MORDRET threshold, 792a2b6103bSPierre Yves MORDRET dst_addr_width); 793a2b6103bSPierre Yves MORDRET chan->mem_burst = dst_best_burst; 794a2b6103bSPierre Yves MORDRET dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst); 795d8b46839SM'boumba Cedric Madianga if (dst_burst_size < 0) 796d8b46839SM'boumba Cedric Madianga return dst_burst_size; 797d8b46839SM'boumba Cedric Madianga 798d8b46839SM'boumba Cedric Madianga dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_DEV_TO_MEM) | 799d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PSIZE(src_bus_width) | 800d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MSIZE(dst_bus_width) | 801d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PBURST(src_burst_size) | 802d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MBURST(dst_burst_size); 803d8b46839SM'boumba Cedric Madianga 804a2b6103bSPierre Yves MORDRET /* Set FIFO threshold */ 805a2b6103bSPierre Yves MORDRET chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; 806a2b6103bSPierre Yves MORDRET chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(threshold); 807a2b6103bSPierre Yves MORDRET 808a2b6103bSPierre Yves MORDRET /* Set peripheral address */ 809d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr; 810d8b46839SM'boumba Cedric Madianga *buswidth = chan->dma_sconfig.src_addr_width; 811d8b46839SM'boumba Cedric Madianga break; 812d8b46839SM'boumba Cedric Madianga 813d8b46839SM'boumba Cedric Madianga default: 814d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Dma direction is not supported\n"); 815d8b46839SM'boumba Cedric Madianga return -EINVAL; 816d8b46839SM'boumba Cedric Madianga } 817d8b46839SM'boumba Cedric Madianga 818a2b6103bSPierre Yves MORDRET stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst); 819d8b46839SM'boumba Cedric Madianga 820a2b6103bSPierre Yves MORDRET /* Set DMA control register */ 821d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK | 822d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PSIZE_MASK | STM32_DMA_SCR_MSIZE_MASK | 823d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PBURST_MASK | STM32_DMA_SCR_MBURST_MASK); 824d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= dma_scr; 825d8b46839SM'boumba Cedric Madianga 826d8b46839SM'boumba Cedric Madianga return 0; 827d8b46839SM'boumba Cedric Madianga } 828d8b46839SM'boumba Cedric Madianga 829d8b46839SM'boumba Cedric Madianga static void stm32_dma_clear_reg(struct stm32_dma_chan_reg *regs) 830d8b46839SM'boumba Cedric Madianga { 831d8b46839SM'boumba Cedric Madianga memset(regs, 0, sizeof(struct stm32_dma_chan_reg)); 832d8b46839SM'boumba Cedric Madianga } 833d8b46839SM'boumba Cedric Madianga 834d8b46839SM'boumba Cedric Madianga static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg( 835d8b46839SM'boumba Cedric Madianga struct dma_chan *c, struct scatterlist *sgl, 836d8b46839SM'boumba Cedric Madianga u32 sg_len, enum dma_transfer_direction direction, 837d8b46839SM'boumba Cedric Madianga unsigned long flags, void *context) 838d8b46839SM'boumba Cedric Madianga { 839d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 840d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc; 841d8b46839SM'boumba Cedric Madianga struct scatterlist *sg; 842d8b46839SM'boumba Cedric Madianga enum dma_slave_buswidth buswidth; 843d8b46839SM'boumba Cedric Madianga u32 nb_data_items; 844d8b46839SM'boumba Cedric Madianga int i, ret; 845d8b46839SM'boumba Cedric Madianga 846d8b46839SM'boumba Cedric Madianga if (!chan->config_init) { 847d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "dma channel is not configured\n"); 848d8b46839SM'boumba Cedric Madianga return NULL; 849d8b46839SM'boumba Cedric Madianga } 850d8b46839SM'boumba Cedric Madianga 851d8b46839SM'boumba Cedric Madianga if (sg_len < 1) { 852d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len); 853d8b46839SM'boumba Cedric Madianga return NULL; 854d8b46839SM'boumba Cedric Madianga } 855d8b46839SM'boumba Cedric Madianga 856d8b46839SM'boumba Cedric Madianga desc = stm32_dma_alloc_desc(sg_len); 857d8b46839SM'boumba Cedric Madianga if (!desc) 858d8b46839SM'boumba Cedric Madianga return NULL; 859d8b46839SM'boumba Cedric Madianga 860d8b46839SM'boumba Cedric Madianga /* Set peripheral flow controller */ 861d8b46839SM'boumba Cedric Madianga if (chan->dma_sconfig.device_fc) 862d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL; 863d8b46839SM'boumba Cedric Madianga else 864d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; 865d8b46839SM'boumba Cedric Madianga 866d8b46839SM'boumba Cedric Madianga for_each_sg(sgl, sg, sg_len, i) { 867a2b6103bSPierre Yves MORDRET ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, 868a2b6103bSPierre Yves MORDRET sg_dma_len(sg)); 869a2b6103bSPierre Yves MORDRET if (ret < 0) 870a2b6103bSPierre Yves MORDRET goto err; 871a2b6103bSPierre Yves MORDRET 872d8b46839SM'boumba Cedric Madianga desc->sg_req[i].len = sg_dma_len(sg); 873d8b46839SM'boumba Cedric Madianga 874d8b46839SM'boumba Cedric Madianga nb_data_items = desc->sg_req[i].len / buswidth; 87580a76952SPierre Yves MORDRET if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) { 876d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "nb items not supported\n"); 877d8b46839SM'boumba Cedric Madianga goto err; 878d8b46839SM'boumba Cedric Madianga } 879d8b46839SM'boumba Cedric Madianga 880d8b46839SM'boumba Cedric Madianga stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); 881d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; 882d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; 883d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; 884d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg); 885d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg); 886d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items; 887d8b46839SM'boumba Cedric Madianga } 888d8b46839SM'boumba Cedric Madianga 889d8b46839SM'boumba Cedric Madianga desc->num_sgs = sg_len; 890d8b46839SM'boumba Cedric Madianga desc->cyclic = false; 891d8b46839SM'boumba Cedric Madianga 892d8b46839SM'boumba Cedric Madianga return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); 893d8b46839SM'boumba Cedric Madianga 894d8b46839SM'boumba Cedric Madianga err: 895d8b46839SM'boumba Cedric Madianga kfree(desc); 896d8b46839SM'boumba Cedric Madianga return NULL; 897d8b46839SM'boumba Cedric Madianga } 898d8b46839SM'boumba Cedric Madianga 899d8b46839SM'boumba Cedric Madianga static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic( 900d8b46839SM'boumba Cedric Madianga struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len, 901d8b46839SM'boumba Cedric Madianga size_t period_len, enum dma_transfer_direction direction, 902d8b46839SM'boumba Cedric Madianga unsigned long flags) 903d8b46839SM'boumba Cedric Madianga { 904d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 905d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc; 906d8b46839SM'boumba Cedric Madianga enum dma_slave_buswidth buswidth; 907d8b46839SM'boumba Cedric Madianga u32 num_periods, nb_data_items; 908d8b46839SM'boumba Cedric Madianga int i, ret; 909d8b46839SM'boumba Cedric Madianga 910d8b46839SM'boumba Cedric Madianga if (!buf_len || !period_len) { 911d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Invalid buffer/period len\n"); 912d8b46839SM'boumba Cedric Madianga return NULL; 913d8b46839SM'boumba Cedric Madianga } 914d8b46839SM'boumba Cedric Madianga 915d8b46839SM'boumba Cedric Madianga if (!chan->config_init) { 916d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "dma channel is not configured\n"); 917d8b46839SM'boumba Cedric Madianga return NULL; 918d8b46839SM'boumba Cedric Madianga } 919d8b46839SM'boumba Cedric Madianga 920d8b46839SM'boumba Cedric Madianga if (buf_len % period_len) { 921d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "buf_len not multiple of period_len\n"); 922d8b46839SM'boumba Cedric Madianga return NULL; 923d8b46839SM'boumba Cedric Madianga } 924d8b46839SM'boumba Cedric Madianga 925d8b46839SM'boumba Cedric Madianga /* 926d8b46839SM'boumba Cedric Madianga * We allow to take more number of requests till DMA is 927d8b46839SM'boumba Cedric Madianga * not started. The driver will loop over all requests. 928d8b46839SM'boumba Cedric Madianga * Once DMA is started then new requests can be queued only after 929d8b46839SM'boumba Cedric Madianga * terminating the DMA. 930d8b46839SM'boumba Cedric Madianga */ 931d8b46839SM'boumba Cedric Madianga if (chan->busy) { 932d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Request not allowed when dma busy\n"); 933d8b46839SM'boumba Cedric Madianga return NULL; 934d8b46839SM'boumba Cedric Madianga } 935d8b46839SM'boumba Cedric Madianga 936a2b6103bSPierre Yves MORDRET ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len); 937d8b46839SM'boumba Cedric Madianga if (ret < 0) 938d8b46839SM'boumba Cedric Madianga return NULL; 939d8b46839SM'boumba Cedric Madianga 940d8b46839SM'boumba Cedric Madianga nb_data_items = period_len / buswidth; 94180a76952SPierre Yves MORDRET if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) { 942d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "number of items not supported\n"); 943d8b46839SM'boumba Cedric Madianga return NULL; 944d8b46839SM'boumba Cedric Madianga } 945d8b46839SM'boumba Cedric Madianga 946d8b46839SM'boumba Cedric Madianga /* Enable Circular mode or double buffer mode */ 947d8b46839SM'boumba Cedric Madianga if (buf_len == period_len) 948d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC; 949d8b46839SM'boumba Cedric Madianga else 950d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM; 951d8b46839SM'boumba Cedric Madianga 952d8b46839SM'boumba Cedric Madianga /* Clear periph ctrl if client set it */ 953d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; 954d8b46839SM'boumba Cedric Madianga 955d8b46839SM'boumba Cedric Madianga num_periods = buf_len / period_len; 956d8b46839SM'boumba Cedric Madianga 957d8b46839SM'boumba Cedric Madianga desc = stm32_dma_alloc_desc(num_periods); 958d8b46839SM'boumba Cedric Madianga if (!desc) 959d8b46839SM'boumba Cedric Madianga return NULL; 960d8b46839SM'boumba Cedric Madianga 961d8b46839SM'boumba Cedric Madianga for (i = 0; i < num_periods; i++) { 962d8b46839SM'boumba Cedric Madianga desc->sg_req[i].len = period_len; 963d8b46839SM'boumba Cedric Madianga 964d8b46839SM'boumba Cedric Madianga stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); 965d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; 966d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; 967d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; 968d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr; 969d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr; 970d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items; 971d8b46839SM'boumba Cedric Madianga buf_addr += period_len; 972d8b46839SM'boumba Cedric Madianga } 973d8b46839SM'boumba Cedric Madianga 974d8b46839SM'boumba Cedric Madianga desc->num_sgs = num_periods; 975d8b46839SM'boumba Cedric Madianga desc->cyclic = true; 976d8b46839SM'boumba Cedric Madianga 977d8b46839SM'boumba Cedric Madianga return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); 978d8b46839SM'boumba Cedric Madianga } 979d8b46839SM'boumba Cedric Madianga 980d8b46839SM'boumba Cedric Madianga static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy( 981d8b46839SM'boumba Cedric Madianga struct dma_chan *c, dma_addr_t dest, 982d8b46839SM'boumba Cedric Madianga dma_addr_t src, size_t len, unsigned long flags) 983d8b46839SM'boumba Cedric Madianga { 984d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 985a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth max_width; 986d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc; 987d8b46839SM'boumba Cedric Madianga size_t xfer_count, offset; 988a2b6103bSPierre Yves MORDRET u32 num_sgs, best_burst, dma_burst, threshold; 989d8b46839SM'boumba Cedric Madianga int i; 990d8b46839SM'boumba Cedric Madianga 99180a76952SPierre Yves MORDRET num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS); 992d8b46839SM'boumba Cedric Madianga desc = stm32_dma_alloc_desc(num_sgs); 993d8b46839SM'boumba Cedric Madianga if (!desc) 994d8b46839SM'boumba Cedric Madianga return NULL; 995d8b46839SM'boumba Cedric Madianga 996a2b6103bSPierre Yves MORDRET threshold = chan->threshold; 997a2b6103bSPierre Yves MORDRET 998d8b46839SM'boumba Cedric Madianga for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) { 999d8b46839SM'boumba Cedric Madianga xfer_count = min_t(size_t, len - offset, 100080a76952SPierre Yves MORDRET STM32_DMA_ALIGNED_MAX_DATA_ITEMS); 1001d8b46839SM'boumba Cedric Madianga 1002a2b6103bSPierre Yves MORDRET /* Compute best burst size */ 1003a2b6103bSPierre Yves MORDRET max_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1004a2b6103bSPierre Yves MORDRET best_burst = stm32_dma_get_best_burst(len, STM32_DMA_MAX_BURST, 1005a2b6103bSPierre Yves MORDRET threshold, max_width); 1006a2b6103bSPierre Yves MORDRET dma_burst = stm32_dma_get_burst(chan, best_burst); 1007d8b46839SM'boumba Cedric Madianga 1008d8b46839SM'boumba Cedric Madianga stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); 1009d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_scr = 1010d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_MEM) | 1011a2b6103bSPierre Yves MORDRET STM32_DMA_SCR_PBURST(dma_burst) | 1012a2b6103bSPierre Yves MORDRET STM32_DMA_SCR_MBURST(dma_burst) | 1013d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MINC | 1014d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PINC | 1015d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_TCIE | 1016d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_TEIE; 1017a2b6103bSPierre Yves MORDRET desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; 1018a2b6103bSPierre Yves MORDRET desc->sg_req[i].chan_reg.dma_sfcr |= 1019a2b6103bSPierre Yves MORDRET STM32_DMA_SFCR_FTH(threshold); 1020d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_spar = src + offset; 1021d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset; 1022d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sndtr = xfer_count; 1023a2b6103bSPierre Yves MORDRET desc->sg_req[i].len = xfer_count; 1024d8b46839SM'boumba Cedric Madianga } 1025d8b46839SM'boumba Cedric Madianga 1026d8b46839SM'boumba Cedric Madianga desc->num_sgs = num_sgs; 1027d8b46839SM'boumba Cedric Madianga desc->cyclic = false; 1028d8b46839SM'boumba Cedric Madianga 1029d8b46839SM'boumba Cedric Madianga return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); 1030d8b46839SM'boumba Cedric Madianga } 1031d8b46839SM'boumba Cedric Madianga 10322b12c558SM'boumba Cedric Madianga static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan) 10332b12c558SM'boumba Cedric Madianga { 10342b12c558SM'boumba Cedric Madianga u32 dma_scr, width, ndtr; 10352b12c558SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 10362b12c558SM'boumba Cedric Madianga 10372b12c558SM'boumba Cedric Madianga dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 10382b12c558SM'boumba Cedric Madianga width = STM32_DMA_SCR_PSIZE_GET(dma_scr); 10392b12c558SM'boumba Cedric Madianga ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); 10402b12c558SM'boumba Cedric Madianga 10412b12c558SM'boumba Cedric Madianga return ndtr << width; 10422b12c558SM'boumba Cedric Madianga } 10432b12c558SM'boumba Cedric Madianga 10442a4885abSArnaud Pouliquen /** 10452a4885abSArnaud Pouliquen * stm32_dma_is_current_sg - check that expected sg_req is currently transferred 10462a4885abSArnaud Pouliquen * @chan: dma channel 10472a4885abSArnaud Pouliquen * 10482a4885abSArnaud Pouliquen * This function called when IRQ are disable, checks that the hardware has not 10492a4885abSArnaud Pouliquen * switched on the next transfer in double buffer mode. The test is done by 10502a4885abSArnaud Pouliquen * comparing the next_sg memory address with the hardware related register 10512a4885abSArnaud Pouliquen * (based on CT bit value). 10522a4885abSArnaud Pouliquen * 10532a4885abSArnaud Pouliquen * Returns true if expected current transfer is still running or double 10542a4885abSArnaud Pouliquen * buffer mode is not activated. 10552a4885abSArnaud Pouliquen */ 10562a4885abSArnaud Pouliquen static bool stm32_dma_is_current_sg(struct stm32_dma_chan *chan) 10572a4885abSArnaud Pouliquen { 10582a4885abSArnaud Pouliquen struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 10592a4885abSArnaud Pouliquen struct stm32_dma_sg_req *sg_req; 10602a4885abSArnaud Pouliquen u32 dma_scr, dma_smar, id; 10612a4885abSArnaud Pouliquen 10622a4885abSArnaud Pouliquen id = chan->id; 10632a4885abSArnaud Pouliquen dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); 10642a4885abSArnaud Pouliquen 10652a4885abSArnaud Pouliquen if (!(dma_scr & STM32_DMA_SCR_DBM)) 10662a4885abSArnaud Pouliquen return true; 10672a4885abSArnaud Pouliquen 10682a4885abSArnaud Pouliquen sg_req = &chan->desc->sg_req[chan->next_sg]; 10692a4885abSArnaud Pouliquen 10702a4885abSArnaud Pouliquen if (dma_scr & STM32_DMA_SCR_CT) { 10712a4885abSArnaud Pouliquen dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)); 10722a4885abSArnaud Pouliquen return (dma_smar == sg_req->chan_reg.dma_sm0ar); 10732a4885abSArnaud Pouliquen } 10742a4885abSArnaud Pouliquen 10752a4885abSArnaud Pouliquen dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)); 10762a4885abSArnaud Pouliquen 10772a4885abSArnaud Pouliquen return (dma_smar == sg_req->chan_reg.dma_sm1ar); 10782a4885abSArnaud Pouliquen } 10792a4885abSArnaud Pouliquen 1080d8b46839SM'boumba Cedric Madianga static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan, 1081d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc, 1082d8b46839SM'boumba Cedric Madianga u32 next_sg) 1083d8b46839SM'boumba Cedric Madianga { 1084a2b6103bSPierre Yves MORDRET u32 modulo, burst_size; 10852a4885abSArnaud Pouliquen u32 residue; 10862a4885abSArnaud Pouliquen u32 n_sg = next_sg; 10872a4885abSArnaud Pouliquen struct stm32_dma_sg_req *sg_req = &chan->desc->sg_req[chan->next_sg]; 1088d8b46839SM'boumba Cedric Madianga int i; 1089d8b46839SM'boumba Cedric Madianga 10902b12c558SM'boumba Cedric Madianga /* 10912a4885abSArnaud Pouliquen * Calculate the residue means compute the descriptors 10922a4885abSArnaud Pouliquen * information: 10932a4885abSArnaud Pouliquen * - the sg_req currently transferred 10942a4885abSArnaud Pouliquen * - the Hardware remaining position in this sg (NDTR bits field). 10952a4885abSArnaud Pouliquen * 10962a4885abSArnaud Pouliquen * A race condition may occur if DMA is running in cyclic or double 10972a4885abSArnaud Pouliquen * buffer mode, since the DMA register are automatically reloaded at end 10982a4885abSArnaud Pouliquen * of period transfer. The hardware may have switched to the next 10992a4885abSArnaud Pouliquen * transfer (CT bit updated) just before the position (SxNDTR reg) is 11002a4885abSArnaud Pouliquen * read. 11012a4885abSArnaud Pouliquen * In this case the SxNDTR reg could (or not) correspond to the new 11022a4885abSArnaud Pouliquen * transfer position, and not the expected one. 11032a4885abSArnaud Pouliquen * The strategy implemented in the stm32 driver is to: 11042a4885abSArnaud Pouliquen * - read the SxNDTR register 11052a4885abSArnaud Pouliquen * - crosscheck that hardware is still in current transfer. 11062a4885abSArnaud Pouliquen * In case of switch, we can assume that the DMA is at the beginning of 11072a4885abSArnaud Pouliquen * the next transfer. So we approximate the residue in consequence, by 11082a4885abSArnaud Pouliquen * pointing on the beginning of next transfer. 11092a4885abSArnaud Pouliquen * 11102a4885abSArnaud Pouliquen * This race condition doesn't apply for none cyclic mode, as double 11112a4885abSArnaud Pouliquen * buffer is not used. In such situation registers are updated by the 11122a4885abSArnaud Pouliquen * software. 11132b12c558SM'boumba Cedric Madianga */ 11142a4885abSArnaud Pouliquen 1115a2b6103bSPierre Yves MORDRET residue = stm32_dma_get_remaining_bytes(chan); 11162a4885abSArnaud Pouliquen 11172a4885abSArnaud Pouliquen if (!stm32_dma_is_current_sg(chan)) { 11182a4885abSArnaud Pouliquen n_sg++; 11192a4885abSArnaud Pouliquen if (n_sg == chan->desc->num_sgs) 11202a4885abSArnaud Pouliquen n_sg = 0; 11212a4885abSArnaud Pouliquen residue = sg_req->len; 1122a2b6103bSPierre Yves MORDRET } 1123d8b46839SM'boumba Cedric Madianga 11242b12c558SM'boumba Cedric Madianga /* 11252a4885abSArnaud Pouliquen * In cyclic mode, for the last period, residue = remaining bytes 11262a4885abSArnaud Pouliquen * from NDTR, 11272a4885abSArnaud Pouliquen * else for all other periods in cyclic mode, and in sg mode, 11282a4885abSArnaud Pouliquen * residue = remaining bytes from NDTR + remaining 11292a4885abSArnaud Pouliquen * periods/sg to be transferred 11302b12c558SM'boumba Cedric Madianga */ 11312a4885abSArnaud Pouliquen if (!chan->desc->cyclic || n_sg != 0) 11322a4885abSArnaud Pouliquen for (i = n_sg; i < desc->num_sgs; i++) 1133d8b46839SM'boumba Cedric Madianga residue += desc->sg_req[i].len; 1134d8b46839SM'boumba Cedric Madianga 1135a2b6103bSPierre Yves MORDRET if (!chan->mem_burst) 1136a2b6103bSPierre Yves MORDRET return residue; 1137a2b6103bSPierre Yves MORDRET 1138a2b6103bSPierre Yves MORDRET burst_size = chan->mem_burst * chan->mem_width; 1139a2b6103bSPierre Yves MORDRET modulo = residue % burst_size; 1140a2b6103bSPierre Yves MORDRET if (modulo) 1141a2b6103bSPierre Yves MORDRET residue = residue - modulo + burst_size; 1142a2b6103bSPierre Yves MORDRET 1143d8b46839SM'boumba Cedric Madianga return residue; 1144d8b46839SM'boumba Cedric Madianga } 1145d8b46839SM'boumba Cedric Madianga 1146d8b46839SM'boumba Cedric Madianga static enum dma_status stm32_dma_tx_status(struct dma_chan *c, 1147d8b46839SM'boumba Cedric Madianga dma_cookie_t cookie, 1148d8b46839SM'boumba Cedric Madianga struct dma_tx_state *state) 1149d8b46839SM'boumba Cedric Madianga { 1150d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1151d8b46839SM'boumba Cedric Madianga struct virt_dma_desc *vdesc; 1152d8b46839SM'boumba Cedric Madianga enum dma_status status; 1153d8b46839SM'boumba Cedric Madianga unsigned long flags; 115457b5a321SM'boumba Cedric Madianga u32 residue = 0; 1155d8b46839SM'boumba Cedric Madianga 1156d8b46839SM'boumba Cedric Madianga status = dma_cookie_status(c, cookie, state); 1157249d5531SPierre Yves MORDRET if (status == DMA_COMPLETE || !state) 1158d8b46839SM'boumba Cedric Madianga return status; 1159d8b46839SM'boumba Cedric Madianga 1160d8b46839SM'boumba Cedric Madianga spin_lock_irqsave(&chan->vchan.lock, flags); 1161d8b46839SM'boumba Cedric Madianga vdesc = vchan_find_desc(&chan->vchan, cookie); 116257b5a321SM'boumba Cedric Madianga if (chan->desc && cookie == chan->desc->vdesc.tx.cookie) 1163d8b46839SM'boumba Cedric Madianga residue = stm32_dma_desc_residue(chan, chan->desc, 1164d8b46839SM'boumba Cedric Madianga chan->next_sg); 116557b5a321SM'boumba Cedric Madianga else if (vdesc) 1166d8b46839SM'boumba Cedric Madianga residue = stm32_dma_desc_residue(chan, 1167d8b46839SM'boumba Cedric Madianga to_stm32_dma_desc(vdesc), 0); 1168d8b46839SM'boumba Cedric Madianga dma_set_residue(state, residue); 1169d8b46839SM'boumba Cedric Madianga 1170d8b46839SM'boumba Cedric Madianga spin_unlock_irqrestore(&chan->vchan.lock, flags); 1171d8b46839SM'boumba Cedric Madianga 1172d8b46839SM'boumba Cedric Madianga return status; 1173d8b46839SM'boumba Cedric Madianga } 1174d8b46839SM'boumba Cedric Madianga 1175d8b46839SM'boumba Cedric Madianga static int stm32_dma_alloc_chan_resources(struct dma_chan *c) 1176d8b46839SM'boumba Cedric Madianga { 1177d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1178d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 1179d8b46839SM'boumba Cedric Madianga int ret; 1180d8b46839SM'boumba Cedric Madianga 1181d8b46839SM'boumba Cedric Madianga chan->config_init = false; 118248bc73baSPierre-Yves MORDRET 118348bc73baSPierre-Yves MORDRET ret = pm_runtime_get_sync(dmadev->ddev.dev); 118448bc73baSPierre-Yves MORDRET if (ret < 0) 1185d8b46839SM'boumba Cedric Madianga return ret; 1186d8b46839SM'boumba Cedric Madianga 1187d8b46839SM'boumba Cedric Madianga ret = stm32_dma_disable_chan(chan); 1188d8b46839SM'boumba Cedric Madianga if (ret < 0) 118948bc73baSPierre-Yves MORDRET pm_runtime_put(dmadev->ddev.dev); 1190d8b46839SM'boumba Cedric Madianga 1191d8b46839SM'boumba Cedric Madianga return ret; 1192d8b46839SM'boumba Cedric Madianga } 1193d8b46839SM'boumba Cedric Madianga 1194d8b46839SM'boumba Cedric Madianga static void stm32_dma_free_chan_resources(struct dma_chan *c) 1195d8b46839SM'boumba Cedric Madianga { 1196d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1197d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 1198d8b46839SM'boumba Cedric Madianga unsigned long flags; 1199d8b46839SM'boumba Cedric Madianga 1200d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id); 1201d8b46839SM'boumba Cedric Madianga 1202d8b46839SM'boumba Cedric Madianga if (chan->busy) { 1203d8b46839SM'boumba Cedric Madianga spin_lock_irqsave(&chan->vchan.lock, flags); 1204d8b46839SM'boumba Cedric Madianga stm32_dma_stop(chan); 1205d8b46839SM'boumba Cedric Madianga chan->desc = NULL; 1206d8b46839SM'boumba Cedric Madianga spin_unlock_irqrestore(&chan->vchan.lock, flags); 1207d8b46839SM'boumba Cedric Madianga } 1208d8b46839SM'boumba Cedric Madianga 120948bc73baSPierre-Yves MORDRET pm_runtime_put(dmadev->ddev.dev); 1210d8b46839SM'boumba Cedric Madianga 1211d8b46839SM'boumba Cedric Madianga vchan_free_chan_resources(to_virt_chan(c)); 1212d8b46839SM'boumba Cedric Madianga } 1213d8b46839SM'boumba Cedric Madianga 1214d8b46839SM'boumba Cedric Madianga static void stm32_dma_desc_free(struct virt_dma_desc *vdesc) 1215d8b46839SM'boumba Cedric Madianga { 1216d8b46839SM'boumba Cedric Madianga kfree(container_of(vdesc, struct stm32_dma_desc, vdesc)); 1217d8b46839SM'boumba Cedric Madianga } 1218d8b46839SM'boumba Cedric Madianga 1219e97adb49SVinod Koul static void stm32_dma_set_config(struct stm32_dma_chan *chan, 1220d8b46839SM'boumba Cedric Madianga struct stm32_dma_cfg *cfg) 1221d8b46839SM'boumba Cedric Madianga { 1222d8b46839SM'boumba Cedric Madianga stm32_dma_clear_reg(&chan->chan_reg); 1223d8b46839SM'boumba Cedric Madianga 1224d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK; 1225d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line); 1226d8b46839SM'boumba Cedric Madianga 1227d8b46839SM'boumba Cedric Madianga /* Enable Interrupts */ 1228d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE; 1229d8b46839SM'boumba Cedric Madianga 1230951f44cbSPierre Yves MORDRET chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features); 1231d8b46839SM'boumba Cedric Madianga } 1232d8b46839SM'boumba Cedric Madianga 1233d8b46839SM'boumba Cedric Madianga static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec, 1234d8b46839SM'boumba Cedric Madianga struct of_dma *ofdma) 1235d8b46839SM'boumba Cedric Madianga { 1236d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = ofdma->of_dma_data; 12375df4eb45SM'boumba Cedric Madianga struct device *dev = dmadev->ddev.dev; 1238d8b46839SM'boumba Cedric Madianga struct stm32_dma_cfg cfg; 1239d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan; 1240d8b46839SM'boumba Cedric Madianga struct dma_chan *c; 1241d8b46839SM'boumba Cedric Madianga 12425df4eb45SM'boumba Cedric Madianga if (dma_spec->args_count < 4) { 12435df4eb45SM'boumba Cedric Madianga dev_err(dev, "Bad number of cells\n"); 1244d8b46839SM'boumba Cedric Madianga return NULL; 12455df4eb45SM'boumba Cedric Madianga } 1246d8b46839SM'boumba Cedric Madianga 1247d8b46839SM'boumba Cedric Madianga cfg.channel_id = dma_spec->args[0]; 1248d8b46839SM'boumba Cedric Madianga cfg.request_line = dma_spec->args[1]; 1249d8b46839SM'boumba Cedric Madianga cfg.stream_config = dma_spec->args[2]; 1250951f44cbSPierre Yves MORDRET cfg.features = dma_spec->args[3]; 1251d8b46839SM'boumba Cedric Madianga 1252249d5531SPierre Yves MORDRET if (cfg.channel_id >= STM32_DMA_MAX_CHANNELS || 1253249d5531SPierre Yves MORDRET cfg.request_line >= STM32_DMA_MAX_REQUEST_ID) { 12545df4eb45SM'boumba Cedric Madianga dev_err(dev, "Bad channel and/or request id\n"); 1255d8b46839SM'boumba Cedric Madianga return NULL; 12565df4eb45SM'boumba Cedric Madianga } 1257d8b46839SM'boumba Cedric Madianga 1258d8b46839SM'boumba Cedric Madianga chan = &dmadev->chan[cfg.channel_id]; 1259d8b46839SM'boumba Cedric Madianga 1260d8b46839SM'boumba Cedric Madianga c = dma_get_slave_channel(&chan->vchan.chan); 12615df4eb45SM'boumba Cedric Madianga if (!c) { 1262041cf7e0SColin Ian King dev_err(dev, "No more channels available\n"); 12635df4eb45SM'boumba Cedric Madianga return NULL; 12645df4eb45SM'boumba Cedric Madianga } 12655df4eb45SM'boumba Cedric Madianga 1266d8b46839SM'boumba Cedric Madianga stm32_dma_set_config(chan, &cfg); 1267d8b46839SM'boumba Cedric Madianga 1268d8b46839SM'boumba Cedric Madianga return c; 1269d8b46839SM'boumba Cedric Madianga } 1270d8b46839SM'boumba Cedric Madianga 1271d8b46839SM'boumba Cedric Madianga static const struct of_device_id stm32_dma_of_match[] = { 1272d8b46839SM'boumba Cedric Madianga { .compatible = "st,stm32-dma", }, 1273d8b46839SM'boumba Cedric Madianga { /* sentinel */ }, 1274d8b46839SM'boumba Cedric Madianga }; 1275d8b46839SM'boumba Cedric Madianga MODULE_DEVICE_TABLE(of, stm32_dma_of_match); 1276d8b46839SM'boumba Cedric Madianga 1277d8b46839SM'boumba Cedric Madianga static int stm32_dma_probe(struct platform_device *pdev) 1278d8b46839SM'boumba Cedric Madianga { 1279d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan; 1280d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev; 1281d8b46839SM'boumba Cedric Madianga struct dma_device *dd; 1282d8b46839SM'boumba Cedric Madianga const struct of_device_id *match; 1283d8b46839SM'boumba Cedric Madianga struct resource *res; 1284d8b46839SM'boumba Cedric Madianga int i, ret; 1285d8b46839SM'boumba Cedric Madianga 1286d8b46839SM'boumba Cedric Madianga match = of_match_device(stm32_dma_of_match, &pdev->dev); 1287d8b46839SM'boumba Cedric Madianga if (!match) { 1288d8b46839SM'boumba Cedric Madianga dev_err(&pdev->dev, "Error: No device match found\n"); 1289d8b46839SM'boumba Cedric Madianga return -ENODEV; 1290d8b46839SM'boumba Cedric Madianga } 1291d8b46839SM'boumba Cedric Madianga 1292d8b46839SM'boumba Cedric Madianga dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL); 1293d8b46839SM'boumba Cedric Madianga if (!dmadev) 1294d8b46839SM'boumba Cedric Madianga return -ENOMEM; 1295d8b46839SM'boumba Cedric Madianga 1296d8b46839SM'boumba Cedric Madianga dd = &dmadev->ddev; 1297d8b46839SM'boumba Cedric Madianga 1298d8b46839SM'boumba Cedric Madianga res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1299d8b46839SM'boumba Cedric Madianga dmadev->base = devm_ioremap_resource(&pdev->dev, res); 1300d8b46839SM'boumba Cedric Madianga if (IS_ERR(dmadev->base)) 1301d8b46839SM'boumba Cedric Madianga return PTR_ERR(dmadev->base); 1302d8b46839SM'boumba Cedric Madianga 1303d8b46839SM'boumba Cedric Madianga dmadev->clk = devm_clk_get(&pdev->dev, NULL); 1304d8b46839SM'boumba Cedric Madianga if (IS_ERR(dmadev->clk)) { 1305d8b46839SM'boumba Cedric Madianga dev_err(&pdev->dev, "Error: Missing controller clock\n"); 1306d8b46839SM'boumba Cedric Madianga return PTR_ERR(dmadev->clk); 1307d8b46839SM'boumba Cedric Madianga } 1308d8b46839SM'boumba Cedric Madianga 130948bc73baSPierre-Yves MORDRET ret = clk_prepare_enable(dmadev->clk); 131048bc73baSPierre-Yves MORDRET if (ret < 0) { 131148bc73baSPierre-Yves MORDRET dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret); 131248bc73baSPierre-Yves MORDRET return ret; 131348bc73baSPierre-Yves MORDRET } 131448bc73baSPierre-Yves MORDRET 1315d8b46839SM'boumba Cedric Madianga dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node, 1316d8b46839SM'boumba Cedric Madianga "st,mem2mem"); 1317d8b46839SM'boumba Cedric Madianga 1318d8b46839SM'boumba Cedric Madianga dmadev->rst = devm_reset_control_get(&pdev->dev, NULL); 1319d8b46839SM'boumba Cedric Madianga if (!IS_ERR(dmadev->rst)) { 1320d8b46839SM'boumba Cedric Madianga reset_control_assert(dmadev->rst); 1321d8b46839SM'boumba Cedric Madianga udelay(2); 1322d8b46839SM'boumba Cedric Madianga reset_control_deassert(dmadev->rst); 1323d8b46839SM'boumba Cedric Madianga } 1324d8b46839SM'boumba Cedric Madianga 1325d8b46839SM'boumba Cedric Madianga dma_cap_set(DMA_SLAVE, dd->cap_mask); 1326d8b46839SM'boumba Cedric Madianga dma_cap_set(DMA_PRIVATE, dd->cap_mask); 1327d8b46839SM'boumba Cedric Madianga dma_cap_set(DMA_CYCLIC, dd->cap_mask); 1328d8b46839SM'boumba Cedric Madianga dd->device_alloc_chan_resources = stm32_dma_alloc_chan_resources; 1329d8b46839SM'boumba Cedric Madianga dd->device_free_chan_resources = stm32_dma_free_chan_resources; 1330d8b46839SM'boumba Cedric Madianga dd->device_tx_status = stm32_dma_tx_status; 1331d8b46839SM'boumba Cedric Madianga dd->device_issue_pending = stm32_dma_issue_pending; 1332d8b46839SM'boumba Cedric Madianga dd->device_prep_slave_sg = stm32_dma_prep_slave_sg; 1333d8b46839SM'boumba Cedric Madianga dd->device_prep_dma_cyclic = stm32_dma_prep_dma_cyclic; 1334d8b46839SM'boumba Cedric Madianga dd->device_config = stm32_dma_slave_config; 1335d8b46839SM'boumba Cedric Madianga dd->device_terminate_all = stm32_dma_terminate_all; 1336dc808675SM'boumba Cedric Madianga dd->device_synchronize = stm32_dma_synchronize; 1337d8b46839SM'boumba Cedric Madianga dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1338d8b46839SM'boumba Cedric Madianga BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1339d8b46839SM'boumba Cedric Madianga BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 1340d8b46839SM'boumba Cedric Madianga dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1341d8b46839SM'boumba Cedric Madianga BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1342d8b46839SM'boumba Cedric Madianga BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 1343d8b46839SM'boumba Cedric Madianga dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 1344d8b46839SM'boumba Cedric Madianga dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 1345276b0046SM'boumba Cedric Madianga dd->max_burst = STM32_DMA_MAX_BURST; 1346d8b46839SM'boumba Cedric Madianga dd->dev = &pdev->dev; 1347d8b46839SM'boumba Cedric Madianga INIT_LIST_HEAD(&dd->channels); 1348d8b46839SM'boumba Cedric Madianga 1349d8b46839SM'boumba Cedric Madianga if (dmadev->mem2mem) { 1350d8b46839SM'boumba Cedric Madianga dma_cap_set(DMA_MEMCPY, dd->cap_mask); 1351d8b46839SM'boumba Cedric Madianga dd->device_prep_dma_memcpy = stm32_dma_prep_dma_memcpy; 1352d8b46839SM'boumba Cedric Madianga dd->directions |= BIT(DMA_MEM_TO_MEM); 1353d8b46839SM'boumba Cedric Madianga } 1354d8b46839SM'boumba Cedric Madianga 1355d8b46839SM'boumba Cedric Madianga for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) { 1356d8b46839SM'boumba Cedric Madianga chan = &dmadev->chan[i]; 1357d8b46839SM'boumba Cedric Madianga chan->id = i; 1358d8b46839SM'boumba Cedric Madianga chan->vchan.desc_free = stm32_dma_desc_free; 1359d8b46839SM'boumba Cedric Madianga vchan_init(&chan->vchan, dd); 1360d8b46839SM'boumba Cedric Madianga } 1361d8b46839SM'boumba Cedric Madianga 1362d8b46839SM'boumba Cedric Madianga ret = dma_async_device_register(dd); 1363d8b46839SM'boumba Cedric Madianga if (ret) 136448bc73baSPierre-Yves MORDRET goto clk_free; 1365d8b46839SM'boumba Cedric Madianga 1366d8b46839SM'boumba Cedric Madianga for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) { 1367d8b46839SM'boumba Cedric Madianga chan = &dmadev->chan[i]; 1368f4fd2ec0SFabien Dessenne chan->irq = platform_get_irq(pdev, i); 1369c6504be5SVinod Koul ret = platform_get_irq(pdev, i); 1370c6504be5SVinod Koul if (ret < 0) { 1371f4fd2ec0SFabien Dessenne if (ret != -EPROBE_DEFER) 1372f4fd2ec0SFabien Dessenne dev_err(&pdev->dev, 1373f4fd2ec0SFabien Dessenne "No irq resource for chan %d\n", i); 1374d8b46839SM'boumba Cedric Madianga goto err_unregister; 1375d8b46839SM'boumba Cedric Madianga } 1376c6504be5SVinod Koul chan->irq = ret; 1377c6504be5SVinod Koul 1378d8b46839SM'boumba Cedric Madianga ret = devm_request_irq(&pdev->dev, chan->irq, 1379d8b46839SM'boumba Cedric Madianga stm32_dma_chan_irq, 0, 1380d8b46839SM'boumba Cedric Madianga dev_name(chan2dev(chan)), chan); 1381d8b46839SM'boumba Cedric Madianga if (ret) { 1382d8b46839SM'boumba Cedric Madianga dev_err(&pdev->dev, 1383d8b46839SM'boumba Cedric Madianga "request_irq failed with err %d channel %d\n", 1384d8b46839SM'boumba Cedric Madianga ret, i); 1385d8b46839SM'boumba Cedric Madianga goto err_unregister; 1386d8b46839SM'boumba Cedric Madianga } 1387d8b46839SM'boumba Cedric Madianga } 1388d8b46839SM'boumba Cedric Madianga 1389d8b46839SM'boumba Cedric Madianga ret = of_dma_controller_register(pdev->dev.of_node, 1390d8b46839SM'boumba Cedric Madianga stm32_dma_of_xlate, dmadev); 1391d8b46839SM'boumba Cedric Madianga if (ret < 0) { 1392d8b46839SM'boumba Cedric Madianga dev_err(&pdev->dev, 1393d8b46839SM'boumba Cedric Madianga "STM32 DMA DMA OF registration failed %d\n", ret); 1394d8b46839SM'boumba Cedric Madianga goto err_unregister; 1395d8b46839SM'boumba Cedric Madianga } 1396d8b46839SM'boumba Cedric Madianga 1397d8b46839SM'boumba Cedric Madianga platform_set_drvdata(pdev, dmadev); 1398d8b46839SM'boumba Cedric Madianga 139948bc73baSPierre-Yves MORDRET pm_runtime_set_active(&pdev->dev); 140048bc73baSPierre-Yves MORDRET pm_runtime_enable(&pdev->dev); 140148bc73baSPierre-Yves MORDRET pm_runtime_get_noresume(&pdev->dev); 140248bc73baSPierre-Yves MORDRET pm_runtime_put(&pdev->dev); 140348bc73baSPierre-Yves MORDRET 1404d8b46839SM'boumba Cedric Madianga dev_info(&pdev->dev, "STM32 DMA driver registered\n"); 1405d8b46839SM'boumba Cedric Madianga 1406d8b46839SM'boumba Cedric Madianga return 0; 1407d8b46839SM'boumba Cedric Madianga 1408d8b46839SM'boumba Cedric Madianga err_unregister: 1409d8b46839SM'boumba Cedric Madianga dma_async_device_unregister(dd); 141048bc73baSPierre-Yves MORDRET clk_free: 141148bc73baSPierre-Yves MORDRET clk_disable_unprepare(dmadev->clk); 1412d8b46839SM'boumba Cedric Madianga 1413d8b46839SM'boumba Cedric Madianga return ret; 1414d8b46839SM'boumba Cedric Madianga } 1415d8b46839SM'boumba Cedric Madianga 141648bc73baSPierre-Yves MORDRET #ifdef CONFIG_PM 141748bc73baSPierre-Yves MORDRET static int stm32_dma_runtime_suspend(struct device *dev) 141848bc73baSPierre-Yves MORDRET { 141948bc73baSPierre-Yves MORDRET struct stm32_dma_device *dmadev = dev_get_drvdata(dev); 142048bc73baSPierre-Yves MORDRET 142148bc73baSPierre-Yves MORDRET clk_disable_unprepare(dmadev->clk); 142248bc73baSPierre-Yves MORDRET 142348bc73baSPierre-Yves MORDRET return 0; 142448bc73baSPierre-Yves MORDRET } 142548bc73baSPierre-Yves MORDRET 142648bc73baSPierre-Yves MORDRET static int stm32_dma_runtime_resume(struct device *dev) 142748bc73baSPierre-Yves MORDRET { 142848bc73baSPierre-Yves MORDRET struct stm32_dma_device *dmadev = dev_get_drvdata(dev); 142948bc73baSPierre-Yves MORDRET int ret; 143048bc73baSPierre-Yves MORDRET 143148bc73baSPierre-Yves MORDRET ret = clk_prepare_enable(dmadev->clk); 143248bc73baSPierre-Yves MORDRET if (ret) { 143348bc73baSPierre-Yves MORDRET dev_err(dev, "failed to prepare_enable clock\n"); 143448bc73baSPierre-Yves MORDRET return ret; 143548bc73baSPierre-Yves MORDRET } 143648bc73baSPierre-Yves MORDRET 143748bc73baSPierre-Yves MORDRET return 0; 143848bc73baSPierre-Yves MORDRET } 143948bc73baSPierre-Yves MORDRET #endif 144048bc73baSPierre-Yves MORDRET 144148bc73baSPierre-Yves MORDRET static const struct dev_pm_ops stm32_dma_pm_ops = { 144248bc73baSPierre-Yves MORDRET SET_RUNTIME_PM_OPS(stm32_dma_runtime_suspend, 144348bc73baSPierre-Yves MORDRET stm32_dma_runtime_resume, NULL) 144448bc73baSPierre-Yves MORDRET }; 144548bc73baSPierre-Yves MORDRET 1446d8b46839SM'boumba Cedric Madianga static struct platform_driver stm32_dma_driver = { 1447d8b46839SM'boumba Cedric Madianga .driver = { 1448d8b46839SM'boumba Cedric Madianga .name = "stm32-dma", 1449d8b46839SM'boumba Cedric Madianga .of_match_table = stm32_dma_of_match, 145048bc73baSPierre-Yves MORDRET .pm = &stm32_dma_pm_ops, 1451d8b46839SM'boumba Cedric Madianga }, 1452d8b46839SM'boumba Cedric Madianga }; 1453d8b46839SM'boumba Cedric Madianga 1454d8b46839SM'boumba Cedric Madianga static int __init stm32_dma_init(void) 1455d8b46839SM'boumba Cedric Madianga { 1456d8b46839SM'boumba Cedric Madianga return platform_driver_probe(&stm32_dma_driver, stm32_dma_probe); 1457d8b46839SM'boumba Cedric Madianga } 1458d8b46839SM'boumba Cedric Madianga subsys_initcall(stm32_dma_init); 1459