1af873fceSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2d8b46839SM'boumba Cedric Madianga /* 3d8b46839SM'boumba Cedric Madianga * Driver for STM32 DMA controller 4d8b46839SM'boumba Cedric Madianga * 5d8b46839SM'boumba Cedric Madianga * Inspired by dma-jz4740.c and tegra20-apb-dma.c 6d8b46839SM'boumba Cedric Madianga * 7d8b46839SM'boumba Cedric Madianga * Copyright (C) M'boumba Cedric Madianga 2015 8d8b46839SM'boumba Cedric Madianga * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 9a2b6103bSPierre Yves MORDRET * Pierre-Yves Mordret <pierre-yves.mordret@st.com> 10d8b46839SM'boumba Cedric Madianga */ 11d8b46839SM'boumba Cedric Madianga 12d8b46839SM'boumba Cedric Madianga #include <linux/clk.h> 13d8b46839SM'boumba Cedric Madianga #include <linux/delay.h> 14d8b46839SM'boumba Cedric Madianga #include <linux/dmaengine.h> 15d8b46839SM'boumba Cedric Madianga #include <linux/dma-mapping.h> 16d8b46839SM'boumba Cedric Madianga #include <linux/err.h> 17d8b46839SM'boumba Cedric Madianga #include <linux/init.h> 18409ffc4dSAmelie Delaunay #include <linux/iopoll.h> 19d8b46839SM'boumba Cedric Madianga #include <linux/jiffies.h> 20d8b46839SM'boumba Cedric Madianga #include <linux/list.h> 21d8b46839SM'boumba Cedric Madianga #include <linux/module.h> 22d8b46839SM'boumba Cedric Madianga #include <linux/of.h> 23d8b46839SM'boumba Cedric Madianga #include <linux/of_device.h> 24d8b46839SM'boumba Cedric Madianga #include <linux/of_dma.h> 25d8b46839SM'boumba Cedric Madianga #include <linux/platform_device.h> 2648bc73baSPierre-Yves MORDRET #include <linux/pm_runtime.h> 27d8b46839SM'boumba Cedric Madianga #include <linux/reset.h> 28d8b46839SM'boumba Cedric Madianga #include <linux/sched.h> 29d8b46839SM'boumba Cedric Madianga #include <linux/slab.h> 30d8b46839SM'boumba Cedric Madianga 31d8b46839SM'boumba Cedric Madianga #include "virt-dma.h" 32d8b46839SM'boumba Cedric Madianga 33d8b46839SM'boumba Cedric Madianga #define STM32_DMA_LISR 0x0000 /* DMA Low Int Status Reg */ 34d8b46839SM'boumba Cedric Madianga #define STM32_DMA_HISR 0x0004 /* DMA High Int Status Reg */ 35d8b46839SM'boumba Cedric Madianga #define STM32_DMA_LIFCR 0x0008 /* DMA Low Int Flag Clear Reg */ 36d8b46839SM'boumba Cedric Madianga #define STM32_DMA_HIFCR 0x000c /* DMA High Int Flag Clear Reg */ 37d8b46839SM'boumba Cedric Madianga #define STM32_DMA_TCI BIT(5) /* Transfer Complete Interrupt */ 38c2d86b1cSPierre Yves MORDRET #define STM32_DMA_HTI BIT(4) /* Half Transfer Interrupt */ 39d8b46839SM'boumba Cedric Madianga #define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */ 40d8b46839SM'boumba Cedric Madianga #define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */ 41d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */ 429df3bd55SPierre Yves MORDRET #define STM32_DMA_MASKI (STM32_DMA_TCI \ 439df3bd55SPierre Yves MORDRET | STM32_DMA_TEI \ 449df3bd55SPierre Yves MORDRET | STM32_DMA_DMEI \ 459df3bd55SPierre Yves MORDRET | STM32_DMA_FEI) 46d8b46839SM'boumba Cedric Madianga 47d8b46839SM'boumba Cedric Madianga /* DMA Stream x Configuration Register */ 48d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */ 49d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_REQ(n) ((n & 0x7) << 25) 50d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MBURST_MASK GENMASK(24, 23) 51d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MBURST(n) ((n & 0x3) << 23) 52d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PBURST_MASK GENMASK(22, 21) 53d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PBURST(n) ((n & 0x3) << 21) 54d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PL_MASK GENMASK(17, 16) 55d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PL(n) ((n & 0x3) << 16) 56d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MSIZE_MASK GENMASK(14, 13) 57d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MSIZE(n) ((n & 0x3) << 13) 58d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PSIZE_MASK GENMASK(12, 11) 59d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PSIZE(n) ((n & 0x3) << 11) 60d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PSIZE_GET(n) ((n & STM32_DMA_SCR_PSIZE_MASK) >> 11) 61d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_DIR_MASK GENMASK(7, 6) 62d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_DIR(n) ((n & 0x3) << 6) 632b5b7405SAmelie Delaunay #define STM32_DMA_SCR_TRBUFF BIT(20) /* Bufferable transfer for USART/UART */ 64d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_CT BIT(19) /* Target in double buffer */ 65d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_DBM BIT(18) /* Double Buffer Mode */ 66d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PINCOS BIT(15) /* Peripheral inc offset size */ 67d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MINC BIT(10) /* Memory increment mode */ 68d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PINC BIT(9) /* Peripheral increment mode */ 69d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_CIRC BIT(8) /* Circular mode */ 70d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PFCTRL BIT(5) /* Peripheral Flow Controller */ 71249d5531SPierre Yves MORDRET #define STM32_DMA_SCR_TCIE BIT(4) /* Transfer Complete Int Enable 72249d5531SPierre Yves MORDRET */ 73d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_TEIE BIT(2) /* Transfer Error Int Enable */ 74d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_DMEIE BIT(1) /* Direct Mode Err Int Enable */ 75d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_EN BIT(0) /* Stream Enable */ 76d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_CFG_MASK (STM32_DMA_SCR_PINC \ 77d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_MINC \ 78d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_PINCOS \ 79d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_PL_MASK) 80d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_IRQ_MASK (STM32_DMA_SCR_TCIE \ 81d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_TEIE \ 82d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_DMEIE) 83d8b46839SM'boumba Cedric Madianga 84d8b46839SM'boumba Cedric Madianga /* DMA Stream x number of data register */ 85d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SNDTR(x) (0x0014 + 0x18 * (x)) 86d8b46839SM'boumba Cedric Madianga 87d8b46839SM'boumba Cedric Madianga /* DMA stream peripheral address register */ 88d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SPAR(x) (0x0018 + 0x18 * (x)) 89d8b46839SM'boumba Cedric Madianga 90d8b46839SM'boumba Cedric Madianga /* DMA stream x memory 0 address register */ 91d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SM0AR(x) (0x001c + 0x18 * (x)) 92d8b46839SM'boumba Cedric Madianga 93d8b46839SM'boumba Cedric Madianga /* DMA stream x memory 1 address register */ 94d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SM1AR(x) (0x0020 + 0x18 * (x)) 95d8b46839SM'boumba Cedric Madianga 96d8b46839SM'boumba Cedric Madianga /* DMA stream x FIFO control register */ 97d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR(x) (0x0024 + 0x18 * (x)) 98d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_FTH_MASK GENMASK(1, 0) 99d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_FTH(n) (n & STM32_DMA_SFCR_FTH_MASK) 100d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_FEIE BIT(7) /* FIFO error interrupt enable */ 101d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_DMDIS BIT(2) /* Direct mode disable */ 102d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_MASK (STM32_DMA_SFCR_FEIE \ 103d8b46839SM'boumba Cedric Madianga | STM32_DMA_SFCR_DMDIS) 104d8b46839SM'boumba Cedric Madianga 105d8b46839SM'boumba Cedric Madianga /* DMA direction */ 106d8b46839SM'boumba Cedric Madianga #define STM32_DMA_DEV_TO_MEM 0x00 107d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MEM_TO_DEV 0x01 108d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MEM_TO_MEM 0x02 109d8b46839SM'boumba Cedric Madianga 110d8b46839SM'boumba Cedric Madianga /* DMA priority level */ 111d8b46839SM'boumba Cedric Madianga #define STM32_DMA_PRIORITY_LOW 0x00 112d8b46839SM'boumba Cedric Madianga #define STM32_DMA_PRIORITY_MEDIUM 0x01 113d8b46839SM'boumba Cedric Madianga #define STM32_DMA_PRIORITY_HIGH 0x02 114d8b46839SM'boumba Cedric Madianga #define STM32_DMA_PRIORITY_VERY_HIGH 0x03 115d8b46839SM'boumba Cedric Madianga 116d8b46839SM'boumba Cedric Madianga /* DMA FIFO threshold selection */ 117d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00 118d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FIFO_THRESHOLD_HALFFULL 0x01 119d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FIFO_THRESHOLD_3QUARTERSFULL 0x02 120d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FIFO_THRESHOLD_FULL 0x03 121955b1766SAmelie Delaunay #define STM32_DMA_FIFO_THRESHOLD_NONE 0x04 122d8b46839SM'boumba Cedric Madianga 123d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MAX_DATA_ITEMS 0xffff 12480a76952SPierre Yves MORDRET /* 12580a76952SPierre Yves MORDRET * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter 12680a76952SPierre Yves MORDRET * gather at boundary. Thus it's safer to round down this value on FIFO 12780a76952SPierre Yves MORDRET * size (16 Bytes) 12880a76952SPierre Yves MORDRET */ 12980a76952SPierre Yves MORDRET #define STM32_DMA_ALIGNED_MAX_DATA_ITEMS \ 13080a76952SPierre Yves MORDRET ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16) 131d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MAX_CHANNELS 0x08 132d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MAX_REQUEST_ID 0x08 133d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MAX_DATA_PARAM 0x03 134a2b6103bSPierre Yves MORDRET #define STM32_DMA_FIFO_SIZE 16 /* FIFO is 16 bytes */ 135a2b6103bSPierre Yves MORDRET #define STM32_DMA_MIN_BURST 4 136276b0046SM'boumba Cedric Madianga #define STM32_DMA_MAX_BURST 16 137d8b46839SM'boumba Cedric Madianga 138951f44cbSPierre Yves MORDRET /* DMA Features */ 139951f44cbSPierre Yves MORDRET #define STM32_DMA_THRESHOLD_FTR_MASK GENMASK(1, 0) 140951f44cbSPierre Yves MORDRET #define STM32_DMA_THRESHOLD_FTR_GET(n) ((n) & STM32_DMA_THRESHOLD_FTR_MASK) 141955b1766SAmelie Delaunay #define STM32_DMA_DIRECT_MODE_MASK BIT(2) 1422b5b7405SAmelie Delaunay #define STM32_DMA_DIRECT_MODE_GET(n) (((n) & STM32_DMA_DIRECT_MODE_MASK) >> 2) 1432b5b7405SAmelie Delaunay #define STM32_DMA_ALT_ACK_MODE_MASK BIT(4) 1442b5b7405SAmelie Delaunay #define STM32_DMA_ALT_ACK_MODE_GET(n) (((n) & STM32_DMA_ALT_ACK_MODE_MASK) >> 4) 145951f44cbSPierre Yves MORDRET 146d8b46839SM'boumba Cedric Madianga enum stm32_dma_width { 147d8b46839SM'boumba Cedric Madianga STM32_DMA_BYTE, 148d8b46839SM'boumba Cedric Madianga STM32_DMA_HALF_WORD, 149d8b46839SM'boumba Cedric Madianga STM32_DMA_WORD, 150d8b46839SM'boumba Cedric Madianga }; 151d8b46839SM'boumba Cedric Madianga 152d8b46839SM'boumba Cedric Madianga enum stm32_dma_burst_size { 153d8b46839SM'boumba Cedric Madianga STM32_DMA_BURST_SINGLE, 154d8b46839SM'boumba Cedric Madianga STM32_DMA_BURST_INCR4, 155d8b46839SM'boumba Cedric Madianga STM32_DMA_BURST_INCR8, 156d8b46839SM'boumba Cedric Madianga STM32_DMA_BURST_INCR16, 157d8b46839SM'boumba Cedric Madianga }; 158d8b46839SM'boumba Cedric Madianga 159951f44cbSPierre Yves MORDRET /** 160951f44cbSPierre Yves MORDRET * struct stm32_dma_cfg - STM32 DMA custom configuration 161951f44cbSPierre Yves MORDRET * @channel_id: channel ID 162951f44cbSPierre Yves MORDRET * @request_line: DMA request 163951f44cbSPierre Yves MORDRET * @stream_config: 32bit mask specifying the DMA channel configuration 164951f44cbSPierre Yves MORDRET * @features: 32bit mask specifying the DMA Feature list 165951f44cbSPierre Yves MORDRET */ 166d8b46839SM'boumba Cedric Madianga struct stm32_dma_cfg { 167d8b46839SM'boumba Cedric Madianga u32 channel_id; 168d8b46839SM'boumba Cedric Madianga u32 request_line; 169d8b46839SM'boumba Cedric Madianga u32 stream_config; 170951f44cbSPierre Yves MORDRET u32 features; 171d8b46839SM'boumba Cedric Madianga }; 172d8b46839SM'boumba Cedric Madianga 173d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan_reg { 174d8b46839SM'boumba Cedric Madianga u32 dma_lisr; 175d8b46839SM'boumba Cedric Madianga u32 dma_hisr; 176d8b46839SM'boumba Cedric Madianga u32 dma_lifcr; 177d8b46839SM'boumba Cedric Madianga u32 dma_hifcr; 178d8b46839SM'boumba Cedric Madianga u32 dma_scr; 179d8b46839SM'boumba Cedric Madianga u32 dma_sndtr; 180d8b46839SM'boumba Cedric Madianga u32 dma_spar; 181d8b46839SM'boumba Cedric Madianga u32 dma_sm0ar; 182d8b46839SM'boumba Cedric Madianga u32 dma_sm1ar; 183d8b46839SM'boumba Cedric Madianga u32 dma_sfcr; 184d8b46839SM'boumba Cedric Madianga }; 185d8b46839SM'boumba Cedric Madianga 186d8b46839SM'boumba Cedric Madianga struct stm32_dma_sg_req { 187d8b46839SM'boumba Cedric Madianga u32 len; 188d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan_reg chan_reg; 189d8b46839SM'boumba Cedric Madianga }; 190d8b46839SM'boumba Cedric Madianga 191d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc { 192d8b46839SM'boumba Cedric Madianga struct virt_dma_desc vdesc; 193d8b46839SM'boumba Cedric Madianga bool cyclic; 194d8b46839SM'boumba Cedric Madianga u32 num_sgs; 195d8b46839SM'boumba Cedric Madianga struct stm32_dma_sg_req sg_req[]; 196d8b46839SM'boumba Cedric Madianga }; 197d8b46839SM'boumba Cedric Madianga 198d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan { 199d8b46839SM'boumba Cedric Madianga struct virt_dma_chan vchan; 200d8b46839SM'boumba Cedric Madianga bool config_init; 201d8b46839SM'boumba Cedric Madianga bool busy; 202d8b46839SM'boumba Cedric Madianga u32 id; 203d8b46839SM'boumba Cedric Madianga u32 irq; 204d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc; 205d8b46839SM'boumba Cedric Madianga u32 next_sg; 206d8b46839SM'boumba Cedric Madianga struct dma_slave_config dma_sconfig; 207d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan_reg chan_reg; 208951f44cbSPierre Yves MORDRET u32 threshold; 209a2b6103bSPierre Yves MORDRET u32 mem_burst; 210a2b6103bSPierre Yves MORDRET u32 mem_width; 211d8b46839SM'boumba Cedric Madianga }; 212d8b46839SM'boumba Cedric Madianga 213d8b46839SM'boumba Cedric Madianga struct stm32_dma_device { 214d8b46839SM'boumba Cedric Madianga struct dma_device ddev; 215d8b46839SM'boumba Cedric Madianga void __iomem *base; 216d8b46839SM'boumba Cedric Madianga struct clk *clk; 217d8b46839SM'boumba Cedric Madianga bool mem2mem; 218d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS]; 219d8b46839SM'boumba Cedric Madianga }; 220d8b46839SM'boumba Cedric Madianga 221d8b46839SM'boumba Cedric Madianga static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan) 222d8b46839SM'boumba Cedric Madianga { 223d8b46839SM'boumba Cedric Madianga return container_of(chan->vchan.chan.device, struct stm32_dma_device, 224d8b46839SM'boumba Cedric Madianga ddev); 225d8b46839SM'boumba Cedric Madianga } 226d8b46839SM'boumba Cedric Madianga 227d8b46839SM'boumba Cedric Madianga static struct stm32_dma_chan *to_stm32_dma_chan(struct dma_chan *c) 228d8b46839SM'boumba Cedric Madianga { 229d8b46839SM'boumba Cedric Madianga return container_of(c, struct stm32_dma_chan, vchan.chan); 230d8b46839SM'boumba Cedric Madianga } 231d8b46839SM'boumba Cedric Madianga 232d8b46839SM'boumba Cedric Madianga static struct stm32_dma_desc *to_stm32_dma_desc(struct virt_dma_desc *vdesc) 233d8b46839SM'boumba Cedric Madianga { 234d8b46839SM'boumba Cedric Madianga return container_of(vdesc, struct stm32_dma_desc, vdesc); 235d8b46839SM'boumba Cedric Madianga } 236d8b46839SM'boumba Cedric Madianga 237d8b46839SM'boumba Cedric Madianga static struct device *chan2dev(struct stm32_dma_chan *chan) 238d8b46839SM'boumba Cedric Madianga { 239d8b46839SM'boumba Cedric Madianga return &chan->vchan.chan.dev->device; 240d8b46839SM'boumba Cedric Madianga } 241d8b46839SM'boumba Cedric Madianga 242d8b46839SM'boumba Cedric Madianga static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg) 243d8b46839SM'boumba Cedric Madianga { 244d8b46839SM'boumba Cedric Madianga return readl_relaxed(dmadev->base + reg); 245d8b46839SM'boumba Cedric Madianga } 246d8b46839SM'boumba Cedric Madianga 247d8b46839SM'boumba Cedric Madianga static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val) 248d8b46839SM'boumba Cedric Madianga { 249d8b46839SM'boumba Cedric Madianga writel_relaxed(val, dmadev->base + reg); 250d8b46839SM'boumba Cedric Madianga } 251d8b46839SM'boumba Cedric Madianga 252d8b46839SM'boumba Cedric Madianga static int stm32_dma_get_width(struct stm32_dma_chan *chan, 253d8b46839SM'boumba Cedric Madianga enum dma_slave_buswidth width) 254d8b46839SM'boumba Cedric Madianga { 255d8b46839SM'boumba Cedric Madianga switch (width) { 256d8b46839SM'boumba Cedric Madianga case DMA_SLAVE_BUSWIDTH_1_BYTE: 257d8b46839SM'boumba Cedric Madianga return STM32_DMA_BYTE; 258d8b46839SM'boumba Cedric Madianga case DMA_SLAVE_BUSWIDTH_2_BYTES: 259d8b46839SM'boumba Cedric Madianga return STM32_DMA_HALF_WORD; 260d8b46839SM'boumba Cedric Madianga case DMA_SLAVE_BUSWIDTH_4_BYTES: 261d8b46839SM'boumba Cedric Madianga return STM32_DMA_WORD; 262d8b46839SM'boumba Cedric Madianga default: 263d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Dma bus width not supported\n"); 264d8b46839SM'boumba Cedric Madianga return -EINVAL; 265d8b46839SM'boumba Cedric Madianga } 266d8b46839SM'boumba Cedric Madianga } 267d8b46839SM'boumba Cedric Madianga 268a2b6103bSPierre Yves MORDRET static enum dma_slave_buswidth stm32_dma_get_max_width(u32 buf_len, 269e0ebdbdcSAmelie Delaunay dma_addr_t buf_addr, 270a2b6103bSPierre Yves MORDRET u32 threshold) 271a2b6103bSPierre Yves MORDRET { 272a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth max_width; 273a2b6103bSPierre Yves MORDRET 274a2b6103bSPierre Yves MORDRET if (threshold == STM32_DMA_FIFO_THRESHOLD_FULL) 275a2b6103bSPierre Yves MORDRET max_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 276a2b6103bSPierre Yves MORDRET else 277a2b6103bSPierre Yves MORDRET max_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 278a2b6103bSPierre Yves MORDRET 279a2b6103bSPierre Yves MORDRET while ((buf_len < max_width || buf_len % max_width) && 280a2b6103bSPierre Yves MORDRET max_width > DMA_SLAVE_BUSWIDTH_1_BYTE) 281a2b6103bSPierre Yves MORDRET max_width = max_width >> 1; 282a2b6103bSPierre Yves MORDRET 283*24983633SArnd Bergmann if (buf_addr & (max_width - 1)) 284e0ebdbdcSAmelie Delaunay max_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 285e0ebdbdcSAmelie Delaunay 286a2b6103bSPierre Yves MORDRET return max_width; 287a2b6103bSPierre Yves MORDRET } 288a2b6103bSPierre Yves MORDRET 289a2b6103bSPierre Yves MORDRET static bool stm32_dma_fifo_threshold_is_allowed(u32 burst, u32 threshold, 290a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth width) 291a2b6103bSPierre Yves MORDRET { 292a2b6103bSPierre Yves MORDRET u32 remaining; 293a2b6103bSPierre Yves MORDRET 294955b1766SAmelie Delaunay if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE) 295955b1766SAmelie Delaunay return false; 296955b1766SAmelie Delaunay 297a2b6103bSPierre Yves MORDRET if (width != DMA_SLAVE_BUSWIDTH_UNDEFINED) { 298a2b6103bSPierre Yves MORDRET if (burst != 0) { 299a2b6103bSPierre Yves MORDRET /* 300a2b6103bSPierre Yves MORDRET * If number of beats fit in several whole bursts 301a2b6103bSPierre Yves MORDRET * this configuration is allowed. 302a2b6103bSPierre Yves MORDRET */ 303a2b6103bSPierre Yves MORDRET remaining = ((STM32_DMA_FIFO_SIZE / width) * 304a2b6103bSPierre Yves MORDRET (threshold + 1) / 4) % burst; 305a2b6103bSPierre Yves MORDRET 306a2b6103bSPierre Yves MORDRET if (remaining == 0) 307a2b6103bSPierre Yves MORDRET return true; 308a2b6103bSPierre Yves MORDRET } else { 309a2b6103bSPierre Yves MORDRET return true; 310a2b6103bSPierre Yves MORDRET } 311a2b6103bSPierre Yves MORDRET } 312a2b6103bSPierre Yves MORDRET 313a2b6103bSPierre Yves MORDRET return false; 314a2b6103bSPierre Yves MORDRET } 315a2b6103bSPierre Yves MORDRET 316a2b6103bSPierre Yves MORDRET static bool stm32_dma_is_burst_possible(u32 buf_len, u32 threshold) 317a2b6103bSPierre Yves MORDRET { 318955b1766SAmelie Delaunay /* If FIFO direct mode, burst is not possible */ 319955b1766SAmelie Delaunay if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE) 320955b1766SAmelie Delaunay return false; 321955b1766SAmelie Delaunay 322cc832dc8SPierre-Yves MORDRET /* 323cc832dc8SPierre-Yves MORDRET * Buffer or period length has to be aligned on FIFO depth. 324cc832dc8SPierre-Yves MORDRET * Otherwise bytes may be stuck within FIFO at buffer or period 325cc832dc8SPierre-Yves MORDRET * length. 326cc832dc8SPierre-Yves MORDRET */ 327cc832dc8SPierre-Yves MORDRET return ((buf_len % ((threshold + 1) * 4)) == 0); 328a2b6103bSPierre Yves MORDRET } 329a2b6103bSPierre Yves MORDRET 330a2b6103bSPierre Yves MORDRET static u32 stm32_dma_get_best_burst(u32 buf_len, u32 max_burst, u32 threshold, 331a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth width) 332a2b6103bSPierre Yves MORDRET { 333a2b6103bSPierre Yves MORDRET u32 best_burst = max_burst; 334a2b6103bSPierre Yves MORDRET 335a2b6103bSPierre Yves MORDRET if (best_burst == 1 || !stm32_dma_is_burst_possible(buf_len, threshold)) 336a2b6103bSPierre Yves MORDRET return 0; 337a2b6103bSPierre Yves MORDRET 338a2b6103bSPierre Yves MORDRET while ((buf_len < best_burst * width && best_burst > 1) || 339a2b6103bSPierre Yves MORDRET !stm32_dma_fifo_threshold_is_allowed(best_burst, threshold, 340a2b6103bSPierre Yves MORDRET width)) { 341a2b6103bSPierre Yves MORDRET if (best_burst > STM32_DMA_MIN_BURST) 342a2b6103bSPierre Yves MORDRET best_burst = best_burst >> 1; 343a2b6103bSPierre Yves MORDRET else 344a2b6103bSPierre Yves MORDRET best_burst = 0; 345a2b6103bSPierre Yves MORDRET } 346a2b6103bSPierre Yves MORDRET 347a2b6103bSPierre Yves MORDRET return best_burst; 348a2b6103bSPierre Yves MORDRET } 349a2b6103bSPierre Yves MORDRET 350d8b46839SM'boumba Cedric Madianga static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst) 351d8b46839SM'boumba Cedric Madianga { 352d8b46839SM'boumba Cedric Madianga switch (maxburst) { 353d8b46839SM'boumba Cedric Madianga case 0: 354d8b46839SM'boumba Cedric Madianga case 1: 355d8b46839SM'boumba Cedric Madianga return STM32_DMA_BURST_SINGLE; 356d8b46839SM'boumba Cedric Madianga case 4: 357d8b46839SM'boumba Cedric Madianga return STM32_DMA_BURST_INCR4; 358d8b46839SM'boumba Cedric Madianga case 8: 359d8b46839SM'boumba Cedric Madianga return STM32_DMA_BURST_INCR8; 360d8b46839SM'boumba Cedric Madianga case 16: 361d8b46839SM'boumba Cedric Madianga return STM32_DMA_BURST_INCR16; 362d8b46839SM'boumba Cedric Madianga default: 363d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Dma burst size not supported\n"); 364d8b46839SM'boumba Cedric Madianga return -EINVAL; 365d8b46839SM'boumba Cedric Madianga } 366d8b46839SM'boumba Cedric Madianga } 367d8b46839SM'boumba Cedric Madianga 368d8b46839SM'boumba Cedric Madianga static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan, 369a2b6103bSPierre Yves MORDRET u32 src_burst, u32 dst_burst) 370d8b46839SM'boumba Cedric Madianga { 371d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK; 372d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE; 373d8b46839SM'boumba Cedric Madianga 374a2b6103bSPierre Yves MORDRET if (!src_burst && !dst_burst) { 375d8b46839SM'boumba Cedric Madianga /* Using direct mode */ 376d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE; 377d8b46839SM'boumba Cedric Madianga } else { 378d8b46839SM'boumba Cedric Madianga /* Using FIFO mode */ 379d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; 380d8b46839SM'boumba Cedric Madianga } 381d8b46839SM'boumba Cedric Madianga } 382d8b46839SM'boumba Cedric Madianga 383d8b46839SM'boumba Cedric Madianga static int stm32_dma_slave_config(struct dma_chan *c, 384d8b46839SM'boumba Cedric Madianga struct dma_slave_config *config) 385d8b46839SM'boumba Cedric Madianga { 386d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 387d8b46839SM'boumba Cedric Madianga 388d8b46839SM'boumba Cedric Madianga memcpy(&chan->dma_sconfig, config, sizeof(*config)); 389d8b46839SM'boumba Cedric Madianga 390d8b46839SM'boumba Cedric Madianga chan->config_init = true; 391d8b46839SM'boumba Cedric Madianga 392d8b46839SM'boumba Cedric Madianga return 0; 393d8b46839SM'boumba Cedric Madianga } 394d8b46839SM'boumba Cedric Madianga 395d8b46839SM'boumba Cedric Madianga static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan) 396d8b46839SM'boumba Cedric Madianga { 397d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 398d8b46839SM'boumba Cedric Madianga u32 flags, dma_isr; 399d8b46839SM'boumba Cedric Madianga 400d8b46839SM'boumba Cedric Madianga /* 401d8b46839SM'boumba Cedric Madianga * Read "flags" from DMA_xISR register corresponding to the selected 402d8b46839SM'boumba Cedric Madianga * DMA channel at the correct bit offset inside that register. 403d8b46839SM'boumba Cedric Madianga * 404d8b46839SM'boumba Cedric Madianga * If (ch % 4) is 2 or 3, left shift the mask by 16 bits. 405d8b46839SM'boumba Cedric Madianga * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. 406d8b46839SM'boumba Cedric Madianga */ 407d8b46839SM'boumba Cedric Madianga 408d8b46839SM'boumba Cedric Madianga if (chan->id & 4) 409d8b46839SM'boumba Cedric Madianga dma_isr = stm32_dma_read(dmadev, STM32_DMA_HISR); 410d8b46839SM'boumba Cedric Madianga else 411d8b46839SM'boumba Cedric Madianga dma_isr = stm32_dma_read(dmadev, STM32_DMA_LISR); 412d8b46839SM'boumba Cedric Madianga 413d8b46839SM'boumba Cedric Madianga flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); 414d8b46839SM'boumba Cedric Madianga 4159df3bd55SPierre Yves MORDRET return flags & STM32_DMA_MASKI; 416d8b46839SM'boumba Cedric Madianga } 417d8b46839SM'boumba Cedric Madianga 418d8b46839SM'boumba Cedric Madianga static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags) 419d8b46839SM'boumba Cedric Madianga { 420d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 421d8b46839SM'boumba Cedric Madianga u32 dma_ifcr; 422d8b46839SM'boumba Cedric Madianga 423d8b46839SM'boumba Cedric Madianga /* 424d8b46839SM'boumba Cedric Madianga * Write "flags" to the DMA_xIFCR register corresponding to the selected 425d8b46839SM'boumba Cedric Madianga * DMA channel at the correct bit offset inside that register. 426d8b46839SM'boumba Cedric Madianga * 427d8b46839SM'boumba Cedric Madianga * If (ch % 4) is 2 or 3, left shift the mask by 16 bits. 428d8b46839SM'boumba Cedric Madianga * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. 429d8b46839SM'boumba Cedric Madianga */ 4309df3bd55SPierre Yves MORDRET flags &= STM32_DMA_MASKI; 431d8b46839SM'boumba Cedric Madianga dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); 432d8b46839SM'boumba Cedric Madianga 433d8b46839SM'boumba Cedric Madianga if (chan->id & 4) 434d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_HIFCR, dma_ifcr); 435d8b46839SM'boumba Cedric Madianga else 436d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_LIFCR, dma_ifcr); 437d8b46839SM'boumba Cedric Madianga } 438d8b46839SM'boumba Cedric Madianga 439d8b46839SM'boumba Cedric Madianga static int stm32_dma_disable_chan(struct stm32_dma_chan *chan) 440d8b46839SM'boumba Cedric Madianga { 441d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 442409ffc4dSAmelie Delaunay u32 dma_scr, id, reg; 443d8b46839SM'boumba Cedric Madianga 444d8b46839SM'boumba Cedric Madianga id = chan->id; 445409ffc4dSAmelie Delaunay reg = STM32_DMA_SCR(id); 446409ffc4dSAmelie Delaunay dma_scr = stm32_dma_read(dmadev, reg); 447d8b46839SM'boumba Cedric Madianga 448d8b46839SM'boumba Cedric Madianga if (dma_scr & STM32_DMA_SCR_EN) { 449d8b46839SM'boumba Cedric Madianga dma_scr &= ~STM32_DMA_SCR_EN; 450409ffc4dSAmelie Delaunay stm32_dma_write(dmadev, reg, dma_scr); 451d8b46839SM'boumba Cedric Madianga 452409ffc4dSAmelie Delaunay return readl_relaxed_poll_timeout_atomic(dmadev->base + reg, 453409ffc4dSAmelie Delaunay dma_scr, !(dma_scr & STM32_DMA_SCR_EN), 454409ffc4dSAmelie Delaunay 10, 1000000); 455d8b46839SM'boumba Cedric Madianga } 456d8b46839SM'boumba Cedric Madianga 457d8b46839SM'boumba Cedric Madianga return 0; 458d8b46839SM'boumba Cedric Madianga } 459d8b46839SM'boumba Cedric Madianga 460d8b46839SM'boumba Cedric Madianga static void stm32_dma_stop(struct stm32_dma_chan *chan) 461d8b46839SM'boumba Cedric Madianga { 462d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 463d8b46839SM'boumba Cedric Madianga u32 dma_scr, dma_sfcr, status; 464d8b46839SM'boumba Cedric Madianga int ret; 465d8b46839SM'boumba Cedric Madianga 466d8b46839SM'boumba Cedric Madianga /* Disable interrupts */ 467d8b46839SM'boumba Cedric Madianga dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 468d8b46839SM'boumba Cedric Madianga dma_scr &= ~STM32_DMA_SCR_IRQ_MASK; 469d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); 470d8b46839SM'boumba Cedric Madianga dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); 471d8b46839SM'boumba Cedric Madianga dma_sfcr &= ~STM32_DMA_SFCR_FEIE; 472d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr); 473d8b46839SM'boumba Cedric Madianga 474d8b46839SM'boumba Cedric Madianga /* Disable DMA */ 475d8b46839SM'boumba Cedric Madianga ret = stm32_dma_disable_chan(chan); 476d8b46839SM'boumba Cedric Madianga if (ret < 0) 477d8b46839SM'boumba Cedric Madianga return; 478d8b46839SM'boumba Cedric Madianga 479d8b46839SM'boumba Cedric Madianga /* Clear interrupt status if it is there */ 480d8b46839SM'boumba Cedric Madianga status = stm32_dma_irq_status(chan); 481d8b46839SM'boumba Cedric Madianga if (status) { 482d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n", 483d8b46839SM'boumba Cedric Madianga __func__, status); 484d8b46839SM'boumba Cedric Madianga stm32_dma_irq_clear(chan, status); 485d8b46839SM'boumba Cedric Madianga } 486d8b46839SM'boumba Cedric Madianga 487d8b46839SM'boumba Cedric Madianga chan->busy = false; 488d8b46839SM'boumba Cedric Madianga } 489d8b46839SM'boumba Cedric Madianga 490d8b46839SM'boumba Cedric Madianga static int stm32_dma_terminate_all(struct dma_chan *c) 491d8b46839SM'boumba Cedric Madianga { 492d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 493d8b46839SM'boumba Cedric Madianga unsigned long flags; 494d8b46839SM'boumba Cedric Madianga LIST_HEAD(head); 495d8b46839SM'boumba Cedric Madianga 496d8b46839SM'boumba Cedric Madianga spin_lock_irqsave(&chan->vchan.lock, flags); 497d8b46839SM'boumba Cedric Madianga 498d80cbef3SAmelie Delaunay if (chan->desc) { 49979e40b06SAmelie Delaunay dma_cookie_complete(&chan->desc->vdesc.tx); 500d80cbef3SAmelie Delaunay vchan_terminate_vdesc(&chan->desc->vdesc); 501d80cbef3SAmelie Delaunay if (chan->busy) 502d8b46839SM'boumba Cedric Madianga stm32_dma_stop(chan); 503d8b46839SM'boumba Cedric Madianga chan->desc = NULL; 504d8b46839SM'boumba Cedric Madianga } 505d8b46839SM'boumba Cedric Madianga 506d8b46839SM'boumba Cedric Madianga vchan_get_all_descriptors(&chan->vchan, &head); 507d8b46839SM'boumba Cedric Madianga spin_unlock_irqrestore(&chan->vchan.lock, flags); 508d8b46839SM'boumba Cedric Madianga vchan_dma_desc_free_list(&chan->vchan, &head); 509d8b46839SM'boumba Cedric Madianga 510d8b46839SM'boumba Cedric Madianga return 0; 511d8b46839SM'boumba Cedric Madianga } 512d8b46839SM'boumba Cedric Madianga 513dc808675SM'boumba Cedric Madianga static void stm32_dma_synchronize(struct dma_chan *c) 514dc808675SM'boumba Cedric Madianga { 515dc808675SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 516dc808675SM'boumba Cedric Madianga 517dc808675SM'boumba Cedric Madianga vchan_synchronize(&chan->vchan); 518dc808675SM'boumba Cedric Madianga } 519dc808675SM'boumba Cedric Madianga 520d8b46839SM'boumba Cedric Madianga static void stm32_dma_dump_reg(struct stm32_dma_chan *chan) 521d8b46839SM'boumba Cedric Madianga { 522d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 523d8b46839SM'boumba Cedric Madianga u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 524d8b46839SM'boumba Cedric Madianga u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); 525d8b46839SM'boumba Cedric Madianga u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id)); 526d8b46839SM'boumba Cedric Madianga u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id)); 527d8b46839SM'boumba Cedric Madianga u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id)); 528d8b46839SM'boumba Cedric Madianga u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); 529d8b46839SM'boumba Cedric Madianga 530d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SCR: 0x%08x\n", scr); 531d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "NDTR: 0x%08x\n", ndtr); 532d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SPAR: 0x%08x\n", spar); 533d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar); 534d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar); 535d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SFCR: 0x%08x\n", sfcr); 536d8b46839SM'boumba Cedric Madianga } 537d8b46839SM'boumba Cedric Madianga 538e57cb3b3SPierre Yves MORDRET static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan); 539e57cb3b3SPierre Yves MORDRET 5408d1b76f0SM'boumba Cedric Madianga static void stm32_dma_start_transfer(struct stm32_dma_chan *chan) 541d8b46839SM'boumba Cedric Madianga { 542d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 543d8b46839SM'boumba Cedric Madianga struct virt_dma_desc *vdesc; 544d8b46839SM'boumba Cedric Madianga struct stm32_dma_sg_req *sg_req; 545d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan_reg *reg; 546d8b46839SM'boumba Cedric Madianga u32 status; 547d8b46839SM'boumba Cedric Madianga int ret; 548d8b46839SM'boumba Cedric Madianga 549d8b46839SM'boumba Cedric Madianga ret = stm32_dma_disable_chan(chan); 550d8b46839SM'boumba Cedric Madianga if (ret < 0) 5518d1b76f0SM'boumba Cedric Madianga return; 552d8b46839SM'boumba Cedric Madianga 553d8b46839SM'boumba Cedric Madianga if (!chan->desc) { 554d8b46839SM'boumba Cedric Madianga vdesc = vchan_next_desc(&chan->vchan); 555d8b46839SM'boumba Cedric Madianga if (!vdesc) 5568d1b76f0SM'boumba Cedric Madianga return; 557d8b46839SM'boumba Cedric Madianga 558d80cbef3SAmelie Delaunay list_del(&vdesc->node); 559d80cbef3SAmelie Delaunay 560d8b46839SM'boumba Cedric Madianga chan->desc = to_stm32_dma_desc(vdesc); 561d8b46839SM'boumba Cedric Madianga chan->next_sg = 0; 562d8b46839SM'boumba Cedric Madianga } 563d8b46839SM'boumba Cedric Madianga 564d8b46839SM'boumba Cedric Madianga if (chan->next_sg == chan->desc->num_sgs) 565d8b46839SM'boumba Cedric Madianga chan->next_sg = 0; 566d8b46839SM'boumba Cedric Madianga 567d8b46839SM'boumba Cedric Madianga sg_req = &chan->desc->sg_req[chan->next_sg]; 568d8b46839SM'boumba Cedric Madianga reg = &sg_req->chan_reg; 569d8b46839SM'boumba Cedric Madianga 57022a0bb29SPierre-Yves MORDRET reg->dma_scr &= ~STM32_DMA_SCR_EN; 571d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); 572d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar); 573d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar); 574d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr); 575d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar); 576d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr); 577d8b46839SM'boumba Cedric Madianga 578d8b46839SM'boumba Cedric Madianga chan->next_sg++; 579d8b46839SM'boumba Cedric Madianga 580d8b46839SM'boumba Cedric Madianga /* Clear interrupt status if it is there */ 581d8b46839SM'boumba Cedric Madianga status = stm32_dma_irq_status(chan); 582d8b46839SM'boumba Cedric Madianga if (status) 583d8b46839SM'boumba Cedric Madianga stm32_dma_irq_clear(chan, status); 584d8b46839SM'boumba Cedric Madianga 585e57cb3b3SPierre Yves MORDRET if (chan->desc->cyclic) 586e57cb3b3SPierre Yves MORDRET stm32_dma_configure_next_sg(chan); 587e57cb3b3SPierre Yves MORDRET 588d8b46839SM'boumba Cedric Madianga stm32_dma_dump_reg(chan); 589d8b46839SM'boumba Cedric Madianga 590d8b46839SM'boumba Cedric Madianga /* Start DMA */ 591d8b46839SM'boumba Cedric Madianga reg->dma_scr |= STM32_DMA_SCR_EN; 592d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); 593d8b46839SM'boumba Cedric Madianga 594d8b46839SM'boumba Cedric Madianga chan->busy = true; 595d8b46839SM'boumba Cedric Madianga 59690ec93cbSBenjamin Gaignard dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan); 597d8b46839SM'boumba Cedric Madianga } 598d8b46839SM'boumba Cedric Madianga 599d8b46839SM'boumba Cedric Madianga static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan) 600d8b46839SM'boumba Cedric Madianga { 601d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 602d8b46839SM'boumba Cedric Madianga struct stm32_dma_sg_req *sg_req; 603d8b46839SM'boumba Cedric Madianga u32 dma_scr, dma_sm0ar, dma_sm1ar, id; 604d8b46839SM'boumba Cedric Madianga 605d8b46839SM'boumba Cedric Madianga id = chan->id; 606d8b46839SM'boumba Cedric Madianga dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); 607d8b46839SM'boumba Cedric Madianga 608d8b46839SM'boumba Cedric Madianga if (dma_scr & STM32_DMA_SCR_DBM) { 609d8b46839SM'boumba Cedric Madianga if (chan->next_sg == chan->desc->num_sgs) 610d8b46839SM'boumba Cedric Madianga chan->next_sg = 0; 611d8b46839SM'boumba Cedric Madianga 612d8b46839SM'boumba Cedric Madianga sg_req = &chan->desc->sg_req[chan->next_sg]; 613d8b46839SM'boumba Cedric Madianga 614d8b46839SM'boumba Cedric Madianga if (dma_scr & STM32_DMA_SCR_CT) { 615d8b46839SM'boumba Cedric Madianga dma_sm0ar = sg_req->chan_reg.dma_sm0ar; 616d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar); 617d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n", 618d8b46839SM'boumba Cedric Madianga stm32_dma_read(dmadev, STM32_DMA_SM0AR(id))); 619d8b46839SM'boumba Cedric Madianga } else { 620d8b46839SM'boumba Cedric Madianga dma_sm1ar = sg_req->chan_reg.dma_sm1ar; 621d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar); 622d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n", 623d8b46839SM'boumba Cedric Madianga stm32_dma_read(dmadev, STM32_DMA_SM1AR(id))); 624d8b46839SM'boumba Cedric Madianga } 625d8b46839SM'boumba Cedric Madianga } 626d8b46839SM'boumba Cedric Madianga } 627d8b46839SM'boumba Cedric Madianga 628d8b46839SM'boumba Cedric Madianga static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan) 629d8b46839SM'boumba Cedric Madianga { 630d8b46839SM'boumba Cedric Madianga if (chan->desc) { 631d8b46839SM'boumba Cedric Madianga if (chan->desc->cyclic) { 632d8b46839SM'boumba Cedric Madianga vchan_cyclic_callback(&chan->desc->vdesc); 6332b12c558SM'boumba Cedric Madianga chan->next_sg++; 634d8b46839SM'boumba Cedric Madianga stm32_dma_configure_next_sg(chan); 635d8b46839SM'boumba Cedric Madianga } else { 636d8b46839SM'boumba Cedric Madianga chan->busy = false; 637d8b46839SM'boumba Cedric Madianga if (chan->next_sg == chan->desc->num_sgs) { 638d8b46839SM'boumba Cedric Madianga vchan_cookie_complete(&chan->desc->vdesc); 639d8b46839SM'boumba Cedric Madianga chan->desc = NULL; 640d8b46839SM'boumba Cedric Madianga } 641d8b46839SM'boumba Cedric Madianga stm32_dma_start_transfer(chan); 642d8b46839SM'boumba Cedric Madianga } 643d8b46839SM'boumba Cedric Madianga } 644d8b46839SM'boumba Cedric Madianga } 645d8b46839SM'boumba Cedric Madianga 646d8b46839SM'boumba Cedric Madianga static irqreturn_t stm32_dma_chan_irq(int irq, void *devid) 647d8b46839SM'boumba Cedric Madianga { 648d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = devid; 649d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 650ca4c72c0SPierre-Yves MORDRET u32 status, scr, sfcr; 651d8b46839SM'boumba Cedric Madianga 652d8b46839SM'boumba Cedric Madianga spin_lock(&chan->vchan.lock); 653d8b46839SM'boumba Cedric Madianga 654d8b46839SM'boumba Cedric Madianga status = stm32_dma_irq_status(chan); 655d8b46839SM'boumba Cedric Madianga scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 656ca4c72c0SPierre-Yves MORDRET sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); 657d8b46839SM'boumba Cedric Madianga 658c2d86b1cSPierre Yves MORDRET if (status & STM32_DMA_FEI) { 659c2d86b1cSPierre Yves MORDRET stm32_dma_irq_clear(chan, STM32_DMA_FEI); 660c2d86b1cSPierre Yves MORDRET status &= ~STM32_DMA_FEI; 661ca4c72c0SPierre-Yves MORDRET if (sfcr & STM32_DMA_SFCR_FEIE) { 662a44d9d72SAmelie Delaunay if (!(scr & STM32_DMA_SCR_EN) && 663a44d9d72SAmelie Delaunay !(status & STM32_DMA_TCI)) 664c2d86b1cSPierre Yves MORDRET dev_err(chan2dev(chan), "FIFO Error\n"); 665c2d86b1cSPierre Yves MORDRET else 666c2d86b1cSPierre Yves MORDRET dev_dbg(chan2dev(chan), "FIFO over/underrun\n"); 667c2d86b1cSPierre Yves MORDRET } 668ca4c72c0SPierre-Yves MORDRET } 669955b1766SAmelie Delaunay if (status & STM32_DMA_DMEI) { 670955b1766SAmelie Delaunay stm32_dma_irq_clear(chan, STM32_DMA_DMEI); 671955b1766SAmelie Delaunay status &= ~STM32_DMA_DMEI; 672955b1766SAmelie Delaunay if (sfcr & STM32_DMA_SCR_DMEIE) 673955b1766SAmelie Delaunay dev_dbg(chan2dev(chan), "Direct mode overrun\n"); 674955b1766SAmelie Delaunay } 675a44d9d72SAmelie Delaunay 676a44d9d72SAmelie Delaunay if (status & STM32_DMA_TCI) { 677a44d9d72SAmelie Delaunay stm32_dma_irq_clear(chan, STM32_DMA_TCI); 678a44d9d72SAmelie Delaunay if (scr & STM32_DMA_SCR_TCIE) 679a44d9d72SAmelie Delaunay stm32_dma_handle_chan_done(chan); 680a44d9d72SAmelie Delaunay status &= ~STM32_DMA_TCI; 681a44d9d72SAmelie Delaunay } 682a44d9d72SAmelie Delaunay 683a44d9d72SAmelie Delaunay if (status & STM32_DMA_HTI) { 684a44d9d72SAmelie Delaunay stm32_dma_irq_clear(chan, STM32_DMA_HTI); 685a44d9d72SAmelie Delaunay status &= ~STM32_DMA_HTI; 686a44d9d72SAmelie Delaunay } 687a44d9d72SAmelie Delaunay 688c2d86b1cSPierre Yves MORDRET if (status) { 689d8b46839SM'boumba Cedric Madianga stm32_dma_irq_clear(chan, status); 690d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status); 691c2d86b1cSPierre Yves MORDRET if (!(scr & STM32_DMA_SCR_EN)) 692c2d86b1cSPierre Yves MORDRET dev_err(chan2dev(chan), "chan disabled by HW\n"); 693d8b46839SM'boumba Cedric Madianga } 694d8b46839SM'boumba Cedric Madianga 695d8b46839SM'boumba Cedric Madianga spin_unlock(&chan->vchan.lock); 696d8b46839SM'boumba Cedric Madianga 697d8b46839SM'boumba Cedric Madianga return IRQ_HANDLED; 698d8b46839SM'boumba Cedric Madianga } 699d8b46839SM'boumba Cedric Madianga 700d8b46839SM'boumba Cedric Madianga static void stm32_dma_issue_pending(struct dma_chan *c) 701d8b46839SM'boumba Cedric Madianga { 702d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 703d8b46839SM'boumba Cedric Madianga unsigned long flags; 704d8b46839SM'boumba Cedric Madianga 705d8b46839SM'boumba Cedric Madianga spin_lock_irqsave(&chan->vchan.lock, flags); 7068d1b76f0SM'boumba Cedric Madianga if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) { 70790ec93cbSBenjamin Gaignard dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan); 7088d1b76f0SM'boumba Cedric Madianga stm32_dma_start_transfer(chan); 709e57cb3b3SPierre Yves MORDRET 710d8b46839SM'boumba Cedric Madianga } 711d8b46839SM'boumba Cedric Madianga spin_unlock_irqrestore(&chan->vchan.lock, flags); 712d8b46839SM'boumba Cedric Madianga } 713d8b46839SM'boumba Cedric Madianga 714d8b46839SM'boumba Cedric Madianga static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan, 715d8b46839SM'boumba Cedric Madianga enum dma_transfer_direction direction, 716a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth *buswidth, 717e0ebdbdcSAmelie Delaunay u32 buf_len, dma_addr_t buf_addr) 718d8b46839SM'boumba Cedric Madianga { 719d8b46839SM'boumba Cedric Madianga enum dma_slave_buswidth src_addr_width, dst_addr_width; 720d8b46839SM'boumba Cedric Madianga int src_bus_width, dst_bus_width; 721d8b46839SM'boumba Cedric Madianga int src_burst_size, dst_burst_size; 722a2b6103bSPierre Yves MORDRET u32 src_maxburst, dst_maxburst, src_best_burst, dst_best_burst; 723955b1766SAmelie Delaunay u32 dma_scr, fifoth; 724d8b46839SM'boumba Cedric Madianga 725d8b46839SM'boumba Cedric Madianga src_addr_width = chan->dma_sconfig.src_addr_width; 726d8b46839SM'boumba Cedric Madianga dst_addr_width = chan->dma_sconfig.dst_addr_width; 727d8b46839SM'boumba Cedric Madianga src_maxburst = chan->dma_sconfig.src_maxburst; 728d8b46839SM'boumba Cedric Madianga dst_maxburst = chan->dma_sconfig.dst_maxburst; 729955b1766SAmelie Delaunay fifoth = chan->threshold; 730d8b46839SM'boumba Cedric Madianga 731d8b46839SM'boumba Cedric Madianga switch (direction) { 732d8b46839SM'boumba Cedric Madianga case DMA_MEM_TO_DEV: 733a2b6103bSPierre Yves MORDRET /* Set device data size */ 734d8b46839SM'boumba Cedric Madianga dst_bus_width = stm32_dma_get_width(chan, dst_addr_width); 735d8b46839SM'boumba Cedric Madianga if (dst_bus_width < 0) 736d8b46839SM'boumba Cedric Madianga return dst_bus_width; 737d8b46839SM'boumba Cedric Madianga 738a2b6103bSPierre Yves MORDRET /* Set device burst size */ 739a2b6103bSPierre Yves MORDRET dst_best_burst = stm32_dma_get_best_burst(buf_len, 740a2b6103bSPierre Yves MORDRET dst_maxburst, 741955b1766SAmelie Delaunay fifoth, 742a2b6103bSPierre Yves MORDRET dst_addr_width); 743a2b6103bSPierre Yves MORDRET 744a2b6103bSPierre Yves MORDRET dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst); 745d8b46839SM'boumba Cedric Madianga if (dst_burst_size < 0) 746d8b46839SM'boumba Cedric Madianga return dst_burst_size; 747d8b46839SM'boumba Cedric Madianga 748a2b6103bSPierre Yves MORDRET /* Set memory data size */ 749e0ebdbdcSAmelie Delaunay src_addr_width = stm32_dma_get_max_width(buf_len, buf_addr, 750e0ebdbdcSAmelie Delaunay fifoth); 751a2b6103bSPierre Yves MORDRET chan->mem_width = src_addr_width; 752d8b46839SM'boumba Cedric Madianga src_bus_width = stm32_dma_get_width(chan, src_addr_width); 753d8b46839SM'boumba Cedric Madianga if (src_bus_width < 0) 754d8b46839SM'boumba Cedric Madianga return src_bus_width; 755d8b46839SM'boumba Cedric Madianga 756af229d2cSAmelie Delaunay /* 757af229d2cSAmelie Delaunay * Set memory burst size - burst not possible if address is not aligned on 758af229d2cSAmelie Delaunay * the address boundary equal to the size of the transfer 759af229d2cSAmelie Delaunay */ 760*24983633SArnd Bergmann if (buf_addr & (buf_len - 1)) 761af229d2cSAmelie Delaunay src_maxburst = 1; 762af229d2cSAmelie Delaunay else 763a2b6103bSPierre Yves MORDRET src_maxburst = STM32_DMA_MAX_BURST; 764a2b6103bSPierre Yves MORDRET src_best_burst = stm32_dma_get_best_burst(buf_len, 765a2b6103bSPierre Yves MORDRET src_maxburst, 766955b1766SAmelie Delaunay fifoth, 767a2b6103bSPierre Yves MORDRET src_addr_width); 768a2b6103bSPierre Yves MORDRET src_burst_size = stm32_dma_get_burst(chan, src_best_burst); 769d8b46839SM'boumba Cedric Madianga if (src_burst_size < 0) 770d8b46839SM'boumba Cedric Madianga return src_burst_size; 771d8b46839SM'boumba Cedric Madianga 772d8b46839SM'boumba Cedric Madianga dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_DEV) | 773d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PSIZE(dst_bus_width) | 774d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MSIZE(src_bus_width) | 775d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PBURST(dst_burst_size) | 776d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MBURST(src_burst_size); 777d8b46839SM'boumba Cedric Madianga 778a2b6103bSPierre Yves MORDRET /* Set FIFO threshold */ 779a2b6103bSPierre Yves MORDRET chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; 780955b1766SAmelie Delaunay if (fifoth != STM32_DMA_FIFO_THRESHOLD_NONE) 781955b1766SAmelie Delaunay chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth); 782a2b6103bSPierre Yves MORDRET 783a2b6103bSPierre Yves MORDRET /* Set peripheral address */ 784d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr; 785d8b46839SM'boumba Cedric Madianga *buswidth = dst_addr_width; 786d8b46839SM'boumba Cedric Madianga break; 787d8b46839SM'boumba Cedric Madianga 788d8b46839SM'boumba Cedric Madianga case DMA_DEV_TO_MEM: 789a2b6103bSPierre Yves MORDRET /* Set device data size */ 790d8b46839SM'boumba Cedric Madianga src_bus_width = stm32_dma_get_width(chan, src_addr_width); 791d8b46839SM'boumba Cedric Madianga if (src_bus_width < 0) 792d8b46839SM'boumba Cedric Madianga return src_bus_width; 793d8b46839SM'boumba Cedric Madianga 794a2b6103bSPierre Yves MORDRET /* Set device burst size */ 795a2b6103bSPierre Yves MORDRET src_best_burst = stm32_dma_get_best_burst(buf_len, 796a2b6103bSPierre Yves MORDRET src_maxburst, 797955b1766SAmelie Delaunay fifoth, 798a2b6103bSPierre Yves MORDRET src_addr_width); 799a2b6103bSPierre Yves MORDRET chan->mem_burst = src_best_burst; 800a2b6103bSPierre Yves MORDRET src_burst_size = stm32_dma_get_burst(chan, src_best_burst); 801d8b46839SM'boumba Cedric Madianga if (src_burst_size < 0) 802d8b46839SM'boumba Cedric Madianga return src_burst_size; 803d8b46839SM'boumba Cedric Madianga 804a2b6103bSPierre Yves MORDRET /* Set memory data size */ 805e0ebdbdcSAmelie Delaunay dst_addr_width = stm32_dma_get_max_width(buf_len, buf_addr, 806e0ebdbdcSAmelie Delaunay fifoth); 807a2b6103bSPierre Yves MORDRET chan->mem_width = dst_addr_width; 808d8b46839SM'boumba Cedric Madianga dst_bus_width = stm32_dma_get_width(chan, dst_addr_width); 809d8b46839SM'boumba Cedric Madianga if (dst_bus_width < 0) 810d8b46839SM'boumba Cedric Madianga return dst_bus_width; 811d8b46839SM'boumba Cedric Madianga 812af229d2cSAmelie Delaunay /* 813af229d2cSAmelie Delaunay * Set memory burst size - burst not possible if address is not aligned on 814af229d2cSAmelie Delaunay * the address boundary equal to the size of the transfer 815af229d2cSAmelie Delaunay */ 816*24983633SArnd Bergmann if (buf_addr & (buf_len - 1)) 817af229d2cSAmelie Delaunay dst_maxburst = 1; 818af229d2cSAmelie Delaunay else 819a2b6103bSPierre Yves MORDRET dst_maxburst = STM32_DMA_MAX_BURST; 820a2b6103bSPierre Yves MORDRET dst_best_burst = stm32_dma_get_best_burst(buf_len, 821a2b6103bSPierre Yves MORDRET dst_maxburst, 822955b1766SAmelie Delaunay fifoth, 823a2b6103bSPierre Yves MORDRET dst_addr_width); 824a2b6103bSPierre Yves MORDRET chan->mem_burst = dst_best_burst; 825a2b6103bSPierre Yves MORDRET dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst); 826d8b46839SM'boumba Cedric Madianga if (dst_burst_size < 0) 827d8b46839SM'boumba Cedric Madianga return dst_burst_size; 828d8b46839SM'boumba Cedric Madianga 829d8b46839SM'boumba Cedric Madianga dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_DEV_TO_MEM) | 830d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PSIZE(src_bus_width) | 831d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MSIZE(dst_bus_width) | 832d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PBURST(src_burst_size) | 833d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MBURST(dst_burst_size); 834d8b46839SM'boumba Cedric Madianga 835a2b6103bSPierre Yves MORDRET /* Set FIFO threshold */ 836a2b6103bSPierre Yves MORDRET chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; 837955b1766SAmelie Delaunay if (fifoth != STM32_DMA_FIFO_THRESHOLD_NONE) 838955b1766SAmelie Delaunay chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth); 839a2b6103bSPierre Yves MORDRET 840a2b6103bSPierre Yves MORDRET /* Set peripheral address */ 841d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr; 842d8b46839SM'boumba Cedric Madianga *buswidth = chan->dma_sconfig.src_addr_width; 843d8b46839SM'boumba Cedric Madianga break; 844d8b46839SM'boumba Cedric Madianga 845d8b46839SM'boumba Cedric Madianga default: 846d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Dma direction is not supported\n"); 847d8b46839SM'boumba Cedric Madianga return -EINVAL; 848d8b46839SM'boumba Cedric Madianga } 849d8b46839SM'boumba Cedric Madianga 850a2b6103bSPierre Yves MORDRET stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst); 851d8b46839SM'boumba Cedric Madianga 852a2b6103bSPierre Yves MORDRET /* Set DMA control register */ 853d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK | 854d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PSIZE_MASK | STM32_DMA_SCR_MSIZE_MASK | 855d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PBURST_MASK | STM32_DMA_SCR_MBURST_MASK); 856d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= dma_scr; 857d8b46839SM'boumba Cedric Madianga 858d8b46839SM'boumba Cedric Madianga return 0; 859d8b46839SM'boumba Cedric Madianga } 860d8b46839SM'boumba Cedric Madianga 861d8b46839SM'boumba Cedric Madianga static void stm32_dma_clear_reg(struct stm32_dma_chan_reg *regs) 862d8b46839SM'boumba Cedric Madianga { 863d8b46839SM'boumba Cedric Madianga memset(regs, 0, sizeof(struct stm32_dma_chan_reg)); 864d8b46839SM'boumba Cedric Madianga } 865d8b46839SM'boumba Cedric Madianga 866d8b46839SM'boumba Cedric Madianga static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg( 867d8b46839SM'boumba Cedric Madianga struct dma_chan *c, struct scatterlist *sgl, 868d8b46839SM'boumba Cedric Madianga u32 sg_len, enum dma_transfer_direction direction, 869d8b46839SM'boumba Cedric Madianga unsigned long flags, void *context) 870d8b46839SM'boumba Cedric Madianga { 871d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 872d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc; 873d8b46839SM'boumba Cedric Madianga struct scatterlist *sg; 874d8b46839SM'boumba Cedric Madianga enum dma_slave_buswidth buswidth; 875d8b46839SM'boumba Cedric Madianga u32 nb_data_items; 876d8b46839SM'boumba Cedric Madianga int i, ret; 877d8b46839SM'boumba Cedric Madianga 878d8b46839SM'boumba Cedric Madianga if (!chan->config_init) { 879d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "dma channel is not configured\n"); 880d8b46839SM'boumba Cedric Madianga return NULL; 881d8b46839SM'boumba Cedric Madianga } 882d8b46839SM'boumba Cedric Madianga 883d8b46839SM'boumba Cedric Madianga if (sg_len < 1) { 884d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len); 885d8b46839SM'boumba Cedric Madianga return NULL; 886d8b46839SM'boumba Cedric Madianga } 887d8b46839SM'boumba Cedric Madianga 888402096cbSGustavo A. R. Silva desc = kzalloc(struct_size(desc, sg_req, sg_len), GFP_NOWAIT); 889d8b46839SM'boumba Cedric Madianga if (!desc) 890d8b46839SM'boumba Cedric Madianga return NULL; 891d8b46839SM'boumba Cedric Madianga 892d8b46839SM'boumba Cedric Madianga /* Set peripheral flow controller */ 893d8b46839SM'boumba Cedric Madianga if (chan->dma_sconfig.device_fc) 894d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL; 895d8b46839SM'boumba Cedric Madianga else 896d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; 897d8b46839SM'boumba Cedric Madianga 898d8b46839SM'boumba Cedric Madianga for_each_sg(sgl, sg, sg_len, i) { 899a2b6103bSPierre Yves MORDRET ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, 900e0ebdbdcSAmelie Delaunay sg_dma_len(sg), 901e0ebdbdcSAmelie Delaunay sg_dma_address(sg)); 902a2b6103bSPierre Yves MORDRET if (ret < 0) 903a2b6103bSPierre Yves MORDRET goto err; 904a2b6103bSPierre Yves MORDRET 905d8b46839SM'boumba Cedric Madianga desc->sg_req[i].len = sg_dma_len(sg); 906d8b46839SM'boumba Cedric Madianga 907d8b46839SM'boumba Cedric Madianga nb_data_items = desc->sg_req[i].len / buswidth; 90880a76952SPierre Yves MORDRET if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) { 909d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "nb items not supported\n"); 910d8b46839SM'boumba Cedric Madianga goto err; 911d8b46839SM'boumba Cedric Madianga } 912d8b46839SM'boumba Cedric Madianga 913d8b46839SM'boumba Cedric Madianga stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); 914d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; 915d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; 916d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; 917d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg); 918d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg); 919d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items; 920d8b46839SM'boumba Cedric Madianga } 921d8b46839SM'boumba Cedric Madianga 922d8b46839SM'boumba Cedric Madianga desc->num_sgs = sg_len; 923d8b46839SM'boumba Cedric Madianga desc->cyclic = false; 924d8b46839SM'boumba Cedric Madianga 925d8b46839SM'boumba Cedric Madianga return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); 926d8b46839SM'boumba Cedric Madianga 927d8b46839SM'boumba Cedric Madianga err: 928d8b46839SM'boumba Cedric Madianga kfree(desc); 929d8b46839SM'boumba Cedric Madianga return NULL; 930d8b46839SM'boumba Cedric Madianga } 931d8b46839SM'boumba Cedric Madianga 932d8b46839SM'boumba Cedric Madianga static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic( 933d8b46839SM'boumba Cedric Madianga struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len, 934d8b46839SM'boumba Cedric Madianga size_t period_len, enum dma_transfer_direction direction, 935d8b46839SM'boumba Cedric Madianga unsigned long flags) 936d8b46839SM'boumba Cedric Madianga { 937d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 938d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc; 939d8b46839SM'boumba Cedric Madianga enum dma_slave_buswidth buswidth; 940d8b46839SM'boumba Cedric Madianga u32 num_periods, nb_data_items; 941d8b46839SM'boumba Cedric Madianga int i, ret; 942d8b46839SM'boumba Cedric Madianga 943d8b46839SM'boumba Cedric Madianga if (!buf_len || !period_len) { 944d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Invalid buffer/period len\n"); 945d8b46839SM'boumba Cedric Madianga return NULL; 946d8b46839SM'boumba Cedric Madianga } 947d8b46839SM'boumba Cedric Madianga 948d8b46839SM'boumba Cedric Madianga if (!chan->config_init) { 949d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "dma channel is not configured\n"); 950d8b46839SM'boumba Cedric Madianga return NULL; 951d8b46839SM'boumba Cedric Madianga } 952d8b46839SM'boumba Cedric Madianga 953d8b46839SM'boumba Cedric Madianga if (buf_len % period_len) { 954d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "buf_len not multiple of period_len\n"); 955d8b46839SM'boumba Cedric Madianga return NULL; 956d8b46839SM'boumba Cedric Madianga } 957d8b46839SM'boumba Cedric Madianga 958d8b46839SM'boumba Cedric Madianga /* 959d8b46839SM'boumba Cedric Madianga * We allow to take more number of requests till DMA is 960d8b46839SM'boumba Cedric Madianga * not started. The driver will loop over all requests. 961d8b46839SM'boumba Cedric Madianga * Once DMA is started then new requests can be queued only after 962d8b46839SM'boumba Cedric Madianga * terminating the DMA. 963d8b46839SM'boumba Cedric Madianga */ 964d8b46839SM'boumba Cedric Madianga if (chan->busy) { 965d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Request not allowed when dma busy\n"); 966d8b46839SM'boumba Cedric Madianga return NULL; 967d8b46839SM'boumba Cedric Madianga } 968d8b46839SM'boumba Cedric Madianga 969e0ebdbdcSAmelie Delaunay ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len, 970e0ebdbdcSAmelie Delaunay buf_addr); 971d8b46839SM'boumba Cedric Madianga if (ret < 0) 972d8b46839SM'boumba Cedric Madianga return NULL; 973d8b46839SM'boumba Cedric Madianga 974d8b46839SM'boumba Cedric Madianga nb_data_items = period_len / buswidth; 97580a76952SPierre Yves MORDRET if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) { 976d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "number of items not supported\n"); 977d8b46839SM'boumba Cedric Madianga return NULL; 978d8b46839SM'boumba Cedric Madianga } 979d8b46839SM'boumba Cedric Madianga 980d8b46839SM'boumba Cedric Madianga /* Enable Circular mode or double buffer mode */ 981d8b46839SM'boumba Cedric Madianga if (buf_len == period_len) 982d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC; 983d8b46839SM'boumba Cedric Madianga else 984d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM; 985d8b46839SM'boumba Cedric Madianga 986d8b46839SM'boumba Cedric Madianga /* Clear periph ctrl if client set it */ 987d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; 988d8b46839SM'boumba Cedric Madianga 989d8b46839SM'boumba Cedric Madianga num_periods = buf_len / period_len; 990d8b46839SM'boumba Cedric Madianga 991402096cbSGustavo A. R. Silva desc = kzalloc(struct_size(desc, sg_req, num_periods), GFP_NOWAIT); 992d8b46839SM'boumba Cedric Madianga if (!desc) 993d8b46839SM'boumba Cedric Madianga return NULL; 994d8b46839SM'boumba Cedric Madianga 995d8b46839SM'boumba Cedric Madianga for (i = 0; i < num_periods; i++) { 996d8b46839SM'boumba Cedric Madianga desc->sg_req[i].len = period_len; 997d8b46839SM'boumba Cedric Madianga 998d8b46839SM'boumba Cedric Madianga stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); 999d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; 1000d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; 1001d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; 1002d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr; 1003d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr; 1004d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items; 1005d8b46839SM'boumba Cedric Madianga buf_addr += period_len; 1006d8b46839SM'boumba Cedric Madianga } 1007d8b46839SM'boumba Cedric Madianga 1008d8b46839SM'boumba Cedric Madianga desc->num_sgs = num_periods; 1009d8b46839SM'boumba Cedric Madianga desc->cyclic = true; 1010d8b46839SM'boumba Cedric Madianga 1011d8b46839SM'boumba Cedric Madianga return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); 1012d8b46839SM'boumba Cedric Madianga } 1013d8b46839SM'boumba Cedric Madianga 1014d8b46839SM'boumba Cedric Madianga static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy( 1015d8b46839SM'boumba Cedric Madianga struct dma_chan *c, dma_addr_t dest, 1016d8b46839SM'boumba Cedric Madianga dma_addr_t src, size_t len, unsigned long flags) 1017d8b46839SM'boumba Cedric Madianga { 1018d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1019a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth max_width; 1020d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc; 1021d8b46839SM'boumba Cedric Madianga size_t xfer_count, offset; 1022a2b6103bSPierre Yves MORDRET u32 num_sgs, best_burst, dma_burst, threshold; 1023d8b46839SM'boumba Cedric Madianga int i; 1024d8b46839SM'boumba Cedric Madianga 102580a76952SPierre Yves MORDRET num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS); 1026402096cbSGustavo A. R. Silva desc = kzalloc(struct_size(desc, sg_req, num_sgs), GFP_NOWAIT); 1027d8b46839SM'boumba Cedric Madianga if (!desc) 1028d8b46839SM'boumba Cedric Madianga return NULL; 1029d8b46839SM'boumba Cedric Madianga 1030a2b6103bSPierre Yves MORDRET threshold = chan->threshold; 1031a2b6103bSPierre Yves MORDRET 1032d8b46839SM'boumba Cedric Madianga for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) { 1033d8b46839SM'boumba Cedric Madianga xfer_count = min_t(size_t, len - offset, 103480a76952SPierre Yves MORDRET STM32_DMA_ALIGNED_MAX_DATA_ITEMS); 1035d8b46839SM'boumba Cedric Madianga 1036a2b6103bSPierre Yves MORDRET /* Compute best burst size */ 1037a2b6103bSPierre Yves MORDRET max_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1038a2b6103bSPierre Yves MORDRET best_burst = stm32_dma_get_best_burst(len, STM32_DMA_MAX_BURST, 1039a2b6103bSPierre Yves MORDRET threshold, max_width); 1040a2b6103bSPierre Yves MORDRET dma_burst = stm32_dma_get_burst(chan, best_burst); 1041d8b46839SM'boumba Cedric Madianga 1042d8b46839SM'boumba Cedric Madianga stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); 1043d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_scr = 1044d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_MEM) | 1045a2b6103bSPierre Yves MORDRET STM32_DMA_SCR_PBURST(dma_burst) | 1046a2b6103bSPierre Yves MORDRET STM32_DMA_SCR_MBURST(dma_burst) | 1047d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MINC | 1048d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PINC | 1049d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_TCIE | 1050d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_TEIE; 1051a2b6103bSPierre Yves MORDRET desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; 1052a2b6103bSPierre Yves MORDRET desc->sg_req[i].chan_reg.dma_sfcr |= 1053a2b6103bSPierre Yves MORDRET STM32_DMA_SFCR_FTH(threshold); 1054d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_spar = src + offset; 1055d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset; 1056d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sndtr = xfer_count; 1057a2b6103bSPierre Yves MORDRET desc->sg_req[i].len = xfer_count; 1058d8b46839SM'boumba Cedric Madianga } 1059d8b46839SM'boumba Cedric Madianga 1060d8b46839SM'boumba Cedric Madianga desc->num_sgs = num_sgs; 1061d8b46839SM'boumba Cedric Madianga desc->cyclic = false; 1062d8b46839SM'boumba Cedric Madianga 1063d8b46839SM'boumba Cedric Madianga return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); 1064d8b46839SM'boumba Cedric Madianga } 1065d8b46839SM'boumba Cedric Madianga 10662b12c558SM'boumba Cedric Madianga static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan) 10672b12c558SM'boumba Cedric Madianga { 10682b12c558SM'boumba Cedric Madianga u32 dma_scr, width, ndtr; 10692b12c558SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 10702b12c558SM'boumba Cedric Madianga 10712b12c558SM'boumba Cedric Madianga dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 10722b12c558SM'boumba Cedric Madianga width = STM32_DMA_SCR_PSIZE_GET(dma_scr); 10732b12c558SM'boumba Cedric Madianga ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); 10742b12c558SM'boumba Cedric Madianga 10752b12c558SM'boumba Cedric Madianga return ndtr << width; 10762b12c558SM'boumba Cedric Madianga } 10772b12c558SM'boumba Cedric Madianga 10782a4885abSArnaud Pouliquen /** 10792a4885abSArnaud Pouliquen * stm32_dma_is_current_sg - check that expected sg_req is currently transferred 10802a4885abSArnaud Pouliquen * @chan: dma channel 10812a4885abSArnaud Pouliquen * 10822a4885abSArnaud Pouliquen * This function called when IRQ are disable, checks that the hardware has not 10832a4885abSArnaud Pouliquen * switched on the next transfer in double buffer mode. The test is done by 10842a4885abSArnaud Pouliquen * comparing the next_sg memory address with the hardware related register 10852a4885abSArnaud Pouliquen * (based on CT bit value). 10862a4885abSArnaud Pouliquen * 10872a4885abSArnaud Pouliquen * Returns true if expected current transfer is still running or double 10882a4885abSArnaud Pouliquen * buffer mode is not activated. 10892a4885abSArnaud Pouliquen */ 10902a4885abSArnaud Pouliquen static bool stm32_dma_is_current_sg(struct stm32_dma_chan *chan) 10912a4885abSArnaud Pouliquen { 10922a4885abSArnaud Pouliquen struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 10932a4885abSArnaud Pouliquen struct stm32_dma_sg_req *sg_req; 10942a4885abSArnaud Pouliquen u32 dma_scr, dma_smar, id; 10952a4885abSArnaud Pouliquen 10962a4885abSArnaud Pouliquen id = chan->id; 10972a4885abSArnaud Pouliquen dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); 10982a4885abSArnaud Pouliquen 10992a4885abSArnaud Pouliquen if (!(dma_scr & STM32_DMA_SCR_DBM)) 11002a4885abSArnaud Pouliquen return true; 11012a4885abSArnaud Pouliquen 11022a4885abSArnaud Pouliquen sg_req = &chan->desc->sg_req[chan->next_sg]; 11032a4885abSArnaud Pouliquen 11042a4885abSArnaud Pouliquen if (dma_scr & STM32_DMA_SCR_CT) { 11052a4885abSArnaud Pouliquen dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)); 11062a4885abSArnaud Pouliquen return (dma_smar == sg_req->chan_reg.dma_sm0ar); 11072a4885abSArnaud Pouliquen } 11082a4885abSArnaud Pouliquen 11092a4885abSArnaud Pouliquen dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)); 11102a4885abSArnaud Pouliquen 11112a4885abSArnaud Pouliquen return (dma_smar == sg_req->chan_reg.dma_sm1ar); 11122a4885abSArnaud Pouliquen } 11132a4885abSArnaud Pouliquen 1114d8b46839SM'boumba Cedric Madianga static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan, 1115d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc, 1116d8b46839SM'boumba Cedric Madianga u32 next_sg) 1117d8b46839SM'boumba Cedric Madianga { 1118a2b6103bSPierre Yves MORDRET u32 modulo, burst_size; 11192a4885abSArnaud Pouliquen u32 residue; 11202a4885abSArnaud Pouliquen u32 n_sg = next_sg; 11212a4885abSArnaud Pouliquen struct stm32_dma_sg_req *sg_req = &chan->desc->sg_req[chan->next_sg]; 1122d8b46839SM'boumba Cedric Madianga int i; 1123d8b46839SM'boumba Cedric Madianga 11242b12c558SM'boumba Cedric Madianga /* 11252a4885abSArnaud Pouliquen * Calculate the residue means compute the descriptors 11262a4885abSArnaud Pouliquen * information: 11272a4885abSArnaud Pouliquen * - the sg_req currently transferred 11282a4885abSArnaud Pouliquen * - the Hardware remaining position in this sg (NDTR bits field). 11292a4885abSArnaud Pouliquen * 11302a4885abSArnaud Pouliquen * A race condition may occur if DMA is running in cyclic or double 11312a4885abSArnaud Pouliquen * buffer mode, since the DMA register are automatically reloaded at end 11322a4885abSArnaud Pouliquen * of period transfer. The hardware may have switched to the next 11332a4885abSArnaud Pouliquen * transfer (CT bit updated) just before the position (SxNDTR reg) is 11342a4885abSArnaud Pouliquen * read. 11352a4885abSArnaud Pouliquen * In this case the SxNDTR reg could (or not) correspond to the new 11362a4885abSArnaud Pouliquen * transfer position, and not the expected one. 11372a4885abSArnaud Pouliquen * The strategy implemented in the stm32 driver is to: 11382a4885abSArnaud Pouliquen * - read the SxNDTR register 11392a4885abSArnaud Pouliquen * - crosscheck that hardware is still in current transfer. 11402a4885abSArnaud Pouliquen * In case of switch, we can assume that the DMA is at the beginning of 11412a4885abSArnaud Pouliquen * the next transfer. So we approximate the residue in consequence, by 11422a4885abSArnaud Pouliquen * pointing on the beginning of next transfer. 11432a4885abSArnaud Pouliquen * 11442a4885abSArnaud Pouliquen * This race condition doesn't apply for none cyclic mode, as double 11452a4885abSArnaud Pouliquen * buffer is not used. In such situation registers are updated by the 11462a4885abSArnaud Pouliquen * software. 11472b12c558SM'boumba Cedric Madianga */ 11482a4885abSArnaud Pouliquen 1149a2b6103bSPierre Yves MORDRET residue = stm32_dma_get_remaining_bytes(chan); 11502a4885abSArnaud Pouliquen 11512a4885abSArnaud Pouliquen if (!stm32_dma_is_current_sg(chan)) { 11522a4885abSArnaud Pouliquen n_sg++; 11532a4885abSArnaud Pouliquen if (n_sg == chan->desc->num_sgs) 11542a4885abSArnaud Pouliquen n_sg = 0; 11552a4885abSArnaud Pouliquen residue = sg_req->len; 1156a2b6103bSPierre Yves MORDRET } 1157d8b46839SM'boumba Cedric Madianga 11582b12c558SM'boumba Cedric Madianga /* 11592a4885abSArnaud Pouliquen * In cyclic mode, for the last period, residue = remaining bytes 11602a4885abSArnaud Pouliquen * from NDTR, 11612a4885abSArnaud Pouliquen * else for all other periods in cyclic mode, and in sg mode, 11622a4885abSArnaud Pouliquen * residue = remaining bytes from NDTR + remaining 11632a4885abSArnaud Pouliquen * periods/sg to be transferred 11642b12c558SM'boumba Cedric Madianga */ 11652a4885abSArnaud Pouliquen if (!chan->desc->cyclic || n_sg != 0) 11662a4885abSArnaud Pouliquen for (i = n_sg; i < desc->num_sgs; i++) 1167d8b46839SM'boumba Cedric Madianga residue += desc->sg_req[i].len; 1168d8b46839SM'boumba Cedric Madianga 1169a2b6103bSPierre Yves MORDRET if (!chan->mem_burst) 1170a2b6103bSPierre Yves MORDRET return residue; 1171a2b6103bSPierre Yves MORDRET 1172a2b6103bSPierre Yves MORDRET burst_size = chan->mem_burst * chan->mem_width; 1173a2b6103bSPierre Yves MORDRET modulo = residue % burst_size; 1174a2b6103bSPierre Yves MORDRET if (modulo) 1175a2b6103bSPierre Yves MORDRET residue = residue - modulo + burst_size; 1176a2b6103bSPierre Yves MORDRET 1177d8b46839SM'boumba Cedric Madianga return residue; 1178d8b46839SM'boumba Cedric Madianga } 1179d8b46839SM'boumba Cedric Madianga 1180d8b46839SM'boumba Cedric Madianga static enum dma_status stm32_dma_tx_status(struct dma_chan *c, 1181d8b46839SM'boumba Cedric Madianga dma_cookie_t cookie, 1182d8b46839SM'boumba Cedric Madianga struct dma_tx_state *state) 1183d8b46839SM'boumba Cedric Madianga { 1184d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1185d8b46839SM'boumba Cedric Madianga struct virt_dma_desc *vdesc; 1186d8b46839SM'boumba Cedric Madianga enum dma_status status; 1187d8b46839SM'boumba Cedric Madianga unsigned long flags; 118857b5a321SM'boumba Cedric Madianga u32 residue = 0; 1189d8b46839SM'boumba Cedric Madianga 1190d8b46839SM'boumba Cedric Madianga status = dma_cookie_status(c, cookie, state); 1191249d5531SPierre Yves MORDRET if (status == DMA_COMPLETE || !state) 1192d8b46839SM'boumba Cedric Madianga return status; 1193d8b46839SM'boumba Cedric Madianga 1194d8b46839SM'boumba Cedric Madianga spin_lock_irqsave(&chan->vchan.lock, flags); 1195d8b46839SM'boumba Cedric Madianga vdesc = vchan_find_desc(&chan->vchan, cookie); 119657b5a321SM'boumba Cedric Madianga if (chan->desc && cookie == chan->desc->vdesc.tx.cookie) 1197d8b46839SM'boumba Cedric Madianga residue = stm32_dma_desc_residue(chan, chan->desc, 1198d8b46839SM'boumba Cedric Madianga chan->next_sg); 119957b5a321SM'boumba Cedric Madianga else if (vdesc) 1200d8b46839SM'boumba Cedric Madianga residue = stm32_dma_desc_residue(chan, 1201d8b46839SM'boumba Cedric Madianga to_stm32_dma_desc(vdesc), 0); 1202d8b46839SM'boumba Cedric Madianga dma_set_residue(state, residue); 1203d8b46839SM'boumba Cedric Madianga 1204d8b46839SM'boumba Cedric Madianga spin_unlock_irqrestore(&chan->vchan.lock, flags); 1205d8b46839SM'boumba Cedric Madianga 1206d8b46839SM'boumba Cedric Madianga return status; 1207d8b46839SM'boumba Cedric Madianga } 1208d8b46839SM'boumba Cedric Madianga 1209d8b46839SM'boumba Cedric Madianga static int stm32_dma_alloc_chan_resources(struct dma_chan *c) 1210d8b46839SM'boumba Cedric Madianga { 1211d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1212d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 1213d8b46839SM'boumba Cedric Madianga int ret; 1214d8b46839SM'boumba Cedric Madianga 1215d8b46839SM'boumba Cedric Madianga chan->config_init = false; 121648bc73baSPierre-Yves MORDRET 1217d54db74aSZhang Qilong ret = pm_runtime_resume_and_get(dmadev->ddev.dev); 121848bc73baSPierre-Yves MORDRET if (ret < 0) 1219d8b46839SM'boumba Cedric Madianga return ret; 1220d8b46839SM'boumba Cedric Madianga 1221d8b46839SM'boumba Cedric Madianga ret = stm32_dma_disable_chan(chan); 1222d8b46839SM'boumba Cedric Madianga if (ret < 0) 122348bc73baSPierre-Yves MORDRET pm_runtime_put(dmadev->ddev.dev); 1224d8b46839SM'boumba Cedric Madianga 1225d8b46839SM'boumba Cedric Madianga return ret; 1226d8b46839SM'boumba Cedric Madianga } 1227d8b46839SM'boumba Cedric Madianga 1228d8b46839SM'boumba Cedric Madianga static void stm32_dma_free_chan_resources(struct dma_chan *c) 1229d8b46839SM'boumba Cedric Madianga { 1230d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1231d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 1232d8b46839SM'boumba Cedric Madianga unsigned long flags; 1233d8b46839SM'boumba Cedric Madianga 1234d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id); 1235d8b46839SM'boumba Cedric Madianga 1236d8b46839SM'boumba Cedric Madianga if (chan->busy) { 1237d8b46839SM'boumba Cedric Madianga spin_lock_irqsave(&chan->vchan.lock, flags); 1238d8b46839SM'boumba Cedric Madianga stm32_dma_stop(chan); 1239d8b46839SM'boumba Cedric Madianga chan->desc = NULL; 1240d8b46839SM'boumba Cedric Madianga spin_unlock_irqrestore(&chan->vchan.lock, flags); 1241d8b46839SM'boumba Cedric Madianga } 1242d8b46839SM'boumba Cedric Madianga 124348bc73baSPierre-Yves MORDRET pm_runtime_put(dmadev->ddev.dev); 1244d8b46839SM'boumba Cedric Madianga 1245d8b46839SM'boumba Cedric Madianga vchan_free_chan_resources(to_virt_chan(c)); 12465d4d4dfbSAmelie Delaunay stm32_dma_clear_reg(&chan->chan_reg); 12475d4d4dfbSAmelie Delaunay chan->threshold = 0; 1248d8b46839SM'boumba Cedric Madianga } 1249d8b46839SM'boumba Cedric Madianga 1250d8b46839SM'boumba Cedric Madianga static void stm32_dma_desc_free(struct virt_dma_desc *vdesc) 1251d8b46839SM'boumba Cedric Madianga { 1252d8b46839SM'boumba Cedric Madianga kfree(container_of(vdesc, struct stm32_dma_desc, vdesc)); 1253d8b46839SM'boumba Cedric Madianga } 1254d8b46839SM'boumba Cedric Madianga 1255e97adb49SVinod Koul static void stm32_dma_set_config(struct stm32_dma_chan *chan, 1256d8b46839SM'boumba Cedric Madianga struct stm32_dma_cfg *cfg) 1257d8b46839SM'boumba Cedric Madianga { 1258d8b46839SM'boumba Cedric Madianga stm32_dma_clear_reg(&chan->chan_reg); 1259d8b46839SM'boumba Cedric Madianga 1260d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK; 1261d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line); 1262d8b46839SM'boumba Cedric Madianga 1263d8b46839SM'boumba Cedric Madianga /* Enable Interrupts */ 1264d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE; 1265d8b46839SM'boumba Cedric Madianga 1266951f44cbSPierre Yves MORDRET chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features); 1267955b1766SAmelie Delaunay if (STM32_DMA_DIRECT_MODE_GET(cfg->features)) 1268955b1766SAmelie Delaunay chan->threshold = STM32_DMA_FIFO_THRESHOLD_NONE; 12692b5b7405SAmelie Delaunay if (STM32_DMA_ALT_ACK_MODE_GET(cfg->features)) 12702b5b7405SAmelie Delaunay chan->chan_reg.dma_scr |= STM32_DMA_SCR_TRBUFF; 1271d8b46839SM'boumba Cedric Madianga } 1272d8b46839SM'boumba Cedric Madianga 1273d8b46839SM'boumba Cedric Madianga static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec, 1274d8b46839SM'boumba Cedric Madianga struct of_dma *ofdma) 1275d8b46839SM'boumba Cedric Madianga { 1276d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = ofdma->of_dma_data; 12775df4eb45SM'boumba Cedric Madianga struct device *dev = dmadev->ddev.dev; 1278d8b46839SM'boumba Cedric Madianga struct stm32_dma_cfg cfg; 1279d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan; 1280d8b46839SM'boumba Cedric Madianga struct dma_chan *c; 1281d8b46839SM'boumba Cedric Madianga 12825df4eb45SM'boumba Cedric Madianga if (dma_spec->args_count < 4) { 12835df4eb45SM'boumba Cedric Madianga dev_err(dev, "Bad number of cells\n"); 1284d8b46839SM'boumba Cedric Madianga return NULL; 12855df4eb45SM'boumba Cedric Madianga } 1286d8b46839SM'boumba Cedric Madianga 1287d8b46839SM'boumba Cedric Madianga cfg.channel_id = dma_spec->args[0]; 1288d8b46839SM'boumba Cedric Madianga cfg.request_line = dma_spec->args[1]; 1289d8b46839SM'boumba Cedric Madianga cfg.stream_config = dma_spec->args[2]; 1290951f44cbSPierre Yves MORDRET cfg.features = dma_spec->args[3]; 1291d8b46839SM'boumba Cedric Madianga 1292249d5531SPierre Yves MORDRET if (cfg.channel_id >= STM32_DMA_MAX_CHANNELS || 1293249d5531SPierre Yves MORDRET cfg.request_line >= STM32_DMA_MAX_REQUEST_ID) { 12945df4eb45SM'boumba Cedric Madianga dev_err(dev, "Bad channel and/or request id\n"); 1295d8b46839SM'boumba Cedric Madianga return NULL; 12965df4eb45SM'boumba Cedric Madianga } 1297d8b46839SM'boumba Cedric Madianga 1298d8b46839SM'boumba Cedric Madianga chan = &dmadev->chan[cfg.channel_id]; 1299d8b46839SM'boumba Cedric Madianga 1300d8b46839SM'boumba Cedric Madianga c = dma_get_slave_channel(&chan->vchan.chan); 13015df4eb45SM'boumba Cedric Madianga if (!c) { 1302041cf7e0SColin Ian King dev_err(dev, "No more channels available\n"); 13035df4eb45SM'boumba Cedric Madianga return NULL; 13045df4eb45SM'boumba Cedric Madianga } 13055df4eb45SM'boumba Cedric Madianga 1306d8b46839SM'boumba Cedric Madianga stm32_dma_set_config(chan, &cfg); 1307d8b46839SM'boumba Cedric Madianga 1308d8b46839SM'boumba Cedric Madianga return c; 1309d8b46839SM'boumba Cedric Madianga } 1310d8b46839SM'boumba Cedric Madianga 1311d8b46839SM'boumba Cedric Madianga static const struct of_device_id stm32_dma_of_match[] = { 1312d8b46839SM'boumba Cedric Madianga { .compatible = "st,stm32-dma", }, 1313d8b46839SM'boumba Cedric Madianga { /* sentinel */ }, 1314d8b46839SM'boumba Cedric Madianga }; 1315d8b46839SM'boumba Cedric Madianga MODULE_DEVICE_TABLE(of, stm32_dma_of_match); 1316d8b46839SM'boumba Cedric Madianga 1317d8b46839SM'boumba Cedric Madianga static int stm32_dma_probe(struct platform_device *pdev) 1318d8b46839SM'boumba Cedric Madianga { 1319d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan; 1320d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev; 1321d8b46839SM'boumba Cedric Madianga struct dma_device *dd; 1322d8b46839SM'boumba Cedric Madianga const struct of_device_id *match; 1323d8b46839SM'boumba Cedric Madianga struct resource *res; 13248cf1e0fcSEtienne Carriere struct reset_control *rst; 1325d8b46839SM'boumba Cedric Madianga int i, ret; 1326d8b46839SM'boumba Cedric Madianga 1327d8b46839SM'boumba Cedric Madianga match = of_match_device(stm32_dma_of_match, &pdev->dev); 1328d8b46839SM'boumba Cedric Madianga if (!match) { 1329d8b46839SM'boumba Cedric Madianga dev_err(&pdev->dev, "Error: No device match found\n"); 1330d8b46839SM'boumba Cedric Madianga return -ENODEV; 1331d8b46839SM'boumba Cedric Madianga } 1332d8b46839SM'boumba Cedric Madianga 1333d8b46839SM'boumba Cedric Madianga dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL); 1334d8b46839SM'boumba Cedric Madianga if (!dmadev) 1335d8b46839SM'boumba Cedric Madianga return -ENOMEM; 1336d8b46839SM'boumba Cedric Madianga 1337d8b46839SM'boumba Cedric Madianga dd = &dmadev->ddev; 1338d8b46839SM'boumba Cedric Madianga 1339d8b46839SM'boumba Cedric Madianga res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1340d8b46839SM'boumba Cedric Madianga dmadev->base = devm_ioremap_resource(&pdev->dev, res); 1341d8b46839SM'boumba Cedric Madianga if (IS_ERR(dmadev->base)) 1342d8b46839SM'boumba Cedric Madianga return PTR_ERR(dmadev->base); 1343d8b46839SM'boumba Cedric Madianga 1344d8b46839SM'boumba Cedric Madianga dmadev->clk = devm_clk_get(&pdev->dev, NULL); 13451c966e1dSKrzysztof Kozlowski if (IS_ERR(dmadev->clk)) 13461c966e1dSKrzysztof Kozlowski return dev_err_probe(&pdev->dev, PTR_ERR(dmadev->clk), "Can't get clock\n"); 1347d8b46839SM'boumba Cedric Madianga 134848bc73baSPierre-Yves MORDRET ret = clk_prepare_enable(dmadev->clk); 134948bc73baSPierre-Yves MORDRET if (ret < 0) { 135048bc73baSPierre-Yves MORDRET dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret); 135148bc73baSPierre-Yves MORDRET return ret; 135248bc73baSPierre-Yves MORDRET } 135348bc73baSPierre-Yves MORDRET 1354d8b46839SM'boumba Cedric Madianga dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node, 1355d8b46839SM'boumba Cedric Madianga "st,mem2mem"); 1356d8b46839SM'boumba Cedric Madianga 13578cf1e0fcSEtienne Carriere rst = devm_reset_control_get(&pdev->dev, NULL); 1358615eee2cSEtienne Carriere if (IS_ERR(rst)) { 1359615eee2cSEtienne Carriere ret = PTR_ERR(rst); 1360615eee2cSEtienne Carriere if (ret == -EPROBE_DEFER) 1361615eee2cSEtienne Carriere goto clk_free; 1362615eee2cSEtienne Carriere } else { 13638cf1e0fcSEtienne Carriere reset_control_assert(rst); 1364d8b46839SM'boumba Cedric Madianga udelay(2); 13658cf1e0fcSEtienne Carriere reset_control_deassert(rst); 1366d8b46839SM'boumba Cedric Madianga } 1367d8b46839SM'boumba Cedric Madianga 1368d7a9e426SAmelie Delaunay dma_set_max_seg_size(&pdev->dev, STM32_DMA_ALIGNED_MAX_DATA_ITEMS); 1369d7a9e426SAmelie Delaunay 1370d8b46839SM'boumba Cedric Madianga dma_cap_set(DMA_SLAVE, dd->cap_mask); 1371d8b46839SM'boumba Cedric Madianga dma_cap_set(DMA_PRIVATE, dd->cap_mask); 1372d8b46839SM'boumba Cedric Madianga dma_cap_set(DMA_CYCLIC, dd->cap_mask); 1373d8b46839SM'boumba Cedric Madianga dd->device_alloc_chan_resources = stm32_dma_alloc_chan_resources; 1374d8b46839SM'boumba Cedric Madianga dd->device_free_chan_resources = stm32_dma_free_chan_resources; 1375d8b46839SM'boumba Cedric Madianga dd->device_tx_status = stm32_dma_tx_status; 1376d8b46839SM'boumba Cedric Madianga dd->device_issue_pending = stm32_dma_issue_pending; 1377d8b46839SM'boumba Cedric Madianga dd->device_prep_slave_sg = stm32_dma_prep_slave_sg; 1378d8b46839SM'boumba Cedric Madianga dd->device_prep_dma_cyclic = stm32_dma_prep_dma_cyclic; 1379d8b46839SM'boumba Cedric Madianga dd->device_config = stm32_dma_slave_config; 1380d8b46839SM'boumba Cedric Madianga dd->device_terminate_all = stm32_dma_terminate_all; 1381dc808675SM'boumba Cedric Madianga dd->device_synchronize = stm32_dma_synchronize; 1382d8b46839SM'boumba Cedric Madianga dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1383d8b46839SM'boumba Cedric Madianga BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1384d8b46839SM'boumba Cedric Madianga BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 1385d8b46839SM'boumba Cedric Madianga dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1386d8b46839SM'boumba Cedric Madianga BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1387d8b46839SM'boumba Cedric Madianga BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 1388d8b46839SM'boumba Cedric Madianga dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 1389d8b46839SM'boumba Cedric Madianga dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 139032ce1088SAmelie Delaunay dd->copy_align = DMAENGINE_ALIGN_32_BYTES; 1391276b0046SM'boumba Cedric Madianga dd->max_burst = STM32_DMA_MAX_BURST; 139222a0bb29SPierre-Yves MORDRET dd->descriptor_reuse = true; 1393d8b46839SM'boumba Cedric Madianga dd->dev = &pdev->dev; 1394d8b46839SM'boumba Cedric Madianga INIT_LIST_HEAD(&dd->channels); 1395d8b46839SM'boumba Cedric Madianga 1396d8b46839SM'boumba Cedric Madianga if (dmadev->mem2mem) { 1397d8b46839SM'boumba Cedric Madianga dma_cap_set(DMA_MEMCPY, dd->cap_mask); 1398d8b46839SM'boumba Cedric Madianga dd->device_prep_dma_memcpy = stm32_dma_prep_dma_memcpy; 1399d8b46839SM'boumba Cedric Madianga dd->directions |= BIT(DMA_MEM_TO_MEM); 1400d8b46839SM'boumba Cedric Madianga } 1401d8b46839SM'boumba Cedric Madianga 1402d8b46839SM'boumba Cedric Madianga for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) { 1403d8b46839SM'boumba Cedric Madianga chan = &dmadev->chan[i]; 1404d8b46839SM'boumba Cedric Madianga chan->id = i; 1405d8b46839SM'boumba Cedric Madianga chan->vchan.desc_free = stm32_dma_desc_free; 1406d8b46839SM'boumba Cedric Madianga vchan_init(&chan->vchan, dd); 1407d8b46839SM'boumba Cedric Madianga } 1408d8b46839SM'boumba Cedric Madianga 1409d8b46839SM'boumba Cedric Madianga ret = dma_async_device_register(dd); 1410d8b46839SM'boumba Cedric Madianga if (ret) 141148bc73baSPierre-Yves MORDRET goto clk_free; 1412d8b46839SM'boumba Cedric Madianga 1413d8b46839SM'boumba Cedric Madianga for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) { 1414d8b46839SM'boumba Cedric Madianga chan = &dmadev->chan[i]; 1415c6504be5SVinod Koul ret = platform_get_irq(pdev, i); 1416e17be6e1SStephen Boyd if (ret < 0) 1417d8b46839SM'boumba Cedric Madianga goto err_unregister; 1418c6504be5SVinod Koul chan->irq = ret; 1419c6504be5SVinod Koul 1420d8b46839SM'boumba Cedric Madianga ret = devm_request_irq(&pdev->dev, chan->irq, 1421d8b46839SM'boumba Cedric Madianga stm32_dma_chan_irq, 0, 1422d8b46839SM'boumba Cedric Madianga dev_name(chan2dev(chan)), chan); 1423d8b46839SM'boumba Cedric Madianga if (ret) { 1424d8b46839SM'boumba Cedric Madianga dev_err(&pdev->dev, 1425d8b46839SM'boumba Cedric Madianga "request_irq failed with err %d channel %d\n", 1426d8b46839SM'boumba Cedric Madianga ret, i); 1427d8b46839SM'boumba Cedric Madianga goto err_unregister; 1428d8b46839SM'boumba Cedric Madianga } 1429d8b46839SM'boumba Cedric Madianga } 1430d8b46839SM'boumba Cedric Madianga 1431d8b46839SM'boumba Cedric Madianga ret = of_dma_controller_register(pdev->dev.of_node, 1432d8b46839SM'boumba Cedric Madianga stm32_dma_of_xlate, dmadev); 1433d8b46839SM'boumba Cedric Madianga if (ret < 0) { 1434d8b46839SM'boumba Cedric Madianga dev_err(&pdev->dev, 1435d8b46839SM'boumba Cedric Madianga "STM32 DMA DMA OF registration failed %d\n", ret); 1436d8b46839SM'boumba Cedric Madianga goto err_unregister; 1437d8b46839SM'boumba Cedric Madianga } 1438d8b46839SM'boumba Cedric Madianga 1439d8b46839SM'boumba Cedric Madianga platform_set_drvdata(pdev, dmadev); 1440d8b46839SM'boumba Cedric Madianga 144148bc73baSPierre-Yves MORDRET pm_runtime_set_active(&pdev->dev); 144248bc73baSPierre-Yves MORDRET pm_runtime_enable(&pdev->dev); 144348bc73baSPierre-Yves MORDRET pm_runtime_get_noresume(&pdev->dev); 144448bc73baSPierre-Yves MORDRET pm_runtime_put(&pdev->dev); 144548bc73baSPierre-Yves MORDRET 1446d8b46839SM'boumba Cedric Madianga dev_info(&pdev->dev, "STM32 DMA driver registered\n"); 1447d8b46839SM'boumba Cedric Madianga 1448d8b46839SM'boumba Cedric Madianga return 0; 1449d8b46839SM'boumba Cedric Madianga 1450d8b46839SM'boumba Cedric Madianga err_unregister: 1451d8b46839SM'boumba Cedric Madianga dma_async_device_unregister(dd); 145248bc73baSPierre-Yves MORDRET clk_free: 145348bc73baSPierre-Yves MORDRET clk_disable_unprepare(dmadev->clk); 1454d8b46839SM'boumba Cedric Madianga 1455d8b46839SM'boumba Cedric Madianga return ret; 1456d8b46839SM'boumba Cedric Madianga } 1457d8b46839SM'boumba Cedric Madianga 145848bc73baSPierre-Yves MORDRET #ifdef CONFIG_PM 145948bc73baSPierre-Yves MORDRET static int stm32_dma_runtime_suspend(struct device *dev) 146048bc73baSPierre-Yves MORDRET { 146148bc73baSPierre-Yves MORDRET struct stm32_dma_device *dmadev = dev_get_drvdata(dev); 146248bc73baSPierre-Yves MORDRET 146348bc73baSPierre-Yves MORDRET clk_disable_unprepare(dmadev->clk); 146448bc73baSPierre-Yves MORDRET 146548bc73baSPierre-Yves MORDRET return 0; 146648bc73baSPierre-Yves MORDRET } 146748bc73baSPierre-Yves MORDRET 146848bc73baSPierre-Yves MORDRET static int stm32_dma_runtime_resume(struct device *dev) 146948bc73baSPierre-Yves MORDRET { 147048bc73baSPierre-Yves MORDRET struct stm32_dma_device *dmadev = dev_get_drvdata(dev); 147148bc73baSPierre-Yves MORDRET int ret; 147248bc73baSPierre-Yves MORDRET 147348bc73baSPierre-Yves MORDRET ret = clk_prepare_enable(dmadev->clk); 147448bc73baSPierre-Yves MORDRET if (ret) { 147548bc73baSPierre-Yves MORDRET dev_err(dev, "failed to prepare_enable clock\n"); 147648bc73baSPierre-Yves MORDRET return ret; 147748bc73baSPierre-Yves MORDRET } 147848bc73baSPierre-Yves MORDRET 147948bc73baSPierre-Yves MORDRET return 0; 148048bc73baSPierre-Yves MORDRET } 148148bc73baSPierre-Yves MORDRET #endif 148248bc73baSPierre-Yves MORDRET 148305f8740aSPierre-Yves MORDRET #ifdef CONFIG_PM_SLEEP 148405f8740aSPierre-Yves MORDRET static int stm32_dma_suspend(struct device *dev) 148505f8740aSPierre-Yves MORDRET { 148605f8740aSPierre-Yves MORDRET struct stm32_dma_device *dmadev = dev_get_drvdata(dev); 148705f8740aSPierre-Yves MORDRET int id, ret, scr; 148805f8740aSPierre-Yves MORDRET 1489d54db74aSZhang Qilong ret = pm_runtime_resume_and_get(dev); 149005f8740aSPierre-Yves MORDRET if (ret < 0) 149105f8740aSPierre-Yves MORDRET return ret; 149205f8740aSPierre-Yves MORDRET 149305f8740aSPierre-Yves MORDRET for (id = 0; id < STM32_DMA_MAX_CHANNELS; id++) { 149405f8740aSPierre-Yves MORDRET scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); 149505f8740aSPierre-Yves MORDRET if (scr & STM32_DMA_SCR_EN) { 149605f8740aSPierre-Yves MORDRET dev_warn(dev, "Suspend is prevented by Chan %i\n", id); 149705f8740aSPierre-Yves MORDRET return -EBUSY; 149805f8740aSPierre-Yves MORDRET } 149905f8740aSPierre-Yves MORDRET } 150005f8740aSPierre-Yves MORDRET 150105f8740aSPierre-Yves MORDRET pm_runtime_put_sync(dev); 150205f8740aSPierre-Yves MORDRET 150305f8740aSPierre-Yves MORDRET pm_runtime_force_suspend(dev); 150405f8740aSPierre-Yves MORDRET 150505f8740aSPierre-Yves MORDRET return 0; 150605f8740aSPierre-Yves MORDRET } 150705f8740aSPierre-Yves MORDRET 150805f8740aSPierre-Yves MORDRET static int stm32_dma_resume(struct device *dev) 150905f8740aSPierre-Yves MORDRET { 151005f8740aSPierre-Yves MORDRET return pm_runtime_force_resume(dev); 151105f8740aSPierre-Yves MORDRET } 151205f8740aSPierre-Yves MORDRET #endif 151305f8740aSPierre-Yves MORDRET 151448bc73baSPierre-Yves MORDRET static const struct dev_pm_ops stm32_dma_pm_ops = { 151505f8740aSPierre-Yves MORDRET SET_SYSTEM_SLEEP_PM_OPS(stm32_dma_suspend, stm32_dma_resume) 151648bc73baSPierre-Yves MORDRET SET_RUNTIME_PM_OPS(stm32_dma_runtime_suspend, 151748bc73baSPierre-Yves MORDRET stm32_dma_runtime_resume, NULL) 151848bc73baSPierre-Yves MORDRET }; 151948bc73baSPierre-Yves MORDRET 1520d8b46839SM'boumba Cedric Madianga static struct platform_driver stm32_dma_driver = { 1521d8b46839SM'boumba Cedric Madianga .driver = { 1522d8b46839SM'boumba Cedric Madianga .name = "stm32-dma", 1523d8b46839SM'boumba Cedric Madianga .of_match_table = stm32_dma_of_match, 152448bc73baSPierre-Yves MORDRET .pm = &stm32_dma_pm_ops, 1525d8b46839SM'boumba Cedric Madianga }, 1526615eee2cSEtienne Carriere .probe = stm32_dma_probe, 1527d8b46839SM'boumba Cedric Madianga }; 1528d8b46839SM'boumba Cedric Madianga 1529d8b46839SM'boumba Cedric Madianga static int __init stm32_dma_init(void) 1530d8b46839SM'boumba Cedric Madianga { 1531615eee2cSEtienne Carriere return platform_driver_register(&stm32_dma_driver); 1532d8b46839SM'boumba Cedric Madianga } 1533d8b46839SM'boumba Cedric Madianga subsys_initcall(stm32_dma_init); 1534