1af873fceSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2d8b46839SM'boumba Cedric Madianga /* 3d8b46839SM'boumba Cedric Madianga * Driver for STM32 DMA controller 4d8b46839SM'boumba Cedric Madianga * 5d8b46839SM'boumba Cedric Madianga * Inspired by dma-jz4740.c and tegra20-apb-dma.c 6d8b46839SM'boumba Cedric Madianga * 7d8b46839SM'boumba Cedric Madianga * Copyright (C) M'boumba Cedric Madianga 2015 8d8b46839SM'boumba Cedric Madianga * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com> 9a2b6103bSPierre Yves MORDRET * Pierre-Yves Mordret <pierre-yves.mordret@st.com> 10d8b46839SM'boumba Cedric Madianga */ 11d8b46839SM'boumba Cedric Madianga 12d8b46839SM'boumba Cedric Madianga #include <linux/clk.h> 13d8b46839SM'boumba Cedric Madianga #include <linux/delay.h> 14d8b46839SM'boumba Cedric Madianga #include <linux/dmaengine.h> 15d8b46839SM'boumba Cedric Madianga #include <linux/dma-mapping.h> 16d8b46839SM'boumba Cedric Madianga #include <linux/err.h> 17d8b46839SM'boumba Cedric Madianga #include <linux/init.h> 18409ffc4dSAmelie Delaunay #include <linux/iopoll.h> 19d8b46839SM'boumba Cedric Madianga #include <linux/jiffies.h> 20d8b46839SM'boumba Cedric Madianga #include <linux/list.h> 21d8b46839SM'boumba Cedric Madianga #include <linux/module.h> 22d8b46839SM'boumba Cedric Madianga #include <linux/of.h> 23d8b46839SM'boumba Cedric Madianga #include <linux/of_device.h> 24d8b46839SM'boumba Cedric Madianga #include <linux/of_dma.h> 25d8b46839SM'boumba Cedric Madianga #include <linux/platform_device.h> 2648bc73baSPierre-Yves MORDRET #include <linux/pm_runtime.h> 27d8b46839SM'boumba Cedric Madianga #include <linux/reset.h> 28d8b46839SM'boumba Cedric Madianga #include <linux/sched.h> 29d8b46839SM'boumba Cedric Madianga #include <linux/slab.h> 30d8b46839SM'boumba Cedric Madianga 31d8b46839SM'boumba Cedric Madianga #include "virt-dma.h" 32d8b46839SM'boumba Cedric Madianga 33d8b46839SM'boumba Cedric Madianga #define STM32_DMA_LISR 0x0000 /* DMA Low Int Status Reg */ 34d8b46839SM'boumba Cedric Madianga #define STM32_DMA_HISR 0x0004 /* DMA High Int Status Reg */ 35d8b46839SM'boumba Cedric Madianga #define STM32_DMA_LIFCR 0x0008 /* DMA Low Int Flag Clear Reg */ 36d8b46839SM'boumba Cedric Madianga #define STM32_DMA_HIFCR 0x000c /* DMA High Int Flag Clear Reg */ 37d8b46839SM'boumba Cedric Madianga #define STM32_DMA_TCI BIT(5) /* Transfer Complete Interrupt */ 38c2d86b1cSPierre Yves MORDRET #define STM32_DMA_HTI BIT(4) /* Half Transfer Interrupt */ 39d8b46839SM'boumba Cedric Madianga #define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */ 40d8b46839SM'boumba Cedric Madianga #define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */ 41d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */ 429df3bd55SPierre Yves MORDRET #define STM32_DMA_MASKI (STM32_DMA_TCI \ 439df3bd55SPierre Yves MORDRET | STM32_DMA_TEI \ 449df3bd55SPierre Yves MORDRET | STM32_DMA_DMEI \ 459df3bd55SPierre Yves MORDRET | STM32_DMA_FEI) 46d8b46839SM'boumba Cedric Madianga 47d8b46839SM'boumba Cedric Madianga /* DMA Stream x Configuration Register */ 48d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */ 49d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_REQ(n) ((n & 0x7) << 25) 50d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MBURST_MASK GENMASK(24, 23) 51d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MBURST(n) ((n & 0x3) << 23) 52d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PBURST_MASK GENMASK(22, 21) 53d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PBURST(n) ((n & 0x3) << 21) 54d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PL_MASK GENMASK(17, 16) 55d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PL(n) ((n & 0x3) << 16) 56d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MSIZE_MASK GENMASK(14, 13) 57d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MSIZE(n) ((n & 0x3) << 13) 58d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PSIZE_MASK GENMASK(12, 11) 59d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PSIZE(n) ((n & 0x3) << 11) 60d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PSIZE_GET(n) ((n & STM32_DMA_SCR_PSIZE_MASK) >> 11) 61d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_DIR_MASK GENMASK(7, 6) 62d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_DIR(n) ((n & 0x3) << 6) 632b5b7405SAmelie Delaunay #define STM32_DMA_SCR_TRBUFF BIT(20) /* Bufferable transfer for USART/UART */ 64d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_CT BIT(19) /* Target in double buffer */ 65d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_DBM BIT(18) /* Double Buffer Mode */ 66d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PINCOS BIT(15) /* Peripheral inc offset size */ 67d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_MINC BIT(10) /* Memory increment mode */ 68d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PINC BIT(9) /* Peripheral increment mode */ 69d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_CIRC BIT(8) /* Circular mode */ 70d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_PFCTRL BIT(5) /* Peripheral Flow Controller */ 71249d5531SPierre Yves MORDRET #define STM32_DMA_SCR_TCIE BIT(4) /* Transfer Complete Int Enable 72249d5531SPierre Yves MORDRET */ 73d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_TEIE BIT(2) /* Transfer Error Int Enable */ 74d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_DMEIE BIT(1) /* Direct Mode Err Int Enable */ 75d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_EN BIT(0) /* Stream Enable */ 76d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_CFG_MASK (STM32_DMA_SCR_PINC \ 77d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_MINC \ 78d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_PINCOS \ 79d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_PL_MASK) 80d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SCR_IRQ_MASK (STM32_DMA_SCR_TCIE \ 81d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_TEIE \ 82d8b46839SM'boumba Cedric Madianga | STM32_DMA_SCR_DMEIE) 83d8b46839SM'boumba Cedric Madianga 84d8b46839SM'boumba Cedric Madianga /* DMA Stream x number of data register */ 85d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SNDTR(x) (0x0014 + 0x18 * (x)) 86d8b46839SM'boumba Cedric Madianga 87d8b46839SM'boumba Cedric Madianga /* DMA stream peripheral address register */ 88d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SPAR(x) (0x0018 + 0x18 * (x)) 89d8b46839SM'boumba Cedric Madianga 90d8b46839SM'boumba Cedric Madianga /* DMA stream x memory 0 address register */ 91d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SM0AR(x) (0x001c + 0x18 * (x)) 92d8b46839SM'boumba Cedric Madianga 93d8b46839SM'boumba Cedric Madianga /* DMA stream x memory 1 address register */ 94d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SM1AR(x) (0x0020 + 0x18 * (x)) 95d8b46839SM'boumba Cedric Madianga 96d8b46839SM'boumba Cedric Madianga /* DMA stream x FIFO control register */ 97d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR(x) (0x0024 + 0x18 * (x)) 98d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_FTH_MASK GENMASK(1, 0) 99d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_FTH(n) (n & STM32_DMA_SFCR_FTH_MASK) 100d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_FEIE BIT(7) /* FIFO error interrupt enable */ 101d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_DMDIS BIT(2) /* Direct mode disable */ 102d8b46839SM'boumba Cedric Madianga #define STM32_DMA_SFCR_MASK (STM32_DMA_SFCR_FEIE \ 103d8b46839SM'boumba Cedric Madianga | STM32_DMA_SFCR_DMDIS) 104d8b46839SM'boumba Cedric Madianga 105d8b46839SM'boumba Cedric Madianga /* DMA direction */ 106d8b46839SM'boumba Cedric Madianga #define STM32_DMA_DEV_TO_MEM 0x00 107d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MEM_TO_DEV 0x01 108d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MEM_TO_MEM 0x02 109d8b46839SM'boumba Cedric Madianga 110d8b46839SM'boumba Cedric Madianga /* DMA priority level */ 111d8b46839SM'boumba Cedric Madianga #define STM32_DMA_PRIORITY_LOW 0x00 112d8b46839SM'boumba Cedric Madianga #define STM32_DMA_PRIORITY_MEDIUM 0x01 113d8b46839SM'boumba Cedric Madianga #define STM32_DMA_PRIORITY_HIGH 0x02 114d8b46839SM'boumba Cedric Madianga #define STM32_DMA_PRIORITY_VERY_HIGH 0x03 115d8b46839SM'boumba Cedric Madianga 116d8b46839SM'boumba Cedric Madianga /* DMA FIFO threshold selection */ 117d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00 118d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FIFO_THRESHOLD_HALFFULL 0x01 119d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FIFO_THRESHOLD_3QUARTERSFULL 0x02 120d8b46839SM'boumba Cedric Madianga #define STM32_DMA_FIFO_THRESHOLD_FULL 0x03 121955b1766SAmelie Delaunay #define STM32_DMA_FIFO_THRESHOLD_NONE 0x04 122d8b46839SM'boumba Cedric Madianga 123d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MAX_DATA_ITEMS 0xffff 12480a76952SPierre Yves MORDRET /* 12580a76952SPierre Yves MORDRET * Valid transfer starts from @0 to @0xFFFE leading to unaligned scatter 12680a76952SPierre Yves MORDRET * gather at boundary. Thus it's safer to round down this value on FIFO 12780a76952SPierre Yves MORDRET * size (16 Bytes) 12880a76952SPierre Yves MORDRET */ 12980a76952SPierre Yves MORDRET #define STM32_DMA_ALIGNED_MAX_DATA_ITEMS \ 13080a76952SPierre Yves MORDRET ALIGN_DOWN(STM32_DMA_MAX_DATA_ITEMS, 16) 131d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MAX_CHANNELS 0x08 132d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MAX_REQUEST_ID 0x08 133d8b46839SM'boumba Cedric Madianga #define STM32_DMA_MAX_DATA_PARAM 0x03 134a2b6103bSPierre Yves MORDRET #define STM32_DMA_FIFO_SIZE 16 /* FIFO is 16 bytes */ 135a2b6103bSPierre Yves MORDRET #define STM32_DMA_MIN_BURST 4 136276b0046SM'boumba Cedric Madianga #define STM32_DMA_MAX_BURST 16 137d8b46839SM'boumba Cedric Madianga 138951f44cbSPierre Yves MORDRET /* DMA Features */ 139951f44cbSPierre Yves MORDRET #define STM32_DMA_THRESHOLD_FTR_MASK GENMASK(1, 0) 140951f44cbSPierre Yves MORDRET #define STM32_DMA_THRESHOLD_FTR_GET(n) ((n) & STM32_DMA_THRESHOLD_FTR_MASK) 141955b1766SAmelie Delaunay #define STM32_DMA_DIRECT_MODE_MASK BIT(2) 1422b5b7405SAmelie Delaunay #define STM32_DMA_DIRECT_MODE_GET(n) (((n) & STM32_DMA_DIRECT_MODE_MASK) >> 2) 1432b5b7405SAmelie Delaunay #define STM32_DMA_ALT_ACK_MODE_MASK BIT(4) 1442b5b7405SAmelie Delaunay #define STM32_DMA_ALT_ACK_MODE_GET(n) (((n) & STM32_DMA_ALT_ACK_MODE_MASK) >> 4) 145951f44cbSPierre Yves MORDRET 146d8b46839SM'boumba Cedric Madianga enum stm32_dma_width { 147d8b46839SM'boumba Cedric Madianga STM32_DMA_BYTE, 148d8b46839SM'boumba Cedric Madianga STM32_DMA_HALF_WORD, 149d8b46839SM'boumba Cedric Madianga STM32_DMA_WORD, 150d8b46839SM'boumba Cedric Madianga }; 151d8b46839SM'boumba Cedric Madianga 152d8b46839SM'boumba Cedric Madianga enum stm32_dma_burst_size { 153d8b46839SM'boumba Cedric Madianga STM32_DMA_BURST_SINGLE, 154d8b46839SM'boumba Cedric Madianga STM32_DMA_BURST_INCR4, 155d8b46839SM'boumba Cedric Madianga STM32_DMA_BURST_INCR8, 156d8b46839SM'boumba Cedric Madianga STM32_DMA_BURST_INCR16, 157d8b46839SM'boumba Cedric Madianga }; 158d8b46839SM'boumba Cedric Madianga 159951f44cbSPierre Yves MORDRET /** 160951f44cbSPierre Yves MORDRET * struct stm32_dma_cfg - STM32 DMA custom configuration 161951f44cbSPierre Yves MORDRET * @channel_id: channel ID 162951f44cbSPierre Yves MORDRET * @request_line: DMA request 163951f44cbSPierre Yves MORDRET * @stream_config: 32bit mask specifying the DMA channel configuration 164951f44cbSPierre Yves MORDRET * @features: 32bit mask specifying the DMA Feature list 165951f44cbSPierre Yves MORDRET */ 166d8b46839SM'boumba Cedric Madianga struct stm32_dma_cfg { 167d8b46839SM'boumba Cedric Madianga u32 channel_id; 168d8b46839SM'boumba Cedric Madianga u32 request_line; 169d8b46839SM'boumba Cedric Madianga u32 stream_config; 170951f44cbSPierre Yves MORDRET u32 features; 171d8b46839SM'boumba Cedric Madianga }; 172d8b46839SM'boumba Cedric Madianga 173d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan_reg { 174d8b46839SM'boumba Cedric Madianga u32 dma_lisr; 175d8b46839SM'boumba Cedric Madianga u32 dma_hisr; 176d8b46839SM'boumba Cedric Madianga u32 dma_lifcr; 177d8b46839SM'boumba Cedric Madianga u32 dma_hifcr; 178d8b46839SM'boumba Cedric Madianga u32 dma_scr; 179d8b46839SM'boumba Cedric Madianga u32 dma_sndtr; 180d8b46839SM'boumba Cedric Madianga u32 dma_spar; 181d8b46839SM'boumba Cedric Madianga u32 dma_sm0ar; 182d8b46839SM'boumba Cedric Madianga u32 dma_sm1ar; 183d8b46839SM'boumba Cedric Madianga u32 dma_sfcr; 184d8b46839SM'boumba Cedric Madianga }; 185d8b46839SM'boumba Cedric Madianga 186d8b46839SM'boumba Cedric Madianga struct stm32_dma_sg_req { 187d8b46839SM'boumba Cedric Madianga u32 len; 188d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan_reg chan_reg; 189d8b46839SM'boumba Cedric Madianga }; 190d8b46839SM'boumba Cedric Madianga 191d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc { 192d8b46839SM'boumba Cedric Madianga struct virt_dma_desc vdesc; 193d8b46839SM'boumba Cedric Madianga bool cyclic; 194d8b46839SM'boumba Cedric Madianga u32 num_sgs; 195d8b46839SM'boumba Cedric Madianga struct stm32_dma_sg_req sg_req[]; 196d8b46839SM'boumba Cedric Madianga }; 197d8b46839SM'boumba Cedric Madianga 198d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan { 199d8b46839SM'boumba Cedric Madianga struct virt_dma_chan vchan; 200d8b46839SM'boumba Cedric Madianga bool config_init; 201d8b46839SM'boumba Cedric Madianga bool busy; 202d8b46839SM'boumba Cedric Madianga u32 id; 203d8b46839SM'boumba Cedric Madianga u32 irq; 204d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc; 205d8b46839SM'boumba Cedric Madianga u32 next_sg; 206d8b46839SM'boumba Cedric Madianga struct dma_slave_config dma_sconfig; 207d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan_reg chan_reg; 208951f44cbSPierre Yves MORDRET u32 threshold; 209a2b6103bSPierre Yves MORDRET u32 mem_burst; 210a2b6103bSPierre Yves MORDRET u32 mem_width; 211*099a9a94SAmelie Delaunay enum dma_status status; 212d8b46839SM'boumba Cedric Madianga }; 213d8b46839SM'boumba Cedric Madianga 214d8b46839SM'boumba Cedric Madianga struct stm32_dma_device { 215d8b46839SM'boumba Cedric Madianga struct dma_device ddev; 216d8b46839SM'boumba Cedric Madianga void __iomem *base; 217d8b46839SM'boumba Cedric Madianga struct clk *clk; 218d8b46839SM'boumba Cedric Madianga bool mem2mem; 219d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan chan[STM32_DMA_MAX_CHANNELS]; 220d8b46839SM'boumba Cedric Madianga }; 221d8b46839SM'boumba Cedric Madianga 222d8b46839SM'boumba Cedric Madianga static struct stm32_dma_device *stm32_dma_get_dev(struct stm32_dma_chan *chan) 223d8b46839SM'boumba Cedric Madianga { 224d8b46839SM'boumba Cedric Madianga return container_of(chan->vchan.chan.device, struct stm32_dma_device, 225d8b46839SM'boumba Cedric Madianga ddev); 226d8b46839SM'boumba Cedric Madianga } 227d8b46839SM'boumba Cedric Madianga 228d8b46839SM'boumba Cedric Madianga static struct stm32_dma_chan *to_stm32_dma_chan(struct dma_chan *c) 229d8b46839SM'boumba Cedric Madianga { 230d8b46839SM'boumba Cedric Madianga return container_of(c, struct stm32_dma_chan, vchan.chan); 231d8b46839SM'boumba Cedric Madianga } 232d8b46839SM'boumba Cedric Madianga 233d8b46839SM'boumba Cedric Madianga static struct stm32_dma_desc *to_stm32_dma_desc(struct virt_dma_desc *vdesc) 234d8b46839SM'boumba Cedric Madianga { 235d8b46839SM'boumba Cedric Madianga return container_of(vdesc, struct stm32_dma_desc, vdesc); 236d8b46839SM'boumba Cedric Madianga } 237d8b46839SM'boumba Cedric Madianga 238d8b46839SM'boumba Cedric Madianga static struct device *chan2dev(struct stm32_dma_chan *chan) 239d8b46839SM'boumba Cedric Madianga { 240d8b46839SM'boumba Cedric Madianga return &chan->vchan.chan.dev->device; 241d8b46839SM'boumba Cedric Madianga } 242d8b46839SM'boumba Cedric Madianga 243d8b46839SM'boumba Cedric Madianga static u32 stm32_dma_read(struct stm32_dma_device *dmadev, u32 reg) 244d8b46839SM'boumba Cedric Madianga { 245d8b46839SM'boumba Cedric Madianga return readl_relaxed(dmadev->base + reg); 246d8b46839SM'boumba Cedric Madianga } 247d8b46839SM'boumba Cedric Madianga 248d8b46839SM'boumba Cedric Madianga static void stm32_dma_write(struct stm32_dma_device *dmadev, u32 reg, u32 val) 249d8b46839SM'boumba Cedric Madianga { 250d8b46839SM'boumba Cedric Madianga writel_relaxed(val, dmadev->base + reg); 251d8b46839SM'boumba Cedric Madianga } 252d8b46839SM'boumba Cedric Madianga 253d8b46839SM'boumba Cedric Madianga static int stm32_dma_get_width(struct stm32_dma_chan *chan, 254d8b46839SM'boumba Cedric Madianga enum dma_slave_buswidth width) 255d8b46839SM'boumba Cedric Madianga { 256d8b46839SM'boumba Cedric Madianga switch (width) { 257d8b46839SM'boumba Cedric Madianga case DMA_SLAVE_BUSWIDTH_1_BYTE: 258d8b46839SM'boumba Cedric Madianga return STM32_DMA_BYTE; 259d8b46839SM'boumba Cedric Madianga case DMA_SLAVE_BUSWIDTH_2_BYTES: 260d8b46839SM'boumba Cedric Madianga return STM32_DMA_HALF_WORD; 261d8b46839SM'boumba Cedric Madianga case DMA_SLAVE_BUSWIDTH_4_BYTES: 262d8b46839SM'boumba Cedric Madianga return STM32_DMA_WORD; 263d8b46839SM'boumba Cedric Madianga default: 264d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Dma bus width not supported\n"); 265d8b46839SM'boumba Cedric Madianga return -EINVAL; 266d8b46839SM'boumba Cedric Madianga } 267d8b46839SM'boumba Cedric Madianga } 268d8b46839SM'boumba Cedric Madianga 269a2b6103bSPierre Yves MORDRET static enum dma_slave_buswidth stm32_dma_get_max_width(u32 buf_len, 270e0ebdbdcSAmelie Delaunay dma_addr_t buf_addr, 271a2b6103bSPierre Yves MORDRET u32 threshold) 272a2b6103bSPierre Yves MORDRET { 273a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth max_width; 274a2b6103bSPierre Yves MORDRET 275a2b6103bSPierre Yves MORDRET if (threshold == STM32_DMA_FIFO_THRESHOLD_FULL) 276a2b6103bSPierre Yves MORDRET max_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 277a2b6103bSPierre Yves MORDRET else 278a2b6103bSPierre Yves MORDRET max_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 279a2b6103bSPierre Yves MORDRET 280a2b6103bSPierre Yves MORDRET while ((buf_len < max_width || buf_len % max_width) && 281a2b6103bSPierre Yves MORDRET max_width > DMA_SLAVE_BUSWIDTH_1_BYTE) 282a2b6103bSPierre Yves MORDRET max_width = max_width >> 1; 283a2b6103bSPierre Yves MORDRET 28424983633SArnd Bergmann if (buf_addr & (max_width - 1)) 285e0ebdbdcSAmelie Delaunay max_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 286e0ebdbdcSAmelie Delaunay 287a2b6103bSPierre Yves MORDRET return max_width; 288a2b6103bSPierre Yves MORDRET } 289a2b6103bSPierre Yves MORDRET 290a2b6103bSPierre Yves MORDRET static bool stm32_dma_fifo_threshold_is_allowed(u32 burst, u32 threshold, 291a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth width) 292a2b6103bSPierre Yves MORDRET { 293a2b6103bSPierre Yves MORDRET u32 remaining; 294a2b6103bSPierre Yves MORDRET 295955b1766SAmelie Delaunay if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE) 296955b1766SAmelie Delaunay return false; 297955b1766SAmelie Delaunay 298a2b6103bSPierre Yves MORDRET if (width != DMA_SLAVE_BUSWIDTH_UNDEFINED) { 299a2b6103bSPierre Yves MORDRET if (burst != 0) { 300a2b6103bSPierre Yves MORDRET /* 301a2b6103bSPierre Yves MORDRET * If number of beats fit in several whole bursts 302a2b6103bSPierre Yves MORDRET * this configuration is allowed. 303a2b6103bSPierre Yves MORDRET */ 304a2b6103bSPierre Yves MORDRET remaining = ((STM32_DMA_FIFO_SIZE / width) * 305a2b6103bSPierre Yves MORDRET (threshold + 1) / 4) % burst; 306a2b6103bSPierre Yves MORDRET 307a2b6103bSPierre Yves MORDRET if (remaining == 0) 308a2b6103bSPierre Yves MORDRET return true; 309a2b6103bSPierre Yves MORDRET } else { 310a2b6103bSPierre Yves MORDRET return true; 311a2b6103bSPierre Yves MORDRET } 312a2b6103bSPierre Yves MORDRET } 313a2b6103bSPierre Yves MORDRET 314a2b6103bSPierre Yves MORDRET return false; 315a2b6103bSPierre Yves MORDRET } 316a2b6103bSPierre Yves MORDRET 317a2b6103bSPierre Yves MORDRET static bool stm32_dma_is_burst_possible(u32 buf_len, u32 threshold) 318a2b6103bSPierre Yves MORDRET { 319955b1766SAmelie Delaunay /* If FIFO direct mode, burst is not possible */ 320955b1766SAmelie Delaunay if (threshold == STM32_DMA_FIFO_THRESHOLD_NONE) 321955b1766SAmelie Delaunay return false; 322955b1766SAmelie Delaunay 323cc832dc8SPierre-Yves MORDRET /* 324cc832dc8SPierre-Yves MORDRET * Buffer or period length has to be aligned on FIFO depth. 325cc832dc8SPierre-Yves MORDRET * Otherwise bytes may be stuck within FIFO at buffer or period 326cc832dc8SPierre-Yves MORDRET * length. 327cc832dc8SPierre-Yves MORDRET */ 328cc832dc8SPierre-Yves MORDRET return ((buf_len % ((threshold + 1) * 4)) == 0); 329a2b6103bSPierre Yves MORDRET } 330a2b6103bSPierre Yves MORDRET 331a2b6103bSPierre Yves MORDRET static u32 stm32_dma_get_best_burst(u32 buf_len, u32 max_burst, u32 threshold, 332a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth width) 333a2b6103bSPierre Yves MORDRET { 334a2b6103bSPierre Yves MORDRET u32 best_burst = max_burst; 335a2b6103bSPierre Yves MORDRET 336a2b6103bSPierre Yves MORDRET if (best_burst == 1 || !stm32_dma_is_burst_possible(buf_len, threshold)) 337a2b6103bSPierre Yves MORDRET return 0; 338a2b6103bSPierre Yves MORDRET 339a2b6103bSPierre Yves MORDRET while ((buf_len < best_burst * width && best_burst > 1) || 340a2b6103bSPierre Yves MORDRET !stm32_dma_fifo_threshold_is_allowed(best_burst, threshold, 341a2b6103bSPierre Yves MORDRET width)) { 342a2b6103bSPierre Yves MORDRET if (best_burst > STM32_DMA_MIN_BURST) 343a2b6103bSPierre Yves MORDRET best_burst = best_burst >> 1; 344a2b6103bSPierre Yves MORDRET else 345a2b6103bSPierre Yves MORDRET best_burst = 0; 346a2b6103bSPierre Yves MORDRET } 347a2b6103bSPierre Yves MORDRET 348a2b6103bSPierre Yves MORDRET return best_burst; 349a2b6103bSPierre Yves MORDRET } 350a2b6103bSPierre Yves MORDRET 351d8b46839SM'boumba Cedric Madianga static int stm32_dma_get_burst(struct stm32_dma_chan *chan, u32 maxburst) 352d8b46839SM'boumba Cedric Madianga { 353d8b46839SM'boumba Cedric Madianga switch (maxburst) { 354d8b46839SM'boumba Cedric Madianga case 0: 355d8b46839SM'boumba Cedric Madianga case 1: 356d8b46839SM'boumba Cedric Madianga return STM32_DMA_BURST_SINGLE; 357d8b46839SM'boumba Cedric Madianga case 4: 358d8b46839SM'boumba Cedric Madianga return STM32_DMA_BURST_INCR4; 359d8b46839SM'boumba Cedric Madianga case 8: 360d8b46839SM'boumba Cedric Madianga return STM32_DMA_BURST_INCR8; 361d8b46839SM'boumba Cedric Madianga case 16: 362d8b46839SM'boumba Cedric Madianga return STM32_DMA_BURST_INCR16; 363d8b46839SM'boumba Cedric Madianga default: 364d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Dma burst size not supported\n"); 365d8b46839SM'boumba Cedric Madianga return -EINVAL; 366d8b46839SM'boumba Cedric Madianga } 367d8b46839SM'boumba Cedric Madianga } 368d8b46839SM'boumba Cedric Madianga 369d8b46839SM'boumba Cedric Madianga static void stm32_dma_set_fifo_config(struct stm32_dma_chan *chan, 370a2b6103bSPierre Yves MORDRET u32 src_burst, u32 dst_burst) 371d8b46839SM'boumba Cedric Madianga { 372d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_MASK; 373d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_DMEIE; 374d8b46839SM'boumba Cedric Madianga 375a2b6103bSPierre Yves MORDRET if (!src_burst && !dst_burst) { 376d8b46839SM'boumba Cedric Madianga /* Using direct mode */ 377d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_DMEIE; 378d8b46839SM'boumba Cedric Madianga } else { 379d8b46839SM'boumba Cedric Madianga /* Using FIFO mode */ 380d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; 381d8b46839SM'boumba Cedric Madianga } 382d8b46839SM'boumba Cedric Madianga } 383d8b46839SM'boumba Cedric Madianga 384d8b46839SM'boumba Cedric Madianga static int stm32_dma_slave_config(struct dma_chan *c, 385d8b46839SM'boumba Cedric Madianga struct dma_slave_config *config) 386d8b46839SM'boumba Cedric Madianga { 387d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 388d8b46839SM'boumba Cedric Madianga 389d8b46839SM'boumba Cedric Madianga memcpy(&chan->dma_sconfig, config, sizeof(*config)); 390d8b46839SM'boumba Cedric Madianga 391d8b46839SM'boumba Cedric Madianga chan->config_init = true; 392d8b46839SM'boumba Cedric Madianga 393d8b46839SM'boumba Cedric Madianga return 0; 394d8b46839SM'boumba Cedric Madianga } 395d8b46839SM'boumba Cedric Madianga 396d8b46839SM'boumba Cedric Madianga static u32 stm32_dma_irq_status(struct stm32_dma_chan *chan) 397d8b46839SM'boumba Cedric Madianga { 398d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 399d8b46839SM'boumba Cedric Madianga u32 flags, dma_isr; 400d8b46839SM'boumba Cedric Madianga 401d8b46839SM'boumba Cedric Madianga /* 402d8b46839SM'boumba Cedric Madianga * Read "flags" from DMA_xISR register corresponding to the selected 403d8b46839SM'boumba Cedric Madianga * DMA channel at the correct bit offset inside that register. 404d8b46839SM'boumba Cedric Madianga * 405d8b46839SM'boumba Cedric Madianga * If (ch % 4) is 2 or 3, left shift the mask by 16 bits. 406d8b46839SM'boumba Cedric Madianga * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. 407d8b46839SM'boumba Cedric Madianga */ 408d8b46839SM'boumba Cedric Madianga 409d8b46839SM'boumba Cedric Madianga if (chan->id & 4) 410d8b46839SM'boumba Cedric Madianga dma_isr = stm32_dma_read(dmadev, STM32_DMA_HISR); 411d8b46839SM'boumba Cedric Madianga else 412d8b46839SM'boumba Cedric Madianga dma_isr = stm32_dma_read(dmadev, STM32_DMA_LISR); 413d8b46839SM'boumba Cedric Madianga 414d8b46839SM'boumba Cedric Madianga flags = dma_isr >> (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); 415d8b46839SM'boumba Cedric Madianga 4169df3bd55SPierre Yves MORDRET return flags & STM32_DMA_MASKI; 417d8b46839SM'boumba Cedric Madianga } 418d8b46839SM'boumba Cedric Madianga 419d8b46839SM'boumba Cedric Madianga static void stm32_dma_irq_clear(struct stm32_dma_chan *chan, u32 flags) 420d8b46839SM'boumba Cedric Madianga { 421d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 422d8b46839SM'boumba Cedric Madianga u32 dma_ifcr; 423d8b46839SM'boumba Cedric Madianga 424d8b46839SM'boumba Cedric Madianga /* 425d8b46839SM'boumba Cedric Madianga * Write "flags" to the DMA_xIFCR register corresponding to the selected 426d8b46839SM'boumba Cedric Madianga * DMA channel at the correct bit offset inside that register. 427d8b46839SM'boumba Cedric Madianga * 428d8b46839SM'boumba Cedric Madianga * If (ch % 4) is 2 or 3, left shift the mask by 16 bits. 429d8b46839SM'boumba Cedric Madianga * If (ch % 4) is 1 or 3, additionally left shift the mask by 6 bits. 430d8b46839SM'boumba Cedric Madianga */ 4319df3bd55SPierre Yves MORDRET flags &= STM32_DMA_MASKI; 432d8b46839SM'boumba Cedric Madianga dma_ifcr = flags << (((chan->id & 2) << 3) | ((chan->id & 1) * 6)); 433d8b46839SM'boumba Cedric Madianga 434d8b46839SM'boumba Cedric Madianga if (chan->id & 4) 435d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_HIFCR, dma_ifcr); 436d8b46839SM'boumba Cedric Madianga else 437d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_LIFCR, dma_ifcr); 438d8b46839SM'boumba Cedric Madianga } 439d8b46839SM'boumba Cedric Madianga 440d8b46839SM'boumba Cedric Madianga static int stm32_dma_disable_chan(struct stm32_dma_chan *chan) 441d8b46839SM'boumba Cedric Madianga { 442d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 443409ffc4dSAmelie Delaunay u32 dma_scr, id, reg; 444d8b46839SM'boumba Cedric Madianga 445d8b46839SM'boumba Cedric Madianga id = chan->id; 446409ffc4dSAmelie Delaunay reg = STM32_DMA_SCR(id); 447409ffc4dSAmelie Delaunay dma_scr = stm32_dma_read(dmadev, reg); 448d8b46839SM'boumba Cedric Madianga 449d8b46839SM'boumba Cedric Madianga if (dma_scr & STM32_DMA_SCR_EN) { 450d8b46839SM'boumba Cedric Madianga dma_scr &= ~STM32_DMA_SCR_EN; 451409ffc4dSAmelie Delaunay stm32_dma_write(dmadev, reg, dma_scr); 452d8b46839SM'boumba Cedric Madianga 453409ffc4dSAmelie Delaunay return readl_relaxed_poll_timeout_atomic(dmadev->base + reg, 454409ffc4dSAmelie Delaunay dma_scr, !(dma_scr & STM32_DMA_SCR_EN), 455409ffc4dSAmelie Delaunay 10, 1000000); 456d8b46839SM'boumba Cedric Madianga } 457d8b46839SM'boumba Cedric Madianga 458d8b46839SM'boumba Cedric Madianga return 0; 459d8b46839SM'boumba Cedric Madianga } 460d8b46839SM'boumba Cedric Madianga 461d8b46839SM'boumba Cedric Madianga static void stm32_dma_stop(struct stm32_dma_chan *chan) 462d8b46839SM'boumba Cedric Madianga { 463d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 464d8b46839SM'boumba Cedric Madianga u32 dma_scr, dma_sfcr, status; 465d8b46839SM'boumba Cedric Madianga int ret; 466d8b46839SM'boumba Cedric Madianga 467d8b46839SM'boumba Cedric Madianga /* Disable interrupts */ 468d8b46839SM'boumba Cedric Madianga dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 469d8b46839SM'boumba Cedric Madianga dma_scr &= ~STM32_DMA_SCR_IRQ_MASK; 470d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); 471d8b46839SM'boumba Cedric Madianga dma_sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); 472d8b46839SM'boumba Cedric Madianga dma_sfcr &= ~STM32_DMA_SFCR_FEIE; 473d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), dma_sfcr); 474d8b46839SM'boumba Cedric Madianga 475d8b46839SM'boumba Cedric Madianga /* Disable DMA */ 476d8b46839SM'boumba Cedric Madianga ret = stm32_dma_disable_chan(chan); 477d8b46839SM'boumba Cedric Madianga if (ret < 0) 478d8b46839SM'boumba Cedric Madianga return; 479d8b46839SM'boumba Cedric Madianga 480d8b46839SM'boumba Cedric Madianga /* Clear interrupt status if it is there */ 481d8b46839SM'boumba Cedric Madianga status = stm32_dma_irq_status(chan); 482d8b46839SM'boumba Cedric Madianga if (status) { 483d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "%s(): clearing interrupt: 0x%08x\n", 484d8b46839SM'boumba Cedric Madianga __func__, status); 485d8b46839SM'boumba Cedric Madianga stm32_dma_irq_clear(chan, status); 486d8b46839SM'boumba Cedric Madianga } 487d8b46839SM'boumba Cedric Madianga 488d8b46839SM'boumba Cedric Madianga chan->busy = false; 489*099a9a94SAmelie Delaunay chan->status = DMA_COMPLETE; 490d8b46839SM'boumba Cedric Madianga } 491d8b46839SM'boumba Cedric Madianga 492d8b46839SM'boumba Cedric Madianga static int stm32_dma_terminate_all(struct dma_chan *c) 493d8b46839SM'boumba Cedric Madianga { 494d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 495d8b46839SM'boumba Cedric Madianga unsigned long flags; 496d8b46839SM'boumba Cedric Madianga LIST_HEAD(head); 497d8b46839SM'boumba Cedric Madianga 498d8b46839SM'boumba Cedric Madianga spin_lock_irqsave(&chan->vchan.lock, flags); 499d8b46839SM'boumba Cedric Madianga 500d80cbef3SAmelie Delaunay if (chan->desc) { 50179e40b06SAmelie Delaunay dma_cookie_complete(&chan->desc->vdesc.tx); 502d80cbef3SAmelie Delaunay vchan_terminate_vdesc(&chan->desc->vdesc); 503d80cbef3SAmelie Delaunay if (chan->busy) 504d8b46839SM'boumba Cedric Madianga stm32_dma_stop(chan); 505d8b46839SM'boumba Cedric Madianga chan->desc = NULL; 506d8b46839SM'boumba Cedric Madianga } 507d8b46839SM'boumba Cedric Madianga 508d8b46839SM'boumba Cedric Madianga vchan_get_all_descriptors(&chan->vchan, &head); 509d8b46839SM'boumba Cedric Madianga spin_unlock_irqrestore(&chan->vchan.lock, flags); 510d8b46839SM'boumba Cedric Madianga vchan_dma_desc_free_list(&chan->vchan, &head); 511d8b46839SM'boumba Cedric Madianga 512d8b46839SM'boumba Cedric Madianga return 0; 513d8b46839SM'boumba Cedric Madianga } 514d8b46839SM'boumba Cedric Madianga 515dc808675SM'boumba Cedric Madianga static void stm32_dma_synchronize(struct dma_chan *c) 516dc808675SM'boumba Cedric Madianga { 517dc808675SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 518dc808675SM'boumba Cedric Madianga 519dc808675SM'boumba Cedric Madianga vchan_synchronize(&chan->vchan); 520dc808675SM'boumba Cedric Madianga } 521dc808675SM'boumba Cedric Madianga 522d8b46839SM'boumba Cedric Madianga static void stm32_dma_dump_reg(struct stm32_dma_chan *chan) 523d8b46839SM'boumba Cedric Madianga { 524d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 525d8b46839SM'boumba Cedric Madianga u32 scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 526d8b46839SM'boumba Cedric Madianga u32 ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); 527d8b46839SM'boumba Cedric Madianga u32 spar = stm32_dma_read(dmadev, STM32_DMA_SPAR(chan->id)); 528d8b46839SM'boumba Cedric Madianga u32 sm0ar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(chan->id)); 529d8b46839SM'boumba Cedric Madianga u32 sm1ar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(chan->id)); 530d8b46839SM'boumba Cedric Madianga u32 sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); 531d8b46839SM'boumba Cedric Madianga 532d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SCR: 0x%08x\n", scr); 533d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "NDTR: 0x%08x\n", ndtr); 534d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SPAR: 0x%08x\n", spar); 535d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SM0AR: 0x%08x\n", sm0ar); 536d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SM1AR: 0x%08x\n", sm1ar); 537d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "SFCR: 0x%08x\n", sfcr); 538d8b46839SM'boumba Cedric Madianga } 539d8b46839SM'boumba Cedric Madianga 540db60a63eSAmelie Delaunay static void stm32_dma_sg_inc(struct stm32_dma_chan *chan) 541db60a63eSAmelie Delaunay { 542db60a63eSAmelie Delaunay chan->next_sg++; 543db60a63eSAmelie Delaunay if (chan->desc->cyclic && (chan->next_sg == chan->desc->num_sgs)) 544db60a63eSAmelie Delaunay chan->next_sg = 0; 545db60a63eSAmelie Delaunay } 546db60a63eSAmelie Delaunay 547e57cb3b3SPierre Yves MORDRET static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan); 548e57cb3b3SPierre Yves MORDRET 5498d1b76f0SM'boumba Cedric Madianga static void stm32_dma_start_transfer(struct stm32_dma_chan *chan) 550d8b46839SM'boumba Cedric Madianga { 551d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 552d8b46839SM'boumba Cedric Madianga struct virt_dma_desc *vdesc; 553d8b46839SM'boumba Cedric Madianga struct stm32_dma_sg_req *sg_req; 554d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan_reg *reg; 555d8b46839SM'boumba Cedric Madianga u32 status; 556d8b46839SM'boumba Cedric Madianga int ret; 557d8b46839SM'boumba Cedric Madianga 558d8b46839SM'boumba Cedric Madianga ret = stm32_dma_disable_chan(chan); 559d8b46839SM'boumba Cedric Madianga if (ret < 0) 5608d1b76f0SM'boumba Cedric Madianga return; 561d8b46839SM'boumba Cedric Madianga 562d8b46839SM'boumba Cedric Madianga if (!chan->desc) { 563d8b46839SM'boumba Cedric Madianga vdesc = vchan_next_desc(&chan->vchan); 564d8b46839SM'boumba Cedric Madianga if (!vdesc) 5658d1b76f0SM'boumba Cedric Madianga return; 566d8b46839SM'boumba Cedric Madianga 567d80cbef3SAmelie Delaunay list_del(&vdesc->node); 568d80cbef3SAmelie Delaunay 569d8b46839SM'boumba Cedric Madianga chan->desc = to_stm32_dma_desc(vdesc); 570d8b46839SM'boumba Cedric Madianga chan->next_sg = 0; 571d8b46839SM'boumba Cedric Madianga } 572d8b46839SM'boumba Cedric Madianga 573d8b46839SM'boumba Cedric Madianga if (chan->next_sg == chan->desc->num_sgs) 574d8b46839SM'boumba Cedric Madianga chan->next_sg = 0; 575d8b46839SM'boumba Cedric Madianga 576d8b46839SM'boumba Cedric Madianga sg_req = &chan->desc->sg_req[chan->next_sg]; 577d8b46839SM'boumba Cedric Madianga reg = &sg_req->chan_reg; 578d8b46839SM'boumba Cedric Madianga 57922a0bb29SPierre-Yves MORDRET reg->dma_scr &= ~STM32_DMA_SCR_EN; 580d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); 581d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SPAR(chan->id), reg->dma_spar); 582d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SM0AR(chan->id), reg->dma_sm0ar); 583d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SFCR(chan->id), reg->dma_sfcr); 584d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SM1AR(chan->id), reg->dma_sm1ar); 585d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), reg->dma_sndtr); 586d8b46839SM'boumba Cedric Madianga 587db60a63eSAmelie Delaunay stm32_dma_sg_inc(chan); 588d8b46839SM'boumba Cedric Madianga 589d8b46839SM'boumba Cedric Madianga /* Clear interrupt status if it is there */ 590d8b46839SM'boumba Cedric Madianga status = stm32_dma_irq_status(chan); 591d8b46839SM'boumba Cedric Madianga if (status) 592d8b46839SM'boumba Cedric Madianga stm32_dma_irq_clear(chan, status); 593d8b46839SM'boumba Cedric Madianga 594e57cb3b3SPierre Yves MORDRET if (chan->desc->cyclic) 595e57cb3b3SPierre Yves MORDRET stm32_dma_configure_next_sg(chan); 596e57cb3b3SPierre Yves MORDRET 597d8b46839SM'boumba Cedric Madianga stm32_dma_dump_reg(chan); 598d8b46839SM'boumba Cedric Madianga 599d8b46839SM'boumba Cedric Madianga /* Start DMA */ 600*099a9a94SAmelie Delaunay chan->busy = true; 601*099a9a94SAmelie Delaunay chan->status = DMA_IN_PROGRESS; 602d8b46839SM'boumba Cedric Madianga reg->dma_scr |= STM32_DMA_SCR_EN; 603d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), reg->dma_scr); 604d8b46839SM'boumba Cedric Madianga 60590ec93cbSBenjamin Gaignard dev_dbg(chan2dev(chan), "vchan %pK: started\n", &chan->vchan); 606d8b46839SM'boumba Cedric Madianga } 607d8b46839SM'boumba Cedric Madianga 608d8b46839SM'boumba Cedric Madianga static void stm32_dma_configure_next_sg(struct stm32_dma_chan *chan) 609d8b46839SM'boumba Cedric Madianga { 610d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 611d8b46839SM'boumba Cedric Madianga struct stm32_dma_sg_req *sg_req; 612d8b46839SM'boumba Cedric Madianga u32 dma_scr, dma_sm0ar, dma_sm1ar, id; 613d8b46839SM'boumba Cedric Madianga 614d8b46839SM'boumba Cedric Madianga id = chan->id; 615d8b46839SM'boumba Cedric Madianga dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); 616d8b46839SM'boumba Cedric Madianga 617d8b46839SM'boumba Cedric Madianga sg_req = &chan->desc->sg_req[chan->next_sg]; 618d8b46839SM'boumba Cedric Madianga 619d8b46839SM'boumba Cedric Madianga if (dma_scr & STM32_DMA_SCR_CT) { 620d8b46839SM'boumba Cedric Madianga dma_sm0ar = sg_req->chan_reg.dma_sm0ar; 621d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), dma_sm0ar); 622d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "CT=1 <=> SM0AR: 0x%08x\n", 623d8b46839SM'boumba Cedric Madianga stm32_dma_read(dmadev, STM32_DMA_SM0AR(id))); 624d8b46839SM'boumba Cedric Madianga } else { 625d8b46839SM'boumba Cedric Madianga dma_sm1ar = sg_req->chan_reg.dma_sm1ar; 626d8b46839SM'boumba Cedric Madianga stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), dma_sm1ar); 627d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "CT=0 <=> SM1AR: 0x%08x\n", 628d8b46839SM'boumba Cedric Madianga stm32_dma_read(dmadev, STM32_DMA_SM1AR(id))); 629d8b46839SM'boumba Cedric Madianga } 630d8b46839SM'boumba Cedric Madianga } 631d8b46839SM'boumba Cedric Madianga 632*099a9a94SAmelie Delaunay static void stm32_dma_handle_chan_paused(struct stm32_dma_chan *chan) 633*099a9a94SAmelie Delaunay { 634*099a9a94SAmelie Delaunay struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 635*099a9a94SAmelie Delaunay u32 dma_scr; 636*099a9a94SAmelie Delaunay 637*099a9a94SAmelie Delaunay /* 638*099a9a94SAmelie Delaunay * Read and store current remaining data items and peripheral/memory addresses to be 639*099a9a94SAmelie Delaunay * updated on resume 640*099a9a94SAmelie Delaunay */ 641*099a9a94SAmelie Delaunay dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 642*099a9a94SAmelie Delaunay /* 643*099a9a94SAmelie Delaunay * Transfer can be paused while between a previous resume and reconfiguration on transfer 644*099a9a94SAmelie Delaunay * complete. If transfer is cyclic and CIRC and DBM have been deactivated for resume, need 645*099a9a94SAmelie Delaunay * to set it here in SCR backup to ensure a good reconfiguration on transfer complete. 646*099a9a94SAmelie Delaunay */ 647*099a9a94SAmelie Delaunay if (chan->desc && chan->desc->cyclic) { 648*099a9a94SAmelie Delaunay if (chan->desc->num_sgs == 1) 649*099a9a94SAmelie Delaunay dma_scr |= STM32_DMA_SCR_CIRC; 650*099a9a94SAmelie Delaunay else 651*099a9a94SAmelie Delaunay dma_scr |= STM32_DMA_SCR_DBM; 652*099a9a94SAmelie Delaunay } 653*099a9a94SAmelie Delaunay chan->chan_reg.dma_scr = dma_scr; 654*099a9a94SAmelie Delaunay 655*099a9a94SAmelie Delaunay /* 656*099a9a94SAmelie Delaunay * Need to temporarily deactivate CIRC/DBM until next Transfer Complete interrupt, otherwise 657*099a9a94SAmelie Delaunay * on resume NDTR autoreload value will be wrong (lower than the initial period length) 658*099a9a94SAmelie Delaunay */ 659*099a9a94SAmelie Delaunay if (chan->desc && chan->desc->cyclic) { 660*099a9a94SAmelie Delaunay dma_scr &= ~(STM32_DMA_SCR_DBM | STM32_DMA_SCR_CIRC); 661*099a9a94SAmelie Delaunay stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); 662*099a9a94SAmelie Delaunay } 663*099a9a94SAmelie Delaunay 664*099a9a94SAmelie Delaunay chan->chan_reg.dma_sndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); 665*099a9a94SAmelie Delaunay 666*099a9a94SAmelie Delaunay dev_dbg(chan2dev(chan), "vchan %pK: paused\n", &chan->vchan); 667*099a9a94SAmelie Delaunay } 668*099a9a94SAmelie Delaunay 669*099a9a94SAmelie Delaunay static void stm32_dma_post_resume_reconfigure(struct stm32_dma_chan *chan) 670*099a9a94SAmelie Delaunay { 671*099a9a94SAmelie Delaunay struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 672*099a9a94SAmelie Delaunay struct stm32_dma_sg_req *sg_req; 673*099a9a94SAmelie Delaunay u32 dma_scr, status, id; 674*099a9a94SAmelie Delaunay 675*099a9a94SAmelie Delaunay id = chan->id; 676*099a9a94SAmelie Delaunay dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); 677*099a9a94SAmelie Delaunay 678*099a9a94SAmelie Delaunay /* Clear interrupt status if it is there */ 679*099a9a94SAmelie Delaunay status = stm32_dma_irq_status(chan); 680*099a9a94SAmelie Delaunay if (status) 681*099a9a94SAmelie Delaunay stm32_dma_irq_clear(chan, status); 682*099a9a94SAmelie Delaunay 683*099a9a94SAmelie Delaunay if (!chan->next_sg) 684*099a9a94SAmelie Delaunay sg_req = &chan->desc->sg_req[chan->desc->num_sgs - 1]; 685*099a9a94SAmelie Delaunay else 686*099a9a94SAmelie Delaunay sg_req = &chan->desc->sg_req[chan->next_sg - 1]; 687*099a9a94SAmelie Delaunay 688*099a9a94SAmelie Delaunay /* Reconfigure NDTR with the initial value */ 689*099a9a94SAmelie Delaunay stm32_dma_write(dmadev, STM32_DMA_SNDTR(chan->id), sg_req->chan_reg.dma_sndtr); 690*099a9a94SAmelie Delaunay 691*099a9a94SAmelie Delaunay /* Restore SPAR */ 692*099a9a94SAmelie Delaunay stm32_dma_write(dmadev, STM32_DMA_SPAR(id), sg_req->chan_reg.dma_spar); 693*099a9a94SAmelie Delaunay 694*099a9a94SAmelie Delaunay /* Restore SM0AR/SM1AR whatever DBM/CT as they may have been modified */ 695*099a9a94SAmelie Delaunay stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), sg_req->chan_reg.dma_sm0ar); 696*099a9a94SAmelie Delaunay stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), sg_req->chan_reg.dma_sm1ar); 697*099a9a94SAmelie Delaunay 698*099a9a94SAmelie Delaunay /* Reactivate CIRC/DBM if needed */ 699*099a9a94SAmelie Delaunay if (chan->chan_reg.dma_scr & STM32_DMA_SCR_DBM) { 700*099a9a94SAmelie Delaunay dma_scr |= STM32_DMA_SCR_DBM; 701*099a9a94SAmelie Delaunay /* Restore CT */ 702*099a9a94SAmelie Delaunay if (chan->chan_reg.dma_scr & STM32_DMA_SCR_CT) 703*099a9a94SAmelie Delaunay dma_scr &= ~STM32_DMA_SCR_CT; 704*099a9a94SAmelie Delaunay else 705*099a9a94SAmelie Delaunay dma_scr |= STM32_DMA_SCR_CT; 706*099a9a94SAmelie Delaunay } else if (chan->chan_reg.dma_scr & STM32_DMA_SCR_CIRC) { 707*099a9a94SAmelie Delaunay dma_scr |= STM32_DMA_SCR_CIRC; 708*099a9a94SAmelie Delaunay } 709*099a9a94SAmelie Delaunay stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); 710*099a9a94SAmelie Delaunay 711*099a9a94SAmelie Delaunay stm32_dma_configure_next_sg(chan); 712*099a9a94SAmelie Delaunay 713*099a9a94SAmelie Delaunay stm32_dma_dump_reg(chan); 714*099a9a94SAmelie Delaunay 715*099a9a94SAmelie Delaunay dma_scr |= STM32_DMA_SCR_EN; 716*099a9a94SAmelie Delaunay stm32_dma_write(dmadev, STM32_DMA_SCR(chan->id), dma_scr); 717*099a9a94SAmelie Delaunay 718*099a9a94SAmelie Delaunay dev_dbg(chan2dev(chan), "vchan %pK: reconfigured after pause/resume\n", &chan->vchan); 719*099a9a94SAmelie Delaunay } 720*099a9a94SAmelie Delaunay 721ded62306SAmelie Delaunay static void stm32_dma_handle_chan_done(struct stm32_dma_chan *chan, u32 scr) 722d8b46839SM'boumba Cedric Madianga { 723ded62306SAmelie Delaunay if (!chan->desc) 724ded62306SAmelie Delaunay return; 725ded62306SAmelie Delaunay 726d8b46839SM'boumba Cedric Madianga if (chan->desc->cyclic) { 727d8b46839SM'boumba Cedric Madianga vchan_cyclic_callback(&chan->desc->vdesc); 728db60a63eSAmelie Delaunay stm32_dma_sg_inc(chan); 729*099a9a94SAmelie Delaunay /* cyclic while CIRC/DBM disable => post resume reconfiguration needed */ 730*099a9a94SAmelie Delaunay if (!(scr & (STM32_DMA_SCR_CIRC | STM32_DMA_SCR_DBM))) 731*099a9a94SAmelie Delaunay stm32_dma_post_resume_reconfigure(chan); 732*099a9a94SAmelie Delaunay else if (scr & STM32_DMA_SCR_DBM) 733d8b46839SM'boumba Cedric Madianga stm32_dma_configure_next_sg(chan); 734d8b46839SM'boumba Cedric Madianga } else { 735d8b46839SM'boumba Cedric Madianga chan->busy = false; 736*099a9a94SAmelie Delaunay chan->status = DMA_COMPLETE; 737d8b46839SM'boumba Cedric Madianga if (chan->next_sg == chan->desc->num_sgs) { 738d8b46839SM'boumba Cedric Madianga vchan_cookie_complete(&chan->desc->vdesc); 739d8b46839SM'boumba Cedric Madianga chan->desc = NULL; 740d8b46839SM'boumba Cedric Madianga } 741d8b46839SM'boumba Cedric Madianga stm32_dma_start_transfer(chan); 742d8b46839SM'boumba Cedric Madianga } 743d8b46839SM'boumba Cedric Madianga } 744d8b46839SM'boumba Cedric Madianga 745d8b46839SM'boumba Cedric Madianga static irqreturn_t stm32_dma_chan_irq(int irq, void *devid) 746d8b46839SM'boumba Cedric Madianga { 747d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = devid; 748d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 749ca4c72c0SPierre-Yves MORDRET u32 status, scr, sfcr; 750d8b46839SM'boumba Cedric Madianga 751d8b46839SM'boumba Cedric Madianga spin_lock(&chan->vchan.lock); 752d8b46839SM'boumba Cedric Madianga 753d8b46839SM'boumba Cedric Madianga status = stm32_dma_irq_status(chan); 754d8b46839SM'boumba Cedric Madianga scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 755ca4c72c0SPierre-Yves MORDRET sfcr = stm32_dma_read(dmadev, STM32_DMA_SFCR(chan->id)); 756d8b46839SM'boumba Cedric Madianga 757c2d86b1cSPierre Yves MORDRET if (status & STM32_DMA_FEI) { 758c2d86b1cSPierre Yves MORDRET stm32_dma_irq_clear(chan, STM32_DMA_FEI); 759c2d86b1cSPierre Yves MORDRET status &= ~STM32_DMA_FEI; 760ca4c72c0SPierre-Yves MORDRET if (sfcr & STM32_DMA_SFCR_FEIE) { 761a44d9d72SAmelie Delaunay if (!(scr & STM32_DMA_SCR_EN) && 762a44d9d72SAmelie Delaunay !(status & STM32_DMA_TCI)) 763c2d86b1cSPierre Yves MORDRET dev_err(chan2dev(chan), "FIFO Error\n"); 764c2d86b1cSPierre Yves MORDRET else 765c2d86b1cSPierre Yves MORDRET dev_dbg(chan2dev(chan), "FIFO over/underrun\n"); 766c2d86b1cSPierre Yves MORDRET } 767ca4c72c0SPierre-Yves MORDRET } 768955b1766SAmelie Delaunay if (status & STM32_DMA_DMEI) { 769955b1766SAmelie Delaunay stm32_dma_irq_clear(chan, STM32_DMA_DMEI); 770955b1766SAmelie Delaunay status &= ~STM32_DMA_DMEI; 771955b1766SAmelie Delaunay if (sfcr & STM32_DMA_SCR_DMEIE) 772955b1766SAmelie Delaunay dev_dbg(chan2dev(chan), "Direct mode overrun\n"); 773955b1766SAmelie Delaunay } 774a44d9d72SAmelie Delaunay 775a44d9d72SAmelie Delaunay if (status & STM32_DMA_TCI) { 776a44d9d72SAmelie Delaunay stm32_dma_irq_clear(chan, STM32_DMA_TCI); 777*099a9a94SAmelie Delaunay if (scr & STM32_DMA_SCR_TCIE) { 778*099a9a94SAmelie Delaunay if (chan->status == DMA_PAUSED && !(scr & STM32_DMA_SCR_EN)) 779*099a9a94SAmelie Delaunay stm32_dma_handle_chan_paused(chan); 780*099a9a94SAmelie Delaunay else 781ded62306SAmelie Delaunay stm32_dma_handle_chan_done(chan, scr); 782*099a9a94SAmelie Delaunay } 783a44d9d72SAmelie Delaunay status &= ~STM32_DMA_TCI; 784a44d9d72SAmelie Delaunay } 785a44d9d72SAmelie Delaunay 786a44d9d72SAmelie Delaunay if (status & STM32_DMA_HTI) { 787a44d9d72SAmelie Delaunay stm32_dma_irq_clear(chan, STM32_DMA_HTI); 788a44d9d72SAmelie Delaunay status &= ~STM32_DMA_HTI; 789a44d9d72SAmelie Delaunay } 790a44d9d72SAmelie Delaunay 791c2d86b1cSPierre Yves MORDRET if (status) { 792d8b46839SM'boumba Cedric Madianga stm32_dma_irq_clear(chan, status); 793d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status); 794c2d86b1cSPierre Yves MORDRET if (!(scr & STM32_DMA_SCR_EN)) 795c2d86b1cSPierre Yves MORDRET dev_err(chan2dev(chan), "chan disabled by HW\n"); 796d8b46839SM'boumba Cedric Madianga } 797d8b46839SM'boumba Cedric Madianga 798d8b46839SM'boumba Cedric Madianga spin_unlock(&chan->vchan.lock); 799d8b46839SM'boumba Cedric Madianga 800d8b46839SM'boumba Cedric Madianga return IRQ_HANDLED; 801d8b46839SM'boumba Cedric Madianga } 802d8b46839SM'boumba Cedric Madianga 803d8b46839SM'boumba Cedric Madianga static void stm32_dma_issue_pending(struct dma_chan *c) 804d8b46839SM'boumba Cedric Madianga { 805d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 806d8b46839SM'boumba Cedric Madianga unsigned long flags; 807d8b46839SM'boumba Cedric Madianga 808d8b46839SM'boumba Cedric Madianga spin_lock_irqsave(&chan->vchan.lock, flags); 8098d1b76f0SM'boumba Cedric Madianga if (vchan_issue_pending(&chan->vchan) && !chan->desc && !chan->busy) { 81090ec93cbSBenjamin Gaignard dev_dbg(chan2dev(chan), "vchan %pK: issued\n", &chan->vchan); 8118d1b76f0SM'boumba Cedric Madianga stm32_dma_start_transfer(chan); 812e57cb3b3SPierre Yves MORDRET 813d8b46839SM'boumba Cedric Madianga } 814d8b46839SM'boumba Cedric Madianga spin_unlock_irqrestore(&chan->vchan.lock, flags); 815d8b46839SM'boumba Cedric Madianga } 816d8b46839SM'boumba Cedric Madianga 817*099a9a94SAmelie Delaunay static int stm32_dma_pause(struct dma_chan *c) 818*099a9a94SAmelie Delaunay { 819*099a9a94SAmelie Delaunay struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 820*099a9a94SAmelie Delaunay unsigned long flags; 821*099a9a94SAmelie Delaunay int ret; 822*099a9a94SAmelie Delaunay 823*099a9a94SAmelie Delaunay if (chan->status != DMA_IN_PROGRESS) 824*099a9a94SAmelie Delaunay return -EPERM; 825*099a9a94SAmelie Delaunay 826*099a9a94SAmelie Delaunay spin_lock_irqsave(&chan->vchan.lock, flags); 827*099a9a94SAmelie Delaunay ret = stm32_dma_disable_chan(chan); 828*099a9a94SAmelie Delaunay /* 829*099a9a94SAmelie Delaunay * A transfer complete flag is set to indicate the end of transfer due to the stream 830*099a9a94SAmelie Delaunay * interruption, so wait for interrupt 831*099a9a94SAmelie Delaunay */ 832*099a9a94SAmelie Delaunay if (!ret) 833*099a9a94SAmelie Delaunay chan->status = DMA_PAUSED; 834*099a9a94SAmelie Delaunay spin_unlock_irqrestore(&chan->vchan.lock, flags); 835*099a9a94SAmelie Delaunay 836*099a9a94SAmelie Delaunay return ret; 837*099a9a94SAmelie Delaunay } 838*099a9a94SAmelie Delaunay 839*099a9a94SAmelie Delaunay static int stm32_dma_resume(struct dma_chan *c) 840*099a9a94SAmelie Delaunay { 841*099a9a94SAmelie Delaunay struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 842*099a9a94SAmelie Delaunay struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 843*099a9a94SAmelie Delaunay struct stm32_dma_chan_reg chan_reg = chan->chan_reg; 844*099a9a94SAmelie Delaunay u32 id = chan->id, scr, ndtr, offset, spar, sm0ar, sm1ar; 845*099a9a94SAmelie Delaunay struct stm32_dma_sg_req *sg_req; 846*099a9a94SAmelie Delaunay unsigned long flags; 847*099a9a94SAmelie Delaunay 848*099a9a94SAmelie Delaunay if (chan->status != DMA_PAUSED) 849*099a9a94SAmelie Delaunay return -EPERM; 850*099a9a94SAmelie Delaunay 851*099a9a94SAmelie Delaunay scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); 852*099a9a94SAmelie Delaunay if (WARN_ON(scr & STM32_DMA_SCR_EN)) 853*099a9a94SAmelie Delaunay return -EPERM; 854*099a9a94SAmelie Delaunay 855*099a9a94SAmelie Delaunay spin_lock_irqsave(&chan->vchan.lock, flags); 856*099a9a94SAmelie Delaunay 857*099a9a94SAmelie Delaunay /* sg_reg[prev_sg] contains original ndtr, sm0ar and sm1ar before pausing the transfer */ 858*099a9a94SAmelie Delaunay if (!chan->next_sg) 859*099a9a94SAmelie Delaunay sg_req = &chan->desc->sg_req[chan->desc->num_sgs - 1]; 860*099a9a94SAmelie Delaunay else 861*099a9a94SAmelie Delaunay sg_req = &chan->desc->sg_req[chan->next_sg - 1]; 862*099a9a94SAmelie Delaunay 863*099a9a94SAmelie Delaunay ndtr = sg_req->chan_reg.dma_sndtr; 864*099a9a94SAmelie Delaunay offset = (ndtr - chan_reg.dma_sndtr) << STM32_DMA_SCR_PSIZE_GET(chan_reg.dma_scr); 865*099a9a94SAmelie Delaunay spar = sg_req->chan_reg.dma_spar; 866*099a9a94SAmelie Delaunay sm0ar = sg_req->chan_reg.dma_sm0ar; 867*099a9a94SAmelie Delaunay sm1ar = sg_req->chan_reg.dma_sm1ar; 868*099a9a94SAmelie Delaunay 869*099a9a94SAmelie Delaunay /* 870*099a9a94SAmelie Delaunay * The peripheral and/or memory addresses have to be updated in order to adjust the 871*099a9a94SAmelie Delaunay * address pointers. Need to check increment. 872*099a9a94SAmelie Delaunay */ 873*099a9a94SAmelie Delaunay if (chan_reg.dma_scr & STM32_DMA_SCR_PINC) 874*099a9a94SAmelie Delaunay stm32_dma_write(dmadev, STM32_DMA_SPAR(id), spar + offset); 875*099a9a94SAmelie Delaunay else 876*099a9a94SAmelie Delaunay stm32_dma_write(dmadev, STM32_DMA_SPAR(id), spar); 877*099a9a94SAmelie Delaunay 878*099a9a94SAmelie Delaunay if (!(chan_reg.dma_scr & STM32_DMA_SCR_MINC)) 879*099a9a94SAmelie Delaunay offset = 0; 880*099a9a94SAmelie Delaunay 881*099a9a94SAmelie Delaunay /* 882*099a9a94SAmelie Delaunay * In case of DBM, the current target could be SM1AR. 883*099a9a94SAmelie Delaunay * Need to temporarily deactivate CIRC/DBM to finish the current transfer, so 884*099a9a94SAmelie Delaunay * SM0AR becomes the current target and must be updated with SM1AR + offset if CT=1. 885*099a9a94SAmelie Delaunay */ 886*099a9a94SAmelie Delaunay if ((chan_reg.dma_scr & STM32_DMA_SCR_DBM) && (chan_reg.dma_scr & STM32_DMA_SCR_CT)) 887*099a9a94SAmelie Delaunay stm32_dma_write(dmadev, STM32_DMA_SM1AR(id), sm1ar + offset); 888*099a9a94SAmelie Delaunay else 889*099a9a94SAmelie Delaunay stm32_dma_write(dmadev, STM32_DMA_SM0AR(id), sm0ar + offset); 890*099a9a94SAmelie Delaunay 891*099a9a94SAmelie Delaunay /* NDTR must be restored otherwise internal HW counter won't be correctly reset */ 892*099a9a94SAmelie Delaunay stm32_dma_write(dmadev, STM32_DMA_SNDTR(id), chan_reg.dma_sndtr); 893*099a9a94SAmelie Delaunay 894*099a9a94SAmelie Delaunay /* 895*099a9a94SAmelie Delaunay * Need to temporarily deactivate CIRC/DBM until next Transfer Complete interrupt, 896*099a9a94SAmelie Delaunay * otherwise NDTR autoreload value will be wrong (lower than the initial period length) 897*099a9a94SAmelie Delaunay */ 898*099a9a94SAmelie Delaunay if (chan_reg.dma_scr & (STM32_DMA_SCR_CIRC | STM32_DMA_SCR_DBM)) 899*099a9a94SAmelie Delaunay chan_reg.dma_scr &= ~(STM32_DMA_SCR_CIRC | STM32_DMA_SCR_DBM); 900*099a9a94SAmelie Delaunay 901*099a9a94SAmelie Delaunay if (chan_reg.dma_scr & STM32_DMA_SCR_DBM) 902*099a9a94SAmelie Delaunay stm32_dma_configure_next_sg(chan); 903*099a9a94SAmelie Delaunay 904*099a9a94SAmelie Delaunay stm32_dma_dump_reg(chan); 905*099a9a94SAmelie Delaunay 906*099a9a94SAmelie Delaunay /* The stream may then be re-enabled to restart transfer from the point it was stopped */ 907*099a9a94SAmelie Delaunay chan->status = DMA_IN_PROGRESS; 908*099a9a94SAmelie Delaunay chan_reg.dma_scr |= STM32_DMA_SCR_EN; 909*099a9a94SAmelie Delaunay stm32_dma_write(dmadev, STM32_DMA_SCR(id), chan_reg.dma_scr); 910*099a9a94SAmelie Delaunay 911*099a9a94SAmelie Delaunay spin_unlock_irqrestore(&chan->vchan.lock, flags); 912*099a9a94SAmelie Delaunay 913*099a9a94SAmelie Delaunay dev_dbg(chan2dev(chan), "vchan %pK: resumed\n", &chan->vchan); 914*099a9a94SAmelie Delaunay 915*099a9a94SAmelie Delaunay return 0; 916*099a9a94SAmelie Delaunay } 917*099a9a94SAmelie Delaunay 918d8b46839SM'boumba Cedric Madianga static int stm32_dma_set_xfer_param(struct stm32_dma_chan *chan, 919d8b46839SM'boumba Cedric Madianga enum dma_transfer_direction direction, 920a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth *buswidth, 921e0ebdbdcSAmelie Delaunay u32 buf_len, dma_addr_t buf_addr) 922d8b46839SM'boumba Cedric Madianga { 923d8b46839SM'boumba Cedric Madianga enum dma_slave_buswidth src_addr_width, dst_addr_width; 924d8b46839SM'boumba Cedric Madianga int src_bus_width, dst_bus_width; 925d8b46839SM'boumba Cedric Madianga int src_burst_size, dst_burst_size; 926a2b6103bSPierre Yves MORDRET u32 src_maxburst, dst_maxburst, src_best_burst, dst_best_burst; 927955b1766SAmelie Delaunay u32 dma_scr, fifoth; 928d8b46839SM'boumba Cedric Madianga 929d8b46839SM'boumba Cedric Madianga src_addr_width = chan->dma_sconfig.src_addr_width; 930d8b46839SM'boumba Cedric Madianga dst_addr_width = chan->dma_sconfig.dst_addr_width; 931d8b46839SM'boumba Cedric Madianga src_maxburst = chan->dma_sconfig.src_maxburst; 932d8b46839SM'boumba Cedric Madianga dst_maxburst = chan->dma_sconfig.dst_maxburst; 933955b1766SAmelie Delaunay fifoth = chan->threshold; 934d8b46839SM'boumba Cedric Madianga 935d8b46839SM'boumba Cedric Madianga switch (direction) { 936d8b46839SM'boumba Cedric Madianga case DMA_MEM_TO_DEV: 937a2b6103bSPierre Yves MORDRET /* Set device data size */ 938d8b46839SM'boumba Cedric Madianga dst_bus_width = stm32_dma_get_width(chan, dst_addr_width); 939d8b46839SM'boumba Cedric Madianga if (dst_bus_width < 0) 940d8b46839SM'boumba Cedric Madianga return dst_bus_width; 941d8b46839SM'boumba Cedric Madianga 942a2b6103bSPierre Yves MORDRET /* Set device burst size */ 943a2b6103bSPierre Yves MORDRET dst_best_burst = stm32_dma_get_best_burst(buf_len, 944a2b6103bSPierre Yves MORDRET dst_maxburst, 945955b1766SAmelie Delaunay fifoth, 946a2b6103bSPierre Yves MORDRET dst_addr_width); 947a2b6103bSPierre Yves MORDRET 948a2b6103bSPierre Yves MORDRET dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst); 949d8b46839SM'boumba Cedric Madianga if (dst_burst_size < 0) 950d8b46839SM'boumba Cedric Madianga return dst_burst_size; 951d8b46839SM'boumba Cedric Madianga 952a2b6103bSPierre Yves MORDRET /* Set memory data size */ 953e0ebdbdcSAmelie Delaunay src_addr_width = stm32_dma_get_max_width(buf_len, buf_addr, 954e0ebdbdcSAmelie Delaunay fifoth); 955a2b6103bSPierre Yves MORDRET chan->mem_width = src_addr_width; 956d8b46839SM'boumba Cedric Madianga src_bus_width = stm32_dma_get_width(chan, src_addr_width); 957d8b46839SM'boumba Cedric Madianga if (src_bus_width < 0) 958d8b46839SM'boumba Cedric Madianga return src_bus_width; 959d8b46839SM'boumba Cedric Madianga 960af229d2cSAmelie Delaunay /* 961af229d2cSAmelie Delaunay * Set memory burst size - burst not possible if address is not aligned on 962af229d2cSAmelie Delaunay * the address boundary equal to the size of the transfer 963af229d2cSAmelie Delaunay */ 96424983633SArnd Bergmann if (buf_addr & (buf_len - 1)) 965af229d2cSAmelie Delaunay src_maxburst = 1; 966af229d2cSAmelie Delaunay else 967a2b6103bSPierre Yves MORDRET src_maxburst = STM32_DMA_MAX_BURST; 968a2b6103bSPierre Yves MORDRET src_best_burst = stm32_dma_get_best_burst(buf_len, 969a2b6103bSPierre Yves MORDRET src_maxburst, 970955b1766SAmelie Delaunay fifoth, 971a2b6103bSPierre Yves MORDRET src_addr_width); 972a2b6103bSPierre Yves MORDRET src_burst_size = stm32_dma_get_burst(chan, src_best_burst); 973d8b46839SM'boumba Cedric Madianga if (src_burst_size < 0) 974d8b46839SM'boumba Cedric Madianga return src_burst_size; 975d8b46839SM'boumba Cedric Madianga 976d8b46839SM'boumba Cedric Madianga dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_DEV) | 977d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PSIZE(dst_bus_width) | 978d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MSIZE(src_bus_width) | 979d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PBURST(dst_burst_size) | 980d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MBURST(src_burst_size); 981d8b46839SM'boumba Cedric Madianga 982a2b6103bSPierre Yves MORDRET /* Set FIFO threshold */ 983a2b6103bSPierre Yves MORDRET chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; 984955b1766SAmelie Delaunay if (fifoth != STM32_DMA_FIFO_THRESHOLD_NONE) 985955b1766SAmelie Delaunay chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth); 986a2b6103bSPierre Yves MORDRET 987a2b6103bSPierre Yves MORDRET /* Set peripheral address */ 988d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_spar = chan->dma_sconfig.dst_addr; 989d8b46839SM'boumba Cedric Madianga *buswidth = dst_addr_width; 990d8b46839SM'boumba Cedric Madianga break; 991d8b46839SM'boumba Cedric Madianga 992d8b46839SM'boumba Cedric Madianga case DMA_DEV_TO_MEM: 993a2b6103bSPierre Yves MORDRET /* Set device data size */ 994d8b46839SM'boumba Cedric Madianga src_bus_width = stm32_dma_get_width(chan, src_addr_width); 995d8b46839SM'boumba Cedric Madianga if (src_bus_width < 0) 996d8b46839SM'boumba Cedric Madianga return src_bus_width; 997d8b46839SM'boumba Cedric Madianga 998a2b6103bSPierre Yves MORDRET /* Set device burst size */ 999a2b6103bSPierre Yves MORDRET src_best_burst = stm32_dma_get_best_burst(buf_len, 1000a2b6103bSPierre Yves MORDRET src_maxburst, 1001955b1766SAmelie Delaunay fifoth, 1002a2b6103bSPierre Yves MORDRET src_addr_width); 1003a2b6103bSPierre Yves MORDRET chan->mem_burst = src_best_burst; 1004a2b6103bSPierre Yves MORDRET src_burst_size = stm32_dma_get_burst(chan, src_best_burst); 1005d8b46839SM'boumba Cedric Madianga if (src_burst_size < 0) 1006d8b46839SM'boumba Cedric Madianga return src_burst_size; 1007d8b46839SM'boumba Cedric Madianga 1008a2b6103bSPierre Yves MORDRET /* Set memory data size */ 1009e0ebdbdcSAmelie Delaunay dst_addr_width = stm32_dma_get_max_width(buf_len, buf_addr, 1010e0ebdbdcSAmelie Delaunay fifoth); 1011a2b6103bSPierre Yves MORDRET chan->mem_width = dst_addr_width; 1012d8b46839SM'boumba Cedric Madianga dst_bus_width = stm32_dma_get_width(chan, dst_addr_width); 1013d8b46839SM'boumba Cedric Madianga if (dst_bus_width < 0) 1014d8b46839SM'boumba Cedric Madianga return dst_bus_width; 1015d8b46839SM'boumba Cedric Madianga 1016af229d2cSAmelie Delaunay /* 1017af229d2cSAmelie Delaunay * Set memory burst size - burst not possible if address is not aligned on 1018af229d2cSAmelie Delaunay * the address boundary equal to the size of the transfer 1019af229d2cSAmelie Delaunay */ 102024983633SArnd Bergmann if (buf_addr & (buf_len - 1)) 1021af229d2cSAmelie Delaunay dst_maxburst = 1; 1022af229d2cSAmelie Delaunay else 1023a2b6103bSPierre Yves MORDRET dst_maxburst = STM32_DMA_MAX_BURST; 1024a2b6103bSPierre Yves MORDRET dst_best_burst = stm32_dma_get_best_burst(buf_len, 1025a2b6103bSPierre Yves MORDRET dst_maxburst, 1026955b1766SAmelie Delaunay fifoth, 1027a2b6103bSPierre Yves MORDRET dst_addr_width); 1028a2b6103bSPierre Yves MORDRET chan->mem_burst = dst_best_burst; 1029a2b6103bSPierre Yves MORDRET dst_burst_size = stm32_dma_get_burst(chan, dst_best_burst); 1030d8b46839SM'boumba Cedric Madianga if (dst_burst_size < 0) 1031d8b46839SM'boumba Cedric Madianga return dst_burst_size; 1032d8b46839SM'boumba Cedric Madianga 1033d8b46839SM'boumba Cedric Madianga dma_scr = STM32_DMA_SCR_DIR(STM32_DMA_DEV_TO_MEM) | 1034d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PSIZE(src_bus_width) | 1035d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MSIZE(dst_bus_width) | 1036d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PBURST(src_burst_size) | 1037d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MBURST(dst_burst_size); 1038d8b46839SM'boumba Cedric Madianga 1039a2b6103bSPierre Yves MORDRET /* Set FIFO threshold */ 1040a2b6103bSPierre Yves MORDRET chan->chan_reg.dma_sfcr &= ~STM32_DMA_SFCR_FTH_MASK; 1041955b1766SAmelie Delaunay if (fifoth != STM32_DMA_FIFO_THRESHOLD_NONE) 1042955b1766SAmelie Delaunay chan->chan_reg.dma_sfcr |= STM32_DMA_SFCR_FTH(fifoth); 1043a2b6103bSPierre Yves MORDRET 1044a2b6103bSPierre Yves MORDRET /* Set peripheral address */ 1045d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_spar = chan->dma_sconfig.src_addr; 1046d8b46839SM'boumba Cedric Madianga *buswidth = chan->dma_sconfig.src_addr_width; 1047d8b46839SM'boumba Cedric Madianga break; 1048d8b46839SM'boumba Cedric Madianga 1049d8b46839SM'boumba Cedric Madianga default: 1050d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Dma direction is not supported\n"); 1051d8b46839SM'boumba Cedric Madianga return -EINVAL; 1052d8b46839SM'boumba Cedric Madianga } 1053d8b46839SM'boumba Cedric Madianga 1054a2b6103bSPierre Yves MORDRET stm32_dma_set_fifo_config(chan, src_best_burst, dst_best_burst); 1055d8b46839SM'boumba Cedric Madianga 1056a2b6103bSPierre Yves MORDRET /* Set DMA control register */ 1057d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr &= ~(STM32_DMA_SCR_DIR_MASK | 1058d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PSIZE_MASK | STM32_DMA_SCR_MSIZE_MASK | 1059d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PBURST_MASK | STM32_DMA_SCR_MBURST_MASK); 1060d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= dma_scr; 1061d8b46839SM'boumba Cedric Madianga 1062d8b46839SM'boumba Cedric Madianga return 0; 1063d8b46839SM'boumba Cedric Madianga } 1064d8b46839SM'boumba Cedric Madianga 1065d8b46839SM'boumba Cedric Madianga static void stm32_dma_clear_reg(struct stm32_dma_chan_reg *regs) 1066d8b46839SM'boumba Cedric Madianga { 1067d8b46839SM'boumba Cedric Madianga memset(regs, 0, sizeof(struct stm32_dma_chan_reg)); 1068d8b46839SM'boumba Cedric Madianga } 1069d8b46839SM'boumba Cedric Madianga 1070d8b46839SM'boumba Cedric Madianga static struct dma_async_tx_descriptor *stm32_dma_prep_slave_sg( 1071d8b46839SM'boumba Cedric Madianga struct dma_chan *c, struct scatterlist *sgl, 1072d8b46839SM'boumba Cedric Madianga u32 sg_len, enum dma_transfer_direction direction, 1073d8b46839SM'boumba Cedric Madianga unsigned long flags, void *context) 1074d8b46839SM'boumba Cedric Madianga { 1075d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1076d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc; 1077d8b46839SM'boumba Cedric Madianga struct scatterlist *sg; 1078d8b46839SM'boumba Cedric Madianga enum dma_slave_buswidth buswidth; 1079d8b46839SM'boumba Cedric Madianga u32 nb_data_items; 1080d8b46839SM'boumba Cedric Madianga int i, ret; 1081d8b46839SM'boumba Cedric Madianga 1082d8b46839SM'boumba Cedric Madianga if (!chan->config_init) { 1083d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "dma channel is not configured\n"); 1084d8b46839SM'boumba Cedric Madianga return NULL; 1085d8b46839SM'boumba Cedric Madianga } 1086d8b46839SM'boumba Cedric Madianga 1087d8b46839SM'boumba Cedric Madianga if (sg_len < 1) { 1088d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Invalid segment length %d\n", sg_len); 1089d8b46839SM'boumba Cedric Madianga return NULL; 1090d8b46839SM'boumba Cedric Madianga } 1091d8b46839SM'boumba Cedric Madianga 1092402096cbSGustavo A. R. Silva desc = kzalloc(struct_size(desc, sg_req, sg_len), GFP_NOWAIT); 1093d8b46839SM'boumba Cedric Madianga if (!desc) 1094d8b46839SM'boumba Cedric Madianga return NULL; 1095d8b46839SM'boumba Cedric Madianga 1096d8b46839SM'boumba Cedric Madianga /* Set peripheral flow controller */ 1097d8b46839SM'boumba Cedric Madianga if (chan->dma_sconfig.device_fc) 1098d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_PFCTRL; 1099d8b46839SM'boumba Cedric Madianga else 1100d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; 1101d8b46839SM'boumba Cedric Madianga 1102d8b46839SM'boumba Cedric Madianga for_each_sg(sgl, sg, sg_len, i) { 1103a2b6103bSPierre Yves MORDRET ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, 1104e0ebdbdcSAmelie Delaunay sg_dma_len(sg), 1105e0ebdbdcSAmelie Delaunay sg_dma_address(sg)); 1106a2b6103bSPierre Yves MORDRET if (ret < 0) 1107a2b6103bSPierre Yves MORDRET goto err; 1108a2b6103bSPierre Yves MORDRET 1109d8b46839SM'boumba Cedric Madianga desc->sg_req[i].len = sg_dma_len(sg); 1110d8b46839SM'boumba Cedric Madianga 1111d8b46839SM'boumba Cedric Madianga nb_data_items = desc->sg_req[i].len / buswidth; 111280a76952SPierre Yves MORDRET if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) { 1113d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "nb items not supported\n"); 1114d8b46839SM'boumba Cedric Madianga goto err; 1115d8b46839SM'boumba Cedric Madianga } 1116d8b46839SM'boumba Cedric Madianga 1117d8b46839SM'boumba Cedric Madianga stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); 1118d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; 1119d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; 1120d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; 1121d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm0ar = sg_dma_address(sg); 1122d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm1ar = sg_dma_address(sg); 1123d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items; 1124d8b46839SM'boumba Cedric Madianga } 1125d8b46839SM'boumba Cedric Madianga 1126d8b46839SM'boumba Cedric Madianga desc->num_sgs = sg_len; 1127d8b46839SM'boumba Cedric Madianga desc->cyclic = false; 1128d8b46839SM'boumba Cedric Madianga 1129d8b46839SM'boumba Cedric Madianga return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); 1130d8b46839SM'boumba Cedric Madianga 1131d8b46839SM'boumba Cedric Madianga err: 1132d8b46839SM'boumba Cedric Madianga kfree(desc); 1133d8b46839SM'boumba Cedric Madianga return NULL; 1134d8b46839SM'boumba Cedric Madianga } 1135d8b46839SM'boumba Cedric Madianga 1136d8b46839SM'boumba Cedric Madianga static struct dma_async_tx_descriptor *stm32_dma_prep_dma_cyclic( 1137d8b46839SM'boumba Cedric Madianga struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len, 1138d8b46839SM'boumba Cedric Madianga size_t period_len, enum dma_transfer_direction direction, 1139d8b46839SM'boumba Cedric Madianga unsigned long flags) 1140d8b46839SM'boumba Cedric Madianga { 1141d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1142d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc; 1143d8b46839SM'boumba Cedric Madianga enum dma_slave_buswidth buswidth; 1144d8b46839SM'boumba Cedric Madianga u32 num_periods, nb_data_items; 1145d8b46839SM'boumba Cedric Madianga int i, ret; 1146d8b46839SM'boumba Cedric Madianga 1147d8b46839SM'boumba Cedric Madianga if (!buf_len || !period_len) { 1148d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Invalid buffer/period len\n"); 1149d8b46839SM'boumba Cedric Madianga return NULL; 1150d8b46839SM'boumba Cedric Madianga } 1151d8b46839SM'boumba Cedric Madianga 1152d8b46839SM'boumba Cedric Madianga if (!chan->config_init) { 1153d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "dma channel is not configured\n"); 1154d8b46839SM'boumba Cedric Madianga return NULL; 1155d8b46839SM'boumba Cedric Madianga } 1156d8b46839SM'boumba Cedric Madianga 1157d8b46839SM'boumba Cedric Madianga if (buf_len % period_len) { 1158d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "buf_len not multiple of period_len\n"); 1159d8b46839SM'boumba Cedric Madianga return NULL; 1160d8b46839SM'boumba Cedric Madianga } 1161d8b46839SM'boumba Cedric Madianga 1162d8b46839SM'boumba Cedric Madianga /* 1163d8b46839SM'boumba Cedric Madianga * We allow to take more number of requests till DMA is 1164d8b46839SM'boumba Cedric Madianga * not started. The driver will loop over all requests. 1165d8b46839SM'boumba Cedric Madianga * Once DMA is started then new requests can be queued only after 1166d8b46839SM'boumba Cedric Madianga * terminating the DMA. 1167d8b46839SM'boumba Cedric Madianga */ 1168d8b46839SM'boumba Cedric Madianga if (chan->busy) { 1169d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "Request not allowed when dma busy\n"); 1170d8b46839SM'boumba Cedric Madianga return NULL; 1171d8b46839SM'boumba Cedric Madianga } 1172d8b46839SM'boumba Cedric Madianga 1173e0ebdbdcSAmelie Delaunay ret = stm32_dma_set_xfer_param(chan, direction, &buswidth, period_len, 1174e0ebdbdcSAmelie Delaunay buf_addr); 1175d8b46839SM'boumba Cedric Madianga if (ret < 0) 1176d8b46839SM'boumba Cedric Madianga return NULL; 1177d8b46839SM'boumba Cedric Madianga 1178d8b46839SM'boumba Cedric Madianga nb_data_items = period_len / buswidth; 117980a76952SPierre Yves MORDRET if (nb_data_items > STM32_DMA_ALIGNED_MAX_DATA_ITEMS) { 1180d8b46839SM'boumba Cedric Madianga dev_err(chan2dev(chan), "number of items not supported\n"); 1181d8b46839SM'boumba Cedric Madianga return NULL; 1182d8b46839SM'boumba Cedric Madianga } 1183d8b46839SM'boumba Cedric Madianga 1184d8b46839SM'boumba Cedric Madianga /* Enable Circular mode or double buffer mode */ 1185*099a9a94SAmelie Delaunay if (buf_len == period_len) { 1186d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_CIRC; 1187*099a9a94SAmelie Delaunay } else { 1188d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_DBM; 1189*099a9a94SAmelie Delaunay chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_CT; 1190*099a9a94SAmelie Delaunay } 1191d8b46839SM'boumba Cedric Madianga 1192d8b46839SM'boumba Cedric Madianga /* Clear periph ctrl if client set it */ 1193d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr &= ~STM32_DMA_SCR_PFCTRL; 1194d8b46839SM'boumba Cedric Madianga 1195d8b46839SM'boumba Cedric Madianga num_periods = buf_len / period_len; 1196d8b46839SM'boumba Cedric Madianga 1197402096cbSGustavo A. R. Silva desc = kzalloc(struct_size(desc, sg_req, num_periods), GFP_NOWAIT); 1198d8b46839SM'boumba Cedric Madianga if (!desc) 1199d8b46839SM'boumba Cedric Madianga return NULL; 1200d8b46839SM'boumba Cedric Madianga 1201d8b46839SM'boumba Cedric Madianga for (i = 0; i < num_periods; i++) { 1202d8b46839SM'boumba Cedric Madianga desc->sg_req[i].len = period_len; 1203d8b46839SM'boumba Cedric Madianga 1204d8b46839SM'boumba Cedric Madianga stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); 1205d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_scr = chan->chan_reg.dma_scr; 1206d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sfcr = chan->chan_reg.dma_sfcr; 1207d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_spar = chan->chan_reg.dma_spar; 1208d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm0ar = buf_addr; 1209d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm1ar = buf_addr; 1210d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sndtr = nb_data_items; 1211d8b46839SM'boumba Cedric Madianga buf_addr += period_len; 1212d8b46839SM'boumba Cedric Madianga } 1213d8b46839SM'boumba Cedric Madianga 1214d8b46839SM'boumba Cedric Madianga desc->num_sgs = num_periods; 1215d8b46839SM'boumba Cedric Madianga desc->cyclic = true; 1216d8b46839SM'boumba Cedric Madianga 1217d8b46839SM'boumba Cedric Madianga return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); 1218d8b46839SM'boumba Cedric Madianga } 1219d8b46839SM'boumba Cedric Madianga 1220d8b46839SM'boumba Cedric Madianga static struct dma_async_tx_descriptor *stm32_dma_prep_dma_memcpy( 1221d8b46839SM'boumba Cedric Madianga struct dma_chan *c, dma_addr_t dest, 1222d8b46839SM'boumba Cedric Madianga dma_addr_t src, size_t len, unsigned long flags) 1223d8b46839SM'boumba Cedric Madianga { 1224d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1225a2b6103bSPierre Yves MORDRET enum dma_slave_buswidth max_width; 1226d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc; 1227d8b46839SM'boumba Cedric Madianga size_t xfer_count, offset; 1228a2b6103bSPierre Yves MORDRET u32 num_sgs, best_burst, dma_burst, threshold; 1229d8b46839SM'boumba Cedric Madianga int i; 1230d8b46839SM'boumba Cedric Madianga 123180a76952SPierre Yves MORDRET num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS); 1232402096cbSGustavo A. R. Silva desc = kzalloc(struct_size(desc, sg_req, num_sgs), GFP_NOWAIT); 1233d8b46839SM'boumba Cedric Madianga if (!desc) 1234d8b46839SM'boumba Cedric Madianga return NULL; 1235d8b46839SM'boumba Cedric Madianga 1236a2b6103bSPierre Yves MORDRET threshold = chan->threshold; 1237a2b6103bSPierre Yves MORDRET 1238d8b46839SM'boumba Cedric Madianga for (offset = 0, i = 0; offset < len; offset += xfer_count, i++) { 1239d8b46839SM'boumba Cedric Madianga xfer_count = min_t(size_t, len - offset, 124080a76952SPierre Yves MORDRET STM32_DMA_ALIGNED_MAX_DATA_ITEMS); 1241d8b46839SM'boumba Cedric Madianga 1242a2b6103bSPierre Yves MORDRET /* Compute best burst size */ 1243a2b6103bSPierre Yves MORDRET max_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1244a2b6103bSPierre Yves MORDRET best_burst = stm32_dma_get_best_burst(len, STM32_DMA_MAX_BURST, 1245a2b6103bSPierre Yves MORDRET threshold, max_width); 1246a2b6103bSPierre Yves MORDRET dma_burst = stm32_dma_get_burst(chan, best_burst); 1247d8b46839SM'boumba Cedric Madianga 1248d8b46839SM'boumba Cedric Madianga stm32_dma_clear_reg(&desc->sg_req[i].chan_reg); 1249d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_scr = 1250d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_DIR(STM32_DMA_MEM_TO_MEM) | 1251a2b6103bSPierre Yves MORDRET STM32_DMA_SCR_PBURST(dma_burst) | 1252a2b6103bSPierre Yves MORDRET STM32_DMA_SCR_MBURST(dma_burst) | 1253d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_MINC | 1254d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_PINC | 1255d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_TCIE | 1256d8b46839SM'boumba Cedric Madianga STM32_DMA_SCR_TEIE; 1257a2b6103bSPierre Yves MORDRET desc->sg_req[i].chan_reg.dma_sfcr |= STM32_DMA_SFCR_MASK; 1258a2b6103bSPierre Yves MORDRET desc->sg_req[i].chan_reg.dma_sfcr |= 1259a2b6103bSPierre Yves MORDRET STM32_DMA_SFCR_FTH(threshold); 1260d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_spar = src + offset; 1261d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sm0ar = dest + offset; 1262d8b46839SM'boumba Cedric Madianga desc->sg_req[i].chan_reg.dma_sndtr = xfer_count; 1263a2b6103bSPierre Yves MORDRET desc->sg_req[i].len = xfer_count; 1264d8b46839SM'boumba Cedric Madianga } 1265d8b46839SM'boumba Cedric Madianga 1266d8b46839SM'boumba Cedric Madianga desc->num_sgs = num_sgs; 1267d8b46839SM'boumba Cedric Madianga desc->cyclic = false; 1268d8b46839SM'boumba Cedric Madianga 1269d8b46839SM'boumba Cedric Madianga return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags); 1270d8b46839SM'boumba Cedric Madianga } 1271d8b46839SM'boumba Cedric Madianga 12722b12c558SM'boumba Cedric Madianga static u32 stm32_dma_get_remaining_bytes(struct stm32_dma_chan *chan) 12732b12c558SM'boumba Cedric Madianga { 12742b12c558SM'boumba Cedric Madianga u32 dma_scr, width, ndtr; 12752b12c558SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 12762b12c558SM'boumba Cedric Madianga 12772b12c558SM'boumba Cedric Madianga dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id)); 12782b12c558SM'boumba Cedric Madianga width = STM32_DMA_SCR_PSIZE_GET(dma_scr); 12792b12c558SM'boumba Cedric Madianga ndtr = stm32_dma_read(dmadev, STM32_DMA_SNDTR(chan->id)); 12802b12c558SM'boumba Cedric Madianga 12812b12c558SM'boumba Cedric Madianga return ndtr << width; 12822b12c558SM'boumba Cedric Madianga } 12832b12c558SM'boumba Cedric Madianga 12842a4885abSArnaud Pouliquen /** 12852a4885abSArnaud Pouliquen * stm32_dma_is_current_sg - check that expected sg_req is currently transferred 12862a4885abSArnaud Pouliquen * @chan: dma channel 12872a4885abSArnaud Pouliquen * 12882a4885abSArnaud Pouliquen * This function called when IRQ are disable, checks that the hardware has not 12892a4885abSArnaud Pouliquen * switched on the next transfer in double buffer mode. The test is done by 12902a4885abSArnaud Pouliquen * comparing the next_sg memory address with the hardware related register 12912a4885abSArnaud Pouliquen * (based on CT bit value). 12922a4885abSArnaud Pouliquen * 12932a4885abSArnaud Pouliquen * Returns true if expected current transfer is still running or double 12942a4885abSArnaud Pouliquen * buffer mode is not activated. 12952a4885abSArnaud Pouliquen */ 12962a4885abSArnaud Pouliquen static bool stm32_dma_is_current_sg(struct stm32_dma_chan *chan) 12972a4885abSArnaud Pouliquen { 12982a4885abSArnaud Pouliquen struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 12992a4885abSArnaud Pouliquen struct stm32_dma_sg_req *sg_req; 1300*099a9a94SAmelie Delaunay u32 dma_scr, dma_smar, id, period_len; 13012a4885abSArnaud Pouliquen 13022a4885abSArnaud Pouliquen id = chan->id; 13032a4885abSArnaud Pouliquen dma_scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); 13042a4885abSArnaud Pouliquen 1305*099a9a94SAmelie Delaunay /* In cyclic CIRC but not DBM, CT is not used */ 13062a4885abSArnaud Pouliquen if (!(dma_scr & STM32_DMA_SCR_DBM)) 13072a4885abSArnaud Pouliquen return true; 13082a4885abSArnaud Pouliquen 13092a4885abSArnaud Pouliquen sg_req = &chan->desc->sg_req[chan->next_sg]; 1310*099a9a94SAmelie Delaunay period_len = sg_req->len; 13112a4885abSArnaud Pouliquen 1312*099a9a94SAmelie Delaunay /* DBM - take care of a previous pause/resume not yet post reconfigured */ 13132a4885abSArnaud Pouliquen if (dma_scr & STM32_DMA_SCR_CT) { 13142a4885abSArnaud Pouliquen dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM0AR(id)); 1315*099a9a94SAmelie Delaunay /* 1316*099a9a94SAmelie Delaunay * If transfer has been pause/resumed, 1317*099a9a94SAmelie Delaunay * SM0AR is in the range of [SM0AR:SM0AR+period_len] 1318*099a9a94SAmelie Delaunay */ 1319*099a9a94SAmelie Delaunay return (dma_smar >= sg_req->chan_reg.dma_sm0ar && 1320*099a9a94SAmelie Delaunay dma_smar < sg_req->chan_reg.dma_sm0ar + period_len); 13212a4885abSArnaud Pouliquen } 13222a4885abSArnaud Pouliquen 13232a4885abSArnaud Pouliquen dma_smar = stm32_dma_read(dmadev, STM32_DMA_SM1AR(id)); 1324*099a9a94SAmelie Delaunay /* 1325*099a9a94SAmelie Delaunay * If transfer has been pause/resumed, 1326*099a9a94SAmelie Delaunay * SM1AR is in the range of [SM1AR:SM1AR+period_len] 1327*099a9a94SAmelie Delaunay */ 1328*099a9a94SAmelie Delaunay return (dma_smar >= sg_req->chan_reg.dma_sm1ar && 1329*099a9a94SAmelie Delaunay dma_smar < sg_req->chan_reg.dma_sm1ar + period_len); 13302a4885abSArnaud Pouliquen } 13312a4885abSArnaud Pouliquen 1332d8b46839SM'boumba Cedric Madianga static size_t stm32_dma_desc_residue(struct stm32_dma_chan *chan, 1333d8b46839SM'boumba Cedric Madianga struct stm32_dma_desc *desc, 1334d8b46839SM'boumba Cedric Madianga u32 next_sg) 1335d8b46839SM'boumba Cedric Madianga { 1336a2b6103bSPierre Yves MORDRET u32 modulo, burst_size; 13372a4885abSArnaud Pouliquen u32 residue; 13382a4885abSArnaud Pouliquen u32 n_sg = next_sg; 13392a4885abSArnaud Pouliquen struct stm32_dma_sg_req *sg_req = &chan->desc->sg_req[chan->next_sg]; 1340d8b46839SM'boumba Cedric Madianga int i; 1341d8b46839SM'boumba Cedric Madianga 13422b12c558SM'boumba Cedric Madianga /* 13432a4885abSArnaud Pouliquen * Calculate the residue means compute the descriptors 13442a4885abSArnaud Pouliquen * information: 13452a4885abSArnaud Pouliquen * - the sg_req currently transferred 13462a4885abSArnaud Pouliquen * - the Hardware remaining position in this sg (NDTR bits field). 13472a4885abSArnaud Pouliquen * 13482a4885abSArnaud Pouliquen * A race condition may occur if DMA is running in cyclic or double 13492a4885abSArnaud Pouliquen * buffer mode, since the DMA register are automatically reloaded at end 13502a4885abSArnaud Pouliquen * of period transfer. The hardware may have switched to the next 13512a4885abSArnaud Pouliquen * transfer (CT bit updated) just before the position (SxNDTR reg) is 13522a4885abSArnaud Pouliquen * read. 13532a4885abSArnaud Pouliquen * In this case the SxNDTR reg could (or not) correspond to the new 13542a4885abSArnaud Pouliquen * transfer position, and not the expected one. 13552a4885abSArnaud Pouliquen * The strategy implemented in the stm32 driver is to: 13562a4885abSArnaud Pouliquen * - read the SxNDTR register 13572a4885abSArnaud Pouliquen * - crosscheck that hardware is still in current transfer. 13582a4885abSArnaud Pouliquen * In case of switch, we can assume that the DMA is at the beginning of 13592a4885abSArnaud Pouliquen * the next transfer. So we approximate the residue in consequence, by 13602a4885abSArnaud Pouliquen * pointing on the beginning of next transfer. 13612a4885abSArnaud Pouliquen * 13622a4885abSArnaud Pouliquen * This race condition doesn't apply for none cyclic mode, as double 13632a4885abSArnaud Pouliquen * buffer is not used. In such situation registers are updated by the 13642a4885abSArnaud Pouliquen * software. 13652b12c558SM'boumba Cedric Madianga */ 13662a4885abSArnaud Pouliquen 1367a2b6103bSPierre Yves MORDRET residue = stm32_dma_get_remaining_bytes(chan); 13682a4885abSArnaud Pouliquen 1369*099a9a94SAmelie Delaunay if (chan->desc->cyclic && !stm32_dma_is_current_sg(chan)) { 13702a4885abSArnaud Pouliquen n_sg++; 13712a4885abSArnaud Pouliquen if (n_sg == chan->desc->num_sgs) 13722a4885abSArnaud Pouliquen n_sg = 0; 13732a4885abSArnaud Pouliquen residue = sg_req->len; 1374a2b6103bSPierre Yves MORDRET } 1375d8b46839SM'boumba Cedric Madianga 13762b12c558SM'boumba Cedric Madianga /* 13772a4885abSArnaud Pouliquen * In cyclic mode, for the last period, residue = remaining bytes 13782a4885abSArnaud Pouliquen * from NDTR, 13792a4885abSArnaud Pouliquen * else for all other periods in cyclic mode, and in sg mode, 13802a4885abSArnaud Pouliquen * residue = remaining bytes from NDTR + remaining 13812a4885abSArnaud Pouliquen * periods/sg to be transferred 13822b12c558SM'boumba Cedric Madianga */ 13832a4885abSArnaud Pouliquen if (!chan->desc->cyclic || n_sg != 0) 13842a4885abSArnaud Pouliquen for (i = n_sg; i < desc->num_sgs; i++) 1385d8b46839SM'boumba Cedric Madianga residue += desc->sg_req[i].len; 1386d8b46839SM'boumba Cedric Madianga 1387a2b6103bSPierre Yves MORDRET if (!chan->mem_burst) 1388a2b6103bSPierre Yves MORDRET return residue; 1389a2b6103bSPierre Yves MORDRET 1390a2b6103bSPierre Yves MORDRET burst_size = chan->mem_burst * chan->mem_width; 1391a2b6103bSPierre Yves MORDRET modulo = residue % burst_size; 1392a2b6103bSPierre Yves MORDRET if (modulo) 1393a2b6103bSPierre Yves MORDRET residue = residue - modulo + burst_size; 1394a2b6103bSPierre Yves MORDRET 1395d8b46839SM'boumba Cedric Madianga return residue; 1396d8b46839SM'boumba Cedric Madianga } 1397d8b46839SM'boumba Cedric Madianga 1398d8b46839SM'boumba Cedric Madianga static enum dma_status stm32_dma_tx_status(struct dma_chan *c, 1399d8b46839SM'boumba Cedric Madianga dma_cookie_t cookie, 1400d8b46839SM'boumba Cedric Madianga struct dma_tx_state *state) 1401d8b46839SM'boumba Cedric Madianga { 1402d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1403d8b46839SM'boumba Cedric Madianga struct virt_dma_desc *vdesc; 1404d8b46839SM'boumba Cedric Madianga enum dma_status status; 1405d8b46839SM'boumba Cedric Madianga unsigned long flags; 140657b5a321SM'boumba Cedric Madianga u32 residue = 0; 1407d8b46839SM'boumba Cedric Madianga 1408d8b46839SM'boumba Cedric Madianga status = dma_cookie_status(c, cookie, state); 1409*099a9a94SAmelie Delaunay if (status == DMA_COMPLETE) 1410*099a9a94SAmelie Delaunay return status; 1411*099a9a94SAmelie Delaunay 1412*099a9a94SAmelie Delaunay status = chan->status; 1413*099a9a94SAmelie Delaunay 1414*099a9a94SAmelie Delaunay if (!state) 1415d8b46839SM'boumba Cedric Madianga return status; 1416d8b46839SM'boumba Cedric Madianga 1417d8b46839SM'boumba Cedric Madianga spin_lock_irqsave(&chan->vchan.lock, flags); 1418d8b46839SM'boumba Cedric Madianga vdesc = vchan_find_desc(&chan->vchan, cookie); 141957b5a321SM'boumba Cedric Madianga if (chan->desc && cookie == chan->desc->vdesc.tx.cookie) 1420d8b46839SM'boumba Cedric Madianga residue = stm32_dma_desc_residue(chan, chan->desc, 1421d8b46839SM'boumba Cedric Madianga chan->next_sg); 142257b5a321SM'boumba Cedric Madianga else if (vdesc) 1423d8b46839SM'boumba Cedric Madianga residue = stm32_dma_desc_residue(chan, 1424d8b46839SM'boumba Cedric Madianga to_stm32_dma_desc(vdesc), 0); 1425d8b46839SM'boumba Cedric Madianga dma_set_residue(state, residue); 1426d8b46839SM'boumba Cedric Madianga 1427d8b46839SM'boumba Cedric Madianga spin_unlock_irqrestore(&chan->vchan.lock, flags); 1428d8b46839SM'boumba Cedric Madianga 1429d8b46839SM'boumba Cedric Madianga return status; 1430d8b46839SM'boumba Cedric Madianga } 1431d8b46839SM'boumba Cedric Madianga 1432d8b46839SM'boumba Cedric Madianga static int stm32_dma_alloc_chan_resources(struct dma_chan *c) 1433d8b46839SM'boumba Cedric Madianga { 1434d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1435d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 1436d8b46839SM'boumba Cedric Madianga int ret; 1437d8b46839SM'boumba Cedric Madianga 1438d8b46839SM'boumba Cedric Madianga chan->config_init = false; 143948bc73baSPierre-Yves MORDRET 1440d54db74aSZhang Qilong ret = pm_runtime_resume_and_get(dmadev->ddev.dev); 144148bc73baSPierre-Yves MORDRET if (ret < 0) 1442d8b46839SM'boumba Cedric Madianga return ret; 1443d8b46839SM'boumba Cedric Madianga 1444d8b46839SM'boumba Cedric Madianga ret = stm32_dma_disable_chan(chan); 1445d8b46839SM'boumba Cedric Madianga if (ret < 0) 144648bc73baSPierre-Yves MORDRET pm_runtime_put(dmadev->ddev.dev); 1447d8b46839SM'boumba Cedric Madianga 1448d8b46839SM'boumba Cedric Madianga return ret; 1449d8b46839SM'boumba Cedric Madianga } 1450d8b46839SM'boumba Cedric Madianga 1451d8b46839SM'boumba Cedric Madianga static void stm32_dma_free_chan_resources(struct dma_chan *c) 1452d8b46839SM'boumba Cedric Madianga { 1453d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan = to_stm32_dma_chan(c); 1454d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = stm32_dma_get_dev(chan); 1455d8b46839SM'boumba Cedric Madianga unsigned long flags; 1456d8b46839SM'boumba Cedric Madianga 1457d8b46839SM'boumba Cedric Madianga dev_dbg(chan2dev(chan), "Freeing channel %d\n", chan->id); 1458d8b46839SM'boumba Cedric Madianga 1459d8b46839SM'boumba Cedric Madianga if (chan->busy) { 1460d8b46839SM'boumba Cedric Madianga spin_lock_irqsave(&chan->vchan.lock, flags); 1461d8b46839SM'boumba Cedric Madianga stm32_dma_stop(chan); 1462d8b46839SM'boumba Cedric Madianga chan->desc = NULL; 1463d8b46839SM'boumba Cedric Madianga spin_unlock_irqrestore(&chan->vchan.lock, flags); 1464d8b46839SM'boumba Cedric Madianga } 1465d8b46839SM'boumba Cedric Madianga 146648bc73baSPierre-Yves MORDRET pm_runtime_put(dmadev->ddev.dev); 1467d8b46839SM'boumba Cedric Madianga 1468d8b46839SM'boumba Cedric Madianga vchan_free_chan_resources(to_virt_chan(c)); 14695d4d4dfbSAmelie Delaunay stm32_dma_clear_reg(&chan->chan_reg); 14705d4d4dfbSAmelie Delaunay chan->threshold = 0; 1471d8b46839SM'boumba Cedric Madianga } 1472d8b46839SM'boumba Cedric Madianga 1473d8b46839SM'boumba Cedric Madianga static void stm32_dma_desc_free(struct virt_dma_desc *vdesc) 1474d8b46839SM'boumba Cedric Madianga { 1475d8b46839SM'boumba Cedric Madianga kfree(container_of(vdesc, struct stm32_dma_desc, vdesc)); 1476d8b46839SM'boumba Cedric Madianga } 1477d8b46839SM'boumba Cedric Madianga 1478e97adb49SVinod Koul static void stm32_dma_set_config(struct stm32_dma_chan *chan, 1479d8b46839SM'boumba Cedric Madianga struct stm32_dma_cfg *cfg) 1480d8b46839SM'boumba Cedric Madianga { 1481d8b46839SM'boumba Cedric Madianga stm32_dma_clear_reg(&chan->chan_reg); 1482d8b46839SM'boumba Cedric Madianga 1483d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr = cfg->stream_config & STM32_DMA_SCR_CFG_MASK; 1484d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_REQ(cfg->request_line); 1485d8b46839SM'boumba Cedric Madianga 1486d8b46839SM'boumba Cedric Madianga /* Enable Interrupts */ 1487d8b46839SM'boumba Cedric Madianga chan->chan_reg.dma_scr |= STM32_DMA_SCR_TEIE | STM32_DMA_SCR_TCIE; 1488d8b46839SM'boumba Cedric Madianga 1489951f44cbSPierre Yves MORDRET chan->threshold = STM32_DMA_THRESHOLD_FTR_GET(cfg->features); 1490955b1766SAmelie Delaunay if (STM32_DMA_DIRECT_MODE_GET(cfg->features)) 1491955b1766SAmelie Delaunay chan->threshold = STM32_DMA_FIFO_THRESHOLD_NONE; 14922b5b7405SAmelie Delaunay if (STM32_DMA_ALT_ACK_MODE_GET(cfg->features)) 14932b5b7405SAmelie Delaunay chan->chan_reg.dma_scr |= STM32_DMA_SCR_TRBUFF; 1494d8b46839SM'boumba Cedric Madianga } 1495d8b46839SM'boumba Cedric Madianga 1496d8b46839SM'boumba Cedric Madianga static struct dma_chan *stm32_dma_of_xlate(struct of_phandle_args *dma_spec, 1497d8b46839SM'boumba Cedric Madianga struct of_dma *ofdma) 1498d8b46839SM'boumba Cedric Madianga { 1499d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev = ofdma->of_dma_data; 15005df4eb45SM'boumba Cedric Madianga struct device *dev = dmadev->ddev.dev; 1501d8b46839SM'boumba Cedric Madianga struct stm32_dma_cfg cfg; 1502d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan; 1503d8b46839SM'boumba Cedric Madianga struct dma_chan *c; 1504d8b46839SM'boumba Cedric Madianga 15055df4eb45SM'boumba Cedric Madianga if (dma_spec->args_count < 4) { 15065df4eb45SM'boumba Cedric Madianga dev_err(dev, "Bad number of cells\n"); 1507d8b46839SM'boumba Cedric Madianga return NULL; 15085df4eb45SM'boumba Cedric Madianga } 1509d8b46839SM'boumba Cedric Madianga 1510d8b46839SM'boumba Cedric Madianga cfg.channel_id = dma_spec->args[0]; 1511d8b46839SM'boumba Cedric Madianga cfg.request_line = dma_spec->args[1]; 1512d8b46839SM'boumba Cedric Madianga cfg.stream_config = dma_spec->args[2]; 1513951f44cbSPierre Yves MORDRET cfg.features = dma_spec->args[3]; 1514d8b46839SM'boumba Cedric Madianga 1515249d5531SPierre Yves MORDRET if (cfg.channel_id >= STM32_DMA_MAX_CHANNELS || 1516249d5531SPierre Yves MORDRET cfg.request_line >= STM32_DMA_MAX_REQUEST_ID) { 15175df4eb45SM'boumba Cedric Madianga dev_err(dev, "Bad channel and/or request id\n"); 1518d8b46839SM'boumba Cedric Madianga return NULL; 15195df4eb45SM'boumba Cedric Madianga } 1520d8b46839SM'boumba Cedric Madianga 1521d8b46839SM'boumba Cedric Madianga chan = &dmadev->chan[cfg.channel_id]; 1522d8b46839SM'boumba Cedric Madianga 1523d8b46839SM'boumba Cedric Madianga c = dma_get_slave_channel(&chan->vchan.chan); 15245df4eb45SM'boumba Cedric Madianga if (!c) { 1525041cf7e0SColin Ian King dev_err(dev, "No more channels available\n"); 15265df4eb45SM'boumba Cedric Madianga return NULL; 15275df4eb45SM'boumba Cedric Madianga } 15285df4eb45SM'boumba Cedric Madianga 1529d8b46839SM'boumba Cedric Madianga stm32_dma_set_config(chan, &cfg); 1530d8b46839SM'boumba Cedric Madianga 1531d8b46839SM'boumba Cedric Madianga return c; 1532d8b46839SM'boumba Cedric Madianga } 1533d8b46839SM'boumba Cedric Madianga 1534d8b46839SM'boumba Cedric Madianga static const struct of_device_id stm32_dma_of_match[] = { 1535d8b46839SM'boumba Cedric Madianga { .compatible = "st,stm32-dma", }, 1536d8b46839SM'boumba Cedric Madianga { /* sentinel */ }, 1537d8b46839SM'boumba Cedric Madianga }; 1538d8b46839SM'boumba Cedric Madianga MODULE_DEVICE_TABLE(of, stm32_dma_of_match); 1539d8b46839SM'boumba Cedric Madianga 1540d8b46839SM'boumba Cedric Madianga static int stm32_dma_probe(struct platform_device *pdev) 1541d8b46839SM'boumba Cedric Madianga { 1542d8b46839SM'boumba Cedric Madianga struct stm32_dma_chan *chan; 1543d8b46839SM'boumba Cedric Madianga struct stm32_dma_device *dmadev; 1544d8b46839SM'boumba Cedric Madianga struct dma_device *dd; 1545d8b46839SM'boumba Cedric Madianga const struct of_device_id *match; 1546d8b46839SM'boumba Cedric Madianga struct resource *res; 15478cf1e0fcSEtienne Carriere struct reset_control *rst; 1548d8b46839SM'boumba Cedric Madianga int i, ret; 1549d8b46839SM'boumba Cedric Madianga 1550d8b46839SM'boumba Cedric Madianga match = of_match_device(stm32_dma_of_match, &pdev->dev); 1551d8b46839SM'boumba Cedric Madianga if (!match) { 1552d8b46839SM'boumba Cedric Madianga dev_err(&pdev->dev, "Error: No device match found\n"); 1553d8b46839SM'boumba Cedric Madianga return -ENODEV; 1554d8b46839SM'boumba Cedric Madianga } 1555d8b46839SM'boumba Cedric Madianga 1556d8b46839SM'boumba Cedric Madianga dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL); 1557d8b46839SM'boumba Cedric Madianga if (!dmadev) 1558d8b46839SM'boumba Cedric Madianga return -ENOMEM; 1559d8b46839SM'boumba Cedric Madianga 1560d8b46839SM'boumba Cedric Madianga dd = &dmadev->ddev; 1561d8b46839SM'boumba Cedric Madianga 1562d8b46839SM'boumba Cedric Madianga res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1563d8b46839SM'boumba Cedric Madianga dmadev->base = devm_ioremap_resource(&pdev->dev, res); 1564d8b46839SM'boumba Cedric Madianga if (IS_ERR(dmadev->base)) 1565d8b46839SM'boumba Cedric Madianga return PTR_ERR(dmadev->base); 1566d8b46839SM'boumba Cedric Madianga 1567d8b46839SM'boumba Cedric Madianga dmadev->clk = devm_clk_get(&pdev->dev, NULL); 15681c966e1dSKrzysztof Kozlowski if (IS_ERR(dmadev->clk)) 15691c966e1dSKrzysztof Kozlowski return dev_err_probe(&pdev->dev, PTR_ERR(dmadev->clk), "Can't get clock\n"); 1570d8b46839SM'boumba Cedric Madianga 157148bc73baSPierre-Yves MORDRET ret = clk_prepare_enable(dmadev->clk); 157248bc73baSPierre-Yves MORDRET if (ret < 0) { 157348bc73baSPierre-Yves MORDRET dev_err(&pdev->dev, "clk_prep_enable error: %d\n", ret); 157448bc73baSPierre-Yves MORDRET return ret; 157548bc73baSPierre-Yves MORDRET } 157648bc73baSPierre-Yves MORDRET 1577d8b46839SM'boumba Cedric Madianga dmadev->mem2mem = of_property_read_bool(pdev->dev.of_node, 1578d8b46839SM'boumba Cedric Madianga "st,mem2mem"); 1579d8b46839SM'boumba Cedric Madianga 15808cf1e0fcSEtienne Carriere rst = devm_reset_control_get(&pdev->dev, NULL); 1581615eee2cSEtienne Carriere if (IS_ERR(rst)) { 1582615eee2cSEtienne Carriere ret = PTR_ERR(rst); 1583615eee2cSEtienne Carriere if (ret == -EPROBE_DEFER) 1584615eee2cSEtienne Carriere goto clk_free; 1585615eee2cSEtienne Carriere } else { 15868cf1e0fcSEtienne Carriere reset_control_assert(rst); 1587d8b46839SM'boumba Cedric Madianga udelay(2); 15888cf1e0fcSEtienne Carriere reset_control_deassert(rst); 1589d8b46839SM'boumba Cedric Madianga } 1590d8b46839SM'boumba Cedric Madianga 1591d7a9e426SAmelie Delaunay dma_set_max_seg_size(&pdev->dev, STM32_DMA_ALIGNED_MAX_DATA_ITEMS); 1592d7a9e426SAmelie Delaunay 1593d8b46839SM'boumba Cedric Madianga dma_cap_set(DMA_SLAVE, dd->cap_mask); 1594d8b46839SM'boumba Cedric Madianga dma_cap_set(DMA_PRIVATE, dd->cap_mask); 1595d8b46839SM'boumba Cedric Madianga dma_cap_set(DMA_CYCLIC, dd->cap_mask); 1596d8b46839SM'boumba Cedric Madianga dd->device_alloc_chan_resources = stm32_dma_alloc_chan_resources; 1597d8b46839SM'boumba Cedric Madianga dd->device_free_chan_resources = stm32_dma_free_chan_resources; 1598d8b46839SM'boumba Cedric Madianga dd->device_tx_status = stm32_dma_tx_status; 1599d8b46839SM'boumba Cedric Madianga dd->device_issue_pending = stm32_dma_issue_pending; 1600d8b46839SM'boumba Cedric Madianga dd->device_prep_slave_sg = stm32_dma_prep_slave_sg; 1601d8b46839SM'boumba Cedric Madianga dd->device_prep_dma_cyclic = stm32_dma_prep_dma_cyclic; 1602d8b46839SM'boumba Cedric Madianga dd->device_config = stm32_dma_slave_config; 1603*099a9a94SAmelie Delaunay dd->device_pause = stm32_dma_pause; 1604*099a9a94SAmelie Delaunay dd->device_resume = stm32_dma_resume; 1605d8b46839SM'boumba Cedric Madianga dd->device_terminate_all = stm32_dma_terminate_all; 1606dc808675SM'boumba Cedric Madianga dd->device_synchronize = stm32_dma_synchronize; 1607d8b46839SM'boumba Cedric Madianga dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1608d8b46839SM'boumba Cedric Madianga BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1609d8b46839SM'boumba Cedric Madianga BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 1610d8b46839SM'boumba Cedric Madianga dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1611d8b46839SM'boumba Cedric Madianga BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1612d8b46839SM'boumba Cedric Madianga BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 1613d8b46839SM'boumba Cedric Madianga dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 1614d8b46839SM'boumba Cedric Madianga dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 161532ce1088SAmelie Delaunay dd->copy_align = DMAENGINE_ALIGN_32_BYTES; 1616276b0046SM'boumba Cedric Madianga dd->max_burst = STM32_DMA_MAX_BURST; 1617728f6c78SAmelie Delaunay dd->max_sg_burst = STM32_DMA_ALIGNED_MAX_DATA_ITEMS; 161822a0bb29SPierre-Yves MORDRET dd->descriptor_reuse = true; 1619d8b46839SM'boumba Cedric Madianga dd->dev = &pdev->dev; 1620d8b46839SM'boumba Cedric Madianga INIT_LIST_HEAD(&dd->channels); 1621d8b46839SM'boumba Cedric Madianga 1622d8b46839SM'boumba Cedric Madianga if (dmadev->mem2mem) { 1623d8b46839SM'boumba Cedric Madianga dma_cap_set(DMA_MEMCPY, dd->cap_mask); 1624d8b46839SM'boumba Cedric Madianga dd->device_prep_dma_memcpy = stm32_dma_prep_dma_memcpy; 1625d8b46839SM'boumba Cedric Madianga dd->directions |= BIT(DMA_MEM_TO_MEM); 1626d8b46839SM'boumba Cedric Madianga } 1627d8b46839SM'boumba Cedric Madianga 1628d8b46839SM'boumba Cedric Madianga for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) { 1629d8b46839SM'boumba Cedric Madianga chan = &dmadev->chan[i]; 1630d8b46839SM'boumba Cedric Madianga chan->id = i; 1631d8b46839SM'boumba Cedric Madianga chan->vchan.desc_free = stm32_dma_desc_free; 1632d8b46839SM'boumba Cedric Madianga vchan_init(&chan->vchan, dd); 1633d8b46839SM'boumba Cedric Madianga } 1634d8b46839SM'boumba Cedric Madianga 1635d8b46839SM'boumba Cedric Madianga ret = dma_async_device_register(dd); 1636d8b46839SM'boumba Cedric Madianga if (ret) 163748bc73baSPierre-Yves MORDRET goto clk_free; 1638d8b46839SM'boumba Cedric Madianga 1639d8b46839SM'boumba Cedric Madianga for (i = 0; i < STM32_DMA_MAX_CHANNELS; i++) { 1640d8b46839SM'boumba Cedric Madianga chan = &dmadev->chan[i]; 1641c6504be5SVinod Koul ret = platform_get_irq(pdev, i); 1642e17be6e1SStephen Boyd if (ret < 0) 1643d8b46839SM'boumba Cedric Madianga goto err_unregister; 1644c6504be5SVinod Koul chan->irq = ret; 1645c6504be5SVinod Koul 1646d8b46839SM'boumba Cedric Madianga ret = devm_request_irq(&pdev->dev, chan->irq, 1647d8b46839SM'boumba Cedric Madianga stm32_dma_chan_irq, 0, 1648d8b46839SM'boumba Cedric Madianga dev_name(chan2dev(chan)), chan); 1649d8b46839SM'boumba Cedric Madianga if (ret) { 1650d8b46839SM'boumba Cedric Madianga dev_err(&pdev->dev, 1651d8b46839SM'boumba Cedric Madianga "request_irq failed with err %d channel %d\n", 1652d8b46839SM'boumba Cedric Madianga ret, i); 1653d8b46839SM'boumba Cedric Madianga goto err_unregister; 1654d8b46839SM'boumba Cedric Madianga } 1655d8b46839SM'boumba Cedric Madianga } 1656d8b46839SM'boumba Cedric Madianga 1657d8b46839SM'boumba Cedric Madianga ret = of_dma_controller_register(pdev->dev.of_node, 1658d8b46839SM'boumba Cedric Madianga stm32_dma_of_xlate, dmadev); 1659d8b46839SM'boumba Cedric Madianga if (ret < 0) { 1660d8b46839SM'boumba Cedric Madianga dev_err(&pdev->dev, 1661d8b46839SM'boumba Cedric Madianga "STM32 DMA DMA OF registration failed %d\n", ret); 1662d8b46839SM'boumba Cedric Madianga goto err_unregister; 1663d8b46839SM'boumba Cedric Madianga } 1664d8b46839SM'boumba Cedric Madianga 1665d8b46839SM'boumba Cedric Madianga platform_set_drvdata(pdev, dmadev); 1666d8b46839SM'boumba Cedric Madianga 166748bc73baSPierre-Yves MORDRET pm_runtime_set_active(&pdev->dev); 166848bc73baSPierre-Yves MORDRET pm_runtime_enable(&pdev->dev); 166948bc73baSPierre-Yves MORDRET pm_runtime_get_noresume(&pdev->dev); 167048bc73baSPierre-Yves MORDRET pm_runtime_put(&pdev->dev); 167148bc73baSPierre-Yves MORDRET 1672d8b46839SM'boumba Cedric Madianga dev_info(&pdev->dev, "STM32 DMA driver registered\n"); 1673d8b46839SM'boumba Cedric Madianga 1674d8b46839SM'boumba Cedric Madianga return 0; 1675d8b46839SM'boumba Cedric Madianga 1676d8b46839SM'boumba Cedric Madianga err_unregister: 1677d8b46839SM'boumba Cedric Madianga dma_async_device_unregister(dd); 167848bc73baSPierre-Yves MORDRET clk_free: 167948bc73baSPierre-Yves MORDRET clk_disable_unprepare(dmadev->clk); 1680d8b46839SM'boumba Cedric Madianga 1681d8b46839SM'boumba Cedric Madianga return ret; 1682d8b46839SM'boumba Cedric Madianga } 1683d8b46839SM'boumba Cedric Madianga 168448bc73baSPierre-Yves MORDRET #ifdef CONFIG_PM 168548bc73baSPierre-Yves MORDRET static int stm32_dma_runtime_suspend(struct device *dev) 168648bc73baSPierre-Yves MORDRET { 168748bc73baSPierre-Yves MORDRET struct stm32_dma_device *dmadev = dev_get_drvdata(dev); 168848bc73baSPierre-Yves MORDRET 168948bc73baSPierre-Yves MORDRET clk_disable_unprepare(dmadev->clk); 169048bc73baSPierre-Yves MORDRET 169148bc73baSPierre-Yves MORDRET return 0; 169248bc73baSPierre-Yves MORDRET } 169348bc73baSPierre-Yves MORDRET 169448bc73baSPierre-Yves MORDRET static int stm32_dma_runtime_resume(struct device *dev) 169548bc73baSPierre-Yves MORDRET { 169648bc73baSPierre-Yves MORDRET struct stm32_dma_device *dmadev = dev_get_drvdata(dev); 169748bc73baSPierre-Yves MORDRET int ret; 169848bc73baSPierre-Yves MORDRET 169948bc73baSPierre-Yves MORDRET ret = clk_prepare_enable(dmadev->clk); 170048bc73baSPierre-Yves MORDRET if (ret) { 170148bc73baSPierre-Yves MORDRET dev_err(dev, "failed to prepare_enable clock\n"); 170248bc73baSPierre-Yves MORDRET return ret; 170348bc73baSPierre-Yves MORDRET } 170448bc73baSPierre-Yves MORDRET 170548bc73baSPierre-Yves MORDRET return 0; 170648bc73baSPierre-Yves MORDRET } 170748bc73baSPierre-Yves MORDRET #endif 170848bc73baSPierre-Yves MORDRET 170905f8740aSPierre-Yves MORDRET #ifdef CONFIG_PM_SLEEP 1710baa14243SAmelie Delaunay static int stm32_dma_pm_suspend(struct device *dev) 171105f8740aSPierre-Yves MORDRET { 171205f8740aSPierre-Yves MORDRET struct stm32_dma_device *dmadev = dev_get_drvdata(dev); 171305f8740aSPierre-Yves MORDRET int id, ret, scr; 171405f8740aSPierre-Yves MORDRET 1715d54db74aSZhang Qilong ret = pm_runtime_resume_and_get(dev); 171605f8740aSPierre-Yves MORDRET if (ret < 0) 171705f8740aSPierre-Yves MORDRET return ret; 171805f8740aSPierre-Yves MORDRET 171905f8740aSPierre-Yves MORDRET for (id = 0; id < STM32_DMA_MAX_CHANNELS; id++) { 172005f8740aSPierre-Yves MORDRET scr = stm32_dma_read(dmadev, STM32_DMA_SCR(id)); 172105f8740aSPierre-Yves MORDRET if (scr & STM32_DMA_SCR_EN) { 172205f8740aSPierre-Yves MORDRET dev_warn(dev, "Suspend is prevented by Chan %i\n", id); 172305f8740aSPierre-Yves MORDRET return -EBUSY; 172405f8740aSPierre-Yves MORDRET } 172505f8740aSPierre-Yves MORDRET } 172605f8740aSPierre-Yves MORDRET 172705f8740aSPierre-Yves MORDRET pm_runtime_put_sync(dev); 172805f8740aSPierre-Yves MORDRET 172905f8740aSPierre-Yves MORDRET pm_runtime_force_suspend(dev); 173005f8740aSPierre-Yves MORDRET 173105f8740aSPierre-Yves MORDRET return 0; 173205f8740aSPierre-Yves MORDRET } 173305f8740aSPierre-Yves MORDRET 1734baa14243SAmelie Delaunay static int stm32_dma_pm_resume(struct device *dev) 173505f8740aSPierre-Yves MORDRET { 173605f8740aSPierre-Yves MORDRET return pm_runtime_force_resume(dev); 173705f8740aSPierre-Yves MORDRET } 173805f8740aSPierre-Yves MORDRET #endif 173905f8740aSPierre-Yves MORDRET 174048bc73baSPierre-Yves MORDRET static const struct dev_pm_ops stm32_dma_pm_ops = { 1741baa14243SAmelie Delaunay SET_SYSTEM_SLEEP_PM_OPS(stm32_dma_pm_suspend, stm32_dma_pm_resume) 174248bc73baSPierre-Yves MORDRET SET_RUNTIME_PM_OPS(stm32_dma_runtime_suspend, 174348bc73baSPierre-Yves MORDRET stm32_dma_runtime_resume, NULL) 174448bc73baSPierre-Yves MORDRET }; 174548bc73baSPierre-Yves MORDRET 1746d8b46839SM'boumba Cedric Madianga static struct platform_driver stm32_dma_driver = { 1747d8b46839SM'boumba Cedric Madianga .driver = { 1748d8b46839SM'boumba Cedric Madianga .name = "stm32-dma", 1749d8b46839SM'boumba Cedric Madianga .of_match_table = stm32_dma_of_match, 175048bc73baSPierre-Yves MORDRET .pm = &stm32_dma_pm_ops, 1751d8b46839SM'boumba Cedric Madianga }, 1752615eee2cSEtienne Carriere .probe = stm32_dma_probe, 1753d8b46839SM'boumba Cedric Madianga }; 1754d8b46839SM'boumba Cedric Madianga 1755d8b46839SM'boumba Cedric Madianga static int __init stm32_dma_init(void) 1756d8b46839SM'boumba Cedric Madianga { 1757615eee2cSEtienne Carriere return platform_driver_register(&stm32_dma_driver); 1758d8b46839SM'boumba Cedric Madianga } 1759d8b46839SM'boumba Cedric Madianga subsys_initcall(stm32_dma_init); 1760