197fb5e8dSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 27f8f209fSSinan Kaya /* 37f8f209fSSinan Kaya * Qualcomm Technologies HIDMA DMA engine Management interface 47f8f209fSSinan Kaya * 513058e33SSinan Kaya * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. 67f8f209fSSinan Kaya */ 77f8f209fSSinan Kaya 87f8f209fSSinan Kaya #include <linux/dmaengine.h> 97f8f209fSSinan Kaya #include <linux/acpi.h> 107f8f209fSSinan Kaya #include <linux/of.h> 117f8f209fSSinan Kaya #include <linux/property.h> 1237fa4905SRob Herring #include <linux/of_address.h> 1342d236f8SSinan Kaya #include <linux/of_irq.h> 1442d236f8SSinan Kaya #include <linux/of_platform.h> 157f8f209fSSinan Kaya #include <linux/module.h> 167f8f209fSSinan Kaya #include <linux/uaccess.h> 177f8f209fSSinan Kaya #include <linux/slab.h> 187f8f209fSSinan Kaya #include <linux/pm_runtime.h> 197f8f209fSSinan Kaya #include <linux/bitops.h> 2042d236f8SSinan Kaya #include <linux/dma-mapping.h> 217f8f209fSSinan Kaya 227f8f209fSSinan Kaya #include "hidma_mgmt.h" 237f8f209fSSinan Kaya 248e734175SSinan Kaya #define HIDMA_QOS_N_OFFSET 0x700 257f8f209fSSinan Kaya #define HIDMA_CFG_OFFSET 0x400 267f8f209fSSinan Kaya #define HIDMA_MAX_BUS_REQ_LEN_OFFSET 0x41C 277f8f209fSSinan Kaya #define HIDMA_MAX_XACTIONS_OFFSET 0x420 287f8f209fSSinan Kaya #define HIDMA_HW_VERSION_OFFSET 0x424 297f8f209fSSinan Kaya #define HIDMA_CHRESET_TIMEOUT_OFFSET 0x418 307f8f209fSSinan Kaya 317f8f209fSSinan Kaya #define HIDMA_MAX_WR_XACTIONS_MASK GENMASK(4, 0) 327f8f209fSSinan Kaya #define HIDMA_MAX_RD_XACTIONS_MASK GENMASK(4, 0) 337f8f209fSSinan Kaya #define HIDMA_WEIGHT_MASK GENMASK(6, 0) 347f8f209fSSinan Kaya #define HIDMA_MAX_BUS_REQ_LEN_MASK GENMASK(15, 0) 357f8f209fSSinan Kaya #define HIDMA_CHRESET_TIMEOUT_MASK GENMASK(19, 0) 367f8f209fSSinan Kaya 377f8f209fSSinan Kaya #define HIDMA_MAX_WR_XACTIONS_BIT_POS 16 387f8f209fSSinan Kaya #define HIDMA_MAX_BUS_WR_REQ_BIT_POS 16 397f8f209fSSinan Kaya #define HIDMA_WRR_BIT_POS 8 407f8f209fSSinan Kaya #define HIDMA_PRIORITY_BIT_POS 15 417f8f209fSSinan Kaya 427f8f209fSSinan Kaya #define HIDMA_AUTOSUSPEND_TIMEOUT 2000 437f8f209fSSinan Kaya #define HIDMA_MAX_CHANNEL_WEIGHT 15 447f8f209fSSinan Kaya 4513058e33SSinan Kaya static unsigned int max_write_request; 4613058e33SSinan Kaya module_param(max_write_request, uint, 0644); 4713058e33SSinan Kaya MODULE_PARM_DESC(max_write_request, 4813058e33SSinan Kaya "maximum write burst (default: ACPI/DT value)"); 4913058e33SSinan Kaya 5013058e33SSinan Kaya static unsigned int max_read_request; 5113058e33SSinan Kaya module_param(max_read_request, uint, 0644); 5213058e33SSinan Kaya MODULE_PARM_DESC(max_read_request, 5313058e33SSinan Kaya "maximum read burst (default: ACPI/DT value)"); 5413058e33SSinan Kaya 5513058e33SSinan Kaya static unsigned int max_wr_xactions; 5613058e33SSinan Kaya module_param(max_wr_xactions, uint, 0644); 5713058e33SSinan Kaya MODULE_PARM_DESC(max_wr_xactions, 5813058e33SSinan Kaya "maximum number of write transactions (default: ACPI/DT value)"); 5913058e33SSinan Kaya 6013058e33SSinan Kaya static unsigned int max_rd_xactions; 6113058e33SSinan Kaya module_param(max_rd_xactions, uint, 0644); 6213058e33SSinan Kaya MODULE_PARM_DESC(max_rd_xactions, 6313058e33SSinan Kaya "maximum number of read transactions (default: ACPI/DT value)"); 6413058e33SSinan Kaya 657f8f209fSSinan Kaya int hidma_mgmt_setup(struct hidma_mgmt_dev *mgmtdev) 667f8f209fSSinan Kaya { 677f8f209fSSinan Kaya unsigned int i; 687f8f209fSSinan Kaya u32 val; 697f8f209fSSinan Kaya 707f8f209fSSinan Kaya if (!is_power_of_2(mgmtdev->max_write_request) || 717f8f209fSSinan Kaya (mgmtdev->max_write_request < 128) || 727f8f209fSSinan Kaya (mgmtdev->max_write_request > 1024)) { 737f8f209fSSinan Kaya dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n", 747f8f209fSSinan Kaya mgmtdev->max_write_request); 757f8f209fSSinan Kaya return -EINVAL; 767f8f209fSSinan Kaya } 777f8f209fSSinan Kaya 787f8f209fSSinan Kaya if (!is_power_of_2(mgmtdev->max_read_request) || 797f8f209fSSinan Kaya (mgmtdev->max_read_request < 128) || 807f8f209fSSinan Kaya (mgmtdev->max_read_request > 1024)) { 817f8f209fSSinan Kaya dev_err(&mgmtdev->pdev->dev, "invalid read request %d\n", 827f8f209fSSinan Kaya mgmtdev->max_read_request); 837f8f209fSSinan Kaya return -EINVAL; 847f8f209fSSinan Kaya } 857f8f209fSSinan Kaya 867f8f209fSSinan Kaya if (mgmtdev->max_wr_xactions > HIDMA_MAX_WR_XACTIONS_MASK) { 877f8f209fSSinan Kaya dev_err(&mgmtdev->pdev->dev, 887f8f209fSSinan Kaya "max_wr_xactions cannot be bigger than %ld\n", 897f8f209fSSinan Kaya HIDMA_MAX_WR_XACTIONS_MASK); 907f8f209fSSinan Kaya return -EINVAL; 917f8f209fSSinan Kaya } 927f8f209fSSinan Kaya 937f8f209fSSinan Kaya if (mgmtdev->max_rd_xactions > HIDMA_MAX_RD_XACTIONS_MASK) { 947f8f209fSSinan Kaya dev_err(&mgmtdev->pdev->dev, 957f8f209fSSinan Kaya "max_rd_xactions cannot be bigger than %ld\n", 967f8f209fSSinan Kaya HIDMA_MAX_RD_XACTIONS_MASK); 977f8f209fSSinan Kaya return -EINVAL; 987f8f209fSSinan Kaya } 997f8f209fSSinan Kaya 1007f8f209fSSinan Kaya for (i = 0; i < mgmtdev->dma_channels; i++) { 1017f8f209fSSinan Kaya if (mgmtdev->priority[i] > 1) { 1027f8f209fSSinan Kaya dev_err(&mgmtdev->pdev->dev, 1037f8f209fSSinan Kaya "priority can be 0 or 1\n"); 1047f8f209fSSinan Kaya return -EINVAL; 1057f8f209fSSinan Kaya } 1067f8f209fSSinan Kaya 1077f8f209fSSinan Kaya if (mgmtdev->weight[i] > HIDMA_MAX_CHANNEL_WEIGHT) { 1087f8f209fSSinan Kaya dev_err(&mgmtdev->pdev->dev, 1097f8f209fSSinan Kaya "max value of weight can be %d.\n", 1107f8f209fSSinan Kaya HIDMA_MAX_CHANNEL_WEIGHT); 1117f8f209fSSinan Kaya return -EINVAL; 1127f8f209fSSinan Kaya } 1137f8f209fSSinan Kaya 1147f8f209fSSinan Kaya /* weight needs to be at least one */ 1157f8f209fSSinan Kaya if (mgmtdev->weight[i] == 0) 1167f8f209fSSinan Kaya mgmtdev->weight[i] = 1; 1177f8f209fSSinan Kaya } 1187f8f209fSSinan Kaya 1197f8f209fSSinan Kaya pm_runtime_get_sync(&mgmtdev->pdev->dev); 1207f8f209fSSinan Kaya val = readl(mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET); 1217f8f209fSSinan Kaya val &= ~(HIDMA_MAX_BUS_REQ_LEN_MASK << HIDMA_MAX_BUS_WR_REQ_BIT_POS); 1227f8f209fSSinan Kaya val |= mgmtdev->max_write_request << HIDMA_MAX_BUS_WR_REQ_BIT_POS; 1237f8f209fSSinan Kaya val &= ~HIDMA_MAX_BUS_REQ_LEN_MASK; 1247f8f209fSSinan Kaya val |= mgmtdev->max_read_request; 1257f8f209fSSinan Kaya writel(val, mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET); 1267f8f209fSSinan Kaya 1277f8f209fSSinan Kaya val = readl(mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET); 1287f8f209fSSinan Kaya val &= ~(HIDMA_MAX_WR_XACTIONS_MASK << HIDMA_MAX_WR_XACTIONS_BIT_POS); 1297f8f209fSSinan Kaya val |= mgmtdev->max_wr_xactions << HIDMA_MAX_WR_XACTIONS_BIT_POS; 1307f8f209fSSinan Kaya val &= ~HIDMA_MAX_RD_XACTIONS_MASK; 1317f8f209fSSinan Kaya val |= mgmtdev->max_rd_xactions; 1327f8f209fSSinan Kaya writel(val, mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET); 1337f8f209fSSinan Kaya 1347f8f209fSSinan Kaya mgmtdev->hw_version = 1357f8f209fSSinan Kaya readl(mgmtdev->virtaddr + HIDMA_HW_VERSION_OFFSET); 1367f8f209fSSinan Kaya mgmtdev->hw_version_major = (mgmtdev->hw_version >> 28) & 0xF; 1377f8f209fSSinan Kaya mgmtdev->hw_version_minor = (mgmtdev->hw_version >> 16) & 0xF; 1387f8f209fSSinan Kaya 1397f8f209fSSinan Kaya for (i = 0; i < mgmtdev->dma_channels; i++) { 1407f8f209fSSinan Kaya u32 weight = mgmtdev->weight[i]; 1417f8f209fSSinan Kaya u32 priority = mgmtdev->priority[i]; 1427f8f209fSSinan Kaya 1437f8f209fSSinan Kaya val = readl(mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i)); 1447f8f209fSSinan Kaya val &= ~(1 << HIDMA_PRIORITY_BIT_POS); 1457f8f209fSSinan Kaya val |= (priority & 0x1) << HIDMA_PRIORITY_BIT_POS; 1467f8f209fSSinan Kaya val &= ~(HIDMA_WEIGHT_MASK << HIDMA_WRR_BIT_POS); 1477f8f209fSSinan Kaya val |= (weight & HIDMA_WEIGHT_MASK) << HIDMA_WRR_BIT_POS; 1487f8f209fSSinan Kaya writel(val, mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i)); 1497f8f209fSSinan Kaya } 1507f8f209fSSinan Kaya 1517f8f209fSSinan Kaya val = readl(mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET); 1527f8f209fSSinan Kaya val &= ~HIDMA_CHRESET_TIMEOUT_MASK; 1537f8f209fSSinan Kaya val |= mgmtdev->chreset_timeout_cycles & HIDMA_CHRESET_TIMEOUT_MASK; 1547f8f209fSSinan Kaya writel(val, mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET); 1557f8f209fSSinan Kaya 1567f8f209fSSinan Kaya pm_runtime_mark_last_busy(&mgmtdev->pdev->dev); 1577f8f209fSSinan Kaya pm_runtime_put_autosuspend(&mgmtdev->pdev->dev); 1587f8f209fSSinan Kaya return 0; 1597f8f209fSSinan Kaya } 1607f8f209fSSinan Kaya EXPORT_SYMBOL_GPL(hidma_mgmt_setup); 1617f8f209fSSinan Kaya 1627f8f209fSSinan Kaya static int hidma_mgmt_probe(struct platform_device *pdev) 1637f8f209fSSinan Kaya { 1647f8f209fSSinan Kaya struct hidma_mgmt_dev *mgmtdev; 1657f8f209fSSinan Kaya struct resource *res; 1667f8f209fSSinan Kaya void __iomem *virtaddr; 1677f8f209fSSinan Kaya int irq; 1687f8f209fSSinan Kaya int rc; 1697f8f209fSSinan Kaya u32 val; 1707f8f209fSSinan Kaya 1717f8f209fSSinan Kaya pm_runtime_set_autosuspend_delay(&pdev->dev, HIDMA_AUTOSUSPEND_TIMEOUT); 1727f8f209fSSinan Kaya pm_runtime_use_autosuspend(&pdev->dev); 1737f8f209fSSinan Kaya pm_runtime_set_active(&pdev->dev); 1747f8f209fSSinan Kaya pm_runtime_enable(&pdev->dev); 1757f8f209fSSinan Kaya pm_runtime_get_sync(&pdev->dev); 1767f8f209fSSinan Kaya 1777f8f209fSSinan Kaya res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1787f8f209fSSinan Kaya virtaddr = devm_ioremap_resource(&pdev->dev, res); 1797f8f209fSSinan Kaya if (IS_ERR(virtaddr)) { 1807f8f209fSSinan Kaya rc = -ENOMEM; 1817f8f209fSSinan Kaya goto out; 1827f8f209fSSinan Kaya } 1837f8f209fSSinan Kaya 1847f8f209fSSinan Kaya irq = platform_get_irq(pdev, 0); 1857f8f209fSSinan Kaya if (irq < 0) { 1867f8f209fSSinan Kaya rc = irq; 1877f8f209fSSinan Kaya goto out; 1887f8f209fSSinan Kaya } 1897f8f209fSSinan Kaya 1907f8f209fSSinan Kaya mgmtdev = devm_kzalloc(&pdev->dev, sizeof(*mgmtdev), GFP_KERNEL); 1917f8f209fSSinan Kaya if (!mgmtdev) { 1927f8f209fSSinan Kaya rc = -ENOMEM; 1937f8f209fSSinan Kaya goto out; 1947f8f209fSSinan Kaya } 1957f8f209fSSinan Kaya 1967f8f209fSSinan Kaya mgmtdev->pdev = pdev; 1977f8f209fSSinan Kaya mgmtdev->addrsize = resource_size(res); 1987f8f209fSSinan Kaya mgmtdev->virtaddr = virtaddr; 1997f8f209fSSinan Kaya 2007f8f209fSSinan Kaya rc = device_property_read_u32(&pdev->dev, "dma-channels", 2017f8f209fSSinan Kaya &mgmtdev->dma_channels); 2027f8f209fSSinan Kaya if (rc) { 2037f8f209fSSinan Kaya dev_err(&pdev->dev, "number of channels missing\n"); 2047f8f209fSSinan Kaya goto out; 2057f8f209fSSinan Kaya } 2067f8f209fSSinan Kaya 2077f8f209fSSinan Kaya rc = device_property_read_u32(&pdev->dev, 2087f8f209fSSinan Kaya "channel-reset-timeout-cycles", 2097f8f209fSSinan Kaya &mgmtdev->chreset_timeout_cycles); 2107f8f209fSSinan Kaya if (rc) { 2117f8f209fSSinan Kaya dev_err(&pdev->dev, "channel reset timeout missing\n"); 2127f8f209fSSinan Kaya goto out; 2137f8f209fSSinan Kaya } 2147f8f209fSSinan Kaya 2157f8f209fSSinan Kaya rc = device_property_read_u32(&pdev->dev, "max-write-burst-bytes", 2167f8f209fSSinan Kaya &mgmtdev->max_write_request); 2177f8f209fSSinan Kaya if (rc) { 2187f8f209fSSinan Kaya dev_err(&pdev->dev, "max-write-burst-bytes missing\n"); 2197f8f209fSSinan Kaya goto out; 2207f8f209fSSinan Kaya } 2217f8f209fSSinan Kaya 2220217cccdSSinan Kaya if (max_write_request && 2230217cccdSSinan Kaya (max_write_request != mgmtdev->max_write_request)) { 22413058e33SSinan Kaya dev_info(&pdev->dev, "overriding max-write-burst-bytes: %d\n", 22513058e33SSinan Kaya max_write_request); 22613058e33SSinan Kaya mgmtdev->max_write_request = max_write_request; 22713058e33SSinan Kaya } else 22813058e33SSinan Kaya max_write_request = mgmtdev->max_write_request; 22913058e33SSinan Kaya 2307f8f209fSSinan Kaya rc = device_property_read_u32(&pdev->dev, "max-read-burst-bytes", 2317f8f209fSSinan Kaya &mgmtdev->max_read_request); 2327f8f209fSSinan Kaya if (rc) { 2337f8f209fSSinan Kaya dev_err(&pdev->dev, "max-read-burst-bytes missing\n"); 2347f8f209fSSinan Kaya goto out; 2357f8f209fSSinan Kaya } 2360217cccdSSinan Kaya if (max_read_request && 2370217cccdSSinan Kaya (max_read_request != mgmtdev->max_read_request)) { 23813058e33SSinan Kaya dev_info(&pdev->dev, "overriding max-read-burst-bytes: %d\n", 23913058e33SSinan Kaya max_read_request); 24013058e33SSinan Kaya mgmtdev->max_read_request = max_read_request; 24113058e33SSinan Kaya } else 24213058e33SSinan Kaya max_read_request = mgmtdev->max_read_request; 2437f8f209fSSinan Kaya 2447f8f209fSSinan Kaya rc = device_property_read_u32(&pdev->dev, "max-write-transactions", 2457f8f209fSSinan Kaya &mgmtdev->max_wr_xactions); 2467f8f209fSSinan Kaya if (rc) { 2477f8f209fSSinan Kaya dev_err(&pdev->dev, "max-write-transactions missing\n"); 2487f8f209fSSinan Kaya goto out; 2497f8f209fSSinan Kaya } 2500217cccdSSinan Kaya if (max_wr_xactions && 2510217cccdSSinan Kaya (max_wr_xactions != mgmtdev->max_wr_xactions)) { 25213058e33SSinan Kaya dev_info(&pdev->dev, "overriding max-write-transactions: %d\n", 25313058e33SSinan Kaya max_wr_xactions); 25413058e33SSinan Kaya mgmtdev->max_wr_xactions = max_wr_xactions; 25513058e33SSinan Kaya } else 25613058e33SSinan Kaya max_wr_xactions = mgmtdev->max_wr_xactions; 2577f8f209fSSinan Kaya 2587f8f209fSSinan Kaya rc = device_property_read_u32(&pdev->dev, "max-read-transactions", 2597f8f209fSSinan Kaya &mgmtdev->max_rd_xactions); 2607f8f209fSSinan Kaya if (rc) { 2617f8f209fSSinan Kaya dev_err(&pdev->dev, "max-read-transactions missing\n"); 2627f8f209fSSinan Kaya goto out; 2637f8f209fSSinan Kaya } 2640217cccdSSinan Kaya if (max_rd_xactions && 2650217cccdSSinan Kaya (max_rd_xactions != mgmtdev->max_rd_xactions)) { 26613058e33SSinan Kaya dev_info(&pdev->dev, "overriding max-read-transactions: %d\n", 26713058e33SSinan Kaya max_rd_xactions); 26813058e33SSinan Kaya mgmtdev->max_rd_xactions = max_rd_xactions; 26913058e33SSinan Kaya } else 27013058e33SSinan Kaya max_rd_xactions = mgmtdev->max_rd_xactions; 2717f8f209fSSinan Kaya 2727f8f209fSSinan Kaya mgmtdev->priority = devm_kcalloc(&pdev->dev, 2737f8f209fSSinan Kaya mgmtdev->dma_channels, 2747f8f209fSSinan Kaya sizeof(*mgmtdev->priority), 2757f8f209fSSinan Kaya GFP_KERNEL); 2767f8f209fSSinan Kaya if (!mgmtdev->priority) { 2777f8f209fSSinan Kaya rc = -ENOMEM; 2787f8f209fSSinan Kaya goto out; 2797f8f209fSSinan Kaya } 2807f8f209fSSinan Kaya 2817f8f209fSSinan Kaya mgmtdev->weight = devm_kcalloc(&pdev->dev, 2827f8f209fSSinan Kaya mgmtdev->dma_channels, 2837f8f209fSSinan Kaya sizeof(*mgmtdev->weight), GFP_KERNEL); 2847f8f209fSSinan Kaya if (!mgmtdev->weight) { 2857f8f209fSSinan Kaya rc = -ENOMEM; 2867f8f209fSSinan Kaya goto out; 2877f8f209fSSinan Kaya } 2887f8f209fSSinan Kaya 2897f8f209fSSinan Kaya rc = hidma_mgmt_setup(mgmtdev); 2907f8f209fSSinan Kaya if (rc) { 2917f8f209fSSinan Kaya dev_err(&pdev->dev, "setup failed\n"); 2927f8f209fSSinan Kaya goto out; 2937f8f209fSSinan Kaya } 2947f8f209fSSinan Kaya 2957f8f209fSSinan Kaya /* start the HW */ 2967f8f209fSSinan Kaya val = readl(mgmtdev->virtaddr + HIDMA_CFG_OFFSET); 2977f8f209fSSinan Kaya val |= 1; 2987f8f209fSSinan Kaya writel(val, mgmtdev->virtaddr + HIDMA_CFG_OFFSET); 2997f8f209fSSinan Kaya 3007f8f209fSSinan Kaya rc = hidma_mgmt_init_sys(mgmtdev); 3017f8f209fSSinan Kaya if (rc) { 3027f8f209fSSinan Kaya dev_err(&pdev->dev, "sysfs setup failed\n"); 3037f8f209fSSinan Kaya goto out; 3047f8f209fSSinan Kaya } 3057f8f209fSSinan Kaya 3067f8f209fSSinan Kaya dev_info(&pdev->dev, 3077f8f209fSSinan Kaya "HW rev: %d.%d @ %pa with %d physical channels\n", 3087f8f209fSSinan Kaya mgmtdev->hw_version_major, mgmtdev->hw_version_minor, 3097f8f209fSSinan Kaya &res->start, mgmtdev->dma_channels); 3107f8f209fSSinan Kaya 3117f8f209fSSinan Kaya platform_set_drvdata(pdev, mgmtdev); 3127f8f209fSSinan Kaya pm_runtime_mark_last_busy(&pdev->dev); 3137f8f209fSSinan Kaya pm_runtime_put_autosuspend(&pdev->dev); 3147f8f209fSSinan Kaya return 0; 3157f8f209fSSinan Kaya out: 3167f8f209fSSinan Kaya pm_runtime_put_sync_suspend(&pdev->dev); 3177f8f209fSSinan Kaya pm_runtime_disable(&pdev->dev); 3187f8f209fSSinan Kaya return rc; 3197f8f209fSSinan Kaya } 3207f8f209fSSinan Kaya 3217f8f209fSSinan Kaya #if IS_ENABLED(CONFIG_ACPI) 3227f8f209fSSinan Kaya static const struct acpi_device_id hidma_mgmt_acpi_ids[] = { 3237f8f209fSSinan Kaya {"QCOM8060"}, 3247f8f209fSSinan Kaya {}, 3257f8f209fSSinan Kaya }; 32675ff7668SSinan Kaya MODULE_DEVICE_TABLE(acpi, hidma_mgmt_acpi_ids); 3277f8f209fSSinan Kaya #endif 3287f8f209fSSinan Kaya 3297f8f209fSSinan Kaya static const struct of_device_id hidma_mgmt_match[] = { 3307f8f209fSSinan Kaya {.compatible = "qcom,hidma-mgmt-1.0",}, 3317f8f209fSSinan Kaya {}, 3327f8f209fSSinan Kaya }; 3337f8f209fSSinan Kaya MODULE_DEVICE_TABLE(of, hidma_mgmt_match); 3347f8f209fSSinan Kaya 3357f8f209fSSinan Kaya static struct platform_driver hidma_mgmt_driver = { 3367f8f209fSSinan Kaya .probe = hidma_mgmt_probe, 3377f8f209fSSinan Kaya .driver = { 3387f8f209fSSinan Kaya .name = "hidma-mgmt", 3397f8f209fSSinan Kaya .of_match_table = hidma_mgmt_match, 3407f8f209fSSinan Kaya .acpi_match_table = ACPI_PTR(hidma_mgmt_acpi_ids), 3417f8f209fSSinan Kaya }, 3427f8f209fSSinan Kaya }; 3437f8f209fSSinan Kaya 34442d236f8SSinan Kaya #if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ) 34542d236f8SSinan Kaya static int object_counter; 34642d236f8SSinan Kaya 34742d236f8SSinan Kaya static int __init hidma_mgmt_of_populate_channels(struct device_node *np) 34842d236f8SSinan Kaya { 34942d236f8SSinan Kaya struct platform_device *pdev_parent = of_find_device_by_node(np); 35042d236f8SSinan Kaya struct platform_device_info pdevinfo; 35142d236f8SSinan Kaya struct device_node *child; 35237fa4905SRob Herring struct resource *res; 35337fa4905SRob Herring int ret = 0; 35442d236f8SSinan Kaya 35542d236f8SSinan Kaya /* allocate a resource array */ 35637fa4905SRob Herring res = kcalloc(3, sizeof(*res), GFP_KERNEL); 35737fa4905SRob Herring if (!res) 35837fa4905SRob Herring return -ENOMEM; 35942d236f8SSinan Kaya 36037fa4905SRob Herring for_each_available_child_of_node(np, child) { 36137fa4905SRob Herring struct platform_device *new_pdev; 36242d236f8SSinan Kaya 36337fa4905SRob Herring ret = of_address_to_resource(child, 0, &res[0]); 36437fa4905SRob Herring if (!ret) 36542d236f8SSinan Kaya goto out; 36642d236f8SSinan Kaya 36737fa4905SRob Herring ret = of_address_to_resource(child, 1, &res[1]); 36837fa4905SRob Herring if (!ret) 36937fa4905SRob Herring goto out; 37037fa4905SRob Herring 37137fa4905SRob Herring ret = of_irq_to_resource(child, 0, &res[2]); 37237fa4905SRob Herring if (ret <= 0) 37337fa4905SRob Herring goto out; 37442d236f8SSinan Kaya 37542d236f8SSinan Kaya memset(&pdevinfo, 0, sizeof(pdevinfo)); 37642d236f8SSinan Kaya pdevinfo.fwnode = &child->fwnode; 37742d236f8SSinan Kaya pdevinfo.parent = pdev_parent ? &pdev_parent->dev : NULL; 37842d236f8SSinan Kaya pdevinfo.name = child->name; 37942d236f8SSinan Kaya pdevinfo.id = object_counter++; 38042d236f8SSinan Kaya pdevinfo.res = res; 38137fa4905SRob Herring pdevinfo.num_res = 3; 38242d236f8SSinan Kaya pdevinfo.data = NULL; 38342d236f8SSinan Kaya pdevinfo.size_data = 0; 38442d236f8SSinan Kaya pdevinfo.dma_mask = DMA_BIT_MASK(64); 38542d236f8SSinan Kaya new_pdev = platform_device_register_full(&pdevinfo); 3866a2cf55dSWei Yongjun if (IS_ERR(new_pdev)) { 3876a2cf55dSWei Yongjun ret = PTR_ERR(new_pdev); 38842d236f8SSinan Kaya goto out; 38942d236f8SSinan Kaya } 3909da0be80SSinan Kaya new_pdev->dev.of_node = child; 3913d6ce86eSChristoph Hellwig of_dma_configure(&new_pdev->dev, child, true); 3929da0be80SSinan Kaya /* 3939da0be80SSinan Kaya * It is assumed that calling of_msi_configure is safe on 3949da0be80SSinan Kaya * platforms with or without MSI support. 3959da0be80SSinan Kaya */ 3969da0be80SSinan Kaya of_msi_configure(&new_pdev->dev, child); 39742d236f8SSinan Kaya } 398057b05d5SNishka Dasgupta 399057b05d5SNishka Dasgupta kfree(res); 400057b05d5SNishka Dasgupta 401057b05d5SNishka Dasgupta return ret; 402057b05d5SNishka Dasgupta 40342d236f8SSinan Kaya out: 404057b05d5SNishka Dasgupta of_node_put(child); 40542d236f8SSinan Kaya kfree(res); 40642d236f8SSinan Kaya 40742d236f8SSinan Kaya return ret; 40842d236f8SSinan Kaya } 40942d236f8SSinan Kaya #endif 41042d236f8SSinan Kaya 41142d236f8SSinan Kaya static int __init hidma_mgmt_init(void) 41242d236f8SSinan Kaya { 41342d236f8SSinan Kaya #if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ) 41442d236f8SSinan Kaya struct device_node *child; 41542d236f8SSinan Kaya 416d8cc38ddSWei Yongjun for_each_matching_node(child, hidma_mgmt_match) { 41742d236f8SSinan Kaya /* device tree based firmware here */ 41842d236f8SSinan Kaya hidma_mgmt_of_populate_channels(child); 41942d236f8SSinan Kaya } 42042d236f8SSinan Kaya #endif 421*4df2a8b0SPhillip Potter /* 422*4df2a8b0SPhillip Potter * We do not check for return value here, as it is assumed that 423*4df2a8b0SPhillip Potter * platform_driver_register must not fail. The reason for this is that 424*4df2a8b0SPhillip Potter * the (potential) hidma_mgmt_of_populate_channels calls above are not 425*4df2a8b0SPhillip Potter * cleaned up if it does fail, and to do this work is quite 426*4df2a8b0SPhillip Potter * complicated. In particular, various calls of of_address_to_resource, 427*4df2a8b0SPhillip Potter * of_irq_to_resource, platform_device_register_full, of_dma_configure, 428*4df2a8b0SPhillip Potter * and of_msi_configure which then call other functions and so on, must 429*4df2a8b0SPhillip Potter * be cleaned up - this is not a trivial exercise. 430*4df2a8b0SPhillip Potter * 431*4df2a8b0SPhillip Potter * Currently, this module is not intended to be unloaded, and there is 432*4df2a8b0SPhillip Potter * no module_exit function defined which does the needed cleanup. For 433*4df2a8b0SPhillip Potter * this reason, we have to assume success here. 434*4df2a8b0SPhillip Potter */ 43543ed0fcfSGreg Kroah-Hartman platform_driver_register(&hidma_mgmt_driver); 43642d236f8SSinan Kaya 43743ed0fcfSGreg Kroah-Hartman return 0; 43842d236f8SSinan Kaya } 43942d236f8SSinan Kaya module_init(hidma_mgmt_init); 4407f8f209fSSinan Kaya MODULE_LICENSE("GPL v2"); 441