1 /* 2 * Qualcomm Technologies HIDMA data structures 3 * 4 * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 and 8 * only version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef QCOM_HIDMA_H 17 #define QCOM_HIDMA_H 18 19 #include <linux/kfifo.h> 20 #include <linux/interrupt.h> 21 #include <linux/dmaengine.h> 22 23 #define HIDMA_TRE_SIZE 32 /* each TRE is 32 bytes */ 24 #define HIDMA_TRE_CFG_IDX 0 25 #define HIDMA_TRE_LEN_IDX 1 26 #define HIDMA_TRE_SRC_LOW_IDX 2 27 #define HIDMA_TRE_SRC_HI_IDX 3 28 #define HIDMA_TRE_DEST_LOW_IDX 4 29 #define HIDMA_TRE_DEST_HI_IDX 5 30 31 enum tre_type { 32 HIDMA_TRE_MEMCPY = 3, 33 HIDMA_TRE_MEMSET = 4, 34 }; 35 36 struct hidma_tre { 37 atomic_t allocated; /* if this channel is allocated */ 38 bool queued; /* flag whether this is pending */ 39 u16 status; /* status */ 40 u32 idx; /* index of the tre */ 41 u32 dma_sig; /* signature of the tre */ 42 const char *dev_name; /* name of the device */ 43 void (*callback)(void *data); /* requester callback */ 44 void *data; /* Data associated with this channel*/ 45 struct hidma_lldev *lldev; /* lldma device pointer */ 46 u32 tre_local[HIDMA_TRE_SIZE / sizeof(u32) + 1]; /* TRE local copy */ 47 u32 tre_index; /* the offset where this was written*/ 48 u32 int_flags; /* interrupt flags */ 49 u8 err_info; /* error record in this transfer */ 50 u8 err_code; /* completion code */ 51 }; 52 53 struct hidma_lldev { 54 bool msi_support; /* flag indicating MSI support */ 55 bool initialized; /* initialized flag */ 56 u8 trch_state; /* trch_state of the device */ 57 u8 evch_state; /* evch_state of the device */ 58 u8 chidx; /* channel index in the core */ 59 u32 nr_tres; /* max number of configs */ 60 spinlock_t lock; /* reentrancy */ 61 struct hidma_tre *trepool; /* trepool of user configs */ 62 struct device *dev; /* device */ 63 void __iomem *trca; /* Transfer Channel address */ 64 void __iomem *evca; /* Event Channel address */ 65 struct hidma_tre 66 **pending_tre_list; /* Pointers to pending TREs */ 67 atomic_t pending_tre_count; /* Number of TREs pending */ 68 69 void *tre_ring; /* TRE ring */ 70 dma_addr_t tre_dma; /* TRE ring to be shared with HW */ 71 u32 tre_ring_size; /* Byte size of the ring */ 72 u32 tre_processed_off; /* last processed TRE */ 73 74 void *evre_ring; /* EVRE ring */ 75 dma_addr_t evre_dma; /* EVRE ring to be shared with HW */ 76 u32 evre_ring_size; /* Byte size of the ring */ 77 u32 evre_processed_off; /* last processed EVRE */ 78 79 u32 tre_write_offset; /* TRE write location */ 80 struct tasklet_struct task; /* task delivering notifications */ 81 DECLARE_KFIFO_PTR(handoff_fifo, 82 struct hidma_tre *); /* pending TREs FIFO */ 83 }; 84 85 struct hidma_desc { 86 struct dma_async_tx_descriptor desc; 87 /* link list node for this channel*/ 88 struct list_head node; 89 u32 tre_ch; 90 }; 91 92 struct hidma_chan { 93 bool paused; 94 bool allocated; 95 char dbg_name[16]; 96 u32 dma_sig; 97 dma_cookie_t last_success; 98 99 /* 100 * active descriptor on this channel 101 * It is used by the DMA complete notification to 102 * locate the descriptor that initiated the transfer. 103 */ 104 struct dentry *debugfs; 105 struct dentry *stats; 106 struct hidma_dev *dmadev; 107 struct hidma_desc *running; 108 109 struct dma_chan chan; 110 struct list_head free; 111 struct list_head prepared; 112 struct list_head queued; 113 struct list_head active; 114 struct list_head completed; 115 116 /* Lock for this structure */ 117 spinlock_t lock; 118 }; 119 120 struct hidma_dev { 121 int irq; 122 int chidx; 123 u32 nr_descriptors; 124 int msi_virqbase; 125 126 struct hidma_lldev *lldev; 127 void __iomem *dev_trca; 128 struct resource *trca_resource; 129 void __iomem *dev_evca; 130 struct resource *evca_resource; 131 132 /* used to protect the pending channel list*/ 133 spinlock_t lock; 134 struct dma_device ddev; 135 136 struct dentry *debugfs; 137 struct dentry *stats; 138 139 /* sysfs entry for the channel id */ 140 struct device_attribute *chid_attrs; 141 142 /* Task delivering issue_pending */ 143 struct tasklet_struct task; 144 }; 145 146 int hidma_ll_request(struct hidma_lldev *llhndl, u32 dev_id, 147 const char *dev_name, 148 void (*callback)(void *data), void *data, u32 *tre_ch); 149 150 void hidma_ll_free(struct hidma_lldev *llhndl, u32 tre_ch); 151 enum dma_status hidma_ll_status(struct hidma_lldev *llhndl, u32 tre_ch); 152 bool hidma_ll_isenabled(struct hidma_lldev *llhndl); 153 void hidma_ll_queue_request(struct hidma_lldev *llhndl, u32 tre_ch); 154 void hidma_ll_start(struct hidma_lldev *llhndl); 155 int hidma_ll_disable(struct hidma_lldev *lldev); 156 int hidma_ll_enable(struct hidma_lldev *llhndl); 157 void hidma_ll_set_transfer_params(struct hidma_lldev *llhndl, u32 tre_ch, 158 dma_addr_t src, dma_addr_t dest, u32 len, u32 flags, u32 txntype); 159 void hidma_ll_setup_irq(struct hidma_lldev *lldev, bool msi); 160 int hidma_ll_setup(struct hidma_lldev *lldev); 161 struct hidma_lldev *hidma_ll_init(struct device *dev, u32 max_channels, 162 void __iomem *trca, void __iomem *evca, 163 u8 chidx); 164 int hidma_ll_uninit(struct hidma_lldev *llhndl); 165 irqreturn_t hidma_ll_inthandler(int irq, void *arg); 166 irqreturn_t hidma_ll_inthandler_msi(int irq, void *arg, int cause); 167 void hidma_cleanup_pending_tre(struct hidma_lldev *llhndl, u8 err_info, 168 u8 err_code); 169 int hidma_debug_init(struct hidma_dev *dmadev); 170 void hidma_debug_uninit(struct hidma_dev *dmadev); 171 #endif 172