1 /* 2 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 /* 15 * QCOM BAM DMA engine driver 16 * 17 * QCOM BAM DMA blocks are distributed amongst a number of the on-chip 18 * peripherals on the MSM 8x74. The configuration of the channels are dependent 19 * on the way they are hard wired to that specific peripheral. The peripheral 20 * device tree entries specify the configuration of each channel. 21 * 22 * The DMA controller requires the use of external memory for storage of the 23 * hardware descriptors for each channel. The descriptor FIFO is accessed as a 24 * circular buffer and operations are managed according to the offset within the 25 * FIFO. After pipe/channel reset, all of the pipe registers and internal state 26 * are back to defaults. 27 * 28 * During DMA operations, we write descriptors to the FIFO, being careful to 29 * handle wrapping and then write the last FIFO offset to that channel's 30 * P_EVNT_REG register to kick off the transaction. The P_SW_OFSTS register 31 * indicates the current FIFO offset that is being processed, so there is some 32 * indication of where the hardware is currently working. 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/io.h> 37 #include <linux/init.h> 38 #include <linux/slab.h> 39 #include <linux/module.h> 40 #include <linux/interrupt.h> 41 #include <linux/dma-mapping.h> 42 #include <linux/scatterlist.h> 43 #include <linux/device.h> 44 #include <linux/platform_device.h> 45 #include <linux/of.h> 46 #include <linux/of_address.h> 47 #include <linux/of_irq.h> 48 #include <linux/of_dma.h> 49 #include <linux/clk.h> 50 #include <linux/dmaengine.h> 51 52 #include "../dmaengine.h" 53 #include "../virt-dma.h" 54 55 struct bam_desc_hw { 56 __le32 addr; /* Buffer physical address */ 57 __le16 size; /* Buffer size in bytes */ 58 __le16 flags; 59 }; 60 61 #define DESC_FLAG_INT BIT(15) 62 #define DESC_FLAG_EOT BIT(14) 63 #define DESC_FLAG_EOB BIT(13) 64 #define DESC_FLAG_NWD BIT(12) 65 66 struct bam_async_desc { 67 struct virt_dma_desc vd; 68 69 u32 num_desc; 70 u32 xfer_len; 71 72 /* transaction flags, EOT|EOB|NWD */ 73 u16 flags; 74 75 struct bam_desc_hw *curr_desc; 76 77 enum dma_transfer_direction dir; 78 size_t length; 79 struct bam_desc_hw desc[0]; 80 }; 81 82 enum bam_reg { 83 BAM_CTRL, 84 BAM_REVISION, 85 BAM_NUM_PIPES, 86 BAM_DESC_CNT_TRSHLD, 87 BAM_IRQ_SRCS, 88 BAM_IRQ_SRCS_MSK, 89 BAM_IRQ_SRCS_UNMASKED, 90 BAM_IRQ_STTS, 91 BAM_IRQ_CLR, 92 BAM_IRQ_EN, 93 BAM_CNFG_BITS, 94 BAM_IRQ_SRCS_EE, 95 BAM_IRQ_SRCS_MSK_EE, 96 BAM_P_CTRL, 97 BAM_P_RST, 98 BAM_P_HALT, 99 BAM_P_IRQ_STTS, 100 BAM_P_IRQ_CLR, 101 BAM_P_IRQ_EN, 102 BAM_P_EVNT_DEST_ADDR, 103 BAM_P_EVNT_REG, 104 BAM_P_SW_OFSTS, 105 BAM_P_DATA_FIFO_ADDR, 106 BAM_P_DESC_FIFO_ADDR, 107 BAM_P_EVNT_GEN_TRSHLD, 108 BAM_P_FIFO_SIZES, 109 }; 110 111 struct reg_offset_data { 112 u32 base_offset; 113 unsigned int pipe_mult, evnt_mult, ee_mult; 114 }; 115 116 static const struct reg_offset_data bam_v1_3_reg_info[] = { 117 [BAM_CTRL] = { 0x0F80, 0x00, 0x00, 0x00 }, 118 [BAM_REVISION] = { 0x0F84, 0x00, 0x00, 0x00 }, 119 [BAM_NUM_PIPES] = { 0x0FBC, 0x00, 0x00, 0x00 }, 120 [BAM_DESC_CNT_TRSHLD] = { 0x0F88, 0x00, 0x00, 0x00 }, 121 [BAM_IRQ_SRCS] = { 0x0F8C, 0x00, 0x00, 0x00 }, 122 [BAM_IRQ_SRCS_MSK] = { 0x0F90, 0x00, 0x00, 0x00 }, 123 [BAM_IRQ_SRCS_UNMASKED] = { 0x0FB0, 0x00, 0x00, 0x00 }, 124 [BAM_IRQ_STTS] = { 0x0F94, 0x00, 0x00, 0x00 }, 125 [BAM_IRQ_CLR] = { 0x0F98, 0x00, 0x00, 0x00 }, 126 [BAM_IRQ_EN] = { 0x0F9C, 0x00, 0x00, 0x00 }, 127 [BAM_CNFG_BITS] = { 0x0FFC, 0x00, 0x00, 0x00 }, 128 [BAM_IRQ_SRCS_EE] = { 0x1800, 0x00, 0x00, 0x80 }, 129 [BAM_IRQ_SRCS_MSK_EE] = { 0x1804, 0x00, 0x00, 0x80 }, 130 [BAM_P_CTRL] = { 0x0000, 0x80, 0x00, 0x00 }, 131 [BAM_P_RST] = { 0x0004, 0x80, 0x00, 0x00 }, 132 [BAM_P_HALT] = { 0x0008, 0x80, 0x00, 0x00 }, 133 [BAM_P_IRQ_STTS] = { 0x0010, 0x80, 0x00, 0x00 }, 134 [BAM_P_IRQ_CLR] = { 0x0014, 0x80, 0x00, 0x00 }, 135 [BAM_P_IRQ_EN] = { 0x0018, 0x80, 0x00, 0x00 }, 136 [BAM_P_EVNT_DEST_ADDR] = { 0x102C, 0x00, 0x40, 0x00 }, 137 [BAM_P_EVNT_REG] = { 0x1018, 0x00, 0x40, 0x00 }, 138 [BAM_P_SW_OFSTS] = { 0x1000, 0x00, 0x40, 0x00 }, 139 [BAM_P_DATA_FIFO_ADDR] = { 0x1024, 0x00, 0x40, 0x00 }, 140 [BAM_P_DESC_FIFO_ADDR] = { 0x101C, 0x00, 0x40, 0x00 }, 141 [BAM_P_EVNT_GEN_TRSHLD] = { 0x1028, 0x00, 0x40, 0x00 }, 142 [BAM_P_FIFO_SIZES] = { 0x1020, 0x00, 0x40, 0x00 }, 143 }; 144 145 static const struct reg_offset_data bam_v1_4_reg_info[] = { 146 [BAM_CTRL] = { 0x0000, 0x00, 0x00, 0x00 }, 147 [BAM_REVISION] = { 0x0004, 0x00, 0x00, 0x00 }, 148 [BAM_NUM_PIPES] = { 0x003C, 0x00, 0x00, 0x00 }, 149 [BAM_DESC_CNT_TRSHLD] = { 0x0008, 0x00, 0x00, 0x00 }, 150 [BAM_IRQ_SRCS] = { 0x000C, 0x00, 0x00, 0x00 }, 151 [BAM_IRQ_SRCS_MSK] = { 0x0010, 0x00, 0x00, 0x00 }, 152 [BAM_IRQ_SRCS_UNMASKED] = { 0x0030, 0x00, 0x00, 0x00 }, 153 [BAM_IRQ_STTS] = { 0x0014, 0x00, 0x00, 0x00 }, 154 [BAM_IRQ_CLR] = { 0x0018, 0x00, 0x00, 0x00 }, 155 [BAM_IRQ_EN] = { 0x001C, 0x00, 0x00, 0x00 }, 156 [BAM_CNFG_BITS] = { 0x007C, 0x00, 0x00, 0x00 }, 157 [BAM_IRQ_SRCS_EE] = { 0x0800, 0x00, 0x00, 0x80 }, 158 [BAM_IRQ_SRCS_MSK_EE] = { 0x0804, 0x00, 0x00, 0x80 }, 159 [BAM_P_CTRL] = { 0x1000, 0x1000, 0x00, 0x00 }, 160 [BAM_P_RST] = { 0x1004, 0x1000, 0x00, 0x00 }, 161 [BAM_P_HALT] = { 0x1008, 0x1000, 0x00, 0x00 }, 162 [BAM_P_IRQ_STTS] = { 0x1010, 0x1000, 0x00, 0x00 }, 163 [BAM_P_IRQ_CLR] = { 0x1014, 0x1000, 0x00, 0x00 }, 164 [BAM_P_IRQ_EN] = { 0x1018, 0x1000, 0x00, 0x00 }, 165 [BAM_P_EVNT_DEST_ADDR] = { 0x182C, 0x00, 0x1000, 0x00 }, 166 [BAM_P_EVNT_REG] = { 0x1818, 0x00, 0x1000, 0x00 }, 167 [BAM_P_SW_OFSTS] = { 0x1800, 0x00, 0x1000, 0x00 }, 168 [BAM_P_DATA_FIFO_ADDR] = { 0x1824, 0x00, 0x1000, 0x00 }, 169 [BAM_P_DESC_FIFO_ADDR] = { 0x181C, 0x00, 0x1000, 0x00 }, 170 [BAM_P_EVNT_GEN_TRSHLD] = { 0x1828, 0x00, 0x1000, 0x00 }, 171 [BAM_P_FIFO_SIZES] = { 0x1820, 0x00, 0x1000, 0x00 }, 172 }; 173 174 static const struct reg_offset_data bam_v1_7_reg_info[] = { 175 [BAM_CTRL] = { 0x00000, 0x00, 0x00, 0x00 }, 176 [BAM_REVISION] = { 0x01000, 0x00, 0x00, 0x00 }, 177 [BAM_NUM_PIPES] = { 0x01008, 0x00, 0x00, 0x00 }, 178 [BAM_DESC_CNT_TRSHLD] = { 0x00008, 0x00, 0x00, 0x00 }, 179 [BAM_IRQ_SRCS] = { 0x03010, 0x00, 0x00, 0x00 }, 180 [BAM_IRQ_SRCS_MSK] = { 0x03014, 0x00, 0x00, 0x00 }, 181 [BAM_IRQ_SRCS_UNMASKED] = { 0x03018, 0x00, 0x00, 0x00 }, 182 [BAM_IRQ_STTS] = { 0x00014, 0x00, 0x00, 0x00 }, 183 [BAM_IRQ_CLR] = { 0x00018, 0x00, 0x00, 0x00 }, 184 [BAM_IRQ_EN] = { 0x0001C, 0x00, 0x00, 0x00 }, 185 [BAM_CNFG_BITS] = { 0x0007C, 0x00, 0x00, 0x00 }, 186 [BAM_IRQ_SRCS_EE] = { 0x03000, 0x00, 0x00, 0x1000 }, 187 [BAM_IRQ_SRCS_MSK_EE] = { 0x03004, 0x00, 0x00, 0x1000 }, 188 [BAM_P_CTRL] = { 0x13000, 0x1000, 0x00, 0x00 }, 189 [BAM_P_RST] = { 0x13004, 0x1000, 0x00, 0x00 }, 190 [BAM_P_HALT] = { 0x13008, 0x1000, 0x00, 0x00 }, 191 [BAM_P_IRQ_STTS] = { 0x13010, 0x1000, 0x00, 0x00 }, 192 [BAM_P_IRQ_CLR] = { 0x13014, 0x1000, 0x00, 0x00 }, 193 [BAM_P_IRQ_EN] = { 0x13018, 0x1000, 0x00, 0x00 }, 194 [BAM_P_EVNT_DEST_ADDR] = { 0x1382C, 0x00, 0x1000, 0x00 }, 195 [BAM_P_EVNT_REG] = { 0x13818, 0x00, 0x1000, 0x00 }, 196 [BAM_P_SW_OFSTS] = { 0x13800, 0x00, 0x1000, 0x00 }, 197 [BAM_P_DATA_FIFO_ADDR] = { 0x13824, 0x00, 0x1000, 0x00 }, 198 [BAM_P_DESC_FIFO_ADDR] = { 0x1381C, 0x00, 0x1000, 0x00 }, 199 [BAM_P_EVNT_GEN_TRSHLD] = { 0x13828, 0x00, 0x1000, 0x00 }, 200 [BAM_P_FIFO_SIZES] = { 0x13820, 0x00, 0x1000, 0x00 }, 201 }; 202 203 /* BAM CTRL */ 204 #define BAM_SW_RST BIT(0) 205 #define BAM_EN BIT(1) 206 #define BAM_EN_ACCUM BIT(4) 207 #define BAM_TESTBUS_SEL_SHIFT 5 208 #define BAM_TESTBUS_SEL_MASK 0x3F 209 #define BAM_DESC_CACHE_SEL_SHIFT 13 210 #define BAM_DESC_CACHE_SEL_MASK 0x3 211 #define BAM_CACHED_DESC_STORE BIT(15) 212 #define IBC_DISABLE BIT(16) 213 214 /* BAM REVISION */ 215 #define REVISION_SHIFT 0 216 #define REVISION_MASK 0xFF 217 #define NUM_EES_SHIFT 8 218 #define NUM_EES_MASK 0xF 219 #define CE_BUFFER_SIZE BIT(13) 220 #define AXI_ACTIVE BIT(14) 221 #define USE_VMIDMT BIT(15) 222 #define SECURED BIT(16) 223 #define BAM_HAS_NO_BYPASS BIT(17) 224 #define HIGH_FREQUENCY_BAM BIT(18) 225 #define INACTIV_TMRS_EXST BIT(19) 226 #define NUM_INACTIV_TMRS BIT(20) 227 #define DESC_CACHE_DEPTH_SHIFT 21 228 #define DESC_CACHE_DEPTH_1 (0 << DESC_CACHE_DEPTH_SHIFT) 229 #define DESC_CACHE_DEPTH_2 (1 << DESC_CACHE_DEPTH_SHIFT) 230 #define DESC_CACHE_DEPTH_3 (2 << DESC_CACHE_DEPTH_SHIFT) 231 #define DESC_CACHE_DEPTH_4 (3 << DESC_CACHE_DEPTH_SHIFT) 232 #define CMD_DESC_EN BIT(23) 233 #define INACTIV_TMR_BASE_SHIFT 24 234 #define INACTIV_TMR_BASE_MASK 0xFF 235 236 /* BAM NUM PIPES */ 237 #define BAM_NUM_PIPES_SHIFT 0 238 #define BAM_NUM_PIPES_MASK 0xFF 239 #define PERIPH_NON_PIPE_GRP_SHIFT 16 240 #define PERIPH_NON_PIP_GRP_MASK 0xFF 241 #define BAM_NON_PIPE_GRP_SHIFT 24 242 #define BAM_NON_PIPE_GRP_MASK 0xFF 243 244 /* BAM CNFG BITS */ 245 #define BAM_PIPE_CNFG BIT(2) 246 #define BAM_FULL_PIPE BIT(11) 247 #define BAM_NO_EXT_P_RST BIT(12) 248 #define BAM_IBC_DISABLE BIT(13) 249 #define BAM_SB_CLK_REQ BIT(14) 250 #define BAM_PSM_CSW_REQ BIT(15) 251 #define BAM_PSM_P_RES BIT(16) 252 #define BAM_AU_P_RES BIT(17) 253 #define BAM_SI_P_RES BIT(18) 254 #define BAM_WB_P_RES BIT(19) 255 #define BAM_WB_BLK_CSW BIT(20) 256 #define BAM_WB_CSW_ACK_IDL BIT(21) 257 #define BAM_WB_RETR_SVPNT BIT(22) 258 #define BAM_WB_DSC_AVL_P_RST BIT(23) 259 #define BAM_REG_P_EN BIT(24) 260 #define BAM_PSM_P_HD_DATA BIT(25) 261 #define BAM_AU_ACCUMED BIT(26) 262 #define BAM_CMD_ENABLE BIT(27) 263 264 #define BAM_CNFG_BITS_DEFAULT (BAM_PIPE_CNFG | \ 265 BAM_NO_EXT_P_RST | \ 266 BAM_IBC_DISABLE | \ 267 BAM_SB_CLK_REQ | \ 268 BAM_PSM_CSW_REQ | \ 269 BAM_PSM_P_RES | \ 270 BAM_AU_P_RES | \ 271 BAM_SI_P_RES | \ 272 BAM_WB_P_RES | \ 273 BAM_WB_BLK_CSW | \ 274 BAM_WB_CSW_ACK_IDL | \ 275 BAM_WB_RETR_SVPNT | \ 276 BAM_WB_DSC_AVL_P_RST | \ 277 BAM_REG_P_EN | \ 278 BAM_PSM_P_HD_DATA | \ 279 BAM_AU_ACCUMED | \ 280 BAM_CMD_ENABLE) 281 282 /* PIPE CTRL */ 283 #define P_EN BIT(1) 284 #define P_DIRECTION BIT(3) 285 #define P_SYS_STRM BIT(4) 286 #define P_SYS_MODE BIT(5) 287 #define P_AUTO_EOB BIT(6) 288 #define P_AUTO_EOB_SEL_SHIFT 7 289 #define P_AUTO_EOB_SEL_512 (0 << P_AUTO_EOB_SEL_SHIFT) 290 #define P_AUTO_EOB_SEL_256 (1 << P_AUTO_EOB_SEL_SHIFT) 291 #define P_AUTO_EOB_SEL_128 (2 << P_AUTO_EOB_SEL_SHIFT) 292 #define P_AUTO_EOB_SEL_64 (3 << P_AUTO_EOB_SEL_SHIFT) 293 #define P_PREFETCH_LIMIT_SHIFT 9 294 #define P_PREFETCH_LIMIT_32 (0 << P_PREFETCH_LIMIT_SHIFT) 295 #define P_PREFETCH_LIMIT_16 (1 << P_PREFETCH_LIMIT_SHIFT) 296 #define P_PREFETCH_LIMIT_4 (2 << P_PREFETCH_LIMIT_SHIFT) 297 #define P_WRITE_NWD BIT(11) 298 #define P_LOCK_GROUP_SHIFT 16 299 #define P_LOCK_GROUP_MASK 0x1F 300 301 /* BAM_DESC_CNT_TRSHLD */ 302 #define CNT_TRSHLD 0xffff 303 #define DEFAULT_CNT_THRSHLD 0x4 304 305 /* BAM_IRQ_SRCS */ 306 #define BAM_IRQ BIT(31) 307 #define P_IRQ 0x7fffffff 308 309 /* BAM_IRQ_SRCS_MSK */ 310 #define BAM_IRQ_MSK BAM_IRQ 311 #define P_IRQ_MSK P_IRQ 312 313 /* BAM_IRQ_STTS */ 314 #define BAM_TIMER_IRQ BIT(4) 315 #define BAM_EMPTY_IRQ BIT(3) 316 #define BAM_ERROR_IRQ BIT(2) 317 #define BAM_HRESP_ERR_IRQ BIT(1) 318 319 /* BAM_IRQ_CLR */ 320 #define BAM_TIMER_CLR BIT(4) 321 #define BAM_EMPTY_CLR BIT(3) 322 #define BAM_ERROR_CLR BIT(2) 323 #define BAM_HRESP_ERR_CLR BIT(1) 324 325 /* BAM_IRQ_EN */ 326 #define BAM_TIMER_EN BIT(4) 327 #define BAM_EMPTY_EN BIT(3) 328 #define BAM_ERROR_EN BIT(2) 329 #define BAM_HRESP_ERR_EN BIT(1) 330 331 /* BAM_P_IRQ_EN */ 332 #define P_PRCSD_DESC_EN BIT(0) 333 #define P_TIMER_EN BIT(1) 334 #define P_WAKE_EN BIT(2) 335 #define P_OUT_OF_DESC_EN BIT(3) 336 #define P_ERR_EN BIT(4) 337 #define P_TRNSFR_END_EN BIT(5) 338 #define P_DEFAULT_IRQS_EN (P_PRCSD_DESC_EN | P_ERR_EN | P_TRNSFR_END_EN) 339 340 /* BAM_P_SW_OFSTS */ 341 #define P_SW_OFSTS_MASK 0xffff 342 343 #define BAM_DESC_FIFO_SIZE SZ_32K 344 #define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw) - 1) 345 #define BAM_FIFO_SIZE (SZ_32K - 8) 346 347 struct bam_chan { 348 struct virt_dma_chan vc; 349 350 struct bam_device *bdev; 351 352 /* configuration from device tree */ 353 u32 id; 354 355 struct bam_async_desc *curr_txd; /* current running dma */ 356 357 /* runtime configuration */ 358 struct dma_slave_config slave; 359 360 /* fifo storage */ 361 struct bam_desc_hw *fifo_virt; 362 dma_addr_t fifo_phys; 363 364 /* fifo markers */ 365 unsigned short head; /* start of active descriptor entries */ 366 unsigned short tail; /* end of active descriptor entries */ 367 368 unsigned int initialized; /* is the channel hw initialized? */ 369 unsigned int paused; /* is the channel paused? */ 370 unsigned int reconfigure; /* new slave config? */ 371 372 struct list_head node; 373 }; 374 375 static inline struct bam_chan *to_bam_chan(struct dma_chan *common) 376 { 377 return container_of(common, struct bam_chan, vc.chan); 378 } 379 380 struct bam_device { 381 void __iomem *regs; 382 struct device *dev; 383 struct dma_device common; 384 struct device_dma_parameters dma_parms; 385 struct bam_chan *channels; 386 u32 num_channels; 387 388 /* execution environment ID, from DT */ 389 u32 ee; 390 bool controlled_remotely; 391 392 const struct reg_offset_data *layout; 393 394 struct clk *bamclk; 395 int irq; 396 397 /* dma start transaction tasklet */ 398 struct tasklet_struct task; 399 }; 400 401 /** 402 * bam_addr - returns BAM register address 403 * @bdev: bam device 404 * @pipe: pipe instance (ignored when register doesn't have multiple instances) 405 * @reg: register enum 406 */ 407 static inline void __iomem *bam_addr(struct bam_device *bdev, u32 pipe, 408 enum bam_reg reg) 409 { 410 const struct reg_offset_data r = bdev->layout[reg]; 411 412 return bdev->regs + r.base_offset + 413 r.pipe_mult * pipe + 414 r.evnt_mult * pipe + 415 r.ee_mult * bdev->ee; 416 } 417 418 /** 419 * bam_reset_channel - Reset individual BAM DMA channel 420 * @bchan: bam channel 421 * 422 * This function resets a specific BAM channel 423 */ 424 static void bam_reset_channel(struct bam_chan *bchan) 425 { 426 struct bam_device *bdev = bchan->bdev; 427 428 lockdep_assert_held(&bchan->vc.lock); 429 430 /* reset channel */ 431 writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_RST)); 432 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_RST)); 433 434 /* don't allow cpu to reorder BAM register accesses done after this */ 435 wmb(); 436 437 /* make sure hw is initialized when channel is used the first time */ 438 bchan->initialized = 0; 439 } 440 441 /** 442 * bam_chan_init_hw - Initialize channel hardware 443 * @bchan: bam channel 444 * 445 * This function resets and initializes the BAM channel 446 */ 447 static void bam_chan_init_hw(struct bam_chan *bchan, 448 enum dma_transfer_direction dir) 449 { 450 struct bam_device *bdev = bchan->bdev; 451 u32 val; 452 453 /* Reset the channel to clear internal state of the FIFO */ 454 bam_reset_channel(bchan); 455 456 /* 457 * write out 8 byte aligned address. We have enough space for this 458 * because we allocated 1 more descriptor (8 bytes) than we can use 459 */ 460 writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)), 461 bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR)); 462 writel_relaxed(BAM_FIFO_SIZE, 463 bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES)); 464 465 /* enable the per pipe interrupts, enable EOT, ERR, and INT irqs */ 466 writel_relaxed(P_DEFAULT_IRQS_EN, 467 bam_addr(bdev, bchan->id, BAM_P_IRQ_EN)); 468 469 /* unmask the specific pipe and EE combo */ 470 val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); 471 val |= BIT(bchan->id); 472 writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); 473 474 /* don't allow cpu to reorder the channel enable done below */ 475 wmb(); 476 477 /* set fixed direction and mode, then enable channel */ 478 val = P_EN | P_SYS_MODE; 479 if (dir == DMA_DEV_TO_MEM) 480 val |= P_DIRECTION; 481 482 writel_relaxed(val, bam_addr(bdev, bchan->id, BAM_P_CTRL)); 483 484 bchan->initialized = 1; 485 486 /* init FIFO pointers */ 487 bchan->head = 0; 488 bchan->tail = 0; 489 } 490 491 /** 492 * bam_alloc_chan - Allocate channel resources for DMA channel. 493 * @chan: specified channel 494 * 495 * This function allocates the FIFO descriptor memory 496 */ 497 static int bam_alloc_chan(struct dma_chan *chan) 498 { 499 struct bam_chan *bchan = to_bam_chan(chan); 500 struct bam_device *bdev = bchan->bdev; 501 502 if (bchan->fifo_virt) 503 return 0; 504 505 /* allocate FIFO descriptor space, but only if necessary */ 506 bchan->fifo_virt = dma_alloc_wc(bdev->dev, BAM_DESC_FIFO_SIZE, 507 &bchan->fifo_phys, GFP_KERNEL); 508 509 if (!bchan->fifo_virt) { 510 dev_err(bdev->dev, "Failed to allocate desc fifo\n"); 511 return -ENOMEM; 512 } 513 514 return 0; 515 } 516 517 /** 518 * bam_free_chan - Frees dma resources associated with specific channel 519 * @chan: specified channel 520 * 521 * Free the allocated fifo descriptor memory and channel resources 522 * 523 */ 524 static void bam_free_chan(struct dma_chan *chan) 525 { 526 struct bam_chan *bchan = to_bam_chan(chan); 527 struct bam_device *bdev = bchan->bdev; 528 u32 val; 529 unsigned long flags; 530 531 vchan_free_chan_resources(to_virt_chan(chan)); 532 533 if (bchan->curr_txd) { 534 dev_err(bchan->bdev->dev, "Cannot free busy channel\n"); 535 return; 536 } 537 538 spin_lock_irqsave(&bchan->vc.lock, flags); 539 bam_reset_channel(bchan); 540 spin_unlock_irqrestore(&bchan->vc.lock, flags); 541 542 dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE, bchan->fifo_virt, 543 bchan->fifo_phys); 544 bchan->fifo_virt = NULL; 545 546 /* mask irq for pipe/channel */ 547 val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); 548 val &= ~BIT(bchan->id); 549 writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); 550 551 /* disable irq */ 552 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_IRQ_EN)); 553 } 554 555 /** 556 * bam_slave_config - set slave configuration for channel 557 * @chan: dma channel 558 * @cfg: slave configuration 559 * 560 * Sets slave configuration for channel 561 * 562 */ 563 static int bam_slave_config(struct dma_chan *chan, 564 struct dma_slave_config *cfg) 565 { 566 struct bam_chan *bchan = to_bam_chan(chan); 567 unsigned long flag; 568 569 spin_lock_irqsave(&bchan->vc.lock, flag); 570 memcpy(&bchan->slave, cfg, sizeof(*cfg)); 571 bchan->reconfigure = 1; 572 spin_unlock_irqrestore(&bchan->vc.lock, flag); 573 574 return 0; 575 } 576 577 /** 578 * bam_prep_slave_sg - Prep slave sg transaction 579 * 580 * @chan: dma channel 581 * @sgl: scatter gather list 582 * @sg_len: length of sg 583 * @direction: DMA transfer direction 584 * @flags: DMA flags 585 * @context: transfer context (unused) 586 */ 587 static struct dma_async_tx_descriptor *bam_prep_slave_sg(struct dma_chan *chan, 588 struct scatterlist *sgl, unsigned int sg_len, 589 enum dma_transfer_direction direction, unsigned long flags, 590 void *context) 591 { 592 struct bam_chan *bchan = to_bam_chan(chan); 593 struct bam_device *bdev = bchan->bdev; 594 struct bam_async_desc *async_desc; 595 struct scatterlist *sg; 596 u32 i; 597 struct bam_desc_hw *desc; 598 unsigned int num_alloc = 0; 599 600 601 if (!is_slave_direction(direction)) { 602 dev_err(bdev->dev, "invalid dma direction\n"); 603 return NULL; 604 } 605 606 /* calculate number of required entries */ 607 for_each_sg(sgl, sg, sg_len, i) 608 num_alloc += DIV_ROUND_UP(sg_dma_len(sg), BAM_FIFO_SIZE); 609 610 /* allocate enough room to accomodate the number of entries */ 611 async_desc = kzalloc(sizeof(*async_desc) + 612 (num_alloc * sizeof(struct bam_desc_hw)), GFP_NOWAIT); 613 614 if (!async_desc) 615 goto err_out; 616 617 if (flags & DMA_PREP_FENCE) 618 async_desc->flags |= DESC_FLAG_NWD; 619 620 if (flags & DMA_PREP_INTERRUPT) 621 async_desc->flags |= DESC_FLAG_EOT; 622 else 623 async_desc->flags |= DESC_FLAG_INT; 624 625 async_desc->num_desc = num_alloc; 626 async_desc->curr_desc = async_desc->desc; 627 async_desc->dir = direction; 628 629 /* fill in temporary descriptors */ 630 desc = async_desc->desc; 631 for_each_sg(sgl, sg, sg_len, i) { 632 unsigned int remainder = sg_dma_len(sg); 633 unsigned int curr_offset = 0; 634 635 do { 636 desc->addr = cpu_to_le32(sg_dma_address(sg) + 637 curr_offset); 638 639 if (remainder > BAM_FIFO_SIZE) { 640 desc->size = cpu_to_le16(BAM_FIFO_SIZE); 641 remainder -= BAM_FIFO_SIZE; 642 curr_offset += BAM_FIFO_SIZE; 643 } else { 644 desc->size = cpu_to_le16(remainder); 645 remainder = 0; 646 } 647 648 async_desc->length += desc->size; 649 desc++; 650 } while (remainder > 0); 651 } 652 653 return vchan_tx_prep(&bchan->vc, &async_desc->vd, flags); 654 655 err_out: 656 kfree(async_desc); 657 return NULL; 658 } 659 660 /** 661 * bam_dma_terminate_all - terminate all transactions on a channel 662 * @bchan: bam dma channel 663 * 664 * Dequeues and frees all transactions 665 * No callbacks are done 666 * 667 */ 668 static int bam_dma_terminate_all(struct dma_chan *chan) 669 { 670 struct bam_chan *bchan = to_bam_chan(chan); 671 unsigned long flag; 672 LIST_HEAD(head); 673 674 /* remove all transactions, including active transaction */ 675 spin_lock_irqsave(&bchan->vc.lock, flag); 676 if (bchan->curr_txd) { 677 list_add(&bchan->curr_txd->vd.node, &bchan->vc.desc_issued); 678 bchan->curr_txd = NULL; 679 } 680 681 vchan_get_all_descriptors(&bchan->vc, &head); 682 spin_unlock_irqrestore(&bchan->vc.lock, flag); 683 684 vchan_dma_desc_free_list(&bchan->vc, &head); 685 686 return 0; 687 } 688 689 /** 690 * bam_pause - Pause DMA channel 691 * @chan: dma channel 692 * 693 */ 694 static int bam_pause(struct dma_chan *chan) 695 { 696 struct bam_chan *bchan = to_bam_chan(chan); 697 struct bam_device *bdev = bchan->bdev; 698 unsigned long flag; 699 700 spin_lock_irqsave(&bchan->vc.lock, flag); 701 writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_HALT)); 702 bchan->paused = 1; 703 spin_unlock_irqrestore(&bchan->vc.lock, flag); 704 705 return 0; 706 } 707 708 /** 709 * bam_resume - Resume DMA channel operations 710 * @chan: dma channel 711 * 712 */ 713 static int bam_resume(struct dma_chan *chan) 714 { 715 struct bam_chan *bchan = to_bam_chan(chan); 716 struct bam_device *bdev = bchan->bdev; 717 unsigned long flag; 718 719 spin_lock_irqsave(&bchan->vc.lock, flag); 720 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_HALT)); 721 bchan->paused = 0; 722 spin_unlock_irqrestore(&bchan->vc.lock, flag); 723 724 return 0; 725 } 726 727 /** 728 * process_channel_irqs - processes the channel interrupts 729 * @bdev: bam controller 730 * 731 * This function processes the channel interrupts 732 * 733 */ 734 static u32 process_channel_irqs(struct bam_device *bdev) 735 { 736 u32 i, srcs, pipe_stts; 737 unsigned long flags; 738 struct bam_async_desc *async_desc; 739 740 srcs = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_EE)); 741 742 /* return early if no pipe/channel interrupts are present */ 743 if (!(srcs & P_IRQ)) 744 return srcs; 745 746 for (i = 0; i < bdev->num_channels; i++) { 747 struct bam_chan *bchan = &bdev->channels[i]; 748 749 if (!(srcs & BIT(i))) 750 continue; 751 752 /* clear pipe irq */ 753 pipe_stts = readl_relaxed(bam_addr(bdev, i, BAM_P_IRQ_STTS)); 754 755 writel_relaxed(pipe_stts, bam_addr(bdev, i, BAM_P_IRQ_CLR)); 756 757 spin_lock_irqsave(&bchan->vc.lock, flags); 758 async_desc = bchan->curr_txd; 759 760 if (async_desc) { 761 async_desc->num_desc -= async_desc->xfer_len; 762 async_desc->curr_desc += async_desc->xfer_len; 763 bchan->curr_txd = NULL; 764 765 /* manage FIFO */ 766 bchan->head += async_desc->xfer_len; 767 bchan->head %= MAX_DESCRIPTORS; 768 769 /* 770 * if complete, process cookie. Otherwise 771 * push back to front of desc_issued so that 772 * it gets restarted by the tasklet 773 */ 774 if (!async_desc->num_desc) 775 vchan_cookie_complete(&async_desc->vd); 776 else 777 list_add(&async_desc->vd.node, 778 &bchan->vc.desc_issued); 779 } 780 781 spin_unlock_irqrestore(&bchan->vc.lock, flags); 782 } 783 784 return srcs; 785 } 786 787 /** 788 * bam_dma_irq - irq handler for bam controller 789 * @irq: IRQ of interrupt 790 * @data: callback data 791 * 792 * IRQ handler for the bam controller 793 */ 794 static irqreturn_t bam_dma_irq(int irq, void *data) 795 { 796 struct bam_device *bdev = data; 797 u32 clr_mask = 0, srcs = 0; 798 799 srcs |= process_channel_irqs(bdev); 800 801 /* kick off tasklet to start next dma transfer */ 802 if (srcs & P_IRQ) 803 tasklet_schedule(&bdev->task); 804 805 if (srcs & BAM_IRQ) { 806 clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS)); 807 808 /* 809 * don't allow reorder of the various accesses to the BAM 810 * registers 811 */ 812 mb(); 813 814 writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR)); 815 } 816 817 return IRQ_HANDLED; 818 } 819 820 /** 821 * bam_tx_status - returns status of transaction 822 * @chan: dma channel 823 * @cookie: transaction cookie 824 * @txstate: DMA transaction state 825 * 826 * Return status of dma transaction 827 */ 828 static enum dma_status bam_tx_status(struct dma_chan *chan, dma_cookie_t cookie, 829 struct dma_tx_state *txstate) 830 { 831 struct bam_chan *bchan = to_bam_chan(chan); 832 struct virt_dma_desc *vd; 833 int ret; 834 size_t residue = 0; 835 unsigned int i; 836 unsigned long flags; 837 838 ret = dma_cookie_status(chan, cookie, txstate); 839 if (ret == DMA_COMPLETE) 840 return ret; 841 842 if (!txstate) 843 return bchan->paused ? DMA_PAUSED : ret; 844 845 spin_lock_irqsave(&bchan->vc.lock, flags); 846 vd = vchan_find_desc(&bchan->vc, cookie); 847 if (vd) 848 residue = container_of(vd, struct bam_async_desc, vd)->length; 849 else if (bchan->curr_txd && bchan->curr_txd->vd.tx.cookie == cookie) 850 for (i = 0; i < bchan->curr_txd->num_desc; i++) 851 residue += bchan->curr_txd->curr_desc[i].size; 852 853 spin_unlock_irqrestore(&bchan->vc.lock, flags); 854 855 dma_set_residue(txstate, residue); 856 857 if (ret == DMA_IN_PROGRESS && bchan->paused) 858 ret = DMA_PAUSED; 859 860 return ret; 861 } 862 863 /** 864 * bam_apply_new_config 865 * @bchan: bam dma channel 866 * @dir: DMA direction 867 */ 868 static void bam_apply_new_config(struct bam_chan *bchan, 869 enum dma_transfer_direction dir) 870 { 871 struct bam_device *bdev = bchan->bdev; 872 u32 maxburst; 873 874 if (dir == DMA_DEV_TO_MEM) 875 maxburst = bchan->slave.src_maxburst; 876 else 877 maxburst = bchan->slave.dst_maxburst; 878 879 writel_relaxed(maxburst, bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD)); 880 881 bchan->reconfigure = 0; 882 } 883 884 /** 885 * bam_start_dma - start next transaction 886 * @bchan - bam dma channel 887 */ 888 static void bam_start_dma(struct bam_chan *bchan) 889 { 890 struct virt_dma_desc *vd = vchan_next_desc(&bchan->vc); 891 struct bam_device *bdev = bchan->bdev; 892 struct bam_async_desc *async_desc; 893 struct bam_desc_hw *desc; 894 struct bam_desc_hw *fifo = PTR_ALIGN(bchan->fifo_virt, 895 sizeof(struct bam_desc_hw)); 896 897 lockdep_assert_held(&bchan->vc.lock); 898 899 if (!vd) 900 return; 901 902 list_del(&vd->node); 903 904 async_desc = container_of(vd, struct bam_async_desc, vd); 905 bchan->curr_txd = async_desc; 906 907 /* on first use, initialize the channel hardware */ 908 if (!bchan->initialized) 909 bam_chan_init_hw(bchan, async_desc->dir); 910 911 /* apply new slave config changes, if necessary */ 912 if (bchan->reconfigure) 913 bam_apply_new_config(bchan, async_desc->dir); 914 915 desc = bchan->curr_txd->curr_desc; 916 917 if (async_desc->num_desc > MAX_DESCRIPTORS) 918 async_desc->xfer_len = MAX_DESCRIPTORS; 919 else 920 async_desc->xfer_len = async_desc->num_desc; 921 922 /* set any special flags on the last descriptor */ 923 if (async_desc->num_desc == async_desc->xfer_len) 924 desc[async_desc->xfer_len - 1].flags = 925 cpu_to_le16(async_desc->flags); 926 else 927 desc[async_desc->xfer_len - 1].flags |= 928 cpu_to_le16(DESC_FLAG_INT); 929 930 if (bchan->tail + async_desc->xfer_len > MAX_DESCRIPTORS) { 931 u32 partial = MAX_DESCRIPTORS - bchan->tail; 932 933 memcpy(&fifo[bchan->tail], desc, 934 partial * sizeof(struct bam_desc_hw)); 935 memcpy(fifo, &desc[partial], (async_desc->xfer_len - partial) * 936 sizeof(struct bam_desc_hw)); 937 } else { 938 memcpy(&fifo[bchan->tail], desc, 939 async_desc->xfer_len * sizeof(struct bam_desc_hw)); 940 } 941 942 bchan->tail += async_desc->xfer_len; 943 bchan->tail %= MAX_DESCRIPTORS; 944 945 /* ensure descriptor writes and dma start not reordered */ 946 wmb(); 947 writel_relaxed(bchan->tail * sizeof(struct bam_desc_hw), 948 bam_addr(bdev, bchan->id, BAM_P_EVNT_REG)); 949 } 950 951 /** 952 * dma_tasklet - DMA IRQ tasklet 953 * @data: tasklet argument (bam controller structure) 954 * 955 * Sets up next DMA operation and then processes all completed transactions 956 */ 957 static void dma_tasklet(unsigned long data) 958 { 959 struct bam_device *bdev = (struct bam_device *)data; 960 struct bam_chan *bchan; 961 unsigned long flags; 962 unsigned int i; 963 964 /* go through the channels and kick off transactions */ 965 for (i = 0; i < bdev->num_channels; i++) { 966 bchan = &bdev->channels[i]; 967 spin_lock_irqsave(&bchan->vc.lock, flags); 968 969 if (!list_empty(&bchan->vc.desc_issued) && !bchan->curr_txd) 970 bam_start_dma(bchan); 971 spin_unlock_irqrestore(&bchan->vc.lock, flags); 972 } 973 } 974 975 /** 976 * bam_issue_pending - starts pending transactions 977 * @chan: dma channel 978 * 979 * Calls tasklet directly which in turn starts any pending transactions 980 */ 981 static void bam_issue_pending(struct dma_chan *chan) 982 { 983 struct bam_chan *bchan = to_bam_chan(chan); 984 unsigned long flags; 985 986 spin_lock_irqsave(&bchan->vc.lock, flags); 987 988 /* if work pending and idle, start a transaction */ 989 if (vchan_issue_pending(&bchan->vc) && !bchan->curr_txd) 990 bam_start_dma(bchan); 991 992 spin_unlock_irqrestore(&bchan->vc.lock, flags); 993 } 994 995 /** 996 * bam_dma_free_desc - free descriptor memory 997 * @vd: virtual descriptor 998 * 999 */ 1000 static void bam_dma_free_desc(struct virt_dma_desc *vd) 1001 { 1002 struct bam_async_desc *async_desc = container_of(vd, 1003 struct bam_async_desc, vd); 1004 1005 kfree(async_desc); 1006 } 1007 1008 static struct dma_chan *bam_dma_xlate(struct of_phandle_args *dma_spec, 1009 struct of_dma *of) 1010 { 1011 struct bam_device *bdev = container_of(of->of_dma_data, 1012 struct bam_device, common); 1013 unsigned int request; 1014 1015 if (dma_spec->args_count != 1) 1016 return NULL; 1017 1018 request = dma_spec->args[0]; 1019 if (request >= bdev->num_channels) 1020 return NULL; 1021 1022 return dma_get_slave_channel(&(bdev->channels[request].vc.chan)); 1023 } 1024 1025 /** 1026 * bam_init 1027 * @bdev: bam device 1028 * 1029 * Initialization helper for global bam registers 1030 */ 1031 static int bam_init(struct bam_device *bdev) 1032 { 1033 u32 val; 1034 1035 /* read revision and configuration information */ 1036 val = readl_relaxed(bam_addr(bdev, 0, BAM_REVISION)) >> NUM_EES_SHIFT; 1037 val &= NUM_EES_MASK; 1038 1039 /* check that configured EE is within range */ 1040 if (bdev->ee >= val) 1041 return -EINVAL; 1042 1043 val = readl_relaxed(bam_addr(bdev, 0, BAM_NUM_PIPES)); 1044 bdev->num_channels = val & BAM_NUM_PIPES_MASK; 1045 1046 if (bdev->controlled_remotely) 1047 return 0; 1048 1049 /* s/w reset bam */ 1050 /* after reset all pipes are disabled and idle */ 1051 val = readl_relaxed(bam_addr(bdev, 0, BAM_CTRL)); 1052 val |= BAM_SW_RST; 1053 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL)); 1054 val &= ~BAM_SW_RST; 1055 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL)); 1056 1057 /* make sure previous stores are visible before enabling BAM */ 1058 wmb(); 1059 1060 /* enable bam */ 1061 val |= BAM_EN; 1062 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL)); 1063 1064 /* set descriptor threshhold, start with 4 bytes */ 1065 writel_relaxed(DEFAULT_CNT_THRSHLD, 1066 bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD)); 1067 1068 /* Enable default set of h/w workarounds, ie all except BAM_FULL_PIPE */ 1069 writel_relaxed(BAM_CNFG_BITS_DEFAULT, bam_addr(bdev, 0, BAM_CNFG_BITS)); 1070 1071 /* enable irqs for errors */ 1072 writel_relaxed(BAM_ERROR_EN | BAM_HRESP_ERR_EN, 1073 bam_addr(bdev, 0, BAM_IRQ_EN)); 1074 1075 /* unmask global bam interrupt */ 1076 writel_relaxed(BAM_IRQ_MSK, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); 1077 1078 return 0; 1079 } 1080 1081 static void bam_channel_init(struct bam_device *bdev, struct bam_chan *bchan, 1082 u32 index) 1083 { 1084 bchan->id = index; 1085 bchan->bdev = bdev; 1086 1087 vchan_init(&bchan->vc, &bdev->common); 1088 bchan->vc.desc_free = bam_dma_free_desc; 1089 } 1090 1091 static const struct of_device_id bam_of_match[] = { 1092 { .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_reg_info }, 1093 { .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_reg_info }, 1094 { .compatible = "qcom,bam-v1.7.0", .data = &bam_v1_7_reg_info }, 1095 {} 1096 }; 1097 1098 MODULE_DEVICE_TABLE(of, bam_of_match); 1099 1100 static int bam_dma_probe(struct platform_device *pdev) 1101 { 1102 struct bam_device *bdev; 1103 const struct of_device_id *match; 1104 struct resource *iores; 1105 int ret, i; 1106 1107 bdev = devm_kzalloc(&pdev->dev, sizeof(*bdev), GFP_KERNEL); 1108 if (!bdev) 1109 return -ENOMEM; 1110 1111 bdev->dev = &pdev->dev; 1112 1113 match = of_match_node(bam_of_match, pdev->dev.of_node); 1114 if (!match) { 1115 dev_err(&pdev->dev, "Unsupported BAM module\n"); 1116 return -ENODEV; 1117 } 1118 1119 bdev->layout = match->data; 1120 1121 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1122 bdev->regs = devm_ioremap_resource(&pdev->dev, iores); 1123 if (IS_ERR(bdev->regs)) 1124 return PTR_ERR(bdev->regs); 1125 1126 bdev->irq = platform_get_irq(pdev, 0); 1127 if (bdev->irq < 0) 1128 return bdev->irq; 1129 1130 ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &bdev->ee); 1131 if (ret) { 1132 dev_err(bdev->dev, "Execution environment unspecified\n"); 1133 return ret; 1134 } 1135 1136 bdev->controlled_remotely = of_property_read_bool(pdev->dev.of_node, 1137 "qcom,controlled-remotely"); 1138 1139 bdev->bamclk = devm_clk_get(bdev->dev, "bam_clk"); 1140 if (IS_ERR(bdev->bamclk)) 1141 return PTR_ERR(bdev->bamclk); 1142 1143 ret = clk_prepare_enable(bdev->bamclk); 1144 if (ret) { 1145 dev_err(bdev->dev, "failed to prepare/enable clock\n"); 1146 return ret; 1147 } 1148 1149 ret = bam_init(bdev); 1150 if (ret) 1151 goto err_disable_clk; 1152 1153 tasklet_init(&bdev->task, dma_tasklet, (unsigned long)bdev); 1154 1155 bdev->channels = devm_kcalloc(bdev->dev, bdev->num_channels, 1156 sizeof(*bdev->channels), GFP_KERNEL); 1157 1158 if (!bdev->channels) { 1159 ret = -ENOMEM; 1160 goto err_tasklet_kill; 1161 } 1162 1163 /* allocate and initialize channels */ 1164 INIT_LIST_HEAD(&bdev->common.channels); 1165 1166 for (i = 0; i < bdev->num_channels; i++) 1167 bam_channel_init(bdev, &bdev->channels[i], i); 1168 1169 ret = devm_request_irq(bdev->dev, bdev->irq, bam_dma_irq, 1170 IRQF_TRIGGER_HIGH, "bam_dma", bdev); 1171 if (ret) 1172 goto err_bam_channel_exit; 1173 1174 /* set max dma segment size */ 1175 bdev->common.dev = bdev->dev; 1176 bdev->common.dev->dma_parms = &bdev->dma_parms; 1177 ret = dma_set_max_seg_size(bdev->common.dev, BAM_FIFO_SIZE); 1178 if (ret) { 1179 dev_err(bdev->dev, "cannot set maximum segment size\n"); 1180 goto err_bam_channel_exit; 1181 } 1182 1183 platform_set_drvdata(pdev, bdev); 1184 1185 /* set capabilities */ 1186 dma_cap_zero(bdev->common.cap_mask); 1187 dma_cap_set(DMA_SLAVE, bdev->common.cap_mask); 1188 1189 /* initialize dmaengine apis */ 1190 bdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 1191 bdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 1192 bdev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES; 1193 bdev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES; 1194 bdev->common.device_alloc_chan_resources = bam_alloc_chan; 1195 bdev->common.device_free_chan_resources = bam_free_chan; 1196 bdev->common.device_prep_slave_sg = bam_prep_slave_sg; 1197 bdev->common.device_config = bam_slave_config; 1198 bdev->common.device_pause = bam_pause; 1199 bdev->common.device_resume = bam_resume; 1200 bdev->common.device_terminate_all = bam_dma_terminate_all; 1201 bdev->common.device_issue_pending = bam_issue_pending; 1202 bdev->common.device_tx_status = bam_tx_status; 1203 bdev->common.dev = bdev->dev; 1204 1205 ret = dma_async_device_register(&bdev->common); 1206 if (ret) { 1207 dev_err(bdev->dev, "failed to register dma async device\n"); 1208 goto err_bam_channel_exit; 1209 } 1210 1211 ret = of_dma_controller_register(pdev->dev.of_node, bam_dma_xlate, 1212 &bdev->common); 1213 if (ret) 1214 goto err_unregister_dma; 1215 1216 return 0; 1217 1218 err_unregister_dma: 1219 dma_async_device_unregister(&bdev->common); 1220 err_bam_channel_exit: 1221 for (i = 0; i < bdev->num_channels; i++) 1222 tasklet_kill(&bdev->channels[i].vc.task); 1223 err_tasklet_kill: 1224 tasklet_kill(&bdev->task); 1225 err_disable_clk: 1226 clk_disable_unprepare(bdev->bamclk); 1227 1228 return ret; 1229 } 1230 1231 static int bam_dma_remove(struct platform_device *pdev) 1232 { 1233 struct bam_device *bdev = platform_get_drvdata(pdev); 1234 u32 i; 1235 1236 of_dma_controller_free(pdev->dev.of_node); 1237 dma_async_device_unregister(&bdev->common); 1238 1239 /* mask all interrupts for this execution environment */ 1240 writel_relaxed(0, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); 1241 1242 devm_free_irq(bdev->dev, bdev->irq, bdev); 1243 1244 for (i = 0; i < bdev->num_channels; i++) { 1245 bam_dma_terminate_all(&bdev->channels[i].vc.chan); 1246 tasklet_kill(&bdev->channels[i].vc.task); 1247 1248 if (!bdev->channels[i].fifo_virt) 1249 continue; 1250 1251 dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE, 1252 bdev->channels[i].fifo_virt, 1253 bdev->channels[i].fifo_phys); 1254 } 1255 1256 tasklet_kill(&bdev->task); 1257 1258 clk_disable_unprepare(bdev->bamclk); 1259 1260 return 0; 1261 } 1262 1263 static struct platform_driver bam_dma_driver = { 1264 .probe = bam_dma_probe, 1265 .remove = bam_dma_remove, 1266 .driver = { 1267 .name = "bam-dma-engine", 1268 .of_match_table = bam_of_match, 1269 }, 1270 }; 1271 1272 module_platform_driver(bam_dma_driver); 1273 1274 MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>"); 1275 MODULE_DESCRIPTION("QCOM BAM DMA engine driver"); 1276 MODULE_LICENSE("GPL v2"); 1277