1# SPDX-License-Identifier: GPL-2.0-only 2config QCOM_ADM 3 tristate "Qualcomm ADM support" 4 depends on (ARCH_QCOM || COMPILE_TEST) && !PHYS_ADDR_T_64BIT 5 select DMA_ENGINE 6 select DMA_VIRTUAL_CHANNELS 7 help 8 Enable support for the Qualcomm Application Data Mover (ADM) DMA 9 controller, as present on MSM8x60, APQ8064, and IPQ8064 devices. 10 This controller provides DMA capabilities for both general purpose 11 and on-chip peripheral devices. 12 13config QCOM_BAM_DMA 14 tristate "QCOM BAM DMA support" 15 depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM) 16 select DMA_ENGINE 17 select DMA_VIRTUAL_CHANNELS 18 help 19 Enable support for the QCOM BAM DMA controller. This controller 20 provides DMA capabilities for a variety of on-chip devices. 21 22config QCOM_GPI_DMA 23 tristate "Qualcomm Technologies GPI DMA support" 24 depends on ARCH_QCOM 25 select DMA_ENGINE 26 select DMA_VIRTUAL_CHANNELS 27 help 28 Enable support for the QCOM GPI DMA controller. This controller 29 provides DMA capabilities for a variety of peripheral buses such 30 as I2C, UART, and SPI. By using GPI dmaengine driver, bus drivers 31 can use a standardize interface that is protocol independent to 32 transfer data between DDR and peripheral. 33 34config QCOM_HIDMA_MGMT 35 tristate "Qualcomm Technologies HIDMA Management support" 36 depends on HAS_IOMEM 37 select DMA_ENGINE 38 help 39 Enable support for the Qualcomm Technologies HIDMA Management. 40 Each DMA device requires one management interface driver 41 for basic initialization before QCOM_HIDMA channel driver can 42 start managing the channels. In a virtualized environment, 43 the guest OS would run QCOM_HIDMA channel driver and the 44 host would run the QCOM_HIDMA_MGMT management driver. 45 46config QCOM_HIDMA 47 tristate "Qualcomm Technologies HIDMA Channel support" 48 select DMA_ENGINE 49 help 50 Enable support for the Qualcomm Technologies HIDMA controller. 51 The HIDMA controller supports optimized buffer copies 52 (user to kernel, kernel to kernel, etc.). It only supports 53 memcpy interface. The core is not intended for general 54 purpose slave DMA. 55