xref: /openbmc/linux/drivers/dma/pxa_dma.c (revision b8d312aa)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright 2015 Robert Jarzmik <robert.jarzmik@free.fr>
4  */
5 
6 #include <linux/err.h>
7 #include <linux/module.h>
8 #include <linux/init.h>
9 #include <linux/types.h>
10 #include <linux/interrupt.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/slab.h>
13 #include <linux/dmaengine.h>
14 #include <linux/platform_device.h>
15 #include <linux/device.h>
16 #include <linux/platform_data/mmp_dma.h>
17 #include <linux/dmapool.h>
18 #include <linux/of_device.h>
19 #include <linux/of_dma.h>
20 #include <linux/of.h>
21 #include <linux/wait.h>
22 #include <linux/dma/pxa-dma.h>
23 
24 #include "dmaengine.h"
25 #include "virt-dma.h"
26 
27 #define DCSR(n)		(0x0000 + ((n) << 2))
28 #define DALGN(n)	0x00a0
29 #define DINT		0x00f0
30 #define DDADR(n)	(0x0200 + ((n) << 4))
31 #define DSADR(n)	(0x0204 + ((n) << 4))
32 #define DTADR(n)	(0x0208 + ((n) << 4))
33 #define DCMD(n)		(0x020c + ((n) << 4))
34 
35 #define PXA_DCSR_RUN		BIT(31)	/* Run Bit (read / write) */
36 #define PXA_DCSR_NODESC		BIT(30)	/* No-Descriptor Fetch (read / write) */
37 #define PXA_DCSR_STOPIRQEN	BIT(29)	/* Stop Interrupt Enable (R/W) */
38 #define PXA_DCSR_REQPEND	BIT(8)	/* Request Pending (read-only) */
39 #define PXA_DCSR_STOPSTATE	BIT(3)	/* Stop State (read-only) */
40 #define PXA_DCSR_ENDINTR	BIT(2)	/* End Interrupt (read / write) */
41 #define PXA_DCSR_STARTINTR	BIT(1)	/* Start Interrupt (read / write) */
42 #define PXA_DCSR_BUSERR		BIT(0)	/* Bus Error Interrupt (read / write) */
43 
44 #define PXA_DCSR_EORIRQEN	BIT(28)	/* End of Receive IRQ Enable (R/W) */
45 #define PXA_DCSR_EORJMPEN	BIT(27)	/* Jump to next descriptor on EOR */
46 #define PXA_DCSR_EORSTOPEN	BIT(26)	/* STOP on an EOR */
47 #define PXA_DCSR_SETCMPST	BIT(25)	/* Set Descriptor Compare Status */
48 #define PXA_DCSR_CLRCMPST	BIT(24)	/* Clear Descriptor Compare Status */
49 #define PXA_DCSR_CMPST		BIT(10)	/* The Descriptor Compare Status */
50 #define PXA_DCSR_EORINTR	BIT(9)	/* The end of Receive */
51 
52 #define DRCMR_MAPVLD	BIT(7)	/* Map Valid (read / write) */
53 #define DRCMR_CHLNUM	0x1f	/* mask for Channel Number (read / write) */
54 
55 #define DDADR_DESCADDR	0xfffffff0	/* Address of next descriptor (mask) */
56 #define DDADR_STOP	BIT(0)	/* Stop (read / write) */
57 
58 #define PXA_DCMD_INCSRCADDR	BIT(31)	/* Source Address Increment Setting. */
59 #define PXA_DCMD_INCTRGADDR	BIT(30)	/* Target Address Increment Setting. */
60 #define PXA_DCMD_FLOWSRC	BIT(29)	/* Flow Control by the source. */
61 #define PXA_DCMD_FLOWTRG	BIT(28)	/* Flow Control by the target. */
62 #define PXA_DCMD_STARTIRQEN	BIT(22)	/* Start Interrupt Enable */
63 #define PXA_DCMD_ENDIRQEN	BIT(21)	/* End Interrupt Enable */
64 #define PXA_DCMD_ENDIAN		BIT(18)	/* Device Endian-ness. */
65 #define PXA_DCMD_BURST8		(1 << 16)	/* 8 byte burst */
66 #define PXA_DCMD_BURST16	(2 << 16)	/* 16 byte burst */
67 #define PXA_DCMD_BURST32	(3 << 16)	/* 32 byte burst */
68 #define PXA_DCMD_WIDTH1		(1 << 14)	/* 1 byte width */
69 #define PXA_DCMD_WIDTH2		(2 << 14)	/* 2 byte width (HalfWord) */
70 #define PXA_DCMD_WIDTH4		(3 << 14)	/* 4 byte width (Word) */
71 #define PXA_DCMD_LENGTH		0x01fff		/* length mask (max = 8K - 1) */
72 
73 #define PDMA_ALIGNMENT		3
74 #define PDMA_MAX_DESC_BYTES	(PXA_DCMD_LENGTH & ~((1 << PDMA_ALIGNMENT) - 1))
75 
76 struct pxad_desc_hw {
77 	u32 ddadr;	/* Points to the next descriptor + flags */
78 	u32 dsadr;	/* DSADR value for the current transfer */
79 	u32 dtadr;	/* DTADR value for the current transfer */
80 	u32 dcmd;	/* DCMD value for the current transfer */
81 } __aligned(16);
82 
83 struct pxad_desc_sw {
84 	struct virt_dma_desc	vd;		/* Virtual descriptor */
85 	int			nb_desc;	/* Number of hw. descriptors */
86 	size_t			len;		/* Number of bytes xfered */
87 	dma_addr_t		first;		/* First descriptor's addr */
88 
89 	/* At least one descriptor has an src/dst address not multiple of 8 */
90 	bool			misaligned;
91 	bool			cyclic;
92 	struct dma_pool		*desc_pool;	/* Channel's used allocator */
93 
94 	struct pxad_desc_hw	*hw_desc[];	/* DMA coherent descriptors */
95 };
96 
97 struct pxad_phy {
98 	int			idx;
99 	void __iomem		*base;
100 	struct pxad_chan	*vchan;
101 };
102 
103 struct pxad_chan {
104 	struct virt_dma_chan	vc;		/* Virtual channel */
105 	u32			drcmr;		/* Requestor of the channel */
106 	enum pxad_chan_prio	prio;		/* Required priority of phy */
107 	/*
108 	 * At least one desc_sw in submitted or issued transfers on this channel
109 	 * has one address such as: addr % 8 != 0. This implies the DALGN
110 	 * setting on the phy.
111 	 */
112 	bool			misaligned;
113 	struct dma_slave_config	cfg;		/* Runtime config */
114 
115 	/* protected by vc->lock */
116 	struct pxad_phy		*phy;
117 	struct dma_pool		*desc_pool;	/* Descriptors pool */
118 	dma_cookie_t		bus_error;
119 
120 	wait_queue_head_t	wq_state;
121 };
122 
123 struct pxad_device {
124 	struct dma_device		slave;
125 	int				nr_chans;
126 	int				nr_requestors;
127 	void __iomem			*base;
128 	struct pxad_phy			*phys;
129 	spinlock_t			phy_lock;	/* Phy association */
130 #ifdef CONFIG_DEBUG_FS
131 	struct dentry			*dbgfs_root;
132 	struct dentry			**dbgfs_chan;
133 #endif
134 };
135 
136 #define tx_to_pxad_desc(tx)					\
137 	container_of(tx, struct pxad_desc_sw, async_tx)
138 #define to_pxad_chan(dchan)					\
139 	container_of(dchan, struct pxad_chan, vc.chan)
140 #define to_pxad_dev(dmadev)					\
141 	container_of(dmadev, struct pxad_device, slave)
142 #define to_pxad_sw_desc(_vd)				\
143 	container_of((_vd), struct pxad_desc_sw, vd)
144 
145 #define _phy_readl_relaxed(phy, _reg)					\
146 	readl_relaxed((phy)->base + _reg((phy)->idx))
147 #define phy_readl_relaxed(phy, _reg)					\
148 	({								\
149 		u32 _v;							\
150 		_v = readl_relaxed((phy)->base + _reg((phy)->idx));	\
151 		dev_vdbg(&phy->vchan->vc.chan.dev->device,		\
152 			 "%s(): readl(%s): 0x%08x\n", __func__, #_reg,	\
153 			  _v);						\
154 		_v;							\
155 	})
156 #define phy_writel(phy, val, _reg)					\
157 	do {								\
158 		writel((val), (phy)->base + _reg((phy)->idx));		\
159 		dev_vdbg(&phy->vchan->vc.chan.dev->device,		\
160 			 "%s(): writel(0x%08x, %s)\n",			\
161 			 __func__, (u32)(val), #_reg);			\
162 	} while (0)
163 #define phy_writel_relaxed(phy, val, _reg)				\
164 	do {								\
165 		writel_relaxed((val), (phy)->base + _reg((phy)->idx));	\
166 		dev_vdbg(&phy->vchan->vc.chan.dev->device,		\
167 			 "%s(): writel_relaxed(0x%08x, %s)\n",		\
168 			 __func__, (u32)(val), #_reg);			\
169 	} while (0)
170 
171 static unsigned int pxad_drcmr(unsigned int line)
172 {
173 	if (line < 64)
174 		return 0x100 + line * 4;
175 	return 0x1000 + line * 4;
176 }
177 
178 static bool pxad_filter_fn(struct dma_chan *chan, void *param);
179 
180 /*
181  * Debug fs
182  */
183 #ifdef CONFIG_DEBUG_FS
184 #include <linux/debugfs.h>
185 #include <linux/uaccess.h>
186 #include <linux/seq_file.h>
187 
188 static int requester_chan_show(struct seq_file *s, void *p)
189 {
190 	struct pxad_phy *phy = s->private;
191 	int i;
192 	u32 drcmr;
193 
194 	seq_printf(s, "DMA channel %d requester :\n", phy->idx);
195 	for (i = 0; i < 70; i++) {
196 		drcmr = readl_relaxed(phy->base + pxad_drcmr(i));
197 		if ((drcmr & DRCMR_CHLNUM) == phy->idx)
198 			seq_printf(s, "\tRequester %d (MAPVLD=%d)\n", i,
199 				   !!(drcmr & DRCMR_MAPVLD));
200 	}
201 	return 0;
202 }
203 
204 static inline int dbg_burst_from_dcmd(u32 dcmd)
205 {
206 	int burst = (dcmd >> 16) & 0x3;
207 
208 	return burst ? 4 << burst : 0;
209 }
210 
211 static int is_phys_valid(unsigned long addr)
212 {
213 	return pfn_valid(__phys_to_pfn(addr));
214 }
215 
216 #define PXA_DCSR_STR(flag) (dcsr & PXA_DCSR_##flag ? #flag" " : "")
217 #define PXA_DCMD_STR(flag) (dcmd & PXA_DCMD_##flag ? #flag" " : "")
218 
219 static int descriptors_show(struct seq_file *s, void *p)
220 {
221 	struct pxad_phy *phy = s->private;
222 	int i, max_show = 20, burst, width;
223 	u32 dcmd;
224 	unsigned long phys_desc, ddadr;
225 	struct pxad_desc_hw *desc;
226 
227 	phys_desc = ddadr = _phy_readl_relaxed(phy, DDADR);
228 
229 	seq_printf(s, "DMA channel %d descriptors :\n", phy->idx);
230 	seq_printf(s, "[%03d] First descriptor unknown\n", 0);
231 	for (i = 1; i < max_show && is_phys_valid(phys_desc); i++) {
232 		desc = phys_to_virt(phys_desc);
233 		dcmd = desc->dcmd;
234 		burst = dbg_burst_from_dcmd(dcmd);
235 		width = (1 << ((dcmd >> 14) & 0x3)) >> 1;
236 
237 		seq_printf(s, "[%03d] Desc at %08lx(virt %p)\n",
238 			   i, phys_desc, desc);
239 		seq_printf(s, "\tDDADR = %08x\n", desc->ddadr);
240 		seq_printf(s, "\tDSADR = %08x\n", desc->dsadr);
241 		seq_printf(s, "\tDTADR = %08x\n", desc->dtadr);
242 		seq_printf(s, "\tDCMD  = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",
243 			   dcmd,
244 			   PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR),
245 			   PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG),
246 			   PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN),
247 			   PXA_DCMD_STR(ENDIAN), burst, width,
248 			   dcmd & PXA_DCMD_LENGTH);
249 		phys_desc = desc->ddadr;
250 	}
251 	if (i == max_show)
252 		seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n",
253 			   i, phys_desc);
254 	else
255 		seq_printf(s, "[%03d] Desc at %08lx is %s\n",
256 			   i, phys_desc, phys_desc == DDADR_STOP ?
257 			   "DDADR_STOP" : "invalid");
258 
259 	return 0;
260 }
261 
262 static int chan_state_show(struct seq_file *s, void *p)
263 {
264 	struct pxad_phy *phy = s->private;
265 	u32 dcsr, dcmd;
266 	int burst, width;
267 	static const char * const str_prio[] = {
268 		"high", "normal", "low", "invalid"
269 	};
270 
271 	dcsr = _phy_readl_relaxed(phy, DCSR);
272 	dcmd = _phy_readl_relaxed(phy, DCMD);
273 	burst = dbg_burst_from_dcmd(dcmd);
274 	width = (1 << ((dcmd >> 14) & 0x3)) >> 1;
275 
276 	seq_printf(s, "DMA channel %d\n", phy->idx);
277 	seq_printf(s, "\tPriority : %s\n",
278 			  str_prio[(phy->idx & 0xf) / 4]);
279 	seq_printf(s, "\tUnaligned transfer bit: %s\n",
280 			  _phy_readl_relaxed(phy, DALGN) & BIT(phy->idx) ?
281 			  "yes" : "no");
282 	seq_printf(s, "\tDCSR  = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
283 		   dcsr, PXA_DCSR_STR(RUN), PXA_DCSR_STR(NODESC),
284 		   PXA_DCSR_STR(STOPIRQEN), PXA_DCSR_STR(EORIRQEN),
285 		   PXA_DCSR_STR(EORJMPEN), PXA_DCSR_STR(EORSTOPEN),
286 		   PXA_DCSR_STR(SETCMPST), PXA_DCSR_STR(CLRCMPST),
287 		   PXA_DCSR_STR(CMPST), PXA_DCSR_STR(EORINTR),
288 		   PXA_DCSR_STR(REQPEND), PXA_DCSR_STR(STOPSTATE),
289 		   PXA_DCSR_STR(ENDINTR), PXA_DCSR_STR(STARTINTR),
290 		   PXA_DCSR_STR(BUSERR));
291 
292 	seq_printf(s, "\tDCMD  = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n",
293 		   dcmd,
294 		   PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR),
295 		   PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG),
296 		   PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN),
297 		   PXA_DCMD_STR(ENDIAN), burst, width, dcmd & PXA_DCMD_LENGTH);
298 	seq_printf(s, "\tDSADR = %08x\n", _phy_readl_relaxed(phy, DSADR));
299 	seq_printf(s, "\tDTADR = %08x\n", _phy_readl_relaxed(phy, DTADR));
300 	seq_printf(s, "\tDDADR = %08x\n", _phy_readl_relaxed(phy, DDADR));
301 
302 	return 0;
303 }
304 
305 static int state_show(struct seq_file *s, void *p)
306 {
307 	struct pxad_device *pdev = s->private;
308 
309 	/* basic device status */
310 	seq_puts(s, "DMA engine status\n");
311 	seq_printf(s, "\tChannel number: %d\n", pdev->nr_chans);
312 
313 	return 0;
314 }
315 
316 DEFINE_SHOW_ATTRIBUTE(state);
317 DEFINE_SHOW_ATTRIBUTE(chan_state);
318 DEFINE_SHOW_ATTRIBUTE(descriptors);
319 DEFINE_SHOW_ATTRIBUTE(requester_chan);
320 
321 static struct dentry *pxad_dbg_alloc_chan(struct pxad_device *pdev,
322 					     int ch, struct dentry *chandir)
323 {
324 	char chan_name[11];
325 	struct dentry *chan;
326 	void *dt;
327 
328 	scnprintf(chan_name, sizeof(chan_name), "%d", ch);
329 	chan = debugfs_create_dir(chan_name, chandir);
330 	dt = (void *)&pdev->phys[ch];
331 
332 	debugfs_create_file("state", 0400, chan, dt, &chan_state_fops);
333 	debugfs_create_file("descriptors", 0400, chan, dt, &descriptors_fops);
334 	debugfs_create_file("requesters", 0400, chan, dt, &requester_chan_fops);
335 
336 	return chan;
337 }
338 
339 static void pxad_init_debugfs(struct pxad_device *pdev)
340 {
341 	int i;
342 	struct dentry *chandir;
343 
344 	pdev->dbgfs_chan =
345 		kmalloc_array(pdev->nr_chans, sizeof(struct dentry *),
346 			      GFP_KERNEL);
347 	if (!pdev->dbgfs_chan)
348 		return;
349 
350 	pdev->dbgfs_root = debugfs_create_dir(dev_name(pdev->slave.dev), NULL);
351 
352 	debugfs_create_file("state", 0400, pdev->dbgfs_root, pdev, &state_fops);
353 
354 	chandir = debugfs_create_dir("channels", pdev->dbgfs_root);
355 
356 	for (i = 0; i < pdev->nr_chans; i++)
357 		pdev->dbgfs_chan[i] = pxad_dbg_alloc_chan(pdev, i, chandir);
358 }
359 
360 static void pxad_cleanup_debugfs(struct pxad_device *pdev)
361 {
362 	debugfs_remove_recursive(pdev->dbgfs_root);
363 }
364 #else
365 static inline void pxad_init_debugfs(struct pxad_device *pdev) {}
366 static inline void pxad_cleanup_debugfs(struct pxad_device *pdev) {}
367 #endif
368 
369 static struct pxad_phy *lookup_phy(struct pxad_chan *pchan)
370 {
371 	int prio, i;
372 	struct pxad_device *pdev = to_pxad_dev(pchan->vc.chan.device);
373 	struct pxad_phy *phy, *found = NULL;
374 	unsigned long flags;
375 
376 	/*
377 	 * dma channel priorities
378 	 * ch 0 - 3,  16 - 19  <--> (0)
379 	 * ch 4 - 7,  20 - 23  <--> (1)
380 	 * ch 8 - 11, 24 - 27  <--> (2)
381 	 * ch 12 - 15, 28 - 31  <--> (3)
382 	 */
383 
384 	spin_lock_irqsave(&pdev->phy_lock, flags);
385 	for (prio = pchan->prio; prio >= PXAD_PRIO_HIGHEST; prio--) {
386 		for (i = 0; i < pdev->nr_chans; i++) {
387 			if (prio != (i & 0xf) >> 2)
388 				continue;
389 			phy = &pdev->phys[i];
390 			if (!phy->vchan) {
391 				phy->vchan = pchan;
392 				found = phy;
393 				goto out_unlock;
394 			}
395 		}
396 	}
397 
398 out_unlock:
399 	spin_unlock_irqrestore(&pdev->phy_lock, flags);
400 	dev_dbg(&pchan->vc.chan.dev->device,
401 		"%s(): phy=%p(%d)\n", __func__, found,
402 		found ? found->idx : -1);
403 
404 	return found;
405 }
406 
407 static void pxad_free_phy(struct pxad_chan *chan)
408 {
409 	struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);
410 	unsigned long flags;
411 	u32 reg;
412 
413 	dev_dbg(&chan->vc.chan.dev->device,
414 		"%s(): freeing\n", __func__);
415 	if (!chan->phy)
416 		return;
417 
418 	/* clear the channel mapping in DRCMR */
419 	if (chan->drcmr <= pdev->nr_requestors) {
420 		reg = pxad_drcmr(chan->drcmr);
421 		writel_relaxed(0, chan->phy->base + reg);
422 	}
423 
424 	spin_lock_irqsave(&pdev->phy_lock, flags);
425 	chan->phy->vchan = NULL;
426 	chan->phy = NULL;
427 	spin_unlock_irqrestore(&pdev->phy_lock, flags);
428 }
429 
430 static bool is_chan_running(struct pxad_chan *chan)
431 {
432 	u32 dcsr;
433 	struct pxad_phy *phy = chan->phy;
434 
435 	if (!phy)
436 		return false;
437 	dcsr = phy_readl_relaxed(phy, DCSR);
438 	return dcsr & PXA_DCSR_RUN;
439 }
440 
441 static bool is_running_chan_misaligned(struct pxad_chan *chan)
442 {
443 	u32 dalgn;
444 
445 	BUG_ON(!chan->phy);
446 	dalgn = phy_readl_relaxed(chan->phy, DALGN);
447 	return dalgn & (BIT(chan->phy->idx));
448 }
449 
450 static void phy_enable(struct pxad_phy *phy, bool misaligned)
451 {
452 	struct pxad_device *pdev;
453 	u32 reg, dalgn;
454 
455 	if (!phy->vchan)
456 		return;
457 
458 	dev_dbg(&phy->vchan->vc.chan.dev->device,
459 		"%s(); phy=%p(%d) misaligned=%d\n", __func__,
460 		phy, phy->idx, misaligned);
461 
462 	pdev = to_pxad_dev(phy->vchan->vc.chan.device);
463 	if (phy->vchan->drcmr <= pdev->nr_requestors) {
464 		reg = pxad_drcmr(phy->vchan->drcmr);
465 		writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg);
466 	}
467 
468 	dalgn = phy_readl_relaxed(phy, DALGN);
469 	if (misaligned)
470 		dalgn |= BIT(phy->idx);
471 	else
472 		dalgn &= ~BIT(phy->idx);
473 	phy_writel_relaxed(phy, dalgn, DALGN);
474 
475 	phy_writel(phy, PXA_DCSR_STOPIRQEN | PXA_DCSR_ENDINTR |
476 		   PXA_DCSR_BUSERR | PXA_DCSR_RUN, DCSR);
477 }
478 
479 static void phy_disable(struct pxad_phy *phy)
480 {
481 	u32 dcsr;
482 
483 	if (!phy)
484 		return;
485 
486 	dcsr = phy_readl_relaxed(phy, DCSR);
487 	dev_dbg(&phy->vchan->vc.chan.dev->device,
488 		"%s(): phy=%p(%d)\n", __func__, phy, phy->idx);
489 	phy_writel(phy, dcsr & ~PXA_DCSR_RUN & ~PXA_DCSR_STOPIRQEN, DCSR);
490 }
491 
492 static void pxad_launch_chan(struct pxad_chan *chan,
493 				 struct pxad_desc_sw *desc)
494 {
495 	dev_dbg(&chan->vc.chan.dev->device,
496 		"%s(): desc=%p\n", __func__, desc);
497 	if (!chan->phy) {
498 		chan->phy = lookup_phy(chan);
499 		if (!chan->phy) {
500 			dev_dbg(&chan->vc.chan.dev->device,
501 				"%s(): no free dma channel\n", __func__);
502 			return;
503 		}
504 	}
505 	chan->bus_error = 0;
506 
507 	/*
508 	 * Program the descriptor's address into the DMA controller,
509 	 * then start the DMA transaction
510 	 */
511 	phy_writel(chan->phy, desc->first, DDADR);
512 	phy_enable(chan->phy, chan->misaligned);
513 	wake_up(&chan->wq_state);
514 }
515 
516 static void set_updater_desc(struct pxad_desc_sw *sw_desc,
517 			     unsigned long flags)
518 {
519 	struct pxad_desc_hw *updater =
520 		sw_desc->hw_desc[sw_desc->nb_desc - 1];
521 	dma_addr_t dma = sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr;
522 
523 	updater->ddadr = DDADR_STOP;
524 	updater->dsadr = dma;
525 	updater->dtadr = dma + 8;
526 	updater->dcmd = PXA_DCMD_WIDTH4 | PXA_DCMD_BURST32 |
527 		(PXA_DCMD_LENGTH & sizeof(u32));
528 	if (flags & DMA_PREP_INTERRUPT)
529 		updater->dcmd |= PXA_DCMD_ENDIRQEN;
530 	if (sw_desc->cyclic)
531 		sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr = sw_desc->first;
532 }
533 
534 static bool is_desc_completed(struct virt_dma_desc *vd)
535 {
536 	struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd);
537 	struct pxad_desc_hw *updater =
538 		sw_desc->hw_desc[sw_desc->nb_desc - 1];
539 
540 	return updater->dtadr != (updater->dsadr + 8);
541 }
542 
543 static void pxad_desc_chain(struct virt_dma_desc *vd1,
544 				struct virt_dma_desc *vd2)
545 {
546 	struct pxad_desc_sw *desc1 = to_pxad_sw_desc(vd1);
547 	struct pxad_desc_sw *desc2 = to_pxad_sw_desc(vd2);
548 	dma_addr_t dma_to_chain;
549 
550 	dma_to_chain = desc2->first;
551 	desc1->hw_desc[desc1->nb_desc - 1]->ddadr = dma_to_chain;
552 }
553 
554 static bool pxad_try_hotchain(struct virt_dma_chan *vc,
555 				  struct virt_dma_desc *vd)
556 {
557 	struct virt_dma_desc *vd_last_issued = NULL;
558 	struct pxad_chan *chan = to_pxad_chan(&vc->chan);
559 
560 	/*
561 	 * Attempt to hot chain the tx if the phy is still running. This is
562 	 * considered successful only if either the channel is still running
563 	 * after the chaining, or if the chained transfer is completed after
564 	 * having been hot chained.
565 	 * A change of alignment is not allowed, and forbids hotchaining.
566 	 */
567 	if (is_chan_running(chan)) {
568 		BUG_ON(list_empty(&vc->desc_issued));
569 
570 		if (!is_running_chan_misaligned(chan) &&
571 		    to_pxad_sw_desc(vd)->misaligned)
572 			return false;
573 
574 		vd_last_issued = list_entry(vc->desc_issued.prev,
575 					    struct virt_dma_desc, node);
576 		pxad_desc_chain(vd_last_issued, vd);
577 		if (is_chan_running(chan) || is_desc_completed(vd))
578 			return true;
579 	}
580 
581 	return false;
582 }
583 
584 static unsigned int clear_chan_irq(struct pxad_phy *phy)
585 {
586 	u32 dcsr;
587 	u32 dint = readl(phy->base + DINT);
588 
589 	if (!(dint & BIT(phy->idx)))
590 		return PXA_DCSR_RUN;
591 
592 	/* clear irq */
593 	dcsr = phy_readl_relaxed(phy, DCSR);
594 	phy_writel(phy, dcsr, DCSR);
595 	if ((dcsr & PXA_DCSR_BUSERR) && (phy->vchan))
596 		dev_warn(&phy->vchan->vc.chan.dev->device,
597 			 "%s(chan=%p): PXA_DCSR_BUSERR\n",
598 			 __func__, &phy->vchan);
599 
600 	return dcsr & ~PXA_DCSR_RUN;
601 }
602 
603 static irqreturn_t pxad_chan_handler(int irq, void *dev_id)
604 {
605 	struct pxad_phy *phy = dev_id;
606 	struct pxad_chan *chan = phy->vchan;
607 	struct virt_dma_desc *vd, *tmp;
608 	unsigned int dcsr;
609 	unsigned long flags;
610 	bool vd_completed;
611 	dma_cookie_t last_started = 0;
612 
613 	BUG_ON(!chan);
614 
615 	dcsr = clear_chan_irq(phy);
616 	if (dcsr & PXA_DCSR_RUN)
617 		return IRQ_NONE;
618 
619 	spin_lock_irqsave(&chan->vc.lock, flags);
620 	list_for_each_entry_safe(vd, tmp, &chan->vc.desc_issued, node) {
621 		vd_completed = is_desc_completed(vd);
622 		dev_dbg(&chan->vc.chan.dev->device,
623 			"%s(): checking txd %p[%x]: completed=%d dcsr=0x%x\n",
624 			__func__, vd, vd->tx.cookie, vd_completed,
625 			dcsr);
626 		last_started = vd->tx.cookie;
627 		if (to_pxad_sw_desc(vd)->cyclic) {
628 			vchan_cyclic_callback(vd);
629 			break;
630 		}
631 		if (vd_completed) {
632 			list_del(&vd->node);
633 			vchan_cookie_complete(vd);
634 		} else {
635 			break;
636 		}
637 	}
638 
639 	if (dcsr & PXA_DCSR_BUSERR) {
640 		chan->bus_error = last_started;
641 		phy_disable(phy);
642 	}
643 
644 	if (!chan->bus_error && dcsr & PXA_DCSR_STOPSTATE) {
645 		dev_dbg(&chan->vc.chan.dev->device,
646 		"%s(): channel stopped, submitted_empty=%d issued_empty=%d",
647 			__func__,
648 			list_empty(&chan->vc.desc_submitted),
649 			list_empty(&chan->vc.desc_issued));
650 		phy_writel_relaxed(phy, dcsr & ~PXA_DCSR_STOPIRQEN, DCSR);
651 
652 		if (list_empty(&chan->vc.desc_issued)) {
653 			chan->misaligned =
654 				!list_empty(&chan->vc.desc_submitted);
655 		} else {
656 			vd = list_first_entry(&chan->vc.desc_issued,
657 					      struct virt_dma_desc, node);
658 			pxad_launch_chan(chan, to_pxad_sw_desc(vd));
659 		}
660 	}
661 	spin_unlock_irqrestore(&chan->vc.lock, flags);
662 	wake_up(&chan->wq_state);
663 
664 	return IRQ_HANDLED;
665 }
666 
667 static irqreturn_t pxad_int_handler(int irq, void *dev_id)
668 {
669 	struct pxad_device *pdev = dev_id;
670 	struct pxad_phy *phy;
671 	u32 dint = readl(pdev->base + DINT);
672 	int i, ret = IRQ_NONE;
673 
674 	while (dint) {
675 		i = __ffs(dint);
676 		dint &= (dint - 1);
677 		phy = &pdev->phys[i];
678 		if (pxad_chan_handler(irq, phy) == IRQ_HANDLED)
679 			ret = IRQ_HANDLED;
680 	}
681 
682 	return ret;
683 }
684 
685 static int pxad_alloc_chan_resources(struct dma_chan *dchan)
686 {
687 	struct pxad_chan *chan = to_pxad_chan(dchan);
688 	struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);
689 
690 	if (chan->desc_pool)
691 		return 1;
692 
693 	chan->desc_pool = dma_pool_create(dma_chan_name(dchan),
694 					  pdev->slave.dev,
695 					  sizeof(struct pxad_desc_hw),
696 					  __alignof__(struct pxad_desc_hw),
697 					  0);
698 	if (!chan->desc_pool) {
699 		dev_err(&chan->vc.chan.dev->device,
700 			"%s(): unable to allocate descriptor pool\n",
701 			__func__);
702 		return -ENOMEM;
703 	}
704 
705 	return 1;
706 }
707 
708 static void pxad_free_chan_resources(struct dma_chan *dchan)
709 {
710 	struct pxad_chan *chan = to_pxad_chan(dchan);
711 
712 	vchan_free_chan_resources(&chan->vc);
713 	dma_pool_destroy(chan->desc_pool);
714 	chan->desc_pool = NULL;
715 
716 	chan->drcmr = U32_MAX;
717 	chan->prio = PXAD_PRIO_LOWEST;
718 }
719 
720 static void pxad_free_desc(struct virt_dma_desc *vd)
721 {
722 	int i;
723 	dma_addr_t dma;
724 	struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd);
725 
726 	BUG_ON(sw_desc->nb_desc == 0);
727 	for (i = sw_desc->nb_desc - 1; i >= 0; i--) {
728 		if (i > 0)
729 			dma = sw_desc->hw_desc[i - 1]->ddadr;
730 		else
731 			dma = sw_desc->first;
732 		dma_pool_free(sw_desc->desc_pool,
733 			      sw_desc->hw_desc[i], dma);
734 	}
735 	sw_desc->nb_desc = 0;
736 	kfree(sw_desc);
737 }
738 
739 static struct pxad_desc_sw *
740 pxad_alloc_desc(struct pxad_chan *chan, unsigned int nb_hw_desc)
741 {
742 	struct pxad_desc_sw *sw_desc;
743 	dma_addr_t dma;
744 	int i;
745 
746 	sw_desc = kzalloc(sizeof(*sw_desc) +
747 			  nb_hw_desc * sizeof(struct pxad_desc_hw *),
748 			  GFP_NOWAIT);
749 	if (!sw_desc)
750 		return NULL;
751 	sw_desc->desc_pool = chan->desc_pool;
752 
753 	for (i = 0; i < nb_hw_desc; i++) {
754 		sw_desc->hw_desc[i] = dma_pool_alloc(sw_desc->desc_pool,
755 						     GFP_NOWAIT, &dma);
756 		if (!sw_desc->hw_desc[i]) {
757 			dev_err(&chan->vc.chan.dev->device,
758 				"%s(): Couldn't allocate the %dth hw_desc from dma_pool %p\n",
759 				__func__, i, sw_desc->desc_pool);
760 			goto err;
761 		}
762 
763 		if (i == 0)
764 			sw_desc->first = dma;
765 		else
766 			sw_desc->hw_desc[i - 1]->ddadr = dma;
767 		sw_desc->nb_desc++;
768 	}
769 
770 	return sw_desc;
771 err:
772 	pxad_free_desc(&sw_desc->vd);
773 	return NULL;
774 }
775 
776 static dma_cookie_t pxad_tx_submit(struct dma_async_tx_descriptor *tx)
777 {
778 	struct virt_dma_chan *vc = to_virt_chan(tx->chan);
779 	struct pxad_chan *chan = to_pxad_chan(&vc->chan);
780 	struct virt_dma_desc *vd_chained = NULL,
781 		*vd = container_of(tx, struct virt_dma_desc, tx);
782 	dma_cookie_t cookie;
783 	unsigned long flags;
784 
785 	set_updater_desc(to_pxad_sw_desc(vd), tx->flags);
786 
787 	spin_lock_irqsave(&vc->lock, flags);
788 	cookie = dma_cookie_assign(tx);
789 
790 	if (list_empty(&vc->desc_submitted) && pxad_try_hotchain(vc, vd)) {
791 		list_move_tail(&vd->node, &vc->desc_issued);
792 		dev_dbg(&chan->vc.chan.dev->device,
793 			"%s(): txd %p[%x]: submitted (hot linked)\n",
794 			__func__, vd, cookie);
795 		goto out;
796 	}
797 
798 	/*
799 	 * Fallback to placing the tx in the submitted queue
800 	 */
801 	if (!list_empty(&vc->desc_submitted)) {
802 		vd_chained = list_entry(vc->desc_submitted.prev,
803 					struct virt_dma_desc, node);
804 		/*
805 		 * Only chain the descriptors if no new misalignment is
806 		 * introduced. If a new misalignment is chained, let the channel
807 		 * stop, and be relaunched in misalign mode from the irq
808 		 * handler.
809 		 */
810 		if (chan->misaligned || !to_pxad_sw_desc(vd)->misaligned)
811 			pxad_desc_chain(vd_chained, vd);
812 		else
813 			vd_chained = NULL;
814 	}
815 	dev_dbg(&chan->vc.chan.dev->device,
816 		"%s(): txd %p[%x]: submitted (%s linked)\n",
817 		__func__, vd, cookie, vd_chained ? "cold" : "not");
818 	list_move_tail(&vd->node, &vc->desc_submitted);
819 	chan->misaligned |= to_pxad_sw_desc(vd)->misaligned;
820 
821 out:
822 	spin_unlock_irqrestore(&vc->lock, flags);
823 	return cookie;
824 }
825 
826 static void pxad_issue_pending(struct dma_chan *dchan)
827 {
828 	struct pxad_chan *chan = to_pxad_chan(dchan);
829 	struct virt_dma_desc *vd_first;
830 	unsigned long flags;
831 
832 	spin_lock_irqsave(&chan->vc.lock, flags);
833 	if (list_empty(&chan->vc.desc_submitted))
834 		goto out;
835 
836 	vd_first = list_first_entry(&chan->vc.desc_submitted,
837 				    struct virt_dma_desc, node);
838 	dev_dbg(&chan->vc.chan.dev->device,
839 		"%s(): txd %p[%x]", __func__, vd_first, vd_first->tx.cookie);
840 
841 	vchan_issue_pending(&chan->vc);
842 	if (!pxad_try_hotchain(&chan->vc, vd_first))
843 		pxad_launch_chan(chan, to_pxad_sw_desc(vd_first));
844 out:
845 	spin_unlock_irqrestore(&chan->vc.lock, flags);
846 }
847 
848 static inline struct dma_async_tx_descriptor *
849 pxad_tx_prep(struct virt_dma_chan *vc, struct virt_dma_desc *vd,
850 		 unsigned long tx_flags)
851 {
852 	struct dma_async_tx_descriptor *tx;
853 	struct pxad_chan *chan = container_of(vc, struct pxad_chan, vc);
854 
855 	INIT_LIST_HEAD(&vd->node);
856 	tx = vchan_tx_prep(vc, vd, tx_flags);
857 	tx->tx_submit = pxad_tx_submit;
858 	dev_dbg(&chan->vc.chan.dev->device,
859 		"%s(): vc=%p txd=%p[%x] flags=0x%lx\n", __func__,
860 		vc, vd, vd->tx.cookie,
861 		tx_flags);
862 
863 	return tx;
864 }
865 
866 static void pxad_get_config(struct pxad_chan *chan,
867 			    enum dma_transfer_direction dir,
868 			    u32 *dcmd, u32 *dev_src, u32 *dev_dst)
869 {
870 	u32 maxburst = 0, dev_addr = 0;
871 	enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
872 	struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);
873 
874 	*dcmd = 0;
875 	if (dir == DMA_DEV_TO_MEM) {
876 		maxburst = chan->cfg.src_maxburst;
877 		width = chan->cfg.src_addr_width;
878 		dev_addr = chan->cfg.src_addr;
879 		*dev_src = dev_addr;
880 		*dcmd |= PXA_DCMD_INCTRGADDR;
881 		if (chan->drcmr <= pdev->nr_requestors)
882 			*dcmd |= PXA_DCMD_FLOWSRC;
883 	}
884 	if (dir == DMA_MEM_TO_DEV) {
885 		maxburst = chan->cfg.dst_maxburst;
886 		width = chan->cfg.dst_addr_width;
887 		dev_addr = chan->cfg.dst_addr;
888 		*dev_dst = dev_addr;
889 		*dcmd |= PXA_DCMD_INCSRCADDR;
890 		if (chan->drcmr <= pdev->nr_requestors)
891 			*dcmd |= PXA_DCMD_FLOWTRG;
892 	}
893 	if (dir == DMA_MEM_TO_MEM)
894 		*dcmd |= PXA_DCMD_BURST32 | PXA_DCMD_INCTRGADDR |
895 			PXA_DCMD_INCSRCADDR;
896 
897 	dev_dbg(&chan->vc.chan.dev->device,
898 		"%s(): dev_addr=0x%x maxburst=%d width=%d  dir=%d\n",
899 		__func__, dev_addr, maxburst, width, dir);
900 
901 	if (width == DMA_SLAVE_BUSWIDTH_1_BYTE)
902 		*dcmd |= PXA_DCMD_WIDTH1;
903 	else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES)
904 		*dcmd |= PXA_DCMD_WIDTH2;
905 	else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES)
906 		*dcmd |= PXA_DCMD_WIDTH4;
907 
908 	if (maxburst == 8)
909 		*dcmd |= PXA_DCMD_BURST8;
910 	else if (maxburst == 16)
911 		*dcmd |= PXA_DCMD_BURST16;
912 	else if (maxburst == 32)
913 		*dcmd |= PXA_DCMD_BURST32;
914 
915 	/* FIXME: drivers should be ported over to use the filter
916 	 * function. Once that's done, the following two lines can
917 	 * be removed.
918 	 */
919 	if (chan->cfg.slave_id)
920 		chan->drcmr = chan->cfg.slave_id;
921 }
922 
923 static struct dma_async_tx_descriptor *
924 pxad_prep_memcpy(struct dma_chan *dchan,
925 		 dma_addr_t dma_dst, dma_addr_t dma_src,
926 		 size_t len, unsigned long flags)
927 {
928 	struct pxad_chan *chan = to_pxad_chan(dchan);
929 	struct pxad_desc_sw *sw_desc;
930 	struct pxad_desc_hw *hw_desc;
931 	u32 dcmd;
932 	unsigned int i, nb_desc = 0;
933 	size_t copy;
934 
935 	if (!dchan || !len)
936 		return NULL;
937 
938 	dev_dbg(&chan->vc.chan.dev->device,
939 		"%s(): dma_dst=0x%lx dma_src=0x%lx len=%zu flags=%lx\n",
940 		__func__, (unsigned long)dma_dst, (unsigned long)dma_src,
941 		len, flags);
942 	pxad_get_config(chan, DMA_MEM_TO_MEM, &dcmd, NULL, NULL);
943 
944 	nb_desc = DIV_ROUND_UP(len, PDMA_MAX_DESC_BYTES);
945 	sw_desc = pxad_alloc_desc(chan, nb_desc + 1);
946 	if (!sw_desc)
947 		return NULL;
948 	sw_desc->len = len;
949 
950 	if (!IS_ALIGNED(dma_src, 1 << PDMA_ALIGNMENT) ||
951 	    !IS_ALIGNED(dma_dst, 1 << PDMA_ALIGNMENT))
952 		sw_desc->misaligned = true;
953 
954 	i = 0;
955 	do {
956 		hw_desc = sw_desc->hw_desc[i++];
957 		copy = min_t(size_t, len, PDMA_MAX_DESC_BYTES);
958 		hw_desc->dcmd = dcmd | (PXA_DCMD_LENGTH & copy);
959 		hw_desc->dsadr = dma_src;
960 		hw_desc->dtadr = dma_dst;
961 		len -= copy;
962 		dma_src += copy;
963 		dma_dst += copy;
964 	} while (len);
965 	set_updater_desc(sw_desc, flags);
966 
967 	return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);
968 }
969 
970 static struct dma_async_tx_descriptor *
971 pxad_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
972 		   unsigned int sg_len, enum dma_transfer_direction dir,
973 		   unsigned long flags, void *context)
974 {
975 	struct pxad_chan *chan = to_pxad_chan(dchan);
976 	struct pxad_desc_sw *sw_desc;
977 	size_t len, avail;
978 	struct scatterlist *sg;
979 	dma_addr_t dma;
980 	u32 dcmd, dsadr = 0, dtadr = 0;
981 	unsigned int nb_desc = 0, i, j = 0;
982 
983 	if ((sgl == NULL) || (sg_len == 0))
984 		return NULL;
985 
986 	pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr);
987 	dev_dbg(&chan->vc.chan.dev->device,
988 		"%s(): dir=%d flags=%lx\n", __func__, dir, flags);
989 
990 	for_each_sg(sgl, sg, sg_len, i)
991 		nb_desc += DIV_ROUND_UP(sg_dma_len(sg), PDMA_MAX_DESC_BYTES);
992 	sw_desc = pxad_alloc_desc(chan, nb_desc + 1);
993 	if (!sw_desc)
994 		return NULL;
995 
996 	for_each_sg(sgl, sg, sg_len, i) {
997 		dma = sg_dma_address(sg);
998 		avail = sg_dma_len(sg);
999 		sw_desc->len += avail;
1000 
1001 		do {
1002 			len = min_t(size_t, avail, PDMA_MAX_DESC_BYTES);
1003 			if (dma & 0x7)
1004 				sw_desc->misaligned = true;
1005 
1006 			sw_desc->hw_desc[j]->dcmd =
1007 				dcmd | (PXA_DCMD_LENGTH & len);
1008 			sw_desc->hw_desc[j]->dsadr = dsadr ? dsadr : dma;
1009 			sw_desc->hw_desc[j++]->dtadr = dtadr ? dtadr : dma;
1010 
1011 			dma += len;
1012 			avail -= len;
1013 		} while (avail);
1014 	}
1015 	set_updater_desc(sw_desc, flags);
1016 
1017 	return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);
1018 }
1019 
1020 static struct dma_async_tx_descriptor *
1021 pxad_prep_dma_cyclic(struct dma_chan *dchan,
1022 		     dma_addr_t buf_addr, size_t len, size_t period_len,
1023 		     enum dma_transfer_direction dir, unsigned long flags)
1024 {
1025 	struct pxad_chan *chan = to_pxad_chan(dchan);
1026 	struct pxad_desc_sw *sw_desc;
1027 	struct pxad_desc_hw **phw_desc;
1028 	dma_addr_t dma;
1029 	u32 dcmd, dsadr = 0, dtadr = 0;
1030 	unsigned int nb_desc = 0;
1031 
1032 	if (!dchan || !len || !period_len)
1033 		return NULL;
1034 	if ((dir != DMA_DEV_TO_MEM) && (dir != DMA_MEM_TO_DEV)) {
1035 		dev_err(&chan->vc.chan.dev->device,
1036 			"Unsupported direction for cyclic DMA\n");
1037 		return NULL;
1038 	}
1039 	/* the buffer length must be a multiple of period_len */
1040 	if (len % period_len != 0 || period_len > PDMA_MAX_DESC_BYTES ||
1041 	    !IS_ALIGNED(period_len, 1 << PDMA_ALIGNMENT))
1042 		return NULL;
1043 
1044 	pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr);
1045 	dcmd |= PXA_DCMD_ENDIRQEN | (PXA_DCMD_LENGTH & period_len);
1046 	dev_dbg(&chan->vc.chan.dev->device,
1047 		"%s(): buf_addr=0x%lx len=%zu period=%zu dir=%d flags=%lx\n",
1048 		__func__, (unsigned long)buf_addr, len, period_len, dir, flags);
1049 
1050 	nb_desc = DIV_ROUND_UP(period_len, PDMA_MAX_DESC_BYTES);
1051 	nb_desc *= DIV_ROUND_UP(len, period_len);
1052 	sw_desc = pxad_alloc_desc(chan, nb_desc + 1);
1053 	if (!sw_desc)
1054 		return NULL;
1055 	sw_desc->cyclic = true;
1056 	sw_desc->len = len;
1057 
1058 	phw_desc = sw_desc->hw_desc;
1059 	dma = buf_addr;
1060 	do {
1061 		phw_desc[0]->dsadr = dsadr ? dsadr : dma;
1062 		phw_desc[0]->dtadr = dtadr ? dtadr : dma;
1063 		phw_desc[0]->dcmd = dcmd;
1064 		phw_desc++;
1065 		dma += period_len;
1066 		len -= period_len;
1067 	} while (len);
1068 	set_updater_desc(sw_desc, flags);
1069 
1070 	return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags);
1071 }
1072 
1073 static int pxad_config(struct dma_chan *dchan,
1074 		       struct dma_slave_config *cfg)
1075 {
1076 	struct pxad_chan *chan = to_pxad_chan(dchan);
1077 
1078 	if (!dchan)
1079 		return -EINVAL;
1080 
1081 	chan->cfg = *cfg;
1082 	return 0;
1083 }
1084 
1085 static int pxad_terminate_all(struct dma_chan *dchan)
1086 {
1087 	struct pxad_chan *chan = to_pxad_chan(dchan);
1088 	struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device);
1089 	struct virt_dma_desc *vd = NULL;
1090 	unsigned long flags;
1091 	struct pxad_phy *phy;
1092 	LIST_HEAD(head);
1093 
1094 	dev_dbg(&chan->vc.chan.dev->device,
1095 		"%s(): vchan %p: terminate all\n", __func__, &chan->vc);
1096 
1097 	spin_lock_irqsave(&chan->vc.lock, flags);
1098 	vchan_get_all_descriptors(&chan->vc, &head);
1099 
1100 	list_for_each_entry(vd, &head, node) {
1101 		dev_dbg(&chan->vc.chan.dev->device,
1102 			"%s(): cancelling txd %p[%x] (completed=%d)", __func__,
1103 			vd, vd->tx.cookie, is_desc_completed(vd));
1104 	}
1105 
1106 	phy = chan->phy;
1107 	if (phy) {
1108 		phy_disable(chan->phy);
1109 		pxad_free_phy(chan);
1110 		chan->phy = NULL;
1111 		spin_lock(&pdev->phy_lock);
1112 		phy->vchan = NULL;
1113 		spin_unlock(&pdev->phy_lock);
1114 	}
1115 	spin_unlock_irqrestore(&chan->vc.lock, flags);
1116 	vchan_dma_desc_free_list(&chan->vc, &head);
1117 
1118 	return 0;
1119 }
1120 
1121 static unsigned int pxad_residue(struct pxad_chan *chan,
1122 				 dma_cookie_t cookie)
1123 {
1124 	struct virt_dma_desc *vd = NULL;
1125 	struct pxad_desc_sw *sw_desc = NULL;
1126 	struct pxad_desc_hw *hw_desc = NULL;
1127 	u32 curr, start, len, end, residue = 0;
1128 	unsigned long flags;
1129 	bool passed = false;
1130 	int i;
1131 
1132 	/*
1133 	 * If the channel does not have a phy pointer anymore, it has already
1134 	 * been completed. Therefore, its residue is 0.
1135 	 */
1136 	if (!chan->phy)
1137 		return 0;
1138 
1139 	spin_lock_irqsave(&chan->vc.lock, flags);
1140 
1141 	vd = vchan_find_desc(&chan->vc, cookie);
1142 	if (!vd)
1143 		goto out;
1144 
1145 	sw_desc = to_pxad_sw_desc(vd);
1146 	if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR)
1147 		curr = phy_readl_relaxed(chan->phy, DSADR);
1148 	else
1149 		curr = phy_readl_relaxed(chan->phy, DTADR);
1150 
1151 	/*
1152 	 * curr has to be actually read before checking descriptor
1153 	 * completion, so that a curr inside a status updater
1154 	 * descriptor implies the following test returns true, and
1155 	 * preventing reordering of curr load and the test.
1156 	 */
1157 	rmb();
1158 	if (is_desc_completed(vd))
1159 		goto out;
1160 
1161 	for (i = 0; i < sw_desc->nb_desc - 1; i++) {
1162 		hw_desc = sw_desc->hw_desc[i];
1163 		if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR)
1164 			start = hw_desc->dsadr;
1165 		else
1166 			start = hw_desc->dtadr;
1167 		len = hw_desc->dcmd & PXA_DCMD_LENGTH;
1168 		end = start + len;
1169 
1170 		/*
1171 		 * 'passed' will be latched once we found the descriptor
1172 		 * which lies inside the boundaries of the curr
1173 		 * pointer. All descriptors that occur in the list
1174 		 * _after_ we found that partially handled descriptor
1175 		 * are still to be processed and are hence added to the
1176 		 * residual bytes counter.
1177 		 */
1178 
1179 		if (passed) {
1180 			residue += len;
1181 		} else if (curr >= start && curr <= end) {
1182 			residue += end - curr;
1183 			passed = true;
1184 		}
1185 	}
1186 	if (!passed)
1187 		residue = sw_desc->len;
1188 
1189 out:
1190 	spin_unlock_irqrestore(&chan->vc.lock, flags);
1191 	dev_dbg(&chan->vc.chan.dev->device,
1192 		"%s(): txd %p[%x] sw_desc=%p: %d\n",
1193 		__func__, vd, cookie, sw_desc, residue);
1194 	return residue;
1195 }
1196 
1197 static enum dma_status pxad_tx_status(struct dma_chan *dchan,
1198 				      dma_cookie_t cookie,
1199 				      struct dma_tx_state *txstate)
1200 {
1201 	struct pxad_chan *chan = to_pxad_chan(dchan);
1202 	enum dma_status ret;
1203 
1204 	if (cookie == chan->bus_error)
1205 		return DMA_ERROR;
1206 
1207 	ret = dma_cookie_status(dchan, cookie, txstate);
1208 	if (likely(txstate && (ret != DMA_ERROR)))
1209 		dma_set_residue(txstate, pxad_residue(chan, cookie));
1210 
1211 	return ret;
1212 }
1213 
1214 static void pxad_synchronize(struct dma_chan *dchan)
1215 {
1216 	struct pxad_chan *chan = to_pxad_chan(dchan);
1217 
1218 	wait_event(chan->wq_state, !is_chan_running(chan));
1219 	vchan_synchronize(&chan->vc);
1220 }
1221 
1222 static void pxad_free_channels(struct dma_device *dmadev)
1223 {
1224 	struct pxad_chan *c, *cn;
1225 
1226 	list_for_each_entry_safe(c, cn, &dmadev->channels,
1227 				 vc.chan.device_node) {
1228 		list_del(&c->vc.chan.device_node);
1229 		tasklet_kill(&c->vc.task);
1230 	}
1231 }
1232 
1233 static int pxad_remove(struct platform_device *op)
1234 {
1235 	struct pxad_device *pdev = platform_get_drvdata(op);
1236 
1237 	pxad_cleanup_debugfs(pdev);
1238 	pxad_free_channels(&pdev->slave);
1239 	return 0;
1240 }
1241 
1242 static int pxad_init_phys(struct platform_device *op,
1243 			  struct pxad_device *pdev,
1244 			  unsigned int nb_phy_chans)
1245 {
1246 	int irq0, irq, nr_irq = 0, i, ret;
1247 	struct pxad_phy *phy;
1248 
1249 	irq0 = platform_get_irq(op, 0);
1250 	if (irq0 < 0)
1251 		return irq0;
1252 
1253 	pdev->phys = devm_kcalloc(&op->dev, nb_phy_chans,
1254 				  sizeof(pdev->phys[0]), GFP_KERNEL);
1255 	if (!pdev->phys)
1256 		return -ENOMEM;
1257 
1258 	for (i = 0; i < nb_phy_chans; i++)
1259 		if (platform_get_irq(op, i) > 0)
1260 			nr_irq++;
1261 
1262 	for (i = 0; i < nb_phy_chans; i++) {
1263 		phy = &pdev->phys[i];
1264 		phy->base = pdev->base;
1265 		phy->idx = i;
1266 		irq = platform_get_irq(op, i);
1267 		if ((nr_irq > 1) && (irq > 0))
1268 			ret = devm_request_irq(&op->dev, irq,
1269 					       pxad_chan_handler,
1270 					       IRQF_SHARED, "pxa-dma", phy);
1271 		if ((nr_irq == 1) && (i == 0))
1272 			ret = devm_request_irq(&op->dev, irq0,
1273 					       pxad_int_handler,
1274 					       IRQF_SHARED, "pxa-dma", pdev);
1275 		if (ret) {
1276 			dev_err(pdev->slave.dev,
1277 				"%s(): can't request irq %d:%d\n", __func__,
1278 				irq, ret);
1279 			return ret;
1280 		}
1281 	}
1282 
1283 	return 0;
1284 }
1285 
1286 static const struct of_device_id pxad_dt_ids[] = {
1287 	{ .compatible = "marvell,pdma-1.0", },
1288 	{}
1289 };
1290 MODULE_DEVICE_TABLE(of, pxad_dt_ids);
1291 
1292 static struct dma_chan *pxad_dma_xlate(struct of_phandle_args *dma_spec,
1293 					   struct of_dma *ofdma)
1294 {
1295 	struct pxad_device *d = ofdma->of_dma_data;
1296 	struct dma_chan *chan;
1297 
1298 	chan = dma_get_any_slave_channel(&d->slave);
1299 	if (!chan)
1300 		return NULL;
1301 
1302 	to_pxad_chan(chan)->drcmr = dma_spec->args[0];
1303 	to_pxad_chan(chan)->prio = dma_spec->args[1];
1304 
1305 	return chan;
1306 }
1307 
1308 static int pxad_init_dmadev(struct platform_device *op,
1309 			    struct pxad_device *pdev,
1310 			    unsigned int nr_phy_chans,
1311 			    unsigned int nr_requestors)
1312 {
1313 	int ret;
1314 	unsigned int i;
1315 	struct pxad_chan *c;
1316 
1317 	pdev->nr_chans = nr_phy_chans;
1318 	pdev->nr_requestors = nr_requestors;
1319 	INIT_LIST_HEAD(&pdev->slave.channels);
1320 	pdev->slave.device_alloc_chan_resources = pxad_alloc_chan_resources;
1321 	pdev->slave.device_free_chan_resources = pxad_free_chan_resources;
1322 	pdev->slave.device_tx_status = pxad_tx_status;
1323 	pdev->slave.device_issue_pending = pxad_issue_pending;
1324 	pdev->slave.device_config = pxad_config;
1325 	pdev->slave.device_synchronize = pxad_synchronize;
1326 	pdev->slave.device_terminate_all = pxad_terminate_all;
1327 
1328 	if (op->dev.coherent_dma_mask)
1329 		dma_set_mask(&op->dev, op->dev.coherent_dma_mask);
1330 	else
1331 		dma_set_mask(&op->dev, DMA_BIT_MASK(32));
1332 
1333 	ret = pxad_init_phys(op, pdev, nr_phy_chans);
1334 	if (ret)
1335 		return ret;
1336 
1337 	for (i = 0; i < nr_phy_chans; i++) {
1338 		c = devm_kzalloc(&op->dev, sizeof(*c), GFP_KERNEL);
1339 		if (!c)
1340 			return -ENOMEM;
1341 
1342 		c->drcmr = U32_MAX;
1343 		c->prio = PXAD_PRIO_LOWEST;
1344 		c->vc.desc_free = pxad_free_desc;
1345 		vchan_init(&c->vc, &pdev->slave);
1346 		init_waitqueue_head(&c->wq_state);
1347 	}
1348 
1349 	return dmaenginem_async_device_register(&pdev->slave);
1350 }
1351 
1352 static int pxad_probe(struct platform_device *op)
1353 {
1354 	struct pxad_device *pdev;
1355 	const struct of_device_id *of_id;
1356 	const struct dma_slave_map *slave_map = NULL;
1357 	struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev);
1358 	struct resource *iores;
1359 	int ret, dma_channels = 0, nb_requestors = 0, slave_map_cnt = 0;
1360 	const enum dma_slave_buswidth widths =
1361 		DMA_SLAVE_BUSWIDTH_1_BYTE   | DMA_SLAVE_BUSWIDTH_2_BYTES |
1362 		DMA_SLAVE_BUSWIDTH_4_BYTES;
1363 
1364 	pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL);
1365 	if (!pdev)
1366 		return -ENOMEM;
1367 
1368 	spin_lock_init(&pdev->phy_lock);
1369 
1370 	iores = platform_get_resource(op, IORESOURCE_MEM, 0);
1371 	pdev->base = devm_ioremap_resource(&op->dev, iores);
1372 	if (IS_ERR(pdev->base))
1373 		return PTR_ERR(pdev->base);
1374 
1375 	of_id = of_match_device(pxad_dt_ids, &op->dev);
1376 	if (of_id) {
1377 		of_property_read_u32(op->dev.of_node, "#dma-channels",
1378 				     &dma_channels);
1379 		ret = of_property_read_u32(op->dev.of_node, "#dma-requests",
1380 					   &nb_requestors);
1381 		if (ret) {
1382 			dev_warn(pdev->slave.dev,
1383 				 "#dma-requests set to default 32 as missing in OF: %d",
1384 				 ret);
1385 			nb_requestors = 32;
1386 		}
1387 	} else if (pdata && pdata->dma_channels) {
1388 		dma_channels = pdata->dma_channels;
1389 		nb_requestors = pdata->nb_requestors;
1390 		slave_map = pdata->slave_map;
1391 		slave_map_cnt = pdata->slave_map_cnt;
1392 	} else {
1393 		dma_channels = 32;	/* default 32 channel */
1394 	}
1395 
1396 	dma_cap_set(DMA_SLAVE, pdev->slave.cap_mask);
1397 	dma_cap_set(DMA_MEMCPY, pdev->slave.cap_mask);
1398 	dma_cap_set(DMA_CYCLIC, pdev->slave.cap_mask);
1399 	dma_cap_set(DMA_PRIVATE, pdev->slave.cap_mask);
1400 	pdev->slave.device_prep_dma_memcpy = pxad_prep_memcpy;
1401 	pdev->slave.device_prep_slave_sg = pxad_prep_slave_sg;
1402 	pdev->slave.device_prep_dma_cyclic = pxad_prep_dma_cyclic;
1403 	pdev->slave.filter.map = slave_map;
1404 	pdev->slave.filter.mapcnt = slave_map_cnt;
1405 	pdev->slave.filter.fn = pxad_filter_fn;
1406 
1407 	pdev->slave.copy_align = PDMA_ALIGNMENT;
1408 	pdev->slave.src_addr_widths = widths;
1409 	pdev->slave.dst_addr_widths = widths;
1410 	pdev->slave.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
1411 	pdev->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1412 	pdev->slave.descriptor_reuse = true;
1413 
1414 	pdev->slave.dev = &op->dev;
1415 	ret = pxad_init_dmadev(op, pdev, dma_channels, nb_requestors);
1416 	if (ret) {
1417 		dev_err(pdev->slave.dev, "unable to register\n");
1418 		return ret;
1419 	}
1420 
1421 	if (op->dev.of_node) {
1422 		/* Device-tree DMA controller registration */
1423 		ret = of_dma_controller_register(op->dev.of_node,
1424 						 pxad_dma_xlate, pdev);
1425 		if (ret < 0) {
1426 			dev_err(pdev->slave.dev,
1427 				"of_dma_controller_register failed\n");
1428 			return ret;
1429 		}
1430 	}
1431 
1432 	platform_set_drvdata(op, pdev);
1433 	pxad_init_debugfs(pdev);
1434 	dev_info(pdev->slave.dev, "initialized %d channels on %d requestors\n",
1435 		 dma_channels, nb_requestors);
1436 	return 0;
1437 }
1438 
1439 static const struct platform_device_id pxad_id_table[] = {
1440 	{ "pxa-dma", },
1441 	{ },
1442 };
1443 
1444 static struct platform_driver pxad_driver = {
1445 	.driver		= {
1446 		.name	= "pxa-dma",
1447 		.of_match_table = pxad_dt_ids,
1448 	},
1449 	.id_table	= pxad_id_table,
1450 	.probe		= pxad_probe,
1451 	.remove		= pxad_remove,
1452 };
1453 
1454 static bool pxad_filter_fn(struct dma_chan *chan, void *param)
1455 {
1456 	struct pxad_chan *c = to_pxad_chan(chan);
1457 	struct pxad_param *p = param;
1458 
1459 	if (chan->device->dev->driver != &pxad_driver.driver)
1460 		return false;
1461 
1462 	c->drcmr = p->drcmr;
1463 	c->prio = p->prio;
1464 
1465 	return true;
1466 }
1467 
1468 module_platform_driver(pxad_driver);
1469 
1470 MODULE_DESCRIPTION("Marvell PXA Peripheral DMA Driver");
1471 MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
1472 MODULE_LICENSE("GPL v2");
1473