1 /* 2 * Copyright 2015 Robert Jarzmik <robert.jarzmik@free.fr> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/err.h> 10 #include <linux/module.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/interrupt.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/slab.h> 16 #include <linux/dmaengine.h> 17 #include <linux/platform_device.h> 18 #include <linux/device.h> 19 #include <linux/platform_data/mmp_dma.h> 20 #include <linux/dmapool.h> 21 #include <linux/of_device.h> 22 #include <linux/of_dma.h> 23 #include <linux/of.h> 24 #include <linux/dma/pxa-dma.h> 25 26 #include "dmaengine.h" 27 #include "virt-dma.h" 28 29 #define DCSR(n) (0x0000 + ((n) << 2)) 30 #define DALGN(n) 0x00a0 31 #define DINT 0x00f0 32 #define DDADR(n) (0x0200 + ((n) << 4)) 33 #define DSADR(n) (0x0204 + ((n) << 4)) 34 #define DTADR(n) (0x0208 + ((n) << 4)) 35 #define DCMD(n) (0x020c + ((n) << 4)) 36 37 #define PXA_DCSR_RUN BIT(31) /* Run Bit (read / write) */ 38 #define PXA_DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */ 39 #define PXA_DCSR_STOPIRQEN BIT(29) /* Stop Interrupt Enable (R/W) */ 40 #define PXA_DCSR_REQPEND BIT(8) /* Request Pending (read-only) */ 41 #define PXA_DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */ 42 #define PXA_DCSR_ENDINTR BIT(2) /* End Interrupt (read / write) */ 43 #define PXA_DCSR_STARTINTR BIT(1) /* Start Interrupt (read / write) */ 44 #define PXA_DCSR_BUSERR BIT(0) /* Bus Error Interrupt (read / write) */ 45 46 #define PXA_DCSR_EORIRQEN BIT(28) /* End of Receive IRQ Enable (R/W) */ 47 #define PXA_DCSR_EORJMPEN BIT(27) /* Jump to next descriptor on EOR */ 48 #define PXA_DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */ 49 #define PXA_DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */ 50 #define PXA_DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */ 51 #define PXA_DCSR_CMPST BIT(10) /* The Descriptor Compare Status */ 52 #define PXA_DCSR_EORINTR BIT(9) /* The end of Receive */ 53 54 #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ 55 #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ 56 57 #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ 58 #define DDADR_STOP BIT(0) /* Stop (read / write) */ 59 60 #define PXA_DCMD_INCSRCADDR BIT(31) /* Source Address Increment Setting. */ 61 #define PXA_DCMD_INCTRGADDR BIT(30) /* Target Address Increment Setting. */ 62 #define PXA_DCMD_FLOWSRC BIT(29) /* Flow Control by the source. */ 63 #define PXA_DCMD_FLOWTRG BIT(28) /* Flow Control by the target. */ 64 #define PXA_DCMD_STARTIRQEN BIT(22) /* Start Interrupt Enable */ 65 #define PXA_DCMD_ENDIRQEN BIT(21) /* End Interrupt Enable */ 66 #define PXA_DCMD_ENDIAN BIT(18) /* Device Endian-ness. */ 67 #define PXA_DCMD_BURST8 (1 << 16) /* 8 byte burst */ 68 #define PXA_DCMD_BURST16 (2 << 16) /* 16 byte burst */ 69 #define PXA_DCMD_BURST32 (3 << 16) /* 32 byte burst */ 70 #define PXA_DCMD_WIDTH1 (1 << 14) /* 1 byte width */ 71 #define PXA_DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ 72 #define PXA_DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ 73 #define PXA_DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ 74 75 #define PDMA_ALIGNMENT 3 76 #define PDMA_MAX_DESC_BYTES (PXA_DCMD_LENGTH & ~((1 << PDMA_ALIGNMENT) - 1)) 77 78 struct pxad_desc_hw { 79 u32 ddadr; /* Points to the next descriptor + flags */ 80 u32 dsadr; /* DSADR value for the current transfer */ 81 u32 dtadr; /* DTADR value for the current transfer */ 82 u32 dcmd; /* DCMD value for the current transfer */ 83 } __aligned(16); 84 85 struct pxad_desc_sw { 86 struct virt_dma_desc vd; /* Virtual descriptor */ 87 int nb_desc; /* Number of hw. descriptors */ 88 size_t len; /* Number of bytes xfered */ 89 dma_addr_t first; /* First descriptor's addr */ 90 91 /* At least one descriptor has an src/dst address not multiple of 8 */ 92 bool misaligned; 93 bool cyclic; 94 struct dma_pool *desc_pool; /* Channel's used allocator */ 95 96 struct pxad_desc_hw *hw_desc[]; /* DMA coherent descriptors */ 97 }; 98 99 struct pxad_phy { 100 int idx; 101 void __iomem *base; 102 struct pxad_chan *vchan; 103 }; 104 105 struct pxad_chan { 106 struct virt_dma_chan vc; /* Virtual channel */ 107 u32 drcmr; /* Requestor of the channel */ 108 enum pxad_chan_prio prio; /* Required priority of phy */ 109 /* 110 * At least one desc_sw in submitted or issued transfers on this channel 111 * has one address such as: addr % 8 != 0. This implies the DALGN 112 * setting on the phy. 113 */ 114 bool misaligned; 115 struct dma_slave_config cfg; /* Runtime config */ 116 117 /* protected by vc->lock */ 118 struct pxad_phy *phy; 119 struct dma_pool *desc_pool; /* Descriptors pool */ 120 dma_cookie_t bus_error; 121 }; 122 123 struct pxad_device { 124 struct dma_device slave; 125 int nr_chans; 126 int nr_requestors; 127 void __iomem *base; 128 struct pxad_phy *phys; 129 spinlock_t phy_lock; /* Phy association */ 130 #ifdef CONFIG_DEBUG_FS 131 struct dentry *dbgfs_root; 132 struct dentry *dbgfs_state; 133 struct dentry **dbgfs_chan; 134 #endif 135 }; 136 137 #define tx_to_pxad_desc(tx) \ 138 container_of(tx, struct pxad_desc_sw, async_tx) 139 #define to_pxad_chan(dchan) \ 140 container_of(dchan, struct pxad_chan, vc.chan) 141 #define to_pxad_dev(dmadev) \ 142 container_of(dmadev, struct pxad_device, slave) 143 #define to_pxad_sw_desc(_vd) \ 144 container_of((_vd), struct pxad_desc_sw, vd) 145 146 #define _phy_readl_relaxed(phy, _reg) \ 147 readl_relaxed((phy)->base + _reg((phy)->idx)) 148 #define phy_readl_relaxed(phy, _reg) \ 149 ({ \ 150 u32 _v; \ 151 _v = readl_relaxed((phy)->base + _reg((phy)->idx)); \ 152 dev_vdbg(&phy->vchan->vc.chan.dev->device, \ 153 "%s(): readl(%s): 0x%08x\n", __func__, #_reg, \ 154 _v); \ 155 _v; \ 156 }) 157 #define phy_writel(phy, val, _reg) \ 158 do { \ 159 writel((val), (phy)->base + _reg((phy)->idx)); \ 160 dev_vdbg(&phy->vchan->vc.chan.dev->device, \ 161 "%s(): writel(0x%08x, %s)\n", \ 162 __func__, (u32)(val), #_reg); \ 163 } while (0) 164 #define phy_writel_relaxed(phy, val, _reg) \ 165 do { \ 166 writel_relaxed((val), (phy)->base + _reg((phy)->idx)); \ 167 dev_vdbg(&phy->vchan->vc.chan.dev->device, \ 168 "%s(): writel_relaxed(0x%08x, %s)\n", \ 169 __func__, (u32)(val), #_reg); \ 170 } while (0) 171 172 static unsigned int pxad_drcmr(unsigned int line) 173 { 174 if (line < 64) 175 return 0x100 + line * 4; 176 return 0x1000 + line * 4; 177 } 178 179 /* 180 * Debug fs 181 */ 182 #ifdef CONFIG_DEBUG_FS 183 #include <linux/debugfs.h> 184 #include <linux/uaccess.h> 185 #include <linux/seq_file.h> 186 187 static int dbg_show_requester_chan(struct seq_file *s, void *p) 188 { 189 struct pxad_phy *phy = s->private; 190 int i; 191 u32 drcmr; 192 193 seq_printf(s, "DMA channel %d requester :\n", phy->idx); 194 for (i = 0; i < 70; i++) { 195 drcmr = readl_relaxed(phy->base + pxad_drcmr(i)); 196 if ((drcmr & DRCMR_CHLNUM) == phy->idx) 197 seq_printf(s, "\tRequester %d (MAPVLD=%d)\n", i, 198 !!(drcmr & DRCMR_MAPVLD)); 199 } 200 return 0; 201 } 202 203 static inline int dbg_burst_from_dcmd(u32 dcmd) 204 { 205 int burst = (dcmd >> 16) & 0x3; 206 207 return burst ? 4 << burst : 0; 208 } 209 210 static int is_phys_valid(unsigned long addr) 211 { 212 return pfn_valid(__phys_to_pfn(addr)); 213 } 214 215 #define PXA_DCSR_STR(flag) (dcsr & PXA_DCSR_##flag ? #flag" " : "") 216 #define PXA_DCMD_STR(flag) (dcmd & PXA_DCMD_##flag ? #flag" " : "") 217 218 static int dbg_show_descriptors(struct seq_file *s, void *p) 219 { 220 struct pxad_phy *phy = s->private; 221 int i, max_show = 20, burst, width; 222 u32 dcmd; 223 unsigned long phys_desc, ddadr; 224 struct pxad_desc_hw *desc; 225 226 phys_desc = ddadr = _phy_readl_relaxed(phy, DDADR); 227 228 seq_printf(s, "DMA channel %d descriptors :\n", phy->idx); 229 seq_printf(s, "[%03d] First descriptor unknown\n", 0); 230 for (i = 1; i < max_show && is_phys_valid(phys_desc); i++) { 231 desc = phys_to_virt(phys_desc); 232 dcmd = desc->dcmd; 233 burst = dbg_burst_from_dcmd(dcmd); 234 width = (1 << ((dcmd >> 14) & 0x3)) >> 1; 235 236 seq_printf(s, "[%03d] Desc at %08lx(virt %p)\n", 237 i, phys_desc, desc); 238 seq_printf(s, "\tDDADR = %08x\n", desc->ddadr); 239 seq_printf(s, "\tDSADR = %08x\n", desc->dsadr); 240 seq_printf(s, "\tDTADR = %08x\n", desc->dtadr); 241 seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n", 242 dcmd, 243 PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR), 244 PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG), 245 PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN), 246 PXA_DCMD_STR(ENDIAN), burst, width, 247 dcmd & PXA_DCMD_LENGTH); 248 phys_desc = desc->ddadr; 249 } 250 if (i == max_show) 251 seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n", 252 i, phys_desc); 253 else 254 seq_printf(s, "[%03d] Desc at %08lx is %s\n", 255 i, phys_desc, phys_desc == DDADR_STOP ? 256 "DDADR_STOP" : "invalid"); 257 258 return 0; 259 } 260 261 static int dbg_show_chan_state(struct seq_file *s, void *p) 262 { 263 struct pxad_phy *phy = s->private; 264 u32 dcsr, dcmd; 265 int burst, width; 266 static const char * const str_prio[] = { 267 "high", "normal", "low", "invalid" 268 }; 269 270 dcsr = _phy_readl_relaxed(phy, DCSR); 271 dcmd = _phy_readl_relaxed(phy, DCMD); 272 burst = dbg_burst_from_dcmd(dcmd); 273 width = (1 << ((dcmd >> 14) & 0x3)) >> 1; 274 275 seq_printf(s, "DMA channel %d\n", phy->idx); 276 seq_printf(s, "\tPriority : %s\n", 277 str_prio[(phy->idx & 0xf) / 4]); 278 seq_printf(s, "\tUnaligned transfer bit: %s\n", 279 _phy_readl_relaxed(phy, DALGN) & BIT(phy->idx) ? 280 "yes" : "no"); 281 seq_printf(s, "\tDCSR = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 282 dcsr, PXA_DCSR_STR(RUN), PXA_DCSR_STR(NODESC), 283 PXA_DCSR_STR(STOPIRQEN), PXA_DCSR_STR(EORIRQEN), 284 PXA_DCSR_STR(EORJMPEN), PXA_DCSR_STR(EORSTOPEN), 285 PXA_DCSR_STR(SETCMPST), PXA_DCSR_STR(CLRCMPST), 286 PXA_DCSR_STR(CMPST), PXA_DCSR_STR(EORINTR), 287 PXA_DCSR_STR(REQPEND), PXA_DCSR_STR(STOPSTATE), 288 PXA_DCSR_STR(ENDINTR), PXA_DCSR_STR(STARTINTR), 289 PXA_DCSR_STR(BUSERR)); 290 291 seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n", 292 dcmd, 293 PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR), 294 PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG), 295 PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN), 296 PXA_DCMD_STR(ENDIAN), burst, width, dcmd & PXA_DCMD_LENGTH); 297 seq_printf(s, "\tDSADR = %08x\n", _phy_readl_relaxed(phy, DSADR)); 298 seq_printf(s, "\tDTADR = %08x\n", _phy_readl_relaxed(phy, DTADR)); 299 seq_printf(s, "\tDDADR = %08x\n", _phy_readl_relaxed(phy, DDADR)); 300 301 return 0; 302 } 303 304 static int dbg_show_state(struct seq_file *s, void *p) 305 { 306 struct pxad_device *pdev = s->private; 307 308 /* basic device status */ 309 seq_puts(s, "DMA engine status\n"); 310 seq_printf(s, "\tChannel number: %d\n", pdev->nr_chans); 311 312 return 0; 313 } 314 315 #define DBGFS_FUNC_DECL(name) \ 316 static int dbg_open_##name(struct inode *inode, struct file *file) \ 317 { \ 318 return single_open(file, dbg_show_##name, inode->i_private); \ 319 } \ 320 static const struct file_operations dbg_fops_##name = { \ 321 .owner = THIS_MODULE, \ 322 .open = dbg_open_##name, \ 323 .llseek = seq_lseek, \ 324 .read = seq_read, \ 325 .release = single_release, \ 326 } 327 328 DBGFS_FUNC_DECL(state); 329 DBGFS_FUNC_DECL(chan_state); 330 DBGFS_FUNC_DECL(descriptors); 331 DBGFS_FUNC_DECL(requester_chan); 332 333 static struct dentry *pxad_dbg_alloc_chan(struct pxad_device *pdev, 334 int ch, struct dentry *chandir) 335 { 336 char chan_name[11]; 337 struct dentry *chan, *chan_state = NULL, *chan_descr = NULL; 338 struct dentry *chan_reqs = NULL; 339 void *dt; 340 341 scnprintf(chan_name, sizeof(chan_name), "%d", ch); 342 chan = debugfs_create_dir(chan_name, chandir); 343 dt = (void *)&pdev->phys[ch]; 344 345 if (chan) 346 chan_state = debugfs_create_file("state", 0400, chan, dt, 347 &dbg_fops_chan_state); 348 if (chan_state) 349 chan_descr = debugfs_create_file("descriptors", 0400, chan, dt, 350 &dbg_fops_descriptors); 351 if (chan_descr) 352 chan_reqs = debugfs_create_file("requesters", 0400, chan, dt, 353 &dbg_fops_requester_chan); 354 if (!chan_reqs) 355 goto err_state; 356 357 return chan; 358 359 err_state: 360 debugfs_remove_recursive(chan); 361 return NULL; 362 } 363 364 static void pxad_init_debugfs(struct pxad_device *pdev) 365 { 366 int i; 367 struct dentry *chandir; 368 369 pdev->dbgfs_root = debugfs_create_dir(dev_name(pdev->slave.dev), NULL); 370 if (IS_ERR(pdev->dbgfs_root) || !pdev->dbgfs_root) 371 goto err_root; 372 373 pdev->dbgfs_state = debugfs_create_file("state", 0400, pdev->dbgfs_root, 374 pdev, &dbg_fops_state); 375 if (!pdev->dbgfs_state) 376 goto err_state; 377 378 pdev->dbgfs_chan = 379 kmalloc_array(pdev->nr_chans, sizeof(*pdev->dbgfs_state), 380 GFP_KERNEL); 381 if (!pdev->dbgfs_chan) 382 goto err_alloc; 383 384 chandir = debugfs_create_dir("channels", pdev->dbgfs_root); 385 if (!chandir) 386 goto err_chandir; 387 388 for (i = 0; i < pdev->nr_chans; i++) { 389 pdev->dbgfs_chan[i] = pxad_dbg_alloc_chan(pdev, i, chandir); 390 if (!pdev->dbgfs_chan[i]) 391 goto err_chans; 392 } 393 394 return; 395 err_chans: 396 err_chandir: 397 kfree(pdev->dbgfs_chan); 398 err_alloc: 399 err_state: 400 debugfs_remove_recursive(pdev->dbgfs_root); 401 err_root: 402 pr_err("pxad: debugfs is not available\n"); 403 } 404 405 static void pxad_cleanup_debugfs(struct pxad_device *pdev) 406 { 407 debugfs_remove_recursive(pdev->dbgfs_root); 408 } 409 #else 410 static inline void pxad_init_debugfs(struct pxad_device *pdev) {} 411 static inline void pxad_cleanup_debugfs(struct pxad_device *pdev) {} 412 #endif 413 414 /* 415 * In the transition phase where legacy pxa handling is done at the same time as 416 * mmp_dma, the DMA physical channel split between the 2 DMA providers is done 417 * through legacy_reserved. Legacy code reserves DMA channels by settings 418 * corresponding bits in legacy_reserved. 419 */ 420 static u32 legacy_reserved; 421 static u32 legacy_unavailable; 422 423 static struct pxad_phy *lookup_phy(struct pxad_chan *pchan) 424 { 425 int prio, i; 426 struct pxad_device *pdev = to_pxad_dev(pchan->vc.chan.device); 427 struct pxad_phy *phy, *found = NULL; 428 unsigned long flags; 429 430 /* 431 * dma channel priorities 432 * ch 0 - 3, 16 - 19 <--> (0) 433 * ch 4 - 7, 20 - 23 <--> (1) 434 * ch 8 - 11, 24 - 27 <--> (2) 435 * ch 12 - 15, 28 - 31 <--> (3) 436 */ 437 438 spin_lock_irqsave(&pdev->phy_lock, flags); 439 for (prio = pchan->prio; prio >= PXAD_PRIO_HIGHEST; prio--) { 440 for (i = 0; i < pdev->nr_chans; i++) { 441 if (prio != (i & 0xf) >> 2) 442 continue; 443 if ((i < 32) && (legacy_reserved & BIT(i))) 444 continue; 445 phy = &pdev->phys[i]; 446 if (!phy->vchan) { 447 phy->vchan = pchan; 448 found = phy; 449 if (i < 32) 450 legacy_unavailable |= BIT(i); 451 goto out_unlock; 452 } 453 } 454 } 455 456 out_unlock: 457 spin_unlock_irqrestore(&pdev->phy_lock, flags); 458 dev_dbg(&pchan->vc.chan.dev->device, 459 "%s(): phy=%p(%d)\n", __func__, found, 460 found ? found->idx : -1); 461 462 return found; 463 } 464 465 static void pxad_free_phy(struct pxad_chan *chan) 466 { 467 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); 468 unsigned long flags; 469 u32 reg; 470 int i; 471 472 dev_dbg(&chan->vc.chan.dev->device, 473 "%s(): freeing\n", __func__); 474 if (!chan->phy) 475 return; 476 477 /* clear the channel mapping in DRCMR */ 478 if (chan->drcmr <= pdev->nr_requestors) { 479 reg = pxad_drcmr(chan->drcmr); 480 writel_relaxed(0, chan->phy->base + reg); 481 } 482 483 spin_lock_irqsave(&pdev->phy_lock, flags); 484 for (i = 0; i < 32; i++) 485 if (chan->phy == &pdev->phys[i]) 486 legacy_unavailable &= ~BIT(i); 487 chan->phy->vchan = NULL; 488 chan->phy = NULL; 489 spin_unlock_irqrestore(&pdev->phy_lock, flags); 490 } 491 492 static bool is_chan_running(struct pxad_chan *chan) 493 { 494 u32 dcsr; 495 struct pxad_phy *phy = chan->phy; 496 497 if (!phy) 498 return false; 499 dcsr = phy_readl_relaxed(phy, DCSR); 500 return dcsr & PXA_DCSR_RUN; 501 } 502 503 static bool is_running_chan_misaligned(struct pxad_chan *chan) 504 { 505 u32 dalgn; 506 507 BUG_ON(!chan->phy); 508 dalgn = phy_readl_relaxed(chan->phy, DALGN); 509 return dalgn & (BIT(chan->phy->idx)); 510 } 511 512 static void phy_enable(struct pxad_phy *phy, bool misaligned) 513 { 514 struct pxad_device *pdev; 515 u32 reg, dalgn; 516 517 if (!phy->vchan) 518 return; 519 520 dev_dbg(&phy->vchan->vc.chan.dev->device, 521 "%s(); phy=%p(%d) misaligned=%d\n", __func__, 522 phy, phy->idx, misaligned); 523 524 pdev = to_pxad_dev(phy->vchan->vc.chan.device); 525 if (phy->vchan->drcmr <= pdev->nr_requestors) { 526 reg = pxad_drcmr(phy->vchan->drcmr); 527 writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg); 528 } 529 530 dalgn = phy_readl_relaxed(phy, DALGN); 531 if (misaligned) 532 dalgn |= BIT(phy->idx); 533 else 534 dalgn &= ~BIT(phy->idx); 535 phy_writel_relaxed(phy, dalgn, DALGN); 536 537 phy_writel(phy, PXA_DCSR_STOPIRQEN | PXA_DCSR_ENDINTR | 538 PXA_DCSR_BUSERR | PXA_DCSR_RUN, DCSR); 539 } 540 541 static void phy_disable(struct pxad_phy *phy) 542 { 543 u32 dcsr; 544 545 if (!phy) 546 return; 547 548 dcsr = phy_readl_relaxed(phy, DCSR); 549 dev_dbg(&phy->vchan->vc.chan.dev->device, 550 "%s(): phy=%p(%d)\n", __func__, phy, phy->idx); 551 phy_writel(phy, dcsr & ~PXA_DCSR_RUN & ~PXA_DCSR_STOPIRQEN, DCSR); 552 } 553 554 static void pxad_launch_chan(struct pxad_chan *chan, 555 struct pxad_desc_sw *desc) 556 { 557 dev_dbg(&chan->vc.chan.dev->device, 558 "%s(): desc=%p\n", __func__, desc); 559 if (!chan->phy) { 560 chan->phy = lookup_phy(chan); 561 if (!chan->phy) { 562 dev_dbg(&chan->vc.chan.dev->device, 563 "%s(): no free dma channel\n", __func__); 564 return; 565 } 566 } 567 chan->bus_error = 0; 568 569 /* 570 * Program the descriptor's address into the DMA controller, 571 * then start the DMA transaction 572 */ 573 phy_writel(chan->phy, desc->first, DDADR); 574 phy_enable(chan->phy, chan->misaligned); 575 } 576 577 static void set_updater_desc(struct pxad_desc_sw *sw_desc, 578 unsigned long flags) 579 { 580 struct pxad_desc_hw *updater = 581 sw_desc->hw_desc[sw_desc->nb_desc - 1]; 582 dma_addr_t dma = sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr; 583 584 updater->ddadr = DDADR_STOP; 585 updater->dsadr = dma; 586 updater->dtadr = dma + 8; 587 updater->dcmd = PXA_DCMD_WIDTH4 | PXA_DCMD_BURST32 | 588 (PXA_DCMD_LENGTH & sizeof(u32)); 589 if (flags & DMA_PREP_INTERRUPT) 590 updater->dcmd |= PXA_DCMD_ENDIRQEN; 591 if (sw_desc->cyclic) 592 sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr = sw_desc->first; 593 } 594 595 static bool is_desc_completed(struct virt_dma_desc *vd) 596 { 597 struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd); 598 struct pxad_desc_hw *updater = 599 sw_desc->hw_desc[sw_desc->nb_desc - 1]; 600 601 return updater->dtadr != (updater->dsadr + 8); 602 } 603 604 static void pxad_desc_chain(struct virt_dma_desc *vd1, 605 struct virt_dma_desc *vd2) 606 { 607 struct pxad_desc_sw *desc1 = to_pxad_sw_desc(vd1); 608 struct pxad_desc_sw *desc2 = to_pxad_sw_desc(vd2); 609 dma_addr_t dma_to_chain; 610 611 dma_to_chain = desc2->first; 612 desc1->hw_desc[desc1->nb_desc - 1]->ddadr = dma_to_chain; 613 } 614 615 static bool pxad_try_hotchain(struct virt_dma_chan *vc, 616 struct virt_dma_desc *vd) 617 { 618 struct virt_dma_desc *vd_last_issued = NULL; 619 struct pxad_chan *chan = to_pxad_chan(&vc->chan); 620 621 /* 622 * Attempt to hot chain the tx if the phy is still running. This is 623 * considered successful only if either the channel is still running 624 * after the chaining, or if the chained transfer is completed after 625 * having been hot chained. 626 * A change of alignment is not allowed, and forbids hotchaining. 627 */ 628 if (is_chan_running(chan)) { 629 BUG_ON(list_empty(&vc->desc_issued)); 630 631 if (!is_running_chan_misaligned(chan) && 632 to_pxad_sw_desc(vd)->misaligned) 633 return false; 634 635 vd_last_issued = list_entry(vc->desc_issued.prev, 636 struct virt_dma_desc, node); 637 pxad_desc_chain(vd_last_issued, vd); 638 if (is_chan_running(chan) || is_desc_completed(vd_last_issued)) 639 return true; 640 } 641 642 return false; 643 } 644 645 static unsigned int clear_chan_irq(struct pxad_phy *phy) 646 { 647 u32 dcsr; 648 u32 dint = readl(phy->base + DINT); 649 650 if (!(dint & BIT(phy->idx))) 651 return PXA_DCSR_RUN; 652 653 /* clear irq */ 654 dcsr = phy_readl_relaxed(phy, DCSR); 655 phy_writel(phy, dcsr, DCSR); 656 if ((dcsr & PXA_DCSR_BUSERR) && (phy->vchan)) 657 dev_warn(&phy->vchan->vc.chan.dev->device, 658 "%s(chan=%p): PXA_DCSR_BUSERR\n", 659 __func__, &phy->vchan); 660 661 return dcsr & ~PXA_DCSR_RUN; 662 } 663 664 static irqreturn_t pxad_chan_handler(int irq, void *dev_id) 665 { 666 struct pxad_phy *phy = dev_id; 667 struct pxad_chan *chan = phy->vchan; 668 struct virt_dma_desc *vd, *tmp; 669 unsigned int dcsr; 670 unsigned long flags; 671 dma_cookie_t last_started = 0; 672 673 BUG_ON(!chan); 674 675 dcsr = clear_chan_irq(phy); 676 if (dcsr & PXA_DCSR_RUN) 677 return IRQ_NONE; 678 679 spin_lock_irqsave(&chan->vc.lock, flags); 680 list_for_each_entry_safe(vd, tmp, &chan->vc.desc_issued, node) { 681 dev_dbg(&chan->vc.chan.dev->device, 682 "%s(): checking txd %p[%x]: completed=%d\n", 683 __func__, vd, vd->tx.cookie, is_desc_completed(vd)); 684 last_started = vd->tx.cookie; 685 if (to_pxad_sw_desc(vd)->cyclic) { 686 vchan_cyclic_callback(vd); 687 break; 688 } 689 if (is_desc_completed(vd)) { 690 list_del(&vd->node); 691 vchan_cookie_complete(vd); 692 } else { 693 break; 694 } 695 } 696 697 if (dcsr & PXA_DCSR_BUSERR) { 698 chan->bus_error = last_started; 699 phy_disable(phy); 700 } 701 702 if (!chan->bus_error && dcsr & PXA_DCSR_STOPSTATE) { 703 dev_dbg(&chan->vc.chan.dev->device, 704 "%s(): channel stopped, submitted_empty=%d issued_empty=%d", 705 __func__, 706 list_empty(&chan->vc.desc_submitted), 707 list_empty(&chan->vc.desc_issued)); 708 phy_writel_relaxed(phy, dcsr & ~PXA_DCSR_STOPIRQEN, DCSR); 709 710 if (list_empty(&chan->vc.desc_issued)) { 711 chan->misaligned = 712 !list_empty(&chan->vc.desc_submitted); 713 } else { 714 vd = list_first_entry(&chan->vc.desc_issued, 715 struct virt_dma_desc, node); 716 pxad_launch_chan(chan, to_pxad_sw_desc(vd)); 717 } 718 } 719 spin_unlock_irqrestore(&chan->vc.lock, flags); 720 721 return IRQ_HANDLED; 722 } 723 724 static irqreturn_t pxad_int_handler(int irq, void *dev_id) 725 { 726 struct pxad_device *pdev = dev_id; 727 struct pxad_phy *phy; 728 u32 dint = readl(pdev->base + DINT); 729 int i, ret = IRQ_NONE; 730 731 while (dint) { 732 i = __ffs(dint); 733 dint &= (dint - 1); 734 phy = &pdev->phys[i]; 735 if ((i < 32) && (legacy_reserved & BIT(i))) 736 continue; 737 if (pxad_chan_handler(irq, phy) == IRQ_HANDLED) 738 ret = IRQ_HANDLED; 739 } 740 741 return ret; 742 } 743 744 static int pxad_alloc_chan_resources(struct dma_chan *dchan) 745 { 746 struct pxad_chan *chan = to_pxad_chan(dchan); 747 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); 748 749 if (chan->desc_pool) 750 return 1; 751 752 chan->desc_pool = dma_pool_create(dma_chan_name(dchan), 753 pdev->slave.dev, 754 sizeof(struct pxad_desc_hw), 755 __alignof__(struct pxad_desc_hw), 756 0); 757 if (!chan->desc_pool) { 758 dev_err(&chan->vc.chan.dev->device, 759 "%s(): unable to allocate descriptor pool\n", 760 __func__); 761 return -ENOMEM; 762 } 763 764 return 1; 765 } 766 767 static void pxad_free_chan_resources(struct dma_chan *dchan) 768 { 769 struct pxad_chan *chan = to_pxad_chan(dchan); 770 771 vchan_free_chan_resources(&chan->vc); 772 dma_pool_destroy(chan->desc_pool); 773 chan->desc_pool = NULL; 774 775 } 776 777 static void pxad_free_desc(struct virt_dma_desc *vd) 778 { 779 int i; 780 dma_addr_t dma; 781 struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd); 782 783 BUG_ON(sw_desc->nb_desc == 0); 784 for (i = sw_desc->nb_desc - 1; i >= 0; i--) { 785 if (i > 0) 786 dma = sw_desc->hw_desc[i - 1]->ddadr; 787 else 788 dma = sw_desc->first; 789 dma_pool_free(sw_desc->desc_pool, 790 sw_desc->hw_desc[i], dma); 791 } 792 sw_desc->nb_desc = 0; 793 kfree(sw_desc); 794 } 795 796 static struct pxad_desc_sw * 797 pxad_alloc_desc(struct pxad_chan *chan, unsigned int nb_hw_desc) 798 { 799 struct pxad_desc_sw *sw_desc; 800 dma_addr_t dma; 801 int i; 802 803 sw_desc = kzalloc(sizeof(*sw_desc) + 804 nb_hw_desc * sizeof(struct pxad_desc_hw *), 805 GFP_NOWAIT); 806 if (!sw_desc) 807 return NULL; 808 sw_desc->desc_pool = chan->desc_pool; 809 810 for (i = 0; i < nb_hw_desc; i++) { 811 sw_desc->hw_desc[i] = dma_pool_alloc(sw_desc->desc_pool, 812 GFP_NOWAIT, &dma); 813 if (!sw_desc->hw_desc[i]) { 814 dev_err(&chan->vc.chan.dev->device, 815 "%s(): Couldn't allocate the %dth hw_desc from dma_pool %p\n", 816 __func__, i, sw_desc->desc_pool); 817 goto err; 818 } 819 820 if (i == 0) 821 sw_desc->first = dma; 822 else 823 sw_desc->hw_desc[i - 1]->ddadr = dma; 824 sw_desc->nb_desc++; 825 } 826 827 return sw_desc; 828 err: 829 pxad_free_desc(&sw_desc->vd); 830 return NULL; 831 } 832 833 static dma_cookie_t pxad_tx_submit(struct dma_async_tx_descriptor *tx) 834 { 835 struct virt_dma_chan *vc = to_virt_chan(tx->chan); 836 struct pxad_chan *chan = to_pxad_chan(&vc->chan); 837 struct virt_dma_desc *vd_chained = NULL, 838 *vd = container_of(tx, struct virt_dma_desc, tx); 839 dma_cookie_t cookie; 840 unsigned long flags; 841 842 set_updater_desc(to_pxad_sw_desc(vd), tx->flags); 843 844 spin_lock_irqsave(&vc->lock, flags); 845 cookie = dma_cookie_assign(tx); 846 847 if (list_empty(&vc->desc_submitted) && pxad_try_hotchain(vc, vd)) { 848 list_move_tail(&vd->node, &vc->desc_issued); 849 dev_dbg(&chan->vc.chan.dev->device, 850 "%s(): txd %p[%x]: submitted (hot linked)\n", 851 __func__, vd, cookie); 852 goto out; 853 } 854 855 /* 856 * Fallback to placing the tx in the submitted queue 857 */ 858 if (!list_empty(&vc->desc_submitted)) { 859 vd_chained = list_entry(vc->desc_submitted.prev, 860 struct virt_dma_desc, node); 861 /* 862 * Only chain the descriptors if no new misalignment is 863 * introduced. If a new misalignment is chained, let the channel 864 * stop, and be relaunched in misalign mode from the irq 865 * handler. 866 */ 867 if (chan->misaligned || !to_pxad_sw_desc(vd)->misaligned) 868 pxad_desc_chain(vd_chained, vd); 869 else 870 vd_chained = NULL; 871 } 872 dev_dbg(&chan->vc.chan.dev->device, 873 "%s(): txd %p[%x]: submitted (%s linked)\n", 874 __func__, vd, cookie, vd_chained ? "cold" : "not"); 875 list_move_tail(&vd->node, &vc->desc_submitted); 876 chan->misaligned |= to_pxad_sw_desc(vd)->misaligned; 877 878 out: 879 spin_unlock_irqrestore(&vc->lock, flags); 880 return cookie; 881 } 882 883 static void pxad_issue_pending(struct dma_chan *dchan) 884 { 885 struct pxad_chan *chan = to_pxad_chan(dchan); 886 struct virt_dma_desc *vd_first; 887 unsigned long flags; 888 889 spin_lock_irqsave(&chan->vc.lock, flags); 890 if (list_empty(&chan->vc.desc_submitted)) 891 goto out; 892 893 vd_first = list_first_entry(&chan->vc.desc_submitted, 894 struct virt_dma_desc, node); 895 dev_dbg(&chan->vc.chan.dev->device, 896 "%s(): txd %p[%x]", __func__, vd_first, vd_first->tx.cookie); 897 898 vchan_issue_pending(&chan->vc); 899 if (!pxad_try_hotchain(&chan->vc, vd_first)) 900 pxad_launch_chan(chan, to_pxad_sw_desc(vd_first)); 901 out: 902 spin_unlock_irqrestore(&chan->vc.lock, flags); 903 } 904 905 static inline struct dma_async_tx_descriptor * 906 pxad_tx_prep(struct virt_dma_chan *vc, struct virt_dma_desc *vd, 907 unsigned long tx_flags) 908 { 909 struct dma_async_tx_descriptor *tx; 910 struct pxad_chan *chan = container_of(vc, struct pxad_chan, vc); 911 912 INIT_LIST_HEAD(&vd->node); 913 tx = vchan_tx_prep(vc, vd, tx_flags); 914 tx->tx_submit = pxad_tx_submit; 915 dev_dbg(&chan->vc.chan.dev->device, 916 "%s(): vc=%p txd=%p[%x] flags=0x%lx\n", __func__, 917 vc, vd, vd->tx.cookie, 918 tx_flags); 919 920 return tx; 921 } 922 923 static void pxad_get_config(struct pxad_chan *chan, 924 enum dma_transfer_direction dir, 925 u32 *dcmd, u32 *dev_src, u32 *dev_dst) 926 { 927 u32 maxburst = 0, dev_addr = 0; 928 enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 929 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); 930 931 *dcmd = 0; 932 if (dir == DMA_DEV_TO_MEM) { 933 maxburst = chan->cfg.src_maxburst; 934 width = chan->cfg.src_addr_width; 935 dev_addr = chan->cfg.src_addr; 936 *dev_src = dev_addr; 937 *dcmd |= PXA_DCMD_INCTRGADDR; 938 if (chan->drcmr <= pdev->nr_requestors) 939 *dcmd |= PXA_DCMD_FLOWSRC; 940 } 941 if (dir == DMA_MEM_TO_DEV) { 942 maxburst = chan->cfg.dst_maxburst; 943 width = chan->cfg.dst_addr_width; 944 dev_addr = chan->cfg.dst_addr; 945 *dev_dst = dev_addr; 946 *dcmd |= PXA_DCMD_INCSRCADDR; 947 if (chan->drcmr <= pdev->nr_requestors) 948 *dcmd |= PXA_DCMD_FLOWTRG; 949 } 950 if (dir == DMA_MEM_TO_MEM) 951 *dcmd |= PXA_DCMD_BURST32 | PXA_DCMD_INCTRGADDR | 952 PXA_DCMD_INCSRCADDR; 953 954 dev_dbg(&chan->vc.chan.dev->device, 955 "%s(): dev_addr=0x%x maxburst=%d width=%d dir=%d\n", 956 __func__, dev_addr, maxburst, width, dir); 957 958 if (width == DMA_SLAVE_BUSWIDTH_1_BYTE) 959 *dcmd |= PXA_DCMD_WIDTH1; 960 else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES) 961 *dcmd |= PXA_DCMD_WIDTH2; 962 else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES) 963 *dcmd |= PXA_DCMD_WIDTH4; 964 965 if (maxburst == 8) 966 *dcmd |= PXA_DCMD_BURST8; 967 else if (maxburst == 16) 968 *dcmd |= PXA_DCMD_BURST16; 969 else if (maxburst == 32) 970 *dcmd |= PXA_DCMD_BURST32; 971 972 /* FIXME: drivers should be ported over to use the filter 973 * function. Once that's done, the following two lines can 974 * be removed. 975 */ 976 if (chan->cfg.slave_id) 977 chan->drcmr = chan->cfg.slave_id; 978 } 979 980 static struct dma_async_tx_descriptor * 981 pxad_prep_memcpy(struct dma_chan *dchan, 982 dma_addr_t dma_dst, dma_addr_t dma_src, 983 size_t len, unsigned long flags) 984 { 985 struct pxad_chan *chan = to_pxad_chan(dchan); 986 struct pxad_desc_sw *sw_desc; 987 struct pxad_desc_hw *hw_desc; 988 u32 dcmd; 989 unsigned int i, nb_desc = 0; 990 size_t copy; 991 992 if (!dchan || !len) 993 return NULL; 994 995 dev_dbg(&chan->vc.chan.dev->device, 996 "%s(): dma_dst=0x%lx dma_src=0x%lx len=%zu flags=%lx\n", 997 __func__, (unsigned long)dma_dst, (unsigned long)dma_src, 998 len, flags); 999 pxad_get_config(chan, DMA_MEM_TO_MEM, &dcmd, NULL, NULL); 1000 1001 nb_desc = DIV_ROUND_UP(len, PDMA_MAX_DESC_BYTES); 1002 sw_desc = pxad_alloc_desc(chan, nb_desc + 1); 1003 if (!sw_desc) 1004 return NULL; 1005 sw_desc->len = len; 1006 1007 if (!IS_ALIGNED(dma_src, 1 << PDMA_ALIGNMENT) || 1008 !IS_ALIGNED(dma_dst, 1 << PDMA_ALIGNMENT)) 1009 sw_desc->misaligned = true; 1010 1011 i = 0; 1012 do { 1013 hw_desc = sw_desc->hw_desc[i++]; 1014 copy = min_t(size_t, len, PDMA_MAX_DESC_BYTES); 1015 hw_desc->dcmd = dcmd | (PXA_DCMD_LENGTH & copy); 1016 hw_desc->dsadr = dma_src; 1017 hw_desc->dtadr = dma_dst; 1018 len -= copy; 1019 dma_src += copy; 1020 dma_dst += copy; 1021 } while (len); 1022 set_updater_desc(sw_desc, flags); 1023 1024 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags); 1025 } 1026 1027 static struct dma_async_tx_descriptor * 1028 pxad_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, 1029 unsigned int sg_len, enum dma_transfer_direction dir, 1030 unsigned long flags, void *context) 1031 { 1032 struct pxad_chan *chan = to_pxad_chan(dchan); 1033 struct pxad_desc_sw *sw_desc; 1034 size_t len, avail; 1035 struct scatterlist *sg; 1036 dma_addr_t dma; 1037 u32 dcmd, dsadr = 0, dtadr = 0; 1038 unsigned int nb_desc = 0, i, j = 0; 1039 1040 if ((sgl == NULL) || (sg_len == 0)) 1041 return NULL; 1042 1043 pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr); 1044 dev_dbg(&chan->vc.chan.dev->device, 1045 "%s(): dir=%d flags=%lx\n", __func__, dir, flags); 1046 1047 for_each_sg(sgl, sg, sg_len, i) 1048 nb_desc += DIV_ROUND_UP(sg_dma_len(sg), PDMA_MAX_DESC_BYTES); 1049 sw_desc = pxad_alloc_desc(chan, nb_desc + 1); 1050 if (!sw_desc) 1051 return NULL; 1052 1053 for_each_sg(sgl, sg, sg_len, i) { 1054 dma = sg_dma_address(sg); 1055 avail = sg_dma_len(sg); 1056 sw_desc->len += avail; 1057 1058 do { 1059 len = min_t(size_t, avail, PDMA_MAX_DESC_BYTES); 1060 if (dma & 0x7) 1061 sw_desc->misaligned = true; 1062 1063 sw_desc->hw_desc[j]->dcmd = 1064 dcmd | (PXA_DCMD_LENGTH & len); 1065 sw_desc->hw_desc[j]->dsadr = dsadr ? dsadr : dma; 1066 sw_desc->hw_desc[j++]->dtadr = dtadr ? dtadr : dma; 1067 1068 dma += len; 1069 avail -= len; 1070 } while (avail); 1071 } 1072 set_updater_desc(sw_desc, flags); 1073 1074 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags); 1075 } 1076 1077 static struct dma_async_tx_descriptor * 1078 pxad_prep_dma_cyclic(struct dma_chan *dchan, 1079 dma_addr_t buf_addr, size_t len, size_t period_len, 1080 enum dma_transfer_direction dir, unsigned long flags) 1081 { 1082 struct pxad_chan *chan = to_pxad_chan(dchan); 1083 struct pxad_desc_sw *sw_desc; 1084 struct pxad_desc_hw **phw_desc; 1085 dma_addr_t dma; 1086 u32 dcmd, dsadr = 0, dtadr = 0; 1087 unsigned int nb_desc = 0; 1088 1089 if (!dchan || !len || !period_len) 1090 return NULL; 1091 if ((dir != DMA_DEV_TO_MEM) && (dir != DMA_MEM_TO_DEV)) { 1092 dev_err(&chan->vc.chan.dev->device, 1093 "Unsupported direction for cyclic DMA\n"); 1094 return NULL; 1095 } 1096 /* the buffer length must be a multiple of period_len */ 1097 if (len % period_len != 0 || period_len > PDMA_MAX_DESC_BYTES || 1098 !IS_ALIGNED(period_len, 1 << PDMA_ALIGNMENT)) 1099 return NULL; 1100 1101 pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr); 1102 dcmd |= PXA_DCMD_ENDIRQEN | (PXA_DCMD_LENGTH & period_len); 1103 dev_dbg(&chan->vc.chan.dev->device, 1104 "%s(): buf_addr=0x%lx len=%zu period=%zu dir=%d flags=%lx\n", 1105 __func__, (unsigned long)buf_addr, len, period_len, dir, flags); 1106 1107 nb_desc = DIV_ROUND_UP(period_len, PDMA_MAX_DESC_BYTES); 1108 nb_desc *= DIV_ROUND_UP(len, period_len); 1109 sw_desc = pxad_alloc_desc(chan, nb_desc + 1); 1110 if (!sw_desc) 1111 return NULL; 1112 sw_desc->cyclic = true; 1113 sw_desc->len = len; 1114 1115 phw_desc = sw_desc->hw_desc; 1116 dma = buf_addr; 1117 do { 1118 phw_desc[0]->dsadr = dsadr ? dsadr : dma; 1119 phw_desc[0]->dtadr = dtadr ? dtadr : dma; 1120 phw_desc[0]->dcmd = dcmd; 1121 phw_desc++; 1122 dma += period_len; 1123 len -= period_len; 1124 } while (len); 1125 set_updater_desc(sw_desc, flags); 1126 1127 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags); 1128 } 1129 1130 static int pxad_config(struct dma_chan *dchan, 1131 struct dma_slave_config *cfg) 1132 { 1133 struct pxad_chan *chan = to_pxad_chan(dchan); 1134 1135 if (!dchan) 1136 return -EINVAL; 1137 1138 chan->cfg = *cfg; 1139 return 0; 1140 } 1141 1142 static int pxad_terminate_all(struct dma_chan *dchan) 1143 { 1144 struct pxad_chan *chan = to_pxad_chan(dchan); 1145 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); 1146 struct virt_dma_desc *vd = NULL; 1147 unsigned long flags; 1148 struct pxad_phy *phy; 1149 LIST_HEAD(head); 1150 1151 dev_dbg(&chan->vc.chan.dev->device, 1152 "%s(): vchan %p: terminate all\n", __func__, &chan->vc); 1153 1154 spin_lock_irqsave(&chan->vc.lock, flags); 1155 vchan_get_all_descriptors(&chan->vc, &head); 1156 1157 list_for_each_entry(vd, &head, node) { 1158 dev_dbg(&chan->vc.chan.dev->device, 1159 "%s(): cancelling txd %p[%x] (completed=%d)", __func__, 1160 vd, vd->tx.cookie, is_desc_completed(vd)); 1161 } 1162 1163 phy = chan->phy; 1164 if (phy) { 1165 phy_disable(chan->phy); 1166 pxad_free_phy(chan); 1167 chan->phy = NULL; 1168 spin_lock(&pdev->phy_lock); 1169 phy->vchan = NULL; 1170 spin_unlock(&pdev->phy_lock); 1171 } 1172 spin_unlock_irqrestore(&chan->vc.lock, flags); 1173 vchan_dma_desc_free_list(&chan->vc, &head); 1174 1175 return 0; 1176 } 1177 1178 static unsigned int pxad_residue(struct pxad_chan *chan, 1179 dma_cookie_t cookie) 1180 { 1181 struct virt_dma_desc *vd = NULL; 1182 struct pxad_desc_sw *sw_desc = NULL; 1183 struct pxad_desc_hw *hw_desc = NULL; 1184 u32 curr, start, len, end, residue = 0; 1185 unsigned long flags; 1186 bool passed = false; 1187 int i; 1188 1189 /* 1190 * If the channel does not have a phy pointer anymore, it has already 1191 * been completed. Therefore, its residue is 0. 1192 */ 1193 if (!chan->phy) 1194 return 0; 1195 1196 spin_lock_irqsave(&chan->vc.lock, flags); 1197 1198 vd = vchan_find_desc(&chan->vc, cookie); 1199 if (!vd) 1200 goto out; 1201 1202 sw_desc = to_pxad_sw_desc(vd); 1203 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR) 1204 curr = phy_readl_relaxed(chan->phy, DSADR); 1205 else 1206 curr = phy_readl_relaxed(chan->phy, DTADR); 1207 1208 /* 1209 * curr has to be actually read before checking descriptor 1210 * completion, so that a curr inside a status updater 1211 * descriptor implies the following test returns true, and 1212 * preventing reordering of curr load and the test. 1213 */ 1214 rmb(); 1215 if (is_desc_completed(vd)) 1216 goto out; 1217 1218 for (i = 0; i < sw_desc->nb_desc - 1; i++) { 1219 hw_desc = sw_desc->hw_desc[i]; 1220 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR) 1221 start = hw_desc->dsadr; 1222 else 1223 start = hw_desc->dtadr; 1224 len = hw_desc->dcmd & PXA_DCMD_LENGTH; 1225 end = start + len; 1226 1227 /* 1228 * 'passed' will be latched once we found the descriptor 1229 * which lies inside the boundaries of the curr 1230 * pointer. All descriptors that occur in the list 1231 * _after_ we found that partially handled descriptor 1232 * are still to be processed and are hence added to the 1233 * residual bytes counter. 1234 */ 1235 1236 if (passed) { 1237 residue += len; 1238 } else if (curr >= start && curr <= end) { 1239 residue += end - curr; 1240 passed = true; 1241 } 1242 } 1243 if (!passed) 1244 residue = sw_desc->len; 1245 1246 out: 1247 spin_unlock_irqrestore(&chan->vc.lock, flags); 1248 dev_dbg(&chan->vc.chan.dev->device, 1249 "%s(): txd %p[%x] sw_desc=%p: %d\n", 1250 __func__, vd, cookie, sw_desc, residue); 1251 return residue; 1252 } 1253 1254 static enum dma_status pxad_tx_status(struct dma_chan *dchan, 1255 dma_cookie_t cookie, 1256 struct dma_tx_state *txstate) 1257 { 1258 struct pxad_chan *chan = to_pxad_chan(dchan); 1259 enum dma_status ret; 1260 1261 if (cookie == chan->bus_error) 1262 return DMA_ERROR; 1263 1264 ret = dma_cookie_status(dchan, cookie, txstate); 1265 if (likely(txstate && (ret != DMA_ERROR))) 1266 dma_set_residue(txstate, pxad_residue(chan, cookie)); 1267 1268 return ret; 1269 } 1270 1271 static void pxad_free_channels(struct dma_device *dmadev) 1272 { 1273 struct pxad_chan *c, *cn; 1274 1275 list_for_each_entry_safe(c, cn, &dmadev->channels, 1276 vc.chan.device_node) { 1277 list_del(&c->vc.chan.device_node); 1278 tasklet_kill(&c->vc.task); 1279 } 1280 } 1281 1282 static int pxad_remove(struct platform_device *op) 1283 { 1284 struct pxad_device *pdev = platform_get_drvdata(op); 1285 1286 pxad_cleanup_debugfs(pdev); 1287 pxad_free_channels(&pdev->slave); 1288 dma_async_device_unregister(&pdev->slave); 1289 return 0; 1290 } 1291 1292 static int pxad_init_phys(struct platform_device *op, 1293 struct pxad_device *pdev, 1294 unsigned int nb_phy_chans) 1295 { 1296 int irq0, irq, nr_irq = 0, i, ret; 1297 struct pxad_phy *phy; 1298 1299 irq0 = platform_get_irq(op, 0); 1300 if (irq0 < 0) 1301 return irq0; 1302 1303 pdev->phys = devm_kcalloc(&op->dev, nb_phy_chans, 1304 sizeof(pdev->phys[0]), GFP_KERNEL); 1305 if (!pdev->phys) 1306 return -ENOMEM; 1307 1308 for (i = 0; i < nb_phy_chans; i++) 1309 if (platform_get_irq(op, i) > 0) 1310 nr_irq++; 1311 1312 for (i = 0; i < nb_phy_chans; i++) { 1313 phy = &pdev->phys[i]; 1314 phy->base = pdev->base; 1315 phy->idx = i; 1316 irq = platform_get_irq(op, i); 1317 if ((nr_irq > 1) && (irq > 0)) 1318 ret = devm_request_irq(&op->dev, irq, 1319 pxad_chan_handler, 1320 IRQF_SHARED, "pxa-dma", phy); 1321 if ((nr_irq == 1) && (i == 0)) 1322 ret = devm_request_irq(&op->dev, irq0, 1323 pxad_int_handler, 1324 IRQF_SHARED, "pxa-dma", pdev); 1325 if (ret) { 1326 dev_err(pdev->slave.dev, 1327 "%s(): can't request irq %d:%d\n", __func__, 1328 irq, ret); 1329 return ret; 1330 } 1331 } 1332 1333 return 0; 1334 } 1335 1336 static const struct of_device_id pxad_dt_ids[] = { 1337 { .compatible = "marvell,pdma-1.0", }, 1338 {} 1339 }; 1340 MODULE_DEVICE_TABLE(of, pxad_dt_ids); 1341 1342 static struct dma_chan *pxad_dma_xlate(struct of_phandle_args *dma_spec, 1343 struct of_dma *ofdma) 1344 { 1345 struct pxad_device *d = ofdma->of_dma_data; 1346 struct dma_chan *chan; 1347 1348 chan = dma_get_any_slave_channel(&d->slave); 1349 if (!chan) 1350 return NULL; 1351 1352 to_pxad_chan(chan)->drcmr = dma_spec->args[0]; 1353 to_pxad_chan(chan)->prio = dma_spec->args[1]; 1354 1355 return chan; 1356 } 1357 1358 static int pxad_init_dmadev(struct platform_device *op, 1359 struct pxad_device *pdev, 1360 unsigned int nr_phy_chans, 1361 unsigned int nr_requestors) 1362 { 1363 int ret; 1364 unsigned int i; 1365 struct pxad_chan *c; 1366 1367 pdev->nr_chans = nr_phy_chans; 1368 pdev->nr_requestors = nr_requestors; 1369 INIT_LIST_HEAD(&pdev->slave.channels); 1370 pdev->slave.device_alloc_chan_resources = pxad_alloc_chan_resources; 1371 pdev->slave.device_free_chan_resources = pxad_free_chan_resources; 1372 pdev->slave.device_tx_status = pxad_tx_status; 1373 pdev->slave.device_issue_pending = pxad_issue_pending; 1374 pdev->slave.device_config = pxad_config; 1375 pdev->slave.device_terminate_all = pxad_terminate_all; 1376 1377 if (op->dev.coherent_dma_mask) 1378 dma_set_mask(&op->dev, op->dev.coherent_dma_mask); 1379 else 1380 dma_set_mask(&op->dev, DMA_BIT_MASK(32)); 1381 1382 ret = pxad_init_phys(op, pdev, nr_phy_chans); 1383 if (ret) 1384 return ret; 1385 1386 for (i = 0; i < nr_phy_chans; i++) { 1387 c = devm_kzalloc(&op->dev, sizeof(*c), GFP_KERNEL); 1388 if (!c) 1389 return -ENOMEM; 1390 c->vc.desc_free = pxad_free_desc; 1391 vchan_init(&c->vc, &pdev->slave); 1392 } 1393 1394 return dma_async_device_register(&pdev->slave); 1395 } 1396 1397 static int pxad_probe(struct platform_device *op) 1398 { 1399 struct pxad_device *pdev; 1400 const struct of_device_id *of_id; 1401 struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev); 1402 struct resource *iores; 1403 int ret, dma_channels = 0, nb_requestors = 0; 1404 const enum dma_slave_buswidth widths = 1405 DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES | 1406 DMA_SLAVE_BUSWIDTH_4_BYTES; 1407 1408 pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL); 1409 if (!pdev) 1410 return -ENOMEM; 1411 1412 spin_lock_init(&pdev->phy_lock); 1413 1414 iores = platform_get_resource(op, IORESOURCE_MEM, 0); 1415 pdev->base = devm_ioremap_resource(&op->dev, iores); 1416 if (IS_ERR(pdev->base)) 1417 return PTR_ERR(pdev->base); 1418 1419 of_id = of_match_device(pxad_dt_ids, &op->dev); 1420 if (of_id) { 1421 of_property_read_u32(op->dev.of_node, "#dma-channels", 1422 &dma_channels); 1423 ret = of_property_read_u32(op->dev.of_node, "#dma-requests", 1424 &nb_requestors); 1425 if (ret) { 1426 dev_warn(pdev->slave.dev, 1427 "#dma-requests set to default 32 as missing in OF: %d", 1428 ret); 1429 nb_requestors = 32; 1430 }; 1431 } else if (pdata && pdata->dma_channels) { 1432 dma_channels = pdata->dma_channels; 1433 nb_requestors = pdata->nb_requestors; 1434 } else { 1435 dma_channels = 32; /* default 32 channel */ 1436 } 1437 1438 dma_cap_set(DMA_SLAVE, pdev->slave.cap_mask); 1439 dma_cap_set(DMA_MEMCPY, pdev->slave.cap_mask); 1440 dma_cap_set(DMA_CYCLIC, pdev->slave.cap_mask); 1441 dma_cap_set(DMA_PRIVATE, pdev->slave.cap_mask); 1442 pdev->slave.device_prep_dma_memcpy = pxad_prep_memcpy; 1443 pdev->slave.device_prep_slave_sg = pxad_prep_slave_sg; 1444 pdev->slave.device_prep_dma_cyclic = pxad_prep_dma_cyclic; 1445 1446 pdev->slave.copy_align = PDMA_ALIGNMENT; 1447 pdev->slave.src_addr_widths = widths; 1448 pdev->slave.dst_addr_widths = widths; 1449 pdev->slave.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); 1450 pdev->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; 1451 pdev->slave.descriptor_reuse = true; 1452 1453 pdev->slave.dev = &op->dev; 1454 ret = pxad_init_dmadev(op, pdev, dma_channels, nb_requestors); 1455 if (ret) { 1456 dev_err(pdev->slave.dev, "unable to register\n"); 1457 return ret; 1458 } 1459 1460 if (op->dev.of_node) { 1461 /* Device-tree DMA controller registration */ 1462 ret = of_dma_controller_register(op->dev.of_node, 1463 pxad_dma_xlate, pdev); 1464 if (ret < 0) { 1465 dev_err(pdev->slave.dev, 1466 "of_dma_controller_register failed\n"); 1467 return ret; 1468 } 1469 } 1470 1471 platform_set_drvdata(op, pdev); 1472 pxad_init_debugfs(pdev); 1473 dev_info(pdev->slave.dev, "initialized %d channels on %d requestors\n", 1474 dma_channels, nb_requestors); 1475 return 0; 1476 } 1477 1478 static const struct platform_device_id pxad_id_table[] = { 1479 { "pxa-dma", }, 1480 { }, 1481 }; 1482 1483 static struct platform_driver pxad_driver = { 1484 .driver = { 1485 .name = "pxa-dma", 1486 .of_match_table = pxad_dt_ids, 1487 }, 1488 .id_table = pxad_id_table, 1489 .probe = pxad_probe, 1490 .remove = pxad_remove, 1491 }; 1492 1493 bool pxad_filter_fn(struct dma_chan *chan, void *param) 1494 { 1495 struct pxad_chan *c = to_pxad_chan(chan); 1496 struct pxad_param *p = param; 1497 1498 if (chan->device->dev->driver != &pxad_driver.driver) 1499 return false; 1500 1501 c->drcmr = p->drcmr; 1502 c->prio = p->prio; 1503 1504 return true; 1505 } 1506 EXPORT_SYMBOL_GPL(pxad_filter_fn); 1507 1508 int pxad_toggle_reserved_channel(int legacy_channel) 1509 { 1510 if (legacy_unavailable & (BIT(legacy_channel))) 1511 return -EBUSY; 1512 legacy_reserved ^= BIT(legacy_channel); 1513 return 0; 1514 } 1515 EXPORT_SYMBOL_GPL(pxad_toggle_reserved_channel); 1516 1517 module_platform_driver(pxad_driver); 1518 1519 MODULE_DESCRIPTION("Marvell PXA Peripheral DMA Driver"); 1520 MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>"); 1521 MODULE_LICENSE("GPL v2"); 1522