1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * AMD Passthru DMA device driver 4 * -- Based on the CCP driver 5 * 6 * Copyright (C) 2016,2021 Advanced Micro Devices, Inc. 7 * 8 * Author: Sanjay R Mehta <sanju.mehta@amd.com> 9 * Author: Tom Lendacky <thomas.lendacky@amd.com> 10 * Author: Gary R Hook <gary.hook@amd.com> 11 */ 12 13 #ifndef __PT_DEV_H__ 14 #define __PT_DEV_H__ 15 16 #include <linux/device.h> 17 #include <linux/dmaengine.h> 18 #include <linux/pci.h> 19 #include <linux/spinlock.h> 20 #include <linux/mutex.h> 21 #include <linux/list.h> 22 #include <linux/wait.h> 23 #include <linux/dmapool.h> 24 25 #include "../virt-dma.h" 26 27 #define MAX_PT_NAME_LEN 16 28 #define MAX_DMAPOOL_NAME_LEN 32 29 30 #define MAX_HW_QUEUES 1 31 #define MAX_CMD_QLEN 100 32 33 #define PT_ENGINE_PASSTHRU 5 34 #define PT_OFFSET 0x0 35 36 /* Register Mappings */ 37 #define IRQ_MASK_REG 0x040 38 #define IRQ_STATUS_REG 0x200 39 40 #define CMD_Q_ERROR(__qs) ((__qs) & 0x0000003f) 41 42 #define CMD_QUEUE_PRIO_OFFSET 0x00 43 #define CMD_REQID_CONFIG_OFFSET 0x04 44 #define CMD_TIMEOUT_OFFSET 0x08 45 #define CMD_PT_VERSION 0x10 46 47 #define CMD_Q_CONTROL_BASE 0x0000 48 #define CMD_Q_TAIL_LO_BASE 0x0004 49 #define CMD_Q_HEAD_LO_BASE 0x0008 50 #define CMD_Q_INT_ENABLE_BASE 0x000C 51 #define CMD_Q_INTERRUPT_STATUS_BASE 0x0010 52 53 #define CMD_Q_STATUS_BASE 0x0100 54 #define CMD_Q_INT_STATUS_BASE 0x0104 55 #define CMD_Q_DMA_STATUS_BASE 0x0108 56 #define CMD_Q_DMA_READ_STATUS_BASE 0x010C 57 #define CMD_Q_DMA_WRITE_STATUS_BASE 0x0110 58 #define CMD_Q_ABORT_BASE 0x0114 59 #define CMD_Q_AX_CACHE_BASE 0x0118 60 61 #define CMD_CONFIG_OFFSET 0x1120 62 #define CMD_CLK_GATE_CTL_OFFSET 0x6004 63 64 #define CMD_DESC_DW0_VAL 0x500012 65 66 /* Address offset for virtual queue registers */ 67 #define CMD_Q_STATUS_INCR 0x1000 68 69 /* Bit masks */ 70 #define CMD_CONFIG_REQID 0 71 #define CMD_TIMEOUT_DISABLE 0 72 #define CMD_CLK_DYN_GATING_DIS 0 73 #define CMD_CLK_SW_GATE_MODE 0 74 #define CMD_CLK_GATE_CTL 0 75 #define CMD_QUEUE_PRIO GENMASK(2, 1) 76 #define CMD_CONFIG_VHB_EN BIT(0) 77 #define CMD_CLK_DYN_GATING_EN BIT(0) 78 #define CMD_CLK_HW_GATE_MODE BIT(0) 79 #define CMD_CLK_GATE_ON_DELAY BIT(12) 80 #define CMD_CLK_GATE_OFF_DELAY BIT(12) 81 82 #define CMD_CLK_GATE_CONFIG (CMD_CLK_GATE_CTL | \ 83 CMD_CLK_HW_GATE_MODE | \ 84 CMD_CLK_GATE_ON_DELAY | \ 85 CMD_CLK_DYN_GATING_EN | \ 86 CMD_CLK_GATE_OFF_DELAY) 87 88 #define CMD_Q_LEN 32 89 #define CMD_Q_RUN BIT(0) 90 #define CMD_Q_HALT BIT(1) 91 #define CMD_Q_MEM_LOCATION BIT(2) 92 #define CMD_Q_SIZE_MASK GENMASK(4, 0) 93 #define CMD_Q_SIZE GENMASK(7, 3) 94 #define CMD_Q_SHIFT GENMASK(1, 0) 95 #define QUEUE_SIZE_VAL ((ffs(CMD_Q_LEN) - 2) & \ 96 CMD_Q_SIZE_MASK) 97 #define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1) 98 #define Q_DESC_SIZE sizeof(struct ptdma_desc) 99 #define Q_SIZE(n) (CMD_Q_LEN * (n)) 100 101 #define INT_COMPLETION BIT(0) 102 #define INT_ERROR BIT(1) 103 #define INT_QUEUE_STOPPED BIT(2) 104 #define INT_EMPTY_QUEUE BIT(3) 105 #define SUPPORTED_INTERRUPTS (INT_COMPLETION | INT_ERROR) 106 107 /****** Local Storage Block ******/ 108 #define LSB_START 0 109 #define LSB_END 127 110 #define LSB_COUNT (LSB_END - LSB_START + 1) 111 112 #define PT_DMAPOOL_MAX_SIZE 64 113 #define PT_DMAPOOL_ALIGN BIT(5) 114 115 #define PT_PASSTHRU_BLOCKSIZE 512 116 117 struct pt_device; 118 119 struct pt_tasklet_data { 120 struct completion completion; 121 struct pt_cmd *cmd; 122 }; 123 124 /* 125 * struct pt_passthru_engine - pass-through operation 126 * without performing DMA mapping 127 * @mask: mask to be applied to data 128 * @mask_len: length in bytes of mask 129 * @src_dma: data to be used for this operation 130 * @dst_dma: data produced by this operation 131 * @src_len: length in bytes of data used for this operation 132 * 133 * Variables required to be set when calling pt_enqueue_cmd(): 134 * - bit_mod, byte_swap, src, dst, src_len 135 * - mask, mask_len if bit_mod is not PT_PASSTHRU_BITWISE_NOOP 136 */ 137 struct pt_passthru_engine { 138 dma_addr_t mask; 139 u32 mask_len; /* In bytes */ 140 141 dma_addr_t src_dma, dst_dma; 142 u64 src_len; /* In bytes */ 143 }; 144 145 /* 146 * struct pt_cmd - PTDMA operation request 147 * @entry: list element 148 * @work: work element used for callbacks 149 * @pt: PT device to be run on 150 * @ret: operation return code 151 * @flags: cmd processing flags 152 * @engine: PTDMA operation to perform (passthru) 153 * @engine_error: PT engine return code 154 * @passthru: engine specific structures, refer to specific engine struct below 155 * @callback: operation completion callback function 156 * @data: parameter value to be supplied to the callback function 157 * 158 * Variables required to be set when calling pt_enqueue_cmd(): 159 * - engine, callback 160 * - See the operation structures below for what is required for each 161 * operation. 162 */ 163 struct pt_cmd { 164 struct list_head entry; 165 struct work_struct work; 166 struct pt_device *pt; 167 int ret; 168 u32 engine; 169 u32 engine_error; 170 struct pt_passthru_engine passthru; 171 /* Completion callback support */ 172 void (*pt_cmd_callback)(void *data, int err); 173 void *data; 174 }; 175 176 struct pt_dma_desc { 177 struct virt_dma_desc vd; 178 struct pt_device *pt; 179 enum dma_status status; 180 size_t len; 181 bool issued_to_hw; 182 struct pt_cmd pt_cmd; 183 }; 184 185 struct pt_dma_chan { 186 struct virt_dma_chan vc; 187 struct pt_device *pt; 188 }; 189 190 struct pt_cmd_queue { 191 struct pt_device *pt; 192 193 /* Queue dma pool */ 194 struct dma_pool *dma_pool; 195 196 /* Queue base address (not neccessarily aligned)*/ 197 struct ptdma_desc *qbase; 198 199 /* Aligned queue start address (per requirement) */ 200 struct mutex q_mutex ____cacheline_aligned; 201 unsigned int qidx; 202 203 unsigned int qsize; 204 dma_addr_t qbase_dma; 205 dma_addr_t qdma_tail; 206 207 unsigned int active; 208 unsigned int suspended; 209 210 /* Register addresses for queue */ 211 void __iomem *reg_control; 212 u32 qcontrol; /* Cached control register */ 213 214 /* Status values from job */ 215 u32 int_status; 216 u32 q_status; 217 u32 q_int_status; 218 u32 cmd_error; 219 } ____cacheline_aligned; 220 221 struct pt_device { 222 struct list_head entry; 223 224 unsigned int ord; 225 char name[MAX_PT_NAME_LEN]; 226 227 struct device *dev; 228 229 /* Bus specific device information */ 230 struct pt_msix *pt_msix; 231 232 struct pt_dev_vdata *dev_vdata; 233 234 unsigned int pt_irq; 235 236 /* I/O area used for device communication */ 237 void __iomem *io_regs; 238 239 spinlock_t cmd_lock ____cacheline_aligned; 240 unsigned int cmd_count; 241 struct list_head cmd; 242 243 /* 244 * The command queue. This represent the queue available on the 245 * PTDMA that are available for processing cmds 246 */ 247 struct pt_cmd_queue cmd_q; 248 249 /* Support for the DMA Engine capabilities */ 250 struct dma_device dma_dev; 251 struct pt_dma_chan *pt_dma_chan; 252 struct kmem_cache *dma_cmd_cache; 253 struct kmem_cache *dma_desc_cache; 254 255 wait_queue_head_t lsb_queue; 256 257 struct pt_tasklet_data tdata; 258 }; 259 260 /* 261 * descriptor for PTDMA commands 262 * 8 32-bit words: 263 * word 0: function; engine; control bits 264 * word 1: length of source data 265 * word 2: low 32 bits of source pointer 266 * word 3: upper 16 bits of source pointer; source memory type 267 * word 4: low 32 bits of destination pointer 268 * word 5: upper 16 bits of destination pointer; destination memory type 269 * word 6: reserved 32 bits 270 * word 7: reserved 32 bits 271 */ 272 273 #define DWORD0_SOC BIT(0) 274 #define DWORD0_IOC BIT(1) 275 276 struct dword3 { 277 unsigned int src_hi:16; 278 unsigned int src_mem:2; 279 unsigned int lsb_cxt_id:8; 280 unsigned int rsvd1:5; 281 unsigned int fixed:1; 282 }; 283 284 struct dword5 { 285 unsigned int dst_hi:16; 286 unsigned int dst_mem:2; 287 unsigned int rsvd1:13; 288 unsigned int fixed:1; 289 }; 290 291 struct ptdma_desc { 292 u32 dw0; 293 u32 length; 294 u32 src_lo; 295 struct dword3 dw3; 296 u32 dst_lo; 297 struct dword5 dw5; 298 __le32 rsvd1; 299 __le32 rsvd2; 300 }; 301 302 /* Structure to hold PT device data */ 303 struct pt_dev_vdata { 304 const unsigned int bar; 305 }; 306 307 int pt_dmaengine_register(struct pt_device *pt); 308 void pt_dmaengine_unregister(struct pt_device *pt); 309 310 int pt_core_init(struct pt_device *pt); 311 void pt_core_destroy(struct pt_device *pt); 312 313 int pt_core_perform_passthru(struct pt_cmd_queue *cmd_q, 314 struct pt_passthru_engine *pt_engine); 315 316 void pt_start_queue(struct pt_cmd_queue *cmd_q); 317 void pt_stop_queue(struct pt_cmd_queue *cmd_q); 318 319 #endif 320