xref: /openbmc/linux/drivers/dma/ppc4xx/adma.h (revision 25985edc)
1 /*
2  * 2006-2009 (C) DENX Software Engineering.
3  *
4  * Author: Yuri Tikhonov <yur@emcraft.com>
5  *
6  * This file is licensed under the terms of the GNU General Public License
7  * version 2.  This program is licensed "as is" without any warranty of
8  * any kind, whether express or implied.
9  */
10 
11 #ifndef _PPC440SPE_ADMA_H
12 #define _PPC440SPE_ADMA_H
13 
14 #include <linux/types.h>
15 #include "dma.h"
16 #include "xor.h"
17 
18 #define to_ppc440spe_adma_chan(chan) \
19 		container_of(chan, struct ppc440spe_adma_chan, common)
20 #define to_ppc440spe_adma_device(dev) \
21 		container_of(dev, struct ppc440spe_adma_device, common)
22 #define tx_to_ppc440spe_adma_slot(tx) \
23 		container_of(tx, struct ppc440spe_adma_desc_slot, async_tx)
24 
25 /* Default polynomial (for 440SP is only available) */
26 #define PPC440SPE_DEFAULT_POLY	0x4d
27 
28 #define PPC440SPE_ADMA_ENGINES_NUM	(XOR_ENGINES_NUM + DMA_ENGINES_NUM)
29 
30 #define PPC440SPE_ADMA_WATCHDOG_MSEC	3
31 #define PPC440SPE_ADMA_THRESHOLD	1
32 
33 #define PPC440SPE_DMA0_ID	0
34 #define PPC440SPE_DMA1_ID	1
35 #define PPC440SPE_XOR_ID	2
36 
37 #define PPC440SPE_ADMA_DMA_MAX_BYTE_COUNT	0xFFFFFFUL
38 /* this is the XOR_CBBCR width */
39 #define PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT	(1 << 31)
40 #define PPC440SPE_ADMA_ZERO_SUM_MAX_BYTE_COUNT PPC440SPE_ADMA_XOR_MAX_BYTE_COUNT
41 
42 #define PPC440SPE_RXOR_RUN	0
43 
44 #define MQ0_CF2H_RXOR_BS_MASK	0x1FF
45 
46 #undef ADMA_LL_DEBUG
47 
48 /**
49  * struct ppc440spe_adma_device - internal representation of an ADMA device
50  * @dev: device
51  * @dma_reg: base for DMAx register access
52  * @xor_reg: base for XOR register access
53  * @i2o_reg: base for I2O register access
54  * @id: HW ADMA Device selector
55  * @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
56  * @dma_desc_pool: base of DMA descriptor region (DMA address)
57  * @pool_size: size of the pool
58  * @irq: DMAx or XOR irq number
59  * @err_irq: DMAx error irq number
60  * @common: embedded struct dma_device
61  */
62 struct ppc440spe_adma_device {
63 	struct device *dev;
64 	struct dma_regs __iomem *dma_reg;
65 	struct xor_regs __iomem *xor_reg;
66 	struct i2o_regs __iomem *i2o_reg;
67 	int id;
68 	void *dma_desc_pool_virt;
69 	dma_addr_t dma_desc_pool;
70 	size_t pool_size;
71 	int irq;
72 	int err_irq;
73 	struct dma_device common;
74 };
75 
76 /**
77  * struct ppc440spe_adma_chan - internal representation of an ADMA channel
78  * @lock: serializes enqueue/dequeue operations to the slot pool
79  * @device: parent device
80  * @chain: device chain view of the descriptors
81  * @common: common dmaengine channel object members
82  * @all_slots: complete domain of slots usable by the channel
83  * @pending: allows batching of hardware operations
84  * @completed_cookie: identifier for the most recently completed operation
85  * @slots_allocated: records the actual size of the descriptor slot pool
86  * @hw_chain_inited: h/w descriptor chain initialization flag
87  * @irq_tasklet: bottom half where ppc440spe_adma_slot_cleanup runs
88  * @needs_unmap: if buffers should not be unmapped upon final processing
89  * @pdest_page: P destination page for async validate operation
90  * @qdest_page: Q destination page for async validate operation
91  * @pdest: P dma addr for async validate operation
92  * @qdest: Q dma addr for async validate operation
93  */
94 struct ppc440spe_adma_chan {
95 	spinlock_t lock;
96 	struct ppc440spe_adma_device *device;
97 	struct list_head chain;
98 	struct dma_chan common;
99 	struct list_head all_slots;
100 	struct ppc440spe_adma_desc_slot *last_used;
101 	int pending;
102 	dma_cookie_t completed_cookie;
103 	int slots_allocated;
104 	int hw_chain_inited;
105 	struct tasklet_struct irq_tasklet;
106 	u8 needs_unmap;
107 	struct page *pdest_page;
108 	struct page *qdest_page;
109 	dma_addr_t pdest;
110 	dma_addr_t qdest;
111 };
112 
113 struct ppc440spe_rxor {
114 	u32 addrl;
115 	u32 addrh;
116 	int len;
117 	int xor_count;
118 	int addr_count;
119 	int desc_count;
120 	int state;
121 };
122 
123 /**
124  * struct ppc440spe_adma_desc_slot - PPC440SPE-ADMA software descriptor
125  * @phys: hardware address of the hardware descriptor chain
126  * @group_head: first operation in a transaction
127  * @hw_next: pointer to the next descriptor in chain
128  * @async_tx: support for the async_tx api
129  * @slot_node: node on the iop_adma_chan.all_slots list
130  * @chain_node: node on the op_adma_chan.chain list
131  * @group_list: list of slots that make up a multi-descriptor transaction
132  *              for example transfer lengths larger than the supported hw max
133  * @unmap_len: transaction bytecount
134  * @hw_desc: virtual address of the hardware descriptor chain
135  * @stride: currently chained or not
136  * @idx: pool index
137  * @slot_cnt: total slots used in an transaction (group of operations)
138  * @src_cnt: number of sources set in this descriptor
139  * @dst_cnt: number of destinations set in the descriptor
140  * @slots_per_op: number of slots per operation
141  * @descs_per_op: number of slot per P/Q operation see comment
142  *                for ppc440spe_prep_dma_pqxor function
143  * @flags: desc state/type
144  * @reverse_flags: 1 if a corresponding rxor address uses reversed address order
145  * @xor_check_result: result of zero sum
146  * @crc32_result: result crc calculation
147  */
148 struct ppc440spe_adma_desc_slot {
149 	dma_addr_t phys;
150 	struct ppc440spe_adma_desc_slot *group_head;
151 	struct ppc440spe_adma_desc_slot *hw_next;
152 	struct dma_async_tx_descriptor async_tx;
153 	struct list_head slot_node;
154 	struct list_head chain_node; /* node in channel ops list */
155 	struct list_head group_list; /* list */
156 	unsigned int unmap_len;
157 	void *hw_desc;
158 	u16 stride;
159 	u16 idx;
160 	u16 slot_cnt;
161 	u8 src_cnt;
162 	u8 dst_cnt;
163 	u8 slots_per_op;
164 	u8 descs_per_op;
165 	unsigned long flags;
166 	unsigned long reverse_flags[8];
167 
168 #define PPC440SPE_DESC_INT	0	/* generate interrupt on complete */
169 #define PPC440SPE_ZERO_P	1	/* clear P destionaion */
170 #define PPC440SPE_ZERO_Q	2	/* clear Q destination */
171 #define PPC440SPE_COHERENT	3	/* src/dst are coherent */
172 
173 #define PPC440SPE_DESC_WXOR	4	/* WXORs are in chain */
174 #define PPC440SPE_DESC_RXOR	5	/* RXOR is in chain */
175 
176 #define PPC440SPE_DESC_RXOR123	8	/* CDB for RXOR123 operation */
177 #define PPC440SPE_DESC_RXOR124	9	/* CDB for RXOR124 operation */
178 #define PPC440SPE_DESC_RXOR125	10	/* CDB for RXOR125 operation */
179 #define PPC440SPE_DESC_RXOR12	11	/* CDB for RXOR12 operation */
180 #define PPC440SPE_DESC_RXOR_REV	12	/* CDB has srcs in reversed order */
181 
182 #define PPC440SPE_DESC_PCHECK	13
183 #define PPC440SPE_DESC_QCHECK	14
184 
185 #define PPC440SPE_DESC_RXOR_MSK	0x3
186 
187 	struct ppc440spe_rxor rxor_cursor;
188 
189 	union {
190 		u32 *xor_check_result;
191 		u32 *crc32_result;
192 	};
193 };
194 
195 #endif /* _PPC440SPE_ADMA_H */
196