1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com 5 * 6 * Copyright (C) 2010 Samsung Electronics Co. Ltd. 7 * Jaswinder Singh <jassi.brar@samsung.com> 8 */ 9 10 #include <linux/debugfs.h> 11 #include <linux/kernel.h> 12 #include <linux/io.h> 13 #include <linux/init.h> 14 #include <linux/slab.h> 15 #include <linux/module.h> 16 #include <linux/string.h> 17 #include <linux/delay.h> 18 #include <linux/interrupt.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/dmaengine.h> 21 #include <linux/amba/bus.h> 22 #include <linux/scatterlist.h> 23 #include <linux/of.h> 24 #include <linux/of_dma.h> 25 #include <linux/err.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/bug.h> 28 #include <linux/reset.h> 29 30 #include "dmaengine.h" 31 #define PL330_MAX_CHAN 8 32 #define PL330_MAX_IRQS 32 33 #define PL330_MAX_PERI 32 34 #define PL330_MAX_BURST 16 35 36 #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0) 37 #define PL330_QUIRK_PERIPH_BURST BIT(1) 38 39 enum pl330_cachectrl { 40 CCTRL0, /* Noncacheable and nonbufferable */ 41 CCTRL1, /* Bufferable only */ 42 CCTRL2, /* Cacheable, but do not allocate */ 43 CCTRL3, /* Cacheable and bufferable, but do not allocate */ 44 INVALID1, /* AWCACHE = 0x1000 */ 45 INVALID2, 46 CCTRL6, /* Cacheable write-through, allocate on writes only */ 47 CCTRL7, /* Cacheable write-back, allocate on writes only */ 48 }; 49 50 enum pl330_byteswap { 51 SWAP_NO, 52 SWAP_2, 53 SWAP_4, 54 SWAP_8, 55 SWAP_16, 56 }; 57 58 /* Register and Bit field Definitions */ 59 #define DS 0x0 60 #define DS_ST_STOP 0x0 61 #define DS_ST_EXEC 0x1 62 #define DS_ST_CMISS 0x2 63 #define DS_ST_UPDTPC 0x3 64 #define DS_ST_WFE 0x4 65 #define DS_ST_ATBRR 0x5 66 #define DS_ST_QBUSY 0x6 67 #define DS_ST_WFP 0x7 68 #define DS_ST_KILL 0x8 69 #define DS_ST_CMPLT 0x9 70 #define DS_ST_FLTCMP 0xe 71 #define DS_ST_FAULT 0xf 72 73 #define DPC 0x4 74 #define INTEN 0x20 75 #define ES 0x24 76 #define INTSTATUS 0x28 77 #define INTCLR 0x2c 78 #define FSM 0x30 79 #define FSC 0x34 80 #define FTM 0x38 81 82 #define _FTC 0x40 83 #define FTC(n) (_FTC + (n)*0x4) 84 85 #define _CS 0x100 86 #define CS(n) (_CS + (n)*0x8) 87 #define CS_CNS (1 << 21) 88 89 #define _CPC 0x104 90 #define CPC(n) (_CPC + (n)*0x8) 91 92 #define _SA 0x400 93 #define SA(n) (_SA + (n)*0x20) 94 95 #define _DA 0x404 96 #define DA(n) (_DA + (n)*0x20) 97 98 #define _CC 0x408 99 #define CC(n) (_CC + (n)*0x20) 100 101 #define CC_SRCINC (1 << 0) 102 #define CC_DSTINC (1 << 14) 103 #define CC_SRCPRI (1 << 8) 104 #define CC_DSTPRI (1 << 22) 105 #define CC_SRCNS (1 << 9) 106 #define CC_DSTNS (1 << 23) 107 #define CC_SRCIA (1 << 10) 108 #define CC_DSTIA (1 << 24) 109 #define CC_SRCBRSTLEN_SHFT 4 110 #define CC_DSTBRSTLEN_SHFT 18 111 #define CC_SRCBRSTSIZE_SHFT 1 112 #define CC_DSTBRSTSIZE_SHFT 15 113 #define CC_SRCCCTRL_SHFT 11 114 #define CC_SRCCCTRL_MASK 0x7 115 #define CC_DSTCCTRL_SHFT 25 116 #define CC_DRCCCTRL_MASK 0x7 117 #define CC_SWAP_SHFT 28 118 119 #define _LC0 0x40c 120 #define LC0(n) (_LC0 + (n)*0x20) 121 122 #define _LC1 0x410 123 #define LC1(n) (_LC1 + (n)*0x20) 124 125 #define DBGSTATUS 0xd00 126 #define DBG_BUSY (1 << 0) 127 128 #define DBGCMD 0xd04 129 #define DBGINST0 0xd08 130 #define DBGINST1 0xd0c 131 132 #define CR0 0xe00 133 #define CR1 0xe04 134 #define CR2 0xe08 135 #define CR3 0xe0c 136 #define CR4 0xe10 137 #define CRD 0xe14 138 139 #define PERIPH_ID 0xfe0 140 #define PERIPH_REV_SHIFT 20 141 #define PERIPH_REV_MASK 0xf 142 #define PERIPH_REV_R0P0 0 143 #define PERIPH_REV_R1P0 1 144 #define PERIPH_REV_R1P1 2 145 146 #define CR0_PERIPH_REQ_SET (1 << 0) 147 #define CR0_BOOT_EN_SET (1 << 1) 148 #define CR0_BOOT_MAN_NS (1 << 2) 149 #define CR0_NUM_CHANS_SHIFT 4 150 #define CR0_NUM_CHANS_MASK 0x7 151 #define CR0_NUM_PERIPH_SHIFT 12 152 #define CR0_NUM_PERIPH_MASK 0x1f 153 #define CR0_NUM_EVENTS_SHIFT 17 154 #define CR0_NUM_EVENTS_MASK 0x1f 155 156 #define CR1_ICACHE_LEN_SHIFT 0 157 #define CR1_ICACHE_LEN_MASK 0x7 158 #define CR1_NUM_ICACHELINES_SHIFT 4 159 #define CR1_NUM_ICACHELINES_MASK 0xf 160 161 #define CRD_DATA_WIDTH_SHIFT 0 162 #define CRD_DATA_WIDTH_MASK 0x7 163 #define CRD_WR_CAP_SHIFT 4 164 #define CRD_WR_CAP_MASK 0x7 165 #define CRD_WR_Q_DEP_SHIFT 8 166 #define CRD_WR_Q_DEP_MASK 0xf 167 #define CRD_RD_CAP_SHIFT 12 168 #define CRD_RD_CAP_MASK 0x7 169 #define CRD_RD_Q_DEP_SHIFT 16 170 #define CRD_RD_Q_DEP_MASK 0xf 171 #define CRD_DATA_BUFF_SHIFT 20 172 #define CRD_DATA_BUFF_MASK 0x3ff 173 174 #define PART 0x330 175 #define DESIGNER 0x41 176 #define REVISION 0x0 177 #define INTEG_CFG 0x0 178 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) 179 180 #define PL330_STATE_STOPPED (1 << 0) 181 #define PL330_STATE_EXECUTING (1 << 1) 182 #define PL330_STATE_WFE (1 << 2) 183 #define PL330_STATE_FAULTING (1 << 3) 184 #define PL330_STATE_COMPLETING (1 << 4) 185 #define PL330_STATE_WFP (1 << 5) 186 #define PL330_STATE_KILLING (1 << 6) 187 #define PL330_STATE_FAULT_COMPLETING (1 << 7) 188 #define PL330_STATE_CACHEMISS (1 << 8) 189 #define PL330_STATE_UPDTPC (1 << 9) 190 #define PL330_STATE_ATBARRIER (1 << 10) 191 #define PL330_STATE_QUEUEBUSY (1 << 11) 192 #define PL330_STATE_INVALID (1 << 15) 193 194 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ 195 | PL330_STATE_WFE | PL330_STATE_FAULTING) 196 197 #define CMD_DMAADDH 0x54 198 #define CMD_DMAEND 0x00 199 #define CMD_DMAFLUSHP 0x35 200 #define CMD_DMAGO 0xa0 201 #define CMD_DMALD 0x04 202 #define CMD_DMALDP 0x25 203 #define CMD_DMALP 0x20 204 #define CMD_DMALPEND 0x28 205 #define CMD_DMAKILL 0x01 206 #define CMD_DMAMOV 0xbc 207 #define CMD_DMANOP 0x18 208 #define CMD_DMARMB 0x12 209 #define CMD_DMASEV 0x34 210 #define CMD_DMAST 0x08 211 #define CMD_DMASTP 0x29 212 #define CMD_DMASTZ 0x0c 213 #define CMD_DMAWFE 0x36 214 #define CMD_DMAWFP 0x30 215 #define CMD_DMAWMB 0x13 216 217 #define SZ_DMAADDH 3 218 #define SZ_DMAEND 1 219 #define SZ_DMAFLUSHP 2 220 #define SZ_DMALD 1 221 #define SZ_DMALDP 2 222 #define SZ_DMALP 2 223 #define SZ_DMALPEND 2 224 #define SZ_DMAKILL 1 225 #define SZ_DMAMOV 6 226 #define SZ_DMANOP 1 227 #define SZ_DMARMB 1 228 #define SZ_DMASEV 2 229 #define SZ_DMAST 1 230 #define SZ_DMASTP 2 231 #define SZ_DMASTZ 1 232 #define SZ_DMAWFE 2 233 #define SZ_DMAWFP 2 234 #define SZ_DMAWMB 1 235 #define SZ_DMAGO 6 236 237 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) 238 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) 239 240 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) 241 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) 242 243 /* 244 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req 245 * at 1byte/burst for P<->M and M<->M respectively. 246 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req 247 * should be enough for P<->M and M<->M respectively. 248 */ 249 #define MCODE_BUFF_PER_REQ 256 250 251 /* Use this _only_ to wait on transient states */ 252 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); 253 254 #ifdef PL330_DEBUG_MCGEN 255 static unsigned cmd_line; 256 #define PL330_DBGCMD_DUMP(off, x...) do { \ 257 printk("%x:", cmd_line); \ 258 printk(KERN_CONT x); \ 259 cmd_line += off; \ 260 } while (0) 261 #define PL330_DBGMC_START(addr) (cmd_line = addr) 262 #else 263 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0) 264 #define PL330_DBGMC_START(addr) do {} while (0) 265 #endif 266 267 /* The number of default descriptors */ 268 269 #define NR_DEFAULT_DESC 16 270 271 /* Delay for runtime PM autosuspend, ms */ 272 #define PL330_AUTOSUSPEND_DELAY 20 273 274 /* Populated by the PL330 core driver for DMA API driver's info */ 275 struct pl330_config { 276 u32 periph_id; 277 #define DMAC_MODE_NS (1 << 0) 278 unsigned int mode; 279 unsigned int data_bus_width:10; /* In number of bits */ 280 unsigned int data_buf_dep:11; 281 unsigned int num_chan:4; 282 unsigned int num_peri:6; 283 u32 peri_ns; 284 unsigned int num_events:6; 285 u32 irq_ns; 286 }; 287 288 /* 289 * Request Configuration. 290 * The PL330 core does not modify this and uses the last 291 * working configuration if the request doesn't provide any. 292 * 293 * The Client may want to provide this info only for the 294 * first request and a request with new settings. 295 */ 296 struct pl330_reqcfg { 297 /* Address Incrementing */ 298 unsigned dst_inc:1; 299 unsigned src_inc:1; 300 301 /* 302 * For now, the SRC & DST protection levels 303 * and burst size/length are assumed same. 304 */ 305 bool nonsecure; 306 bool privileged; 307 bool insnaccess; 308 unsigned brst_len:5; 309 unsigned brst_size:3; /* in power of 2 */ 310 311 enum pl330_cachectrl dcctl; 312 enum pl330_cachectrl scctl; 313 enum pl330_byteswap swap; 314 struct pl330_config *pcfg; 315 }; 316 317 /* 318 * One cycle of DMAC operation. 319 * There may be more than one xfer in a request. 320 */ 321 struct pl330_xfer { 322 u32 src_addr; 323 u32 dst_addr; 324 /* Size to xfer */ 325 u32 bytes; 326 }; 327 328 /* The xfer callbacks are made with one of these arguments. */ 329 enum pl330_op_err { 330 /* The all xfers in the request were success. */ 331 PL330_ERR_NONE, 332 /* If req aborted due to global error. */ 333 PL330_ERR_ABORT, 334 /* If req failed due to problem with Channel. */ 335 PL330_ERR_FAIL, 336 }; 337 338 enum dmamov_dst { 339 SAR = 0, 340 CCR, 341 DAR, 342 }; 343 344 enum pl330_dst { 345 SRC = 0, 346 DST, 347 }; 348 349 enum pl330_cond { 350 SINGLE, 351 BURST, 352 ALWAYS, 353 }; 354 355 struct dma_pl330_desc; 356 357 struct _pl330_req { 358 u32 mc_bus; 359 void *mc_cpu; 360 struct dma_pl330_desc *desc; 361 }; 362 363 /* ToBeDone for tasklet */ 364 struct _pl330_tbd { 365 bool reset_dmac; 366 bool reset_mngr; 367 u8 reset_chan; 368 }; 369 370 /* A DMAC Thread */ 371 struct pl330_thread { 372 u8 id; 373 int ev; 374 /* If the channel is not yet acquired by any client */ 375 bool free; 376 /* Parent DMAC */ 377 struct pl330_dmac *dmac; 378 /* Only two at a time */ 379 struct _pl330_req req[2]; 380 /* Index of the last enqueued request */ 381 unsigned lstenq; 382 /* Index of the last submitted request or -1 if the DMA is stopped */ 383 int req_running; 384 }; 385 386 enum pl330_dmac_state { 387 UNINIT, 388 INIT, 389 DYING, 390 }; 391 392 enum desc_status { 393 /* In the DMAC pool */ 394 FREE, 395 /* 396 * Allocated to some channel during prep_xxx 397 * Also may be sitting on the work_list. 398 */ 399 PREP, 400 /* 401 * Sitting on the work_list and already submitted 402 * to the PL330 core. Not more than two descriptors 403 * of a channel can be BUSY at any time. 404 */ 405 BUSY, 406 /* 407 * Sitting on the channel work_list but xfer done 408 * by PL330 core 409 */ 410 DONE, 411 }; 412 413 struct dma_pl330_chan { 414 /* Schedule desc completion */ 415 struct tasklet_struct task; 416 417 /* DMA-Engine Channel */ 418 struct dma_chan chan; 419 420 /* List of submitted descriptors */ 421 struct list_head submitted_list; 422 /* List of issued descriptors */ 423 struct list_head work_list; 424 /* List of completed descriptors */ 425 struct list_head completed_list; 426 427 /* Pointer to the DMAC that manages this channel, 428 * NULL if the channel is available to be acquired. 429 * As the parent, this DMAC also provides descriptors 430 * to the channel. 431 */ 432 struct pl330_dmac *dmac; 433 434 /* To protect channel manipulation */ 435 spinlock_t lock; 436 437 /* 438 * Hardware channel thread of PL330 DMAC. NULL if the channel is 439 * available. 440 */ 441 struct pl330_thread *thread; 442 443 /* For D-to-M and M-to-D channels */ 444 int burst_sz; /* the peripheral fifo width */ 445 int burst_len; /* the number of burst */ 446 phys_addr_t fifo_addr; 447 /* DMA-mapped view of the FIFO; may differ if an IOMMU is present */ 448 dma_addr_t fifo_dma; 449 enum dma_data_direction dir; 450 struct dma_slave_config slave_config; 451 452 /* for cyclic capability */ 453 bool cyclic; 454 455 /* for runtime pm tracking */ 456 bool active; 457 }; 458 459 struct pl330_dmac { 460 /* DMA-Engine Device */ 461 struct dma_device ddma; 462 463 /* Pool of descriptors available for the DMAC's channels */ 464 struct list_head desc_pool; 465 /* To protect desc_pool manipulation */ 466 spinlock_t pool_lock; 467 468 /* Size of MicroCode buffers for each channel. */ 469 unsigned mcbufsz; 470 /* ioremap'ed address of PL330 registers. */ 471 void __iomem *base; 472 /* Populated by the PL330 core driver during pl330_add */ 473 struct pl330_config pcfg; 474 475 spinlock_t lock; 476 /* Maximum possible events/irqs */ 477 int events[32]; 478 /* BUS address of MicroCode buffer */ 479 dma_addr_t mcode_bus; 480 /* CPU address of MicroCode buffer */ 481 void *mcode_cpu; 482 /* List of all Channel threads */ 483 struct pl330_thread *channels; 484 /* Pointer to the MANAGER thread */ 485 struct pl330_thread *manager; 486 /* To handle bad news in interrupt */ 487 struct tasklet_struct tasks; 488 struct _pl330_tbd dmac_tbd; 489 /* State of DMAC operation */ 490 enum pl330_dmac_state state; 491 /* Holds list of reqs with due callbacks */ 492 struct list_head req_done; 493 494 /* Peripheral channels connected to this DMAC */ 495 unsigned int num_peripherals; 496 struct dma_pl330_chan *peripherals; /* keep at end */ 497 int quirks; 498 499 struct reset_control *rstc; 500 struct reset_control *rstc_ocp; 501 }; 502 503 static struct pl330_of_quirks { 504 char *quirk; 505 int id; 506 } of_quirks[] = { 507 { 508 .quirk = "arm,pl330-broken-no-flushp", 509 .id = PL330_QUIRK_BROKEN_NO_FLUSHP, 510 }, 511 { 512 .quirk = "arm,pl330-periph-burst", 513 .id = PL330_QUIRK_PERIPH_BURST, 514 } 515 }; 516 517 struct dma_pl330_desc { 518 /* To attach to a queue as child */ 519 struct list_head node; 520 521 /* Descriptor for the DMA Engine API */ 522 struct dma_async_tx_descriptor txd; 523 524 /* Xfer for PL330 core */ 525 struct pl330_xfer px; 526 527 struct pl330_reqcfg rqcfg; 528 529 enum desc_status status; 530 531 int bytes_requested; 532 bool last; 533 534 /* The channel which currently holds this desc */ 535 struct dma_pl330_chan *pchan; 536 537 enum dma_transfer_direction rqtype; 538 /* Index of peripheral for the xfer. */ 539 unsigned peri:5; 540 /* Hook to attach to DMAC's list of reqs with due callback */ 541 struct list_head rqd; 542 }; 543 544 struct _xfer_spec { 545 u32 ccr; 546 struct dma_pl330_desc *desc; 547 }; 548 549 static int pl330_config_write(struct dma_chan *chan, 550 struct dma_slave_config *slave_config, 551 enum dma_transfer_direction direction); 552 553 static inline bool _queue_full(struct pl330_thread *thrd) 554 { 555 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL; 556 } 557 558 static inline bool is_manager(struct pl330_thread *thrd) 559 { 560 return thrd->dmac->manager == thrd; 561 } 562 563 /* If manager of the thread is in Non-Secure mode */ 564 static inline bool _manager_ns(struct pl330_thread *thrd) 565 { 566 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false; 567 } 568 569 static inline u32 get_revision(u32 periph_id) 570 { 571 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; 572 } 573 574 static inline u32 _emit_END(unsigned dry_run, u8 buf[]) 575 { 576 if (dry_run) 577 return SZ_DMAEND; 578 579 buf[0] = CMD_DMAEND; 580 581 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); 582 583 return SZ_DMAEND; 584 } 585 586 static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) 587 { 588 if (dry_run) 589 return SZ_DMAFLUSHP; 590 591 buf[0] = CMD_DMAFLUSHP; 592 593 peri &= 0x1f; 594 peri <<= 3; 595 buf[1] = peri; 596 597 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); 598 599 return SZ_DMAFLUSHP; 600 } 601 602 static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) 603 { 604 if (dry_run) 605 return SZ_DMALD; 606 607 buf[0] = CMD_DMALD; 608 609 if (cond == SINGLE) 610 buf[0] |= (0 << 1) | (1 << 0); 611 else if (cond == BURST) 612 buf[0] |= (1 << 1) | (1 << 0); 613 614 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", 615 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); 616 617 return SZ_DMALD; 618 } 619 620 static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], 621 enum pl330_cond cond, u8 peri) 622 { 623 if (dry_run) 624 return SZ_DMALDP; 625 626 buf[0] = CMD_DMALDP; 627 628 if (cond == BURST) 629 buf[0] |= (1 << 1); 630 631 peri &= 0x1f; 632 peri <<= 3; 633 buf[1] = peri; 634 635 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", 636 cond == SINGLE ? 'S' : 'B', peri >> 3); 637 638 return SZ_DMALDP; 639 } 640 641 static inline u32 _emit_LP(unsigned dry_run, u8 buf[], 642 unsigned loop, u8 cnt) 643 { 644 if (dry_run) 645 return SZ_DMALP; 646 647 buf[0] = CMD_DMALP; 648 649 if (loop) 650 buf[0] |= (1 << 1); 651 652 cnt--; /* DMAC increments by 1 internally */ 653 buf[1] = cnt; 654 655 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); 656 657 return SZ_DMALP; 658 } 659 660 struct _arg_LPEND { 661 enum pl330_cond cond; 662 bool forever; 663 unsigned loop; 664 u8 bjump; 665 }; 666 667 static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], 668 const struct _arg_LPEND *arg) 669 { 670 enum pl330_cond cond = arg->cond; 671 bool forever = arg->forever; 672 unsigned loop = arg->loop; 673 u8 bjump = arg->bjump; 674 675 if (dry_run) 676 return SZ_DMALPEND; 677 678 buf[0] = CMD_DMALPEND; 679 680 if (loop) 681 buf[0] |= (1 << 2); 682 683 if (!forever) 684 buf[0] |= (1 << 4); 685 686 if (cond == SINGLE) 687 buf[0] |= (0 << 1) | (1 << 0); 688 else if (cond == BURST) 689 buf[0] |= (1 << 1) | (1 << 0); 690 691 buf[1] = bjump; 692 693 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", 694 forever ? "FE" : "END", 695 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), 696 loop ? '1' : '0', 697 bjump); 698 699 return SZ_DMALPEND; 700 } 701 702 static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) 703 { 704 if (dry_run) 705 return SZ_DMAKILL; 706 707 buf[0] = CMD_DMAKILL; 708 709 return SZ_DMAKILL; 710 } 711 712 static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], 713 enum dmamov_dst dst, u32 val) 714 { 715 if (dry_run) 716 return SZ_DMAMOV; 717 718 buf[0] = CMD_DMAMOV; 719 buf[1] = dst; 720 buf[2] = val; 721 buf[3] = val >> 8; 722 buf[4] = val >> 16; 723 buf[5] = val >> 24; 724 725 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", 726 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); 727 728 return SZ_DMAMOV; 729 } 730 731 static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) 732 { 733 if (dry_run) 734 return SZ_DMARMB; 735 736 buf[0] = CMD_DMARMB; 737 738 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); 739 740 return SZ_DMARMB; 741 } 742 743 static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) 744 { 745 if (dry_run) 746 return SZ_DMASEV; 747 748 buf[0] = CMD_DMASEV; 749 750 ev &= 0x1f; 751 ev <<= 3; 752 buf[1] = ev; 753 754 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); 755 756 return SZ_DMASEV; 757 } 758 759 static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) 760 { 761 if (dry_run) 762 return SZ_DMAST; 763 764 buf[0] = CMD_DMAST; 765 766 if (cond == SINGLE) 767 buf[0] |= (0 << 1) | (1 << 0); 768 else if (cond == BURST) 769 buf[0] |= (1 << 1) | (1 << 0); 770 771 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", 772 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); 773 774 return SZ_DMAST; 775 } 776 777 static inline u32 _emit_STP(unsigned dry_run, u8 buf[], 778 enum pl330_cond cond, u8 peri) 779 { 780 if (dry_run) 781 return SZ_DMASTP; 782 783 buf[0] = CMD_DMASTP; 784 785 if (cond == BURST) 786 buf[0] |= (1 << 1); 787 788 peri &= 0x1f; 789 peri <<= 3; 790 buf[1] = peri; 791 792 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", 793 cond == SINGLE ? 'S' : 'B', peri >> 3); 794 795 return SZ_DMASTP; 796 } 797 798 static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], 799 enum pl330_cond cond, u8 peri) 800 { 801 if (dry_run) 802 return SZ_DMAWFP; 803 804 buf[0] = CMD_DMAWFP; 805 806 if (cond == SINGLE) 807 buf[0] |= (0 << 1) | (0 << 0); 808 else if (cond == BURST) 809 buf[0] |= (1 << 1) | (0 << 0); 810 else 811 buf[0] |= (0 << 1) | (1 << 0); 812 813 peri &= 0x1f; 814 peri <<= 3; 815 buf[1] = peri; 816 817 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", 818 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); 819 820 return SZ_DMAWFP; 821 } 822 823 static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) 824 { 825 if (dry_run) 826 return SZ_DMAWMB; 827 828 buf[0] = CMD_DMAWMB; 829 830 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); 831 832 return SZ_DMAWMB; 833 } 834 835 struct _arg_GO { 836 u8 chan; 837 u32 addr; 838 unsigned ns; 839 }; 840 841 static inline u32 _emit_GO(unsigned dry_run, u8 buf[], 842 const struct _arg_GO *arg) 843 { 844 u8 chan = arg->chan; 845 u32 addr = arg->addr; 846 unsigned ns = arg->ns; 847 848 if (dry_run) 849 return SZ_DMAGO; 850 851 buf[0] = CMD_DMAGO; 852 buf[0] |= (ns << 1); 853 buf[1] = chan & 0x7; 854 buf[2] = addr; 855 buf[3] = addr >> 8; 856 buf[4] = addr >> 16; 857 buf[5] = addr >> 24; 858 859 return SZ_DMAGO; 860 } 861 862 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 863 864 /* Returns Time-Out */ 865 static bool _until_dmac_idle(struct pl330_thread *thrd) 866 { 867 void __iomem *regs = thrd->dmac->base; 868 unsigned long loops = msecs_to_loops(5); 869 870 do { 871 /* Until Manager is Idle */ 872 if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) 873 break; 874 875 cpu_relax(); 876 } while (--loops); 877 878 if (!loops) 879 return true; 880 881 return false; 882 } 883 884 static inline void _execute_DBGINSN(struct pl330_thread *thrd, 885 u8 insn[], bool as_manager) 886 { 887 void __iomem *regs = thrd->dmac->base; 888 u32 val; 889 890 /* If timed out due to halted state-machine */ 891 if (_until_dmac_idle(thrd)) { 892 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n"); 893 return; 894 } 895 896 val = (insn[0] << 16) | (insn[1] << 24); 897 if (!as_manager) { 898 val |= (1 << 0); 899 val |= (thrd->id << 8); /* Channel Number */ 900 } 901 writel(val, regs + DBGINST0); 902 903 val = le32_to_cpu(*((__le32 *)&insn[2])); 904 writel(val, regs + DBGINST1); 905 906 /* Get going */ 907 writel(0, regs + DBGCMD); 908 } 909 910 static inline u32 _state(struct pl330_thread *thrd) 911 { 912 void __iomem *regs = thrd->dmac->base; 913 u32 val; 914 915 if (is_manager(thrd)) 916 val = readl(regs + DS) & 0xf; 917 else 918 val = readl(regs + CS(thrd->id)) & 0xf; 919 920 switch (val) { 921 case DS_ST_STOP: 922 return PL330_STATE_STOPPED; 923 case DS_ST_EXEC: 924 return PL330_STATE_EXECUTING; 925 case DS_ST_CMISS: 926 return PL330_STATE_CACHEMISS; 927 case DS_ST_UPDTPC: 928 return PL330_STATE_UPDTPC; 929 case DS_ST_WFE: 930 return PL330_STATE_WFE; 931 case DS_ST_FAULT: 932 return PL330_STATE_FAULTING; 933 case DS_ST_ATBRR: 934 if (is_manager(thrd)) 935 return PL330_STATE_INVALID; 936 else 937 return PL330_STATE_ATBARRIER; 938 case DS_ST_QBUSY: 939 if (is_manager(thrd)) 940 return PL330_STATE_INVALID; 941 else 942 return PL330_STATE_QUEUEBUSY; 943 case DS_ST_WFP: 944 if (is_manager(thrd)) 945 return PL330_STATE_INVALID; 946 else 947 return PL330_STATE_WFP; 948 case DS_ST_KILL: 949 if (is_manager(thrd)) 950 return PL330_STATE_INVALID; 951 else 952 return PL330_STATE_KILLING; 953 case DS_ST_CMPLT: 954 if (is_manager(thrd)) 955 return PL330_STATE_INVALID; 956 else 957 return PL330_STATE_COMPLETING; 958 case DS_ST_FLTCMP: 959 if (is_manager(thrd)) 960 return PL330_STATE_INVALID; 961 else 962 return PL330_STATE_FAULT_COMPLETING; 963 default: 964 return PL330_STATE_INVALID; 965 } 966 } 967 968 static void _stop(struct pl330_thread *thrd) 969 { 970 void __iomem *regs = thrd->dmac->base; 971 u8 insn[6] = {0, 0, 0, 0, 0, 0}; 972 u32 inten = readl(regs + INTEN); 973 974 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING) 975 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); 976 977 /* Return if nothing needs to be done */ 978 if (_state(thrd) == PL330_STATE_COMPLETING 979 || _state(thrd) == PL330_STATE_KILLING 980 || _state(thrd) == PL330_STATE_STOPPED) 981 return; 982 983 _emit_KILL(0, insn); 984 985 _execute_DBGINSN(thrd, insn, is_manager(thrd)); 986 987 /* clear the event */ 988 if (inten & (1 << thrd->ev)) 989 writel(1 << thrd->ev, regs + INTCLR); 990 /* Stop generating interrupts for SEV */ 991 writel(inten & ~(1 << thrd->ev), regs + INTEN); 992 } 993 994 /* Start doing req 'idx' of thread 'thrd' */ 995 static bool _trigger(struct pl330_thread *thrd) 996 { 997 void __iomem *regs = thrd->dmac->base; 998 struct _pl330_req *req; 999 struct dma_pl330_desc *desc; 1000 struct _arg_GO go; 1001 unsigned ns; 1002 u8 insn[6] = {0, 0, 0, 0, 0, 0}; 1003 int idx; 1004 1005 /* Return if already ACTIVE */ 1006 if (_state(thrd) != PL330_STATE_STOPPED) 1007 return true; 1008 1009 idx = 1 - thrd->lstenq; 1010 if (thrd->req[idx].desc != NULL) { 1011 req = &thrd->req[idx]; 1012 } else { 1013 idx = thrd->lstenq; 1014 if (thrd->req[idx].desc != NULL) 1015 req = &thrd->req[idx]; 1016 else 1017 req = NULL; 1018 } 1019 1020 /* Return if no request */ 1021 if (!req) 1022 return true; 1023 1024 /* Return if req is running */ 1025 if (idx == thrd->req_running) 1026 return true; 1027 1028 desc = req->desc; 1029 1030 ns = desc->rqcfg.nonsecure ? 1 : 0; 1031 1032 /* See 'Abort Sources' point-4 at Page 2-25 */ 1033 if (_manager_ns(thrd) && !ns) 1034 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n", 1035 __func__, __LINE__); 1036 1037 go.chan = thrd->id; 1038 go.addr = req->mc_bus; 1039 go.ns = ns; 1040 _emit_GO(0, insn, &go); 1041 1042 /* Set to generate interrupts for SEV */ 1043 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); 1044 1045 /* Only manager can execute GO */ 1046 _execute_DBGINSN(thrd, insn, true); 1047 1048 thrd->req_running = idx; 1049 1050 return true; 1051 } 1052 1053 static bool _start(struct pl330_thread *thrd) 1054 { 1055 switch (_state(thrd)) { 1056 case PL330_STATE_FAULT_COMPLETING: 1057 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); 1058 1059 if (_state(thrd) == PL330_STATE_KILLING) 1060 UNTIL(thrd, PL330_STATE_STOPPED) 1061 fallthrough; 1062 1063 case PL330_STATE_FAULTING: 1064 _stop(thrd); 1065 fallthrough; 1066 1067 case PL330_STATE_KILLING: 1068 case PL330_STATE_COMPLETING: 1069 UNTIL(thrd, PL330_STATE_STOPPED) 1070 fallthrough; 1071 1072 case PL330_STATE_STOPPED: 1073 return _trigger(thrd); 1074 1075 case PL330_STATE_WFP: 1076 case PL330_STATE_QUEUEBUSY: 1077 case PL330_STATE_ATBARRIER: 1078 case PL330_STATE_UPDTPC: 1079 case PL330_STATE_CACHEMISS: 1080 case PL330_STATE_EXECUTING: 1081 return true; 1082 1083 case PL330_STATE_WFE: /* For RESUME, nothing yet */ 1084 default: 1085 return false; 1086 } 1087 } 1088 1089 static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], 1090 const struct _xfer_spec *pxs, int cyc) 1091 { 1092 int off = 0; 1093 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg; 1094 1095 /* check lock-up free version */ 1096 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { 1097 while (cyc--) { 1098 off += _emit_LD(dry_run, &buf[off], ALWAYS); 1099 off += _emit_ST(dry_run, &buf[off], ALWAYS); 1100 } 1101 } else { 1102 while (cyc--) { 1103 off += _emit_LD(dry_run, &buf[off], ALWAYS); 1104 off += _emit_RMB(dry_run, &buf[off]); 1105 off += _emit_ST(dry_run, &buf[off], ALWAYS); 1106 off += _emit_WMB(dry_run, &buf[off]); 1107 } 1108 } 1109 1110 return off; 1111 } 1112 1113 static u32 _emit_load(unsigned int dry_run, u8 buf[], 1114 enum pl330_cond cond, enum dma_transfer_direction direction, 1115 u8 peri) 1116 { 1117 int off = 0; 1118 1119 switch (direction) { 1120 case DMA_MEM_TO_MEM: 1121 case DMA_MEM_TO_DEV: 1122 off += _emit_LD(dry_run, &buf[off], cond); 1123 break; 1124 1125 case DMA_DEV_TO_MEM: 1126 if (cond == ALWAYS) { 1127 off += _emit_LDP(dry_run, &buf[off], SINGLE, 1128 peri); 1129 off += _emit_LDP(dry_run, &buf[off], BURST, 1130 peri); 1131 } else { 1132 off += _emit_LDP(dry_run, &buf[off], cond, 1133 peri); 1134 } 1135 break; 1136 1137 default: 1138 /* this code should be unreachable */ 1139 WARN_ON(1); 1140 break; 1141 } 1142 1143 return off; 1144 } 1145 1146 static inline u32 _emit_store(unsigned int dry_run, u8 buf[], 1147 enum pl330_cond cond, enum dma_transfer_direction direction, 1148 u8 peri) 1149 { 1150 int off = 0; 1151 1152 switch (direction) { 1153 case DMA_MEM_TO_MEM: 1154 case DMA_DEV_TO_MEM: 1155 off += _emit_ST(dry_run, &buf[off], cond); 1156 break; 1157 1158 case DMA_MEM_TO_DEV: 1159 if (cond == ALWAYS) { 1160 off += _emit_STP(dry_run, &buf[off], SINGLE, 1161 peri); 1162 off += _emit_STP(dry_run, &buf[off], BURST, 1163 peri); 1164 } else { 1165 off += _emit_STP(dry_run, &buf[off], cond, 1166 peri); 1167 } 1168 break; 1169 1170 default: 1171 /* this code should be unreachable */ 1172 WARN_ON(1); 1173 break; 1174 } 1175 1176 return off; 1177 } 1178 1179 static inline int _ldst_peripheral(struct pl330_dmac *pl330, 1180 unsigned dry_run, u8 buf[], 1181 const struct _xfer_spec *pxs, int cyc, 1182 enum pl330_cond cond) 1183 { 1184 int off = 0; 1185 1186 /* 1187 * do FLUSHP at beginning to clear any stale dma requests before the 1188 * first WFP. 1189 */ 1190 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)) 1191 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri); 1192 while (cyc--) { 1193 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri); 1194 off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype, 1195 pxs->desc->peri); 1196 off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype, 1197 pxs->desc->peri); 1198 } 1199 1200 return off; 1201 } 1202 1203 static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[], 1204 const struct _xfer_spec *pxs, int cyc) 1205 { 1206 int off = 0; 1207 enum pl330_cond cond = BRST_LEN(pxs->ccr) > 1 ? BURST : SINGLE; 1208 1209 if (pl330->quirks & PL330_QUIRK_PERIPH_BURST) 1210 cond = BURST; 1211 1212 switch (pxs->desc->rqtype) { 1213 case DMA_MEM_TO_DEV: 1214 case DMA_DEV_TO_MEM: 1215 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, cyc, 1216 cond); 1217 break; 1218 1219 case DMA_MEM_TO_MEM: 1220 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); 1221 break; 1222 1223 default: 1224 /* this code should be unreachable */ 1225 WARN_ON(1); 1226 break; 1227 } 1228 1229 return off; 1230 } 1231 1232 /* 1233 * only the unaligned burst transfers have the dregs. 1234 * so, still transfer dregs with a reduced size burst 1235 * for mem-to-mem, mem-to-dev or dev-to-mem. 1236 */ 1237 static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[], 1238 const struct _xfer_spec *pxs, int transfer_length) 1239 { 1240 int off = 0; 1241 int dregs_ccr; 1242 1243 if (transfer_length == 0) 1244 return off; 1245 1246 /* 1247 * dregs_len = (total bytes - BURST_TO_BYTE(bursts, ccr)) / 1248 * BRST_SIZE(ccr) 1249 * the dregs len must be smaller than burst len, 1250 * so, for higher efficiency, we can modify CCR 1251 * to use a reduced size burst len for the dregs. 1252 */ 1253 dregs_ccr = pxs->ccr; 1254 dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) | 1255 (0xf << CC_DSTBRSTLEN_SHFT)); 1256 dregs_ccr |= (((transfer_length - 1) & 0xf) << 1257 CC_SRCBRSTLEN_SHFT); 1258 dregs_ccr |= (((transfer_length - 1) & 0xf) << 1259 CC_DSTBRSTLEN_SHFT); 1260 1261 switch (pxs->desc->rqtype) { 1262 case DMA_MEM_TO_DEV: 1263 case DMA_DEV_TO_MEM: 1264 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr); 1265 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, 1, 1266 BURST); 1267 break; 1268 1269 case DMA_MEM_TO_MEM: 1270 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr); 1271 off += _ldst_memtomem(dry_run, &buf[off], pxs, 1); 1272 break; 1273 1274 default: 1275 /* this code should be unreachable */ 1276 WARN_ON(1); 1277 break; 1278 } 1279 1280 return off; 1281 } 1282 1283 /* Returns bytes consumed and updates bursts */ 1284 static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[], 1285 unsigned long *bursts, const struct _xfer_spec *pxs) 1286 { 1287 int cyc, cycmax, szlp, szlpend, szbrst, off; 1288 unsigned lcnt0, lcnt1, ljmp0, ljmp1; 1289 struct _arg_LPEND lpend; 1290 1291 if (*bursts == 1) 1292 return _bursts(pl330, dry_run, buf, pxs, 1); 1293 1294 /* Max iterations possible in DMALP is 256 */ 1295 if (*bursts >= 256*256) { 1296 lcnt1 = 256; 1297 lcnt0 = 256; 1298 cyc = *bursts / lcnt1 / lcnt0; 1299 } else if (*bursts > 256) { 1300 lcnt1 = 256; 1301 lcnt0 = *bursts / lcnt1; 1302 cyc = 1; 1303 } else { 1304 lcnt1 = *bursts; 1305 lcnt0 = 0; 1306 cyc = 1; 1307 } 1308 1309 szlp = _emit_LP(1, buf, 0, 0); 1310 szbrst = _bursts(pl330, 1, buf, pxs, 1); 1311 1312 lpend.cond = ALWAYS; 1313 lpend.forever = false; 1314 lpend.loop = 0; 1315 lpend.bjump = 0; 1316 szlpend = _emit_LPEND(1, buf, &lpend); 1317 1318 if (lcnt0) { 1319 szlp *= 2; 1320 szlpend *= 2; 1321 } 1322 1323 /* 1324 * Max bursts that we can unroll due to limit on the 1325 * size of backward jump that can be encoded in DMALPEND 1326 * which is 8-bits and hence 255 1327 */ 1328 cycmax = (255 - (szlp + szlpend)) / szbrst; 1329 1330 cyc = (cycmax < cyc) ? cycmax : cyc; 1331 1332 off = 0; 1333 1334 if (lcnt0) { 1335 off += _emit_LP(dry_run, &buf[off], 0, lcnt0); 1336 ljmp0 = off; 1337 } 1338 1339 off += _emit_LP(dry_run, &buf[off], 1, lcnt1); 1340 ljmp1 = off; 1341 1342 off += _bursts(pl330, dry_run, &buf[off], pxs, cyc); 1343 1344 lpend.cond = ALWAYS; 1345 lpend.forever = false; 1346 lpend.loop = 1; 1347 lpend.bjump = off - ljmp1; 1348 off += _emit_LPEND(dry_run, &buf[off], &lpend); 1349 1350 if (lcnt0) { 1351 lpend.cond = ALWAYS; 1352 lpend.forever = false; 1353 lpend.loop = 0; 1354 lpend.bjump = off - ljmp0; 1355 off += _emit_LPEND(dry_run, &buf[off], &lpend); 1356 } 1357 1358 *bursts = lcnt1 * cyc; 1359 if (lcnt0) 1360 *bursts *= lcnt0; 1361 1362 return off; 1363 } 1364 1365 static inline int _setup_loops(struct pl330_dmac *pl330, 1366 unsigned dry_run, u8 buf[], 1367 const struct _xfer_spec *pxs) 1368 { 1369 struct pl330_xfer *x = &pxs->desc->px; 1370 u32 ccr = pxs->ccr; 1371 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); 1372 int num_dregs = (x->bytes - BURST_TO_BYTE(bursts, ccr)) / 1373 BRST_SIZE(ccr); 1374 int off = 0; 1375 1376 while (bursts) { 1377 c = bursts; 1378 off += _loop(pl330, dry_run, &buf[off], &c, pxs); 1379 bursts -= c; 1380 } 1381 off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs); 1382 1383 return off; 1384 } 1385 1386 static inline int _setup_xfer(struct pl330_dmac *pl330, 1387 unsigned dry_run, u8 buf[], 1388 const struct _xfer_spec *pxs) 1389 { 1390 struct pl330_xfer *x = &pxs->desc->px; 1391 int off = 0; 1392 1393 /* DMAMOV SAR, x->src_addr */ 1394 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); 1395 /* DMAMOV DAR, x->dst_addr */ 1396 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr); 1397 1398 /* Setup Loop(s) */ 1399 off += _setup_loops(pl330, dry_run, &buf[off], pxs); 1400 1401 return off; 1402 } 1403 1404 /* 1405 * A req is a sequence of one or more xfer units. 1406 * Returns the number of bytes taken to setup the MC for the req. 1407 */ 1408 static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run, 1409 struct pl330_thread *thrd, unsigned index, 1410 struct _xfer_spec *pxs) 1411 { 1412 struct _pl330_req *req = &thrd->req[index]; 1413 u8 *buf = req->mc_cpu; 1414 int off = 0; 1415 1416 PL330_DBGMC_START(req->mc_bus); 1417 1418 /* DMAMOV CCR, ccr */ 1419 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); 1420 1421 off += _setup_xfer(pl330, dry_run, &buf[off], pxs); 1422 1423 /* DMASEV peripheral/event */ 1424 off += _emit_SEV(dry_run, &buf[off], thrd->ev); 1425 /* DMAEND */ 1426 off += _emit_END(dry_run, &buf[off]); 1427 1428 return off; 1429 } 1430 1431 static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) 1432 { 1433 u32 ccr = 0; 1434 1435 if (rqc->src_inc) 1436 ccr |= CC_SRCINC; 1437 1438 if (rqc->dst_inc) 1439 ccr |= CC_DSTINC; 1440 1441 /* We set same protection levels for Src and DST for now */ 1442 if (rqc->privileged) 1443 ccr |= CC_SRCPRI | CC_DSTPRI; 1444 if (rqc->nonsecure) 1445 ccr |= CC_SRCNS | CC_DSTNS; 1446 if (rqc->insnaccess) 1447 ccr |= CC_SRCIA | CC_DSTIA; 1448 1449 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); 1450 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); 1451 1452 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); 1453 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); 1454 1455 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); 1456 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); 1457 1458 ccr |= (rqc->swap << CC_SWAP_SHFT); 1459 1460 return ccr; 1461 } 1462 1463 /* 1464 * Submit a list of xfers after which the client wants notification. 1465 * Client is not notified after each xfer unit, just once after all 1466 * xfer units are done or some error occurs. 1467 */ 1468 static int pl330_submit_req(struct pl330_thread *thrd, 1469 struct dma_pl330_desc *desc) 1470 { 1471 struct pl330_dmac *pl330 = thrd->dmac; 1472 struct _xfer_spec xs; 1473 unsigned long flags; 1474 unsigned idx; 1475 u32 ccr; 1476 int ret = 0; 1477 1478 switch (desc->rqtype) { 1479 case DMA_MEM_TO_DEV: 1480 break; 1481 1482 case DMA_DEV_TO_MEM: 1483 break; 1484 1485 case DMA_MEM_TO_MEM: 1486 break; 1487 1488 default: 1489 return -ENOTSUPP; 1490 } 1491 1492 if (pl330->state == DYING 1493 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { 1494 dev_info(thrd->dmac->ddma.dev, "%s:%d\n", 1495 __func__, __LINE__); 1496 return -EAGAIN; 1497 } 1498 1499 /* If request for non-existing peripheral */ 1500 if (desc->rqtype != DMA_MEM_TO_MEM && 1501 desc->peri >= pl330->pcfg.num_peri) { 1502 dev_info(thrd->dmac->ddma.dev, 1503 "%s:%d Invalid peripheral(%u)!\n", 1504 __func__, __LINE__, desc->peri); 1505 return -EINVAL; 1506 } 1507 1508 spin_lock_irqsave(&pl330->lock, flags); 1509 1510 if (_queue_full(thrd)) { 1511 ret = -EAGAIN; 1512 goto xfer_exit; 1513 } 1514 1515 /* Prefer Secure Channel */ 1516 if (!_manager_ns(thrd)) 1517 desc->rqcfg.nonsecure = 0; 1518 else 1519 desc->rqcfg.nonsecure = 1; 1520 1521 ccr = _prepare_ccr(&desc->rqcfg); 1522 1523 idx = thrd->req[0].desc == NULL ? 0 : 1; 1524 1525 xs.ccr = ccr; 1526 xs.desc = desc; 1527 1528 /* First dry run to check if req is acceptable */ 1529 ret = _setup_req(pl330, 1, thrd, idx, &xs); 1530 if (ret < 0) 1531 goto xfer_exit; 1532 1533 if (ret > pl330->mcbufsz / 2) { 1534 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n", 1535 __func__, __LINE__, ret, pl330->mcbufsz / 2); 1536 ret = -ENOMEM; 1537 goto xfer_exit; 1538 } 1539 1540 /* Hook the request */ 1541 thrd->lstenq = idx; 1542 thrd->req[idx].desc = desc; 1543 _setup_req(pl330, 0, thrd, idx, &xs); 1544 1545 ret = 0; 1546 1547 xfer_exit: 1548 spin_unlock_irqrestore(&pl330->lock, flags); 1549 1550 return ret; 1551 } 1552 1553 static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err) 1554 { 1555 struct dma_pl330_chan *pch; 1556 unsigned long flags; 1557 1558 if (!desc) 1559 return; 1560 1561 pch = desc->pchan; 1562 1563 /* If desc aborted */ 1564 if (!pch) 1565 return; 1566 1567 spin_lock_irqsave(&pch->lock, flags); 1568 1569 desc->status = DONE; 1570 1571 spin_unlock_irqrestore(&pch->lock, flags); 1572 1573 tasklet_schedule(&pch->task); 1574 } 1575 1576 static void pl330_dotask(struct tasklet_struct *t) 1577 { 1578 struct pl330_dmac *pl330 = from_tasklet(pl330, t, tasks); 1579 unsigned long flags; 1580 int i; 1581 1582 spin_lock_irqsave(&pl330->lock, flags); 1583 1584 /* The DMAC itself gone nuts */ 1585 if (pl330->dmac_tbd.reset_dmac) { 1586 pl330->state = DYING; 1587 /* Reset the manager too */ 1588 pl330->dmac_tbd.reset_mngr = true; 1589 /* Clear the reset flag */ 1590 pl330->dmac_tbd.reset_dmac = false; 1591 } 1592 1593 if (pl330->dmac_tbd.reset_mngr) { 1594 _stop(pl330->manager); 1595 /* Reset all channels */ 1596 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1; 1597 /* Clear the reset flag */ 1598 pl330->dmac_tbd.reset_mngr = false; 1599 } 1600 1601 for (i = 0; i < pl330->pcfg.num_chan; i++) { 1602 1603 if (pl330->dmac_tbd.reset_chan & (1 << i)) { 1604 struct pl330_thread *thrd = &pl330->channels[i]; 1605 void __iomem *regs = pl330->base; 1606 enum pl330_op_err err; 1607 1608 _stop(thrd); 1609 1610 if (readl(regs + FSC) & (1 << thrd->id)) 1611 err = PL330_ERR_FAIL; 1612 else 1613 err = PL330_ERR_ABORT; 1614 1615 spin_unlock_irqrestore(&pl330->lock, flags); 1616 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err); 1617 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err); 1618 spin_lock_irqsave(&pl330->lock, flags); 1619 1620 thrd->req[0].desc = NULL; 1621 thrd->req[1].desc = NULL; 1622 thrd->req_running = -1; 1623 1624 /* Clear the reset flag */ 1625 pl330->dmac_tbd.reset_chan &= ~(1 << i); 1626 } 1627 } 1628 1629 spin_unlock_irqrestore(&pl330->lock, flags); 1630 1631 return; 1632 } 1633 1634 /* Returns 1 if state was updated, 0 otherwise */ 1635 static int pl330_update(struct pl330_dmac *pl330) 1636 { 1637 struct dma_pl330_desc *descdone; 1638 unsigned long flags; 1639 void __iomem *regs; 1640 u32 val; 1641 int id, ev, ret = 0; 1642 1643 regs = pl330->base; 1644 1645 spin_lock_irqsave(&pl330->lock, flags); 1646 1647 val = readl(regs + FSM) & 0x1; 1648 if (val) 1649 pl330->dmac_tbd.reset_mngr = true; 1650 else 1651 pl330->dmac_tbd.reset_mngr = false; 1652 1653 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1); 1654 pl330->dmac_tbd.reset_chan |= val; 1655 if (val) { 1656 int i = 0; 1657 while (i < pl330->pcfg.num_chan) { 1658 if (val & (1 << i)) { 1659 dev_info(pl330->ddma.dev, 1660 "Reset Channel-%d\t CS-%x FTC-%x\n", 1661 i, readl(regs + CS(i)), 1662 readl(regs + FTC(i))); 1663 _stop(&pl330->channels[i]); 1664 } 1665 i++; 1666 } 1667 } 1668 1669 /* Check which event happened i.e, thread notified */ 1670 val = readl(regs + ES); 1671 if (pl330->pcfg.num_events < 32 1672 && val & ~((1 << pl330->pcfg.num_events) - 1)) { 1673 pl330->dmac_tbd.reset_dmac = true; 1674 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__, 1675 __LINE__); 1676 ret = 1; 1677 goto updt_exit; 1678 } 1679 1680 for (ev = 0; ev < pl330->pcfg.num_events; ev++) { 1681 if (val & (1 << ev)) { /* Event occurred */ 1682 struct pl330_thread *thrd; 1683 u32 inten = readl(regs + INTEN); 1684 int active; 1685 1686 /* Clear the event */ 1687 if (inten & (1 << ev)) 1688 writel(1 << ev, regs + INTCLR); 1689 1690 ret = 1; 1691 1692 id = pl330->events[ev]; 1693 1694 thrd = &pl330->channels[id]; 1695 1696 active = thrd->req_running; 1697 if (active == -1) /* Aborted */ 1698 continue; 1699 1700 /* Detach the req */ 1701 descdone = thrd->req[active].desc; 1702 thrd->req[active].desc = NULL; 1703 1704 thrd->req_running = -1; 1705 1706 /* Get going again ASAP */ 1707 _start(thrd); 1708 1709 /* For now, just make a list of callbacks to be done */ 1710 list_add_tail(&descdone->rqd, &pl330->req_done); 1711 } 1712 } 1713 1714 /* Now that we are in no hurry, do the callbacks */ 1715 while (!list_empty(&pl330->req_done)) { 1716 descdone = list_first_entry(&pl330->req_done, 1717 struct dma_pl330_desc, rqd); 1718 list_del(&descdone->rqd); 1719 spin_unlock_irqrestore(&pl330->lock, flags); 1720 dma_pl330_rqcb(descdone, PL330_ERR_NONE); 1721 spin_lock_irqsave(&pl330->lock, flags); 1722 } 1723 1724 updt_exit: 1725 spin_unlock_irqrestore(&pl330->lock, flags); 1726 1727 if (pl330->dmac_tbd.reset_dmac 1728 || pl330->dmac_tbd.reset_mngr 1729 || pl330->dmac_tbd.reset_chan) { 1730 ret = 1; 1731 tasklet_schedule(&pl330->tasks); 1732 } 1733 1734 return ret; 1735 } 1736 1737 /* Reserve an event */ 1738 static inline int _alloc_event(struct pl330_thread *thrd) 1739 { 1740 struct pl330_dmac *pl330 = thrd->dmac; 1741 int ev; 1742 1743 for (ev = 0; ev < pl330->pcfg.num_events; ev++) 1744 if (pl330->events[ev] == -1) { 1745 pl330->events[ev] = thrd->id; 1746 return ev; 1747 } 1748 1749 return -1; 1750 } 1751 1752 static bool _chan_ns(const struct pl330_dmac *pl330, int i) 1753 { 1754 return pl330->pcfg.irq_ns & (1 << i); 1755 } 1756 1757 /* Upon success, returns IdentityToken for the 1758 * allocated channel, NULL otherwise. 1759 */ 1760 static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330) 1761 { 1762 struct pl330_thread *thrd = NULL; 1763 int chans, i; 1764 1765 if (pl330->state == DYING) 1766 return NULL; 1767 1768 chans = pl330->pcfg.num_chan; 1769 1770 for (i = 0; i < chans; i++) { 1771 thrd = &pl330->channels[i]; 1772 if ((thrd->free) && (!_manager_ns(thrd) || 1773 _chan_ns(pl330, i))) { 1774 thrd->ev = _alloc_event(thrd); 1775 if (thrd->ev >= 0) { 1776 thrd->free = false; 1777 thrd->lstenq = 1; 1778 thrd->req[0].desc = NULL; 1779 thrd->req[1].desc = NULL; 1780 thrd->req_running = -1; 1781 break; 1782 } 1783 } 1784 thrd = NULL; 1785 } 1786 1787 return thrd; 1788 } 1789 1790 /* Release an event */ 1791 static inline void _free_event(struct pl330_thread *thrd, int ev) 1792 { 1793 struct pl330_dmac *pl330 = thrd->dmac; 1794 1795 /* If the event is valid and was held by the thread */ 1796 if (ev >= 0 && ev < pl330->pcfg.num_events 1797 && pl330->events[ev] == thrd->id) 1798 pl330->events[ev] = -1; 1799 } 1800 1801 static void pl330_release_channel(struct pl330_thread *thrd) 1802 { 1803 if (!thrd || thrd->free) 1804 return; 1805 1806 _stop(thrd); 1807 1808 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT); 1809 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT); 1810 1811 _free_event(thrd, thrd->ev); 1812 thrd->free = true; 1813 } 1814 1815 /* Initialize the structure for PL330 configuration, that can be used 1816 * by the client driver the make best use of the DMAC 1817 */ 1818 static void read_dmac_config(struct pl330_dmac *pl330) 1819 { 1820 void __iomem *regs = pl330->base; 1821 u32 val; 1822 1823 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; 1824 val &= CRD_DATA_WIDTH_MASK; 1825 pl330->pcfg.data_bus_width = 8 * (1 << val); 1826 1827 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; 1828 val &= CRD_DATA_BUFF_MASK; 1829 pl330->pcfg.data_buf_dep = val + 1; 1830 1831 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; 1832 val &= CR0_NUM_CHANS_MASK; 1833 val += 1; 1834 pl330->pcfg.num_chan = val; 1835 1836 val = readl(regs + CR0); 1837 if (val & CR0_PERIPH_REQ_SET) { 1838 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; 1839 val += 1; 1840 pl330->pcfg.num_peri = val; 1841 pl330->pcfg.peri_ns = readl(regs + CR4); 1842 } else { 1843 pl330->pcfg.num_peri = 0; 1844 } 1845 1846 val = readl(regs + CR0); 1847 if (val & CR0_BOOT_MAN_NS) 1848 pl330->pcfg.mode |= DMAC_MODE_NS; 1849 else 1850 pl330->pcfg.mode &= ~DMAC_MODE_NS; 1851 1852 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; 1853 val &= CR0_NUM_EVENTS_MASK; 1854 val += 1; 1855 pl330->pcfg.num_events = val; 1856 1857 pl330->pcfg.irq_ns = readl(regs + CR3); 1858 } 1859 1860 static inline void _reset_thread(struct pl330_thread *thrd) 1861 { 1862 struct pl330_dmac *pl330 = thrd->dmac; 1863 1864 thrd->req[0].mc_cpu = pl330->mcode_cpu 1865 + (thrd->id * pl330->mcbufsz); 1866 thrd->req[0].mc_bus = pl330->mcode_bus 1867 + (thrd->id * pl330->mcbufsz); 1868 thrd->req[0].desc = NULL; 1869 1870 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu 1871 + pl330->mcbufsz / 2; 1872 thrd->req[1].mc_bus = thrd->req[0].mc_bus 1873 + pl330->mcbufsz / 2; 1874 thrd->req[1].desc = NULL; 1875 1876 thrd->req_running = -1; 1877 } 1878 1879 static int dmac_alloc_threads(struct pl330_dmac *pl330) 1880 { 1881 int chans = pl330->pcfg.num_chan; 1882 struct pl330_thread *thrd; 1883 int i; 1884 1885 /* Allocate 1 Manager and 'chans' Channel threads */ 1886 pl330->channels = kcalloc(1 + chans, sizeof(*thrd), 1887 GFP_KERNEL); 1888 if (!pl330->channels) 1889 return -ENOMEM; 1890 1891 /* Init Channel threads */ 1892 for (i = 0; i < chans; i++) { 1893 thrd = &pl330->channels[i]; 1894 thrd->id = i; 1895 thrd->dmac = pl330; 1896 _reset_thread(thrd); 1897 thrd->free = true; 1898 } 1899 1900 /* MANAGER is indexed at the end */ 1901 thrd = &pl330->channels[chans]; 1902 thrd->id = chans; 1903 thrd->dmac = pl330; 1904 thrd->free = false; 1905 pl330->manager = thrd; 1906 1907 return 0; 1908 } 1909 1910 static int dmac_alloc_resources(struct pl330_dmac *pl330) 1911 { 1912 int chans = pl330->pcfg.num_chan; 1913 int ret; 1914 1915 /* 1916 * Alloc MicroCode buffer for 'chans' Channel threads. 1917 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN) 1918 */ 1919 pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev, 1920 chans * pl330->mcbufsz, 1921 &pl330->mcode_bus, GFP_KERNEL, 1922 DMA_ATTR_PRIVILEGED); 1923 if (!pl330->mcode_cpu) { 1924 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n", 1925 __func__, __LINE__); 1926 return -ENOMEM; 1927 } 1928 1929 ret = dmac_alloc_threads(pl330); 1930 if (ret) { 1931 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n", 1932 __func__, __LINE__); 1933 dma_free_attrs(pl330->ddma.dev, 1934 chans * pl330->mcbufsz, 1935 pl330->mcode_cpu, pl330->mcode_bus, 1936 DMA_ATTR_PRIVILEGED); 1937 return ret; 1938 } 1939 1940 return 0; 1941 } 1942 1943 static int pl330_add(struct pl330_dmac *pl330) 1944 { 1945 int i, ret; 1946 1947 /* Check if we can handle this DMAC */ 1948 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) { 1949 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n", 1950 pl330->pcfg.periph_id); 1951 return -EINVAL; 1952 } 1953 1954 /* Read the configuration of the DMAC */ 1955 read_dmac_config(pl330); 1956 1957 if (pl330->pcfg.num_events == 0) { 1958 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n", 1959 __func__, __LINE__); 1960 return -EINVAL; 1961 } 1962 1963 spin_lock_init(&pl330->lock); 1964 1965 INIT_LIST_HEAD(&pl330->req_done); 1966 1967 /* Use default MC buffer size if not provided */ 1968 if (!pl330->mcbufsz) 1969 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2; 1970 1971 /* Mark all events as free */ 1972 for (i = 0; i < pl330->pcfg.num_events; i++) 1973 pl330->events[i] = -1; 1974 1975 /* Allocate resources needed by the DMAC */ 1976 ret = dmac_alloc_resources(pl330); 1977 if (ret) { 1978 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n"); 1979 return ret; 1980 } 1981 1982 tasklet_setup(&pl330->tasks, pl330_dotask); 1983 1984 pl330->state = INIT; 1985 1986 return 0; 1987 } 1988 1989 static int dmac_free_threads(struct pl330_dmac *pl330) 1990 { 1991 struct pl330_thread *thrd; 1992 int i; 1993 1994 /* Release Channel threads */ 1995 for (i = 0; i < pl330->pcfg.num_chan; i++) { 1996 thrd = &pl330->channels[i]; 1997 pl330_release_channel(thrd); 1998 } 1999 2000 /* Free memory */ 2001 kfree(pl330->channels); 2002 2003 return 0; 2004 } 2005 2006 static void pl330_del(struct pl330_dmac *pl330) 2007 { 2008 pl330->state = UNINIT; 2009 2010 tasklet_kill(&pl330->tasks); 2011 2012 /* Free DMAC resources */ 2013 dmac_free_threads(pl330); 2014 2015 dma_free_attrs(pl330->ddma.dev, 2016 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu, 2017 pl330->mcode_bus, DMA_ATTR_PRIVILEGED); 2018 } 2019 2020 /* forward declaration */ 2021 static struct amba_driver pl330_driver; 2022 2023 static inline struct dma_pl330_chan * 2024 to_pchan(struct dma_chan *ch) 2025 { 2026 if (!ch) 2027 return NULL; 2028 2029 return container_of(ch, struct dma_pl330_chan, chan); 2030 } 2031 2032 static inline struct dma_pl330_desc * 2033 to_desc(struct dma_async_tx_descriptor *tx) 2034 { 2035 return container_of(tx, struct dma_pl330_desc, txd); 2036 } 2037 2038 static inline void fill_queue(struct dma_pl330_chan *pch) 2039 { 2040 struct dma_pl330_desc *desc; 2041 int ret; 2042 2043 list_for_each_entry(desc, &pch->work_list, node) { 2044 2045 /* If already submitted */ 2046 if (desc->status == BUSY) 2047 continue; 2048 2049 ret = pl330_submit_req(pch->thread, desc); 2050 if (!ret) { 2051 desc->status = BUSY; 2052 } else if (ret == -EAGAIN) { 2053 /* QFull or DMAC Dying */ 2054 break; 2055 } else { 2056 /* Unacceptable request */ 2057 desc->status = DONE; 2058 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n", 2059 __func__, __LINE__, desc->txd.cookie); 2060 tasklet_schedule(&pch->task); 2061 } 2062 } 2063 } 2064 2065 static void pl330_tasklet(struct tasklet_struct *t) 2066 { 2067 struct dma_pl330_chan *pch = from_tasklet(pch, t, task); 2068 struct dma_pl330_desc *desc, *_dt; 2069 unsigned long flags; 2070 bool power_down = false; 2071 2072 spin_lock_irqsave(&pch->lock, flags); 2073 2074 /* Pick up ripe tomatoes */ 2075 list_for_each_entry_safe(desc, _dt, &pch->work_list, node) 2076 if (desc->status == DONE) { 2077 if (!pch->cyclic) 2078 dma_cookie_complete(&desc->txd); 2079 list_move_tail(&desc->node, &pch->completed_list); 2080 } 2081 2082 /* Try to submit a req imm. next to the last completed cookie */ 2083 fill_queue(pch); 2084 2085 if (list_empty(&pch->work_list)) { 2086 spin_lock(&pch->thread->dmac->lock); 2087 _stop(pch->thread); 2088 spin_unlock(&pch->thread->dmac->lock); 2089 power_down = true; 2090 pch->active = false; 2091 } else { 2092 /* Make sure the PL330 Channel thread is active */ 2093 spin_lock(&pch->thread->dmac->lock); 2094 _start(pch->thread); 2095 spin_unlock(&pch->thread->dmac->lock); 2096 } 2097 2098 while (!list_empty(&pch->completed_list)) { 2099 struct dmaengine_desc_callback cb; 2100 2101 desc = list_first_entry(&pch->completed_list, 2102 struct dma_pl330_desc, node); 2103 2104 dmaengine_desc_get_callback(&desc->txd, &cb); 2105 2106 if (pch->cyclic) { 2107 desc->status = PREP; 2108 list_move_tail(&desc->node, &pch->work_list); 2109 if (power_down) { 2110 pch->active = true; 2111 spin_lock(&pch->thread->dmac->lock); 2112 _start(pch->thread); 2113 spin_unlock(&pch->thread->dmac->lock); 2114 power_down = false; 2115 } 2116 } else { 2117 desc->status = FREE; 2118 list_move_tail(&desc->node, &pch->dmac->desc_pool); 2119 } 2120 2121 dma_descriptor_unmap(&desc->txd); 2122 2123 if (dmaengine_desc_callback_valid(&cb)) { 2124 spin_unlock_irqrestore(&pch->lock, flags); 2125 dmaengine_desc_callback_invoke(&cb, NULL); 2126 spin_lock_irqsave(&pch->lock, flags); 2127 } 2128 } 2129 spin_unlock_irqrestore(&pch->lock, flags); 2130 2131 /* If work list empty, power down */ 2132 if (power_down) { 2133 pm_runtime_mark_last_busy(pch->dmac->ddma.dev); 2134 pm_runtime_put_autosuspend(pch->dmac->ddma.dev); 2135 } 2136 } 2137 2138 static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec, 2139 struct of_dma *ofdma) 2140 { 2141 int count = dma_spec->args_count; 2142 struct pl330_dmac *pl330 = ofdma->of_dma_data; 2143 unsigned int chan_id; 2144 2145 if (!pl330) 2146 return NULL; 2147 2148 if (count != 1) 2149 return NULL; 2150 2151 chan_id = dma_spec->args[0]; 2152 if (chan_id >= pl330->num_peripherals) 2153 return NULL; 2154 2155 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan); 2156 } 2157 2158 static int pl330_alloc_chan_resources(struct dma_chan *chan) 2159 { 2160 struct dma_pl330_chan *pch = to_pchan(chan); 2161 struct pl330_dmac *pl330 = pch->dmac; 2162 unsigned long flags; 2163 2164 spin_lock_irqsave(&pl330->lock, flags); 2165 2166 dma_cookie_init(chan); 2167 pch->cyclic = false; 2168 2169 pch->thread = pl330_request_channel(pl330); 2170 if (!pch->thread) { 2171 spin_unlock_irqrestore(&pl330->lock, flags); 2172 return -ENOMEM; 2173 } 2174 2175 tasklet_setup(&pch->task, pl330_tasklet); 2176 2177 spin_unlock_irqrestore(&pl330->lock, flags); 2178 2179 return 1; 2180 } 2181 2182 /* 2183 * We need the data direction between the DMAC (the dma-mapping "device") and 2184 * the FIFO (the dmaengine "dev"), from the FIFO's point of view. Confusing! 2185 */ 2186 static enum dma_data_direction 2187 pl330_dma_slave_map_dir(enum dma_transfer_direction dir) 2188 { 2189 switch (dir) { 2190 case DMA_MEM_TO_DEV: 2191 return DMA_FROM_DEVICE; 2192 case DMA_DEV_TO_MEM: 2193 return DMA_TO_DEVICE; 2194 case DMA_DEV_TO_DEV: 2195 return DMA_BIDIRECTIONAL; 2196 default: 2197 return DMA_NONE; 2198 } 2199 } 2200 2201 static void pl330_unprep_slave_fifo(struct dma_pl330_chan *pch) 2202 { 2203 if (pch->dir != DMA_NONE) 2204 dma_unmap_resource(pch->chan.device->dev, pch->fifo_dma, 2205 1 << pch->burst_sz, pch->dir, 0); 2206 pch->dir = DMA_NONE; 2207 } 2208 2209 2210 static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch, 2211 enum dma_transfer_direction dir) 2212 { 2213 struct device *dev = pch->chan.device->dev; 2214 enum dma_data_direction dma_dir = pl330_dma_slave_map_dir(dir); 2215 2216 /* Already mapped for this config? */ 2217 if (pch->dir == dma_dir) 2218 return true; 2219 2220 pl330_unprep_slave_fifo(pch); 2221 pch->fifo_dma = dma_map_resource(dev, pch->fifo_addr, 2222 1 << pch->burst_sz, dma_dir, 0); 2223 if (dma_mapping_error(dev, pch->fifo_dma)) 2224 return false; 2225 2226 pch->dir = dma_dir; 2227 return true; 2228 } 2229 2230 static int fixup_burst_len(int max_burst_len, int quirks) 2231 { 2232 if (max_burst_len > PL330_MAX_BURST) 2233 return PL330_MAX_BURST; 2234 else if (max_burst_len < 1) 2235 return 1; 2236 else 2237 return max_burst_len; 2238 } 2239 2240 static int pl330_config_write(struct dma_chan *chan, 2241 struct dma_slave_config *slave_config, 2242 enum dma_transfer_direction direction) 2243 { 2244 struct dma_pl330_chan *pch = to_pchan(chan); 2245 2246 pl330_unprep_slave_fifo(pch); 2247 if (direction == DMA_MEM_TO_DEV) { 2248 if (slave_config->dst_addr) 2249 pch->fifo_addr = slave_config->dst_addr; 2250 if (slave_config->dst_addr_width) 2251 pch->burst_sz = __ffs(slave_config->dst_addr_width); 2252 pch->burst_len = fixup_burst_len(slave_config->dst_maxburst, 2253 pch->dmac->quirks); 2254 } else if (direction == DMA_DEV_TO_MEM) { 2255 if (slave_config->src_addr) 2256 pch->fifo_addr = slave_config->src_addr; 2257 if (slave_config->src_addr_width) 2258 pch->burst_sz = __ffs(slave_config->src_addr_width); 2259 pch->burst_len = fixup_burst_len(slave_config->src_maxburst, 2260 pch->dmac->quirks); 2261 } 2262 2263 return 0; 2264 } 2265 2266 static int pl330_config(struct dma_chan *chan, 2267 struct dma_slave_config *slave_config) 2268 { 2269 struct dma_pl330_chan *pch = to_pchan(chan); 2270 2271 memcpy(&pch->slave_config, slave_config, sizeof(*slave_config)); 2272 2273 return 0; 2274 } 2275 2276 static int pl330_terminate_all(struct dma_chan *chan) 2277 { 2278 struct dma_pl330_chan *pch = to_pchan(chan); 2279 struct dma_pl330_desc *desc; 2280 unsigned long flags; 2281 struct pl330_dmac *pl330 = pch->dmac; 2282 bool power_down = false; 2283 2284 pm_runtime_get_sync(pl330->ddma.dev); 2285 spin_lock_irqsave(&pch->lock, flags); 2286 2287 spin_lock(&pl330->lock); 2288 _stop(pch->thread); 2289 pch->thread->req[0].desc = NULL; 2290 pch->thread->req[1].desc = NULL; 2291 pch->thread->req_running = -1; 2292 spin_unlock(&pl330->lock); 2293 2294 power_down = pch->active; 2295 pch->active = false; 2296 2297 /* Mark all desc done */ 2298 list_for_each_entry(desc, &pch->submitted_list, node) { 2299 desc->status = FREE; 2300 dma_cookie_complete(&desc->txd); 2301 } 2302 2303 list_for_each_entry(desc, &pch->work_list , node) { 2304 desc->status = FREE; 2305 dma_cookie_complete(&desc->txd); 2306 } 2307 2308 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool); 2309 list_splice_tail_init(&pch->work_list, &pl330->desc_pool); 2310 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool); 2311 spin_unlock_irqrestore(&pch->lock, flags); 2312 pm_runtime_mark_last_busy(pl330->ddma.dev); 2313 if (power_down) 2314 pm_runtime_put_autosuspend(pl330->ddma.dev); 2315 pm_runtime_put_autosuspend(pl330->ddma.dev); 2316 2317 return 0; 2318 } 2319 2320 /* 2321 * We don't support DMA_RESUME command because of hardware 2322 * limitations, so after pausing the channel we cannot restore 2323 * it to active state. We have to terminate channel and setup 2324 * DMA transfer again. This pause feature was implemented to 2325 * allow safely read residue before channel termination. 2326 */ 2327 static int pl330_pause(struct dma_chan *chan) 2328 { 2329 struct dma_pl330_chan *pch = to_pchan(chan); 2330 struct pl330_dmac *pl330 = pch->dmac; 2331 unsigned long flags; 2332 2333 pm_runtime_get_sync(pl330->ddma.dev); 2334 spin_lock_irqsave(&pch->lock, flags); 2335 2336 spin_lock(&pl330->lock); 2337 _stop(pch->thread); 2338 spin_unlock(&pl330->lock); 2339 2340 spin_unlock_irqrestore(&pch->lock, flags); 2341 pm_runtime_mark_last_busy(pl330->ddma.dev); 2342 pm_runtime_put_autosuspend(pl330->ddma.dev); 2343 2344 return 0; 2345 } 2346 2347 static void pl330_free_chan_resources(struct dma_chan *chan) 2348 { 2349 struct dma_pl330_chan *pch = to_pchan(chan); 2350 struct pl330_dmac *pl330 = pch->dmac; 2351 unsigned long flags; 2352 2353 tasklet_kill(&pch->task); 2354 2355 pm_runtime_get_sync(pch->dmac->ddma.dev); 2356 spin_lock_irqsave(&pl330->lock, flags); 2357 2358 pl330_release_channel(pch->thread); 2359 pch->thread = NULL; 2360 2361 if (pch->cyclic) 2362 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); 2363 2364 spin_unlock_irqrestore(&pl330->lock, flags); 2365 pm_runtime_mark_last_busy(pch->dmac->ddma.dev); 2366 pm_runtime_put_autosuspend(pch->dmac->ddma.dev); 2367 pl330_unprep_slave_fifo(pch); 2368 } 2369 2370 static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch, 2371 struct dma_pl330_desc *desc) 2372 { 2373 struct pl330_thread *thrd = pch->thread; 2374 struct pl330_dmac *pl330 = pch->dmac; 2375 void __iomem *regs = thrd->dmac->base; 2376 u32 val, addr; 2377 2378 pm_runtime_get_sync(pl330->ddma.dev); 2379 val = addr = 0; 2380 if (desc->rqcfg.src_inc) { 2381 val = readl(regs + SA(thrd->id)); 2382 addr = desc->px.src_addr; 2383 } else { 2384 val = readl(regs + DA(thrd->id)); 2385 addr = desc->px.dst_addr; 2386 } 2387 pm_runtime_mark_last_busy(pch->dmac->ddma.dev); 2388 pm_runtime_put_autosuspend(pl330->ddma.dev); 2389 2390 /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */ 2391 if (!val) 2392 return 0; 2393 2394 return val - addr; 2395 } 2396 2397 static enum dma_status 2398 pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, 2399 struct dma_tx_state *txstate) 2400 { 2401 enum dma_status ret; 2402 unsigned long flags; 2403 struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL; 2404 struct dma_pl330_chan *pch = to_pchan(chan); 2405 unsigned int transferred, residual = 0; 2406 2407 ret = dma_cookie_status(chan, cookie, txstate); 2408 2409 if (!txstate) 2410 return ret; 2411 2412 if (ret == DMA_COMPLETE) 2413 goto out; 2414 2415 spin_lock_irqsave(&pch->lock, flags); 2416 spin_lock(&pch->thread->dmac->lock); 2417 2418 if (pch->thread->req_running != -1) 2419 running = pch->thread->req[pch->thread->req_running].desc; 2420 2421 last_enq = pch->thread->req[pch->thread->lstenq].desc; 2422 2423 /* Check in pending list */ 2424 list_for_each_entry(desc, &pch->work_list, node) { 2425 if (desc->status == DONE) 2426 transferred = desc->bytes_requested; 2427 else if (running && desc == running) 2428 transferred = 2429 pl330_get_current_xferred_count(pch, desc); 2430 else if (desc->status == BUSY) 2431 /* 2432 * Busy but not running means either just enqueued, 2433 * or finished and not yet marked done 2434 */ 2435 if (desc == last_enq) 2436 transferred = 0; 2437 else 2438 transferred = desc->bytes_requested; 2439 else 2440 transferred = 0; 2441 residual += desc->bytes_requested - transferred; 2442 if (desc->txd.cookie == cookie) { 2443 switch (desc->status) { 2444 case DONE: 2445 ret = DMA_COMPLETE; 2446 break; 2447 case PREP: 2448 case BUSY: 2449 ret = DMA_IN_PROGRESS; 2450 break; 2451 default: 2452 WARN_ON(1); 2453 } 2454 break; 2455 } 2456 if (desc->last) 2457 residual = 0; 2458 } 2459 spin_unlock(&pch->thread->dmac->lock); 2460 spin_unlock_irqrestore(&pch->lock, flags); 2461 2462 out: 2463 dma_set_residue(txstate, residual); 2464 2465 return ret; 2466 } 2467 2468 static void pl330_issue_pending(struct dma_chan *chan) 2469 { 2470 struct dma_pl330_chan *pch = to_pchan(chan); 2471 unsigned long flags; 2472 2473 spin_lock_irqsave(&pch->lock, flags); 2474 if (list_empty(&pch->work_list)) { 2475 /* 2476 * Warn on nothing pending. Empty submitted_list may 2477 * break our pm_runtime usage counter as it is 2478 * updated on work_list emptiness status. 2479 */ 2480 WARN_ON(list_empty(&pch->submitted_list)); 2481 pch->active = true; 2482 pm_runtime_get_sync(pch->dmac->ddma.dev); 2483 } 2484 list_splice_tail_init(&pch->submitted_list, &pch->work_list); 2485 spin_unlock_irqrestore(&pch->lock, flags); 2486 2487 pl330_tasklet(&pch->task); 2488 } 2489 2490 /* 2491 * We returned the last one of the circular list of descriptor(s) 2492 * from prep_xxx, so the argument to submit corresponds to the last 2493 * descriptor of the list. 2494 */ 2495 static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) 2496 { 2497 struct dma_pl330_desc *desc, *last = to_desc(tx); 2498 struct dma_pl330_chan *pch = to_pchan(tx->chan); 2499 dma_cookie_t cookie; 2500 unsigned long flags; 2501 2502 spin_lock_irqsave(&pch->lock, flags); 2503 2504 /* Assign cookies to all nodes */ 2505 while (!list_empty(&last->node)) { 2506 desc = list_entry(last->node.next, struct dma_pl330_desc, node); 2507 if (pch->cyclic) { 2508 desc->txd.callback = last->txd.callback; 2509 desc->txd.callback_param = last->txd.callback_param; 2510 } 2511 desc->last = false; 2512 2513 dma_cookie_assign(&desc->txd); 2514 2515 list_move_tail(&desc->node, &pch->submitted_list); 2516 } 2517 2518 last->last = true; 2519 cookie = dma_cookie_assign(&last->txd); 2520 list_add_tail(&last->node, &pch->submitted_list); 2521 spin_unlock_irqrestore(&pch->lock, flags); 2522 2523 return cookie; 2524 } 2525 2526 static inline void _init_desc(struct dma_pl330_desc *desc) 2527 { 2528 desc->rqcfg.swap = SWAP_NO; 2529 desc->rqcfg.scctl = CCTRL0; 2530 desc->rqcfg.dcctl = CCTRL0; 2531 desc->txd.tx_submit = pl330_tx_submit; 2532 2533 INIT_LIST_HEAD(&desc->node); 2534 } 2535 2536 /* Returns the number of descriptors added to the DMAC pool */ 2537 static int add_desc(struct list_head *pool, spinlock_t *lock, 2538 gfp_t flg, int count) 2539 { 2540 struct dma_pl330_desc *desc; 2541 unsigned long flags; 2542 int i; 2543 2544 desc = kcalloc(count, sizeof(*desc), flg); 2545 if (!desc) 2546 return 0; 2547 2548 spin_lock_irqsave(lock, flags); 2549 2550 for (i = 0; i < count; i++) { 2551 _init_desc(&desc[i]); 2552 list_add_tail(&desc[i].node, pool); 2553 } 2554 2555 spin_unlock_irqrestore(lock, flags); 2556 2557 return count; 2558 } 2559 2560 static struct dma_pl330_desc *pluck_desc(struct list_head *pool, 2561 spinlock_t *lock) 2562 { 2563 struct dma_pl330_desc *desc = NULL; 2564 unsigned long flags; 2565 2566 spin_lock_irqsave(lock, flags); 2567 2568 if (!list_empty(pool)) { 2569 desc = list_entry(pool->next, 2570 struct dma_pl330_desc, node); 2571 2572 list_del_init(&desc->node); 2573 2574 desc->status = PREP; 2575 desc->txd.callback = NULL; 2576 } 2577 2578 spin_unlock_irqrestore(lock, flags); 2579 2580 return desc; 2581 } 2582 2583 static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) 2584 { 2585 struct pl330_dmac *pl330 = pch->dmac; 2586 u8 *peri_id = pch->chan.private; 2587 struct dma_pl330_desc *desc; 2588 2589 /* Pluck one desc from the pool of DMAC */ 2590 desc = pluck_desc(&pl330->desc_pool, &pl330->pool_lock); 2591 2592 /* If the DMAC pool is empty, alloc new */ 2593 if (!desc) { 2594 DEFINE_SPINLOCK(lock); 2595 LIST_HEAD(pool); 2596 2597 if (!add_desc(&pool, &lock, GFP_ATOMIC, 1)) 2598 return NULL; 2599 2600 desc = pluck_desc(&pool, &lock); 2601 WARN_ON(!desc || !list_empty(&pool)); 2602 } 2603 2604 /* Initialize the descriptor */ 2605 desc->pchan = pch; 2606 desc->txd.cookie = 0; 2607 async_tx_ack(&desc->txd); 2608 2609 desc->peri = peri_id ? pch->chan.chan_id : 0; 2610 desc->rqcfg.pcfg = &pch->dmac->pcfg; 2611 2612 dma_async_tx_descriptor_init(&desc->txd, &pch->chan); 2613 2614 return desc; 2615 } 2616 2617 static inline void fill_px(struct pl330_xfer *px, 2618 dma_addr_t dst, dma_addr_t src, size_t len) 2619 { 2620 px->bytes = len; 2621 px->dst_addr = dst; 2622 px->src_addr = src; 2623 } 2624 2625 static struct dma_pl330_desc * 2626 __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, 2627 dma_addr_t src, size_t len) 2628 { 2629 struct dma_pl330_desc *desc = pl330_get_desc(pch); 2630 2631 if (!desc) { 2632 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", 2633 __func__, __LINE__); 2634 return NULL; 2635 } 2636 2637 /* 2638 * Ideally we should lookout for reqs bigger than 2639 * those that can be programmed with 256 bytes of 2640 * MC buffer, but considering a req size is seldom 2641 * going to be word-unaligned and more than 200MB, 2642 * we take it easy. 2643 * Also, should the limit is reached we'd rather 2644 * have the platform increase MC buffer size than 2645 * complicating this API driver. 2646 */ 2647 fill_px(&desc->px, dst, src, len); 2648 2649 return desc; 2650 } 2651 2652 /* Call after fixing burst size */ 2653 static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) 2654 { 2655 struct dma_pl330_chan *pch = desc->pchan; 2656 struct pl330_dmac *pl330 = pch->dmac; 2657 int burst_len; 2658 2659 burst_len = pl330->pcfg.data_bus_width / 8; 2660 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan; 2661 burst_len >>= desc->rqcfg.brst_size; 2662 2663 /* src/dst_burst_len can't be more than 16 */ 2664 if (burst_len > PL330_MAX_BURST) 2665 burst_len = PL330_MAX_BURST; 2666 2667 return burst_len; 2668 } 2669 2670 static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( 2671 struct dma_chan *chan, dma_addr_t dma_addr, size_t len, 2672 size_t period_len, enum dma_transfer_direction direction, 2673 unsigned long flags) 2674 { 2675 struct dma_pl330_desc *desc = NULL, *first = NULL; 2676 struct dma_pl330_chan *pch = to_pchan(chan); 2677 struct pl330_dmac *pl330 = pch->dmac; 2678 unsigned int i; 2679 dma_addr_t dst; 2680 dma_addr_t src; 2681 2682 if (len % period_len != 0) 2683 return NULL; 2684 2685 if (!is_slave_direction(direction)) { 2686 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n", 2687 __func__, __LINE__); 2688 return NULL; 2689 } 2690 2691 pl330_config_write(chan, &pch->slave_config, direction); 2692 2693 if (!pl330_prep_slave_fifo(pch, direction)) 2694 return NULL; 2695 2696 for (i = 0; i < len / period_len; i++) { 2697 desc = pl330_get_desc(pch); 2698 if (!desc) { 2699 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", 2700 __func__, __LINE__); 2701 2702 if (!first) 2703 return NULL; 2704 2705 spin_lock_irqsave(&pl330->pool_lock, flags); 2706 2707 while (!list_empty(&first->node)) { 2708 desc = list_entry(first->node.next, 2709 struct dma_pl330_desc, node); 2710 list_move_tail(&desc->node, &pl330->desc_pool); 2711 } 2712 2713 list_move_tail(&first->node, &pl330->desc_pool); 2714 2715 spin_unlock_irqrestore(&pl330->pool_lock, flags); 2716 2717 return NULL; 2718 } 2719 2720 switch (direction) { 2721 case DMA_MEM_TO_DEV: 2722 desc->rqcfg.src_inc = 1; 2723 desc->rqcfg.dst_inc = 0; 2724 src = dma_addr; 2725 dst = pch->fifo_dma; 2726 break; 2727 case DMA_DEV_TO_MEM: 2728 desc->rqcfg.src_inc = 0; 2729 desc->rqcfg.dst_inc = 1; 2730 src = pch->fifo_dma; 2731 dst = dma_addr; 2732 break; 2733 default: 2734 break; 2735 } 2736 2737 desc->rqtype = direction; 2738 desc->rqcfg.brst_size = pch->burst_sz; 2739 desc->rqcfg.brst_len = pch->burst_len; 2740 desc->bytes_requested = period_len; 2741 fill_px(&desc->px, dst, src, period_len); 2742 2743 if (!first) 2744 first = desc; 2745 else 2746 list_add_tail(&desc->node, &first->node); 2747 2748 dma_addr += period_len; 2749 } 2750 2751 if (!desc) 2752 return NULL; 2753 2754 pch->cyclic = true; 2755 desc->txd.flags = flags; 2756 2757 return &desc->txd; 2758 } 2759 2760 static struct dma_async_tx_descriptor * 2761 pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, 2762 dma_addr_t src, size_t len, unsigned long flags) 2763 { 2764 struct dma_pl330_desc *desc; 2765 struct dma_pl330_chan *pch = to_pchan(chan); 2766 struct pl330_dmac *pl330; 2767 int burst; 2768 2769 if (unlikely(!pch || !len)) 2770 return NULL; 2771 2772 pl330 = pch->dmac; 2773 2774 desc = __pl330_prep_dma_memcpy(pch, dst, src, len); 2775 if (!desc) 2776 return NULL; 2777 2778 desc->rqcfg.src_inc = 1; 2779 desc->rqcfg.dst_inc = 1; 2780 desc->rqtype = DMA_MEM_TO_MEM; 2781 2782 /* Select max possible burst size */ 2783 burst = pl330->pcfg.data_bus_width / 8; 2784 2785 /* 2786 * Make sure we use a burst size that aligns with all the memcpy 2787 * parameters because our DMA programming algorithm doesn't cope with 2788 * transfers which straddle an entry in the DMA device's MFIFO. 2789 */ 2790 while ((src | dst | len) & (burst - 1)) 2791 burst /= 2; 2792 2793 desc->rqcfg.brst_size = 0; 2794 while (burst != (1 << desc->rqcfg.brst_size)) 2795 desc->rqcfg.brst_size++; 2796 2797 desc->rqcfg.brst_len = get_burst_len(desc, len); 2798 /* 2799 * If burst size is smaller than bus width then make sure we only 2800 * transfer one at a time to avoid a burst stradling an MFIFO entry. 2801 */ 2802 if (burst * 8 < pl330->pcfg.data_bus_width) 2803 desc->rqcfg.brst_len = 1; 2804 2805 desc->bytes_requested = len; 2806 2807 desc->txd.flags = flags; 2808 2809 return &desc->txd; 2810 } 2811 2812 static void __pl330_giveback_desc(struct pl330_dmac *pl330, 2813 struct dma_pl330_desc *first) 2814 { 2815 unsigned long flags; 2816 struct dma_pl330_desc *desc; 2817 2818 if (!first) 2819 return; 2820 2821 spin_lock_irqsave(&pl330->pool_lock, flags); 2822 2823 while (!list_empty(&first->node)) { 2824 desc = list_entry(first->node.next, 2825 struct dma_pl330_desc, node); 2826 list_move_tail(&desc->node, &pl330->desc_pool); 2827 } 2828 2829 list_move_tail(&first->node, &pl330->desc_pool); 2830 2831 spin_unlock_irqrestore(&pl330->pool_lock, flags); 2832 } 2833 2834 static struct dma_async_tx_descriptor * 2835 pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 2836 unsigned int sg_len, enum dma_transfer_direction direction, 2837 unsigned long flg, void *context) 2838 { 2839 struct dma_pl330_desc *first, *desc = NULL; 2840 struct dma_pl330_chan *pch = to_pchan(chan); 2841 struct scatterlist *sg; 2842 int i; 2843 2844 if (unlikely(!pch || !sgl || !sg_len)) 2845 return NULL; 2846 2847 pl330_config_write(chan, &pch->slave_config, direction); 2848 2849 if (!pl330_prep_slave_fifo(pch, direction)) 2850 return NULL; 2851 2852 first = NULL; 2853 2854 for_each_sg(sgl, sg, sg_len, i) { 2855 2856 desc = pl330_get_desc(pch); 2857 if (!desc) { 2858 struct pl330_dmac *pl330 = pch->dmac; 2859 2860 dev_err(pch->dmac->ddma.dev, 2861 "%s:%d Unable to fetch desc\n", 2862 __func__, __LINE__); 2863 __pl330_giveback_desc(pl330, first); 2864 2865 return NULL; 2866 } 2867 2868 if (!first) 2869 first = desc; 2870 else 2871 list_add_tail(&desc->node, &first->node); 2872 2873 if (direction == DMA_MEM_TO_DEV) { 2874 desc->rqcfg.src_inc = 1; 2875 desc->rqcfg.dst_inc = 0; 2876 fill_px(&desc->px, pch->fifo_dma, sg_dma_address(sg), 2877 sg_dma_len(sg)); 2878 } else { 2879 desc->rqcfg.src_inc = 0; 2880 desc->rqcfg.dst_inc = 1; 2881 fill_px(&desc->px, sg_dma_address(sg), pch->fifo_dma, 2882 sg_dma_len(sg)); 2883 } 2884 2885 desc->rqcfg.brst_size = pch->burst_sz; 2886 desc->rqcfg.brst_len = pch->burst_len; 2887 desc->rqtype = direction; 2888 desc->bytes_requested = sg_dma_len(sg); 2889 } 2890 2891 /* Return the last desc in the chain */ 2892 desc->txd.flags = flg; 2893 return &desc->txd; 2894 } 2895 2896 static irqreturn_t pl330_irq_handler(int irq, void *data) 2897 { 2898 if (pl330_update(data)) 2899 return IRQ_HANDLED; 2900 else 2901 return IRQ_NONE; 2902 } 2903 2904 #define PL330_DMA_BUSWIDTHS \ 2905 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ 2906 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 2907 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 2908 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ 2909 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) 2910 2911 #ifdef CONFIG_DEBUG_FS 2912 static int pl330_debugfs_show(struct seq_file *s, void *data) 2913 { 2914 struct pl330_dmac *pl330 = s->private; 2915 int chans, pchs, ch, pr; 2916 2917 chans = pl330->pcfg.num_chan; 2918 pchs = pl330->num_peripherals; 2919 2920 seq_puts(s, "PL330 physical channels:\n"); 2921 seq_puts(s, "THREAD:\t\tCHANNEL:\n"); 2922 seq_puts(s, "--------\t-----\n"); 2923 for (ch = 0; ch < chans; ch++) { 2924 struct pl330_thread *thrd = &pl330->channels[ch]; 2925 int found = -1; 2926 2927 for (pr = 0; pr < pchs; pr++) { 2928 struct dma_pl330_chan *pch = &pl330->peripherals[pr]; 2929 2930 if (!pch->thread || thrd->id != pch->thread->id) 2931 continue; 2932 2933 found = pr; 2934 } 2935 2936 seq_printf(s, "%d\t\t", thrd->id); 2937 if (found == -1) 2938 seq_puts(s, "--\n"); 2939 else 2940 seq_printf(s, "%d\n", found); 2941 } 2942 2943 return 0; 2944 } 2945 2946 DEFINE_SHOW_ATTRIBUTE(pl330_debugfs); 2947 2948 static inline void init_pl330_debugfs(struct pl330_dmac *pl330) 2949 { 2950 debugfs_create_file(dev_name(pl330->ddma.dev), 2951 S_IFREG | 0444, NULL, pl330, 2952 &pl330_debugfs_fops); 2953 } 2954 #else 2955 static inline void init_pl330_debugfs(struct pl330_dmac *pl330) 2956 { 2957 } 2958 #endif 2959 2960 /* 2961 * Runtime PM callbacks are provided by amba/bus.c driver. 2962 * 2963 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba 2964 * bus driver will only disable/enable the clock in runtime PM callbacks. 2965 */ 2966 static int __maybe_unused pl330_suspend(struct device *dev) 2967 { 2968 struct amba_device *pcdev = to_amba_device(dev); 2969 2970 pm_runtime_force_suspend(dev); 2971 amba_pclk_unprepare(pcdev); 2972 2973 return 0; 2974 } 2975 2976 static int __maybe_unused pl330_resume(struct device *dev) 2977 { 2978 struct amba_device *pcdev = to_amba_device(dev); 2979 int ret; 2980 2981 ret = amba_pclk_prepare(pcdev); 2982 if (ret) 2983 return ret; 2984 2985 pm_runtime_force_resume(dev); 2986 2987 return ret; 2988 } 2989 2990 static const struct dev_pm_ops pl330_pm = { 2991 SET_LATE_SYSTEM_SLEEP_PM_OPS(pl330_suspend, pl330_resume) 2992 }; 2993 2994 static int 2995 pl330_probe(struct amba_device *adev, const struct amba_id *id) 2996 { 2997 struct pl330_config *pcfg; 2998 struct pl330_dmac *pl330; 2999 struct dma_pl330_chan *pch, *_p; 3000 struct dma_device *pd; 3001 struct resource *res; 3002 int i, ret, irq; 3003 int num_chan; 3004 struct device_node *np = adev->dev.of_node; 3005 3006 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32)); 3007 if (ret) 3008 return ret; 3009 3010 /* Allocate a new DMAC and its Channels */ 3011 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL); 3012 if (!pl330) 3013 return -ENOMEM; 3014 3015 pd = &pl330->ddma; 3016 pd->dev = &adev->dev; 3017 3018 pl330->mcbufsz = 0; 3019 3020 /* get quirk */ 3021 for (i = 0; i < ARRAY_SIZE(of_quirks); i++) 3022 if (of_property_read_bool(np, of_quirks[i].quirk)) 3023 pl330->quirks |= of_quirks[i].id; 3024 3025 res = &adev->res; 3026 pl330->base = devm_ioremap_resource(&adev->dev, res); 3027 if (IS_ERR(pl330->base)) 3028 return PTR_ERR(pl330->base); 3029 3030 amba_set_drvdata(adev, pl330); 3031 3032 pl330->rstc = devm_reset_control_get_optional(&adev->dev, "dma"); 3033 if (IS_ERR(pl330->rstc)) { 3034 return dev_err_probe(&adev->dev, PTR_ERR(pl330->rstc), "Failed to get reset!\n"); 3035 } else { 3036 ret = reset_control_deassert(pl330->rstc); 3037 if (ret) { 3038 dev_err(&adev->dev, "Couldn't deassert the device from reset!\n"); 3039 return ret; 3040 } 3041 } 3042 3043 pl330->rstc_ocp = devm_reset_control_get_optional(&adev->dev, "dma-ocp"); 3044 if (IS_ERR(pl330->rstc_ocp)) { 3045 return dev_err_probe(&adev->dev, PTR_ERR(pl330->rstc_ocp), 3046 "Failed to get OCP reset!\n"); 3047 } else { 3048 ret = reset_control_deassert(pl330->rstc_ocp); 3049 if (ret) { 3050 dev_err(&adev->dev, "Couldn't deassert the device from OCP reset!\n"); 3051 return ret; 3052 } 3053 } 3054 3055 for (i = 0; i < AMBA_NR_IRQS; i++) { 3056 irq = adev->irq[i]; 3057 if (irq) { 3058 ret = devm_request_irq(&adev->dev, irq, 3059 pl330_irq_handler, 0, 3060 dev_name(&adev->dev), pl330); 3061 if (ret) 3062 return ret; 3063 } else { 3064 break; 3065 } 3066 } 3067 3068 pcfg = &pl330->pcfg; 3069 3070 pcfg->periph_id = adev->periphid; 3071 ret = pl330_add(pl330); 3072 if (ret) 3073 return ret; 3074 3075 INIT_LIST_HEAD(&pl330->desc_pool); 3076 spin_lock_init(&pl330->pool_lock); 3077 3078 /* Create a descriptor pool of default size */ 3079 if (!add_desc(&pl330->desc_pool, &pl330->pool_lock, 3080 GFP_KERNEL, NR_DEFAULT_DESC)) 3081 dev_warn(&adev->dev, "unable to allocate desc\n"); 3082 3083 INIT_LIST_HEAD(&pd->channels); 3084 3085 /* Initialize channel parameters */ 3086 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan); 3087 3088 pl330->num_peripherals = num_chan; 3089 3090 pl330->peripherals = kcalloc(num_chan, sizeof(*pch), GFP_KERNEL); 3091 if (!pl330->peripherals) { 3092 ret = -ENOMEM; 3093 goto probe_err2; 3094 } 3095 3096 for (i = 0; i < num_chan; i++) { 3097 pch = &pl330->peripherals[i]; 3098 3099 pch->chan.private = adev->dev.of_node; 3100 INIT_LIST_HEAD(&pch->submitted_list); 3101 INIT_LIST_HEAD(&pch->work_list); 3102 INIT_LIST_HEAD(&pch->completed_list); 3103 spin_lock_init(&pch->lock); 3104 pch->thread = NULL; 3105 pch->chan.device = pd; 3106 pch->dmac = pl330; 3107 pch->dir = DMA_NONE; 3108 3109 /* Add the channel to the DMAC list */ 3110 list_add_tail(&pch->chan.device_node, &pd->channels); 3111 } 3112 3113 dma_cap_set(DMA_MEMCPY, pd->cap_mask); 3114 if (pcfg->num_peri) { 3115 dma_cap_set(DMA_SLAVE, pd->cap_mask); 3116 dma_cap_set(DMA_CYCLIC, pd->cap_mask); 3117 dma_cap_set(DMA_PRIVATE, pd->cap_mask); 3118 } 3119 3120 pd->device_alloc_chan_resources = pl330_alloc_chan_resources; 3121 pd->device_free_chan_resources = pl330_free_chan_resources; 3122 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; 3123 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; 3124 pd->device_tx_status = pl330_tx_status; 3125 pd->device_prep_slave_sg = pl330_prep_slave_sg; 3126 pd->device_config = pl330_config; 3127 pd->device_pause = pl330_pause; 3128 pd->device_terminate_all = pl330_terminate_all; 3129 pd->device_issue_pending = pl330_issue_pending; 3130 pd->src_addr_widths = PL330_DMA_BUSWIDTHS; 3131 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS; 3132 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 3133 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 3134 pd->max_burst = PL330_MAX_BURST; 3135 3136 ret = dma_async_device_register(pd); 3137 if (ret) { 3138 dev_err(&adev->dev, "unable to register DMAC\n"); 3139 goto probe_err3; 3140 } 3141 3142 if (adev->dev.of_node) { 3143 ret = of_dma_controller_register(adev->dev.of_node, 3144 of_dma_pl330_xlate, pl330); 3145 if (ret) { 3146 dev_err(&adev->dev, 3147 "unable to register DMA to the generic DT DMA helpers\n"); 3148 } 3149 } 3150 3151 /* 3152 * This is the limit for transfers with a buswidth of 1, larger 3153 * buswidths will have larger limits. 3154 */ 3155 ret = dma_set_max_seg_size(&adev->dev, 1900800); 3156 if (ret) 3157 dev_err(&adev->dev, "unable to set the seg size\n"); 3158 3159 3160 init_pl330_debugfs(pl330); 3161 dev_info(&adev->dev, 3162 "Loaded driver for PL330 DMAC-%x\n", adev->periphid); 3163 dev_info(&adev->dev, 3164 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", 3165 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan, 3166 pcfg->num_peri, pcfg->num_events); 3167 3168 pm_runtime_irq_safe(&adev->dev); 3169 pm_runtime_use_autosuspend(&adev->dev); 3170 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY); 3171 pm_runtime_mark_last_busy(&adev->dev); 3172 pm_runtime_put_autosuspend(&adev->dev); 3173 3174 return 0; 3175 probe_err3: 3176 /* Idle the DMAC */ 3177 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, 3178 chan.device_node) { 3179 3180 /* Remove the channel */ 3181 list_del(&pch->chan.device_node); 3182 3183 /* Flush the channel */ 3184 if (pch->thread) { 3185 pl330_terminate_all(&pch->chan); 3186 pl330_free_chan_resources(&pch->chan); 3187 } 3188 } 3189 probe_err2: 3190 pl330_del(pl330); 3191 3192 if (pl330->rstc_ocp) 3193 reset_control_assert(pl330->rstc_ocp); 3194 3195 if (pl330->rstc) 3196 reset_control_assert(pl330->rstc); 3197 return ret; 3198 } 3199 3200 static int pl330_remove(struct amba_device *adev) 3201 { 3202 struct pl330_dmac *pl330 = amba_get_drvdata(adev); 3203 struct dma_pl330_chan *pch, *_p; 3204 int i, irq; 3205 3206 pm_runtime_get_noresume(pl330->ddma.dev); 3207 3208 if (adev->dev.of_node) 3209 of_dma_controller_free(adev->dev.of_node); 3210 3211 for (i = 0; i < AMBA_NR_IRQS; i++) { 3212 irq = adev->irq[i]; 3213 if (irq) 3214 devm_free_irq(&adev->dev, irq, pl330); 3215 } 3216 3217 dma_async_device_unregister(&pl330->ddma); 3218 3219 /* Idle the DMAC */ 3220 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, 3221 chan.device_node) { 3222 3223 /* Remove the channel */ 3224 list_del(&pch->chan.device_node); 3225 3226 /* Flush the channel */ 3227 if (pch->thread) { 3228 pl330_terminate_all(&pch->chan); 3229 pl330_free_chan_resources(&pch->chan); 3230 } 3231 } 3232 3233 pl330_del(pl330); 3234 3235 if (pl330->rstc_ocp) 3236 reset_control_assert(pl330->rstc_ocp); 3237 3238 if (pl330->rstc) 3239 reset_control_assert(pl330->rstc); 3240 return 0; 3241 } 3242 3243 static const struct amba_id pl330_ids[] = { 3244 { 3245 .id = 0x00041330, 3246 .mask = 0x000fffff, 3247 }, 3248 { 0, 0 }, 3249 }; 3250 3251 MODULE_DEVICE_TABLE(amba, pl330_ids); 3252 3253 static struct amba_driver pl330_driver = { 3254 .drv = { 3255 .owner = THIS_MODULE, 3256 .name = "dma-pl330", 3257 .pm = &pl330_pm, 3258 }, 3259 .id_table = pl330_ids, 3260 .probe = pl330_probe, 3261 .remove = pl330_remove, 3262 }; 3263 3264 module_amba_driver(pl330_driver); 3265 3266 MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>"); 3267 MODULE_DESCRIPTION("API Driver for PL330 DMAC"); 3268 MODULE_LICENSE("GPL"); 3269