1b7d861d9SBoojin Kim /* 2b7d861d9SBoojin Kim * Copyright (c) 2012 Samsung Electronics Co., Ltd. 3b7d861d9SBoojin Kim * http://www.samsung.com 4b3040e40SJassi Brar * 5b3040e40SJassi Brar * Copyright (C) 2010 Samsung Electronics Co. Ltd. 6b3040e40SJassi Brar * Jaswinder Singh <jassi.brar@samsung.com> 7b3040e40SJassi Brar * 8b3040e40SJassi Brar * This program is free software; you can redistribute it and/or modify 9b3040e40SJassi Brar * it under the terms of the GNU General Public License as published by 10b3040e40SJassi Brar * the Free Software Foundation; either version 2 of the License, or 11b3040e40SJassi Brar * (at your option) any later version. 12b3040e40SJassi Brar */ 13b3040e40SJassi Brar 14b7d861d9SBoojin Kim #include <linux/kernel.h> 15b3040e40SJassi Brar #include <linux/io.h> 16b3040e40SJassi Brar #include <linux/init.h> 17b3040e40SJassi Brar #include <linux/slab.h> 18b3040e40SJassi Brar #include <linux/module.h> 19b7d861d9SBoojin Kim #include <linux/string.h> 20b7d861d9SBoojin Kim #include <linux/delay.h> 21b7d861d9SBoojin Kim #include <linux/interrupt.h> 22b7d861d9SBoojin Kim #include <linux/dma-mapping.h> 23b3040e40SJassi Brar #include <linux/dmaengine.h> 24b3040e40SJassi Brar #include <linux/amba/bus.h> 25b3040e40SJassi Brar #include <linux/amba/pl330.h> 261b9bb715SBoojin Kim #include <linux/scatterlist.h> 2793ed5544SThomas Abraham #include <linux/of.h> 28a80258f9SPadmavathi Venna #include <linux/of_dma.h> 29bcc7fa95SSachin Kamat #include <linux/err.h> 30b3040e40SJassi Brar 31d2ebfb33SRussell King - ARM Linux #include "dmaengine.h" 32b7d861d9SBoojin Kim #define PL330_MAX_CHAN 8 33b7d861d9SBoojin Kim #define PL330_MAX_IRQS 32 34b7d861d9SBoojin Kim #define PL330_MAX_PERI 32 35b7d861d9SBoojin Kim 36f0564c7eSLars-Peter Clausen enum pl330_cachectrl { 37f0564c7eSLars-Peter Clausen CCTRL0, /* Noncacheable and nonbufferable */ 38f0564c7eSLars-Peter Clausen CCTRL1, /* Bufferable only */ 39f0564c7eSLars-Peter Clausen CCTRL2, /* Cacheable, but do not allocate */ 40f0564c7eSLars-Peter Clausen CCTRL3, /* Cacheable and bufferable, but do not allocate */ 41f0564c7eSLars-Peter Clausen INVALID1, /* AWCACHE = 0x1000 */ 42f0564c7eSLars-Peter Clausen INVALID2, 43f0564c7eSLars-Peter Clausen CCTRL6, /* Cacheable write-through, allocate on writes only */ 44f0564c7eSLars-Peter Clausen CCTRL7, /* Cacheable write-back, allocate on writes only */ 45b7d861d9SBoojin Kim }; 46b7d861d9SBoojin Kim 47b7d861d9SBoojin Kim enum pl330_byteswap { 48b7d861d9SBoojin Kim SWAP_NO, 49b7d861d9SBoojin Kim SWAP_2, 50b7d861d9SBoojin Kim SWAP_4, 51b7d861d9SBoojin Kim SWAP_8, 52b7d861d9SBoojin Kim SWAP_16, 53b7d861d9SBoojin Kim }; 54b7d861d9SBoojin Kim 55b7d861d9SBoojin Kim /* Register and Bit field Definitions */ 56b7d861d9SBoojin Kim #define DS 0x0 57b7d861d9SBoojin Kim #define DS_ST_STOP 0x0 58b7d861d9SBoojin Kim #define DS_ST_EXEC 0x1 59b7d861d9SBoojin Kim #define DS_ST_CMISS 0x2 60b7d861d9SBoojin Kim #define DS_ST_UPDTPC 0x3 61b7d861d9SBoojin Kim #define DS_ST_WFE 0x4 62b7d861d9SBoojin Kim #define DS_ST_ATBRR 0x5 63b7d861d9SBoojin Kim #define DS_ST_QBUSY 0x6 64b7d861d9SBoojin Kim #define DS_ST_WFP 0x7 65b7d861d9SBoojin Kim #define DS_ST_KILL 0x8 66b7d861d9SBoojin Kim #define DS_ST_CMPLT 0x9 67b7d861d9SBoojin Kim #define DS_ST_FLTCMP 0xe 68b7d861d9SBoojin Kim #define DS_ST_FAULT 0xf 69b7d861d9SBoojin Kim 70b7d861d9SBoojin Kim #define DPC 0x4 71b7d861d9SBoojin Kim #define INTEN 0x20 72b7d861d9SBoojin Kim #define ES 0x24 73b7d861d9SBoojin Kim #define INTSTATUS 0x28 74b7d861d9SBoojin Kim #define INTCLR 0x2c 75b7d861d9SBoojin Kim #define FSM 0x30 76b7d861d9SBoojin Kim #define FSC 0x34 77b7d861d9SBoojin Kim #define FTM 0x38 78b7d861d9SBoojin Kim 79b7d861d9SBoojin Kim #define _FTC 0x40 80b7d861d9SBoojin Kim #define FTC(n) (_FTC + (n)*0x4) 81b7d861d9SBoojin Kim 82b7d861d9SBoojin Kim #define _CS 0x100 83b7d861d9SBoojin Kim #define CS(n) (_CS + (n)*0x8) 84b7d861d9SBoojin Kim #define CS_CNS (1 << 21) 85b7d861d9SBoojin Kim 86b7d861d9SBoojin Kim #define _CPC 0x104 87b7d861d9SBoojin Kim #define CPC(n) (_CPC + (n)*0x8) 88b7d861d9SBoojin Kim 89b7d861d9SBoojin Kim #define _SA 0x400 90b7d861d9SBoojin Kim #define SA(n) (_SA + (n)*0x20) 91b7d861d9SBoojin Kim 92b7d861d9SBoojin Kim #define _DA 0x404 93b7d861d9SBoojin Kim #define DA(n) (_DA + (n)*0x20) 94b7d861d9SBoojin Kim 95b7d861d9SBoojin Kim #define _CC 0x408 96b7d861d9SBoojin Kim #define CC(n) (_CC + (n)*0x20) 97b7d861d9SBoojin Kim 98b7d861d9SBoojin Kim #define CC_SRCINC (1 << 0) 99b7d861d9SBoojin Kim #define CC_DSTINC (1 << 14) 100b7d861d9SBoojin Kim #define CC_SRCPRI (1 << 8) 101b7d861d9SBoojin Kim #define CC_DSTPRI (1 << 22) 102b7d861d9SBoojin Kim #define CC_SRCNS (1 << 9) 103b7d861d9SBoojin Kim #define CC_DSTNS (1 << 23) 104b7d861d9SBoojin Kim #define CC_SRCIA (1 << 10) 105b7d861d9SBoojin Kim #define CC_DSTIA (1 << 24) 106b7d861d9SBoojin Kim #define CC_SRCBRSTLEN_SHFT 4 107b7d861d9SBoojin Kim #define CC_DSTBRSTLEN_SHFT 18 108b7d861d9SBoojin Kim #define CC_SRCBRSTSIZE_SHFT 1 109b7d861d9SBoojin Kim #define CC_DSTBRSTSIZE_SHFT 15 110b7d861d9SBoojin Kim #define CC_SRCCCTRL_SHFT 11 111b7d861d9SBoojin Kim #define CC_SRCCCTRL_MASK 0x7 112b7d861d9SBoojin Kim #define CC_DSTCCTRL_SHFT 25 113b7d861d9SBoojin Kim #define CC_DRCCCTRL_MASK 0x7 114b7d861d9SBoojin Kim #define CC_SWAP_SHFT 28 115b7d861d9SBoojin Kim 116b7d861d9SBoojin Kim #define _LC0 0x40c 117b7d861d9SBoojin Kim #define LC0(n) (_LC0 + (n)*0x20) 118b7d861d9SBoojin Kim 119b7d861d9SBoojin Kim #define _LC1 0x410 120b7d861d9SBoojin Kim #define LC1(n) (_LC1 + (n)*0x20) 121b7d861d9SBoojin Kim 122b7d861d9SBoojin Kim #define DBGSTATUS 0xd00 123b7d861d9SBoojin Kim #define DBG_BUSY (1 << 0) 124b7d861d9SBoojin Kim 125b7d861d9SBoojin Kim #define DBGCMD 0xd04 126b7d861d9SBoojin Kim #define DBGINST0 0xd08 127b7d861d9SBoojin Kim #define DBGINST1 0xd0c 128b7d861d9SBoojin Kim 129b7d861d9SBoojin Kim #define CR0 0xe00 130b7d861d9SBoojin Kim #define CR1 0xe04 131b7d861d9SBoojin Kim #define CR2 0xe08 132b7d861d9SBoojin Kim #define CR3 0xe0c 133b7d861d9SBoojin Kim #define CR4 0xe10 134b7d861d9SBoojin Kim #define CRD 0xe14 135b7d861d9SBoojin Kim 136b7d861d9SBoojin Kim #define PERIPH_ID 0xfe0 1373ecf51a4SBoojin Kim #define PERIPH_REV_SHIFT 20 1383ecf51a4SBoojin Kim #define PERIPH_REV_MASK 0xf 1393ecf51a4SBoojin Kim #define PERIPH_REV_R0P0 0 1403ecf51a4SBoojin Kim #define PERIPH_REV_R1P0 1 1413ecf51a4SBoojin Kim #define PERIPH_REV_R1P1 2 142b7d861d9SBoojin Kim 143b7d861d9SBoojin Kim #define CR0_PERIPH_REQ_SET (1 << 0) 144b7d861d9SBoojin Kim #define CR0_BOOT_EN_SET (1 << 1) 145b7d861d9SBoojin Kim #define CR0_BOOT_MAN_NS (1 << 2) 146b7d861d9SBoojin Kim #define CR0_NUM_CHANS_SHIFT 4 147b7d861d9SBoojin Kim #define CR0_NUM_CHANS_MASK 0x7 148b7d861d9SBoojin Kim #define CR0_NUM_PERIPH_SHIFT 12 149b7d861d9SBoojin Kim #define CR0_NUM_PERIPH_MASK 0x1f 150b7d861d9SBoojin Kim #define CR0_NUM_EVENTS_SHIFT 17 151b7d861d9SBoojin Kim #define CR0_NUM_EVENTS_MASK 0x1f 152b7d861d9SBoojin Kim 153b7d861d9SBoojin Kim #define CR1_ICACHE_LEN_SHIFT 0 154b7d861d9SBoojin Kim #define CR1_ICACHE_LEN_MASK 0x7 155b7d861d9SBoojin Kim #define CR1_NUM_ICACHELINES_SHIFT 4 156b7d861d9SBoojin Kim #define CR1_NUM_ICACHELINES_MASK 0xf 157b7d861d9SBoojin Kim 158b7d861d9SBoojin Kim #define CRD_DATA_WIDTH_SHIFT 0 159b7d861d9SBoojin Kim #define CRD_DATA_WIDTH_MASK 0x7 160b7d861d9SBoojin Kim #define CRD_WR_CAP_SHIFT 4 161b7d861d9SBoojin Kim #define CRD_WR_CAP_MASK 0x7 162b7d861d9SBoojin Kim #define CRD_WR_Q_DEP_SHIFT 8 163b7d861d9SBoojin Kim #define CRD_WR_Q_DEP_MASK 0xf 164b7d861d9SBoojin Kim #define CRD_RD_CAP_SHIFT 12 165b7d861d9SBoojin Kim #define CRD_RD_CAP_MASK 0x7 166b7d861d9SBoojin Kim #define CRD_RD_Q_DEP_SHIFT 16 167b7d861d9SBoojin Kim #define CRD_RD_Q_DEP_MASK 0xf 168b7d861d9SBoojin Kim #define CRD_DATA_BUFF_SHIFT 20 169b7d861d9SBoojin Kim #define CRD_DATA_BUFF_MASK 0x3ff 170b7d861d9SBoojin Kim 171b7d861d9SBoojin Kim #define PART 0x330 172b7d861d9SBoojin Kim #define DESIGNER 0x41 173b7d861d9SBoojin Kim #define REVISION 0x0 174b7d861d9SBoojin Kim #define INTEG_CFG 0x0 175b7d861d9SBoojin Kim #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) 176b7d861d9SBoojin Kim 177b7d861d9SBoojin Kim #define PL330_STATE_STOPPED (1 << 0) 178b7d861d9SBoojin Kim #define PL330_STATE_EXECUTING (1 << 1) 179b7d861d9SBoojin Kim #define PL330_STATE_WFE (1 << 2) 180b7d861d9SBoojin Kim #define PL330_STATE_FAULTING (1 << 3) 181b7d861d9SBoojin Kim #define PL330_STATE_COMPLETING (1 << 4) 182b7d861d9SBoojin Kim #define PL330_STATE_WFP (1 << 5) 183b7d861d9SBoojin Kim #define PL330_STATE_KILLING (1 << 6) 184b7d861d9SBoojin Kim #define PL330_STATE_FAULT_COMPLETING (1 << 7) 185b7d861d9SBoojin Kim #define PL330_STATE_CACHEMISS (1 << 8) 186b7d861d9SBoojin Kim #define PL330_STATE_UPDTPC (1 << 9) 187b7d861d9SBoojin Kim #define PL330_STATE_ATBARRIER (1 << 10) 188b7d861d9SBoojin Kim #define PL330_STATE_QUEUEBUSY (1 << 11) 189b7d861d9SBoojin Kim #define PL330_STATE_INVALID (1 << 15) 190b7d861d9SBoojin Kim 191b7d861d9SBoojin Kim #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ 192b7d861d9SBoojin Kim | PL330_STATE_WFE | PL330_STATE_FAULTING) 193b7d861d9SBoojin Kim 194b7d861d9SBoojin Kim #define CMD_DMAADDH 0x54 195b7d861d9SBoojin Kim #define CMD_DMAEND 0x00 196b7d861d9SBoojin Kim #define CMD_DMAFLUSHP 0x35 197b7d861d9SBoojin Kim #define CMD_DMAGO 0xa0 198b7d861d9SBoojin Kim #define CMD_DMALD 0x04 199b7d861d9SBoojin Kim #define CMD_DMALDP 0x25 200b7d861d9SBoojin Kim #define CMD_DMALP 0x20 201b7d861d9SBoojin Kim #define CMD_DMALPEND 0x28 202b7d861d9SBoojin Kim #define CMD_DMAKILL 0x01 203b7d861d9SBoojin Kim #define CMD_DMAMOV 0xbc 204b7d861d9SBoojin Kim #define CMD_DMANOP 0x18 205b7d861d9SBoojin Kim #define CMD_DMARMB 0x12 206b7d861d9SBoojin Kim #define CMD_DMASEV 0x34 207b7d861d9SBoojin Kim #define CMD_DMAST 0x08 208b7d861d9SBoojin Kim #define CMD_DMASTP 0x29 209b7d861d9SBoojin Kim #define CMD_DMASTZ 0x0c 210b7d861d9SBoojin Kim #define CMD_DMAWFE 0x36 211b7d861d9SBoojin Kim #define CMD_DMAWFP 0x30 212b7d861d9SBoojin Kim #define CMD_DMAWMB 0x13 213b7d861d9SBoojin Kim 214b7d861d9SBoojin Kim #define SZ_DMAADDH 3 215b7d861d9SBoojin Kim #define SZ_DMAEND 1 216b7d861d9SBoojin Kim #define SZ_DMAFLUSHP 2 217b7d861d9SBoojin Kim #define SZ_DMALD 1 218b7d861d9SBoojin Kim #define SZ_DMALDP 2 219b7d861d9SBoojin Kim #define SZ_DMALP 2 220b7d861d9SBoojin Kim #define SZ_DMALPEND 2 221b7d861d9SBoojin Kim #define SZ_DMAKILL 1 222b7d861d9SBoojin Kim #define SZ_DMAMOV 6 223b7d861d9SBoojin Kim #define SZ_DMANOP 1 224b7d861d9SBoojin Kim #define SZ_DMARMB 1 225b7d861d9SBoojin Kim #define SZ_DMASEV 2 226b7d861d9SBoojin Kim #define SZ_DMAST 1 227b7d861d9SBoojin Kim #define SZ_DMASTP 2 228b7d861d9SBoojin Kim #define SZ_DMASTZ 1 229b7d861d9SBoojin Kim #define SZ_DMAWFE 2 230b7d861d9SBoojin Kim #define SZ_DMAWFP 2 231b7d861d9SBoojin Kim #define SZ_DMAWMB 1 232b7d861d9SBoojin Kim #define SZ_DMAGO 6 233b7d861d9SBoojin Kim 234b7d861d9SBoojin Kim #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) 235b7d861d9SBoojin Kim #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) 236b7d861d9SBoojin Kim 237b7d861d9SBoojin Kim #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) 238b7d861d9SBoojin Kim #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) 239b7d861d9SBoojin Kim 240b7d861d9SBoojin Kim /* 241b7d861d9SBoojin Kim * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req 242b7d861d9SBoojin Kim * at 1byte/burst for P<->M and M<->M respectively. 243b7d861d9SBoojin Kim * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req 244b7d861d9SBoojin Kim * should be enough for P<->M and M<->M respectively. 245b7d861d9SBoojin Kim */ 246b7d861d9SBoojin Kim #define MCODE_BUFF_PER_REQ 256 247b7d861d9SBoojin Kim 248b7d861d9SBoojin Kim /* If the _pl330_req is available to the client */ 249b7d861d9SBoojin Kim #define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND) 250b7d861d9SBoojin Kim 251b7d861d9SBoojin Kim /* Use this _only_ to wait on transient states */ 252b7d861d9SBoojin Kim #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); 253b7d861d9SBoojin Kim 254b7d861d9SBoojin Kim #ifdef PL330_DEBUG_MCGEN 255b7d861d9SBoojin Kim static unsigned cmd_line; 256b7d861d9SBoojin Kim #define PL330_DBGCMD_DUMP(off, x...) do { \ 257b7d861d9SBoojin Kim printk("%x:", cmd_line); \ 258b7d861d9SBoojin Kim printk(x); \ 259b7d861d9SBoojin Kim cmd_line += off; \ 260b7d861d9SBoojin Kim } while (0) 261b7d861d9SBoojin Kim #define PL330_DBGMC_START(addr) (cmd_line = addr) 262b7d861d9SBoojin Kim #else 263b7d861d9SBoojin Kim #define PL330_DBGCMD_DUMP(off, x...) do {} while (0) 264b7d861d9SBoojin Kim #define PL330_DBGMC_START(addr) do {} while (0) 265b7d861d9SBoojin Kim #endif 266b7d861d9SBoojin Kim 267b7d861d9SBoojin Kim /* The number of default descriptors */ 268d2ebfb33SRussell King - ARM Linux 269b3040e40SJassi Brar #define NR_DEFAULT_DESC 16 270b3040e40SJassi Brar 271b7d861d9SBoojin Kim /* Populated by the PL330 core driver for DMA API driver's info */ 272b7d861d9SBoojin Kim struct pl330_config { 273b7d861d9SBoojin Kim u32 periph_id; 274b7d861d9SBoojin Kim #define DMAC_MODE_NS (1 << 0) 275b7d861d9SBoojin Kim unsigned int mode; 276b7d861d9SBoojin Kim unsigned int data_bus_width:10; /* In number of bits */ 277b7d861d9SBoojin Kim unsigned int data_buf_dep:10; 278b7d861d9SBoojin Kim unsigned int num_chan:4; 279b7d861d9SBoojin Kim unsigned int num_peri:6; 280b7d861d9SBoojin Kim u32 peri_ns; 281b7d861d9SBoojin Kim unsigned int num_events:6; 282b7d861d9SBoojin Kim u32 irq_ns; 283b7d861d9SBoojin Kim }; 284b7d861d9SBoojin Kim 285b7d861d9SBoojin Kim /** 286b7d861d9SBoojin Kim * Request Configuration. 287b7d861d9SBoojin Kim * The PL330 core does not modify this and uses the last 288b7d861d9SBoojin Kim * working configuration if the request doesn't provide any. 289b7d861d9SBoojin Kim * 290b7d861d9SBoojin Kim * The Client may want to provide this info only for the 291b7d861d9SBoojin Kim * first request and a request with new settings. 292b7d861d9SBoojin Kim */ 293b7d861d9SBoojin Kim struct pl330_reqcfg { 294b7d861d9SBoojin Kim /* Address Incrementing */ 295b7d861d9SBoojin Kim unsigned dst_inc:1; 296b7d861d9SBoojin Kim unsigned src_inc:1; 297b7d861d9SBoojin Kim 298b7d861d9SBoojin Kim /* 299b7d861d9SBoojin Kim * For now, the SRC & DST protection levels 300b7d861d9SBoojin Kim * and burst size/length are assumed same. 301b7d861d9SBoojin Kim */ 302b7d861d9SBoojin Kim bool nonsecure; 303b7d861d9SBoojin Kim bool privileged; 304b7d861d9SBoojin Kim bool insnaccess; 305b7d861d9SBoojin Kim unsigned brst_len:5; 306b7d861d9SBoojin Kim unsigned brst_size:3; /* in power of 2 */ 307b7d861d9SBoojin Kim 308f0564c7eSLars-Peter Clausen enum pl330_cachectrl dcctl; 309f0564c7eSLars-Peter Clausen enum pl330_cachectrl scctl; 310b7d861d9SBoojin Kim enum pl330_byteswap swap; 3113ecf51a4SBoojin Kim struct pl330_config *pcfg; 312b7d861d9SBoojin Kim }; 313b7d861d9SBoojin Kim 314b7d861d9SBoojin Kim /* 315b7d861d9SBoojin Kim * One cycle of DMAC operation. 316b7d861d9SBoojin Kim * There may be more than one xfer in a request. 317b7d861d9SBoojin Kim */ 318b7d861d9SBoojin Kim struct pl330_xfer { 319b7d861d9SBoojin Kim u32 src_addr; 320b7d861d9SBoojin Kim u32 dst_addr; 321b7d861d9SBoojin Kim /* Size to xfer */ 322b7d861d9SBoojin Kim u32 bytes; 323b7d861d9SBoojin Kim }; 324b7d861d9SBoojin Kim 325b7d861d9SBoojin Kim /* The xfer callbacks are made with one of these arguments. */ 326b7d861d9SBoojin Kim enum pl330_op_err { 327b7d861d9SBoojin Kim /* The all xfers in the request were success. */ 328b7d861d9SBoojin Kim PL330_ERR_NONE, 329b7d861d9SBoojin Kim /* If req aborted due to global error. */ 330b7d861d9SBoojin Kim PL330_ERR_ABORT, 331b7d861d9SBoojin Kim /* If req failed due to problem with Channel. */ 332b7d861d9SBoojin Kim PL330_ERR_FAIL, 333b7d861d9SBoojin Kim }; 334b7d861d9SBoojin Kim 335b7d861d9SBoojin Kim /* A request defining Scatter-Gather List ending with NULL xfer. */ 336b7d861d9SBoojin Kim struct pl330_req { 337585a9d0bSLars-Peter Clausen enum dma_transfer_direction rqtype; 338b7d861d9SBoojin Kim /* Index of peripheral for the xfer. */ 339b7d861d9SBoojin Kim unsigned peri:5; 340b7d861d9SBoojin Kim /* If NULL, req will be done at last set parameters. */ 341b7d861d9SBoojin Kim struct pl330_reqcfg *cfg; 342b7d861d9SBoojin Kim /* Pointer to first xfer in the request. */ 343b7d861d9SBoojin Kim struct pl330_xfer *x; 344fdec53d5SJavi Merino /* Hook to attach to DMAC's list of reqs with due callback */ 345fdec53d5SJavi Merino struct list_head rqd; 346b7d861d9SBoojin Kim }; 347b7d861d9SBoojin Kim 348b7d861d9SBoojin Kim enum pl330_chan_op { 349b7d861d9SBoojin Kim /* Start the channel */ 350b7d861d9SBoojin Kim PL330_OP_START, 351b7d861d9SBoojin Kim /* Abort the active xfer */ 352b7d861d9SBoojin Kim PL330_OP_ABORT, 353b7d861d9SBoojin Kim /* Stop xfer and flush queue */ 354b7d861d9SBoojin Kim PL330_OP_FLUSH, 355b7d861d9SBoojin Kim }; 356b7d861d9SBoojin Kim 357b7d861d9SBoojin Kim struct _xfer_spec { 358b7d861d9SBoojin Kim u32 ccr; 359b7d861d9SBoojin Kim struct pl330_req *r; 360b7d861d9SBoojin Kim struct pl330_xfer *x; 361b7d861d9SBoojin Kim }; 362b7d861d9SBoojin Kim 363b7d861d9SBoojin Kim enum dmamov_dst { 364b7d861d9SBoojin Kim SAR = 0, 365b7d861d9SBoojin Kim CCR, 366b7d861d9SBoojin Kim DAR, 367b7d861d9SBoojin Kim }; 368b7d861d9SBoojin Kim 369b7d861d9SBoojin Kim enum pl330_dst { 370b7d861d9SBoojin Kim SRC = 0, 371b7d861d9SBoojin Kim DST, 372b7d861d9SBoojin Kim }; 373b7d861d9SBoojin Kim 374b7d861d9SBoojin Kim enum pl330_cond { 375b7d861d9SBoojin Kim SINGLE, 376b7d861d9SBoojin Kim BURST, 377b7d861d9SBoojin Kim ALWAYS, 378b7d861d9SBoojin Kim }; 379b7d861d9SBoojin Kim 380b7d861d9SBoojin Kim struct _pl330_req { 381b7d861d9SBoojin Kim u32 mc_bus; 382b7d861d9SBoojin Kim void *mc_cpu; 383b7d861d9SBoojin Kim struct pl330_req *r; 384b7d861d9SBoojin Kim }; 385b7d861d9SBoojin Kim 386b7d861d9SBoojin Kim /* ToBeDone for tasklet */ 387b7d861d9SBoojin Kim struct _pl330_tbd { 388b7d861d9SBoojin Kim bool reset_dmac; 389b7d861d9SBoojin Kim bool reset_mngr; 390b7d861d9SBoojin Kim u8 reset_chan; 391b7d861d9SBoojin Kim }; 392b7d861d9SBoojin Kim 393b7d861d9SBoojin Kim /* A DMAC Thread */ 394b7d861d9SBoojin Kim struct pl330_thread { 395b7d861d9SBoojin Kim u8 id; 396b7d861d9SBoojin Kim int ev; 397b7d861d9SBoojin Kim /* If the channel is not yet acquired by any client */ 398b7d861d9SBoojin Kim bool free; 399b7d861d9SBoojin Kim /* Parent DMAC */ 400b7d861d9SBoojin Kim struct pl330_dmac *dmac; 401b7d861d9SBoojin Kim /* Only two at a time */ 402b7d861d9SBoojin Kim struct _pl330_req req[2]; 403b7d861d9SBoojin Kim /* Index of the last enqueued request */ 404b7d861d9SBoojin Kim unsigned lstenq; 405b7d861d9SBoojin Kim /* Index of the last submitted request or -1 if the DMA is stopped */ 406b7d861d9SBoojin Kim int req_running; 407b7d861d9SBoojin Kim }; 408b7d861d9SBoojin Kim 409b7d861d9SBoojin Kim enum pl330_dmac_state { 410b7d861d9SBoojin Kim UNINIT, 411b7d861d9SBoojin Kim INIT, 412b7d861d9SBoojin Kim DYING, 413b7d861d9SBoojin Kim }; 414b7d861d9SBoojin Kim 415b3040e40SJassi Brar enum desc_status { 416b3040e40SJassi Brar /* In the DMAC pool */ 417b3040e40SJassi Brar FREE, 418b3040e40SJassi Brar /* 419d73111c6SMasanari Iida * Allocated to some channel during prep_xxx 420b3040e40SJassi Brar * Also may be sitting on the work_list. 421b3040e40SJassi Brar */ 422b3040e40SJassi Brar PREP, 423b3040e40SJassi Brar /* 424b3040e40SJassi Brar * Sitting on the work_list and already submitted 425b3040e40SJassi Brar * to the PL330 core. Not more than two descriptors 426b3040e40SJassi Brar * of a channel can be BUSY at any time. 427b3040e40SJassi Brar */ 428b3040e40SJassi Brar BUSY, 429b3040e40SJassi Brar /* 430b3040e40SJassi Brar * Sitting on the channel work_list but xfer done 431b3040e40SJassi Brar * by PL330 core 432b3040e40SJassi Brar */ 433b3040e40SJassi Brar DONE, 434b3040e40SJassi Brar }; 435b3040e40SJassi Brar 436b3040e40SJassi Brar struct dma_pl330_chan { 437b3040e40SJassi Brar /* Schedule desc completion */ 438b3040e40SJassi Brar struct tasklet_struct task; 439b3040e40SJassi Brar 440b3040e40SJassi Brar /* DMA-Engine Channel */ 441b3040e40SJassi Brar struct dma_chan chan; 442b3040e40SJassi Brar 44304abf5daSLars-Peter Clausen /* List of submitted descriptors */ 44404abf5daSLars-Peter Clausen struct list_head submitted_list; 44504abf5daSLars-Peter Clausen /* List of issued descriptors */ 446b3040e40SJassi Brar struct list_head work_list; 44739ff8613SLars-Peter Clausen /* List of completed descriptors */ 44839ff8613SLars-Peter Clausen struct list_head completed_list; 449b3040e40SJassi Brar 450b3040e40SJassi Brar /* Pointer to the DMAC that manages this channel, 451b3040e40SJassi Brar * NULL if the channel is available to be acquired. 452b3040e40SJassi Brar * As the parent, this DMAC also provides descriptors 453b3040e40SJassi Brar * to the channel. 454b3040e40SJassi Brar */ 455f6f2421cSLars-Peter Clausen struct pl330_dmac *dmac; 456b3040e40SJassi Brar 457b3040e40SJassi Brar /* To protect channel manipulation */ 458b3040e40SJassi Brar spinlock_t lock; 459b3040e40SJassi Brar 46065ad6060SLars-Peter Clausen /* 46165ad6060SLars-Peter Clausen * Hardware channel thread of PL330 DMAC. NULL if the channel is 46265ad6060SLars-Peter Clausen * available. 463b3040e40SJassi Brar */ 46465ad6060SLars-Peter Clausen struct pl330_thread *thread; 4651b9bb715SBoojin Kim 4661b9bb715SBoojin Kim /* For D-to-M and M-to-D channels */ 4671b9bb715SBoojin Kim int burst_sz; /* the peripheral fifo width */ 4681d0c1d60SBoojin Kim int burst_len; /* the number of burst */ 4691b9bb715SBoojin Kim dma_addr_t fifo_addr; 47042bc9cf4SBoojin Kim 47142bc9cf4SBoojin Kim /* for cyclic capability */ 47242bc9cf4SBoojin Kim bool cyclic; 473b3040e40SJassi Brar }; 474b3040e40SJassi Brar 475f6f2421cSLars-Peter Clausen struct pl330_dmac { 476b3040e40SJassi Brar /* DMA-Engine Device */ 477b3040e40SJassi Brar struct dma_device ddma; 478b3040e40SJassi Brar 479b714b84eSLars-Peter Clausen /* Holds info about sg limitations */ 480b714b84eSLars-Peter Clausen struct device_dma_parameters dma_parms; 481b714b84eSLars-Peter Clausen 482b3040e40SJassi Brar /* Pool of descriptors available for the DMAC's channels */ 483b3040e40SJassi Brar struct list_head desc_pool; 484b3040e40SJassi Brar /* To protect desc_pool manipulation */ 485b3040e40SJassi Brar spinlock_t pool_lock; 486b3040e40SJassi Brar 487f6f2421cSLars-Peter Clausen /* Size of MicroCode buffers for each channel. */ 488f6f2421cSLars-Peter Clausen unsigned mcbufsz; 489f6f2421cSLars-Peter Clausen /* ioremap'ed address of PL330 registers. */ 490f6f2421cSLars-Peter Clausen void __iomem *base; 491f6f2421cSLars-Peter Clausen /* Populated by the PL330 core driver during pl330_add */ 492f6f2421cSLars-Peter Clausen struct pl330_config pcfg; 493f6f2421cSLars-Peter Clausen 494f6f2421cSLars-Peter Clausen spinlock_t lock; 495f6f2421cSLars-Peter Clausen /* Maximum possible events/irqs */ 496f6f2421cSLars-Peter Clausen int events[32]; 497f6f2421cSLars-Peter Clausen /* BUS address of MicroCode buffer */ 498f6f2421cSLars-Peter Clausen dma_addr_t mcode_bus; 499f6f2421cSLars-Peter Clausen /* CPU address of MicroCode buffer */ 500f6f2421cSLars-Peter Clausen void *mcode_cpu; 501f6f2421cSLars-Peter Clausen /* List of all Channel threads */ 502f6f2421cSLars-Peter Clausen struct pl330_thread *channels; 503f6f2421cSLars-Peter Clausen /* Pointer to the MANAGER thread */ 504f6f2421cSLars-Peter Clausen struct pl330_thread *manager; 505f6f2421cSLars-Peter Clausen /* To handle bad news in interrupt */ 506f6f2421cSLars-Peter Clausen struct tasklet_struct tasks; 507f6f2421cSLars-Peter Clausen struct _pl330_tbd dmac_tbd; 508f6f2421cSLars-Peter Clausen /* State of DMAC operation */ 509f6f2421cSLars-Peter Clausen enum pl330_dmac_state state; 510f6f2421cSLars-Peter Clausen /* Holds list of reqs with due callbacks */ 511f6f2421cSLars-Peter Clausen struct list_head req_done; 512f6f2421cSLars-Peter Clausen 513b3040e40SJassi Brar /* Peripheral channels connected to this DMAC */ 51470cbb163SLars-Peter Clausen unsigned int num_peripherals; 5154e0e6109SRob Herring struct dma_pl330_chan *peripherals; /* keep at end */ 516b3040e40SJassi Brar }; 517b3040e40SJassi Brar 518b3040e40SJassi Brar struct dma_pl330_desc { 519b3040e40SJassi Brar /* To attach to a queue as child */ 520b3040e40SJassi Brar struct list_head node; 521b3040e40SJassi Brar 522b3040e40SJassi Brar /* Descriptor for the DMA Engine API */ 523b3040e40SJassi Brar struct dma_async_tx_descriptor txd; 524b3040e40SJassi Brar 525b3040e40SJassi Brar /* Xfer for PL330 core */ 526b3040e40SJassi Brar struct pl330_xfer px; 527b3040e40SJassi Brar 528b3040e40SJassi Brar struct pl330_reqcfg rqcfg; 529b3040e40SJassi Brar struct pl330_req req; 530b3040e40SJassi Brar 531b3040e40SJassi Brar enum desc_status status; 532b3040e40SJassi Brar 533b3040e40SJassi Brar /* The channel which currently holds this desc */ 534b3040e40SJassi Brar struct dma_pl330_chan *pchan; 535b3040e40SJassi Brar }; 536b3040e40SJassi Brar 537b7d861d9SBoojin Kim static inline bool _queue_empty(struct pl330_thread *thrd) 538b7d861d9SBoojin Kim { 539b7d861d9SBoojin Kim return (IS_FREE(&thrd->req[0]) && IS_FREE(&thrd->req[1])) 540b7d861d9SBoojin Kim ? true : false; 541b7d861d9SBoojin Kim } 542b7d861d9SBoojin Kim 543b7d861d9SBoojin Kim static inline bool _queue_full(struct pl330_thread *thrd) 544b7d861d9SBoojin Kim { 545b7d861d9SBoojin Kim return (IS_FREE(&thrd->req[0]) || IS_FREE(&thrd->req[1])) 546b7d861d9SBoojin Kim ? false : true; 547b7d861d9SBoojin Kim } 548b7d861d9SBoojin Kim 549b7d861d9SBoojin Kim static inline bool is_manager(struct pl330_thread *thrd) 550b7d861d9SBoojin Kim { 551fbbcd9beSLars-Peter Clausen return thrd->dmac->manager == thrd; 552b7d861d9SBoojin Kim } 553b7d861d9SBoojin Kim 554b7d861d9SBoojin Kim /* If manager of the thread is in Non-Secure mode */ 555b7d861d9SBoojin Kim static inline bool _manager_ns(struct pl330_thread *thrd) 556b7d861d9SBoojin Kim { 557f6f2421cSLars-Peter Clausen return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false; 558b7d861d9SBoojin Kim } 559b7d861d9SBoojin Kim 5603ecf51a4SBoojin Kim static inline u32 get_revision(u32 periph_id) 5613ecf51a4SBoojin Kim { 5623ecf51a4SBoojin Kim return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; 5633ecf51a4SBoojin Kim } 5643ecf51a4SBoojin Kim 565b7d861d9SBoojin Kim static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[], 566b7d861d9SBoojin Kim enum pl330_dst da, u16 val) 567b7d861d9SBoojin Kim { 568b7d861d9SBoojin Kim if (dry_run) 569b7d861d9SBoojin Kim return SZ_DMAADDH; 570b7d861d9SBoojin Kim 571b7d861d9SBoojin Kim buf[0] = CMD_DMAADDH; 572b7d861d9SBoojin Kim buf[0] |= (da << 1); 573b7d861d9SBoojin Kim *((u16 *)&buf[1]) = val; 574b7d861d9SBoojin Kim 575b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n", 576b7d861d9SBoojin Kim da == 1 ? "DA" : "SA", val); 577b7d861d9SBoojin Kim 578b7d861d9SBoojin Kim return SZ_DMAADDH; 579b7d861d9SBoojin Kim } 580b7d861d9SBoojin Kim 581b7d861d9SBoojin Kim static inline u32 _emit_END(unsigned dry_run, u8 buf[]) 582b7d861d9SBoojin Kim { 583b7d861d9SBoojin Kim if (dry_run) 584b7d861d9SBoojin Kim return SZ_DMAEND; 585b7d861d9SBoojin Kim 586b7d861d9SBoojin Kim buf[0] = CMD_DMAEND; 587b7d861d9SBoojin Kim 588b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); 589b7d861d9SBoojin Kim 590b7d861d9SBoojin Kim return SZ_DMAEND; 591b7d861d9SBoojin Kim } 592b7d861d9SBoojin Kim 593b7d861d9SBoojin Kim static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) 594b7d861d9SBoojin Kim { 595b7d861d9SBoojin Kim if (dry_run) 596b7d861d9SBoojin Kim return SZ_DMAFLUSHP; 597b7d861d9SBoojin Kim 598b7d861d9SBoojin Kim buf[0] = CMD_DMAFLUSHP; 599b7d861d9SBoojin Kim 600b7d861d9SBoojin Kim peri &= 0x1f; 601b7d861d9SBoojin Kim peri <<= 3; 602b7d861d9SBoojin Kim buf[1] = peri; 603b7d861d9SBoojin Kim 604b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); 605b7d861d9SBoojin Kim 606b7d861d9SBoojin Kim return SZ_DMAFLUSHP; 607b7d861d9SBoojin Kim } 608b7d861d9SBoojin Kim 609b7d861d9SBoojin Kim static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) 610b7d861d9SBoojin Kim { 611b7d861d9SBoojin Kim if (dry_run) 612b7d861d9SBoojin Kim return SZ_DMALD; 613b7d861d9SBoojin Kim 614b7d861d9SBoojin Kim buf[0] = CMD_DMALD; 615b7d861d9SBoojin Kim 616b7d861d9SBoojin Kim if (cond == SINGLE) 617b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 618b7d861d9SBoojin Kim else if (cond == BURST) 619b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (1 << 0); 620b7d861d9SBoojin Kim 621b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", 622b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); 623b7d861d9SBoojin Kim 624b7d861d9SBoojin Kim return SZ_DMALD; 625b7d861d9SBoojin Kim } 626b7d861d9SBoojin Kim 627b7d861d9SBoojin Kim static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], 628b7d861d9SBoojin Kim enum pl330_cond cond, u8 peri) 629b7d861d9SBoojin Kim { 630b7d861d9SBoojin Kim if (dry_run) 631b7d861d9SBoojin Kim return SZ_DMALDP; 632b7d861d9SBoojin Kim 633b7d861d9SBoojin Kim buf[0] = CMD_DMALDP; 634b7d861d9SBoojin Kim 635b7d861d9SBoojin Kim if (cond == BURST) 636b7d861d9SBoojin Kim buf[0] |= (1 << 1); 637b7d861d9SBoojin Kim 638b7d861d9SBoojin Kim peri &= 0x1f; 639b7d861d9SBoojin Kim peri <<= 3; 640b7d861d9SBoojin Kim buf[1] = peri; 641b7d861d9SBoojin Kim 642b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", 643b7d861d9SBoojin Kim cond == SINGLE ? 'S' : 'B', peri >> 3); 644b7d861d9SBoojin Kim 645b7d861d9SBoojin Kim return SZ_DMALDP; 646b7d861d9SBoojin Kim } 647b7d861d9SBoojin Kim 648b7d861d9SBoojin Kim static inline u32 _emit_LP(unsigned dry_run, u8 buf[], 649b7d861d9SBoojin Kim unsigned loop, u8 cnt) 650b7d861d9SBoojin Kim { 651b7d861d9SBoojin Kim if (dry_run) 652b7d861d9SBoojin Kim return SZ_DMALP; 653b7d861d9SBoojin Kim 654b7d861d9SBoojin Kim buf[0] = CMD_DMALP; 655b7d861d9SBoojin Kim 656b7d861d9SBoojin Kim if (loop) 657b7d861d9SBoojin Kim buf[0] |= (1 << 1); 658b7d861d9SBoojin Kim 659b7d861d9SBoojin Kim cnt--; /* DMAC increments by 1 internally */ 660b7d861d9SBoojin Kim buf[1] = cnt; 661b7d861d9SBoojin Kim 662b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); 663b7d861d9SBoojin Kim 664b7d861d9SBoojin Kim return SZ_DMALP; 665b7d861d9SBoojin Kim } 666b7d861d9SBoojin Kim 667b7d861d9SBoojin Kim struct _arg_LPEND { 668b7d861d9SBoojin Kim enum pl330_cond cond; 669b7d861d9SBoojin Kim bool forever; 670b7d861d9SBoojin Kim unsigned loop; 671b7d861d9SBoojin Kim u8 bjump; 672b7d861d9SBoojin Kim }; 673b7d861d9SBoojin Kim 674b7d861d9SBoojin Kim static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], 675b7d861d9SBoojin Kim const struct _arg_LPEND *arg) 676b7d861d9SBoojin Kim { 677b7d861d9SBoojin Kim enum pl330_cond cond = arg->cond; 678b7d861d9SBoojin Kim bool forever = arg->forever; 679b7d861d9SBoojin Kim unsigned loop = arg->loop; 680b7d861d9SBoojin Kim u8 bjump = arg->bjump; 681b7d861d9SBoojin Kim 682b7d861d9SBoojin Kim if (dry_run) 683b7d861d9SBoojin Kim return SZ_DMALPEND; 684b7d861d9SBoojin Kim 685b7d861d9SBoojin Kim buf[0] = CMD_DMALPEND; 686b7d861d9SBoojin Kim 687b7d861d9SBoojin Kim if (loop) 688b7d861d9SBoojin Kim buf[0] |= (1 << 2); 689b7d861d9SBoojin Kim 690b7d861d9SBoojin Kim if (!forever) 691b7d861d9SBoojin Kim buf[0] |= (1 << 4); 692b7d861d9SBoojin Kim 693b7d861d9SBoojin Kim if (cond == SINGLE) 694b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 695b7d861d9SBoojin Kim else if (cond == BURST) 696b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (1 << 0); 697b7d861d9SBoojin Kim 698b7d861d9SBoojin Kim buf[1] = bjump; 699b7d861d9SBoojin Kim 700b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", 701b7d861d9SBoojin Kim forever ? "FE" : "END", 702b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), 703b7d861d9SBoojin Kim loop ? '1' : '0', 704b7d861d9SBoojin Kim bjump); 705b7d861d9SBoojin Kim 706b7d861d9SBoojin Kim return SZ_DMALPEND; 707b7d861d9SBoojin Kim } 708b7d861d9SBoojin Kim 709b7d861d9SBoojin Kim static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) 710b7d861d9SBoojin Kim { 711b7d861d9SBoojin Kim if (dry_run) 712b7d861d9SBoojin Kim return SZ_DMAKILL; 713b7d861d9SBoojin Kim 714b7d861d9SBoojin Kim buf[0] = CMD_DMAKILL; 715b7d861d9SBoojin Kim 716b7d861d9SBoojin Kim return SZ_DMAKILL; 717b7d861d9SBoojin Kim } 718b7d861d9SBoojin Kim 719b7d861d9SBoojin Kim static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], 720b7d861d9SBoojin Kim enum dmamov_dst dst, u32 val) 721b7d861d9SBoojin Kim { 722b7d861d9SBoojin Kim if (dry_run) 723b7d861d9SBoojin Kim return SZ_DMAMOV; 724b7d861d9SBoojin Kim 725b7d861d9SBoojin Kim buf[0] = CMD_DMAMOV; 726b7d861d9SBoojin Kim buf[1] = dst; 727b7d861d9SBoojin Kim *((u32 *)&buf[2]) = val; 728b7d861d9SBoojin Kim 729b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", 730b7d861d9SBoojin Kim dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); 731b7d861d9SBoojin Kim 732b7d861d9SBoojin Kim return SZ_DMAMOV; 733b7d861d9SBoojin Kim } 734b7d861d9SBoojin Kim 735b7d861d9SBoojin Kim static inline u32 _emit_NOP(unsigned dry_run, u8 buf[]) 736b7d861d9SBoojin Kim { 737b7d861d9SBoojin Kim if (dry_run) 738b7d861d9SBoojin Kim return SZ_DMANOP; 739b7d861d9SBoojin Kim 740b7d861d9SBoojin Kim buf[0] = CMD_DMANOP; 741b7d861d9SBoojin Kim 742b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n"); 743b7d861d9SBoojin Kim 744b7d861d9SBoojin Kim return SZ_DMANOP; 745b7d861d9SBoojin Kim } 746b7d861d9SBoojin Kim 747b7d861d9SBoojin Kim static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) 748b7d861d9SBoojin Kim { 749b7d861d9SBoojin Kim if (dry_run) 750b7d861d9SBoojin Kim return SZ_DMARMB; 751b7d861d9SBoojin Kim 752b7d861d9SBoojin Kim buf[0] = CMD_DMARMB; 753b7d861d9SBoojin Kim 754b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); 755b7d861d9SBoojin Kim 756b7d861d9SBoojin Kim return SZ_DMARMB; 757b7d861d9SBoojin Kim } 758b7d861d9SBoojin Kim 759b7d861d9SBoojin Kim static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) 760b7d861d9SBoojin Kim { 761b7d861d9SBoojin Kim if (dry_run) 762b7d861d9SBoojin Kim return SZ_DMASEV; 763b7d861d9SBoojin Kim 764b7d861d9SBoojin Kim buf[0] = CMD_DMASEV; 765b7d861d9SBoojin Kim 766b7d861d9SBoojin Kim ev &= 0x1f; 767b7d861d9SBoojin Kim ev <<= 3; 768b7d861d9SBoojin Kim buf[1] = ev; 769b7d861d9SBoojin Kim 770b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); 771b7d861d9SBoojin Kim 772b7d861d9SBoojin Kim return SZ_DMASEV; 773b7d861d9SBoojin Kim } 774b7d861d9SBoojin Kim 775b7d861d9SBoojin Kim static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) 776b7d861d9SBoojin Kim { 777b7d861d9SBoojin Kim if (dry_run) 778b7d861d9SBoojin Kim return SZ_DMAST; 779b7d861d9SBoojin Kim 780b7d861d9SBoojin Kim buf[0] = CMD_DMAST; 781b7d861d9SBoojin Kim 782b7d861d9SBoojin Kim if (cond == SINGLE) 783b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 784b7d861d9SBoojin Kim else if (cond == BURST) 785b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (1 << 0); 786b7d861d9SBoojin Kim 787b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", 788b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); 789b7d861d9SBoojin Kim 790b7d861d9SBoojin Kim return SZ_DMAST; 791b7d861d9SBoojin Kim } 792b7d861d9SBoojin Kim 793b7d861d9SBoojin Kim static inline u32 _emit_STP(unsigned dry_run, u8 buf[], 794b7d861d9SBoojin Kim enum pl330_cond cond, u8 peri) 795b7d861d9SBoojin Kim { 796b7d861d9SBoojin Kim if (dry_run) 797b7d861d9SBoojin Kim return SZ_DMASTP; 798b7d861d9SBoojin Kim 799b7d861d9SBoojin Kim buf[0] = CMD_DMASTP; 800b7d861d9SBoojin Kim 801b7d861d9SBoojin Kim if (cond == BURST) 802b7d861d9SBoojin Kim buf[0] |= (1 << 1); 803b7d861d9SBoojin Kim 804b7d861d9SBoojin Kim peri &= 0x1f; 805b7d861d9SBoojin Kim peri <<= 3; 806b7d861d9SBoojin Kim buf[1] = peri; 807b7d861d9SBoojin Kim 808b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", 809b7d861d9SBoojin Kim cond == SINGLE ? 'S' : 'B', peri >> 3); 810b7d861d9SBoojin Kim 811b7d861d9SBoojin Kim return SZ_DMASTP; 812b7d861d9SBoojin Kim } 813b7d861d9SBoojin Kim 814b7d861d9SBoojin Kim static inline u32 _emit_STZ(unsigned dry_run, u8 buf[]) 815b7d861d9SBoojin Kim { 816b7d861d9SBoojin Kim if (dry_run) 817b7d861d9SBoojin Kim return SZ_DMASTZ; 818b7d861d9SBoojin Kim 819b7d861d9SBoojin Kim buf[0] = CMD_DMASTZ; 820b7d861d9SBoojin Kim 821b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n"); 822b7d861d9SBoojin Kim 823b7d861d9SBoojin Kim return SZ_DMASTZ; 824b7d861d9SBoojin Kim } 825b7d861d9SBoojin Kim 826b7d861d9SBoojin Kim static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, 827b7d861d9SBoojin Kim unsigned invalidate) 828b7d861d9SBoojin Kim { 829b7d861d9SBoojin Kim if (dry_run) 830b7d861d9SBoojin Kim return SZ_DMAWFE; 831b7d861d9SBoojin Kim 832b7d861d9SBoojin Kim buf[0] = CMD_DMAWFE; 833b7d861d9SBoojin Kim 834b7d861d9SBoojin Kim ev &= 0x1f; 835b7d861d9SBoojin Kim ev <<= 3; 836b7d861d9SBoojin Kim buf[1] = ev; 837b7d861d9SBoojin Kim 838b7d861d9SBoojin Kim if (invalidate) 839b7d861d9SBoojin Kim buf[1] |= (1 << 1); 840b7d861d9SBoojin Kim 841b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n", 842b7d861d9SBoojin Kim ev >> 3, invalidate ? ", I" : ""); 843b7d861d9SBoojin Kim 844b7d861d9SBoojin Kim return SZ_DMAWFE; 845b7d861d9SBoojin Kim } 846b7d861d9SBoojin Kim 847b7d861d9SBoojin Kim static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], 848b7d861d9SBoojin Kim enum pl330_cond cond, u8 peri) 849b7d861d9SBoojin Kim { 850b7d861d9SBoojin Kim if (dry_run) 851b7d861d9SBoojin Kim return SZ_DMAWFP; 852b7d861d9SBoojin Kim 853b7d861d9SBoojin Kim buf[0] = CMD_DMAWFP; 854b7d861d9SBoojin Kim 855b7d861d9SBoojin Kim if (cond == SINGLE) 856b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (0 << 0); 857b7d861d9SBoojin Kim else if (cond == BURST) 858b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (0 << 0); 859b7d861d9SBoojin Kim else 860b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 861b7d861d9SBoojin Kim 862b7d861d9SBoojin Kim peri &= 0x1f; 863b7d861d9SBoojin Kim peri <<= 3; 864b7d861d9SBoojin Kim buf[1] = peri; 865b7d861d9SBoojin Kim 866b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", 867b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); 868b7d861d9SBoojin Kim 869b7d861d9SBoojin Kim return SZ_DMAWFP; 870b7d861d9SBoojin Kim } 871b7d861d9SBoojin Kim 872b7d861d9SBoojin Kim static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) 873b7d861d9SBoojin Kim { 874b7d861d9SBoojin Kim if (dry_run) 875b7d861d9SBoojin Kim return SZ_DMAWMB; 876b7d861d9SBoojin Kim 877b7d861d9SBoojin Kim buf[0] = CMD_DMAWMB; 878b7d861d9SBoojin Kim 879b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); 880b7d861d9SBoojin Kim 881b7d861d9SBoojin Kim return SZ_DMAWMB; 882b7d861d9SBoojin Kim } 883b7d861d9SBoojin Kim 884b7d861d9SBoojin Kim struct _arg_GO { 885b7d861d9SBoojin Kim u8 chan; 886b7d861d9SBoojin Kim u32 addr; 887b7d861d9SBoojin Kim unsigned ns; 888b7d861d9SBoojin Kim }; 889b7d861d9SBoojin Kim 890b7d861d9SBoojin Kim static inline u32 _emit_GO(unsigned dry_run, u8 buf[], 891b7d861d9SBoojin Kim const struct _arg_GO *arg) 892b7d861d9SBoojin Kim { 893b7d861d9SBoojin Kim u8 chan = arg->chan; 894b7d861d9SBoojin Kim u32 addr = arg->addr; 895b7d861d9SBoojin Kim unsigned ns = arg->ns; 896b7d861d9SBoojin Kim 897b7d861d9SBoojin Kim if (dry_run) 898b7d861d9SBoojin Kim return SZ_DMAGO; 899b7d861d9SBoojin Kim 900b7d861d9SBoojin Kim buf[0] = CMD_DMAGO; 901b7d861d9SBoojin Kim buf[0] |= (ns << 1); 902b7d861d9SBoojin Kim 903b7d861d9SBoojin Kim buf[1] = chan & 0x7; 904b7d861d9SBoojin Kim 905b7d861d9SBoojin Kim *((u32 *)&buf[2]) = addr; 906b7d861d9SBoojin Kim 907b7d861d9SBoojin Kim return SZ_DMAGO; 908b7d861d9SBoojin Kim } 909b7d861d9SBoojin Kim 910b7d861d9SBoojin Kim #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 911b7d861d9SBoojin Kim 912b7d861d9SBoojin Kim /* Returns Time-Out */ 913b7d861d9SBoojin Kim static bool _until_dmac_idle(struct pl330_thread *thrd) 914b7d861d9SBoojin Kim { 915f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 916b7d861d9SBoojin Kim unsigned long loops = msecs_to_loops(5); 917b7d861d9SBoojin Kim 918b7d861d9SBoojin Kim do { 919b7d861d9SBoojin Kim /* Until Manager is Idle */ 920b7d861d9SBoojin Kim if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) 921b7d861d9SBoojin Kim break; 922b7d861d9SBoojin Kim 923b7d861d9SBoojin Kim cpu_relax(); 924b7d861d9SBoojin Kim } while (--loops); 925b7d861d9SBoojin Kim 926b7d861d9SBoojin Kim if (!loops) 927b7d861d9SBoojin Kim return true; 928b7d861d9SBoojin Kim 929b7d861d9SBoojin Kim return false; 930b7d861d9SBoojin Kim } 931b7d861d9SBoojin Kim 932b7d861d9SBoojin Kim static inline void _execute_DBGINSN(struct pl330_thread *thrd, 933b7d861d9SBoojin Kim u8 insn[], bool as_manager) 934b7d861d9SBoojin Kim { 935f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 936b7d861d9SBoojin Kim u32 val; 937b7d861d9SBoojin Kim 938b7d861d9SBoojin Kim val = (insn[0] << 16) | (insn[1] << 24); 939b7d861d9SBoojin Kim if (!as_manager) { 940b7d861d9SBoojin Kim val |= (1 << 0); 941b7d861d9SBoojin Kim val |= (thrd->id << 8); /* Channel Number */ 942b7d861d9SBoojin Kim } 943b7d861d9SBoojin Kim writel(val, regs + DBGINST0); 944b7d861d9SBoojin Kim 945b7d861d9SBoojin Kim val = *((u32 *)&insn[2]); 946b7d861d9SBoojin Kim writel(val, regs + DBGINST1); 947b7d861d9SBoojin Kim 948b7d861d9SBoojin Kim /* If timed out due to halted state-machine */ 949b7d861d9SBoojin Kim if (_until_dmac_idle(thrd)) { 950f6f2421cSLars-Peter Clausen dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n"); 951b7d861d9SBoojin Kim return; 952b7d861d9SBoojin Kim } 953b7d861d9SBoojin Kim 954b7d861d9SBoojin Kim /* Get going */ 955b7d861d9SBoojin Kim writel(0, regs + DBGCMD); 956b7d861d9SBoojin Kim } 957b7d861d9SBoojin Kim 958b7d861d9SBoojin Kim /* 959b7d861d9SBoojin Kim * Mark a _pl330_req as free. 960b7d861d9SBoojin Kim * We do it by writing DMAEND as the first instruction 961b7d861d9SBoojin Kim * because no valid request is going to have DMAEND as 962b7d861d9SBoojin Kim * its first instruction to execute. 963b7d861d9SBoojin Kim */ 964b7d861d9SBoojin Kim static void mark_free(struct pl330_thread *thrd, int idx) 965b7d861d9SBoojin Kim { 966b7d861d9SBoojin Kim struct _pl330_req *req = &thrd->req[idx]; 967b7d861d9SBoojin Kim 968b7d861d9SBoojin Kim _emit_END(0, req->mc_cpu); 969b7d861d9SBoojin Kim 970b7d861d9SBoojin Kim thrd->req_running = -1; 971b7d861d9SBoojin Kim } 972b7d861d9SBoojin Kim 973b7d861d9SBoojin Kim static inline u32 _state(struct pl330_thread *thrd) 974b7d861d9SBoojin Kim { 975f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 976b7d861d9SBoojin Kim u32 val; 977b7d861d9SBoojin Kim 978b7d861d9SBoojin Kim if (is_manager(thrd)) 979b7d861d9SBoojin Kim val = readl(regs + DS) & 0xf; 980b7d861d9SBoojin Kim else 981b7d861d9SBoojin Kim val = readl(regs + CS(thrd->id)) & 0xf; 982b7d861d9SBoojin Kim 983b7d861d9SBoojin Kim switch (val) { 984b7d861d9SBoojin Kim case DS_ST_STOP: 985b7d861d9SBoojin Kim return PL330_STATE_STOPPED; 986b7d861d9SBoojin Kim case DS_ST_EXEC: 987b7d861d9SBoojin Kim return PL330_STATE_EXECUTING; 988b7d861d9SBoojin Kim case DS_ST_CMISS: 989b7d861d9SBoojin Kim return PL330_STATE_CACHEMISS; 990b7d861d9SBoojin Kim case DS_ST_UPDTPC: 991b7d861d9SBoojin Kim return PL330_STATE_UPDTPC; 992b7d861d9SBoojin Kim case DS_ST_WFE: 993b7d861d9SBoojin Kim return PL330_STATE_WFE; 994b7d861d9SBoojin Kim case DS_ST_FAULT: 995b7d861d9SBoojin Kim return PL330_STATE_FAULTING; 996b7d861d9SBoojin Kim case DS_ST_ATBRR: 997b7d861d9SBoojin Kim if (is_manager(thrd)) 998b7d861d9SBoojin Kim return PL330_STATE_INVALID; 999b7d861d9SBoojin Kim else 1000b7d861d9SBoojin Kim return PL330_STATE_ATBARRIER; 1001b7d861d9SBoojin Kim case DS_ST_QBUSY: 1002b7d861d9SBoojin Kim if (is_manager(thrd)) 1003b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1004b7d861d9SBoojin Kim else 1005b7d861d9SBoojin Kim return PL330_STATE_QUEUEBUSY; 1006b7d861d9SBoojin Kim case DS_ST_WFP: 1007b7d861d9SBoojin Kim if (is_manager(thrd)) 1008b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1009b7d861d9SBoojin Kim else 1010b7d861d9SBoojin Kim return PL330_STATE_WFP; 1011b7d861d9SBoojin Kim case DS_ST_KILL: 1012b7d861d9SBoojin Kim if (is_manager(thrd)) 1013b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1014b7d861d9SBoojin Kim else 1015b7d861d9SBoojin Kim return PL330_STATE_KILLING; 1016b7d861d9SBoojin Kim case DS_ST_CMPLT: 1017b7d861d9SBoojin Kim if (is_manager(thrd)) 1018b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1019b7d861d9SBoojin Kim else 1020b7d861d9SBoojin Kim return PL330_STATE_COMPLETING; 1021b7d861d9SBoojin Kim case DS_ST_FLTCMP: 1022b7d861d9SBoojin Kim if (is_manager(thrd)) 1023b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1024b7d861d9SBoojin Kim else 1025b7d861d9SBoojin Kim return PL330_STATE_FAULT_COMPLETING; 1026b7d861d9SBoojin Kim default: 1027b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1028b7d861d9SBoojin Kim } 1029b7d861d9SBoojin Kim } 1030b7d861d9SBoojin Kim 1031b7d861d9SBoojin Kim static void _stop(struct pl330_thread *thrd) 1032b7d861d9SBoojin Kim { 1033f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 1034b7d861d9SBoojin Kim u8 insn[6] = {0, 0, 0, 0, 0, 0}; 1035b7d861d9SBoojin Kim 1036b7d861d9SBoojin Kim if (_state(thrd) == PL330_STATE_FAULT_COMPLETING) 1037b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); 1038b7d861d9SBoojin Kim 1039b7d861d9SBoojin Kim /* Return if nothing needs to be done */ 1040b7d861d9SBoojin Kim if (_state(thrd) == PL330_STATE_COMPLETING 1041b7d861d9SBoojin Kim || _state(thrd) == PL330_STATE_KILLING 1042b7d861d9SBoojin Kim || _state(thrd) == PL330_STATE_STOPPED) 1043b7d861d9SBoojin Kim return; 1044b7d861d9SBoojin Kim 1045b7d861d9SBoojin Kim _emit_KILL(0, insn); 1046b7d861d9SBoojin Kim 1047b7d861d9SBoojin Kim /* Stop generating interrupts for SEV */ 1048b7d861d9SBoojin Kim writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN); 1049b7d861d9SBoojin Kim 1050b7d861d9SBoojin Kim _execute_DBGINSN(thrd, insn, is_manager(thrd)); 1051b7d861d9SBoojin Kim } 1052b7d861d9SBoojin Kim 1053b7d861d9SBoojin Kim /* Start doing req 'idx' of thread 'thrd' */ 1054b7d861d9SBoojin Kim static bool _trigger(struct pl330_thread *thrd) 1055b7d861d9SBoojin Kim { 1056f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 1057b7d861d9SBoojin Kim struct _pl330_req *req; 1058b7d861d9SBoojin Kim struct pl330_req *r; 1059b7d861d9SBoojin Kim struct _arg_GO go; 1060b7d861d9SBoojin Kim unsigned ns; 1061b7d861d9SBoojin Kim u8 insn[6] = {0, 0, 0, 0, 0, 0}; 1062b7d861d9SBoojin Kim int idx; 1063b7d861d9SBoojin Kim 1064b7d861d9SBoojin Kim /* Return if already ACTIVE */ 1065b7d861d9SBoojin Kim if (_state(thrd) != PL330_STATE_STOPPED) 1066b7d861d9SBoojin Kim return true; 1067b7d861d9SBoojin Kim 1068b7d861d9SBoojin Kim idx = 1 - thrd->lstenq; 1069b7d861d9SBoojin Kim if (!IS_FREE(&thrd->req[idx])) 1070b7d861d9SBoojin Kim req = &thrd->req[idx]; 1071b7d861d9SBoojin Kim else { 1072b7d861d9SBoojin Kim idx = thrd->lstenq; 1073b7d861d9SBoojin Kim if (!IS_FREE(&thrd->req[idx])) 1074b7d861d9SBoojin Kim req = &thrd->req[idx]; 1075b7d861d9SBoojin Kim else 1076b7d861d9SBoojin Kim req = NULL; 1077b7d861d9SBoojin Kim } 1078b7d861d9SBoojin Kim 1079b7d861d9SBoojin Kim /* Return if no request */ 1080b7d861d9SBoojin Kim if (!req || !req->r) 1081b7d861d9SBoojin Kim return true; 1082b7d861d9SBoojin Kim 1083b7d861d9SBoojin Kim r = req->r; 1084b7d861d9SBoojin Kim 1085b7d861d9SBoojin Kim if (r->cfg) 1086b7d861d9SBoojin Kim ns = r->cfg->nonsecure ? 1 : 0; 1087b7d861d9SBoojin Kim else if (readl(regs + CS(thrd->id)) & CS_CNS) 1088b7d861d9SBoojin Kim ns = 1; 1089b7d861d9SBoojin Kim else 1090b7d861d9SBoojin Kim ns = 0; 1091b7d861d9SBoojin Kim 1092b7d861d9SBoojin Kim /* See 'Abort Sources' point-4 at Page 2-25 */ 1093b7d861d9SBoojin Kim if (_manager_ns(thrd) && !ns) 1094f6f2421cSLars-Peter Clausen dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n", 1095b7d861d9SBoojin Kim __func__, __LINE__); 1096b7d861d9SBoojin Kim 1097b7d861d9SBoojin Kim go.chan = thrd->id; 1098b7d861d9SBoojin Kim go.addr = req->mc_bus; 1099b7d861d9SBoojin Kim go.ns = ns; 1100b7d861d9SBoojin Kim _emit_GO(0, insn, &go); 1101b7d861d9SBoojin Kim 1102b7d861d9SBoojin Kim /* Set to generate interrupts for SEV */ 1103b7d861d9SBoojin Kim writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); 1104b7d861d9SBoojin Kim 1105b7d861d9SBoojin Kim /* Only manager can execute GO */ 1106b7d861d9SBoojin Kim _execute_DBGINSN(thrd, insn, true); 1107b7d861d9SBoojin Kim 1108b7d861d9SBoojin Kim thrd->req_running = idx; 1109b7d861d9SBoojin Kim 1110b7d861d9SBoojin Kim return true; 1111b7d861d9SBoojin Kim } 1112b7d861d9SBoojin Kim 1113b7d861d9SBoojin Kim static bool _start(struct pl330_thread *thrd) 1114b7d861d9SBoojin Kim { 1115b7d861d9SBoojin Kim switch (_state(thrd)) { 1116b7d861d9SBoojin Kim case PL330_STATE_FAULT_COMPLETING: 1117b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); 1118b7d861d9SBoojin Kim 1119b7d861d9SBoojin Kim if (_state(thrd) == PL330_STATE_KILLING) 1120b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_STOPPED) 1121b7d861d9SBoojin Kim 1122b7d861d9SBoojin Kim case PL330_STATE_FAULTING: 1123b7d861d9SBoojin Kim _stop(thrd); 1124b7d861d9SBoojin Kim 1125b7d861d9SBoojin Kim case PL330_STATE_KILLING: 1126b7d861d9SBoojin Kim case PL330_STATE_COMPLETING: 1127b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_STOPPED) 1128b7d861d9SBoojin Kim 1129b7d861d9SBoojin Kim case PL330_STATE_STOPPED: 1130b7d861d9SBoojin Kim return _trigger(thrd); 1131b7d861d9SBoojin Kim 1132b7d861d9SBoojin Kim case PL330_STATE_WFP: 1133b7d861d9SBoojin Kim case PL330_STATE_QUEUEBUSY: 1134b7d861d9SBoojin Kim case PL330_STATE_ATBARRIER: 1135b7d861d9SBoojin Kim case PL330_STATE_UPDTPC: 1136b7d861d9SBoojin Kim case PL330_STATE_CACHEMISS: 1137b7d861d9SBoojin Kim case PL330_STATE_EXECUTING: 1138b7d861d9SBoojin Kim return true; 1139b7d861d9SBoojin Kim 1140b7d861d9SBoojin Kim case PL330_STATE_WFE: /* For RESUME, nothing yet */ 1141b7d861d9SBoojin Kim default: 1142b7d861d9SBoojin Kim return false; 1143b7d861d9SBoojin Kim } 1144b7d861d9SBoojin Kim } 1145b7d861d9SBoojin Kim 1146b7d861d9SBoojin Kim static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], 1147b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1148b7d861d9SBoojin Kim { 1149b7d861d9SBoojin Kim int off = 0; 11503ecf51a4SBoojin Kim struct pl330_config *pcfg = pxs->r->cfg->pcfg; 1151b7d861d9SBoojin Kim 11523ecf51a4SBoojin Kim /* check lock-up free version */ 11533ecf51a4SBoojin Kim if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { 11543ecf51a4SBoojin Kim while (cyc--) { 11553ecf51a4SBoojin Kim off += _emit_LD(dry_run, &buf[off], ALWAYS); 11563ecf51a4SBoojin Kim off += _emit_ST(dry_run, &buf[off], ALWAYS); 11573ecf51a4SBoojin Kim } 11583ecf51a4SBoojin Kim } else { 1159b7d861d9SBoojin Kim while (cyc--) { 1160b7d861d9SBoojin Kim off += _emit_LD(dry_run, &buf[off], ALWAYS); 1161b7d861d9SBoojin Kim off += _emit_RMB(dry_run, &buf[off]); 1162b7d861d9SBoojin Kim off += _emit_ST(dry_run, &buf[off], ALWAYS); 1163b7d861d9SBoojin Kim off += _emit_WMB(dry_run, &buf[off]); 1164b7d861d9SBoojin Kim } 11653ecf51a4SBoojin Kim } 1166b7d861d9SBoojin Kim 1167b7d861d9SBoojin Kim return off; 1168b7d861d9SBoojin Kim } 1169b7d861d9SBoojin Kim 1170b7d861d9SBoojin Kim static inline int _ldst_devtomem(unsigned dry_run, u8 buf[], 1171b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1172b7d861d9SBoojin Kim { 1173b7d861d9SBoojin Kim int off = 0; 1174b7d861d9SBoojin Kim 1175b7d861d9SBoojin Kim while (cyc--) { 1176b7d861d9SBoojin Kim off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri); 1177b7d861d9SBoojin Kim off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->r->peri); 1178b7d861d9SBoojin Kim off += _emit_ST(dry_run, &buf[off], ALWAYS); 1179b7d861d9SBoojin Kim off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri); 1180b7d861d9SBoojin Kim } 1181b7d861d9SBoojin Kim 1182b7d861d9SBoojin Kim return off; 1183b7d861d9SBoojin Kim } 1184b7d861d9SBoojin Kim 1185b7d861d9SBoojin Kim static inline int _ldst_memtodev(unsigned dry_run, u8 buf[], 1186b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1187b7d861d9SBoojin Kim { 1188b7d861d9SBoojin Kim int off = 0; 1189b7d861d9SBoojin Kim 1190b7d861d9SBoojin Kim while (cyc--) { 1191b7d861d9SBoojin Kim off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri); 1192b7d861d9SBoojin Kim off += _emit_LD(dry_run, &buf[off], ALWAYS); 1193b7d861d9SBoojin Kim off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->r->peri); 1194b7d861d9SBoojin Kim off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri); 1195b7d861d9SBoojin Kim } 1196b7d861d9SBoojin Kim 1197b7d861d9SBoojin Kim return off; 1198b7d861d9SBoojin Kim } 1199b7d861d9SBoojin Kim 1200b7d861d9SBoojin Kim static int _bursts(unsigned dry_run, u8 buf[], 1201b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1202b7d861d9SBoojin Kim { 1203b7d861d9SBoojin Kim int off = 0; 1204b7d861d9SBoojin Kim 1205b7d861d9SBoojin Kim switch (pxs->r->rqtype) { 1206585a9d0bSLars-Peter Clausen case DMA_MEM_TO_DEV: 1207b7d861d9SBoojin Kim off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc); 1208b7d861d9SBoojin Kim break; 1209585a9d0bSLars-Peter Clausen case DMA_DEV_TO_MEM: 1210b7d861d9SBoojin Kim off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc); 1211b7d861d9SBoojin Kim break; 1212585a9d0bSLars-Peter Clausen case DMA_MEM_TO_MEM: 1213b7d861d9SBoojin Kim off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); 1214b7d861d9SBoojin Kim break; 1215b7d861d9SBoojin Kim default: 1216b7d861d9SBoojin Kim off += 0x40000000; /* Scare off the Client */ 1217b7d861d9SBoojin Kim break; 1218b7d861d9SBoojin Kim } 1219b7d861d9SBoojin Kim 1220b7d861d9SBoojin Kim return off; 1221b7d861d9SBoojin Kim } 1222b7d861d9SBoojin Kim 1223b7d861d9SBoojin Kim /* Returns bytes consumed and updates bursts */ 1224b7d861d9SBoojin Kim static inline int _loop(unsigned dry_run, u8 buf[], 1225b7d861d9SBoojin Kim unsigned long *bursts, const struct _xfer_spec *pxs) 1226b7d861d9SBoojin Kim { 1227b7d861d9SBoojin Kim int cyc, cycmax, szlp, szlpend, szbrst, off; 1228b7d861d9SBoojin Kim unsigned lcnt0, lcnt1, ljmp0, ljmp1; 1229b7d861d9SBoojin Kim struct _arg_LPEND lpend; 1230b7d861d9SBoojin Kim 1231b7d861d9SBoojin Kim /* Max iterations possible in DMALP is 256 */ 1232b7d861d9SBoojin Kim if (*bursts >= 256*256) { 1233b7d861d9SBoojin Kim lcnt1 = 256; 1234b7d861d9SBoojin Kim lcnt0 = 256; 1235b7d861d9SBoojin Kim cyc = *bursts / lcnt1 / lcnt0; 1236b7d861d9SBoojin Kim } else if (*bursts > 256) { 1237b7d861d9SBoojin Kim lcnt1 = 256; 1238b7d861d9SBoojin Kim lcnt0 = *bursts / lcnt1; 1239b7d861d9SBoojin Kim cyc = 1; 1240b7d861d9SBoojin Kim } else { 1241b7d861d9SBoojin Kim lcnt1 = *bursts; 1242b7d861d9SBoojin Kim lcnt0 = 0; 1243b7d861d9SBoojin Kim cyc = 1; 1244b7d861d9SBoojin Kim } 1245b7d861d9SBoojin Kim 1246b7d861d9SBoojin Kim szlp = _emit_LP(1, buf, 0, 0); 1247b7d861d9SBoojin Kim szbrst = _bursts(1, buf, pxs, 1); 1248b7d861d9SBoojin Kim 1249b7d861d9SBoojin Kim lpend.cond = ALWAYS; 1250b7d861d9SBoojin Kim lpend.forever = false; 1251b7d861d9SBoojin Kim lpend.loop = 0; 1252b7d861d9SBoojin Kim lpend.bjump = 0; 1253b7d861d9SBoojin Kim szlpend = _emit_LPEND(1, buf, &lpend); 1254b7d861d9SBoojin Kim 1255b7d861d9SBoojin Kim if (lcnt0) { 1256b7d861d9SBoojin Kim szlp *= 2; 1257b7d861d9SBoojin Kim szlpend *= 2; 1258b7d861d9SBoojin Kim } 1259b7d861d9SBoojin Kim 1260b7d861d9SBoojin Kim /* 1261b7d861d9SBoojin Kim * Max bursts that we can unroll due to limit on the 1262b7d861d9SBoojin Kim * size of backward jump that can be encoded in DMALPEND 1263b7d861d9SBoojin Kim * which is 8-bits and hence 255 1264b7d861d9SBoojin Kim */ 1265b7d861d9SBoojin Kim cycmax = (255 - (szlp + szlpend)) / szbrst; 1266b7d861d9SBoojin Kim 1267b7d861d9SBoojin Kim cyc = (cycmax < cyc) ? cycmax : cyc; 1268b7d861d9SBoojin Kim 1269b7d861d9SBoojin Kim off = 0; 1270b7d861d9SBoojin Kim 1271b7d861d9SBoojin Kim if (lcnt0) { 1272b7d861d9SBoojin Kim off += _emit_LP(dry_run, &buf[off], 0, lcnt0); 1273b7d861d9SBoojin Kim ljmp0 = off; 1274b7d861d9SBoojin Kim } 1275b7d861d9SBoojin Kim 1276b7d861d9SBoojin Kim off += _emit_LP(dry_run, &buf[off], 1, lcnt1); 1277b7d861d9SBoojin Kim ljmp1 = off; 1278b7d861d9SBoojin Kim 1279b7d861d9SBoojin Kim off += _bursts(dry_run, &buf[off], pxs, cyc); 1280b7d861d9SBoojin Kim 1281b7d861d9SBoojin Kim lpend.cond = ALWAYS; 1282b7d861d9SBoojin Kim lpend.forever = false; 1283b7d861d9SBoojin Kim lpend.loop = 1; 1284b7d861d9SBoojin Kim lpend.bjump = off - ljmp1; 1285b7d861d9SBoojin Kim off += _emit_LPEND(dry_run, &buf[off], &lpend); 1286b7d861d9SBoojin Kim 1287b7d861d9SBoojin Kim if (lcnt0) { 1288b7d861d9SBoojin Kim lpend.cond = ALWAYS; 1289b7d861d9SBoojin Kim lpend.forever = false; 1290b7d861d9SBoojin Kim lpend.loop = 0; 1291b7d861d9SBoojin Kim lpend.bjump = off - ljmp0; 1292b7d861d9SBoojin Kim off += _emit_LPEND(dry_run, &buf[off], &lpend); 1293b7d861d9SBoojin Kim } 1294b7d861d9SBoojin Kim 1295b7d861d9SBoojin Kim *bursts = lcnt1 * cyc; 1296b7d861d9SBoojin Kim if (lcnt0) 1297b7d861d9SBoojin Kim *bursts *= lcnt0; 1298b7d861d9SBoojin Kim 1299b7d861d9SBoojin Kim return off; 1300b7d861d9SBoojin Kim } 1301b7d861d9SBoojin Kim 1302b7d861d9SBoojin Kim static inline int _setup_loops(unsigned dry_run, u8 buf[], 1303b7d861d9SBoojin Kim const struct _xfer_spec *pxs) 1304b7d861d9SBoojin Kim { 1305b7d861d9SBoojin Kim struct pl330_xfer *x = pxs->x; 1306b7d861d9SBoojin Kim u32 ccr = pxs->ccr; 1307b7d861d9SBoojin Kim unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); 1308b7d861d9SBoojin Kim int off = 0; 1309b7d861d9SBoojin Kim 1310b7d861d9SBoojin Kim while (bursts) { 1311b7d861d9SBoojin Kim c = bursts; 1312b7d861d9SBoojin Kim off += _loop(dry_run, &buf[off], &c, pxs); 1313b7d861d9SBoojin Kim bursts -= c; 1314b7d861d9SBoojin Kim } 1315b7d861d9SBoojin Kim 1316b7d861d9SBoojin Kim return off; 1317b7d861d9SBoojin Kim } 1318b7d861d9SBoojin Kim 1319b7d861d9SBoojin Kim static inline int _setup_xfer(unsigned dry_run, u8 buf[], 1320b7d861d9SBoojin Kim const struct _xfer_spec *pxs) 1321b7d861d9SBoojin Kim { 1322b7d861d9SBoojin Kim struct pl330_xfer *x = pxs->x; 1323b7d861d9SBoojin Kim int off = 0; 1324b7d861d9SBoojin Kim 1325b7d861d9SBoojin Kim /* DMAMOV SAR, x->src_addr */ 1326b7d861d9SBoojin Kim off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); 1327b7d861d9SBoojin Kim /* DMAMOV DAR, x->dst_addr */ 1328b7d861d9SBoojin Kim off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr); 1329b7d861d9SBoojin Kim 1330b7d861d9SBoojin Kim /* Setup Loop(s) */ 1331b7d861d9SBoojin Kim off += _setup_loops(dry_run, &buf[off], pxs); 1332b7d861d9SBoojin Kim 1333b7d861d9SBoojin Kim return off; 1334b7d861d9SBoojin Kim } 1335b7d861d9SBoojin Kim 1336b7d861d9SBoojin Kim /* 1337b7d861d9SBoojin Kim * A req is a sequence of one or more xfer units. 1338b7d861d9SBoojin Kim * Returns the number of bytes taken to setup the MC for the req. 1339b7d861d9SBoojin Kim */ 1340b7d861d9SBoojin Kim static int _setup_req(unsigned dry_run, struct pl330_thread *thrd, 1341b7d861d9SBoojin Kim unsigned index, struct _xfer_spec *pxs) 1342b7d861d9SBoojin Kim { 1343b7d861d9SBoojin Kim struct _pl330_req *req = &thrd->req[index]; 1344b7d861d9SBoojin Kim struct pl330_xfer *x; 1345b7d861d9SBoojin Kim u8 *buf = req->mc_cpu; 1346b7d861d9SBoojin Kim int off = 0; 1347b7d861d9SBoojin Kim 1348b7d861d9SBoojin Kim PL330_DBGMC_START(req->mc_bus); 1349b7d861d9SBoojin Kim 1350b7d861d9SBoojin Kim /* DMAMOV CCR, ccr */ 1351b7d861d9SBoojin Kim off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); 1352b7d861d9SBoojin Kim 1353b7d861d9SBoojin Kim x = pxs->r->x; 1354b7d861d9SBoojin Kim /* Error if xfer length is not aligned at burst size */ 1355b7d861d9SBoojin Kim if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr))) 1356b7d861d9SBoojin Kim return -EINVAL; 1357b7d861d9SBoojin Kim 1358b7d861d9SBoojin Kim pxs->x = x; 1359b7d861d9SBoojin Kim off += _setup_xfer(dry_run, &buf[off], pxs); 1360b7d861d9SBoojin Kim 1361b7d861d9SBoojin Kim /* DMASEV peripheral/event */ 1362b7d861d9SBoojin Kim off += _emit_SEV(dry_run, &buf[off], thrd->ev); 1363b7d861d9SBoojin Kim /* DMAEND */ 1364b7d861d9SBoojin Kim off += _emit_END(dry_run, &buf[off]); 1365b7d861d9SBoojin Kim 1366b7d861d9SBoojin Kim return off; 1367b7d861d9SBoojin Kim } 1368b7d861d9SBoojin Kim 1369b7d861d9SBoojin Kim static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) 1370b7d861d9SBoojin Kim { 1371b7d861d9SBoojin Kim u32 ccr = 0; 1372b7d861d9SBoojin Kim 1373b7d861d9SBoojin Kim if (rqc->src_inc) 1374b7d861d9SBoojin Kim ccr |= CC_SRCINC; 1375b7d861d9SBoojin Kim 1376b7d861d9SBoojin Kim if (rqc->dst_inc) 1377b7d861d9SBoojin Kim ccr |= CC_DSTINC; 1378b7d861d9SBoojin Kim 1379b7d861d9SBoojin Kim /* We set same protection levels for Src and DST for now */ 1380b7d861d9SBoojin Kim if (rqc->privileged) 1381b7d861d9SBoojin Kim ccr |= CC_SRCPRI | CC_DSTPRI; 1382b7d861d9SBoojin Kim if (rqc->nonsecure) 1383b7d861d9SBoojin Kim ccr |= CC_SRCNS | CC_DSTNS; 1384b7d861d9SBoojin Kim if (rqc->insnaccess) 1385b7d861d9SBoojin Kim ccr |= CC_SRCIA | CC_DSTIA; 1386b7d861d9SBoojin Kim 1387b7d861d9SBoojin Kim ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); 1388b7d861d9SBoojin Kim ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); 1389b7d861d9SBoojin Kim 1390b7d861d9SBoojin Kim ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); 1391b7d861d9SBoojin Kim ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); 1392b7d861d9SBoojin Kim 1393b7d861d9SBoojin Kim ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); 1394b7d861d9SBoojin Kim ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); 1395b7d861d9SBoojin Kim 1396b7d861d9SBoojin Kim ccr |= (rqc->swap << CC_SWAP_SHFT); 1397b7d861d9SBoojin Kim 1398b7d861d9SBoojin Kim return ccr; 1399b7d861d9SBoojin Kim } 1400b7d861d9SBoojin Kim 1401b7d861d9SBoojin Kim /* 1402b7d861d9SBoojin Kim * Submit a list of xfers after which the client wants notification. 1403b7d861d9SBoojin Kim * Client is not notified after each xfer unit, just once after all 1404b7d861d9SBoojin Kim * xfer units are done or some error occurs. 1405b7d861d9SBoojin Kim */ 140665ad6060SLars-Peter Clausen static int pl330_submit_req(struct pl330_thread *thrd, struct pl330_req *r) 1407b7d861d9SBoojin Kim { 1408f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = thrd->dmac; 1409b7d861d9SBoojin Kim struct _xfer_spec xs; 1410b7d861d9SBoojin Kim unsigned long flags; 1411b7d861d9SBoojin Kim void __iomem *regs; 1412b7d861d9SBoojin Kim unsigned idx; 1413b7d861d9SBoojin Kim u32 ccr; 1414b7d861d9SBoojin Kim int ret = 0; 1415b7d861d9SBoojin Kim 1416b7d861d9SBoojin Kim /* No Req or Unacquired Channel or DMAC */ 1417b7d861d9SBoojin Kim if (!r || !thrd || thrd->free) 1418b7d861d9SBoojin Kim return -EINVAL; 1419b7d861d9SBoojin Kim 1420f6f2421cSLars-Peter Clausen regs = thrd->dmac->base; 1421b7d861d9SBoojin Kim 1422b7d861d9SBoojin Kim if (pl330->state == DYING 1423b7d861d9SBoojin Kim || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { 1424f6f2421cSLars-Peter Clausen dev_info(thrd->dmac->ddma.dev, "%s:%d\n", 1425b7d861d9SBoojin Kim __func__, __LINE__); 1426b7d861d9SBoojin Kim return -EAGAIN; 1427b7d861d9SBoojin Kim } 1428b7d861d9SBoojin Kim 1429b7d861d9SBoojin Kim /* If request for non-existing peripheral */ 1430f6f2421cSLars-Peter Clausen if (r->rqtype != DMA_MEM_TO_MEM && r->peri >= pl330->pcfg.num_peri) { 1431f6f2421cSLars-Peter Clausen dev_info(thrd->dmac->ddma.dev, 1432b7d861d9SBoojin Kim "%s:%d Invalid peripheral(%u)!\n", 1433b7d861d9SBoojin Kim __func__, __LINE__, r->peri); 1434b7d861d9SBoojin Kim return -EINVAL; 1435b7d861d9SBoojin Kim } 1436b7d861d9SBoojin Kim 1437b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1438b7d861d9SBoojin Kim 1439b7d861d9SBoojin Kim if (_queue_full(thrd)) { 1440b7d861d9SBoojin Kim ret = -EAGAIN; 1441b7d861d9SBoojin Kim goto xfer_exit; 1442b7d861d9SBoojin Kim } 1443b7d861d9SBoojin Kim 14442e2c682bSSachin Kamat 14452e2c682bSSachin Kamat /* Use last settings, if not provided */ 14462e2c682bSSachin Kamat if (r->cfg) { 1447b7d861d9SBoojin Kim /* Prefer Secure Channel */ 1448b7d861d9SBoojin Kim if (!_manager_ns(thrd)) 1449b7d861d9SBoojin Kim r->cfg->nonsecure = 0; 1450b7d861d9SBoojin Kim else 1451b7d861d9SBoojin Kim r->cfg->nonsecure = 1; 1452b7d861d9SBoojin Kim 1453b7d861d9SBoojin Kim ccr = _prepare_ccr(r->cfg); 14542e2c682bSSachin Kamat } else { 1455b7d861d9SBoojin Kim ccr = readl(regs + CC(thrd->id)); 14562e2c682bSSachin Kamat } 1457b7d861d9SBoojin Kim 1458b7d861d9SBoojin Kim idx = IS_FREE(&thrd->req[0]) ? 0 : 1; 1459b7d861d9SBoojin Kim 1460b7d861d9SBoojin Kim xs.ccr = ccr; 1461b7d861d9SBoojin Kim xs.r = r; 1462b7d861d9SBoojin Kim 1463b7d861d9SBoojin Kim /* First dry run to check if req is acceptable */ 1464b7d861d9SBoojin Kim ret = _setup_req(1, thrd, idx, &xs); 1465b7d861d9SBoojin Kim if (ret < 0) 1466b7d861d9SBoojin Kim goto xfer_exit; 1467b7d861d9SBoojin Kim 1468f6f2421cSLars-Peter Clausen if (ret > pl330->mcbufsz / 2) { 1469f6f2421cSLars-Peter Clausen dev_info(pl330->ddma.dev, "%s:%d Trying increasing mcbufsz\n", 1470b7d861d9SBoojin Kim __func__, __LINE__); 1471b7d861d9SBoojin Kim ret = -ENOMEM; 1472b7d861d9SBoojin Kim goto xfer_exit; 1473b7d861d9SBoojin Kim } 1474b7d861d9SBoojin Kim 1475b7d861d9SBoojin Kim /* Hook the request */ 1476b7d861d9SBoojin Kim thrd->lstenq = idx; 1477b7d861d9SBoojin Kim thrd->req[idx].r = r; 1478be025329SLars-Peter Clausen _setup_req(0, thrd, idx, &xs); 1479b7d861d9SBoojin Kim 1480b7d861d9SBoojin Kim ret = 0; 1481b7d861d9SBoojin Kim 1482b7d861d9SBoojin Kim xfer_exit: 1483b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1484b7d861d9SBoojin Kim 1485b7d861d9SBoojin Kim return ret; 1486b7d861d9SBoojin Kim } 1487b7d861d9SBoojin Kim 14886079d38cSLars-Peter Clausen static void dma_pl330_rqcb(struct pl330_req *req, enum pl330_op_err err) 14896079d38cSLars-Peter Clausen { 14906079d38cSLars-Peter Clausen struct dma_pl330_desc *desc = container_of(req, struct dma_pl330_desc, req); 14916079d38cSLars-Peter Clausen struct dma_pl330_chan *pch = desc->pchan; 14926079d38cSLars-Peter Clausen unsigned long flags; 14936079d38cSLars-Peter Clausen 14946079d38cSLars-Peter Clausen /* If desc aborted */ 14956079d38cSLars-Peter Clausen if (!pch) 14966079d38cSLars-Peter Clausen return; 14976079d38cSLars-Peter Clausen 14986079d38cSLars-Peter Clausen spin_lock_irqsave(&pch->lock, flags); 14996079d38cSLars-Peter Clausen 15006079d38cSLars-Peter Clausen desc->status = DONE; 15016079d38cSLars-Peter Clausen 15026079d38cSLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 15036079d38cSLars-Peter Clausen 15046079d38cSLars-Peter Clausen tasklet_schedule(&pch->task); 15056079d38cSLars-Peter Clausen } 15066079d38cSLars-Peter Clausen 1507b7d861d9SBoojin Kim static void pl330_dotask(unsigned long data) 1508b7d861d9SBoojin Kim { 1509b7d861d9SBoojin Kim struct pl330_dmac *pl330 = (struct pl330_dmac *) data; 1510b7d861d9SBoojin Kim unsigned long flags; 1511b7d861d9SBoojin Kim int i; 1512b7d861d9SBoojin Kim 1513b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1514b7d861d9SBoojin Kim 1515b7d861d9SBoojin Kim /* The DMAC itself gone nuts */ 1516b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_dmac) { 1517b7d861d9SBoojin Kim pl330->state = DYING; 1518b7d861d9SBoojin Kim /* Reset the manager too */ 1519b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = true; 1520b7d861d9SBoojin Kim /* Clear the reset flag */ 1521b7d861d9SBoojin Kim pl330->dmac_tbd.reset_dmac = false; 1522b7d861d9SBoojin Kim } 1523b7d861d9SBoojin Kim 1524b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_mngr) { 1525b7d861d9SBoojin Kim _stop(pl330->manager); 1526b7d861d9SBoojin Kim /* Reset all channels */ 1527f6f2421cSLars-Peter Clausen pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1; 1528b7d861d9SBoojin Kim /* Clear the reset flag */ 1529b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = false; 1530b7d861d9SBoojin Kim } 1531b7d861d9SBoojin Kim 1532f6f2421cSLars-Peter Clausen for (i = 0; i < pl330->pcfg.num_chan; i++) { 1533b7d861d9SBoojin Kim 1534b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_chan & (1 << i)) { 1535b7d861d9SBoojin Kim struct pl330_thread *thrd = &pl330->channels[i]; 1536f6f2421cSLars-Peter Clausen void __iomem *regs = pl330->base; 1537b7d861d9SBoojin Kim enum pl330_op_err err; 1538b7d861d9SBoojin Kim 1539b7d861d9SBoojin Kim _stop(thrd); 1540b7d861d9SBoojin Kim 1541b7d861d9SBoojin Kim if (readl(regs + FSC) & (1 << thrd->id)) 1542b7d861d9SBoojin Kim err = PL330_ERR_FAIL; 1543b7d861d9SBoojin Kim else 1544b7d861d9SBoojin Kim err = PL330_ERR_ABORT; 1545b7d861d9SBoojin Kim 1546b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 15476079d38cSLars-Peter Clausen dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].r, err); 15486079d38cSLars-Peter Clausen dma_pl330_rqcb(thrd->req[thrd->lstenq].r, err); 1549b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1550b7d861d9SBoojin Kim 1551b7d861d9SBoojin Kim thrd->req[0].r = NULL; 1552b7d861d9SBoojin Kim thrd->req[1].r = NULL; 1553b7d861d9SBoojin Kim mark_free(thrd, 0); 1554b7d861d9SBoojin Kim mark_free(thrd, 1); 1555b7d861d9SBoojin Kim 1556b7d861d9SBoojin Kim /* Clear the reset flag */ 1557b7d861d9SBoojin Kim pl330->dmac_tbd.reset_chan &= ~(1 << i); 1558b7d861d9SBoojin Kim } 1559b7d861d9SBoojin Kim } 1560b7d861d9SBoojin Kim 1561b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1562b7d861d9SBoojin Kim 1563b7d861d9SBoojin Kim return; 1564b7d861d9SBoojin Kim } 1565b7d861d9SBoojin Kim 1566b7d861d9SBoojin Kim /* Returns 1 if state was updated, 0 otherwise */ 1567f6f2421cSLars-Peter Clausen static int pl330_update(struct pl330_dmac *pl330) 1568b7d861d9SBoojin Kim { 1569fdec53d5SJavi Merino struct pl330_req *rqdone, *tmp; 1570b7d861d9SBoojin Kim unsigned long flags; 1571b7d861d9SBoojin Kim void __iomem *regs; 1572b7d861d9SBoojin Kim u32 val; 1573b7d861d9SBoojin Kim int id, ev, ret = 0; 1574b7d861d9SBoojin Kim 1575f6f2421cSLars-Peter Clausen regs = pl330->base; 1576b7d861d9SBoojin Kim 1577b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1578b7d861d9SBoojin Kim 1579b7d861d9SBoojin Kim val = readl(regs + FSM) & 0x1; 1580b7d861d9SBoojin Kim if (val) 1581b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = true; 1582b7d861d9SBoojin Kim else 1583b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = false; 1584b7d861d9SBoojin Kim 1585f6f2421cSLars-Peter Clausen val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1); 1586b7d861d9SBoojin Kim pl330->dmac_tbd.reset_chan |= val; 1587b7d861d9SBoojin Kim if (val) { 1588b7d861d9SBoojin Kim int i = 0; 1589f6f2421cSLars-Peter Clausen while (i < pl330->pcfg.num_chan) { 1590b7d861d9SBoojin Kim if (val & (1 << i)) { 1591f6f2421cSLars-Peter Clausen dev_info(pl330->ddma.dev, 1592b7d861d9SBoojin Kim "Reset Channel-%d\t CS-%x FTC-%x\n", 1593b7d861d9SBoojin Kim i, readl(regs + CS(i)), 1594b7d861d9SBoojin Kim readl(regs + FTC(i))); 1595b7d861d9SBoojin Kim _stop(&pl330->channels[i]); 1596b7d861d9SBoojin Kim } 1597b7d861d9SBoojin Kim i++; 1598b7d861d9SBoojin Kim } 1599b7d861d9SBoojin Kim } 1600b7d861d9SBoojin Kim 1601b7d861d9SBoojin Kim /* Check which event happened i.e, thread notified */ 1602b7d861d9SBoojin Kim val = readl(regs + ES); 1603f6f2421cSLars-Peter Clausen if (pl330->pcfg.num_events < 32 1604f6f2421cSLars-Peter Clausen && val & ~((1 << pl330->pcfg.num_events) - 1)) { 1605b7d861d9SBoojin Kim pl330->dmac_tbd.reset_dmac = true; 1606f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__, 1607f6f2421cSLars-Peter Clausen __LINE__); 1608b7d861d9SBoojin Kim ret = 1; 1609b7d861d9SBoojin Kim goto updt_exit; 1610b7d861d9SBoojin Kim } 1611b7d861d9SBoojin Kim 1612f6f2421cSLars-Peter Clausen for (ev = 0; ev < pl330->pcfg.num_events; ev++) { 1613b7d861d9SBoojin Kim if (val & (1 << ev)) { /* Event occurred */ 1614b7d861d9SBoojin Kim struct pl330_thread *thrd; 1615b7d861d9SBoojin Kim u32 inten = readl(regs + INTEN); 1616b7d861d9SBoojin Kim int active; 1617b7d861d9SBoojin Kim 1618b7d861d9SBoojin Kim /* Clear the event */ 1619b7d861d9SBoojin Kim if (inten & (1 << ev)) 1620b7d861d9SBoojin Kim writel(1 << ev, regs + INTCLR); 1621b7d861d9SBoojin Kim 1622b7d861d9SBoojin Kim ret = 1; 1623b7d861d9SBoojin Kim 1624b7d861d9SBoojin Kim id = pl330->events[ev]; 1625b7d861d9SBoojin Kim 1626b7d861d9SBoojin Kim thrd = &pl330->channels[id]; 1627b7d861d9SBoojin Kim 1628b7d861d9SBoojin Kim active = thrd->req_running; 1629b7d861d9SBoojin Kim if (active == -1) /* Aborted */ 1630b7d861d9SBoojin Kim continue; 1631b7d861d9SBoojin Kim 1632fdec53d5SJavi Merino /* Detach the req */ 1633fdec53d5SJavi Merino rqdone = thrd->req[active].r; 1634fdec53d5SJavi Merino thrd->req[active].r = NULL; 1635fdec53d5SJavi Merino 1636b7d861d9SBoojin Kim mark_free(thrd, active); 1637b7d861d9SBoojin Kim 1638b7d861d9SBoojin Kim /* Get going again ASAP */ 1639b7d861d9SBoojin Kim _start(thrd); 1640b7d861d9SBoojin Kim 1641b7d861d9SBoojin Kim /* For now, just make a list of callbacks to be done */ 1642b7d861d9SBoojin Kim list_add_tail(&rqdone->rqd, &pl330->req_done); 1643b7d861d9SBoojin Kim } 1644b7d861d9SBoojin Kim } 1645b7d861d9SBoojin Kim 1646b7d861d9SBoojin Kim /* Now that we are in no hurry, do the callbacks */ 1647fdec53d5SJavi Merino list_for_each_entry_safe(rqdone, tmp, &pl330->req_done, rqd) { 1648fdec53d5SJavi Merino list_del(&rqdone->rqd); 1649b7d861d9SBoojin Kim 1650b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 16516079d38cSLars-Peter Clausen dma_pl330_rqcb(rqdone, PL330_ERR_NONE); 1652b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1653b7d861d9SBoojin Kim } 1654b7d861d9SBoojin Kim 1655b7d861d9SBoojin Kim updt_exit: 1656b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1657b7d861d9SBoojin Kim 1658b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_dmac 1659b7d861d9SBoojin Kim || pl330->dmac_tbd.reset_mngr 1660b7d861d9SBoojin Kim || pl330->dmac_tbd.reset_chan) { 1661b7d861d9SBoojin Kim ret = 1; 1662b7d861d9SBoojin Kim tasklet_schedule(&pl330->tasks); 1663b7d861d9SBoojin Kim } 1664b7d861d9SBoojin Kim 1665b7d861d9SBoojin Kim return ret; 1666b7d861d9SBoojin Kim } 1667b7d861d9SBoojin Kim 166865ad6060SLars-Peter Clausen static int pl330_chan_ctrl(struct pl330_thread *thrd, enum pl330_chan_op op) 1669b7d861d9SBoojin Kim { 1670b7d861d9SBoojin Kim struct pl330_dmac *pl330; 1671b7d861d9SBoojin Kim unsigned long flags; 1672ef08e782SLinus Torvalds int ret = 0, active; 1673b7d861d9SBoojin Kim 1674b7d861d9SBoojin Kim if (!thrd || thrd->free || thrd->dmac->state == DYING) 1675b7d861d9SBoojin Kim return -EINVAL; 1676b7d861d9SBoojin Kim 1677b7d861d9SBoojin Kim pl330 = thrd->dmac; 1678ef08e782SLinus Torvalds active = thrd->req_running; 1679b7d861d9SBoojin Kim 1680b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1681b7d861d9SBoojin Kim 1682b7d861d9SBoojin Kim switch (op) { 1683b7d861d9SBoojin Kim case PL330_OP_FLUSH: 1684b7d861d9SBoojin Kim /* Make sure the channel is stopped */ 1685b7d861d9SBoojin Kim _stop(thrd); 1686b7d861d9SBoojin Kim 1687b7d861d9SBoojin Kim thrd->req[0].r = NULL; 1688b7d861d9SBoojin Kim thrd->req[1].r = NULL; 1689b7d861d9SBoojin Kim mark_free(thrd, 0); 1690b7d861d9SBoojin Kim mark_free(thrd, 1); 1691b7d861d9SBoojin Kim break; 1692b7d861d9SBoojin Kim 1693b7d861d9SBoojin Kim case PL330_OP_ABORT: 1694b7d861d9SBoojin Kim /* Make sure the channel is stopped */ 1695b7d861d9SBoojin Kim _stop(thrd); 1696b7d861d9SBoojin Kim 1697b7d861d9SBoojin Kim /* ABORT is only for the active req */ 1698b7d861d9SBoojin Kim if (active == -1) 1699b7d861d9SBoojin Kim break; 1700b7d861d9SBoojin Kim 1701b7d861d9SBoojin Kim thrd->req[active].r = NULL; 1702b7d861d9SBoojin Kim mark_free(thrd, active); 1703b7d861d9SBoojin Kim 1704b7d861d9SBoojin Kim /* Start the next */ 1705b7d861d9SBoojin Kim case PL330_OP_START: 1706b7d861d9SBoojin Kim if ((active == -1) && !_start(thrd)) 1707b7d861d9SBoojin Kim ret = -EIO; 1708b7d861d9SBoojin Kim break; 1709b7d861d9SBoojin Kim 1710b7d861d9SBoojin Kim default: 1711b7d861d9SBoojin Kim ret = -EINVAL; 1712b7d861d9SBoojin Kim } 1713b7d861d9SBoojin Kim 1714b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1715b7d861d9SBoojin Kim return ret; 1716b7d861d9SBoojin Kim } 1717b7d861d9SBoojin Kim 1718b7d861d9SBoojin Kim /* Reserve an event */ 1719b7d861d9SBoojin Kim static inline int _alloc_event(struct pl330_thread *thrd) 1720b7d861d9SBoojin Kim { 1721b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 1722b7d861d9SBoojin Kim int ev; 1723b7d861d9SBoojin Kim 1724f6f2421cSLars-Peter Clausen for (ev = 0; ev < pl330->pcfg.num_events; ev++) 1725b7d861d9SBoojin Kim if (pl330->events[ev] == -1) { 1726b7d861d9SBoojin Kim pl330->events[ev] = thrd->id; 1727b7d861d9SBoojin Kim return ev; 1728b7d861d9SBoojin Kim } 1729b7d861d9SBoojin Kim 1730b7d861d9SBoojin Kim return -1; 1731b7d861d9SBoojin Kim } 1732b7d861d9SBoojin Kim 1733f6f2421cSLars-Peter Clausen static bool _chan_ns(const struct pl330_dmac *pl330, int i) 1734b7d861d9SBoojin Kim { 1735f6f2421cSLars-Peter Clausen return pl330->pcfg.irq_ns & (1 << i); 1736b7d861d9SBoojin Kim } 1737b7d861d9SBoojin Kim 1738b7d861d9SBoojin Kim /* Upon success, returns IdentityToken for the 1739b7d861d9SBoojin Kim * allocated channel, NULL otherwise. 1740b7d861d9SBoojin Kim */ 1741f6f2421cSLars-Peter Clausen static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330) 1742b7d861d9SBoojin Kim { 1743b7d861d9SBoojin Kim struct pl330_thread *thrd = NULL; 1744b7d861d9SBoojin Kim unsigned long flags; 1745b7d861d9SBoojin Kim int chans, i; 1746b7d861d9SBoojin Kim 1747b7d861d9SBoojin Kim if (pl330->state == DYING) 1748b7d861d9SBoojin Kim return NULL; 1749b7d861d9SBoojin Kim 1750f6f2421cSLars-Peter Clausen chans = pl330->pcfg.num_chan; 1751b7d861d9SBoojin Kim 1752b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1753b7d861d9SBoojin Kim 1754b7d861d9SBoojin Kim for (i = 0; i < chans; i++) { 1755b7d861d9SBoojin Kim thrd = &pl330->channels[i]; 1756b7d861d9SBoojin Kim if ((thrd->free) && (!_manager_ns(thrd) || 1757f6f2421cSLars-Peter Clausen _chan_ns(pl330, i))) { 1758b7d861d9SBoojin Kim thrd->ev = _alloc_event(thrd); 1759b7d861d9SBoojin Kim if (thrd->ev >= 0) { 1760b7d861d9SBoojin Kim thrd->free = false; 1761b7d861d9SBoojin Kim thrd->lstenq = 1; 1762b7d861d9SBoojin Kim thrd->req[0].r = NULL; 1763b7d861d9SBoojin Kim mark_free(thrd, 0); 1764b7d861d9SBoojin Kim thrd->req[1].r = NULL; 1765b7d861d9SBoojin Kim mark_free(thrd, 1); 1766b7d861d9SBoojin Kim break; 1767b7d861d9SBoojin Kim } 1768b7d861d9SBoojin Kim } 1769b7d861d9SBoojin Kim thrd = NULL; 1770b7d861d9SBoojin Kim } 1771b7d861d9SBoojin Kim 1772b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1773b7d861d9SBoojin Kim 1774b7d861d9SBoojin Kim return thrd; 1775b7d861d9SBoojin Kim } 1776b7d861d9SBoojin Kim 1777b7d861d9SBoojin Kim /* Release an event */ 1778b7d861d9SBoojin Kim static inline void _free_event(struct pl330_thread *thrd, int ev) 1779b7d861d9SBoojin Kim { 1780b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 1781b7d861d9SBoojin Kim 1782b7d861d9SBoojin Kim /* If the event is valid and was held by the thread */ 1783f6f2421cSLars-Peter Clausen if (ev >= 0 && ev < pl330->pcfg.num_events 1784b7d861d9SBoojin Kim && pl330->events[ev] == thrd->id) 1785b7d861d9SBoojin Kim pl330->events[ev] = -1; 1786b7d861d9SBoojin Kim } 1787b7d861d9SBoojin Kim 178865ad6060SLars-Peter Clausen static void pl330_release_channel(struct pl330_thread *thrd) 1789b7d861d9SBoojin Kim { 1790b7d861d9SBoojin Kim struct pl330_dmac *pl330; 1791b7d861d9SBoojin Kim unsigned long flags; 1792b7d861d9SBoojin Kim 1793b7d861d9SBoojin Kim if (!thrd || thrd->free) 1794b7d861d9SBoojin Kim return; 1795b7d861d9SBoojin Kim 1796b7d861d9SBoojin Kim _stop(thrd); 1797b7d861d9SBoojin Kim 17986079d38cSLars-Peter Clausen dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].r, PL330_ERR_ABORT); 17996079d38cSLars-Peter Clausen dma_pl330_rqcb(thrd->req[thrd->lstenq].r, PL330_ERR_ABORT); 1800b7d861d9SBoojin Kim 1801b7d861d9SBoojin Kim pl330 = thrd->dmac; 1802b7d861d9SBoojin Kim 1803b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1804b7d861d9SBoojin Kim _free_event(thrd, thrd->ev); 1805b7d861d9SBoojin Kim thrd->free = true; 1806b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1807b7d861d9SBoojin Kim } 1808b7d861d9SBoojin Kim 1809b7d861d9SBoojin Kim /* Initialize the structure for PL330 configuration, that can be used 1810b7d861d9SBoojin Kim * by the client driver the make best use of the DMAC 1811b7d861d9SBoojin Kim */ 1812f6f2421cSLars-Peter Clausen static void read_dmac_config(struct pl330_dmac *pl330) 1813b7d861d9SBoojin Kim { 1814f6f2421cSLars-Peter Clausen void __iomem *regs = pl330->base; 1815b7d861d9SBoojin Kim u32 val; 1816b7d861d9SBoojin Kim 1817b7d861d9SBoojin Kim val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; 1818b7d861d9SBoojin Kim val &= CRD_DATA_WIDTH_MASK; 1819f6f2421cSLars-Peter Clausen pl330->pcfg.data_bus_width = 8 * (1 << val); 1820b7d861d9SBoojin Kim 1821b7d861d9SBoojin Kim val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; 1822b7d861d9SBoojin Kim val &= CRD_DATA_BUFF_MASK; 1823f6f2421cSLars-Peter Clausen pl330->pcfg.data_buf_dep = val + 1; 1824b7d861d9SBoojin Kim 1825b7d861d9SBoojin Kim val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; 1826b7d861d9SBoojin Kim val &= CR0_NUM_CHANS_MASK; 1827b7d861d9SBoojin Kim val += 1; 1828f6f2421cSLars-Peter Clausen pl330->pcfg.num_chan = val; 1829b7d861d9SBoojin Kim 1830b7d861d9SBoojin Kim val = readl(regs + CR0); 1831b7d861d9SBoojin Kim if (val & CR0_PERIPH_REQ_SET) { 1832b7d861d9SBoojin Kim val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; 1833b7d861d9SBoojin Kim val += 1; 1834f6f2421cSLars-Peter Clausen pl330->pcfg.num_peri = val; 1835f6f2421cSLars-Peter Clausen pl330->pcfg.peri_ns = readl(regs + CR4); 1836b7d861d9SBoojin Kim } else { 1837f6f2421cSLars-Peter Clausen pl330->pcfg.num_peri = 0; 1838b7d861d9SBoojin Kim } 1839b7d861d9SBoojin Kim 1840b7d861d9SBoojin Kim val = readl(regs + CR0); 1841b7d861d9SBoojin Kim if (val & CR0_BOOT_MAN_NS) 1842f6f2421cSLars-Peter Clausen pl330->pcfg.mode |= DMAC_MODE_NS; 1843b7d861d9SBoojin Kim else 1844f6f2421cSLars-Peter Clausen pl330->pcfg.mode &= ~DMAC_MODE_NS; 1845b7d861d9SBoojin Kim 1846b7d861d9SBoojin Kim val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; 1847b7d861d9SBoojin Kim val &= CR0_NUM_EVENTS_MASK; 1848b7d861d9SBoojin Kim val += 1; 1849f6f2421cSLars-Peter Clausen pl330->pcfg.num_events = val; 1850b7d861d9SBoojin Kim 1851f6f2421cSLars-Peter Clausen pl330->pcfg.irq_ns = readl(regs + CR3); 1852b7d861d9SBoojin Kim } 1853b7d861d9SBoojin Kim 1854b7d861d9SBoojin Kim static inline void _reset_thread(struct pl330_thread *thrd) 1855b7d861d9SBoojin Kim { 1856b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 1857b7d861d9SBoojin Kim 1858b7d861d9SBoojin Kim thrd->req[0].mc_cpu = pl330->mcode_cpu 1859f6f2421cSLars-Peter Clausen + (thrd->id * pl330->mcbufsz); 1860b7d861d9SBoojin Kim thrd->req[0].mc_bus = pl330->mcode_bus 1861f6f2421cSLars-Peter Clausen + (thrd->id * pl330->mcbufsz); 1862b7d861d9SBoojin Kim thrd->req[0].r = NULL; 1863b7d861d9SBoojin Kim mark_free(thrd, 0); 1864b7d861d9SBoojin Kim 1865b7d861d9SBoojin Kim thrd->req[1].mc_cpu = thrd->req[0].mc_cpu 1866f6f2421cSLars-Peter Clausen + pl330->mcbufsz / 2; 1867b7d861d9SBoojin Kim thrd->req[1].mc_bus = thrd->req[0].mc_bus 1868f6f2421cSLars-Peter Clausen + pl330->mcbufsz / 2; 1869b7d861d9SBoojin Kim thrd->req[1].r = NULL; 1870b7d861d9SBoojin Kim mark_free(thrd, 1); 1871b7d861d9SBoojin Kim } 1872b7d861d9SBoojin Kim 1873b7d861d9SBoojin Kim static int dmac_alloc_threads(struct pl330_dmac *pl330) 1874b7d861d9SBoojin Kim { 1875f6f2421cSLars-Peter Clausen int chans = pl330->pcfg.num_chan; 1876b7d861d9SBoojin Kim struct pl330_thread *thrd; 1877b7d861d9SBoojin Kim int i; 1878b7d861d9SBoojin Kim 1879b7d861d9SBoojin Kim /* Allocate 1 Manager and 'chans' Channel threads */ 1880b7d861d9SBoojin Kim pl330->channels = kzalloc((1 + chans) * sizeof(*thrd), 1881b7d861d9SBoojin Kim GFP_KERNEL); 1882b7d861d9SBoojin Kim if (!pl330->channels) 1883b7d861d9SBoojin Kim return -ENOMEM; 1884b7d861d9SBoojin Kim 1885b7d861d9SBoojin Kim /* Init Channel threads */ 1886b7d861d9SBoojin Kim for (i = 0; i < chans; i++) { 1887b7d861d9SBoojin Kim thrd = &pl330->channels[i]; 1888b7d861d9SBoojin Kim thrd->id = i; 1889b7d861d9SBoojin Kim thrd->dmac = pl330; 1890b7d861d9SBoojin Kim _reset_thread(thrd); 1891b7d861d9SBoojin Kim thrd->free = true; 1892b7d861d9SBoojin Kim } 1893b7d861d9SBoojin Kim 1894b7d861d9SBoojin Kim /* MANAGER is indexed at the end */ 1895b7d861d9SBoojin Kim thrd = &pl330->channels[chans]; 1896b7d861d9SBoojin Kim thrd->id = chans; 1897b7d861d9SBoojin Kim thrd->dmac = pl330; 1898b7d861d9SBoojin Kim thrd->free = false; 1899b7d861d9SBoojin Kim pl330->manager = thrd; 1900b7d861d9SBoojin Kim 1901b7d861d9SBoojin Kim return 0; 1902b7d861d9SBoojin Kim } 1903b7d861d9SBoojin Kim 1904b7d861d9SBoojin Kim static int dmac_alloc_resources(struct pl330_dmac *pl330) 1905b7d861d9SBoojin Kim { 1906f6f2421cSLars-Peter Clausen int chans = pl330->pcfg.num_chan; 1907b7d861d9SBoojin Kim int ret; 1908b7d861d9SBoojin Kim 1909b7d861d9SBoojin Kim /* 1910b7d861d9SBoojin Kim * Alloc MicroCode buffer for 'chans' Channel threads. 1911b7d861d9SBoojin Kim * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN) 1912b7d861d9SBoojin Kim */ 1913f6f2421cSLars-Peter Clausen pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev, 1914f6f2421cSLars-Peter Clausen chans * pl330->mcbufsz, 1915b7d861d9SBoojin Kim &pl330->mcode_bus, GFP_KERNEL); 1916b7d861d9SBoojin Kim if (!pl330->mcode_cpu) { 1917f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n", 1918b7d861d9SBoojin Kim __func__, __LINE__); 1919b7d861d9SBoojin Kim return -ENOMEM; 1920b7d861d9SBoojin Kim } 1921b7d861d9SBoojin Kim 1922b7d861d9SBoojin Kim ret = dmac_alloc_threads(pl330); 1923b7d861d9SBoojin Kim if (ret) { 1924f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n", 1925b7d861d9SBoojin Kim __func__, __LINE__); 1926f6f2421cSLars-Peter Clausen dma_free_coherent(pl330->ddma.dev, 1927f6f2421cSLars-Peter Clausen chans * pl330->mcbufsz, 1928b7d861d9SBoojin Kim pl330->mcode_cpu, pl330->mcode_bus); 1929b7d861d9SBoojin Kim return ret; 1930b7d861d9SBoojin Kim } 1931b7d861d9SBoojin Kim 1932b7d861d9SBoojin Kim return 0; 1933b7d861d9SBoojin Kim } 1934b7d861d9SBoojin Kim 1935f6f2421cSLars-Peter Clausen static int pl330_add(struct pl330_dmac *pl330) 1936b7d861d9SBoojin Kim { 1937b7d861d9SBoojin Kim void __iomem *regs; 1938b7d861d9SBoojin Kim int i, ret; 1939b7d861d9SBoojin Kim 1940f6f2421cSLars-Peter Clausen regs = pl330->base; 1941b7d861d9SBoojin Kim 1942b7d861d9SBoojin Kim /* Check if we can handle this DMAC */ 1943f6f2421cSLars-Peter Clausen if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) { 1944f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n", 1945f6f2421cSLars-Peter Clausen pl330->pcfg.periph_id); 1946b7d861d9SBoojin Kim return -EINVAL; 1947b7d861d9SBoojin Kim } 1948b7d861d9SBoojin Kim 1949b7d861d9SBoojin Kim /* Read the configuration of the DMAC */ 1950f6f2421cSLars-Peter Clausen read_dmac_config(pl330); 1951b7d861d9SBoojin Kim 1952f6f2421cSLars-Peter Clausen if (pl330->pcfg.num_events == 0) { 1953f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n", 1954b7d861d9SBoojin Kim __func__, __LINE__); 1955b7d861d9SBoojin Kim return -EINVAL; 1956b7d861d9SBoojin Kim } 1957b7d861d9SBoojin Kim 1958b7d861d9SBoojin Kim spin_lock_init(&pl330->lock); 1959b7d861d9SBoojin Kim 1960b7d861d9SBoojin Kim INIT_LIST_HEAD(&pl330->req_done); 1961b7d861d9SBoojin Kim 1962b7d861d9SBoojin Kim /* Use default MC buffer size if not provided */ 1963f6f2421cSLars-Peter Clausen if (!pl330->mcbufsz) 1964f6f2421cSLars-Peter Clausen pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2; 1965b7d861d9SBoojin Kim 1966b7d861d9SBoojin Kim /* Mark all events as free */ 1967f6f2421cSLars-Peter Clausen for (i = 0; i < pl330->pcfg.num_events; i++) 1968b7d861d9SBoojin Kim pl330->events[i] = -1; 1969b7d861d9SBoojin Kim 1970b7d861d9SBoojin Kim /* Allocate resources needed by the DMAC */ 1971b7d861d9SBoojin Kim ret = dmac_alloc_resources(pl330); 1972b7d861d9SBoojin Kim if (ret) { 1973f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n"); 1974b7d861d9SBoojin Kim return ret; 1975b7d861d9SBoojin Kim } 1976b7d861d9SBoojin Kim 1977b7d861d9SBoojin Kim tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330); 1978b7d861d9SBoojin Kim 1979b7d861d9SBoojin Kim pl330->state = INIT; 1980b7d861d9SBoojin Kim 1981b7d861d9SBoojin Kim return 0; 1982b7d861d9SBoojin Kim } 1983b7d861d9SBoojin Kim 1984b7d861d9SBoojin Kim static int dmac_free_threads(struct pl330_dmac *pl330) 1985b7d861d9SBoojin Kim { 1986b7d861d9SBoojin Kim struct pl330_thread *thrd; 1987b7d861d9SBoojin Kim int i; 1988b7d861d9SBoojin Kim 1989b7d861d9SBoojin Kim /* Release Channel threads */ 1990f6f2421cSLars-Peter Clausen for (i = 0; i < pl330->pcfg.num_chan; i++) { 1991b7d861d9SBoojin Kim thrd = &pl330->channels[i]; 199265ad6060SLars-Peter Clausen pl330_release_channel(thrd); 1993b7d861d9SBoojin Kim } 1994b7d861d9SBoojin Kim 1995b7d861d9SBoojin Kim /* Free memory */ 1996b7d861d9SBoojin Kim kfree(pl330->channels); 1997b7d861d9SBoojin Kim 1998b7d861d9SBoojin Kim return 0; 1999b7d861d9SBoojin Kim } 2000b7d861d9SBoojin Kim 2001f6f2421cSLars-Peter Clausen static void pl330_del(struct pl330_dmac *pl330) 2002b7d861d9SBoojin Kim { 2003b7d861d9SBoojin Kim pl330->state = UNINIT; 2004b7d861d9SBoojin Kim 2005b7d861d9SBoojin Kim tasklet_kill(&pl330->tasks); 2006b7d861d9SBoojin Kim 2007b7d861d9SBoojin Kim /* Free DMAC resources */ 2008f6f2421cSLars-Peter Clausen dmac_free_threads(pl330); 2009b7d861d9SBoojin Kim 2010f6f2421cSLars-Peter Clausen dma_free_coherent(pl330->ddma.dev, 2011f6f2421cSLars-Peter Clausen pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu, 2012f6f2421cSLars-Peter Clausen pl330->mcode_bus); 2013b7d861d9SBoojin Kim } 2014b7d861d9SBoojin Kim 20153e2ec13aSThomas Abraham /* forward declaration */ 20163e2ec13aSThomas Abraham static struct amba_driver pl330_driver; 20173e2ec13aSThomas Abraham 2018b3040e40SJassi Brar static inline struct dma_pl330_chan * 2019b3040e40SJassi Brar to_pchan(struct dma_chan *ch) 2020b3040e40SJassi Brar { 2021b3040e40SJassi Brar if (!ch) 2022b3040e40SJassi Brar return NULL; 2023b3040e40SJassi Brar 2024b3040e40SJassi Brar return container_of(ch, struct dma_pl330_chan, chan); 2025b3040e40SJassi Brar } 2026b3040e40SJassi Brar 2027b3040e40SJassi Brar static inline struct dma_pl330_desc * 2028b3040e40SJassi Brar to_desc(struct dma_async_tx_descriptor *tx) 2029b3040e40SJassi Brar { 2030b3040e40SJassi Brar return container_of(tx, struct dma_pl330_desc, txd); 2031b3040e40SJassi Brar } 2032b3040e40SJassi Brar 2033b3040e40SJassi Brar static inline void fill_queue(struct dma_pl330_chan *pch) 2034b3040e40SJassi Brar { 2035b3040e40SJassi Brar struct dma_pl330_desc *desc; 2036b3040e40SJassi Brar int ret; 2037b3040e40SJassi Brar 2038b3040e40SJassi Brar list_for_each_entry(desc, &pch->work_list, node) { 2039b3040e40SJassi Brar 2040b3040e40SJassi Brar /* If already submitted */ 2041b3040e40SJassi Brar if (desc->status == BUSY) 204230fb980bSJassi Brar continue; 2043b3040e40SJassi Brar 204465ad6060SLars-Peter Clausen ret = pl330_submit_req(pch->thread, &desc->req); 2045b3040e40SJassi Brar if (!ret) { 2046b3040e40SJassi Brar desc->status = BUSY; 2047b3040e40SJassi Brar } else if (ret == -EAGAIN) { 2048b3040e40SJassi Brar /* QFull or DMAC Dying */ 2049b3040e40SJassi Brar break; 2050b3040e40SJassi Brar } else { 2051b3040e40SJassi Brar /* Unacceptable request */ 2052b3040e40SJassi Brar desc->status = DONE; 2053f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n", 2054b3040e40SJassi Brar __func__, __LINE__, desc->txd.cookie); 2055b3040e40SJassi Brar tasklet_schedule(&pch->task); 2056b3040e40SJassi Brar } 2057b3040e40SJassi Brar } 2058b3040e40SJassi Brar } 2059b3040e40SJassi Brar 2060b3040e40SJassi Brar static void pl330_tasklet(unsigned long data) 2061b3040e40SJassi Brar { 2062b3040e40SJassi Brar struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data; 2063b3040e40SJassi Brar struct dma_pl330_desc *desc, *_dt; 2064b3040e40SJassi Brar unsigned long flags; 2065b3040e40SJassi Brar 2066b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2067b3040e40SJassi Brar 2068b3040e40SJassi Brar /* Pick up ripe tomatoes */ 2069b3040e40SJassi Brar list_for_each_entry_safe(desc, _dt, &pch->work_list, node) 2070b3040e40SJassi Brar if (desc->status == DONE) { 207130c1dc0fSTushar Behera if (!pch->cyclic) 2072f7fbce07SRussell King - ARM Linux dma_cookie_complete(&desc->txd); 207339ff8613SLars-Peter Clausen list_move_tail(&desc->node, &pch->completed_list); 2074b3040e40SJassi Brar } 2075b3040e40SJassi Brar 2076b3040e40SJassi Brar /* Try to submit a req imm. next to the last completed cookie */ 2077b3040e40SJassi Brar fill_queue(pch); 2078b3040e40SJassi Brar 2079b3040e40SJassi Brar /* Make sure the PL330 Channel thread is active */ 208065ad6060SLars-Peter Clausen pl330_chan_ctrl(pch->thread, PL330_OP_START); 2081b3040e40SJassi Brar 208239ff8613SLars-Peter Clausen while (!list_empty(&pch->completed_list)) { 208339ff8613SLars-Peter Clausen dma_async_tx_callback callback; 208439ff8613SLars-Peter Clausen void *callback_param; 2085b3040e40SJassi Brar 208639ff8613SLars-Peter Clausen desc = list_first_entry(&pch->completed_list, 208739ff8613SLars-Peter Clausen struct dma_pl330_desc, node); 208839ff8613SLars-Peter Clausen 208939ff8613SLars-Peter Clausen callback = desc->txd.callback; 209039ff8613SLars-Peter Clausen callback_param = desc->txd.callback_param; 209139ff8613SLars-Peter Clausen 209239ff8613SLars-Peter Clausen if (pch->cyclic) { 209339ff8613SLars-Peter Clausen desc->status = PREP; 209439ff8613SLars-Peter Clausen list_move_tail(&desc->node, &pch->work_list); 209539ff8613SLars-Peter Clausen } else { 209639ff8613SLars-Peter Clausen desc->status = FREE; 209739ff8613SLars-Peter Clausen list_move_tail(&desc->node, &pch->dmac->desc_pool); 209839ff8613SLars-Peter Clausen } 209939ff8613SLars-Peter Clausen 2100d38a8c62SDan Williams dma_descriptor_unmap(&desc->txd); 2101d38a8c62SDan Williams 210239ff8613SLars-Peter Clausen if (callback) { 210339ff8613SLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 210439ff8613SLars-Peter Clausen callback(callback_param); 210539ff8613SLars-Peter Clausen spin_lock_irqsave(&pch->lock, flags); 210639ff8613SLars-Peter Clausen } 210739ff8613SLars-Peter Clausen } 210839ff8613SLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 2109b3040e40SJassi Brar } 2110b3040e40SJassi Brar 21113e2ec13aSThomas Abraham bool pl330_filter(struct dma_chan *chan, void *param) 21123e2ec13aSThomas Abraham { 2113cd072515SThomas Abraham u8 *peri_id; 21143e2ec13aSThomas Abraham 21153e2ec13aSThomas Abraham if (chan->device->dev->driver != &pl330_driver.drv) 21163e2ec13aSThomas Abraham return false; 21173e2ec13aSThomas Abraham 2118cd072515SThomas Abraham peri_id = chan->private; 21192f986ec6SDan Carpenter return *peri_id == (unsigned long)param; 21203e2ec13aSThomas Abraham } 21213e2ec13aSThomas Abraham EXPORT_SYMBOL(pl330_filter); 21223e2ec13aSThomas Abraham 2123a80258f9SPadmavathi Venna static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec, 2124a80258f9SPadmavathi Venna struct of_dma *ofdma) 2125a80258f9SPadmavathi Venna { 2126a80258f9SPadmavathi Venna int count = dma_spec->args_count; 2127f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = ofdma->of_dma_data; 212870cbb163SLars-Peter Clausen unsigned int chan_id; 2129a80258f9SPadmavathi Venna 2130f6f2421cSLars-Peter Clausen if (!pl330) 2131f6f2421cSLars-Peter Clausen return NULL; 2132f6f2421cSLars-Peter Clausen 2133a80258f9SPadmavathi Venna if (count != 1) 2134a80258f9SPadmavathi Venna return NULL; 2135a80258f9SPadmavathi Venna 213670cbb163SLars-Peter Clausen chan_id = dma_spec->args[0]; 2137f6f2421cSLars-Peter Clausen if (chan_id >= pl330->num_peripherals) 213870cbb163SLars-Peter Clausen return NULL; 2139a80258f9SPadmavathi Venna 2140f6f2421cSLars-Peter Clausen return dma_get_slave_channel(&pl330->peripherals[chan_id].chan); 2141a80258f9SPadmavathi Venna } 2142a80258f9SPadmavathi Venna 2143b3040e40SJassi Brar static int pl330_alloc_chan_resources(struct dma_chan *chan) 2144b3040e40SJassi Brar { 2145b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2146f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2147b3040e40SJassi Brar unsigned long flags; 2148b3040e40SJassi Brar 2149b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2150b3040e40SJassi Brar 2151d3ee98cdSRussell King - ARM Linux dma_cookie_init(chan); 215242bc9cf4SBoojin Kim pch->cyclic = false; 2153b3040e40SJassi Brar 2154f6f2421cSLars-Peter Clausen pch->thread = pl330_request_channel(pl330); 215565ad6060SLars-Peter Clausen if (!pch->thread) { 2156b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 215702747885SInderpal Singh return -ENOMEM; 2158b3040e40SJassi Brar } 2159b3040e40SJassi Brar 2160b3040e40SJassi Brar tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch); 2161b3040e40SJassi Brar 2162b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 2163b3040e40SJassi Brar 2164b3040e40SJassi Brar return 1; 2165b3040e40SJassi Brar } 2166b3040e40SJassi Brar 2167b3040e40SJassi Brar static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg) 2168b3040e40SJassi Brar { 2169b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 217039ff8613SLars-Peter Clausen struct dma_pl330_desc *desc; 2171b3040e40SJassi Brar unsigned long flags; 2172f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 21731d0c1d60SBoojin Kim struct dma_slave_config *slave_config; 2174ae43b886SBoojin Kim LIST_HEAD(list); 2175b3040e40SJassi Brar 21761d0c1d60SBoojin Kim switch (cmd) { 21771d0c1d60SBoojin Kim case DMA_TERMINATE_ALL: 2178b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2179b3040e40SJassi Brar 2180b3040e40SJassi Brar /* FLUSH the PL330 Channel thread */ 218165ad6060SLars-Peter Clausen pl330_chan_ctrl(pch->thread, PL330_OP_FLUSH); 2182b3040e40SJassi Brar 2183b3040e40SJassi Brar /* Mark all desc done */ 218404abf5daSLars-Peter Clausen list_for_each_entry(desc, &pch->submitted_list, node) { 218504abf5daSLars-Peter Clausen desc->status = FREE; 218604abf5daSLars-Peter Clausen dma_cookie_complete(&desc->txd); 218704abf5daSLars-Peter Clausen } 218804abf5daSLars-Peter Clausen 218939ff8613SLars-Peter Clausen list_for_each_entry(desc, &pch->work_list , node) { 219039ff8613SLars-Peter Clausen desc->status = FREE; 219139ff8613SLars-Peter Clausen dma_cookie_complete(&desc->txd); 2192ae43b886SBoojin Kim } 2193b3040e40SJassi Brar 219439ff8613SLars-Peter Clausen list_for_each_entry(desc, &pch->completed_list , node) { 219539ff8613SLars-Peter Clausen desc->status = FREE; 219639ff8613SLars-Peter Clausen dma_cookie_complete(&desc->txd); 219739ff8613SLars-Peter Clausen } 219839ff8613SLars-Peter Clausen 2199f6f2421cSLars-Peter Clausen list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool); 2200f6f2421cSLars-Peter Clausen list_splice_tail_init(&pch->work_list, &pl330->desc_pool); 2201f6f2421cSLars-Peter Clausen list_splice_tail_init(&pch->completed_list, &pl330->desc_pool); 2202b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 22031d0c1d60SBoojin Kim break; 22041d0c1d60SBoojin Kim case DMA_SLAVE_CONFIG: 22051d0c1d60SBoojin Kim slave_config = (struct dma_slave_config *)arg; 2206b3040e40SJassi Brar 2207db8196dfSVinod Koul if (slave_config->direction == DMA_MEM_TO_DEV) { 22081d0c1d60SBoojin Kim if (slave_config->dst_addr) 22091d0c1d60SBoojin Kim pch->fifo_addr = slave_config->dst_addr; 22101d0c1d60SBoojin Kim if (slave_config->dst_addr_width) 22111d0c1d60SBoojin Kim pch->burst_sz = __ffs(slave_config->dst_addr_width); 22121d0c1d60SBoojin Kim if (slave_config->dst_maxburst) 22131d0c1d60SBoojin Kim pch->burst_len = slave_config->dst_maxburst; 2214db8196dfSVinod Koul } else if (slave_config->direction == DMA_DEV_TO_MEM) { 22151d0c1d60SBoojin Kim if (slave_config->src_addr) 22161d0c1d60SBoojin Kim pch->fifo_addr = slave_config->src_addr; 22171d0c1d60SBoojin Kim if (slave_config->src_addr_width) 22181d0c1d60SBoojin Kim pch->burst_sz = __ffs(slave_config->src_addr_width); 22191d0c1d60SBoojin Kim if (slave_config->src_maxburst) 22201d0c1d60SBoojin Kim pch->burst_len = slave_config->src_maxburst; 22211d0c1d60SBoojin Kim } 22221d0c1d60SBoojin Kim break; 22231d0c1d60SBoojin Kim default: 2224f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, "Not supported command.\n"); 22251d0c1d60SBoojin Kim return -ENXIO; 22261d0c1d60SBoojin Kim } 2227b3040e40SJassi Brar 2228b3040e40SJassi Brar return 0; 2229b3040e40SJassi Brar } 2230b3040e40SJassi Brar 2231b3040e40SJassi Brar static void pl330_free_chan_resources(struct dma_chan *chan) 2232b3040e40SJassi Brar { 2233b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2234b3040e40SJassi Brar unsigned long flags; 2235b3040e40SJassi Brar 2236b3040e40SJassi Brar tasklet_kill(&pch->task); 2237b3040e40SJassi Brar 2238da331ba8SBartlomiej Zolnierkiewicz spin_lock_irqsave(&pch->lock, flags); 2239da331ba8SBartlomiej Zolnierkiewicz 224065ad6060SLars-Peter Clausen pl330_release_channel(pch->thread); 224165ad6060SLars-Peter Clausen pch->thread = NULL; 2242b3040e40SJassi Brar 224342bc9cf4SBoojin Kim if (pch->cyclic) 224442bc9cf4SBoojin Kim list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); 224542bc9cf4SBoojin Kim 2246b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 2247b3040e40SJassi Brar } 2248b3040e40SJassi Brar 2249b3040e40SJassi Brar static enum dma_status 2250b3040e40SJassi Brar pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, 2251b3040e40SJassi Brar struct dma_tx_state *txstate) 2252b3040e40SJassi Brar { 225396a2af41SRussell King - ARM Linux return dma_cookie_status(chan, cookie, txstate); 2254b3040e40SJassi Brar } 2255b3040e40SJassi Brar 2256b3040e40SJassi Brar static void pl330_issue_pending(struct dma_chan *chan) 2257b3040e40SJassi Brar { 225804abf5daSLars-Peter Clausen struct dma_pl330_chan *pch = to_pchan(chan); 225904abf5daSLars-Peter Clausen unsigned long flags; 226004abf5daSLars-Peter Clausen 226104abf5daSLars-Peter Clausen spin_lock_irqsave(&pch->lock, flags); 226204abf5daSLars-Peter Clausen list_splice_tail_init(&pch->submitted_list, &pch->work_list); 226304abf5daSLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 226404abf5daSLars-Peter Clausen 226504abf5daSLars-Peter Clausen pl330_tasklet((unsigned long)pch); 2266b3040e40SJassi Brar } 2267b3040e40SJassi Brar 2268b3040e40SJassi Brar /* 2269b3040e40SJassi Brar * We returned the last one of the circular list of descriptor(s) 2270b3040e40SJassi Brar * from prep_xxx, so the argument to submit corresponds to the last 2271b3040e40SJassi Brar * descriptor of the list. 2272b3040e40SJassi Brar */ 2273b3040e40SJassi Brar static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) 2274b3040e40SJassi Brar { 2275b3040e40SJassi Brar struct dma_pl330_desc *desc, *last = to_desc(tx); 2276b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(tx->chan); 2277b3040e40SJassi Brar dma_cookie_t cookie; 2278b3040e40SJassi Brar unsigned long flags; 2279b3040e40SJassi Brar 2280b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2281b3040e40SJassi Brar 2282b3040e40SJassi Brar /* Assign cookies to all nodes */ 2283b3040e40SJassi Brar while (!list_empty(&last->node)) { 2284b3040e40SJassi Brar desc = list_entry(last->node.next, struct dma_pl330_desc, node); 2285fc514460SLars-Peter Clausen if (pch->cyclic) { 2286fc514460SLars-Peter Clausen desc->txd.callback = last->txd.callback; 2287fc514460SLars-Peter Clausen desc->txd.callback_param = last->txd.callback_param; 2288fc514460SLars-Peter Clausen } 2289b3040e40SJassi Brar 2290884485e1SRussell King - ARM Linux dma_cookie_assign(&desc->txd); 2291b3040e40SJassi Brar 229204abf5daSLars-Peter Clausen list_move_tail(&desc->node, &pch->submitted_list); 2293b3040e40SJassi Brar } 2294b3040e40SJassi Brar 2295884485e1SRussell King - ARM Linux cookie = dma_cookie_assign(&last->txd); 229604abf5daSLars-Peter Clausen list_add_tail(&last->node, &pch->submitted_list); 2297b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 2298b3040e40SJassi Brar 2299b3040e40SJassi Brar return cookie; 2300b3040e40SJassi Brar } 2301b3040e40SJassi Brar 2302b3040e40SJassi Brar static inline void _init_desc(struct dma_pl330_desc *desc) 2303b3040e40SJassi Brar { 2304b3040e40SJassi Brar desc->req.x = &desc->px; 2305b3040e40SJassi Brar desc->rqcfg.swap = SWAP_NO; 2306f0564c7eSLars-Peter Clausen desc->rqcfg.scctl = CCTRL0; 2307f0564c7eSLars-Peter Clausen desc->rqcfg.dcctl = CCTRL0; 2308b3040e40SJassi Brar desc->req.cfg = &desc->rqcfg; 2309b3040e40SJassi Brar desc->txd.tx_submit = pl330_tx_submit; 2310b3040e40SJassi Brar 2311b3040e40SJassi Brar INIT_LIST_HEAD(&desc->node); 2312b3040e40SJassi Brar } 2313b3040e40SJassi Brar 2314b3040e40SJassi Brar /* Returns the number of descriptors added to the DMAC pool */ 2315f6f2421cSLars-Peter Clausen static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count) 2316b3040e40SJassi Brar { 2317b3040e40SJassi Brar struct dma_pl330_desc *desc; 2318b3040e40SJassi Brar unsigned long flags; 2319b3040e40SJassi Brar int i; 2320b3040e40SJassi Brar 23210baf8f6aSWill Deacon desc = kcalloc(count, sizeof(*desc), flg); 2322b3040e40SJassi Brar if (!desc) 2323b3040e40SJassi Brar return 0; 2324b3040e40SJassi Brar 2325f6f2421cSLars-Peter Clausen spin_lock_irqsave(&pl330->pool_lock, flags); 2326b3040e40SJassi Brar 2327b3040e40SJassi Brar for (i = 0; i < count; i++) { 2328b3040e40SJassi Brar _init_desc(&desc[i]); 2329f6f2421cSLars-Peter Clausen list_add_tail(&desc[i].node, &pl330->desc_pool); 2330b3040e40SJassi Brar } 2331b3040e40SJassi Brar 2332f6f2421cSLars-Peter Clausen spin_unlock_irqrestore(&pl330->pool_lock, flags); 2333b3040e40SJassi Brar 2334b3040e40SJassi Brar return count; 2335b3040e40SJassi Brar } 2336b3040e40SJassi Brar 2337f6f2421cSLars-Peter Clausen static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330) 2338b3040e40SJassi Brar { 2339b3040e40SJassi Brar struct dma_pl330_desc *desc = NULL; 2340b3040e40SJassi Brar unsigned long flags; 2341b3040e40SJassi Brar 2342f6f2421cSLars-Peter Clausen spin_lock_irqsave(&pl330->pool_lock, flags); 2343b3040e40SJassi Brar 2344f6f2421cSLars-Peter Clausen if (!list_empty(&pl330->desc_pool)) { 2345f6f2421cSLars-Peter Clausen desc = list_entry(pl330->desc_pool.next, 2346b3040e40SJassi Brar struct dma_pl330_desc, node); 2347b3040e40SJassi Brar 2348b3040e40SJassi Brar list_del_init(&desc->node); 2349b3040e40SJassi Brar 2350b3040e40SJassi Brar desc->status = PREP; 2351b3040e40SJassi Brar desc->txd.callback = NULL; 2352b3040e40SJassi Brar } 2353b3040e40SJassi Brar 2354f6f2421cSLars-Peter Clausen spin_unlock_irqrestore(&pl330->pool_lock, flags); 2355b3040e40SJassi Brar 2356b3040e40SJassi Brar return desc; 2357b3040e40SJassi Brar } 2358b3040e40SJassi Brar 2359b3040e40SJassi Brar static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) 2360b3040e40SJassi Brar { 2361f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2362cd072515SThomas Abraham u8 *peri_id = pch->chan.private; 2363b3040e40SJassi Brar struct dma_pl330_desc *desc; 2364b3040e40SJassi Brar 2365b3040e40SJassi Brar /* Pluck one desc from the pool of DMAC */ 2366f6f2421cSLars-Peter Clausen desc = pluck_desc(pl330); 2367b3040e40SJassi Brar 2368b3040e40SJassi Brar /* If the DMAC pool is empty, alloc new */ 2369b3040e40SJassi Brar if (!desc) { 2370f6f2421cSLars-Peter Clausen if (!add_desc(pl330, GFP_ATOMIC, 1)) 2371b3040e40SJassi Brar return NULL; 2372b3040e40SJassi Brar 2373b3040e40SJassi Brar /* Try again */ 2374f6f2421cSLars-Peter Clausen desc = pluck_desc(pl330); 2375b3040e40SJassi Brar if (!desc) { 2376f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, 2377b3040e40SJassi Brar "%s:%d ALERT!\n", __func__, __LINE__); 2378b3040e40SJassi Brar return NULL; 2379b3040e40SJassi Brar } 2380b3040e40SJassi Brar } 2381b3040e40SJassi Brar 2382b3040e40SJassi Brar /* Initialize the descriptor */ 2383b3040e40SJassi Brar desc->pchan = pch; 2384b3040e40SJassi Brar desc->txd.cookie = 0; 2385b3040e40SJassi Brar async_tx_ack(&desc->txd); 2386b3040e40SJassi Brar 2387cd072515SThomas Abraham desc->req.peri = peri_id ? pch->chan.chan_id : 0; 2388f6f2421cSLars-Peter Clausen desc->rqcfg.pcfg = &pch->dmac->pcfg; 2389b3040e40SJassi Brar 2390b3040e40SJassi Brar dma_async_tx_descriptor_init(&desc->txd, &pch->chan); 2391b3040e40SJassi Brar 2392b3040e40SJassi Brar return desc; 2393b3040e40SJassi Brar } 2394b3040e40SJassi Brar 2395b3040e40SJassi Brar static inline void fill_px(struct pl330_xfer *px, 2396b3040e40SJassi Brar dma_addr_t dst, dma_addr_t src, size_t len) 2397b3040e40SJassi Brar { 2398b3040e40SJassi Brar px->bytes = len; 2399b3040e40SJassi Brar px->dst_addr = dst; 2400b3040e40SJassi Brar px->src_addr = src; 2401b3040e40SJassi Brar } 2402b3040e40SJassi Brar 2403b3040e40SJassi Brar static struct dma_pl330_desc * 2404b3040e40SJassi Brar __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, 2405b3040e40SJassi Brar dma_addr_t src, size_t len) 2406b3040e40SJassi Brar { 2407b3040e40SJassi Brar struct dma_pl330_desc *desc = pl330_get_desc(pch); 2408b3040e40SJassi Brar 2409b3040e40SJassi Brar if (!desc) { 2410f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", 2411b3040e40SJassi Brar __func__, __LINE__); 2412b3040e40SJassi Brar return NULL; 2413b3040e40SJassi Brar } 2414b3040e40SJassi Brar 2415b3040e40SJassi Brar /* 2416b3040e40SJassi Brar * Ideally we should lookout for reqs bigger than 2417b3040e40SJassi Brar * those that can be programmed with 256 bytes of 2418b3040e40SJassi Brar * MC buffer, but considering a req size is seldom 2419b3040e40SJassi Brar * going to be word-unaligned and more than 200MB, 2420b3040e40SJassi Brar * we take it easy. 2421b3040e40SJassi Brar * Also, should the limit is reached we'd rather 2422b3040e40SJassi Brar * have the platform increase MC buffer size than 2423b3040e40SJassi Brar * complicating this API driver. 2424b3040e40SJassi Brar */ 2425b3040e40SJassi Brar fill_px(&desc->px, dst, src, len); 2426b3040e40SJassi Brar 2427b3040e40SJassi Brar return desc; 2428b3040e40SJassi Brar } 2429b3040e40SJassi Brar 2430b3040e40SJassi Brar /* Call after fixing burst size */ 2431b3040e40SJassi Brar static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) 2432b3040e40SJassi Brar { 2433b3040e40SJassi Brar struct dma_pl330_chan *pch = desc->pchan; 2434f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2435b3040e40SJassi Brar int burst_len; 2436b3040e40SJassi Brar 2437f6f2421cSLars-Peter Clausen burst_len = pl330->pcfg.data_bus_width / 8; 2438f6f2421cSLars-Peter Clausen burst_len *= pl330->pcfg.data_buf_dep; 2439b3040e40SJassi Brar burst_len >>= desc->rqcfg.brst_size; 2440b3040e40SJassi Brar 2441b3040e40SJassi Brar /* src/dst_burst_len can't be more than 16 */ 2442b3040e40SJassi Brar if (burst_len > 16) 2443b3040e40SJassi Brar burst_len = 16; 2444b3040e40SJassi Brar 2445b3040e40SJassi Brar while (burst_len > 1) { 2446b3040e40SJassi Brar if (!(len % (burst_len << desc->rqcfg.brst_size))) 2447b3040e40SJassi Brar break; 2448b3040e40SJassi Brar burst_len--; 2449b3040e40SJassi Brar } 2450b3040e40SJassi Brar 2451b3040e40SJassi Brar return burst_len; 2452b3040e40SJassi Brar } 2453b3040e40SJassi Brar 245442bc9cf4SBoojin Kim static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( 245542bc9cf4SBoojin Kim struct dma_chan *chan, dma_addr_t dma_addr, size_t len, 2456185ecb5fSAlexandre Bounine size_t period_len, enum dma_transfer_direction direction, 2457ec8b5e48SPeter Ujfalusi unsigned long flags, void *context) 245842bc9cf4SBoojin Kim { 2459fc514460SLars-Peter Clausen struct dma_pl330_desc *desc = NULL, *first = NULL; 246042bc9cf4SBoojin Kim struct dma_pl330_chan *pch = to_pchan(chan); 2461f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2462fc514460SLars-Peter Clausen unsigned int i; 246342bc9cf4SBoojin Kim dma_addr_t dst; 246442bc9cf4SBoojin Kim dma_addr_t src; 246542bc9cf4SBoojin Kim 2466fc514460SLars-Peter Clausen if (len % period_len != 0) 2467fc514460SLars-Peter Clausen return NULL; 2468fc514460SLars-Peter Clausen 2469fc514460SLars-Peter Clausen if (!is_slave_direction(direction)) { 2470f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n", 2471fc514460SLars-Peter Clausen __func__, __LINE__); 2472fc514460SLars-Peter Clausen return NULL; 2473fc514460SLars-Peter Clausen } 2474fc514460SLars-Peter Clausen 2475fc514460SLars-Peter Clausen for (i = 0; i < len / period_len; i++) { 247642bc9cf4SBoojin Kim desc = pl330_get_desc(pch); 247742bc9cf4SBoojin Kim if (!desc) { 2478f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", 247942bc9cf4SBoojin Kim __func__, __LINE__); 2480fc514460SLars-Peter Clausen 2481fc514460SLars-Peter Clausen if (!first) 2482fc514460SLars-Peter Clausen return NULL; 2483fc514460SLars-Peter Clausen 2484f6f2421cSLars-Peter Clausen spin_lock_irqsave(&pl330->pool_lock, flags); 2485fc514460SLars-Peter Clausen 2486fc514460SLars-Peter Clausen while (!list_empty(&first->node)) { 2487fc514460SLars-Peter Clausen desc = list_entry(first->node.next, 2488fc514460SLars-Peter Clausen struct dma_pl330_desc, node); 2489f6f2421cSLars-Peter Clausen list_move_tail(&desc->node, &pl330->desc_pool); 2490fc514460SLars-Peter Clausen } 2491fc514460SLars-Peter Clausen 2492f6f2421cSLars-Peter Clausen list_move_tail(&first->node, &pl330->desc_pool); 2493fc514460SLars-Peter Clausen 2494f6f2421cSLars-Peter Clausen spin_unlock_irqrestore(&pl330->pool_lock, flags); 2495fc514460SLars-Peter Clausen 249642bc9cf4SBoojin Kim return NULL; 249742bc9cf4SBoojin Kim } 249842bc9cf4SBoojin Kim 249942bc9cf4SBoojin Kim switch (direction) { 2500db8196dfSVinod Koul case DMA_MEM_TO_DEV: 250142bc9cf4SBoojin Kim desc->rqcfg.src_inc = 1; 250242bc9cf4SBoojin Kim desc->rqcfg.dst_inc = 0; 250342bc9cf4SBoojin Kim src = dma_addr; 250442bc9cf4SBoojin Kim dst = pch->fifo_addr; 250542bc9cf4SBoojin Kim break; 2506db8196dfSVinod Koul case DMA_DEV_TO_MEM: 250742bc9cf4SBoojin Kim desc->rqcfg.src_inc = 0; 250842bc9cf4SBoojin Kim desc->rqcfg.dst_inc = 1; 250942bc9cf4SBoojin Kim src = pch->fifo_addr; 251042bc9cf4SBoojin Kim dst = dma_addr; 251142bc9cf4SBoojin Kim break; 251242bc9cf4SBoojin Kim default: 2513fc514460SLars-Peter Clausen break; 251442bc9cf4SBoojin Kim } 251542bc9cf4SBoojin Kim 2516585a9d0bSLars-Peter Clausen desc->req.rqtype = direction; 251742bc9cf4SBoojin Kim desc->rqcfg.brst_size = pch->burst_sz; 251842bc9cf4SBoojin Kim desc->rqcfg.brst_len = 1; 2519fc514460SLars-Peter Clausen fill_px(&desc->px, dst, src, period_len); 2520fc514460SLars-Peter Clausen 2521fc514460SLars-Peter Clausen if (!first) 2522fc514460SLars-Peter Clausen first = desc; 2523fc514460SLars-Peter Clausen else 2524fc514460SLars-Peter Clausen list_add_tail(&desc->node, &first->node); 2525fc514460SLars-Peter Clausen 2526fc514460SLars-Peter Clausen dma_addr += period_len; 2527fc514460SLars-Peter Clausen } 2528fc514460SLars-Peter Clausen 2529fc514460SLars-Peter Clausen if (!desc) 2530fc514460SLars-Peter Clausen return NULL; 253142bc9cf4SBoojin Kim 253242bc9cf4SBoojin Kim pch->cyclic = true; 2533fc514460SLars-Peter Clausen desc->txd.flags = flags; 253442bc9cf4SBoojin Kim 253542bc9cf4SBoojin Kim return &desc->txd; 253642bc9cf4SBoojin Kim } 253742bc9cf4SBoojin Kim 2538b3040e40SJassi Brar static struct dma_async_tx_descriptor * 2539b3040e40SJassi Brar pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, 2540b3040e40SJassi Brar dma_addr_t src, size_t len, unsigned long flags) 2541b3040e40SJassi Brar { 2542b3040e40SJassi Brar struct dma_pl330_desc *desc; 2543b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2544f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2545b3040e40SJassi Brar int burst; 2546b3040e40SJassi Brar 25474e0e6109SRob Herring if (unlikely(!pch || !len)) 2548b3040e40SJassi Brar return NULL; 2549b3040e40SJassi Brar 2550b3040e40SJassi Brar desc = __pl330_prep_dma_memcpy(pch, dst, src, len); 2551b3040e40SJassi Brar if (!desc) 2552b3040e40SJassi Brar return NULL; 2553b3040e40SJassi Brar 2554b3040e40SJassi Brar desc->rqcfg.src_inc = 1; 2555b3040e40SJassi Brar desc->rqcfg.dst_inc = 1; 2556585a9d0bSLars-Peter Clausen desc->req.rqtype = DMA_MEM_TO_MEM; 2557b3040e40SJassi Brar 2558b3040e40SJassi Brar /* Select max possible burst size */ 2559f6f2421cSLars-Peter Clausen burst = pl330->pcfg.data_bus_width / 8; 2560b3040e40SJassi Brar 2561b3040e40SJassi Brar while (burst > 1) { 2562b3040e40SJassi Brar if (!(len % burst)) 2563b3040e40SJassi Brar break; 2564b3040e40SJassi Brar burst /= 2; 2565b3040e40SJassi Brar } 2566b3040e40SJassi Brar 2567b3040e40SJassi Brar desc->rqcfg.brst_size = 0; 2568b3040e40SJassi Brar while (burst != (1 << desc->rqcfg.brst_size)) 2569b3040e40SJassi Brar desc->rqcfg.brst_size++; 2570b3040e40SJassi Brar 2571b3040e40SJassi Brar desc->rqcfg.brst_len = get_burst_len(desc, len); 2572b3040e40SJassi Brar 2573b3040e40SJassi Brar desc->txd.flags = flags; 2574b3040e40SJassi Brar 2575b3040e40SJassi Brar return &desc->txd; 2576b3040e40SJassi Brar } 2577b3040e40SJassi Brar 2578f6f2421cSLars-Peter Clausen static void __pl330_giveback_desc(struct pl330_dmac *pl330, 257952a9d179SChanho Park struct dma_pl330_desc *first) 258052a9d179SChanho Park { 258152a9d179SChanho Park unsigned long flags; 258252a9d179SChanho Park struct dma_pl330_desc *desc; 258352a9d179SChanho Park 258452a9d179SChanho Park if (!first) 258552a9d179SChanho Park return; 258652a9d179SChanho Park 2587f6f2421cSLars-Peter Clausen spin_lock_irqsave(&pl330->pool_lock, flags); 258852a9d179SChanho Park 258952a9d179SChanho Park while (!list_empty(&first->node)) { 259052a9d179SChanho Park desc = list_entry(first->node.next, 259152a9d179SChanho Park struct dma_pl330_desc, node); 2592f6f2421cSLars-Peter Clausen list_move_tail(&desc->node, &pl330->desc_pool); 259352a9d179SChanho Park } 259452a9d179SChanho Park 2595f6f2421cSLars-Peter Clausen list_move_tail(&first->node, &pl330->desc_pool); 259652a9d179SChanho Park 2597f6f2421cSLars-Peter Clausen spin_unlock_irqrestore(&pl330->pool_lock, flags); 259852a9d179SChanho Park } 259952a9d179SChanho Park 2600b3040e40SJassi Brar static struct dma_async_tx_descriptor * 2601b3040e40SJassi Brar pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 2602db8196dfSVinod Koul unsigned int sg_len, enum dma_transfer_direction direction, 2603185ecb5fSAlexandre Bounine unsigned long flg, void *context) 2604b3040e40SJassi Brar { 2605b3040e40SJassi Brar struct dma_pl330_desc *first, *desc = NULL; 2606b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2607b3040e40SJassi Brar struct scatterlist *sg; 26081b9bb715SBoojin Kim int i; 2609b3040e40SJassi Brar dma_addr_t addr; 2610b3040e40SJassi Brar 2611cd072515SThomas Abraham if (unlikely(!pch || !sgl || !sg_len)) 2612b3040e40SJassi Brar return NULL; 2613b3040e40SJassi Brar 26141b9bb715SBoojin Kim addr = pch->fifo_addr; 2615b3040e40SJassi Brar 2616b3040e40SJassi Brar first = NULL; 2617b3040e40SJassi Brar 2618b3040e40SJassi Brar for_each_sg(sgl, sg, sg_len, i) { 2619b3040e40SJassi Brar 2620b3040e40SJassi Brar desc = pl330_get_desc(pch); 2621b3040e40SJassi Brar if (!desc) { 2622f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2623b3040e40SJassi Brar 2624f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, 2625b3040e40SJassi Brar "%s:%d Unable to fetch desc\n", 2626b3040e40SJassi Brar __func__, __LINE__); 2627f6f2421cSLars-Peter Clausen __pl330_giveback_desc(pl330, first); 2628b3040e40SJassi Brar 2629b3040e40SJassi Brar return NULL; 2630b3040e40SJassi Brar } 2631b3040e40SJassi Brar 2632b3040e40SJassi Brar if (!first) 2633b3040e40SJassi Brar first = desc; 2634b3040e40SJassi Brar else 2635b3040e40SJassi Brar list_add_tail(&desc->node, &first->node); 2636b3040e40SJassi Brar 2637db8196dfSVinod Koul if (direction == DMA_MEM_TO_DEV) { 2638b3040e40SJassi Brar desc->rqcfg.src_inc = 1; 2639b3040e40SJassi Brar desc->rqcfg.dst_inc = 0; 2640b3040e40SJassi Brar fill_px(&desc->px, 2641b3040e40SJassi Brar addr, sg_dma_address(sg), sg_dma_len(sg)); 2642b3040e40SJassi Brar } else { 2643b3040e40SJassi Brar desc->rqcfg.src_inc = 0; 2644b3040e40SJassi Brar desc->rqcfg.dst_inc = 1; 2645b3040e40SJassi Brar fill_px(&desc->px, 2646b3040e40SJassi Brar sg_dma_address(sg), addr, sg_dma_len(sg)); 2647b3040e40SJassi Brar } 2648b3040e40SJassi Brar 26491b9bb715SBoojin Kim desc->rqcfg.brst_size = pch->burst_sz; 2650b3040e40SJassi Brar desc->rqcfg.brst_len = 1; 2651585a9d0bSLars-Peter Clausen desc->req.rqtype = direction; 2652b3040e40SJassi Brar } 2653b3040e40SJassi Brar 2654b3040e40SJassi Brar /* Return the last desc in the chain */ 2655b3040e40SJassi Brar desc->txd.flags = flg; 2656b3040e40SJassi Brar return &desc->txd; 2657b3040e40SJassi Brar } 2658b3040e40SJassi Brar 2659b3040e40SJassi Brar static irqreturn_t pl330_irq_handler(int irq, void *data) 2660b3040e40SJassi Brar { 2661b3040e40SJassi Brar if (pl330_update(data)) 2662b3040e40SJassi Brar return IRQ_HANDLED; 2663b3040e40SJassi Brar else 2664b3040e40SJassi Brar return IRQ_NONE; 2665b3040e40SJassi Brar } 2666b3040e40SJassi Brar 2667ca38ff13SLars-Peter Clausen #define PL330_DMA_BUSWIDTHS \ 2668ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ 2669ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 2670ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 2671ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ 2672ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) 2673ca38ff13SLars-Peter Clausen 2674ca38ff13SLars-Peter Clausen static int pl330_dma_device_slave_caps(struct dma_chan *dchan, 2675ca38ff13SLars-Peter Clausen struct dma_slave_caps *caps) 2676ca38ff13SLars-Peter Clausen { 2677ca38ff13SLars-Peter Clausen caps->src_addr_widths = PL330_DMA_BUSWIDTHS; 2678ca38ff13SLars-Peter Clausen caps->dstn_addr_widths = PL330_DMA_BUSWIDTHS; 2679ca38ff13SLars-Peter Clausen caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 2680ca38ff13SLars-Peter Clausen caps->cmd_pause = false; 2681ca38ff13SLars-Peter Clausen caps->cmd_terminate = true; 2682bfb9bb42SLars-Peter Clausen caps->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; 2683ca38ff13SLars-Peter Clausen 2684ca38ff13SLars-Peter Clausen return 0; 2685ca38ff13SLars-Peter Clausen } 2686ca38ff13SLars-Peter Clausen 2687463a1f8bSBill Pemberton static int 2688aa25afadSRussell King pl330_probe(struct amba_device *adev, const struct amba_id *id) 2689b3040e40SJassi Brar { 2690b3040e40SJassi Brar struct dma_pl330_platdata *pdat; 2691f6f2421cSLars-Peter Clausen struct pl330_config *pcfg; 2692f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330; 26930b94c577SPadmavathi Venna struct dma_pl330_chan *pch, *_p; 2694b3040e40SJassi Brar struct dma_device *pd; 2695b3040e40SJassi Brar struct resource *res; 2696b3040e40SJassi Brar int i, ret, irq; 26974e0e6109SRob Herring int num_chan; 2698b3040e40SJassi Brar 2699d4adcc01SJingoo Han pdat = dev_get_platdata(&adev->dev); 2700b3040e40SJassi Brar 270164113016SRussell King ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32)); 270264113016SRussell King if (ret) 270364113016SRussell King return ret; 270464113016SRussell King 2705b3040e40SJassi Brar /* Allocate a new DMAC and its Channels */ 2706f6f2421cSLars-Peter Clausen pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL); 2707f6f2421cSLars-Peter Clausen if (!pl330) { 2708b3040e40SJassi Brar dev_err(&adev->dev, "unable to allocate mem\n"); 2709b3040e40SJassi Brar return -ENOMEM; 2710b3040e40SJassi Brar } 2711b3040e40SJassi Brar 2712f6f2421cSLars-Peter Clausen pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0; 2713b3040e40SJassi Brar 2714b3040e40SJassi Brar res = &adev->res; 2715f6f2421cSLars-Peter Clausen pl330->base = devm_ioremap_resource(&adev->dev, res); 2716f6f2421cSLars-Peter Clausen if (IS_ERR(pl330->base)) 2717f6f2421cSLars-Peter Clausen return PTR_ERR(pl330->base); 2718b3040e40SJassi Brar 2719f6f2421cSLars-Peter Clausen amba_set_drvdata(adev, pl330); 2720a2f5203fSBoojin Kim 272102808b42SDan Carpenter for (i = 0; i < AMBA_NR_IRQS; i++) { 2722e98b3cafSMichal Simek irq = adev->irq[i]; 2723e98b3cafSMichal Simek if (irq) { 2724e98b3cafSMichal Simek ret = devm_request_irq(&adev->dev, irq, 2725e98b3cafSMichal Simek pl330_irq_handler, 0, 2726f6f2421cSLars-Peter Clausen dev_name(&adev->dev), pl330); 2727b3040e40SJassi Brar if (ret) 2728e4d43c17SSachin Kamat return ret; 2729e98b3cafSMichal Simek } else { 2730e98b3cafSMichal Simek break; 2731e98b3cafSMichal Simek } 2732e98b3cafSMichal Simek } 2733b3040e40SJassi Brar 2734f6f2421cSLars-Peter Clausen pcfg = &pl330->pcfg; 2735f6f2421cSLars-Peter Clausen 2736f6f2421cSLars-Peter Clausen pcfg->periph_id = adev->periphid; 2737f6f2421cSLars-Peter Clausen ret = pl330_add(pl330); 2738b3040e40SJassi Brar if (ret) 2739173e838cSMichal Simek return ret; 2740b3040e40SJassi Brar 2741f6f2421cSLars-Peter Clausen INIT_LIST_HEAD(&pl330->desc_pool); 2742f6f2421cSLars-Peter Clausen spin_lock_init(&pl330->pool_lock); 2743b3040e40SJassi Brar 2744b3040e40SJassi Brar /* Create a descriptor pool of default size */ 2745f6f2421cSLars-Peter Clausen if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC)) 2746b3040e40SJassi Brar dev_warn(&adev->dev, "unable to allocate desc\n"); 2747b3040e40SJassi Brar 2748f6f2421cSLars-Peter Clausen pd = &pl330->ddma; 2749b3040e40SJassi Brar INIT_LIST_HEAD(&pd->channels); 2750b3040e40SJassi Brar 2751b3040e40SJassi Brar /* Initialize channel parameters */ 2752c8473828SOlof Johansson if (pdat) 2753f6f2421cSLars-Peter Clausen num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan); 2754c8473828SOlof Johansson else 2755f6f2421cSLars-Peter Clausen num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan); 2756c8473828SOlof Johansson 2757f6f2421cSLars-Peter Clausen pl330->num_peripherals = num_chan; 275870cbb163SLars-Peter Clausen 2759f6f2421cSLars-Peter Clausen pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL); 2760f6f2421cSLars-Peter Clausen if (!pl330->peripherals) { 276161c6e753SSachin Kamat ret = -ENOMEM; 2762f6f2421cSLars-Peter Clausen dev_err(&adev->dev, "unable to allocate pl330->peripherals\n"); 2763e4d43c17SSachin Kamat goto probe_err2; 276461c6e753SSachin Kamat } 27654e0e6109SRob Herring 27664e0e6109SRob Herring for (i = 0; i < num_chan; i++) { 2767f6f2421cSLars-Peter Clausen pch = &pl330->peripherals[i]; 276893ed5544SThomas Abraham if (!adev->dev.of_node) 2769cd072515SThomas Abraham pch->chan.private = pdat ? &pdat->peri_id[i] : NULL; 277093ed5544SThomas Abraham else 277193ed5544SThomas Abraham pch->chan.private = adev->dev.of_node; 2772b3040e40SJassi Brar 277304abf5daSLars-Peter Clausen INIT_LIST_HEAD(&pch->submitted_list); 2774b3040e40SJassi Brar INIT_LIST_HEAD(&pch->work_list); 277539ff8613SLars-Peter Clausen INIT_LIST_HEAD(&pch->completed_list); 2776b3040e40SJassi Brar spin_lock_init(&pch->lock); 277765ad6060SLars-Peter Clausen pch->thread = NULL; 2778b3040e40SJassi Brar pch->chan.device = pd; 2779f6f2421cSLars-Peter Clausen pch->dmac = pl330; 2780b3040e40SJassi Brar 2781b3040e40SJassi Brar /* Add the channel to the DMAC list */ 2782b3040e40SJassi Brar list_add_tail(&pch->chan.device_node, &pd->channels); 2783b3040e40SJassi Brar } 2784b3040e40SJassi Brar 2785b3040e40SJassi Brar pd->dev = &adev->dev; 278693ed5544SThomas Abraham if (pdat) { 2787cd072515SThomas Abraham pd->cap_mask = pdat->cap_mask; 278893ed5544SThomas Abraham } else { 2789cd072515SThomas Abraham dma_cap_set(DMA_MEMCPY, pd->cap_mask); 2790f6f2421cSLars-Peter Clausen if (pcfg->num_peri) { 279193ed5544SThomas Abraham dma_cap_set(DMA_SLAVE, pd->cap_mask); 279293ed5544SThomas Abraham dma_cap_set(DMA_CYCLIC, pd->cap_mask); 27935557a419STushar Behera dma_cap_set(DMA_PRIVATE, pd->cap_mask); 279493ed5544SThomas Abraham } 279593ed5544SThomas Abraham } 2796b3040e40SJassi Brar 2797b3040e40SJassi Brar pd->device_alloc_chan_resources = pl330_alloc_chan_resources; 2798b3040e40SJassi Brar pd->device_free_chan_resources = pl330_free_chan_resources; 2799b3040e40SJassi Brar pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; 280042bc9cf4SBoojin Kim pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; 2801b3040e40SJassi Brar pd->device_tx_status = pl330_tx_status; 2802b3040e40SJassi Brar pd->device_prep_slave_sg = pl330_prep_slave_sg; 2803b3040e40SJassi Brar pd->device_control = pl330_control; 2804b3040e40SJassi Brar pd->device_issue_pending = pl330_issue_pending; 2805ca38ff13SLars-Peter Clausen pd->device_slave_caps = pl330_dma_device_slave_caps; 2806b3040e40SJassi Brar 2807b3040e40SJassi Brar ret = dma_async_device_register(pd); 2808b3040e40SJassi Brar if (ret) { 2809b3040e40SJassi Brar dev_err(&adev->dev, "unable to register DMAC\n"); 28100b94c577SPadmavathi Venna goto probe_err3; 28110b94c577SPadmavathi Venna } 28120b94c577SPadmavathi Venna 28130b94c577SPadmavathi Venna if (adev->dev.of_node) { 28140b94c577SPadmavathi Venna ret = of_dma_controller_register(adev->dev.of_node, 2815f6f2421cSLars-Peter Clausen of_dma_pl330_xlate, pl330); 28160b94c577SPadmavathi Venna if (ret) { 28170b94c577SPadmavathi Venna dev_err(&adev->dev, 28180b94c577SPadmavathi Venna "unable to register DMA to the generic DT DMA helpers\n"); 28190b94c577SPadmavathi Venna } 2820b3040e40SJassi Brar } 2821b714b84eSLars-Peter Clausen 2822f6f2421cSLars-Peter Clausen adev->dev.dma_parms = &pl330->dma_parms; 2823b714b84eSLars-Peter Clausen 2824dbaf6d85SVinod Koul /* 2825dbaf6d85SVinod Koul * This is the limit for transfers with a buswidth of 1, larger 2826dbaf6d85SVinod Koul * buswidths will have larger limits. 2827dbaf6d85SVinod Koul */ 2828dbaf6d85SVinod Koul ret = dma_set_max_seg_size(&adev->dev, 1900800); 2829dbaf6d85SVinod Koul if (ret) 2830dbaf6d85SVinod Koul dev_err(&adev->dev, "unable to set the seg size\n"); 2831dbaf6d85SVinod Koul 2832b3040e40SJassi Brar 2833b3040e40SJassi Brar dev_info(&adev->dev, 2834b3040e40SJassi Brar "Loaded driver for PL330 DMAC-%d\n", adev->periphid); 2835b3040e40SJassi Brar dev_info(&adev->dev, 2836b3040e40SJassi Brar "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", 2837f6f2421cSLars-Peter Clausen pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan, 2838f6f2421cSLars-Peter Clausen pcfg->num_peri, pcfg->num_events); 2839b3040e40SJassi Brar 2840b3040e40SJassi Brar return 0; 28410b94c577SPadmavathi Venna probe_err3: 28420b94c577SPadmavathi Venna /* Idle the DMAC */ 2843f6f2421cSLars-Peter Clausen list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, 28440b94c577SPadmavathi Venna chan.device_node) { 28450b94c577SPadmavathi Venna 28460b94c577SPadmavathi Venna /* Remove the channel */ 28470b94c577SPadmavathi Venna list_del(&pch->chan.device_node); 28480b94c577SPadmavathi Venna 28490b94c577SPadmavathi Venna /* Flush the channel */ 28500b94c577SPadmavathi Venna pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); 28510b94c577SPadmavathi Venna pl330_free_chan_resources(&pch->chan); 28520b94c577SPadmavathi Venna } 2853b3040e40SJassi Brar probe_err2: 2854f6f2421cSLars-Peter Clausen pl330_del(pl330); 2855b3040e40SJassi Brar 2856b3040e40SJassi Brar return ret; 2857b3040e40SJassi Brar } 2858b3040e40SJassi Brar 28594bf27b8bSGreg Kroah-Hartman static int pl330_remove(struct amba_device *adev) 2860b3040e40SJassi Brar { 2861f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = amba_get_drvdata(adev); 2862b3040e40SJassi Brar struct dma_pl330_chan *pch, *_p; 2863b3040e40SJassi Brar 28640b94c577SPadmavathi Venna if (adev->dev.of_node) 2865421da89aSPadmavathi Venna of_dma_controller_free(adev->dev.of_node); 2866421da89aSPadmavathi Venna 2867f6f2421cSLars-Peter Clausen dma_async_device_unregister(&pl330->ddma); 2868b3040e40SJassi Brar 2869b3040e40SJassi Brar /* Idle the DMAC */ 2870f6f2421cSLars-Peter Clausen list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, 2871b3040e40SJassi Brar chan.device_node) { 2872b3040e40SJassi Brar 2873b3040e40SJassi Brar /* Remove the channel */ 2874b3040e40SJassi Brar list_del(&pch->chan.device_node); 2875b3040e40SJassi Brar 2876b3040e40SJassi Brar /* Flush the channel */ 2877b3040e40SJassi Brar pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); 2878b3040e40SJassi Brar pl330_free_chan_resources(&pch->chan); 2879b3040e40SJassi Brar } 2880b3040e40SJassi Brar 2881f6f2421cSLars-Peter Clausen pl330_del(pl330); 2882b3040e40SJassi Brar 2883b3040e40SJassi Brar return 0; 2884b3040e40SJassi Brar } 2885b3040e40SJassi Brar 2886b3040e40SJassi Brar static struct amba_id pl330_ids[] = { 2887b3040e40SJassi Brar { 2888b3040e40SJassi Brar .id = 0x00041330, 2889b3040e40SJassi Brar .mask = 0x000fffff, 2890b3040e40SJassi Brar }, 2891b3040e40SJassi Brar { 0, 0 }, 2892b3040e40SJassi Brar }; 2893b3040e40SJassi Brar 2894e8fa516aSDave Martin MODULE_DEVICE_TABLE(amba, pl330_ids); 2895e8fa516aSDave Martin 2896b3040e40SJassi Brar static struct amba_driver pl330_driver = { 2897b3040e40SJassi Brar .drv = { 2898b3040e40SJassi Brar .owner = THIS_MODULE, 2899b3040e40SJassi Brar .name = "dma-pl330", 2900b3040e40SJassi Brar }, 2901b3040e40SJassi Brar .id_table = pl330_ids, 2902b3040e40SJassi Brar .probe = pl330_probe, 2903b3040e40SJassi Brar .remove = pl330_remove, 2904b3040e40SJassi Brar }; 2905b3040e40SJassi Brar 29069e5ed094Sviresh kumar module_amba_driver(pl330_driver); 2907b3040e40SJassi Brar 2908b3040e40SJassi Brar MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); 2909b3040e40SJassi Brar MODULE_DESCRIPTION("API Driver for PL330 DMAC"); 2910b3040e40SJassi Brar MODULE_LICENSE("GPL"); 2911