1b7d861d9SBoojin Kim /* 2b7d861d9SBoojin Kim * Copyright (c) 2012 Samsung Electronics Co., Ltd. 3b7d861d9SBoojin Kim * http://www.samsung.com 4b3040e40SJassi Brar * 5b3040e40SJassi Brar * Copyright (C) 2010 Samsung Electronics Co. Ltd. 6b3040e40SJassi Brar * Jaswinder Singh <jassi.brar@samsung.com> 7b3040e40SJassi Brar * 8b3040e40SJassi Brar * This program is free software; you can redistribute it and/or modify 9b3040e40SJassi Brar * it under the terms of the GNU General Public License as published by 10b3040e40SJassi Brar * the Free Software Foundation; either version 2 of the License, or 11b3040e40SJassi Brar * (at your option) any later version. 12b3040e40SJassi Brar */ 13b3040e40SJassi Brar 14b7d861d9SBoojin Kim #include <linux/kernel.h> 15b3040e40SJassi Brar #include <linux/io.h> 16b3040e40SJassi Brar #include <linux/init.h> 17b3040e40SJassi Brar #include <linux/slab.h> 18b3040e40SJassi Brar #include <linux/module.h> 19b7d861d9SBoojin Kim #include <linux/string.h> 20b7d861d9SBoojin Kim #include <linux/delay.h> 21b7d861d9SBoojin Kim #include <linux/interrupt.h> 22b7d861d9SBoojin Kim #include <linux/dma-mapping.h> 23b3040e40SJassi Brar #include <linux/dmaengine.h> 24b3040e40SJassi Brar #include <linux/amba/bus.h> 25b3040e40SJassi Brar #include <linux/amba/pl330.h> 261b9bb715SBoojin Kim #include <linux/scatterlist.h> 2793ed5544SThomas Abraham #include <linux/of.h> 28a80258f9SPadmavathi Venna #include <linux/of_dma.h> 29bcc7fa95SSachin Kamat #include <linux/err.h> 30ae43b328SKrzysztof Kozlowski #include <linux/pm_runtime.h> 31b3040e40SJassi Brar 32d2ebfb33SRussell King - ARM Linux #include "dmaengine.h" 33b7d861d9SBoojin Kim #define PL330_MAX_CHAN 8 34b7d861d9SBoojin Kim #define PL330_MAX_IRQS 32 35b7d861d9SBoojin Kim #define PL330_MAX_PERI 32 36b7d861d9SBoojin Kim 37f0564c7eSLars-Peter Clausen enum pl330_cachectrl { 38f0564c7eSLars-Peter Clausen CCTRL0, /* Noncacheable and nonbufferable */ 39f0564c7eSLars-Peter Clausen CCTRL1, /* Bufferable only */ 40f0564c7eSLars-Peter Clausen CCTRL2, /* Cacheable, but do not allocate */ 41f0564c7eSLars-Peter Clausen CCTRL3, /* Cacheable and bufferable, but do not allocate */ 42f0564c7eSLars-Peter Clausen INVALID1, /* AWCACHE = 0x1000 */ 43f0564c7eSLars-Peter Clausen INVALID2, 44f0564c7eSLars-Peter Clausen CCTRL6, /* Cacheable write-through, allocate on writes only */ 45f0564c7eSLars-Peter Clausen CCTRL7, /* Cacheable write-back, allocate on writes only */ 46b7d861d9SBoojin Kim }; 47b7d861d9SBoojin Kim 48b7d861d9SBoojin Kim enum pl330_byteswap { 49b7d861d9SBoojin Kim SWAP_NO, 50b7d861d9SBoojin Kim SWAP_2, 51b7d861d9SBoojin Kim SWAP_4, 52b7d861d9SBoojin Kim SWAP_8, 53b7d861d9SBoojin Kim SWAP_16, 54b7d861d9SBoojin Kim }; 55b7d861d9SBoojin Kim 56b7d861d9SBoojin Kim /* Register and Bit field Definitions */ 57b7d861d9SBoojin Kim #define DS 0x0 58b7d861d9SBoojin Kim #define DS_ST_STOP 0x0 59b7d861d9SBoojin Kim #define DS_ST_EXEC 0x1 60b7d861d9SBoojin Kim #define DS_ST_CMISS 0x2 61b7d861d9SBoojin Kim #define DS_ST_UPDTPC 0x3 62b7d861d9SBoojin Kim #define DS_ST_WFE 0x4 63b7d861d9SBoojin Kim #define DS_ST_ATBRR 0x5 64b7d861d9SBoojin Kim #define DS_ST_QBUSY 0x6 65b7d861d9SBoojin Kim #define DS_ST_WFP 0x7 66b7d861d9SBoojin Kim #define DS_ST_KILL 0x8 67b7d861d9SBoojin Kim #define DS_ST_CMPLT 0x9 68b7d861d9SBoojin Kim #define DS_ST_FLTCMP 0xe 69b7d861d9SBoojin Kim #define DS_ST_FAULT 0xf 70b7d861d9SBoojin Kim 71b7d861d9SBoojin Kim #define DPC 0x4 72b7d861d9SBoojin Kim #define INTEN 0x20 73b7d861d9SBoojin Kim #define ES 0x24 74b7d861d9SBoojin Kim #define INTSTATUS 0x28 75b7d861d9SBoojin Kim #define INTCLR 0x2c 76b7d861d9SBoojin Kim #define FSM 0x30 77b7d861d9SBoojin Kim #define FSC 0x34 78b7d861d9SBoojin Kim #define FTM 0x38 79b7d861d9SBoojin Kim 80b7d861d9SBoojin Kim #define _FTC 0x40 81b7d861d9SBoojin Kim #define FTC(n) (_FTC + (n)*0x4) 82b7d861d9SBoojin Kim 83b7d861d9SBoojin Kim #define _CS 0x100 84b7d861d9SBoojin Kim #define CS(n) (_CS + (n)*0x8) 85b7d861d9SBoojin Kim #define CS_CNS (1 << 21) 86b7d861d9SBoojin Kim 87b7d861d9SBoojin Kim #define _CPC 0x104 88b7d861d9SBoojin Kim #define CPC(n) (_CPC + (n)*0x8) 89b7d861d9SBoojin Kim 90b7d861d9SBoojin Kim #define _SA 0x400 91b7d861d9SBoojin Kim #define SA(n) (_SA + (n)*0x20) 92b7d861d9SBoojin Kim 93b7d861d9SBoojin Kim #define _DA 0x404 94b7d861d9SBoojin Kim #define DA(n) (_DA + (n)*0x20) 95b7d861d9SBoojin Kim 96b7d861d9SBoojin Kim #define _CC 0x408 97b7d861d9SBoojin Kim #define CC(n) (_CC + (n)*0x20) 98b7d861d9SBoojin Kim 99b7d861d9SBoojin Kim #define CC_SRCINC (1 << 0) 100b7d861d9SBoojin Kim #define CC_DSTINC (1 << 14) 101b7d861d9SBoojin Kim #define CC_SRCPRI (1 << 8) 102b7d861d9SBoojin Kim #define CC_DSTPRI (1 << 22) 103b7d861d9SBoojin Kim #define CC_SRCNS (1 << 9) 104b7d861d9SBoojin Kim #define CC_DSTNS (1 << 23) 105b7d861d9SBoojin Kim #define CC_SRCIA (1 << 10) 106b7d861d9SBoojin Kim #define CC_DSTIA (1 << 24) 107b7d861d9SBoojin Kim #define CC_SRCBRSTLEN_SHFT 4 108b7d861d9SBoojin Kim #define CC_DSTBRSTLEN_SHFT 18 109b7d861d9SBoojin Kim #define CC_SRCBRSTSIZE_SHFT 1 110b7d861d9SBoojin Kim #define CC_DSTBRSTSIZE_SHFT 15 111b7d861d9SBoojin Kim #define CC_SRCCCTRL_SHFT 11 112b7d861d9SBoojin Kim #define CC_SRCCCTRL_MASK 0x7 113b7d861d9SBoojin Kim #define CC_DSTCCTRL_SHFT 25 114b7d861d9SBoojin Kim #define CC_DRCCCTRL_MASK 0x7 115b7d861d9SBoojin Kim #define CC_SWAP_SHFT 28 116b7d861d9SBoojin Kim 117b7d861d9SBoojin Kim #define _LC0 0x40c 118b7d861d9SBoojin Kim #define LC0(n) (_LC0 + (n)*0x20) 119b7d861d9SBoojin Kim 120b7d861d9SBoojin Kim #define _LC1 0x410 121b7d861d9SBoojin Kim #define LC1(n) (_LC1 + (n)*0x20) 122b7d861d9SBoojin Kim 123b7d861d9SBoojin Kim #define DBGSTATUS 0xd00 124b7d861d9SBoojin Kim #define DBG_BUSY (1 << 0) 125b7d861d9SBoojin Kim 126b7d861d9SBoojin Kim #define DBGCMD 0xd04 127b7d861d9SBoojin Kim #define DBGINST0 0xd08 128b7d861d9SBoojin Kim #define DBGINST1 0xd0c 129b7d861d9SBoojin Kim 130b7d861d9SBoojin Kim #define CR0 0xe00 131b7d861d9SBoojin Kim #define CR1 0xe04 132b7d861d9SBoojin Kim #define CR2 0xe08 133b7d861d9SBoojin Kim #define CR3 0xe0c 134b7d861d9SBoojin Kim #define CR4 0xe10 135b7d861d9SBoojin Kim #define CRD 0xe14 136b7d861d9SBoojin Kim 137b7d861d9SBoojin Kim #define PERIPH_ID 0xfe0 1383ecf51a4SBoojin Kim #define PERIPH_REV_SHIFT 20 1393ecf51a4SBoojin Kim #define PERIPH_REV_MASK 0xf 1403ecf51a4SBoojin Kim #define PERIPH_REV_R0P0 0 1413ecf51a4SBoojin Kim #define PERIPH_REV_R1P0 1 1423ecf51a4SBoojin Kim #define PERIPH_REV_R1P1 2 143b7d861d9SBoojin Kim 144b7d861d9SBoojin Kim #define CR0_PERIPH_REQ_SET (1 << 0) 145b7d861d9SBoojin Kim #define CR0_BOOT_EN_SET (1 << 1) 146b7d861d9SBoojin Kim #define CR0_BOOT_MAN_NS (1 << 2) 147b7d861d9SBoojin Kim #define CR0_NUM_CHANS_SHIFT 4 148b7d861d9SBoojin Kim #define CR0_NUM_CHANS_MASK 0x7 149b7d861d9SBoojin Kim #define CR0_NUM_PERIPH_SHIFT 12 150b7d861d9SBoojin Kim #define CR0_NUM_PERIPH_MASK 0x1f 151b7d861d9SBoojin Kim #define CR0_NUM_EVENTS_SHIFT 17 152b7d861d9SBoojin Kim #define CR0_NUM_EVENTS_MASK 0x1f 153b7d861d9SBoojin Kim 154b7d861d9SBoojin Kim #define CR1_ICACHE_LEN_SHIFT 0 155b7d861d9SBoojin Kim #define CR1_ICACHE_LEN_MASK 0x7 156b7d861d9SBoojin Kim #define CR1_NUM_ICACHELINES_SHIFT 4 157b7d861d9SBoojin Kim #define CR1_NUM_ICACHELINES_MASK 0xf 158b7d861d9SBoojin Kim 159b7d861d9SBoojin Kim #define CRD_DATA_WIDTH_SHIFT 0 160b7d861d9SBoojin Kim #define CRD_DATA_WIDTH_MASK 0x7 161b7d861d9SBoojin Kim #define CRD_WR_CAP_SHIFT 4 162b7d861d9SBoojin Kim #define CRD_WR_CAP_MASK 0x7 163b7d861d9SBoojin Kim #define CRD_WR_Q_DEP_SHIFT 8 164b7d861d9SBoojin Kim #define CRD_WR_Q_DEP_MASK 0xf 165b7d861d9SBoojin Kim #define CRD_RD_CAP_SHIFT 12 166b7d861d9SBoojin Kim #define CRD_RD_CAP_MASK 0x7 167b7d861d9SBoojin Kim #define CRD_RD_Q_DEP_SHIFT 16 168b7d861d9SBoojin Kim #define CRD_RD_Q_DEP_MASK 0xf 169b7d861d9SBoojin Kim #define CRD_DATA_BUFF_SHIFT 20 170b7d861d9SBoojin Kim #define CRD_DATA_BUFF_MASK 0x3ff 171b7d861d9SBoojin Kim 172b7d861d9SBoojin Kim #define PART 0x330 173b7d861d9SBoojin Kim #define DESIGNER 0x41 174b7d861d9SBoojin Kim #define REVISION 0x0 175b7d861d9SBoojin Kim #define INTEG_CFG 0x0 176b7d861d9SBoojin Kim #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) 177b7d861d9SBoojin Kim 178b7d861d9SBoojin Kim #define PL330_STATE_STOPPED (1 << 0) 179b7d861d9SBoojin Kim #define PL330_STATE_EXECUTING (1 << 1) 180b7d861d9SBoojin Kim #define PL330_STATE_WFE (1 << 2) 181b7d861d9SBoojin Kim #define PL330_STATE_FAULTING (1 << 3) 182b7d861d9SBoojin Kim #define PL330_STATE_COMPLETING (1 << 4) 183b7d861d9SBoojin Kim #define PL330_STATE_WFP (1 << 5) 184b7d861d9SBoojin Kim #define PL330_STATE_KILLING (1 << 6) 185b7d861d9SBoojin Kim #define PL330_STATE_FAULT_COMPLETING (1 << 7) 186b7d861d9SBoojin Kim #define PL330_STATE_CACHEMISS (1 << 8) 187b7d861d9SBoojin Kim #define PL330_STATE_UPDTPC (1 << 9) 188b7d861d9SBoojin Kim #define PL330_STATE_ATBARRIER (1 << 10) 189b7d861d9SBoojin Kim #define PL330_STATE_QUEUEBUSY (1 << 11) 190b7d861d9SBoojin Kim #define PL330_STATE_INVALID (1 << 15) 191b7d861d9SBoojin Kim 192b7d861d9SBoojin Kim #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ 193b7d861d9SBoojin Kim | PL330_STATE_WFE | PL330_STATE_FAULTING) 194b7d861d9SBoojin Kim 195b7d861d9SBoojin Kim #define CMD_DMAADDH 0x54 196b7d861d9SBoojin Kim #define CMD_DMAEND 0x00 197b7d861d9SBoojin Kim #define CMD_DMAFLUSHP 0x35 198b7d861d9SBoojin Kim #define CMD_DMAGO 0xa0 199b7d861d9SBoojin Kim #define CMD_DMALD 0x04 200b7d861d9SBoojin Kim #define CMD_DMALDP 0x25 201b7d861d9SBoojin Kim #define CMD_DMALP 0x20 202b7d861d9SBoojin Kim #define CMD_DMALPEND 0x28 203b7d861d9SBoojin Kim #define CMD_DMAKILL 0x01 204b7d861d9SBoojin Kim #define CMD_DMAMOV 0xbc 205b7d861d9SBoojin Kim #define CMD_DMANOP 0x18 206b7d861d9SBoojin Kim #define CMD_DMARMB 0x12 207b7d861d9SBoojin Kim #define CMD_DMASEV 0x34 208b7d861d9SBoojin Kim #define CMD_DMAST 0x08 209b7d861d9SBoojin Kim #define CMD_DMASTP 0x29 210b7d861d9SBoojin Kim #define CMD_DMASTZ 0x0c 211b7d861d9SBoojin Kim #define CMD_DMAWFE 0x36 212b7d861d9SBoojin Kim #define CMD_DMAWFP 0x30 213b7d861d9SBoojin Kim #define CMD_DMAWMB 0x13 214b7d861d9SBoojin Kim 215b7d861d9SBoojin Kim #define SZ_DMAADDH 3 216b7d861d9SBoojin Kim #define SZ_DMAEND 1 217b7d861d9SBoojin Kim #define SZ_DMAFLUSHP 2 218b7d861d9SBoojin Kim #define SZ_DMALD 1 219b7d861d9SBoojin Kim #define SZ_DMALDP 2 220b7d861d9SBoojin Kim #define SZ_DMALP 2 221b7d861d9SBoojin Kim #define SZ_DMALPEND 2 222b7d861d9SBoojin Kim #define SZ_DMAKILL 1 223b7d861d9SBoojin Kim #define SZ_DMAMOV 6 224b7d861d9SBoojin Kim #define SZ_DMANOP 1 225b7d861d9SBoojin Kim #define SZ_DMARMB 1 226b7d861d9SBoojin Kim #define SZ_DMASEV 2 227b7d861d9SBoojin Kim #define SZ_DMAST 1 228b7d861d9SBoojin Kim #define SZ_DMASTP 2 229b7d861d9SBoojin Kim #define SZ_DMASTZ 1 230b7d861d9SBoojin Kim #define SZ_DMAWFE 2 231b7d861d9SBoojin Kim #define SZ_DMAWFP 2 232b7d861d9SBoojin Kim #define SZ_DMAWMB 1 233b7d861d9SBoojin Kim #define SZ_DMAGO 6 234b7d861d9SBoojin Kim 235b7d861d9SBoojin Kim #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) 236b7d861d9SBoojin Kim #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) 237b7d861d9SBoojin Kim 238b7d861d9SBoojin Kim #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) 239b7d861d9SBoojin Kim #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) 240b7d861d9SBoojin Kim 241b7d861d9SBoojin Kim /* 242b7d861d9SBoojin Kim * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req 243b7d861d9SBoojin Kim * at 1byte/burst for P<->M and M<->M respectively. 244b7d861d9SBoojin Kim * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req 245b7d861d9SBoojin Kim * should be enough for P<->M and M<->M respectively. 246b7d861d9SBoojin Kim */ 247b7d861d9SBoojin Kim #define MCODE_BUFF_PER_REQ 256 248b7d861d9SBoojin Kim 249b7d861d9SBoojin Kim /* Use this _only_ to wait on transient states */ 250b7d861d9SBoojin Kim #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); 251b7d861d9SBoojin Kim 252b7d861d9SBoojin Kim #ifdef PL330_DEBUG_MCGEN 253b7d861d9SBoojin Kim static unsigned cmd_line; 254b7d861d9SBoojin Kim #define PL330_DBGCMD_DUMP(off, x...) do { \ 255b7d861d9SBoojin Kim printk("%x:", cmd_line); \ 256b7d861d9SBoojin Kim printk(x); \ 257b7d861d9SBoojin Kim cmd_line += off; \ 258b7d861d9SBoojin Kim } while (0) 259b7d861d9SBoojin Kim #define PL330_DBGMC_START(addr) (cmd_line = addr) 260b7d861d9SBoojin Kim #else 261b7d861d9SBoojin Kim #define PL330_DBGCMD_DUMP(off, x...) do {} while (0) 262b7d861d9SBoojin Kim #define PL330_DBGMC_START(addr) do {} while (0) 263b7d861d9SBoojin Kim #endif 264b7d861d9SBoojin Kim 265b7d861d9SBoojin Kim /* The number of default descriptors */ 266d2ebfb33SRussell King - ARM Linux 267b3040e40SJassi Brar #define NR_DEFAULT_DESC 16 268b3040e40SJassi Brar 269ae43b328SKrzysztof Kozlowski /* Delay for runtime PM autosuspend, ms */ 270ae43b328SKrzysztof Kozlowski #define PL330_AUTOSUSPEND_DELAY 20 271ae43b328SKrzysztof Kozlowski 272b7d861d9SBoojin Kim /* Populated by the PL330 core driver for DMA API driver's info */ 273b7d861d9SBoojin Kim struct pl330_config { 274b7d861d9SBoojin Kim u32 periph_id; 275b7d861d9SBoojin Kim #define DMAC_MODE_NS (1 << 0) 276b7d861d9SBoojin Kim unsigned int mode; 277b7d861d9SBoojin Kim unsigned int data_bus_width:10; /* In number of bits */ 2781f0a5cbfSLiviu Dudau unsigned int data_buf_dep:11; 279b7d861d9SBoojin Kim unsigned int num_chan:4; 280b7d861d9SBoojin Kim unsigned int num_peri:6; 281b7d861d9SBoojin Kim u32 peri_ns; 282b7d861d9SBoojin Kim unsigned int num_events:6; 283b7d861d9SBoojin Kim u32 irq_ns; 284b7d861d9SBoojin Kim }; 285b7d861d9SBoojin Kim 286b7d861d9SBoojin Kim /** 287b7d861d9SBoojin Kim * Request Configuration. 288b7d861d9SBoojin Kim * The PL330 core does not modify this and uses the last 289b7d861d9SBoojin Kim * working configuration if the request doesn't provide any. 290b7d861d9SBoojin Kim * 291b7d861d9SBoojin Kim * The Client may want to provide this info only for the 292b7d861d9SBoojin Kim * first request and a request with new settings. 293b7d861d9SBoojin Kim */ 294b7d861d9SBoojin Kim struct pl330_reqcfg { 295b7d861d9SBoojin Kim /* Address Incrementing */ 296b7d861d9SBoojin Kim unsigned dst_inc:1; 297b7d861d9SBoojin Kim unsigned src_inc:1; 298b7d861d9SBoojin Kim 299b7d861d9SBoojin Kim /* 300b7d861d9SBoojin Kim * For now, the SRC & DST protection levels 301b7d861d9SBoojin Kim * and burst size/length are assumed same. 302b7d861d9SBoojin Kim */ 303b7d861d9SBoojin Kim bool nonsecure; 304b7d861d9SBoojin Kim bool privileged; 305b7d861d9SBoojin Kim bool insnaccess; 306b7d861d9SBoojin Kim unsigned brst_len:5; 307b7d861d9SBoojin Kim unsigned brst_size:3; /* in power of 2 */ 308b7d861d9SBoojin Kim 309f0564c7eSLars-Peter Clausen enum pl330_cachectrl dcctl; 310f0564c7eSLars-Peter Clausen enum pl330_cachectrl scctl; 311b7d861d9SBoojin Kim enum pl330_byteswap swap; 3123ecf51a4SBoojin Kim struct pl330_config *pcfg; 313b7d861d9SBoojin Kim }; 314b7d861d9SBoojin Kim 315b7d861d9SBoojin Kim /* 316b7d861d9SBoojin Kim * One cycle of DMAC operation. 317b7d861d9SBoojin Kim * There may be more than one xfer in a request. 318b7d861d9SBoojin Kim */ 319b7d861d9SBoojin Kim struct pl330_xfer { 320b7d861d9SBoojin Kim u32 src_addr; 321b7d861d9SBoojin Kim u32 dst_addr; 322b7d861d9SBoojin Kim /* Size to xfer */ 323b7d861d9SBoojin Kim u32 bytes; 324b7d861d9SBoojin Kim }; 325b7d861d9SBoojin Kim 326b7d861d9SBoojin Kim /* The xfer callbacks are made with one of these arguments. */ 327b7d861d9SBoojin Kim enum pl330_op_err { 328b7d861d9SBoojin Kim /* The all xfers in the request were success. */ 329b7d861d9SBoojin Kim PL330_ERR_NONE, 330b7d861d9SBoojin Kim /* If req aborted due to global error. */ 331b7d861d9SBoojin Kim PL330_ERR_ABORT, 332b7d861d9SBoojin Kim /* If req failed due to problem with Channel. */ 333b7d861d9SBoojin Kim PL330_ERR_FAIL, 334b7d861d9SBoojin Kim }; 335b7d861d9SBoojin Kim 336b7d861d9SBoojin Kim enum dmamov_dst { 337b7d861d9SBoojin Kim SAR = 0, 338b7d861d9SBoojin Kim CCR, 339b7d861d9SBoojin Kim DAR, 340b7d861d9SBoojin Kim }; 341b7d861d9SBoojin Kim 342b7d861d9SBoojin Kim enum pl330_dst { 343b7d861d9SBoojin Kim SRC = 0, 344b7d861d9SBoojin Kim DST, 345b7d861d9SBoojin Kim }; 346b7d861d9SBoojin Kim 347b7d861d9SBoojin Kim enum pl330_cond { 348b7d861d9SBoojin Kim SINGLE, 349b7d861d9SBoojin Kim BURST, 350b7d861d9SBoojin Kim ALWAYS, 351b7d861d9SBoojin Kim }; 352b7d861d9SBoojin Kim 3539dc5a315SLars-Peter Clausen struct dma_pl330_desc; 3549dc5a315SLars-Peter Clausen 355b7d861d9SBoojin Kim struct _pl330_req { 356b7d861d9SBoojin Kim u32 mc_bus; 357b7d861d9SBoojin Kim void *mc_cpu; 3589dc5a315SLars-Peter Clausen struct dma_pl330_desc *desc; 359b7d861d9SBoojin Kim }; 360b7d861d9SBoojin Kim 361b7d861d9SBoojin Kim /* ToBeDone for tasklet */ 362b7d861d9SBoojin Kim struct _pl330_tbd { 363b7d861d9SBoojin Kim bool reset_dmac; 364b7d861d9SBoojin Kim bool reset_mngr; 365b7d861d9SBoojin Kim u8 reset_chan; 366b7d861d9SBoojin Kim }; 367b7d861d9SBoojin Kim 368b7d861d9SBoojin Kim /* A DMAC Thread */ 369b7d861d9SBoojin Kim struct pl330_thread { 370b7d861d9SBoojin Kim u8 id; 371b7d861d9SBoojin Kim int ev; 372b7d861d9SBoojin Kim /* If the channel is not yet acquired by any client */ 373b7d861d9SBoojin Kim bool free; 374b7d861d9SBoojin Kim /* Parent DMAC */ 375b7d861d9SBoojin Kim struct pl330_dmac *dmac; 376b7d861d9SBoojin Kim /* Only two at a time */ 377b7d861d9SBoojin Kim struct _pl330_req req[2]; 378b7d861d9SBoojin Kim /* Index of the last enqueued request */ 379b7d861d9SBoojin Kim unsigned lstenq; 380b7d861d9SBoojin Kim /* Index of the last submitted request or -1 if the DMA is stopped */ 381b7d861d9SBoojin Kim int req_running; 382b7d861d9SBoojin Kim }; 383b7d861d9SBoojin Kim 384b7d861d9SBoojin Kim enum pl330_dmac_state { 385b7d861d9SBoojin Kim UNINIT, 386b7d861d9SBoojin Kim INIT, 387b7d861d9SBoojin Kim DYING, 388b7d861d9SBoojin Kim }; 389b7d861d9SBoojin Kim 390b3040e40SJassi Brar enum desc_status { 391b3040e40SJassi Brar /* In the DMAC pool */ 392b3040e40SJassi Brar FREE, 393b3040e40SJassi Brar /* 394d73111c6SMasanari Iida * Allocated to some channel during prep_xxx 395b3040e40SJassi Brar * Also may be sitting on the work_list. 396b3040e40SJassi Brar */ 397b3040e40SJassi Brar PREP, 398b3040e40SJassi Brar /* 399b3040e40SJassi Brar * Sitting on the work_list and already submitted 400b3040e40SJassi Brar * to the PL330 core. Not more than two descriptors 401b3040e40SJassi Brar * of a channel can be BUSY at any time. 402b3040e40SJassi Brar */ 403b3040e40SJassi Brar BUSY, 404b3040e40SJassi Brar /* 405b3040e40SJassi Brar * Sitting on the channel work_list but xfer done 406b3040e40SJassi Brar * by PL330 core 407b3040e40SJassi Brar */ 408b3040e40SJassi Brar DONE, 409b3040e40SJassi Brar }; 410b3040e40SJassi Brar 411b3040e40SJassi Brar struct dma_pl330_chan { 412b3040e40SJassi Brar /* Schedule desc completion */ 413b3040e40SJassi Brar struct tasklet_struct task; 414b3040e40SJassi Brar 415b3040e40SJassi Brar /* DMA-Engine Channel */ 416b3040e40SJassi Brar struct dma_chan chan; 417b3040e40SJassi Brar 41804abf5daSLars-Peter Clausen /* List of submitted descriptors */ 41904abf5daSLars-Peter Clausen struct list_head submitted_list; 42004abf5daSLars-Peter Clausen /* List of issued descriptors */ 421b3040e40SJassi Brar struct list_head work_list; 42239ff8613SLars-Peter Clausen /* List of completed descriptors */ 42339ff8613SLars-Peter Clausen struct list_head completed_list; 424b3040e40SJassi Brar 425b3040e40SJassi Brar /* Pointer to the DMAC that manages this channel, 426b3040e40SJassi Brar * NULL if the channel is available to be acquired. 427b3040e40SJassi Brar * As the parent, this DMAC also provides descriptors 428b3040e40SJassi Brar * to the channel. 429b3040e40SJassi Brar */ 430f6f2421cSLars-Peter Clausen struct pl330_dmac *dmac; 431b3040e40SJassi Brar 432b3040e40SJassi Brar /* To protect channel manipulation */ 433b3040e40SJassi Brar spinlock_t lock; 434b3040e40SJassi Brar 43565ad6060SLars-Peter Clausen /* 43665ad6060SLars-Peter Clausen * Hardware channel thread of PL330 DMAC. NULL if the channel is 43765ad6060SLars-Peter Clausen * available. 438b3040e40SJassi Brar */ 43965ad6060SLars-Peter Clausen struct pl330_thread *thread; 4401b9bb715SBoojin Kim 4411b9bb715SBoojin Kim /* For D-to-M and M-to-D channels */ 4421b9bb715SBoojin Kim int burst_sz; /* the peripheral fifo width */ 4431d0c1d60SBoojin Kim int burst_len; /* the number of burst */ 4441b9bb715SBoojin Kim dma_addr_t fifo_addr; 44542bc9cf4SBoojin Kim 44642bc9cf4SBoojin Kim /* for cyclic capability */ 44742bc9cf4SBoojin Kim bool cyclic; 448b3040e40SJassi Brar }; 449b3040e40SJassi Brar 450f6f2421cSLars-Peter Clausen struct pl330_dmac { 451b3040e40SJassi Brar /* DMA-Engine Device */ 452b3040e40SJassi Brar struct dma_device ddma; 453b3040e40SJassi Brar 454b714b84eSLars-Peter Clausen /* Holds info about sg limitations */ 455b714b84eSLars-Peter Clausen struct device_dma_parameters dma_parms; 456b714b84eSLars-Peter Clausen 457b3040e40SJassi Brar /* Pool of descriptors available for the DMAC's channels */ 458b3040e40SJassi Brar struct list_head desc_pool; 459b3040e40SJassi Brar /* To protect desc_pool manipulation */ 460b3040e40SJassi Brar spinlock_t pool_lock; 461b3040e40SJassi Brar 462f6f2421cSLars-Peter Clausen /* Size of MicroCode buffers for each channel. */ 463f6f2421cSLars-Peter Clausen unsigned mcbufsz; 464f6f2421cSLars-Peter Clausen /* ioremap'ed address of PL330 registers. */ 465f6f2421cSLars-Peter Clausen void __iomem *base; 466f6f2421cSLars-Peter Clausen /* Populated by the PL330 core driver during pl330_add */ 467f6f2421cSLars-Peter Clausen struct pl330_config pcfg; 468f6f2421cSLars-Peter Clausen 469f6f2421cSLars-Peter Clausen spinlock_t lock; 470f6f2421cSLars-Peter Clausen /* Maximum possible events/irqs */ 471f6f2421cSLars-Peter Clausen int events[32]; 472f6f2421cSLars-Peter Clausen /* BUS address of MicroCode buffer */ 473f6f2421cSLars-Peter Clausen dma_addr_t mcode_bus; 474f6f2421cSLars-Peter Clausen /* CPU address of MicroCode buffer */ 475f6f2421cSLars-Peter Clausen void *mcode_cpu; 476f6f2421cSLars-Peter Clausen /* List of all Channel threads */ 477f6f2421cSLars-Peter Clausen struct pl330_thread *channels; 478f6f2421cSLars-Peter Clausen /* Pointer to the MANAGER thread */ 479f6f2421cSLars-Peter Clausen struct pl330_thread *manager; 480f6f2421cSLars-Peter Clausen /* To handle bad news in interrupt */ 481f6f2421cSLars-Peter Clausen struct tasklet_struct tasks; 482f6f2421cSLars-Peter Clausen struct _pl330_tbd dmac_tbd; 483f6f2421cSLars-Peter Clausen /* State of DMAC operation */ 484f6f2421cSLars-Peter Clausen enum pl330_dmac_state state; 485f6f2421cSLars-Peter Clausen /* Holds list of reqs with due callbacks */ 486f6f2421cSLars-Peter Clausen struct list_head req_done; 487f6f2421cSLars-Peter Clausen 488b3040e40SJassi Brar /* Peripheral channels connected to this DMAC */ 48970cbb163SLars-Peter Clausen unsigned int num_peripherals; 4904e0e6109SRob Herring struct dma_pl330_chan *peripherals; /* keep at end */ 491b3040e40SJassi Brar }; 492b3040e40SJassi Brar 493b3040e40SJassi Brar struct dma_pl330_desc { 494b3040e40SJassi Brar /* To attach to a queue as child */ 495b3040e40SJassi Brar struct list_head node; 496b3040e40SJassi Brar 497b3040e40SJassi Brar /* Descriptor for the DMA Engine API */ 498b3040e40SJassi Brar struct dma_async_tx_descriptor txd; 499b3040e40SJassi Brar 500b3040e40SJassi Brar /* Xfer for PL330 core */ 501b3040e40SJassi Brar struct pl330_xfer px; 502b3040e40SJassi Brar 503b3040e40SJassi Brar struct pl330_reqcfg rqcfg; 504b3040e40SJassi Brar 505b3040e40SJassi Brar enum desc_status status; 506b3040e40SJassi Brar 507aee4d1faSRobert Baldyga int bytes_requested; 508aee4d1faSRobert Baldyga bool last; 509aee4d1faSRobert Baldyga 510b3040e40SJassi Brar /* The channel which currently holds this desc */ 511b3040e40SJassi Brar struct dma_pl330_chan *pchan; 5129dc5a315SLars-Peter Clausen 5139dc5a315SLars-Peter Clausen enum dma_transfer_direction rqtype; 5149dc5a315SLars-Peter Clausen /* Index of peripheral for the xfer. */ 5159dc5a315SLars-Peter Clausen unsigned peri:5; 5169dc5a315SLars-Peter Clausen /* Hook to attach to DMAC's list of reqs with due callback */ 5179dc5a315SLars-Peter Clausen struct list_head rqd; 5189dc5a315SLars-Peter Clausen }; 5199dc5a315SLars-Peter Clausen 5209dc5a315SLars-Peter Clausen struct _xfer_spec { 5219dc5a315SLars-Peter Clausen u32 ccr; 5229dc5a315SLars-Peter Clausen struct dma_pl330_desc *desc; 523b3040e40SJassi Brar }; 524b3040e40SJassi Brar 525b7d861d9SBoojin Kim static inline bool _queue_empty(struct pl330_thread *thrd) 526b7d861d9SBoojin Kim { 5278ed30a14SLars-Peter Clausen return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL; 528b7d861d9SBoojin Kim } 529b7d861d9SBoojin Kim 530b7d861d9SBoojin Kim static inline bool _queue_full(struct pl330_thread *thrd) 531b7d861d9SBoojin Kim { 5328ed30a14SLars-Peter Clausen return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL; 533b7d861d9SBoojin Kim } 534b7d861d9SBoojin Kim 535b7d861d9SBoojin Kim static inline bool is_manager(struct pl330_thread *thrd) 536b7d861d9SBoojin Kim { 537fbbcd9beSLars-Peter Clausen return thrd->dmac->manager == thrd; 538b7d861d9SBoojin Kim } 539b7d861d9SBoojin Kim 540b7d861d9SBoojin Kim /* If manager of the thread is in Non-Secure mode */ 541b7d861d9SBoojin Kim static inline bool _manager_ns(struct pl330_thread *thrd) 542b7d861d9SBoojin Kim { 543f6f2421cSLars-Peter Clausen return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false; 544b7d861d9SBoojin Kim } 545b7d861d9SBoojin Kim 5463ecf51a4SBoojin Kim static inline u32 get_revision(u32 periph_id) 5473ecf51a4SBoojin Kim { 5483ecf51a4SBoojin Kim return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; 5493ecf51a4SBoojin Kim } 5503ecf51a4SBoojin Kim 551b7d861d9SBoojin Kim static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[], 552b7d861d9SBoojin Kim enum pl330_dst da, u16 val) 553b7d861d9SBoojin Kim { 554b7d861d9SBoojin Kim if (dry_run) 555b7d861d9SBoojin Kim return SZ_DMAADDH; 556b7d861d9SBoojin Kim 557b7d861d9SBoojin Kim buf[0] = CMD_DMAADDH; 558b7d861d9SBoojin Kim buf[0] |= (da << 1); 5593a2307f7SBen Dooks *((__le16 *)&buf[1]) = cpu_to_le16(val); 560b7d861d9SBoojin Kim 561b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n", 562b7d861d9SBoojin Kim da == 1 ? "DA" : "SA", val); 563b7d861d9SBoojin Kim 564b7d861d9SBoojin Kim return SZ_DMAADDH; 565b7d861d9SBoojin Kim } 566b7d861d9SBoojin Kim 567b7d861d9SBoojin Kim static inline u32 _emit_END(unsigned dry_run, u8 buf[]) 568b7d861d9SBoojin Kim { 569b7d861d9SBoojin Kim if (dry_run) 570b7d861d9SBoojin Kim return SZ_DMAEND; 571b7d861d9SBoojin Kim 572b7d861d9SBoojin Kim buf[0] = CMD_DMAEND; 573b7d861d9SBoojin Kim 574b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); 575b7d861d9SBoojin Kim 576b7d861d9SBoojin Kim return SZ_DMAEND; 577b7d861d9SBoojin Kim } 578b7d861d9SBoojin Kim 579b7d861d9SBoojin Kim static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) 580b7d861d9SBoojin Kim { 581b7d861d9SBoojin Kim if (dry_run) 582b7d861d9SBoojin Kim return SZ_DMAFLUSHP; 583b7d861d9SBoojin Kim 584b7d861d9SBoojin Kim buf[0] = CMD_DMAFLUSHP; 585b7d861d9SBoojin Kim 586b7d861d9SBoojin Kim peri &= 0x1f; 587b7d861d9SBoojin Kim peri <<= 3; 588b7d861d9SBoojin Kim buf[1] = peri; 589b7d861d9SBoojin Kim 590b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); 591b7d861d9SBoojin Kim 592b7d861d9SBoojin Kim return SZ_DMAFLUSHP; 593b7d861d9SBoojin Kim } 594b7d861d9SBoojin Kim 595b7d861d9SBoojin Kim static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) 596b7d861d9SBoojin Kim { 597b7d861d9SBoojin Kim if (dry_run) 598b7d861d9SBoojin Kim return SZ_DMALD; 599b7d861d9SBoojin Kim 600b7d861d9SBoojin Kim buf[0] = CMD_DMALD; 601b7d861d9SBoojin Kim 602b7d861d9SBoojin Kim if (cond == SINGLE) 603b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 604b7d861d9SBoojin Kim else if (cond == BURST) 605b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (1 << 0); 606b7d861d9SBoojin Kim 607b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", 608b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); 609b7d861d9SBoojin Kim 610b7d861d9SBoojin Kim return SZ_DMALD; 611b7d861d9SBoojin Kim } 612b7d861d9SBoojin Kim 613b7d861d9SBoojin Kim static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], 614b7d861d9SBoojin Kim enum pl330_cond cond, u8 peri) 615b7d861d9SBoojin Kim { 616b7d861d9SBoojin Kim if (dry_run) 617b7d861d9SBoojin Kim return SZ_DMALDP; 618b7d861d9SBoojin Kim 619b7d861d9SBoojin Kim buf[0] = CMD_DMALDP; 620b7d861d9SBoojin Kim 621b7d861d9SBoojin Kim if (cond == BURST) 622b7d861d9SBoojin Kim buf[0] |= (1 << 1); 623b7d861d9SBoojin Kim 624b7d861d9SBoojin Kim peri &= 0x1f; 625b7d861d9SBoojin Kim peri <<= 3; 626b7d861d9SBoojin Kim buf[1] = peri; 627b7d861d9SBoojin Kim 628b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", 629b7d861d9SBoojin Kim cond == SINGLE ? 'S' : 'B', peri >> 3); 630b7d861d9SBoojin Kim 631b7d861d9SBoojin Kim return SZ_DMALDP; 632b7d861d9SBoojin Kim } 633b7d861d9SBoojin Kim 634b7d861d9SBoojin Kim static inline u32 _emit_LP(unsigned dry_run, u8 buf[], 635b7d861d9SBoojin Kim unsigned loop, u8 cnt) 636b7d861d9SBoojin Kim { 637b7d861d9SBoojin Kim if (dry_run) 638b7d861d9SBoojin Kim return SZ_DMALP; 639b7d861d9SBoojin Kim 640b7d861d9SBoojin Kim buf[0] = CMD_DMALP; 641b7d861d9SBoojin Kim 642b7d861d9SBoojin Kim if (loop) 643b7d861d9SBoojin Kim buf[0] |= (1 << 1); 644b7d861d9SBoojin Kim 645b7d861d9SBoojin Kim cnt--; /* DMAC increments by 1 internally */ 646b7d861d9SBoojin Kim buf[1] = cnt; 647b7d861d9SBoojin Kim 648b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); 649b7d861d9SBoojin Kim 650b7d861d9SBoojin Kim return SZ_DMALP; 651b7d861d9SBoojin Kim } 652b7d861d9SBoojin Kim 653b7d861d9SBoojin Kim struct _arg_LPEND { 654b7d861d9SBoojin Kim enum pl330_cond cond; 655b7d861d9SBoojin Kim bool forever; 656b7d861d9SBoojin Kim unsigned loop; 657b7d861d9SBoojin Kim u8 bjump; 658b7d861d9SBoojin Kim }; 659b7d861d9SBoojin Kim 660b7d861d9SBoojin Kim static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], 661b7d861d9SBoojin Kim const struct _arg_LPEND *arg) 662b7d861d9SBoojin Kim { 663b7d861d9SBoojin Kim enum pl330_cond cond = arg->cond; 664b7d861d9SBoojin Kim bool forever = arg->forever; 665b7d861d9SBoojin Kim unsigned loop = arg->loop; 666b7d861d9SBoojin Kim u8 bjump = arg->bjump; 667b7d861d9SBoojin Kim 668b7d861d9SBoojin Kim if (dry_run) 669b7d861d9SBoojin Kim return SZ_DMALPEND; 670b7d861d9SBoojin Kim 671b7d861d9SBoojin Kim buf[0] = CMD_DMALPEND; 672b7d861d9SBoojin Kim 673b7d861d9SBoojin Kim if (loop) 674b7d861d9SBoojin Kim buf[0] |= (1 << 2); 675b7d861d9SBoojin Kim 676b7d861d9SBoojin Kim if (!forever) 677b7d861d9SBoojin Kim buf[0] |= (1 << 4); 678b7d861d9SBoojin Kim 679b7d861d9SBoojin Kim if (cond == SINGLE) 680b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 681b7d861d9SBoojin Kim else if (cond == BURST) 682b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (1 << 0); 683b7d861d9SBoojin Kim 684b7d861d9SBoojin Kim buf[1] = bjump; 685b7d861d9SBoojin Kim 686b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", 687b7d861d9SBoojin Kim forever ? "FE" : "END", 688b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), 689b7d861d9SBoojin Kim loop ? '1' : '0', 690b7d861d9SBoojin Kim bjump); 691b7d861d9SBoojin Kim 692b7d861d9SBoojin Kim return SZ_DMALPEND; 693b7d861d9SBoojin Kim } 694b7d861d9SBoojin Kim 695b7d861d9SBoojin Kim static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) 696b7d861d9SBoojin Kim { 697b7d861d9SBoojin Kim if (dry_run) 698b7d861d9SBoojin Kim return SZ_DMAKILL; 699b7d861d9SBoojin Kim 700b7d861d9SBoojin Kim buf[0] = CMD_DMAKILL; 701b7d861d9SBoojin Kim 702b7d861d9SBoojin Kim return SZ_DMAKILL; 703b7d861d9SBoojin Kim } 704b7d861d9SBoojin Kim 705b7d861d9SBoojin Kim static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], 706b7d861d9SBoojin Kim enum dmamov_dst dst, u32 val) 707b7d861d9SBoojin Kim { 708b7d861d9SBoojin Kim if (dry_run) 709b7d861d9SBoojin Kim return SZ_DMAMOV; 710b7d861d9SBoojin Kim 711b7d861d9SBoojin Kim buf[0] = CMD_DMAMOV; 712b7d861d9SBoojin Kim buf[1] = dst; 7133a2307f7SBen Dooks *((__le32 *)&buf[2]) = cpu_to_le32(val); 714b7d861d9SBoojin Kim 715b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", 716b7d861d9SBoojin Kim dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); 717b7d861d9SBoojin Kim 718b7d861d9SBoojin Kim return SZ_DMAMOV; 719b7d861d9SBoojin Kim } 720b7d861d9SBoojin Kim 721b7d861d9SBoojin Kim static inline u32 _emit_NOP(unsigned dry_run, u8 buf[]) 722b7d861d9SBoojin Kim { 723b7d861d9SBoojin Kim if (dry_run) 724b7d861d9SBoojin Kim return SZ_DMANOP; 725b7d861d9SBoojin Kim 726b7d861d9SBoojin Kim buf[0] = CMD_DMANOP; 727b7d861d9SBoojin Kim 728b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n"); 729b7d861d9SBoojin Kim 730b7d861d9SBoojin Kim return SZ_DMANOP; 731b7d861d9SBoojin Kim } 732b7d861d9SBoojin Kim 733b7d861d9SBoojin Kim static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) 734b7d861d9SBoojin Kim { 735b7d861d9SBoojin Kim if (dry_run) 736b7d861d9SBoojin Kim return SZ_DMARMB; 737b7d861d9SBoojin Kim 738b7d861d9SBoojin Kim buf[0] = CMD_DMARMB; 739b7d861d9SBoojin Kim 740b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); 741b7d861d9SBoojin Kim 742b7d861d9SBoojin Kim return SZ_DMARMB; 743b7d861d9SBoojin Kim } 744b7d861d9SBoojin Kim 745b7d861d9SBoojin Kim static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) 746b7d861d9SBoojin Kim { 747b7d861d9SBoojin Kim if (dry_run) 748b7d861d9SBoojin Kim return SZ_DMASEV; 749b7d861d9SBoojin Kim 750b7d861d9SBoojin Kim buf[0] = CMD_DMASEV; 751b7d861d9SBoojin Kim 752b7d861d9SBoojin Kim ev &= 0x1f; 753b7d861d9SBoojin Kim ev <<= 3; 754b7d861d9SBoojin Kim buf[1] = ev; 755b7d861d9SBoojin Kim 756b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); 757b7d861d9SBoojin Kim 758b7d861d9SBoojin Kim return SZ_DMASEV; 759b7d861d9SBoojin Kim } 760b7d861d9SBoojin Kim 761b7d861d9SBoojin Kim static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) 762b7d861d9SBoojin Kim { 763b7d861d9SBoojin Kim if (dry_run) 764b7d861d9SBoojin Kim return SZ_DMAST; 765b7d861d9SBoojin Kim 766b7d861d9SBoojin Kim buf[0] = CMD_DMAST; 767b7d861d9SBoojin Kim 768b7d861d9SBoojin Kim if (cond == SINGLE) 769b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 770b7d861d9SBoojin Kim else if (cond == BURST) 771b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (1 << 0); 772b7d861d9SBoojin Kim 773b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", 774b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); 775b7d861d9SBoojin Kim 776b7d861d9SBoojin Kim return SZ_DMAST; 777b7d861d9SBoojin Kim } 778b7d861d9SBoojin Kim 779b7d861d9SBoojin Kim static inline u32 _emit_STP(unsigned dry_run, u8 buf[], 780b7d861d9SBoojin Kim enum pl330_cond cond, u8 peri) 781b7d861d9SBoojin Kim { 782b7d861d9SBoojin Kim if (dry_run) 783b7d861d9SBoojin Kim return SZ_DMASTP; 784b7d861d9SBoojin Kim 785b7d861d9SBoojin Kim buf[0] = CMD_DMASTP; 786b7d861d9SBoojin Kim 787b7d861d9SBoojin Kim if (cond == BURST) 788b7d861d9SBoojin Kim buf[0] |= (1 << 1); 789b7d861d9SBoojin Kim 790b7d861d9SBoojin Kim peri &= 0x1f; 791b7d861d9SBoojin Kim peri <<= 3; 792b7d861d9SBoojin Kim buf[1] = peri; 793b7d861d9SBoojin Kim 794b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", 795b7d861d9SBoojin Kim cond == SINGLE ? 'S' : 'B', peri >> 3); 796b7d861d9SBoojin Kim 797b7d861d9SBoojin Kim return SZ_DMASTP; 798b7d861d9SBoojin Kim } 799b7d861d9SBoojin Kim 800b7d861d9SBoojin Kim static inline u32 _emit_STZ(unsigned dry_run, u8 buf[]) 801b7d861d9SBoojin Kim { 802b7d861d9SBoojin Kim if (dry_run) 803b7d861d9SBoojin Kim return SZ_DMASTZ; 804b7d861d9SBoojin Kim 805b7d861d9SBoojin Kim buf[0] = CMD_DMASTZ; 806b7d861d9SBoojin Kim 807b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n"); 808b7d861d9SBoojin Kim 809b7d861d9SBoojin Kim return SZ_DMASTZ; 810b7d861d9SBoojin Kim } 811b7d861d9SBoojin Kim 812b7d861d9SBoojin Kim static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, 813b7d861d9SBoojin Kim unsigned invalidate) 814b7d861d9SBoojin Kim { 815b7d861d9SBoojin Kim if (dry_run) 816b7d861d9SBoojin Kim return SZ_DMAWFE; 817b7d861d9SBoojin Kim 818b7d861d9SBoojin Kim buf[0] = CMD_DMAWFE; 819b7d861d9SBoojin Kim 820b7d861d9SBoojin Kim ev &= 0x1f; 821b7d861d9SBoojin Kim ev <<= 3; 822b7d861d9SBoojin Kim buf[1] = ev; 823b7d861d9SBoojin Kim 824b7d861d9SBoojin Kim if (invalidate) 825b7d861d9SBoojin Kim buf[1] |= (1 << 1); 826b7d861d9SBoojin Kim 827b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n", 828b7d861d9SBoojin Kim ev >> 3, invalidate ? ", I" : ""); 829b7d861d9SBoojin Kim 830b7d861d9SBoojin Kim return SZ_DMAWFE; 831b7d861d9SBoojin Kim } 832b7d861d9SBoojin Kim 833b7d861d9SBoojin Kim static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], 834b7d861d9SBoojin Kim enum pl330_cond cond, u8 peri) 835b7d861d9SBoojin Kim { 836b7d861d9SBoojin Kim if (dry_run) 837b7d861d9SBoojin Kim return SZ_DMAWFP; 838b7d861d9SBoojin Kim 839b7d861d9SBoojin Kim buf[0] = CMD_DMAWFP; 840b7d861d9SBoojin Kim 841b7d861d9SBoojin Kim if (cond == SINGLE) 842b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (0 << 0); 843b7d861d9SBoojin Kim else if (cond == BURST) 844b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (0 << 0); 845b7d861d9SBoojin Kim else 846b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 847b7d861d9SBoojin Kim 848b7d861d9SBoojin Kim peri &= 0x1f; 849b7d861d9SBoojin Kim peri <<= 3; 850b7d861d9SBoojin Kim buf[1] = peri; 851b7d861d9SBoojin Kim 852b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", 853b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); 854b7d861d9SBoojin Kim 855b7d861d9SBoojin Kim return SZ_DMAWFP; 856b7d861d9SBoojin Kim } 857b7d861d9SBoojin Kim 858b7d861d9SBoojin Kim static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) 859b7d861d9SBoojin Kim { 860b7d861d9SBoojin Kim if (dry_run) 861b7d861d9SBoojin Kim return SZ_DMAWMB; 862b7d861d9SBoojin Kim 863b7d861d9SBoojin Kim buf[0] = CMD_DMAWMB; 864b7d861d9SBoojin Kim 865b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); 866b7d861d9SBoojin Kim 867b7d861d9SBoojin Kim return SZ_DMAWMB; 868b7d861d9SBoojin Kim } 869b7d861d9SBoojin Kim 870b7d861d9SBoojin Kim struct _arg_GO { 871b7d861d9SBoojin Kim u8 chan; 872b7d861d9SBoojin Kim u32 addr; 873b7d861d9SBoojin Kim unsigned ns; 874b7d861d9SBoojin Kim }; 875b7d861d9SBoojin Kim 876b7d861d9SBoojin Kim static inline u32 _emit_GO(unsigned dry_run, u8 buf[], 877b7d861d9SBoojin Kim const struct _arg_GO *arg) 878b7d861d9SBoojin Kim { 879b7d861d9SBoojin Kim u8 chan = arg->chan; 880b7d861d9SBoojin Kim u32 addr = arg->addr; 881b7d861d9SBoojin Kim unsigned ns = arg->ns; 882b7d861d9SBoojin Kim 883b7d861d9SBoojin Kim if (dry_run) 884b7d861d9SBoojin Kim return SZ_DMAGO; 885b7d861d9SBoojin Kim 886b7d861d9SBoojin Kim buf[0] = CMD_DMAGO; 887b7d861d9SBoojin Kim buf[0] |= (ns << 1); 888b7d861d9SBoojin Kim 889b7d861d9SBoojin Kim buf[1] = chan & 0x7; 890b7d861d9SBoojin Kim 8913a2307f7SBen Dooks *((__le32 *)&buf[2]) = cpu_to_le32(addr); 892b7d861d9SBoojin Kim 893b7d861d9SBoojin Kim return SZ_DMAGO; 894b7d861d9SBoojin Kim } 895b7d861d9SBoojin Kim 896b7d861d9SBoojin Kim #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 897b7d861d9SBoojin Kim 898b7d861d9SBoojin Kim /* Returns Time-Out */ 899b7d861d9SBoojin Kim static bool _until_dmac_idle(struct pl330_thread *thrd) 900b7d861d9SBoojin Kim { 901f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 902b7d861d9SBoojin Kim unsigned long loops = msecs_to_loops(5); 903b7d861d9SBoojin Kim 904b7d861d9SBoojin Kim do { 905b7d861d9SBoojin Kim /* Until Manager is Idle */ 906b7d861d9SBoojin Kim if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) 907b7d861d9SBoojin Kim break; 908b7d861d9SBoojin Kim 909b7d861d9SBoojin Kim cpu_relax(); 910b7d861d9SBoojin Kim } while (--loops); 911b7d861d9SBoojin Kim 912b7d861d9SBoojin Kim if (!loops) 913b7d861d9SBoojin Kim return true; 914b7d861d9SBoojin Kim 915b7d861d9SBoojin Kim return false; 916b7d861d9SBoojin Kim } 917b7d861d9SBoojin Kim 918b7d861d9SBoojin Kim static inline void _execute_DBGINSN(struct pl330_thread *thrd, 919b7d861d9SBoojin Kim u8 insn[], bool as_manager) 920b7d861d9SBoojin Kim { 921f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 922b7d861d9SBoojin Kim u32 val; 923b7d861d9SBoojin Kim 924b7d861d9SBoojin Kim val = (insn[0] << 16) | (insn[1] << 24); 925b7d861d9SBoojin Kim if (!as_manager) { 926b7d861d9SBoojin Kim val |= (1 << 0); 927b7d861d9SBoojin Kim val |= (thrd->id << 8); /* Channel Number */ 928b7d861d9SBoojin Kim } 929b7d861d9SBoojin Kim writel(val, regs + DBGINST0); 930b7d861d9SBoojin Kim 9313a2307f7SBen Dooks val = le32_to_cpu(*((__le32 *)&insn[2])); 932b7d861d9SBoojin Kim writel(val, regs + DBGINST1); 933b7d861d9SBoojin Kim 934b7d861d9SBoojin Kim /* If timed out due to halted state-machine */ 935b7d861d9SBoojin Kim if (_until_dmac_idle(thrd)) { 936f6f2421cSLars-Peter Clausen dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n"); 937b7d861d9SBoojin Kim return; 938b7d861d9SBoojin Kim } 939b7d861d9SBoojin Kim 940b7d861d9SBoojin Kim /* Get going */ 941b7d861d9SBoojin Kim writel(0, regs + DBGCMD); 942b7d861d9SBoojin Kim } 943b7d861d9SBoojin Kim 944b7d861d9SBoojin Kim static inline u32 _state(struct pl330_thread *thrd) 945b7d861d9SBoojin Kim { 946f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 947b7d861d9SBoojin Kim u32 val; 948b7d861d9SBoojin Kim 949b7d861d9SBoojin Kim if (is_manager(thrd)) 950b7d861d9SBoojin Kim val = readl(regs + DS) & 0xf; 951b7d861d9SBoojin Kim else 952b7d861d9SBoojin Kim val = readl(regs + CS(thrd->id)) & 0xf; 953b7d861d9SBoojin Kim 954b7d861d9SBoojin Kim switch (val) { 955b7d861d9SBoojin Kim case DS_ST_STOP: 956b7d861d9SBoojin Kim return PL330_STATE_STOPPED; 957b7d861d9SBoojin Kim case DS_ST_EXEC: 958b7d861d9SBoojin Kim return PL330_STATE_EXECUTING; 959b7d861d9SBoojin Kim case DS_ST_CMISS: 960b7d861d9SBoojin Kim return PL330_STATE_CACHEMISS; 961b7d861d9SBoojin Kim case DS_ST_UPDTPC: 962b7d861d9SBoojin Kim return PL330_STATE_UPDTPC; 963b7d861d9SBoojin Kim case DS_ST_WFE: 964b7d861d9SBoojin Kim return PL330_STATE_WFE; 965b7d861d9SBoojin Kim case DS_ST_FAULT: 966b7d861d9SBoojin Kim return PL330_STATE_FAULTING; 967b7d861d9SBoojin Kim case DS_ST_ATBRR: 968b7d861d9SBoojin Kim if (is_manager(thrd)) 969b7d861d9SBoojin Kim return PL330_STATE_INVALID; 970b7d861d9SBoojin Kim else 971b7d861d9SBoojin Kim return PL330_STATE_ATBARRIER; 972b7d861d9SBoojin Kim case DS_ST_QBUSY: 973b7d861d9SBoojin Kim if (is_manager(thrd)) 974b7d861d9SBoojin Kim return PL330_STATE_INVALID; 975b7d861d9SBoojin Kim else 976b7d861d9SBoojin Kim return PL330_STATE_QUEUEBUSY; 977b7d861d9SBoojin Kim case DS_ST_WFP: 978b7d861d9SBoojin Kim if (is_manager(thrd)) 979b7d861d9SBoojin Kim return PL330_STATE_INVALID; 980b7d861d9SBoojin Kim else 981b7d861d9SBoojin Kim return PL330_STATE_WFP; 982b7d861d9SBoojin Kim case DS_ST_KILL: 983b7d861d9SBoojin Kim if (is_manager(thrd)) 984b7d861d9SBoojin Kim return PL330_STATE_INVALID; 985b7d861d9SBoojin Kim else 986b7d861d9SBoojin Kim return PL330_STATE_KILLING; 987b7d861d9SBoojin Kim case DS_ST_CMPLT: 988b7d861d9SBoojin Kim if (is_manager(thrd)) 989b7d861d9SBoojin Kim return PL330_STATE_INVALID; 990b7d861d9SBoojin Kim else 991b7d861d9SBoojin Kim return PL330_STATE_COMPLETING; 992b7d861d9SBoojin Kim case DS_ST_FLTCMP: 993b7d861d9SBoojin Kim if (is_manager(thrd)) 994b7d861d9SBoojin Kim return PL330_STATE_INVALID; 995b7d861d9SBoojin Kim else 996b7d861d9SBoojin Kim return PL330_STATE_FAULT_COMPLETING; 997b7d861d9SBoojin Kim default: 998b7d861d9SBoojin Kim return PL330_STATE_INVALID; 999b7d861d9SBoojin Kim } 1000b7d861d9SBoojin Kim } 1001b7d861d9SBoojin Kim 1002b7d861d9SBoojin Kim static void _stop(struct pl330_thread *thrd) 1003b7d861d9SBoojin Kim { 1004f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 1005b7d861d9SBoojin Kim u8 insn[6] = {0, 0, 0, 0, 0, 0}; 1006b7d861d9SBoojin Kim 1007b7d861d9SBoojin Kim if (_state(thrd) == PL330_STATE_FAULT_COMPLETING) 1008b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); 1009b7d861d9SBoojin Kim 1010b7d861d9SBoojin Kim /* Return if nothing needs to be done */ 1011b7d861d9SBoojin Kim if (_state(thrd) == PL330_STATE_COMPLETING 1012b7d861d9SBoojin Kim || _state(thrd) == PL330_STATE_KILLING 1013b7d861d9SBoojin Kim || _state(thrd) == PL330_STATE_STOPPED) 1014b7d861d9SBoojin Kim return; 1015b7d861d9SBoojin Kim 1016b7d861d9SBoojin Kim _emit_KILL(0, insn); 1017b7d861d9SBoojin Kim 1018b7d861d9SBoojin Kim /* Stop generating interrupts for SEV */ 1019b7d861d9SBoojin Kim writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN); 1020b7d861d9SBoojin Kim 1021b7d861d9SBoojin Kim _execute_DBGINSN(thrd, insn, is_manager(thrd)); 1022b7d861d9SBoojin Kim } 1023b7d861d9SBoojin Kim 1024b7d861d9SBoojin Kim /* Start doing req 'idx' of thread 'thrd' */ 1025b7d861d9SBoojin Kim static bool _trigger(struct pl330_thread *thrd) 1026b7d861d9SBoojin Kim { 1027f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 1028b7d861d9SBoojin Kim struct _pl330_req *req; 10299dc5a315SLars-Peter Clausen struct dma_pl330_desc *desc; 1030b7d861d9SBoojin Kim struct _arg_GO go; 1031b7d861d9SBoojin Kim unsigned ns; 1032b7d861d9SBoojin Kim u8 insn[6] = {0, 0, 0, 0, 0, 0}; 1033b7d861d9SBoojin Kim int idx; 1034b7d861d9SBoojin Kim 1035b7d861d9SBoojin Kim /* Return if already ACTIVE */ 1036b7d861d9SBoojin Kim if (_state(thrd) != PL330_STATE_STOPPED) 1037b7d861d9SBoojin Kim return true; 1038b7d861d9SBoojin Kim 1039b7d861d9SBoojin Kim idx = 1 - thrd->lstenq; 10408ed30a14SLars-Peter Clausen if (thrd->req[idx].desc != NULL) { 1041b7d861d9SBoojin Kim req = &thrd->req[idx]; 10428ed30a14SLars-Peter Clausen } else { 1043b7d861d9SBoojin Kim idx = thrd->lstenq; 10448ed30a14SLars-Peter Clausen if (thrd->req[idx].desc != NULL) 1045b7d861d9SBoojin Kim req = &thrd->req[idx]; 1046b7d861d9SBoojin Kim else 1047b7d861d9SBoojin Kim req = NULL; 1048b7d861d9SBoojin Kim } 1049b7d861d9SBoojin Kim 1050b7d861d9SBoojin Kim /* Return if no request */ 10518ed30a14SLars-Peter Clausen if (!req) 1052b7d861d9SBoojin Kim return true; 1053b7d861d9SBoojin Kim 10540091b9d6SAddy Ke /* Return if req is running */ 10550091b9d6SAddy Ke if (idx == thrd->req_running) 10560091b9d6SAddy Ke return true; 10570091b9d6SAddy Ke 10589dc5a315SLars-Peter Clausen desc = req->desc; 1059b7d861d9SBoojin Kim 10609dc5a315SLars-Peter Clausen ns = desc->rqcfg.nonsecure ? 1 : 0; 1061b7d861d9SBoojin Kim 1062b7d861d9SBoojin Kim /* See 'Abort Sources' point-4 at Page 2-25 */ 1063b7d861d9SBoojin Kim if (_manager_ns(thrd) && !ns) 1064f6f2421cSLars-Peter Clausen dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n", 1065b7d861d9SBoojin Kim __func__, __LINE__); 1066b7d861d9SBoojin Kim 1067b7d861d9SBoojin Kim go.chan = thrd->id; 1068b7d861d9SBoojin Kim go.addr = req->mc_bus; 1069b7d861d9SBoojin Kim go.ns = ns; 1070b7d861d9SBoojin Kim _emit_GO(0, insn, &go); 1071b7d861d9SBoojin Kim 1072b7d861d9SBoojin Kim /* Set to generate interrupts for SEV */ 1073b7d861d9SBoojin Kim writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); 1074b7d861d9SBoojin Kim 1075b7d861d9SBoojin Kim /* Only manager can execute GO */ 1076b7d861d9SBoojin Kim _execute_DBGINSN(thrd, insn, true); 1077b7d861d9SBoojin Kim 1078b7d861d9SBoojin Kim thrd->req_running = idx; 1079b7d861d9SBoojin Kim 1080b7d861d9SBoojin Kim return true; 1081b7d861d9SBoojin Kim } 1082b7d861d9SBoojin Kim 1083b7d861d9SBoojin Kim static bool _start(struct pl330_thread *thrd) 1084b7d861d9SBoojin Kim { 1085b7d861d9SBoojin Kim switch (_state(thrd)) { 1086b7d861d9SBoojin Kim case PL330_STATE_FAULT_COMPLETING: 1087b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); 1088b7d861d9SBoojin Kim 1089b7d861d9SBoojin Kim if (_state(thrd) == PL330_STATE_KILLING) 1090b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_STOPPED) 1091b7d861d9SBoojin Kim 1092b7d861d9SBoojin Kim case PL330_STATE_FAULTING: 1093b7d861d9SBoojin Kim _stop(thrd); 1094b7d861d9SBoojin Kim 1095b7d861d9SBoojin Kim case PL330_STATE_KILLING: 1096b7d861d9SBoojin Kim case PL330_STATE_COMPLETING: 1097b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_STOPPED) 1098b7d861d9SBoojin Kim 1099b7d861d9SBoojin Kim case PL330_STATE_STOPPED: 1100b7d861d9SBoojin Kim return _trigger(thrd); 1101b7d861d9SBoojin Kim 1102b7d861d9SBoojin Kim case PL330_STATE_WFP: 1103b7d861d9SBoojin Kim case PL330_STATE_QUEUEBUSY: 1104b7d861d9SBoojin Kim case PL330_STATE_ATBARRIER: 1105b7d861d9SBoojin Kim case PL330_STATE_UPDTPC: 1106b7d861d9SBoojin Kim case PL330_STATE_CACHEMISS: 1107b7d861d9SBoojin Kim case PL330_STATE_EXECUTING: 1108b7d861d9SBoojin Kim return true; 1109b7d861d9SBoojin Kim 1110b7d861d9SBoojin Kim case PL330_STATE_WFE: /* For RESUME, nothing yet */ 1111b7d861d9SBoojin Kim default: 1112b7d861d9SBoojin Kim return false; 1113b7d861d9SBoojin Kim } 1114b7d861d9SBoojin Kim } 1115b7d861d9SBoojin Kim 1116b7d861d9SBoojin Kim static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], 1117b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1118b7d861d9SBoojin Kim { 1119b7d861d9SBoojin Kim int off = 0; 11209dc5a315SLars-Peter Clausen struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg; 1121b7d861d9SBoojin Kim 11223ecf51a4SBoojin Kim /* check lock-up free version */ 11233ecf51a4SBoojin Kim if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { 11243ecf51a4SBoojin Kim while (cyc--) { 11253ecf51a4SBoojin Kim off += _emit_LD(dry_run, &buf[off], ALWAYS); 11263ecf51a4SBoojin Kim off += _emit_ST(dry_run, &buf[off], ALWAYS); 11273ecf51a4SBoojin Kim } 11283ecf51a4SBoojin Kim } else { 1129b7d861d9SBoojin Kim while (cyc--) { 1130b7d861d9SBoojin Kim off += _emit_LD(dry_run, &buf[off], ALWAYS); 1131b7d861d9SBoojin Kim off += _emit_RMB(dry_run, &buf[off]); 1132b7d861d9SBoojin Kim off += _emit_ST(dry_run, &buf[off], ALWAYS); 1133b7d861d9SBoojin Kim off += _emit_WMB(dry_run, &buf[off]); 1134b7d861d9SBoojin Kim } 11353ecf51a4SBoojin Kim } 1136b7d861d9SBoojin Kim 1137b7d861d9SBoojin Kim return off; 1138b7d861d9SBoojin Kim } 1139b7d861d9SBoojin Kim 1140b7d861d9SBoojin Kim static inline int _ldst_devtomem(unsigned dry_run, u8 buf[], 1141b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1142b7d861d9SBoojin Kim { 1143b7d861d9SBoojin Kim int off = 0; 1144b7d861d9SBoojin Kim 1145b7d861d9SBoojin Kim while (cyc--) { 11469dc5a315SLars-Peter Clausen off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri); 11479dc5a315SLars-Peter Clausen off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->desc->peri); 1148b7d861d9SBoojin Kim off += _emit_ST(dry_run, &buf[off], ALWAYS); 11499dc5a315SLars-Peter Clausen off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri); 1150b7d861d9SBoojin Kim } 1151b7d861d9SBoojin Kim 1152b7d861d9SBoojin Kim return off; 1153b7d861d9SBoojin Kim } 1154b7d861d9SBoojin Kim 1155b7d861d9SBoojin Kim static inline int _ldst_memtodev(unsigned dry_run, u8 buf[], 1156b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1157b7d861d9SBoojin Kim { 1158b7d861d9SBoojin Kim int off = 0; 1159b7d861d9SBoojin Kim 1160b7d861d9SBoojin Kim while (cyc--) { 11619dc5a315SLars-Peter Clausen off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->desc->peri); 1162b7d861d9SBoojin Kim off += _emit_LD(dry_run, &buf[off], ALWAYS); 11639dc5a315SLars-Peter Clausen off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->desc->peri); 11649dc5a315SLars-Peter Clausen off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri); 1165b7d861d9SBoojin Kim } 1166b7d861d9SBoojin Kim 1167b7d861d9SBoojin Kim return off; 1168b7d861d9SBoojin Kim } 1169b7d861d9SBoojin Kim 1170b7d861d9SBoojin Kim static int _bursts(unsigned dry_run, u8 buf[], 1171b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1172b7d861d9SBoojin Kim { 1173b7d861d9SBoojin Kim int off = 0; 1174b7d861d9SBoojin Kim 11759dc5a315SLars-Peter Clausen switch (pxs->desc->rqtype) { 1176585a9d0bSLars-Peter Clausen case DMA_MEM_TO_DEV: 1177b7d861d9SBoojin Kim off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc); 1178b7d861d9SBoojin Kim break; 1179585a9d0bSLars-Peter Clausen case DMA_DEV_TO_MEM: 1180b7d861d9SBoojin Kim off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc); 1181b7d861d9SBoojin Kim break; 1182585a9d0bSLars-Peter Clausen case DMA_MEM_TO_MEM: 1183b7d861d9SBoojin Kim off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); 1184b7d861d9SBoojin Kim break; 1185b7d861d9SBoojin Kim default: 1186b7d861d9SBoojin Kim off += 0x40000000; /* Scare off the Client */ 1187b7d861d9SBoojin Kim break; 1188b7d861d9SBoojin Kim } 1189b7d861d9SBoojin Kim 1190b7d861d9SBoojin Kim return off; 1191b7d861d9SBoojin Kim } 1192b7d861d9SBoojin Kim 1193b7d861d9SBoojin Kim /* Returns bytes consumed and updates bursts */ 1194b7d861d9SBoojin Kim static inline int _loop(unsigned dry_run, u8 buf[], 1195b7d861d9SBoojin Kim unsigned long *bursts, const struct _xfer_spec *pxs) 1196b7d861d9SBoojin Kim { 1197b7d861d9SBoojin Kim int cyc, cycmax, szlp, szlpend, szbrst, off; 1198b7d861d9SBoojin Kim unsigned lcnt0, lcnt1, ljmp0, ljmp1; 1199b7d861d9SBoojin Kim struct _arg_LPEND lpend; 1200b7d861d9SBoojin Kim 1201b7d861d9SBoojin Kim /* Max iterations possible in DMALP is 256 */ 1202b7d861d9SBoojin Kim if (*bursts >= 256*256) { 1203b7d861d9SBoojin Kim lcnt1 = 256; 1204b7d861d9SBoojin Kim lcnt0 = 256; 1205b7d861d9SBoojin Kim cyc = *bursts / lcnt1 / lcnt0; 1206b7d861d9SBoojin Kim } else if (*bursts > 256) { 1207b7d861d9SBoojin Kim lcnt1 = 256; 1208b7d861d9SBoojin Kim lcnt0 = *bursts / lcnt1; 1209b7d861d9SBoojin Kim cyc = 1; 1210b7d861d9SBoojin Kim } else { 1211b7d861d9SBoojin Kim lcnt1 = *bursts; 1212b7d861d9SBoojin Kim lcnt0 = 0; 1213b7d861d9SBoojin Kim cyc = 1; 1214b7d861d9SBoojin Kim } 1215b7d861d9SBoojin Kim 1216b7d861d9SBoojin Kim szlp = _emit_LP(1, buf, 0, 0); 1217b7d861d9SBoojin Kim szbrst = _bursts(1, buf, pxs, 1); 1218b7d861d9SBoojin Kim 1219b7d861d9SBoojin Kim lpend.cond = ALWAYS; 1220b7d861d9SBoojin Kim lpend.forever = false; 1221b7d861d9SBoojin Kim lpend.loop = 0; 1222b7d861d9SBoojin Kim lpend.bjump = 0; 1223b7d861d9SBoojin Kim szlpend = _emit_LPEND(1, buf, &lpend); 1224b7d861d9SBoojin Kim 1225b7d861d9SBoojin Kim if (lcnt0) { 1226b7d861d9SBoojin Kim szlp *= 2; 1227b7d861d9SBoojin Kim szlpend *= 2; 1228b7d861d9SBoojin Kim } 1229b7d861d9SBoojin Kim 1230b7d861d9SBoojin Kim /* 1231b7d861d9SBoojin Kim * Max bursts that we can unroll due to limit on the 1232b7d861d9SBoojin Kim * size of backward jump that can be encoded in DMALPEND 1233b7d861d9SBoojin Kim * which is 8-bits and hence 255 1234b7d861d9SBoojin Kim */ 1235b7d861d9SBoojin Kim cycmax = (255 - (szlp + szlpend)) / szbrst; 1236b7d861d9SBoojin Kim 1237b7d861d9SBoojin Kim cyc = (cycmax < cyc) ? cycmax : cyc; 1238b7d861d9SBoojin Kim 1239b7d861d9SBoojin Kim off = 0; 1240b7d861d9SBoojin Kim 1241b7d861d9SBoojin Kim if (lcnt0) { 1242b7d861d9SBoojin Kim off += _emit_LP(dry_run, &buf[off], 0, lcnt0); 1243b7d861d9SBoojin Kim ljmp0 = off; 1244b7d861d9SBoojin Kim } 1245b7d861d9SBoojin Kim 1246b7d861d9SBoojin Kim off += _emit_LP(dry_run, &buf[off], 1, lcnt1); 1247b7d861d9SBoojin Kim ljmp1 = off; 1248b7d861d9SBoojin Kim 1249b7d861d9SBoojin Kim off += _bursts(dry_run, &buf[off], pxs, cyc); 1250b7d861d9SBoojin Kim 1251b7d861d9SBoojin Kim lpend.cond = ALWAYS; 1252b7d861d9SBoojin Kim lpend.forever = false; 1253b7d861d9SBoojin Kim lpend.loop = 1; 1254b7d861d9SBoojin Kim lpend.bjump = off - ljmp1; 1255b7d861d9SBoojin Kim off += _emit_LPEND(dry_run, &buf[off], &lpend); 1256b7d861d9SBoojin Kim 1257b7d861d9SBoojin Kim if (lcnt0) { 1258b7d861d9SBoojin Kim lpend.cond = ALWAYS; 1259b7d861d9SBoojin Kim lpend.forever = false; 1260b7d861d9SBoojin Kim lpend.loop = 0; 1261b7d861d9SBoojin Kim lpend.bjump = off - ljmp0; 1262b7d861d9SBoojin Kim off += _emit_LPEND(dry_run, &buf[off], &lpend); 1263b7d861d9SBoojin Kim } 1264b7d861d9SBoojin Kim 1265b7d861d9SBoojin Kim *bursts = lcnt1 * cyc; 1266b7d861d9SBoojin Kim if (lcnt0) 1267b7d861d9SBoojin Kim *bursts *= lcnt0; 1268b7d861d9SBoojin Kim 1269b7d861d9SBoojin Kim return off; 1270b7d861d9SBoojin Kim } 1271b7d861d9SBoojin Kim 1272b7d861d9SBoojin Kim static inline int _setup_loops(unsigned dry_run, u8 buf[], 1273b7d861d9SBoojin Kim const struct _xfer_spec *pxs) 1274b7d861d9SBoojin Kim { 12759dc5a315SLars-Peter Clausen struct pl330_xfer *x = &pxs->desc->px; 1276b7d861d9SBoojin Kim u32 ccr = pxs->ccr; 1277b7d861d9SBoojin Kim unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); 1278b7d861d9SBoojin Kim int off = 0; 1279b7d861d9SBoojin Kim 1280b7d861d9SBoojin Kim while (bursts) { 1281b7d861d9SBoojin Kim c = bursts; 1282b7d861d9SBoojin Kim off += _loop(dry_run, &buf[off], &c, pxs); 1283b7d861d9SBoojin Kim bursts -= c; 1284b7d861d9SBoojin Kim } 1285b7d861d9SBoojin Kim 1286b7d861d9SBoojin Kim return off; 1287b7d861d9SBoojin Kim } 1288b7d861d9SBoojin Kim 1289b7d861d9SBoojin Kim static inline int _setup_xfer(unsigned dry_run, u8 buf[], 1290b7d861d9SBoojin Kim const struct _xfer_spec *pxs) 1291b7d861d9SBoojin Kim { 12929dc5a315SLars-Peter Clausen struct pl330_xfer *x = &pxs->desc->px; 1293b7d861d9SBoojin Kim int off = 0; 1294b7d861d9SBoojin Kim 1295b7d861d9SBoojin Kim /* DMAMOV SAR, x->src_addr */ 1296b7d861d9SBoojin Kim off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); 1297b7d861d9SBoojin Kim /* DMAMOV DAR, x->dst_addr */ 1298b7d861d9SBoojin Kim off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr); 1299b7d861d9SBoojin Kim 1300b7d861d9SBoojin Kim /* Setup Loop(s) */ 1301b7d861d9SBoojin Kim off += _setup_loops(dry_run, &buf[off], pxs); 1302b7d861d9SBoojin Kim 1303b7d861d9SBoojin Kim return off; 1304b7d861d9SBoojin Kim } 1305b7d861d9SBoojin Kim 1306b7d861d9SBoojin Kim /* 1307b7d861d9SBoojin Kim * A req is a sequence of one or more xfer units. 1308b7d861d9SBoojin Kim * Returns the number of bytes taken to setup the MC for the req. 1309b7d861d9SBoojin Kim */ 1310b7d861d9SBoojin Kim static int _setup_req(unsigned dry_run, struct pl330_thread *thrd, 1311b7d861d9SBoojin Kim unsigned index, struct _xfer_spec *pxs) 1312b7d861d9SBoojin Kim { 1313b7d861d9SBoojin Kim struct _pl330_req *req = &thrd->req[index]; 1314b7d861d9SBoojin Kim struct pl330_xfer *x; 1315b7d861d9SBoojin Kim u8 *buf = req->mc_cpu; 1316b7d861d9SBoojin Kim int off = 0; 1317b7d861d9SBoojin Kim 1318b7d861d9SBoojin Kim PL330_DBGMC_START(req->mc_bus); 1319b7d861d9SBoojin Kim 1320b7d861d9SBoojin Kim /* DMAMOV CCR, ccr */ 1321b7d861d9SBoojin Kim off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); 1322b7d861d9SBoojin Kim 13239dc5a315SLars-Peter Clausen x = &pxs->desc->px; 1324b7d861d9SBoojin Kim /* Error if xfer length is not aligned at burst size */ 1325b7d861d9SBoojin Kim if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr))) 1326b7d861d9SBoojin Kim return -EINVAL; 1327b7d861d9SBoojin Kim 1328b7d861d9SBoojin Kim off += _setup_xfer(dry_run, &buf[off], pxs); 1329b7d861d9SBoojin Kim 1330b7d861d9SBoojin Kim /* DMASEV peripheral/event */ 1331b7d861d9SBoojin Kim off += _emit_SEV(dry_run, &buf[off], thrd->ev); 1332b7d861d9SBoojin Kim /* DMAEND */ 1333b7d861d9SBoojin Kim off += _emit_END(dry_run, &buf[off]); 1334b7d861d9SBoojin Kim 1335b7d861d9SBoojin Kim return off; 1336b7d861d9SBoojin Kim } 1337b7d861d9SBoojin Kim 1338b7d861d9SBoojin Kim static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) 1339b7d861d9SBoojin Kim { 1340b7d861d9SBoojin Kim u32 ccr = 0; 1341b7d861d9SBoojin Kim 1342b7d861d9SBoojin Kim if (rqc->src_inc) 1343b7d861d9SBoojin Kim ccr |= CC_SRCINC; 1344b7d861d9SBoojin Kim 1345b7d861d9SBoojin Kim if (rqc->dst_inc) 1346b7d861d9SBoojin Kim ccr |= CC_DSTINC; 1347b7d861d9SBoojin Kim 1348b7d861d9SBoojin Kim /* We set same protection levels for Src and DST for now */ 1349b7d861d9SBoojin Kim if (rqc->privileged) 1350b7d861d9SBoojin Kim ccr |= CC_SRCPRI | CC_DSTPRI; 1351b7d861d9SBoojin Kim if (rqc->nonsecure) 1352b7d861d9SBoojin Kim ccr |= CC_SRCNS | CC_DSTNS; 1353b7d861d9SBoojin Kim if (rqc->insnaccess) 1354b7d861d9SBoojin Kim ccr |= CC_SRCIA | CC_DSTIA; 1355b7d861d9SBoojin Kim 1356b7d861d9SBoojin Kim ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); 1357b7d861d9SBoojin Kim ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); 1358b7d861d9SBoojin Kim 1359b7d861d9SBoojin Kim ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); 1360b7d861d9SBoojin Kim ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); 1361b7d861d9SBoojin Kim 1362b7d861d9SBoojin Kim ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); 1363b7d861d9SBoojin Kim ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); 1364b7d861d9SBoojin Kim 1365b7d861d9SBoojin Kim ccr |= (rqc->swap << CC_SWAP_SHFT); 1366b7d861d9SBoojin Kim 1367b7d861d9SBoojin Kim return ccr; 1368b7d861d9SBoojin Kim } 1369b7d861d9SBoojin Kim 1370b7d861d9SBoojin Kim /* 1371b7d861d9SBoojin Kim * Submit a list of xfers after which the client wants notification. 1372b7d861d9SBoojin Kim * Client is not notified after each xfer unit, just once after all 1373b7d861d9SBoojin Kim * xfer units are done or some error occurs. 1374b7d861d9SBoojin Kim */ 13759dc5a315SLars-Peter Clausen static int pl330_submit_req(struct pl330_thread *thrd, 13769dc5a315SLars-Peter Clausen struct dma_pl330_desc *desc) 1377b7d861d9SBoojin Kim { 1378f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = thrd->dmac; 1379b7d861d9SBoojin Kim struct _xfer_spec xs; 1380b7d861d9SBoojin Kim unsigned long flags; 1381b7d861d9SBoojin Kim unsigned idx; 1382b7d861d9SBoojin Kim u32 ccr; 1383b7d861d9SBoojin Kim int ret = 0; 1384b7d861d9SBoojin Kim 1385b7d861d9SBoojin Kim if (pl330->state == DYING 1386b7d861d9SBoojin Kim || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { 1387f6f2421cSLars-Peter Clausen dev_info(thrd->dmac->ddma.dev, "%s:%d\n", 1388b7d861d9SBoojin Kim __func__, __LINE__); 1389b7d861d9SBoojin Kim return -EAGAIN; 1390b7d861d9SBoojin Kim } 1391b7d861d9SBoojin Kim 1392b7d861d9SBoojin Kim /* If request for non-existing peripheral */ 13939dc5a315SLars-Peter Clausen if (desc->rqtype != DMA_MEM_TO_MEM && 13949dc5a315SLars-Peter Clausen desc->peri >= pl330->pcfg.num_peri) { 1395f6f2421cSLars-Peter Clausen dev_info(thrd->dmac->ddma.dev, 1396b7d861d9SBoojin Kim "%s:%d Invalid peripheral(%u)!\n", 13979dc5a315SLars-Peter Clausen __func__, __LINE__, desc->peri); 1398b7d861d9SBoojin Kim return -EINVAL; 1399b7d861d9SBoojin Kim } 1400b7d861d9SBoojin Kim 1401b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1402b7d861d9SBoojin Kim 1403b7d861d9SBoojin Kim if (_queue_full(thrd)) { 1404b7d861d9SBoojin Kim ret = -EAGAIN; 1405b7d861d9SBoojin Kim goto xfer_exit; 1406b7d861d9SBoojin Kim } 1407b7d861d9SBoojin Kim 1408b7d861d9SBoojin Kim /* Prefer Secure Channel */ 1409b7d861d9SBoojin Kim if (!_manager_ns(thrd)) 14109dc5a315SLars-Peter Clausen desc->rqcfg.nonsecure = 0; 1411b7d861d9SBoojin Kim else 14129dc5a315SLars-Peter Clausen desc->rqcfg.nonsecure = 1; 1413b7d861d9SBoojin Kim 14149dc5a315SLars-Peter Clausen ccr = _prepare_ccr(&desc->rqcfg); 1415b7d861d9SBoojin Kim 14168ed30a14SLars-Peter Clausen idx = thrd->req[0].desc == NULL ? 0 : 1; 1417b7d861d9SBoojin Kim 1418b7d861d9SBoojin Kim xs.ccr = ccr; 14199dc5a315SLars-Peter Clausen xs.desc = desc; 1420b7d861d9SBoojin Kim 1421b7d861d9SBoojin Kim /* First dry run to check if req is acceptable */ 1422b7d861d9SBoojin Kim ret = _setup_req(1, thrd, idx, &xs); 1423b7d861d9SBoojin Kim if (ret < 0) 1424b7d861d9SBoojin Kim goto xfer_exit; 1425b7d861d9SBoojin Kim 1426f6f2421cSLars-Peter Clausen if (ret > pl330->mcbufsz / 2) { 1427e5489d5eSMichal Suchanek dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n", 1428e5489d5eSMichal Suchanek __func__, __LINE__, ret, pl330->mcbufsz / 2); 1429b7d861d9SBoojin Kim ret = -ENOMEM; 1430b7d861d9SBoojin Kim goto xfer_exit; 1431b7d861d9SBoojin Kim } 1432b7d861d9SBoojin Kim 1433b7d861d9SBoojin Kim /* Hook the request */ 1434b7d861d9SBoojin Kim thrd->lstenq = idx; 14359dc5a315SLars-Peter Clausen thrd->req[idx].desc = desc; 1436be025329SLars-Peter Clausen _setup_req(0, thrd, idx, &xs); 1437b7d861d9SBoojin Kim 1438b7d861d9SBoojin Kim ret = 0; 1439b7d861d9SBoojin Kim 1440b7d861d9SBoojin Kim xfer_exit: 1441b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1442b7d861d9SBoojin Kim 1443b7d861d9SBoojin Kim return ret; 1444b7d861d9SBoojin Kim } 1445b7d861d9SBoojin Kim 14469dc5a315SLars-Peter Clausen static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err) 14476079d38cSLars-Peter Clausen { 1448b1e51d77SJavier Martinez Canillas struct dma_pl330_chan *pch; 14496079d38cSLars-Peter Clausen unsigned long flags; 14506079d38cSLars-Peter Clausen 1451b1e51d77SJavier Martinez Canillas if (!desc) 1452b1e51d77SJavier Martinez Canillas return; 1453b1e51d77SJavier Martinez Canillas 1454b1e51d77SJavier Martinez Canillas pch = desc->pchan; 1455b1e51d77SJavier Martinez Canillas 14566079d38cSLars-Peter Clausen /* If desc aborted */ 14576079d38cSLars-Peter Clausen if (!pch) 14586079d38cSLars-Peter Clausen return; 14596079d38cSLars-Peter Clausen 14606079d38cSLars-Peter Clausen spin_lock_irqsave(&pch->lock, flags); 14616079d38cSLars-Peter Clausen 14626079d38cSLars-Peter Clausen desc->status = DONE; 14636079d38cSLars-Peter Clausen 14646079d38cSLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 14656079d38cSLars-Peter Clausen 14666079d38cSLars-Peter Clausen tasklet_schedule(&pch->task); 14676079d38cSLars-Peter Clausen } 14686079d38cSLars-Peter Clausen 1469b7d861d9SBoojin Kim static void pl330_dotask(unsigned long data) 1470b7d861d9SBoojin Kim { 1471b7d861d9SBoojin Kim struct pl330_dmac *pl330 = (struct pl330_dmac *) data; 1472b7d861d9SBoojin Kim unsigned long flags; 1473b7d861d9SBoojin Kim int i; 1474b7d861d9SBoojin Kim 1475b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1476b7d861d9SBoojin Kim 1477b7d861d9SBoojin Kim /* The DMAC itself gone nuts */ 1478b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_dmac) { 1479b7d861d9SBoojin Kim pl330->state = DYING; 1480b7d861d9SBoojin Kim /* Reset the manager too */ 1481b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = true; 1482b7d861d9SBoojin Kim /* Clear the reset flag */ 1483b7d861d9SBoojin Kim pl330->dmac_tbd.reset_dmac = false; 1484b7d861d9SBoojin Kim } 1485b7d861d9SBoojin Kim 1486b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_mngr) { 1487b7d861d9SBoojin Kim _stop(pl330->manager); 1488b7d861d9SBoojin Kim /* Reset all channels */ 1489f6f2421cSLars-Peter Clausen pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1; 1490b7d861d9SBoojin Kim /* Clear the reset flag */ 1491b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = false; 1492b7d861d9SBoojin Kim } 1493b7d861d9SBoojin Kim 1494f6f2421cSLars-Peter Clausen for (i = 0; i < pl330->pcfg.num_chan; i++) { 1495b7d861d9SBoojin Kim 1496b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_chan & (1 << i)) { 1497b7d861d9SBoojin Kim struct pl330_thread *thrd = &pl330->channels[i]; 1498f6f2421cSLars-Peter Clausen void __iomem *regs = pl330->base; 1499b7d861d9SBoojin Kim enum pl330_op_err err; 1500b7d861d9SBoojin Kim 1501b7d861d9SBoojin Kim _stop(thrd); 1502b7d861d9SBoojin Kim 1503b7d861d9SBoojin Kim if (readl(regs + FSC) & (1 << thrd->id)) 1504b7d861d9SBoojin Kim err = PL330_ERR_FAIL; 1505b7d861d9SBoojin Kim else 1506b7d861d9SBoojin Kim err = PL330_ERR_ABORT; 1507b7d861d9SBoojin Kim 1508b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 15099dc5a315SLars-Peter Clausen dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err); 15109dc5a315SLars-Peter Clausen dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err); 1511b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1512b7d861d9SBoojin Kim 15139dc5a315SLars-Peter Clausen thrd->req[0].desc = NULL; 15149dc5a315SLars-Peter Clausen thrd->req[1].desc = NULL; 15158ed30a14SLars-Peter Clausen thrd->req_running = -1; 1516b7d861d9SBoojin Kim 1517b7d861d9SBoojin Kim /* Clear the reset flag */ 1518b7d861d9SBoojin Kim pl330->dmac_tbd.reset_chan &= ~(1 << i); 1519b7d861d9SBoojin Kim } 1520b7d861d9SBoojin Kim } 1521b7d861d9SBoojin Kim 1522b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1523b7d861d9SBoojin Kim 1524b7d861d9SBoojin Kim return; 1525b7d861d9SBoojin Kim } 1526b7d861d9SBoojin Kim 1527b7d861d9SBoojin Kim /* Returns 1 if state was updated, 0 otherwise */ 1528f6f2421cSLars-Peter Clausen static int pl330_update(struct pl330_dmac *pl330) 1529b7d861d9SBoojin Kim { 15309dc5a315SLars-Peter Clausen struct dma_pl330_desc *descdone, *tmp; 1531b7d861d9SBoojin Kim unsigned long flags; 1532b7d861d9SBoojin Kim void __iomem *regs; 1533b7d861d9SBoojin Kim u32 val; 1534b7d861d9SBoojin Kim int id, ev, ret = 0; 1535b7d861d9SBoojin Kim 1536f6f2421cSLars-Peter Clausen regs = pl330->base; 1537b7d861d9SBoojin Kim 1538b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1539b7d861d9SBoojin Kim 1540b7d861d9SBoojin Kim val = readl(regs + FSM) & 0x1; 1541b7d861d9SBoojin Kim if (val) 1542b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = true; 1543b7d861d9SBoojin Kim else 1544b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = false; 1545b7d861d9SBoojin Kim 1546f6f2421cSLars-Peter Clausen val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1); 1547b7d861d9SBoojin Kim pl330->dmac_tbd.reset_chan |= val; 1548b7d861d9SBoojin Kim if (val) { 1549b7d861d9SBoojin Kim int i = 0; 1550f6f2421cSLars-Peter Clausen while (i < pl330->pcfg.num_chan) { 1551b7d861d9SBoojin Kim if (val & (1 << i)) { 1552f6f2421cSLars-Peter Clausen dev_info(pl330->ddma.dev, 1553b7d861d9SBoojin Kim "Reset Channel-%d\t CS-%x FTC-%x\n", 1554b7d861d9SBoojin Kim i, readl(regs + CS(i)), 1555b7d861d9SBoojin Kim readl(regs + FTC(i))); 1556b7d861d9SBoojin Kim _stop(&pl330->channels[i]); 1557b7d861d9SBoojin Kim } 1558b7d861d9SBoojin Kim i++; 1559b7d861d9SBoojin Kim } 1560b7d861d9SBoojin Kim } 1561b7d861d9SBoojin Kim 1562b7d861d9SBoojin Kim /* Check which event happened i.e, thread notified */ 1563b7d861d9SBoojin Kim val = readl(regs + ES); 1564f6f2421cSLars-Peter Clausen if (pl330->pcfg.num_events < 32 1565f6f2421cSLars-Peter Clausen && val & ~((1 << pl330->pcfg.num_events) - 1)) { 1566b7d861d9SBoojin Kim pl330->dmac_tbd.reset_dmac = true; 1567f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__, 1568f6f2421cSLars-Peter Clausen __LINE__); 1569b7d861d9SBoojin Kim ret = 1; 1570b7d861d9SBoojin Kim goto updt_exit; 1571b7d861d9SBoojin Kim } 1572b7d861d9SBoojin Kim 1573f6f2421cSLars-Peter Clausen for (ev = 0; ev < pl330->pcfg.num_events; ev++) { 1574b7d861d9SBoojin Kim if (val & (1 << ev)) { /* Event occurred */ 1575b7d861d9SBoojin Kim struct pl330_thread *thrd; 1576b7d861d9SBoojin Kim u32 inten = readl(regs + INTEN); 1577b7d861d9SBoojin Kim int active; 1578b7d861d9SBoojin Kim 1579b7d861d9SBoojin Kim /* Clear the event */ 1580b7d861d9SBoojin Kim if (inten & (1 << ev)) 1581b7d861d9SBoojin Kim writel(1 << ev, regs + INTCLR); 1582b7d861d9SBoojin Kim 1583b7d861d9SBoojin Kim ret = 1; 1584b7d861d9SBoojin Kim 1585b7d861d9SBoojin Kim id = pl330->events[ev]; 1586b7d861d9SBoojin Kim 1587b7d861d9SBoojin Kim thrd = &pl330->channels[id]; 1588b7d861d9SBoojin Kim 1589b7d861d9SBoojin Kim active = thrd->req_running; 1590b7d861d9SBoojin Kim if (active == -1) /* Aborted */ 1591b7d861d9SBoojin Kim continue; 1592b7d861d9SBoojin Kim 1593fdec53d5SJavi Merino /* Detach the req */ 15949dc5a315SLars-Peter Clausen descdone = thrd->req[active].desc; 15959dc5a315SLars-Peter Clausen thrd->req[active].desc = NULL; 1596fdec53d5SJavi Merino 15970091b9d6SAddy Ke thrd->req_running = -1; 15980091b9d6SAddy Ke 1599b7d861d9SBoojin Kim /* Get going again ASAP */ 1600b7d861d9SBoojin Kim _start(thrd); 1601b7d861d9SBoojin Kim 1602b7d861d9SBoojin Kim /* For now, just make a list of callbacks to be done */ 16039dc5a315SLars-Peter Clausen list_add_tail(&descdone->rqd, &pl330->req_done); 1604b7d861d9SBoojin Kim } 1605b7d861d9SBoojin Kim } 1606b7d861d9SBoojin Kim 1607b7d861d9SBoojin Kim /* Now that we are in no hurry, do the callbacks */ 16089dc5a315SLars-Peter Clausen list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) { 16099dc5a315SLars-Peter Clausen list_del(&descdone->rqd); 1610b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 16119dc5a315SLars-Peter Clausen dma_pl330_rqcb(descdone, PL330_ERR_NONE); 1612b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1613b7d861d9SBoojin Kim } 1614b7d861d9SBoojin Kim 1615b7d861d9SBoojin Kim updt_exit: 1616b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1617b7d861d9SBoojin Kim 1618b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_dmac 1619b7d861d9SBoojin Kim || pl330->dmac_tbd.reset_mngr 1620b7d861d9SBoojin Kim || pl330->dmac_tbd.reset_chan) { 1621b7d861d9SBoojin Kim ret = 1; 1622b7d861d9SBoojin Kim tasklet_schedule(&pl330->tasks); 1623b7d861d9SBoojin Kim } 1624b7d861d9SBoojin Kim 1625b7d861d9SBoojin Kim return ret; 1626b7d861d9SBoojin Kim } 1627b7d861d9SBoojin Kim 1628b7d861d9SBoojin Kim /* Reserve an event */ 1629b7d861d9SBoojin Kim static inline int _alloc_event(struct pl330_thread *thrd) 1630b7d861d9SBoojin Kim { 1631b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 1632b7d861d9SBoojin Kim int ev; 1633b7d861d9SBoojin Kim 1634f6f2421cSLars-Peter Clausen for (ev = 0; ev < pl330->pcfg.num_events; ev++) 1635b7d861d9SBoojin Kim if (pl330->events[ev] == -1) { 1636b7d861d9SBoojin Kim pl330->events[ev] = thrd->id; 1637b7d861d9SBoojin Kim return ev; 1638b7d861d9SBoojin Kim } 1639b7d861d9SBoojin Kim 1640b7d861d9SBoojin Kim return -1; 1641b7d861d9SBoojin Kim } 1642b7d861d9SBoojin Kim 1643f6f2421cSLars-Peter Clausen static bool _chan_ns(const struct pl330_dmac *pl330, int i) 1644b7d861d9SBoojin Kim { 1645f6f2421cSLars-Peter Clausen return pl330->pcfg.irq_ns & (1 << i); 1646b7d861d9SBoojin Kim } 1647b7d861d9SBoojin Kim 1648b7d861d9SBoojin Kim /* Upon success, returns IdentityToken for the 1649b7d861d9SBoojin Kim * allocated channel, NULL otherwise. 1650b7d861d9SBoojin Kim */ 1651f6f2421cSLars-Peter Clausen static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330) 1652b7d861d9SBoojin Kim { 1653b7d861d9SBoojin Kim struct pl330_thread *thrd = NULL; 1654b7d861d9SBoojin Kim unsigned long flags; 1655b7d861d9SBoojin Kim int chans, i; 1656b7d861d9SBoojin Kim 1657b7d861d9SBoojin Kim if (pl330->state == DYING) 1658b7d861d9SBoojin Kim return NULL; 1659b7d861d9SBoojin Kim 1660f6f2421cSLars-Peter Clausen chans = pl330->pcfg.num_chan; 1661b7d861d9SBoojin Kim 1662b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1663b7d861d9SBoojin Kim 1664b7d861d9SBoojin Kim for (i = 0; i < chans; i++) { 1665b7d861d9SBoojin Kim thrd = &pl330->channels[i]; 1666b7d861d9SBoojin Kim if ((thrd->free) && (!_manager_ns(thrd) || 1667f6f2421cSLars-Peter Clausen _chan_ns(pl330, i))) { 1668b7d861d9SBoojin Kim thrd->ev = _alloc_event(thrd); 1669b7d861d9SBoojin Kim if (thrd->ev >= 0) { 1670b7d861d9SBoojin Kim thrd->free = false; 1671b7d861d9SBoojin Kim thrd->lstenq = 1; 16729dc5a315SLars-Peter Clausen thrd->req[0].desc = NULL; 16739dc5a315SLars-Peter Clausen thrd->req[1].desc = NULL; 16748ed30a14SLars-Peter Clausen thrd->req_running = -1; 1675b7d861d9SBoojin Kim break; 1676b7d861d9SBoojin Kim } 1677b7d861d9SBoojin Kim } 1678b7d861d9SBoojin Kim thrd = NULL; 1679b7d861d9SBoojin Kim } 1680b7d861d9SBoojin Kim 1681b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1682b7d861d9SBoojin Kim 1683b7d861d9SBoojin Kim return thrd; 1684b7d861d9SBoojin Kim } 1685b7d861d9SBoojin Kim 1686b7d861d9SBoojin Kim /* Release an event */ 1687b7d861d9SBoojin Kim static inline void _free_event(struct pl330_thread *thrd, int ev) 1688b7d861d9SBoojin Kim { 1689b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 1690b7d861d9SBoojin Kim 1691b7d861d9SBoojin Kim /* If the event is valid and was held by the thread */ 1692f6f2421cSLars-Peter Clausen if (ev >= 0 && ev < pl330->pcfg.num_events 1693b7d861d9SBoojin Kim && pl330->events[ev] == thrd->id) 1694b7d861d9SBoojin Kim pl330->events[ev] = -1; 1695b7d861d9SBoojin Kim } 1696b7d861d9SBoojin Kim 169765ad6060SLars-Peter Clausen static void pl330_release_channel(struct pl330_thread *thrd) 1698b7d861d9SBoojin Kim { 1699b7d861d9SBoojin Kim struct pl330_dmac *pl330; 1700b7d861d9SBoojin Kim unsigned long flags; 1701b7d861d9SBoojin Kim 1702b7d861d9SBoojin Kim if (!thrd || thrd->free) 1703b7d861d9SBoojin Kim return; 1704b7d861d9SBoojin Kim 1705b7d861d9SBoojin Kim _stop(thrd); 1706b7d861d9SBoojin Kim 17079dc5a315SLars-Peter Clausen dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT); 17089dc5a315SLars-Peter Clausen dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT); 1709b7d861d9SBoojin Kim 1710b7d861d9SBoojin Kim pl330 = thrd->dmac; 1711b7d861d9SBoojin Kim 1712b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1713b7d861d9SBoojin Kim _free_event(thrd, thrd->ev); 1714b7d861d9SBoojin Kim thrd->free = true; 1715b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1716b7d861d9SBoojin Kim } 1717b7d861d9SBoojin Kim 1718b7d861d9SBoojin Kim /* Initialize the structure for PL330 configuration, that can be used 1719b7d861d9SBoojin Kim * by the client driver the make best use of the DMAC 1720b7d861d9SBoojin Kim */ 1721f6f2421cSLars-Peter Clausen static void read_dmac_config(struct pl330_dmac *pl330) 1722b7d861d9SBoojin Kim { 1723f6f2421cSLars-Peter Clausen void __iomem *regs = pl330->base; 1724b7d861d9SBoojin Kim u32 val; 1725b7d861d9SBoojin Kim 1726b7d861d9SBoojin Kim val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; 1727b7d861d9SBoojin Kim val &= CRD_DATA_WIDTH_MASK; 1728f6f2421cSLars-Peter Clausen pl330->pcfg.data_bus_width = 8 * (1 << val); 1729b7d861d9SBoojin Kim 1730b7d861d9SBoojin Kim val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; 1731b7d861d9SBoojin Kim val &= CRD_DATA_BUFF_MASK; 1732f6f2421cSLars-Peter Clausen pl330->pcfg.data_buf_dep = val + 1; 1733b7d861d9SBoojin Kim 1734b7d861d9SBoojin Kim val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; 1735b7d861d9SBoojin Kim val &= CR0_NUM_CHANS_MASK; 1736b7d861d9SBoojin Kim val += 1; 1737f6f2421cSLars-Peter Clausen pl330->pcfg.num_chan = val; 1738b7d861d9SBoojin Kim 1739b7d861d9SBoojin Kim val = readl(regs + CR0); 1740b7d861d9SBoojin Kim if (val & CR0_PERIPH_REQ_SET) { 1741b7d861d9SBoojin Kim val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; 1742b7d861d9SBoojin Kim val += 1; 1743f6f2421cSLars-Peter Clausen pl330->pcfg.num_peri = val; 1744f6f2421cSLars-Peter Clausen pl330->pcfg.peri_ns = readl(regs + CR4); 1745b7d861d9SBoojin Kim } else { 1746f6f2421cSLars-Peter Clausen pl330->pcfg.num_peri = 0; 1747b7d861d9SBoojin Kim } 1748b7d861d9SBoojin Kim 1749b7d861d9SBoojin Kim val = readl(regs + CR0); 1750b7d861d9SBoojin Kim if (val & CR0_BOOT_MAN_NS) 1751f6f2421cSLars-Peter Clausen pl330->pcfg.mode |= DMAC_MODE_NS; 1752b7d861d9SBoojin Kim else 1753f6f2421cSLars-Peter Clausen pl330->pcfg.mode &= ~DMAC_MODE_NS; 1754b7d861d9SBoojin Kim 1755b7d861d9SBoojin Kim val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; 1756b7d861d9SBoojin Kim val &= CR0_NUM_EVENTS_MASK; 1757b7d861d9SBoojin Kim val += 1; 1758f6f2421cSLars-Peter Clausen pl330->pcfg.num_events = val; 1759b7d861d9SBoojin Kim 1760f6f2421cSLars-Peter Clausen pl330->pcfg.irq_ns = readl(regs + CR3); 1761b7d861d9SBoojin Kim } 1762b7d861d9SBoojin Kim 1763b7d861d9SBoojin Kim static inline void _reset_thread(struct pl330_thread *thrd) 1764b7d861d9SBoojin Kim { 1765b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 1766b7d861d9SBoojin Kim 1767b7d861d9SBoojin Kim thrd->req[0].mc_cpu = pl330->mcode_cpu 1768f6f2421cSLars-Peter Clausen + (thrd->id * pl330->mcbufsz); 1769b7d861d9SBoojin Kim thrd->req[0].mc_bus = pl330->mcode_bus 1770f6f2421cSLars-Peter Clausen + (thrd->id * pl330->mcbufsz); 17719dc5a315SLars-Peter Clausen thrd->req[0].desc = NULL; 1772b7d861d9SBoojin Kim 1773b7d861d9SBoojin Kim thrd->req[1].mc_cpu = thrd->req[0].mc_cpu 1774f6f2421cSLars-Peter Clausen + pl330->mcbufsz / 2; 1775b7d861d9SBoojin Kim thrd->req[1].mc_bus = thrd->req[0].mc_bus 1776f6f2421cSLars-Peter Clausen + pl330->mcbufsz / 2; 17779dc5a315SLars-Peter Clausen thrd->req[1].desc = NULL; 17788ed30a14SLars-Peter Clausen 17798ed30a14SLars-Peter Clausen thrd->req_running = -1; 1780b7d861d9SBoojin Kim } 1781b7d861d9SBoojin Kim 1782b7d861d9SBoojin Kim static int dmac_alloc_threads(struct pl330_dmac *pl330) 1783b7d861d9SBoojin Kim { 1784f6f2421cSLars-Peter Clausen int chans = pl330->pcfg.num_chan; 1785b7d861d9SBoojin Kim struct pl330_thread *thrd; 1786b7d861d9SBoojin Kim int i; 1787b7d861d9SBoojin Kim 1788b7d861d9SBoojin Kim /* Allocate 1 Manager and 'chans' Channel threads */ 1789b7d861d9SBoojin Kim pl330->channels = kzalloc((1 + chans) * sizeof(*thrd), 1790b7d861d9SBoojin Kim GFP_KERNEL); 1791b7d861d9SBoojin Kim if (!pl330->channels) 1792b7d861d9SBoojin Kim return -ENOMEM; 1793b7d861d9SBoojin Kim 1794b7d861d9SBoojin Kim /* Init Channel threads */ 1795b7d861d9SBoojin Kim for (i = 0; i < chans; i++) { 1796b7d861d9SBoojin Kim thrd = &pl330->channels[i]; 1797b7d861d9SBoojin Kim thrd->id = i; 1798b7d861d9SBoojin Kim thrd->dmac = pl330; 1799b7d861d9SBoojin Kim _reset_thread(thrd); 1800b7d861d9SBoojin Kim thrd->free = true; 1801b7d861d9SBoojin Kim } 1802b7d861d9SBoojin Kim 1803b7d861d9SBoojin Kim /* MANAGER is indexed at the end */ 1804b7d861d9SBoojin Kim thrd = &pl330->channels[chans]; 1805b7d861d9SBoojin Kim thrd->id = chans; 1806b7d861d9SBoojin Kim thrd->dmac = pl330; 1807b7d861d9SBoojin Kim thrd->free = false; 1808b7d861d9SBoojin Kim pl330->manager = thrd; 1809b7d861d9SBoojin Kim 1810b7d861d9SBoojin Kim return 0; 1811b7d861d9SBoojin Kim } 1812b7d861d9SBoojin Kim 1813b7d861d9SBoojin Kim static int dmac_alloc_resources(struct pl330_dmac *pl330) 1814b7d861d9SBoojin Kim { 1815f6f2421cSLars-Peter Clausen int chans = pl330->pcfg.num_chan; 1816b7d861d9SBoojin Kim int ret; 1817b7d861d9SBoojin Kim 1818b7d861d9SBoojin Kim /* 1819b7d861d9SBoojin Kim * Alloc MicroCode buffer for 'chans' Channel threads. 1820b7d861d9SBoojin Kim * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN) 1821b7d861d9SBoojin Kim */ 1822f6f2421cSLars-Peter Clausen pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev, 1823f6f2421cSLars-Peter Clausen chans * pl330->mcbufsz, 1824b7d861d9SBoojin Kim &pl330->mcode_bus, GFP_KERNEL); 1825b7d861d9SBoojin Kim if (!pl330->mcode_cpu) { 1826f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n", 1827b7d861d9SBoojin Kim __func__, __LINE__); 1828b7d861d9SBoojin Kim return -ENOMEM; 1829b7d861d9SBoojin Kim } 1830b7d861d9SBoojin Kim 1831b7d861d9SBoojin Kim ret = dmac_alloc_threads(pl330); 1832b7d861d9SBoojin Kim if (ret) { 1833f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n", 1834b7d861d9SBoojin Kim __func__, __LINE__); 1835f6f2421cSLars-Peter Clausen dma_free_coherent(pl330->ddma.dev, 1836f6f2421cSLars-Peter Clausen chans * pl330->mcbufsz, 1837b7d861d9SBoojin Kim pl330->mcode_cpu, pl330->mcode_bus); 1838b7d861d9SBoojin Kim return ret; 1839b7d861d9SBoojin Kim } 1840b7d861d9SBoojin Kim 1841b7d861d9SBoojin Kim return 0; 1842b7d861d9SBoojin Kim } 1843b7d861d9SBoojin Kim 1844f6f2421cSLars-Peter Clausen static int pl330_add(struct pl330_dmac *pl330) 1845b7d861d9SBoojin Kim { 1846b7d861d9SBoojin Kim void __iomem *regs; 1847b7d861d9SBoojin Kim int i, ret; 1848b7d861d9SBoojin Kim 1849f6f2421cSLars-Peter Clausen regs = pl330->base; 1850b7d861d9SBoojin Kim 1851b7d861d9SBoojin Kim /* Check if we can handle this DMAC */ 1852f6f2421cSLars-Peter Clausen if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) { 1853f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n", 1854f6f2421cSLars-Peter Clausen pl330->pcfg.periph_id); 1855b7d861d9SBoojin Kim return -EINVAL; 1856b7d861d9SBoojin Kim } 1857b7d861d9SBoojin Kim 1858b7d861d9SBoojin Kim /* Read the configuration of the DMAC */ 1859f6f2421cSLars-Peter Clausen read_dmac_config(pl330); 1860b7d861d9SBoojin Kim 1861f6f2421cSLars-Peter Clausen if (pl330->pcfg.num_events == 0) { 1862f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n", 1863b7d861d9SBoojin Kim __func__, __LINE__); 1864b7d861d9SBoojin Kim return -EINVAL; 1865b7d861d9SBoojin Kim } 1866b7d861d9SBoojin Kim 1867b7d861d9SBoojin Kim spin_lock_init(&pl330->lock); 1868b7d861d9SBoojin Kim 1869b7d861d9SBoojin Kim INIT_LIST_HEAD(&pl330->req_done); 1870b7d861d9SBoojin Kim 1871b7d861d9SBoojin Kim /* Use default MC buffer size if not provided */ 1872f6f2421cSLars-Peter Clausen if (!pl330->mcbufsz) 1873f6f2421cSLars-Peter Clausen pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2; 1874b7d861d9SBoojin Kim 1875b7d861d9SBoojin Kim /* Mark all events as free */ 1876f6f2421cSLars-Peter Clausen for (i = 0; i < pl330->pcfg.num_events; i++) 1877b7d861d9SBoojin Kim pl330->events[i] = -1; 1878b7d861d9SBoojin Kim 1879b7d861d9SBoojin Kim /* Allocate resources needed by the DMAC */ 1880b7d861d9SBoojin Kim ret = dmac_alloc_resources(pl330); 1881b7d861d9SBoojin Kim if (ret) { 1882f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n"); 1883b7d861d9SBoojin Kim return ret; 1884b7d861d9SBoojin Kim } 1885b7d861d9SBoojin Kim 1886b7d861d9SBoojin Kim tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330); 1887b7d861d9SBoojin Kim 1888b7d861d9SBoojin Kim pl330->state = INIT; 1889b7d861d9SBoojin Kim 1890b7d861d9SBoojin Kim return 0; 1891b7d861d9SBoojin Kim } 1892b7d861d9SBoojin Kim 1893b7d861d9SBoojin Kim static int dmac_free_threads(struct pl330_dmac *pl330) 1894b7d861d9SBoojin Kim { 1895b7d861d9SBoojin Kim struct pl330_thread *thrd; 1896b7d861d9SBoojin Kim int i; 1897b7d861d9SBoojin Kim 1898b7d861d9SBoojin Kim /* Release Channel threads */ 1899f6f2421cSLars-Peter Clausen for (i = 0; i < pl330->pcfg.num_chan; i++) { 1900b7d861d9SBoojin Kim thrd = &pl330->channels[i]; 190165ad6060SLars-Peter Clausen pl330_release_channel(thrd); 1902b7d861d9SBoojin Kim } 1903b7d861d9SBoojin Kim 1904b7d861d9SBoojin Kim /* Free memory */ 1905b7d861d9SBoojin Kim kfree(pl330->channels); 1906b7d861d9SBoojin Kim 1907b7d861d9SBoojin Kim return 0; 1908b7d861d9SBoojin Kim } 1909b7d861d9SBoojin Kim 1910f6f2421cSLars-Peter Clausen static void pl330_del(struct pl330_dmac *pl330) 1911b7d861d9SBoojin Kim { 1912b7d861d9SBoojin Kim pl330->state = UNINIT; 1913b7d861d9SBoojin Kim 1914b7d861d9SBoojin Kim tasklet_kill(&pl330->tasks); 1915b7d861d9SBoojin Kim 1916b7d861d9SBoojin Kim /* Free DMAC resources */ 1917f6f2421cSLars-Peter Clausen dmac_free_threads(pl330); 1918b7d861d9SBoojin Kim 1919f6f2421cSLars-Peter Clausen dma_free_coherent(pl330->ddma.dev, 1920f6f2421cSLars-Peter Clausen pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu, 1921f6f2421cSLars-Peter Clausen pl330->mcode_bus); 1922b7d861d9SBoojin Kim } 1923b7d861d9SBoojin Kim 19243e2ec13aSThomas Abraham /* forward declaration */ 19253e2ec13aSThomas Abraham static struct amba_driver pl330_driver; 19263e2ec13aSThomas Abraham 1927b3040e40SJassi Brar static inline struct dma_pl330_chan * 1928b3040e40SJassi Brar to_pchan(struct dma_chan *ch) 1929b3040e40SJassi Brar { 1930b3040e40SJassi Brar if (!ch) 1931b3040e40SJassi Brar return NULL; 1932b3040e40SJassi Brar 1933b3040e40SJassi Brar return container_of(ch, struct dma_pl330_chan, chan); 1934b3040e40SJassi Brar } 1935b3040e40SJassi Brar 1936b3040e40SJassi Brar static inline struct dma_pl330_desc * 1937b3040e40SJassi Brar to_desc(struct dma_async_tx_descriptor *tx) 1938b3040e40SJassi Brar { 1939b3040e40SJassi Brar return container_of(tx, struct dma_pl330_desc, txd); 1940b3040e40SJassi Brar } 1941b3040e40SJassi Brar 1942b3040e40SJassi Brar static inline void fill_queue(struct dma_pl330_chan *pch) 1943b3040e40SJassi Brar { 1944b3040e40SJassi Brar struct dma_pl330_desc *desc; 1945b3040e40SJassi Brar int ret; 1946b3040e40SJassi Brar 1947b3040e40SJassi Brar list_for_each_entry(desc, &pch->work_list, node) { 1948b3040e40SJassi Brar 1949b3040e40SJassi Brar /* If already submitted */ 1950b3040e40SJassi Brar if (desc->status == BUSY) 195130fb980bSJassi Brar continue; 1952b3040e40SJassi Brar 19539dc5a315SLars-Peter Clausen ret = pl330_submit_req(pch->thread, desc); 1954b3040e40SJassi Brar if (!ret) { 1955b3040e40SJassi Brar desc->status = BUSY; 1956b3040e40SJassi Brar } else if (ret == -EAGAIN) { 1957b3040e40SJassi Brar /* QFull or DMAC Dying */ 1958b3040e40SJassi Brar break; 1959b3040e40SJassi Brar } else { 1960b3040e40SJassi Brar /* Unacceptable request */ 1961b3040e40SJassi Brar desc->status = DONE; 1962f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n", 1963b3040e40SJassi Brar __func__, __LINE__, desc->txd.cookie); 1964b3040e40SJassi Brar tasklet_schedule(&pch->task); 1965b3040e40SJassi Brar } 1966b3040e40SJassi Brar } 1967b3040e40SJassi Brar } 1968b3040e40SJassi Brar 1969b3040e40SJassi Brar static void pl330_tasklet(unsigned long data) 1970b3040e40SJassi Brar { 1971b3040e40SJassi Brar struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data; 1972b3040e40SJassi Brar struct dma_pl330_desc *desc, *_dt; 1973b3040e40SJassi Brar unsigned long flags; 1974ae43b328SKrzysztof Kozlowski bool power_down = false; 1975b3040e40SJassi Brar 1976b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 1977b3040e40SJassi Brar 1978b3040e40SJassi Brar /* Pick up ripe tomatoes */ 1979b3040e40SJassi Brar list_for_each_entry_safe(desc, _dt, &pch->work_list, node) 1980b3040e40SJassi Brar if (desc->status == DONE) { 198130c1dc0fSTushar Behera if (!pch->cyclic) 1982f7fbce07SRussell King - ARM Linux dma_cookie_complete(&desc->txd); 198339ff8613SLars-Peter Clausen list_move_tail(&desc->node, &pch->completed_list); 1984b3040e40SJassi Brar } 1985b3040e40SJassi Brar 1986b3040e40SJassi Brar /* Try to submit a req imm. next to the last completed cookie */ 1987b3040e40SJassi Brar fill_queue(pch); 1988b3040e40SJassi Brar 1989ae43b328SKrzysztof Kozlowski if (list_empty(&pch->work_list)) { 1990ae43b328SKrzysztof Kozlowski spin_lock(&pch->thread->dmac->lock); 1991ae43b328SKrzysztof Kozlowski _stop(pch->thread); 1992ae43b328SKrzysztof Kozlowski spin_unlock(&pch->thread->dmac->lock); 1993ae43b328SKrzysztof Kozlowski power_down = true; 1994ae43b328SKrzysztof Kozlowski } else { 1995b3040e40SJassi Brar /* Make sure the PL330 Channel thread is active */ 1996c26939e5SLars-Peter Clausen spin_lock(&pch->thread->dmac->lock); 1997c26939e5SLars-Peter Clausen _start(pch->thread); 1998c26939e5SLars-Peter Clausen spin_unlock(&pch->thread->dmac->lock); 1999ae43b328SKrzysztof Kozlowski } 2000b3040e40SJassi Brar 200139ff8613SLars-Peter Clausen while (!list_empty(&pch->completed_list)) { 200239ff8613SLars-Peter Clausen dma_async_tx_callback callback; 200339ff8613SLars-Peter Clausen void *callback_param; 2004b3040e40SJassi Brar 200539ff8613SLars-Peter Clausen desc = list_first_entry(&pch->completed_list, 200639ff8613SLars-Peter Clausen struct dma_pl330_desc, node); 200739ff8613SLars-Peter Clausen 200839ff8613SLars-Peter Clausen callback = desc->txd.callback; 200939ff8613SLars-Peter Clausen callback_param = desc->txd.callback_param; 201039ff8613SLars-Peter Clausen 201139ff8613SLars-Peter Clausen if (pch->cyclic) { 201239ff8613SLars-Peter Clausen desc->status = PREP; 201339ff8613SLars-Peter Clausen list_move_tail(&desc->node, &pch->work_list); 2014ae43b328SKrzysztof Kozlowski if (power_down) { 2015ae43b328SKrzysztof Kozlowski spin_lock(&pch->thread->dmac->lock); 2016ae43b328SKrzysztof Kozlowski _start(pch->thread); 2017ae43b328SKrzysztof Kozlowski spin_unlock(&pch->thread->dmac->lock); 2018ae43b328SKrzysztof Kozlowski power_down = false; 2019ae43b328SKrzysztof Kozlowski } 202039ff8613SLars-Peter Clausen } else { 202139ff8613SLars-Peter Clausen desc->status = FREE; 202239ff8613SLars-Peter Clausen list_move_tail(&desc->node, &pch->dmac->desc_pool); 202339ff8613SLars-Peter Clausen } 202439ff8613SLars-Peter Clausen 2025d38a8c62SDan Williams dma_descriptor_unmap(&desc->txd); 2026d38a8c62SDan Williams 202739ff8613SLars-Peter Clausen if (callback) { 202839ff8613SLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 202939ff8613SLars-Peter Clausen callback(callback_param); 203039ff8613SLars-Peter Clausen spin_lock_irqsave(&pch->lock, flags); 203139ff8613SLars-Peter Clausen } 203239ff8613SLars-Peter Clausen } 203339ff8613SLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 2034ae43b328SKrzysztof Kozlowski 2035ae43b328SKrzysztof Kozlowski /* If work list empty, power down */ 2036ae43b328SKrzysztof Kozlowski if (power_down) { 2037ae43b328SKrzysztof Kozlowski pm_runtime_mark_last_busy(pch->dmac->ddma.dev); 2038ae43b328SKrzysztof Kozlowski pm_runtime_put_autosuspend(pch->dmac->ddma.dev); 2039ae43b328SKrzysztof Kozlowski } 2040b3040e40SJassi Brar } 2041b3040e40SJassi Brar 20423e2ec13aSThomas Abraham bool pl330_filter(struct dma_chan *chan, void *param) 20433e2ec13aSThomas Abraham { 2044cd072515SThomas Abraham u8 *peri_id; 20453e2ec13aSThomas Abraham 20463e2ec13aSThomas Abraham if (chan->device->dev->driver != &pl330_driver.drv) 20473e2ec13aSThomas Abraham return false; 20483e2ec13aSThomas Abraham 2049cd072515SThomas Abraham peri_id = chan->private; 20502f986ec6SDan Carpenter return *peri_id == (unsigned long)param; 20513e2ec13aSThomas Abraham } 20523e2ec13aSThomas Abraham EXPORT_SYMBOL(pl330_filter); 20533e2ec13aSThomas Abraham 2054a80258f9SPadmavathi Venna static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec, 2055a80258f9SPadmavathi Venna struct of_dma *ofdma) 2056a80258f9SPadmavathi Venna { 2057a80258f9SPadmavathi Venna int count = dma_spec->args_count; 2058f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = ofdma->of_dma_data; 205970cbb163SLars-Peter Clausen unsigned int chan_id; 2060a80258f9SPadmavathi Venna 2061f6f2421cSLars-Peter Clausen if (!pl330) 2062f6f2421cSLars-Peter Clausen return NULL; 2063f6f2421cSLars-Peter Clausen 2064a80258f9SPadmavathi Venna if (count != 1) 2065a80258f9SPadmavathi Venna return NULL; 2066a80258f9SPadmavathi Venna 206770cbb163SLars-Peter Clausen chan_id = dma_spec->args[0]; 2068f6f2421cSLars-Peter Clausen if (chan_id >= pl330->num_peripherals) 206970cbb163SLars-Peter Clausen return NULL; 2070a80258f9SPadmavathi Venna 2071f6f2421cSLars-Peter Clausen return dma_get_slave_channel(&pl330->peripherals[chan_id].chan); 2072a80258f9SPadmavathi Venna } 2073a80258f9SPadmavathi Venna 2074b3040e40SJassi Brar static int pl330_alloc_chan_resources(struct dma_chan *chan) 2075b3040e40SJassi Brar { 2076b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2077f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2078b3040e40SJassi Brar unsigned long flags; 2079b3040e40SJassi Brar 2080b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2081b3040e40SJassi Brar 2082d3ee98cdSRussell King - ARM Linux dma_cookie_init(chan); 208342bc9cf4SBoojin Kim pch->cyclic = false; 2084b3040e40SJassi Brar 2085f6f2421cSLars-Peter Clausen pch->thread = pl330_request_channel(pl330); 208665ad6060SLars-Peter Clausen if (!pch->thread) { 2087b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 208802747885SInderpal Singh return -ENOMEM; 2089b3040e40SJassi Brar } 2090b3040e40SJassi Brar 2091b3040e40SJassi Brar tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch); 2092b3040e40SJassi Brar 2093b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 2094b3040e40SJassi Brar 2095b3040e40SJassi Brar return 1; 2096b3040e40SJassi Brar } 2097b3040e40SJassi Brar 2098740aa957SMaxime Ripard static int pl330_config(struct dma_chan *chan, 2099740aa957SMaxime Ripard struct dma_slave_config *slave_config) 2100740aa957SMaxime Ripard { 2101740aa957SMaxime Ripard struct dma_pl330_chan *pch = to_pchan(chan); 2102740aa957SMaxime Ripard 2103740aa957SMaxime Ripard if (slave_config->direction == DMA_MEM_TO_DEV) { 2104740aa957SMaxime Ripard if (slave_config->dst_addr) 2105740aa957SMaxime Ripard pch->fifo_addr = slave_config->dst_addr; 2106740aa957SMaxime Ripard if (slave_config->dst_addr_width) 2107740aa957SMaxime Ripard pch->burst_sz = __ffs(slave_config->dst_addr_width); 2108740aa957SMaxime Ripard if (slave_config->dst_maxburst) 2109740aa957SMaxime Ripard pch->burst_len = slave_config->dst_maxburst; 2110740aa957SMaxime Ripard } else if (slave_config->direction == DMA_DEV_TO_MEM) { 2111740aa957SMaxime Ripard if (slave_config->src_addr) 2112740aa957SMaxime Ripard pch->fifo_addr = slave_config->src_addr; 2113740aa957SMaxime Ripard if (slave_config->src_addr_width) 2114740aa957SMaxime Ripard pch->burst_sz = __ffs(slave_config->src_addr_width); 2115740aa957SMaxime Ripard if (slave_config->src_maxburst) 2116740aa957SMaxime Ripard pch->burst_len = slave_config->src_maxburst; 2117740aa957SMaxime Ripard } 2118740aa957SMaxime Ripard 2119740aa957SMaxime Ripard return 0; 2120740aa957SMaxime Ripard } 2121740aa957SMaxime Ripard 2122740aa957SMaxime Ripard static int pl330_terminate_all(struct dma_chan *chan) 2123b3040e40SJassi Brar { 2124b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 212539ff8613SLars-Peter Clausen struct dma_pl330_desc *desc; 2126b3040e40SJassi Brar unsigned long flags; 2127f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2128ae43b886SBoojin Kim LIST_HEAD(list); 2129b3040e40SJassi Brar 2130b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2131c26939e5SLars-Peter Clausen spin_lock(&pl330->lock); 2132c26939e5SLars-Peter Clausen _stop(pch->thread); 2133c26939e5SLars-Peter Clausen spin_unlock(&pl330->lock); 2134c26939e5SLars-Peter Clausen 2135c26939e5SLars-Peter Clausen pch->thread->req[0].desc = NULL; 2136c26939e5SLars-Peter Clausen pch->thread->req[1].desc = NULL; 2137c26939e5SLars-Peter Clausen pch->thread->req_running = -1; 2138b3040e40SJassi Brar 2139b3040e40SJassi Brar /* Mark all desc done */ 214004abf5daSLars-Peter Clausen list_for_each_entry(desc, &pch->submitted_list, node) { 214104abf5daSLars-Peter Clausen desc->status = FREE; 214204abf5daSLars-Peter Clausen dma_cookie_complete(&desc->txd); 214304abf5daSLars-Peter Clausen } 214404abf5daSLars-Peter Clausen 214539ff8613SLars-Peter Clausen list_for_each_entry(desc, &pch->work_list , node) { 214639ff8613SLars-Peter Clausen desc->status = FREE; 214739ff8613SLars-Peter Clausen dma_cookie_complete(&desc->txd); 2148ae43b886SBoojin Kim } 2149b3040e40SJassi Brar 2150f6f2421cSLars-Peter Clausen list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool); 2151f6f2421cSLars-Peter Clausen list_splice_tail_init(&pch->work_list, &pl330->desc_pool); 2152f6f2421cSLars-Peter Clausen list_splice_tail_init(&pch->completed_list, &pl330->desc_pool); 2153b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 2154b3040e40SJassi Brar 2155b3040e40SJassi Brar return 0; 2156b3040e40SJassi Brar } 2157b3040e40SJassi Brar 215888987d2cSRobert Baldyga /* 215988987d2cSRobert Baldyga * We don't support DMA_RESUME command because of hardware 216088987d2cSRobert Baldyga * limitations, so after pausing the channel we cannot restore 216188987d2cSRobert Baldyga * it to active state. We have to terminate channel and setup 216288987d2cSRobert Baldyga * DMA transfer again. This pause feature was implemented to 216388987d2cSRobert Baldyga * allow safely read residue before channel termination. 216488987d2cSRobert Baldyga */ 21655503aed8SBen Dooks static int pl330_pause(struct dma_chan *chan) 216688987d2cSRobert Baldyga { 216788987d2cSRobert Baldyga struct dma_pl330_chan *pch = to_pchan(chan); 216888987d2cSRobert Baldyga struct pl330_dmac *pl330 = pch->dmac; 216988987d2cSRobert Baldyga unsigned long flags; 217088987d2cSRobert Baldyga 217188987d2cSRobert Baldyga pm_runtime_get_sync(pl330->ddma.dev); 217288987d2cSRobert Baldyga spin_lock_irqsave(&pch->lock, flags); 217388987d2cSRobert Baldyga 217488987d2cSRobert Baldyga spin_lock(&pl330->lock); 217588987d2cSRobert Baldyga _stop(pch->thread); 217688987d2cSRobert Baldyga spin_unlock(&pl330->lock); 217788987d2cSRobert Baldyga 217888987d2cSRobert Baldyga spin_unlock_irqrestore(&pch->lock, flags); 217988987d2cSRobert Baldyga pm_runtime_mark_last_busy(pl330->ddma.dev); 218088987d2cSRobert Baldyga pm_runtime_put_autosuspend(pl330->ddma.dev); 218188987d2cSRobert Baldyga 218288987d2cSRobert Baldyga return 0; 218388987d2cSRobert Baldyga } 218488987d2cSRobert Baldyga 2185b3040e40SJassi Brar static void pl330_free_chan_resources(struct dma_chan *chan) 2186b3040e40SJassi Brar { 2187b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2188b3040e40SJassi Brar unsigned long flags; 2189b3040e40SJassi Brar 2190b3040e40SJassi Brar tasklet_kill(&pch->task); 2191b3040e40SJassi Brar 2192ae43b328SKrzysztof Kozlowski pm_runtime_get_sync(pch->dmac->ddma.dev); 2193da331ba8SBartlomiej Zolnierkiewicz spin_lock_irqsave(&pch->lock, flags); 2194da331ba8SBartlomiej Zolnierkiewicz 219565ad6060SLars-Peter Clausen pl330_release_channel(pch->thread); 219665ad6060SLars-Peter Clausen pch->thread = NULL; 2197b3040e40SJassi Brar 219842bc9cf4SBoojin Kim if (pch->cyclic) 219942bc9cf4SBoojin Kim list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); 220042bc9cf4SBoojin Kim 2201b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 2202ae43b328SKrzysztof Kozlowski pm_runtime_mark_last_busy(pch->dmac->ddma.dev); 2203ae43b328SKrzysztof Kozlowski pm_runtime_put_autosuspend(pch->dmac->ddma.dev); 2204b3040e40SJassi Brar } 2205b3040e40SJassi Brar 22065503aed8SBen Dooks static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch, 2207aee4d1faSRobert Baldyga struct dma_pl330_desc *desc) 2208aee4d1faSRobert Baldyga { 2209aee4d1faSRobert Baldyga struct pl330_thread *thrd = pch->thread; 2210aee4d1faSRobert Baldyga struct pl330_dmac *pl330 = pch->dmac; 2211aee4d1faSRobert Baldyga void __iomem *regs = thrd->dmac->base; 2212aee4d1faSRobert Baldyga u32 val, addr; 2213aee4d1faSRobert Baldyga 2214aee4d1faSRobert Baldyga pm_runtime_get_sync(pl330->ddma.dev); 2215aee4d1faSRobert Baldyga val = addr = 0; 2216aee4d1faSRobert Baldyga if (desc->rqcfg.src_inc) { 2217aee4d1faSRobert Baldyga val = readl(regs + SA(thrd->id)); 2218aee4d1faSRobert Baldyga addr = desc->px.src_addr; 2219aee4d1faSRobert Baldyga } else { 2220aee4d1faSRobert Baldyga val = readl(regs + DA(thrd->id)); 2221aee4d1faSRobert Baldyga addr = desc->px.dst_addr; 2222aee4d1faSRobert Baldyga } 2223aee4d1faSRobert Baldyga pm_runtime_mark_last_busy(pch->dmac->ddma.dev); 2224aee4d1faSRobert Baldyga pm_runtime_put_autosuspend(pl330->ddma.dev); 2225aee4d1faSRobert Baldyga return val - addr; 2226aee4d1faSRobert Baldyga } 2227aee4d1faSRobert Baldyga 2228b3040e40SJassi Brar static enum dma_status 2229b3040e40SJassi Brar pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, 2230b3040e40SJassi Brar struct dma_tx_state *txstate) 2231b3040e40SJassi Brar { 2232aee4d1faSRobert Baldyga enum dma_status ret; 2233aee4d1faSRobert Baldyga unsigned long flags; 2234aee4d1faSRobert Baldyga struct dma_pl330_desc *desc, *running = NULL; 2235aee4d1faSRobert Baldyga struct dma_pl330_chan *pch = to_pchan(chan); 2236aee4d1faSRobert Baldyga unsigned int transferred, residual = 0; 2237aee4d1faSRobert Baldyga 2238aee4d1faSRobert Baldyga ret = dma_cookie_status(chan, cookie, txstate); 2239aee4d1faSRobert Baldyga 2240aee4d1faSRobert Baldyga if (!txstate) 2241aee4d1faSRobert Baldyga return ret; 2242aee4d1faSRobert Baldyga 2243aee4d1faSRobert Baldyga if (ret == DMA_COMPLETE) 2244aee4d1faSRobert Baldyga goto out; 2245aee4d1faSRobert Baldyga 2246aee4d1faSRobert Baldyga spin_lock_irqsave(&pch->lock, flags); 2247aee4d1faSRobert Baldyga 2248aee4d1faSRobert Baldyga if (pch->thread->req_running != -1) 2249aee4d1faSRobert Baldyga running = pch->thread->req[pch->thread->req_running].desc; 2250aee4d1faSRobert Baldyga 2251aee4d1faSRobert Baldyga /* Check in pending list */ 2252aee4d1faSRobert Baldyga list_for_each_entry(desc, &pch->work_list, node) { 2253aee4d1faSRobert Baldyga if (desc->status == DONE) 2254aee4d1faSRobert Baldyga transferred = desc->bytes_requested; 2255aee4d1faSRobert Baldyga else if (running && desc == running) 2256aee4d1faSRobert Baldyga transferred = 2257aee4d1faSRobert Baldyga pl330_get_current_xferred_count(pch, desc); 2258aee4d1faSRobert Baldyga else 2259aee4d1faSRobert Baldyga transferred = 0; 2260aee4d1faSRobert Baldyga residual += desc->bytes_requested - transferred; 2261aee4d1faSRobert Baldyga if (desc->txd.cookie == cookie) { 226275967b78SBen Dooks switch (desc->status) { 226375967b78SBen Dooks case DONE: 226475967b78SBen Dooks ret = DMA_COMPLETE; 226575967b78SBen Dooks break; 226675967b78SBen Dooks case PREP: 226775967b78SBen Dooks case BUSY: 226875967b78SBen Dooks ret = DMA_IN_PROGRESS; 226975967b78SBen Dooks break; 227075967b78SBen Dooks default: 227175967b78SBen Dooks WARN_ON(1); 227275967b78SBen Dooks } 2273aee4d1faSRobert Baldyga break; 2274aee4d1faSRobert Baldyga } 2275aee4d1faSRobert Baldyga if (desc->last) 2276aee4d1faSRobert Baldyga residual = 0; 2277aee4d1faSRobert Baldyga } 2278aee4d1faSRobert Baldyga spin_unlock_irqrestore(&pch->lock, flags); 2279aee4d1faSRobert Baldyga 2280aee4d1faSRobert Baldyga out: 2281aee4d1faSRobert Baldyga dma_set_residue(txstate, residual); 2282aee4d1faSRobert Baldyga 2283aee4d1faSRobert Baldyga return ret; 2284b3040e40SJassi Brar } 2285b3040e40SJassi Brar 2286b3040e40SJassi Brar static void pl330_issue_pending(struct dma_chan *chan) 2287b3040e40SJassi Brar { 228804abf5daSLars-Peter Clausen struct dma_pl330_chan *pch = to_pchan(chan); 228904abf5daSLars-Peter Clausen unsigned long flags; 229004abf5daSLars-Peter Clausen 229104abf5daSLars-Peter Clausen spin_lock_irqsave(&pch->lock, flags); 2292ae43b328SKrzysztof Kozlowski if (list_empty(&pch->work_list)) { 2293ae43b328SKrzysztof Kozlowski /* 2294ae43b328SKrzysztof Kozlowski * Warn on nothing pending. Empty submitted_list may 2295ae43b328SKrzysztof Kozlowski * break our pm_runtime usage counter as it is 2296ae43b328SKrzysztof Kozlowski * updated on work_list emptiness status. 2297ae43b328SKrzysztof Kozlowski */ 2298ae43b328SKrzysztof Kozlowski WARN_ON(list_empty(&pch->submitted_list)); 2299ae43b328SKrzysztof Kozlowski pm_runtime_get_sync(pch->dmac->ddma.dev); 2300ae43b328SKrzysztof Kozlowski } 230104abf5daSLars-Peter Clausen list_splice_tail_init(&pch->submitted_list, &pch->work_list); 230204abf5daSLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 230304abf5daSLars-Peter Clausen 230404abf5daSLars-Peter Clausen pl330_tasklet((unsigned long)pch); 2305b3040e40SJassi Brar } 2306b3040e40SJassi Brar 2307b3040e40SJassi Brar /* 2308b3040e40SJassi Brar * We returned the last one of the circular list of descriptor(s) 2309b3040e40SJassi Brar * from prep_xxx, so the argument to submit corresponds to the last 2310b3040e40SJassi Brar * descriptor of the list. 2311b3040e40SJassi Brar */ 2312b3040e40SJassi Brar static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) 2313b3040e40SJassi Brar { 2314b3040e40SJassi Brar struct dma_pl330_desc *desc, *last = to_desc(tx); 2315b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(tx->chan); 2316b3040e40SJassi Brar dma_cookie_t cookie; 2317b3040e40SJassi Brar unsigned long flags; 2318b3040e40SJassi Brar 2319b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2320b3040e40SJassi Brar 2321b3040e40SJassi Brar /* Assign cookies to all nodes */ 2322b3040e40SJassi Brar while (!list_empty(&last->node)) { 2323b3040e40SJassi Brar desc = list_entry(last->node.next, struct dma_pl330_desc, node); 2324fc514460SLars-Peter Clausen if (pch->cyclic) { 2325fc514460SLars-Peter Clausen desc->txd.callback = last->txd.callback; 2326fc514460SLars-Peter Clausen desc->txd.callback_param = last->txd.callback_param; 2327fc514460SLars-Peter Clausen } 2328aee4d1faSRobert Baldyga last->last = false; 2329b3040e40SJassi Brar 2330884485e1SRussell King - ARM Linux dma_cookie_assign(&desc->txd); 2331b3040e40SJassi Brar 233204abf5daSLars-Peter Clausen list_move_tail(&desc->node, &pch->submitted_list); 2333b3040e40SJassi Brar } 2334b3040e40SJassi Brar 2335aee4d1faSRobert Baldyga last->last = true; 2336884485e1SRussell King - ARM Linux cookie = dma_cookie_assign(&last->txd); 233704abf5daSLars-Peter Clausen list_add_tail(&last->node, &pch->submitted_list); 2338b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 2339b3040e40SJassi Brar 2340b3040e40SJassi Brar return cookie; 2341b3040e40SJassi Brar } 2342b3040e40SJassi Brar 2343b3040e40SJassi Brar static inline void _init_desc(struct dma_pl330_desc *desc) 2344b3040e40SJassi Brar { 2345b3040e40SJassi Brar desc->rqcfg.swap = SWAP_NO; 2346f0564c7eSLars-Peter Clausen desc->rqcfg.scctl = CCTRL0; 2347f0564c7eSLars-Peter Clausen desc->rqcfg.dcctl = CCTRL0; 2348b3040e40SJassi Brar desc->txd.tx_submit = pl330_tx_submit; 2349b3040e40SJassi Brar 2350b3040e40SJassi Brar INIT_LIST_HEAD(&desc->node); 2351b3040e40SJassi Brar } 2352b3040e40SJassi Brar 2353b3040e40SJassi Brar /* Returns the number of descriptors added to the DMAC pool */ 2354f6f2421cSLars-Peter Clausen static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count) 2355b3040e40SJassi Brar { 2356b3040e40SJassi Brar struct dma_pl330_desc *desc; 2357b3040e40SJassi Brar unsigned long flags; 2358b3040e40SJassi Brar int i; 2359b3040e40SJassi Brar 23600baf8f6aSWill Deacon desc = kcalloc(count, sizeof(*desc), flg); 2361b3040e40SJassi Brar if (!desc) 2362b3040e40SJassi Brar return 0; 2363b3040e40SJassi Brar 2364f6f2421cSLars-Peter Clausen spin_lock_irqsave(&pl330->pool_lock, flags); 2365b3040e40SJassi Brar 2366b3040e40SJassi Brar for (i = 0; i < count; i++) { 2367b3040e40SJassi Brar _init_desc(&desc[i]); 2368f6f2421cSLars-Peter Clausen list_add_tail(&desc[i].node, &pl330->desc_pool); 2369b3040e40SJassi Brar } 2370b3040e40SJassi Brar 2371f6f2421cSLars-Peter Clausen spin_unlock_irqrestore(&pl330->pool_lock, flags); 2372b3040e40SJassi Brar 2373b3040e40SJassi Brar return count; 2374b3040e40SJassi Brar } 2375b3040e40SJassi Brar 2376f6f2421cSLars-Peter Clausen static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330) 2377b3040e40SJassi Brar { 2378b3040e40SJassi Brar struct dma_pl330_desc *desc = NULL; 2379b3040e40SJassi Brar unsigned long flags; 2380b3040e40SJassi Brar 2381f6f2421cSLars-Peter Clausen spin_lock_irqsave(&pl330->pool_lock, flags); 2382b3040e40SJassi Brar 2383f6f2421cSLars-Peter Clausen if (!list_empty(&pl330->desc_pool)) { 2384f6f2421cSLars-Peter Clausen desc = list_entry(pl330->desc_pool.next, 2385b3040e40SJassi Brar struct dma_pl330_desc, node); 2386b3040e40SJassi Brar 2387b3040e40SJassi Brar list_del_init(&desc->node); 2388b3040e40SJassi Brar 2389b3040e40SJassi Brar desc->status = PREP; 2390b3040e40SJassi Brar desc->txd.callback = NULL; 2391b3040e40SJassi Brar } 2392b3040e40SJassi Brar 2393f6f2421cSLars-Peter Clausen spin_unlock_irqrestore(&pl330->pool_lock, flags); 2394b3040e40SJassi Brar 2395b3040e40SJassi Brar return desc; 2396b3040e40SJassi Brar } 2397b3040e40SJassi Brar 2398b3040e40SJassi Brar static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) 2399b3040e40SJassi Brar { 2400f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2401cd072515SThomas Abraham u8 *peri_id = pch->chan.private; 2402b3040e40SJassi Brar struct dma_pl330_desc *desc; 2403b3040e40SJassi Brar 2404b3040e40SJassi Brar /* Pluck one desc from the pool of DMAC */ 2405f6f2421cSLars-Peter Clausen desc = pluck_desc(pl330); 2406b3040e40SJassi Brar 2407b3040e40SJassi Brar /* If the DMAC pool is empty, alloc new */ 2408b3040e40SJassi Brar if (!desc) { 2409f6f2421cSLars-Peter Clausen if (!add_desc(pl330, GFP_ATOMIC, 1)) 2410b3040e40SJassi Brar return NULL; 2411b3040e40SJassi Brar 2412b3040e40SJassi Brar /* Try again */ 2413f6f2421cSLars-Peter Clausen desc = pluck_desc(pl330); 2414b3040e40SJassi Brar if (!desc) { 2415f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, 2416b3040e40SJassi Brar "%s:%d ALERT!\n", __func__, __LINE__); 2417b3040e40SJassi Brar return NULL; 2418b3040e40SJassi Brar } 2419b3040e40SJassi Brar } 2420b3040e40SJassi Brar 2421b3040e40SJassi Brar /* Initialize the descriptor */ 2422b3040e40SJassi Brar desc->pchan = pch; 2423b3040e40SJassi Brar desc->txd.cookie = 0; 2424b3040e40SJassi Brar async_tx_ack(&desc->txd); 2425b3040e40SJassi Brar 24269dc5a315SLars-Peter Clausen desc->peri = peri_id ? pch->chan.chan_id : 0; 2427f6f2421cSLars-Peter Clausen desc->rqcfg.pcfg = &pch->dmac->pcfg; 2428b3040e40SJassi Brar 2429b3040e40SJassi Brar dma_async_tx_descriptor_init(&desc->txd, &pch->chan); 2430b3040e40SJassi Brar 2431b3040e40SJassi Brar return desc; 2432b3040e40SJassi Brar } 2433b3040e40SJassi Brar 2434b3040e40SJassi Brar static inline void fill_px(struct pl330_xfer *px, 2435b3040e40SJassi Brar dma_addr_t dst, dma_addr_t src, size_t len) 2436b3040e40SJassi Brar { 2437b3040e40SJassi Brar px->bytes = len; 2438b3040e40SJassi Brar px->dst_addr = dst; 2439b3040e40SJassi Brar px->src_addr = src; 2440b3040e40SJassi Brar } 2441b3040e40SJassi Brar 2442b3040e40SJassi Brar static struct dma_pl330_desc * 2443b3040e40SJassi Brar __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, 2444b3040e40SJassi Brar dma_addr_t src, size_t len) 2445b3040e40SJassi Brar { 2446b3040e40SJassi Brar struct dma_pl330_desc *desc = pl330_get_desc(pch); 2447b3040e40SJassi Brar 2448b3040e40SJassi Brar if (!desc) { 2449f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", 2450b3040e40SJassi Brar __func__, __LINE__); 2451b3040e40SJassi Brar return NULL; 2452b3040e40SJassi Brar } 2453b3040e40SJassi Brar 2454b3040e40SJassi Brar /* 2455b3040e40SJassi Brar * Ideally we should lookout for reqs bigger than 2456b3040e40SJassi Brar * those that can be programmed with 256 bytes of 2457b3040e40SJassi Brar * MC buffer, but considering a req size is seldom 2458b3040e40SJassi Brar * going to be word-unaligned and more than 200MB, 2459b3040e40SJassi Brar * we take it easy. 2460b3040e40SJassi Brar * Also, should the limit is reached we'd rather 2461b3040e40SJassi Brar * have the platform increase MC buffer size than 2462b3040e40SJassi Brar * complicating this API driver. 2463b3040e40SJassi Brar */ 2464b3040e40SJassi Brar fill_px(&desc->px, dst, src, len); 2465b3040e40SJassi Brar 2466b3040e40SJassi Brar return desc; 2467b3040e40SJassi Brar } 2468b3040e40SJassi Brar 2469b3040e40SJassi Brar /* Call after fixing burst size */ 2470b3040e40SJassi Brar static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) 2471b3040e40SJassi Brar { 2472b3040e40SJassi Brar struct dma_pl330_chan *pch = desc->pchan; 2473f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2474b3040e40SJassi Brar int burst_len; 2475b3040e40SJassi Brar 2476f6f2421cSLars-Peter Clausen burst_len = pl330->pcfg.data_bus_width / 8; 2477c27f9556SJon Medhurst burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan; 2478b3040e40SJassi Brar burst_len >>= desc->rqcfg.brst_size; 2479b3040e40SJassi Brar 2480b3040e40SJassi Brar /* src/dst_burst_len can't be more than 16 */ 2481b3040e40SJassi Brar if (burst_len > 16) 2482b3040e40SJassi Brar burst_len = 16; 2483b3040e40SJassi Brar 2484b3040e40SJassi Brar while (burst_len > 1) { 2485b3040e40SJassi Brar if (!(len % (burst_len << desc->rqcfg.brst_size))) 2486b3040e40SJassi Brar break; 2487b3040e40SJassi Brar burst_len--; 2488b3040e40SJassi Brar } 2489b3040e40SJassi Brar 2490b3040e40SJassi Brar return burst_len; 2491b3040e40SJassi Brar } 2492b3040e40SJassi Brar 249342bc9cf4SBoojin Kim static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( 249442bc9cf4SBoojin Kim struct dma_chan *chan, dma_addr_t dma_addr, size_t len, 2495185ecb5fSAlexandre Bounine size_t period_len, enum dma_transfer_direction direction, 249631c1e5a1SLaurent Pinchart unsigned long flags) 249742bc9cf4SBoojin Kim { 2498fc514460SLars-Peter Clausen struct dma_pl330_desc *desc = NULL, *first = NULL; 249942bc9cf4SBoojin Kim struct dma_pl330_chan *pch = to_pchan(chan); 2500f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2501fc514460SLars-Peter Clausen unsigned int i; 250242bc9cf4SBoojin Kim dma_addr_t dst; 250342bc9cf4SBoojin Kim dma_addr_t src; 250442bc9cf4SBoojin Kim 2505fc514460SLars-Peter Clausen if (len % period_len != 0) 2506fc514460SLars-Peter Clausen return NULL; 2507fc514460SLars-Peter Clausen 2508fc514460SLars-Peter Clausen if (!is_slave_direction(direction)) { 2509f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n", 2510fc514460SLars-Peter Clausen __func__, __LINE__); 2511fc514460SLars-Peter Clausen return NULL; 2512fc514460SLars-Peter Clausen } 2513fc514460SLars-Peter Clausen 2514fc514460SLars-Peter Clausen for (i = 0; i < len / period_len; i++) { 251542bc9cf4SBoojin Kim desc = pl330_get_desc(pch); 251642bc9cf4SBoojin Kim if (!desc) { 2517f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", 251842bc9cf4SBoojin Kim __func__, __LINE__); 2519fc514460SLars-Peter Clausen 2520fc514460SLars-Peter Clausen if (!first) 2521fc514460SLars-Peter Clausen return NULL; 2522fc514460SLars-Peter Clausen 2523f6f2421cSLars-Peter Clausen spin_lock_irqsave(&pl330->pool_lock, flags); 2524fc514460SLars-Peter Clausen 2525fc514460SLars-Peter Clausen while (!list_empty(&first->node)) { 2526fc514460SLars-Peter Clausen desc = list_entry(first->node.next, 2527fc514460SLars-Peter Clausen struct dma_pl330_desc, node); 2528f6f2421cSLars-Peter Clausen list_move_tail(&desc->node, &pl330->desc_pool); 2529fc514460SLars-Peter Clausen } 2530fc514460SLars-Peter Clausen 2531f6f2421cSLars-Peter Clausen list_move_tail(&first->node, &pl330->desc_pool); 2532fc514460SLars-Peter Clausen 2533f6f2421cSLars-Peter Clausen spin_unlock_irqrestore(&pl330->pool_lock, flags); 2534fc514460SLars-Peter Clausen 253542bc9cf4SBoojin Kim return NULL; 253642bc9cf4SBoojin Kim } 253742bc9cf4SBoojin Kim 253842bc9cf4SBoojin Kim switch (direction) { 2539db8196dfSVinod Koul case DMA_MEM_TO_DEV: 254042bc9cf4SBoojin Kim desc->rqcfg.src_inc = 1; 254142bc9cf4SBoojin Kim desc->rqcfg.dst_inc = 0; 254242bc9cf4SBoojin Kim src = dma_addr; 254342bc9cf4SBoojin Kim dst = pch->fifo_addr; 254442bc9cf4SBoojin Kim break; 2545db8196dfSVinod Koul case DMA_DEV_TO_MEM: 254642bc9cf4SBoojin Kim desc->rqcfg.src_inc = 0; 254742bc9cf4SBoojin Kim desc->rqcfg.dst_inc = 1; 254842bc9cf4SBoojin Kim src = pch->fifo_addr; 254942bc9cf4SBoojin Kim dst = dma_addr; 255042bc9cf4SBoojin Kim break; 255142bc9cf4SBoojin Kim default: 2552fc514460SLars-Peter Clausen break; 255342bc9cf4SBoojin Kim } 255442bc9cf4SBoojin Kim 25559dc5a315SLars-Peter Clausen desc->rqtype = direction; 255642bc9cf4SBoojin Kim desc->rqcfg.brst_size = pch->burst_sz; 255742bc9cf4SBoojin Kim desc->rqcfg.brst_len = 1; 2558aee4d1faSRobert Baldyga desc->bytes_requested = period_len; 2559fc514460SLars-Peter Clausen fill_px(&desc->px, dst, src, period_len); 2560fc514460SLars-Peter Clausen 2561fc514460SLars-Peter Clausen if (!first) 2562fc514460SLars-Peter Clausen first = desc; 2563fc514460SLars-Peter Clausen else 2564fc514460SLars-Peter Clausen list_add_tail(&desc->node, &first->node); 2565fc514460SLars-Peter Clausen 2566fc514460SLars-Peter Clausen dma_addr += period_len; 2567fc514460SLars-Peter Clausen } 2568fc514460SLars-Peter Clausen 2569fc514460SLars-Peter Clausen if (!desc) 2570fc514460SLars-Peter Clausen return NULL; 257142bc9cf4SBoojin Kim 257242bc9cf4SBoojin Kim pch->cyclic = true; 2573fc514460SLars-Peter Clausen desc->txd.flags = flags; 257442bc9cf4SBoojin Kim 257542bc9cf4SBoojin Kim return &desc->txd; 257642bc9cf4SBoojin Kim } 257742bc9cf4SBoojin Kim 2578b3040e40SJassi Brar static struct dma_async_tx_descriptor * 2579b3040e40SJassi Brar pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, 2580b3040e40SJassi Brar dma_addr_t src, size_t len, unsigned long flags) 2581b3040e40SJassi Brar { 2582b3040e40SJassi Brar struct dma_pl330_desc *desc; 2583b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2584f5636854SManinder Singh struct pl330_dmac *pl330; 2585b3040e40SJassi Brar int burst; 2586b3040e40SJassi Brar 25874e0e6109SRob Herring if (unlikely(!pch || !len)) 2588b3040e40SJassi Brar return NULL; 2589b3040e40SJassi Brar 2590f5636854SManinder Singh pl330 = pch->dmac; 2591f5636854SManinder Singh 2592b3040e40SJassi Brar desc = __pl330_prep_dma_memcpy(pch, dst, src, len); 2593b3040e40SJassi Brar if (!desc) 2594b3040e40SJassi Brar return NULL; 2595b3040e40SJassi Brar 2596b3040e40SJassi Brar desc->rqcfg.src_inc = 1; 2597b3040e40SJassi Brar desc->rqcfg.dst_inc = 1; 25989dc5a315SLars-Peter Clausen desc->rqtype = DMA_MEM_TO_MEM; 2599b3040e40SJassi Brar 2600b3040e40SJassi Brar /* Select max possible burst size */ 2601f6f2421cSLars-Peter Clausen burst = pl330->pcfg.data_bus_width / 8; 2602b3040e40SJassi Brar 2603137bd110SJon Medhurst /* 2604137bd110SJon Medhurst * Make sure we use a burst size that aligns with all the memcpy 2605137bd110SJon Medhurst * parameters because our DMA programming algorithm doesn't cope with 2606137bd110SJon Medhurst * transfers which straddle an entry in the DMA device's MFIFO. 2607137bd110SJon Medhurst */ 2608137bd110SJon Medhurst while ((src | dst | len) & (burst - 1)) 2609b3040e40SJassi Brar burst /= 2; 2610b3040e40SJassi Brar 2611b3040e40SJassi Brar desc->rqcfg.brst_size = 0; 2612b3040e40SJassi Brar while (burst != (1 << desc->rqcfg.brst_size)) 2613b3040e40SJassi Brar desc->rqcfg.brst_size++; 2614b3040e40SJassi Brar 2615137bd110SJon Medhurst /* 2616137bd110SJon Medhurst * If burst size is smaller than bus width then make sure we only 2617137bd110SJon Medhurst * transfer one at a time to avoid a burst stradling an MFIFO entry. 2618137bd110SJon Medhurst */ 2619137bd110SJon Medhurst if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width) 2620137bd110SJon Medhurst desc->rqcfg.brst_len = 1; 2621137bd110SJon Medhurst 2622b3040e40SJassi Brar desc->rqcfg.brst_len = get_burst_len(desc, len); 2623b3040e40SJassi Brar 2624b3040e40SJassi Brar desc->txd.flags = flags; 2625b3040e40SJassi Brar 2626b3040e40SJassi Brar return &desc->txd; 2627b3040e40SJassi Brar } 2628b3040e40SJassi Brar 2629f6f2421cSLars-Peter Clausen static void __pl330_giveback_desc(struct pl330_dmac *pl330, 263052a9d179SChanho Park struct dma_pl330_desc *first) 263152a9d179SChanho Park { 263252a9d179SChanho Park unsigned long flags; 263352a9d179SChanho Park struct dma_pl330_desc *desc; 263452a9d179SChanho Park 263552a9d179SChanho Park if (!first) 263652a9d179SChanho Park return; 263752a9d179SChanho Park 2638f6f2421cSLars-Peter Clausen spin_lock_irqsave(&pl330->pool_lock, flags); 263952a9d179SChanho Park 264052a9d179SChanho Park while (!list_empty(&first->node)) { 264152a9d179SChanho Park desc = list_entry(first->node.next, 264252a9d179SChanho Park struct dma_pl330_desc, node); 2643f6f2421cSLars-Peter Clausen list_move_tail(&desc->node, &pl330->desc_pool); 264452a9d179SChanho Park } 264552a9d179SChanho Park 2646f6f2421cSLars-Peter Clausen list_move_tail(&first->node, &pl330->desc_pool); 264752a9d179SChanho Park 2648f6f2421cSLars-Peter Clausen spin_unlock_irqrestore(&pl330->pool_lock, flags); 264952a9d179SChanho Park } 265052a9d179SChanho Park 2651b3040e40SJassi Brar static struct dma_async_tx_descriptor * 2652b3040e40SJassi Brar pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 2653db8196dfSVinod Koul unsigned int sg_len, enum dma_transfer_direction direction, 2654185ecb5fSAlexandre Bounine unsigned long flg, void *context) 2655b3040e40SJassi Brar { 2656b3040e40SJassi Brar struct dma_pl330_desc *first, *desc = NULL; 2657b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2658b3040e40SJassi Brar struct scatterlist *sg; 26591b9bb715SBoojin Kim int i; 2660b3040e40SJassi Brar dma_addr_t addr; 2661b3040e40SJassi Brar 2662cd072515SThomas Abraham if (unlikely(!pch || !sgl || !sg_len)) 2663b3040e40SJassi Brar return NULL; 2664b3040e40SJassi Brar 26651b9bb715SBoojin Kim addr = pch->fifo_addr; 2666b3040e40SJassi Brar 2667b3040e40SJassi Brar first = NULL; 2668b3040e40SJassi Brar 2669b3040e40SJassi Brar for_each_sg(sgl, sg, sg_len, i) { 2670b3040e40SJassi Brar 2671b3040e40SJassi Brar desc = pl330_get_desc(pch); 2672b3040e40SJassi Brar if (!desc) { 2673f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2674b3040e40SJassi Brar 2675f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, 2676b3040e40SJassi Brar "%s:%d Unable to fetch desc\n", 2677b3040e40SJassi Brar __func__, __LINE__); 2678f6f2421cSLars-Peter Clausen __pl330_giveback_desc(pl330, first); 2679b3040e40SJassi Brar 2680b3040e40SJassi Brar return NULL; 2681b3040e40SJassi Brar } 2682b3040e40SJassi Brar 2683b3040e40SJassi Brar if (!first) 2684b3040e40SJassi Brar first = desc; 2685b3040e40SJassi Brar else 2686b3040e40SJassi Brar list_add_tail(&desc->node, &first->node); 2687b3040e40SJassi Brar 2688db8196dfSVinod Koul if (direction == DMA_MEM_TO_DEV) { 2689b3040e40SJassi Brar desc->rqcfg.src_inc = 1; 2690b3040e40SJassi Brar desc->rqcfg.dst_inc = 0; 2691b3040e40SJassi Brar fill_px(&desc->px, 2692b3040e40SJassi Brar addr, sg_dma_address(sg), sg_dma_len(sg)); 2693b3040e40SJassi Brar } else { 2694b3040e40SJassi Brar desc->rqcfg.src_inc = 0; 2695b3040e40SJassi Brar desc->rqcfg.dst_inc = 1; 2696b3040e40SJassi Brar fill_px(&desc->px, 2697b3040e40SJassi Brar sg_dma_address(sg), addr, sg_dma_len(sg)); 2698b3040e40SJassi Brar } 2699b3040e40SJassi Brar 27001b9bb715SBoojin Kim desc->rqcfg.brst_size = pch->burst_sz; 2701b3040e40SJassi Brar desc->rqcfg.brst_len = 1; 27029dc5a315SLars-Peter Clausen desc->rqtype = direction; 2703aee4d1faSRobert Baldyga desc->bytes_requested = sg_dma_len(sg); 2704b3040e40SJassi Brar } 2705b3040e40SJassi Brar 2706b3040e40SJassi Brar /* Return the last desc in the chain */ 2707b3040e40SJassi Brar desc->txd.flags = flg; 2708b3040e40SJassi Brar return &desc->txd; 2709b3040e40SJassi Brar } 2710b3040e40SJassi Brar 2711b3040e40SJassi Brar static irqreturn_t pl330_irq_handler(int irq, void *data) 2712b3040e40SJassi Brar { 2713b3040e40SJassi Brar if (pl330_update(data)) 2714b3040e40SJassi Brar return IRQ_HANDLED; 2715b3040e40SJassi Brar else 2716b3040e40SJassi Brar return IRQ_NONE; 2717b3040e40SJassi Brar } 2718b3040e40SJassi Brar 2719ca38ff13SLars-Peter Clausen #define PL330_DMA_BUSWIDTHS \ 2720ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ 2721ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 2722ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 2723ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ 2724ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) 2725ca38ff13SLars-Peter Clausen 2726b816ccc5SKrzysztof Kozlowski /* 2727b816ccc5SKrzysztof Kozlowski * Runtime PM callbacks are provided by amba/bus.c driver. 2728b816ccc5SKrzysztof Kozlowski * 2729b816ccc5SKrzysztof Kozlowski * It is assumed here that IRQ safe runtime PM is chosen in probe and amba 2730b816ccc5SKrzysztof Kozlowski * bus driver will only disable/enable the clock in runtime PM callbacks. 2731b816ccc5SKrzysztof Kozlowski */ 2732b816ccc5SKrzysztof Kozlowski static int __maybe_unused pl330_suspend(struct device *dev) 2733b816ccc5SKrzysztof Kozlowski { 2734b816ccc5SKrzysztof Kozlowski struct amba_device *pcdev = to_amba_device(dev); 2735b816ccc5SKrzysztof Kozlowski 2736b816ccc5SKrzysztof Kozlowski pm_runtime_disable(dev); 2737b816ccc5SKrzysztof Kozlowski 2738b816ccc5SKrzysztof Kozlowski if (!pm_runtime_status_suspended(dev)) { 2739b816ccc5SKrzysztof Kozlowski /* amba did not disable the clock */ 2740b816ccc5SKrzysztof Kozlowski amba_pclk_disable(pcdev); 2741b816ccc5SKrzysztof Kozlowski } 2742b816ccc5SKrzysztof Kozlowski amba_pclk_unprepare(pcdev); 2743b816ccc5SKrzysztof Kozlowski 2744b816ccc5SKrzysztof Kozlowski return 0; 2745b816ccc5SKrzysztof Kozlowski } 2746b816ccc5SKrzysztof Kozlowski 2747b816ccc5SKrzysztof Kozlowski static int __maybe_unused pl330_resume(struct device *dev) 2748b816ccc5SKrzysztof Kozlowski { 2749b816ccc5SKrzysztof Kozlowski struct amba_device *pcdev = to_amba_device(dev); 2750b816ccc5SKrzysztof Kozlowski int ret; 2751b816ccc5SKrzysztof Kozlowski 2752b816ccc5SKrzysztof Kozlowski ret = amba_pclk_prepare(pcdev); 2753b816ccc5SKrzysztof Kozlowski if (ret) 2754b816ccc5SKrzysztof Kozlowski return ret; 2755b816ccc5SKrzysztof Kozlowski 2756b816ccc5SKrzysztof Kozlowski if (!pm_runtime_status_suspended(dev)) 2757b816ccc5SKrzysztof Kozlowski ret = amba_pclk_enable(pcdev); 2758b816ccc5SKrzysztof Kozlowski 2759b816ccc5SKrzysztof Kozlowski pm_runtime_enable(dev); 2760b816ccc5SKrzysztof Kozlowski 2761b816ccc5SKrzysztof Kozlowski return ret; 2762b816ccc5SKrzysztof Kozlowski } 2763b816ccc5SKrzysztof Kozlowski 2764b816ccc5SKrzysztof Kozlowski static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume); 2765b816ccc5SKrzysztof Kozlowski 2766463a1f8bSBill Pemberton static int 2767aa25afadSRussell King pl330_probe(struct amba_device *adev, const struct amba_id *id) 2768b3040e40SJassi Brar { 2769b3040e40SJassi Brar struct dma_pl330_platdata *pdat; 2770f6f2421cSLars-Peter Clausen struct pl330_config *pcfg; 2771f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330; 27720b94c577SPadmavathi Venna struct dma_pl330_chan *pch, *_p; 2773b3040e40SJassi Brar struct dma_device *pd; 2774b3040e40SJassi Brar struct resource *res; 2775b3040e40SJassi Brar int i, ret, irq; 27764e0e6109SRob Herring int num_chan; 2777b3040e40SJassi Brar 2778d4adcc01SJingoo Han pdat = dev_get_platdata(&adev->dev); 2779b3040e40SJassi Brar 278064113016SRussell King ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32)); 278164113016SRussell King if (ret) 278264113016SRussell King return ret; 278364113016SRussell King 2784b3040e40SJassi Brar /* Allocate a new DMAC and its Channels */ 2785f6f2421cSLars-Peter Clausen pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL); 2786f6f2421cSLars-Peter Clausen if (!pl330) { 2787b3040e40SJassi Brar dev_err(&adev->dev, "unable to allocate mem\n"); 2788b3040e40SJassi Brar return -ENOMEM; 2789b3040e40SJassi Brar } 2790b3040e40SJassi Brar 2791cee42392SAndrew Jackson pd = &pl330->ddma; 2792cee42392SAndrew Jackson pd->dev = &adev->dev; 2793cee42392SAndrew Jackson 2794f6f2421cSLars-Peter Clausen pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0; 2795b3040e40SJassi Brar 2796b3040e40SJassi Brar res = &adev->res; 2797f6f2421cSLars-Peter Clausen pl330->base = devm_ioremap_resource(&adev->dev, res); 2798f6f2421cSLars-Peter Clausen if (IS_ERR(pl330->base)) 2799f6f2421cSLars-Peter Clausen return PTR_ERR(pl330->base); 2800b3040e40SJassi Brar 2801f6f2421cSLars-Peter Clausen amba_set_drvdata(adev, pl330); 2802a2f5203fSBoojin Kim 280302808b42SDan Carpenter for (i = 0; i < AMBA_NR_IRQS; i++) { 2804e98b3cafSMichal Simek irq = adev->irq[i]; 2805e98b3cafSMichal Simek if (irq) { 2806e98b3cafSMichal Simek ret = devm_request_irq(&adev->dev, irq, 2807e98b3cafSMichal Simek pl330_irq_handler, 0, 2808f6f2421cSLars-Peter Clausen dev_name(&adev->dev), pl330); 2809b3040e40SJassi Brar if (ret) 2810e4d43c17SSachin Kamat return ret; 2811e98b3cafSMichal Simek } else { 2812e98b3cafSMichal Simek break; 2813e98b3cafSMichal Simek } 2814e98b3cafSMichal Simek } 2815b3040e40SJassi Brar 2816f6f2421cSLars-Peter Clausen pcfg = &pl330->pcfg; 2817f6f2421cSLars-Peter Clausen 2818f6f2421cSLars-Peter Clausen pcfg->periph_id = adev->periphid; 2819f6f2421cSLars-Peter Clausen ret = pl330_add(pl330); 2820b3040e40SJassi Brar if (ret) 2821173e838cSMichal Simek return ret; 2822b3040e40SJassi Brar 2823f6f2421cSLars-Peter Clausen INIT_LIST_HEAD(&pl330->desc_pool); 2824f6f2421cSLars-Peter Clausen spin_lock_init(&pl330->pool_lock); 2825b3040e40SJassi Brar 2826b3040e40SJassi Brar /* Create a descriptor pool of default size */ 2827f6f2421cSLars-Peter Clausen if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC)) 2828b3040e40SJassi Brar dev_warn(&adev->dev, "unable to allocate desc\n"); 2829b3040e40SJassi Brar 2830b3040e40SJassi Brar INIT_LIST_HEAD(&pd->channels); 2831b3040e40SJassi Brar 2832b3040e40SJassi Brar /* Initialize channel parameters */ 2833c8473828SOlof Johansson if (pdat) 2834f6f2421cSLars-Peter Clausen num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan); 2835c8473828SOlof Johansson else 2836f6f2421cSLars-Peter Clausen num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan); 2837c8473828SOlof Johansson 2838f6f2421cSLars-Peter Clausen pl330->num_peripherals = num_chan; 283970cbb163SLars-Peter Clausen 2840f6f2421cSLars-Peter Clausen pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL); 2841f6f2421cSLars-Peter Clausen if (!pl330->peripherals) { 284261c6e753SSachin Kamat ret = -ENOMEM; 2843f6f2421cSLars-Peter Clausen dev_err(&adev->dev, "unable to allocate pl330->peripherals\n"); 2844e4d43c17SSachin Kamat goto probe_err2; 284561c6e753SSachin Kamat } 28464e0e6109SRob Herring 28474e0e6109SRob Herring for (i = 0; i < num_chan; i++) { 2848f6f2421cSLars-Peter Clausen pch = &pl330->peripherals[i]; 284993ed5544SThomas Abraham if (!adev->dev.of_node) 2850cd072515SThomas Abraham pch->chan.private = pdat ? &pdat->peri_id[i] : NULL; 285193ed5544SThomas Abraham else 285293ed5544SThomas Abraham pch->chan.private = adev->dev.of_node; 2853b3040e40SJassi Brar 285404abf5daSLars-Peter Clausen INIT_LIST_HEAD(&pch->submitted_list); 2855b3040e40SJassi Brar INIT_LIST_HEAD(&pch->work_list); 285639ff8613SLars-Peter Clausen INIT_LIST_HEAD(&pch->completed_list); 2857b3040e40SJassi Brar spin_lock_init(&pch->lock); 285865ad6060SLars-Peter Clausen pch->thread = NULL; 2859b3040e40SJassi Brar pch->chan.device = pd; 2860f6f2421cSLars-Peter Clausen pch->dmac = pl330; 2861b3040e40SJassi Brar 2862b3040e40SJassi Brar /* Add the channel to the DMAC list */ 2863b3040e40SJassi Brar list_add_tail(&pch->chan.device_node, &pd->channels); 2864b3040e40SJassi Brar } 2865b3040e40SJassi Brar 286693ed5544SThomas Abraham if (pdat) { 2867cd072515SThomas Abraham pd->cap_mask = pdat->cap_mask; 286893ed5544SThomas Abraham } else { 2869cd072515SThomas Abraham dma_cap_set(DMA_MEMCPY, pd->cap_mask); 2870f6f2421cSLars-Peter Clausen if (pcfg->num_peri) { 287193ed5544SThomas Abraham dma_cap_set(DMA_SLAVE, pd->cap_mask); 287293ed5544SThomas Abraham dma_cap_set(DMA_CYCLIC, pd->cap_mask); 28735557a419STushar Behera dma_cap_set(DMA_PRIVATE, pd->cap_mask); 287493ed5544SThomas Abraham } 287593ed5544SThomas Abraham } 2876b3040e40SJassi Brar 2877b3040e40SJassi Brar pd->device_alloc_chan_resources = pl330_alloc_chan_resources; 2878b3040e40SJassi Brar pd->device_free_chan_resources = pl330_free_chan_resources; 2879b3040e40SJassi Brar pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; 288042bc9cf4SBoojin Kim pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; 2881b3040e40SJassi Brar pd->device_tx_status = pl330_tx_status; 2882b3040e40SJassi Brar pd->device_prep_slave_sg = pl330_prep_slave_sg; 2883740aa957SMaxime Ripard pd->device_config = pl330_config; 288488987d2cSRobert Baldyga pd->device_pause = pl330_pause; 2885740aa957SMaxime Ripard pd->device_terminate_all = pl330_terminate_all; 2886b3040e40SJassi Brar pd->device_issue_pending = pl330_issue_pending; 2887dcabe456SMaxime Ripard pd->src_addr_widths = PL330_DMA_BUSWIDTHS; 2888dcabe456SMaxime Ripard pd->dst_addr_widths = PL330_DMA_BUSWIDTHS; 2889dcabe456SMaxime Ripard pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 2890aee4d1faSRobert Baldyga pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 2891b3040e40SJassi Brar 2892b3040e40SJassi Brar ret = dma_async_device_register(pd); 2893b3040e40SJassi Brar if (ret) { 2894b3040e40SJassi Brar dev_err(&adev->dev, "unable to register DMAC\n"); 28950b94c577SPadmavathi Venna goto probe_err3; 28960b94c577SPadmavathi Venna } 28970b94c577SPadmavathi Venna 28980b94c577SPadmavathi Venna if (adev->dev.of_node) { 28990b94c577SPadmavathi Venna ret = of_dma_controller_register(adev->dev.of_node, 2900f6f2421cSLars-Peter Clausen of_dma_pl330_xlate, pl330); 29010b94c577SPadmavathi Venna if (ret) { 29020b94c577SPadmavathi Venna dev_err(&adev->dev, 29030b94c577SPadmavathi Venna "unable to register DMA to the generic DT DMA helpers\n"); 29040b94c577SPadmavathi Venna } 2905b3040e40SJassi Brar } 2906b714b84eSLars-Peter Clausen 2907f6f2421cSLars-Peter Clausen adev->dev.dma_parms = &pl330->dma_parms; 2908b714b84eSLars-Peter Clausen 2909dbaf6d85SVinod Koul /* 2910dbaf6d85SVinod Koul * This is the limit for transfers with a buswidth of 1, larger 2911dbaf6d85SVinod Koul * buswidths will have larger limits. 2912dbaf6d85SVinod Koul */ 2913dbaf6d85SVinod Koul ret = dma_set_max_seg_size(&adev->dev, 1900800); 2914dbaf6d85SVinod Koul if (ret) 2915dbaf6d85SVinod Koul dev_err(&adev->dev, "unable to set the seg size\n"); 2916dbaf6d85SVinod Koul 2917b3040e40SJassi Brar 2918b3040e40SJassi Brar dev_info(&adev->dev, 29191f0a5cbfSLiviu Dudau "Loaded driver for PL330 DMAC-%x\n", adev->periphid); 2920b3040e40SJassi Brar dev_info(&adev->dev, 2921b3040e40SJassi Brar "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", 2922f6f2421cSLars-Peter Clausen pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan, 2923f6f2421cSLars-Peter Clausen pcfg->num_peri, pcfg->num_events); 2924b3040e40SJassi Brar 2925ae43b328SKrzysztof Kozlowski pm_runtime_irq_safe(&adev->dev); 2926ae43b328SKrzysztof Kozlowski pm_runtime_use_autosuspend(&adev->dev); 2927ae43b328SKrzysztof Kozlowski pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY); 2928ae43b328SKrzysztof Kozlowski pm_runtime_mark_last_busy(&adev->dev); 2929ae43b328SKrzysztof Kozlowski pm_runtime_put_autosuspend(&adev->dev); 2930ae43b328SKrzysztof Kozlowski 2931b3040e40SJassi Brar return 0; 29320b94c577SPadmavathi Venna probe_err3: 29330b94c577SPadmavathi Venna /* Idle the DMAC */ 2934f6f2421cSLars-Peter Clausen list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, 29350b94c577SPadmavathi Venna chan.device_node) { 29360b94c577SPadmavathi Venna 29370b94c577SPadmavathi Venna /* Remove the channel */ 29380b94c577SPadmavathi Venna list_del(&pch->chan.device_node); 29390b94c577SPadmavathi Venna 29400b94c577SPadmavathi Venna /* Flush the channel */ 29410f5ebabdSKrzysztof Kozlowski if (pch->thread) { 2942740aa957SMaxime Ripard pl330_terminate_all(&pch->chan); 29430b94c577SPadmavathi Venna pl330_free_chan_resources(&pch->chan); 29440b94c577SPadmavathi Venna } 29450f5ebabdSKrzysztof Kozlowski } 2946b3040e40SJassi Brar probe_err2: 2947f6f2421cSLars-Peter Clausen pl330_del(pl330); 2948b3040e40SJassi Brar 2949b3040e40SJassi Brar return ret; 2950b3040e40SJassi Brar } 2951b3040e40SJassi Brar 29524bf27b8bSGreg Kroah-Hartman static int pl330_remove(struct amba_device *adev) 2953b3040e40SJassi Brar { 2954f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = amba_get_drvdata(adev); 2955b3040e40SJassi Brar struct dma_pl330_chan *pch, *_p; 2956b3040e40SJassi Brar 2957ae43b328SKrzysztof Kozlowski pm_runtime_get_noresume(pl330->ddma.dev); 2958ae43b328SKrzysztof Kozlowski 29590b94c577SPadmavathi Venna if (adev->dev.of_node) 2960421da89aSPadmavathi Venna of_dma_controller_free(adev->dev.of_node); 2961421da89aSPadmavathi Venna 2962f6f2421cSLars-Peter Clausen dma_async_device_unregister(&pl330->ddma); 2963b3040e40SJassi Brar 2964b3040e40SJassi Brar /* Idle the DMAC */ 2965f6f2421cSLars-Peter Clausen list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, 2966b3040e40SJassi Brar chan.device_node) { 2967b3040e40SJassi Brar 2968b3040e40SJassi Brar /* Remove the channel */ 2969b3040e40SJassi Brar list_del(&pch->chan.device_node); 2970b3040e40SJassi Brar 2971b3040e40SJassi Brar /* Flush the channel */ 29726e4a2a83SKrzysztof Kozlowski if (pch->thread) { 2973740aa957SMaxime Ripard pl330_terminate_all(&pch->chan); 2974b3040e40SJassi Brar pl330_free_chan_resources(&pch->chan); 2975b3040e40SJassi Brar } 29766e4a2a83SKrzysztof Kozlowski } 2977b3040e40SJassi Brar 2978f6f2421cSLars-Peter Clausen pl330_del(pl330); 2979b3040e40SJassi Brar 2980b3040e40SJassi Brar return 0; 2981b3040e40SJassi Brar } 2982b3040e40SJassi Brar 2983b3040e40SJassi Brar static struct amba_id pl330_ids[] = { 2984b3040e40SJassi Brar { 2985b3040e40SJassi Brar .id = 0x00041330, 2986b3040e40SJassi Brar .mask = 0x000fffff, 2987b3040e40SJassi Brar }, 2988b3040e40SJassi Brar { 0, 0 }, 2989b3040e40SJassi Brar }; 2990b3040e40SJassi Brar 2991e8fa516aSDave Martin MODULE_DEVICE_TABLE(amba, pl330_ids); 2992e8fa516aSDave Martin 2993b3040e40SJassi Brar static struct amba_driver pl330_driver = { 2994b3040e40SJassi Brar .drv = { 2995b3040e40SJassi Brar .owner = THIS_MODULE, 2996b3040e40SJassi Brar .name = "dma-pl330", 2997b816ccc5SKrzysztof Kozlowski .pm = &pl330_pm, 2998b3040e40SJassi Brar }, 2999b3040e40SJassi Brar .id_table = pl330_ids, 3000b3040e40SJassi Brar .probe = pl330_probe, 3001b3040e40SJassi Brar .remove = pl330_remove, 3002b3040e40SJassi Brar }; 3003b3040e40SJassi Brar 30049e5ed094Sviresh kumar module_amba_driver(pl330_driver); 3005b3040e40SJassi Brar 3006046209f6SJassi Brar MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>"); 3007b3040e40SJassi Brar MODULE_DESCRIPTION("API Driver for PL330 DMAC"); 3008b3040e40SJassi Brar MODULE_LICENSE("GPL"); 3009