1b7d861d9SBoojin Kim /* 2b7d861d9SBoojin Kim * Copyright (c) 2012 Samsung Electronics Co., Ltd. 3b7d861d9SBoojin Kim * http://www.samsung.com 4b3040e40SJassi Brar * 5b3040e40SJassi Brar * Copyright (C) 2010 Samsung Electronics Co. Ltd. 6b3040e40SJassi Brar * Jaswinder Singh <jassi.brar@samsung.com> 7b3040e40SJassi Brar * 8b3040e40SJassi Brar * This program is free software; you can redistribute it and/or modify 9b3040e40SJassi Brar * it under the terms of the GNU General Public License as published by 10b3040e40SJassi Brar * the Free Software Foundation; either version 2 of the License, or 11b3040e40SJassi Brar * (at your option) any later version. 12b3040e40SJassi Brar */ 13b3040e40SJassi Brar 14b7d861d9SBoojin Kim #include <linux/kernel.h> 15b3040e40SJassi Brar #include <linux/io.h> 16b3040e40SJassi Brar #include <linux/init.h> 17b3040e40SJassi Brar #include <linux/slab.h> 18b3040e40SJassi Brar #include <linux/module.h> 19b7d861d9SBoojin Kim #include <linux/string.h> 20b7d861d9SBoojin Kim #include <linux/delay.h> 21b7d861d9SBoojin Kim #include <linux/interrupt.h> 22b7d861d9SBoojin Kim #include <linux/dma-mapping.h> 23b3040e40SJassi Brar #include <linux/dmaengine.h> 24b3040e40SJassi Brar #include <linux/amba/bus.h> 25b3040e40SJassi Brar #include <linux/amba/pl330.h> 261b9bb715SBoojin Kim #include <linux/scatterlist.h> 2793ed5544SThomas Abraham #include <linux/of.h> 28a80258f9SPadmavathi Venna #include <linux/of_dma.h> 29bcc7fa95SSachin Kamat #include <linux/err.h> 30b3040e40SJassi Brar 31d2ebfb33SRussell King - ARM Linux #include "dmaengine.h" 32b7d861d9SBoojin Kim #define PL330_MAX_CHAN 8 33b7d861d9SBoojin Kim #define PL330_MAX_IRQS 32 34b7d861d9SBoojin Kim #define PL330_MAX_PERI 32 35b7d861d9SBoojin Kim 36b7d861d9SBoojin Kim enum pl330_srccachectrl { 37b7d861d9SBoojin Kim SCCTRL0, /* Noncacheable and nonbufferable */ 38b7d861d9SBoojin Kim SCCTRL1, /* Bufferable only */ 39b7d861d9SBoojin Kim SCCTRL2, /* Cacheable, but do not allocate */ 40b7d861d9SBoojin Kim SCCTRL3, /* Cacheable and bufferable, but do not allocate */ 41b7d861d9SBoojin Kim SINVALID1, 42b7d861d9SBoojin Kim SINVALID2, 43b7d861d9SBoojin Kim SCCTRL6, /* Cacheable write-through, allocate on reads only */ 44b7d861d9SBoojin Kim SCCTRL7, /* Cacheable write-back, allocate on reads only */ 45b7d861d9SBoojin Kim }; 46b7d861d9SBoojin Kim 47b7d861d9SBoojin Kim enum pl330_dstcachectrl { 48b7d861d9SBoojin Kim DCCTRL0, /* Noncacheable and nonbufferable */ 49b7d861d9SBoojin Kim DCCTRL1, /* Bufferable only */ 50b7d861d9SBoojin Kim DCCTRL2, /* Cacheable, but do not allocate */ 51b7d861d9SBoojin Kim DCCTRL3, /* Cacheable and bufferable, but do not allocate */ 52ef08e782SLinus Torvalds DINVALID1, /* AWCACHE = 0x1000 */ 53b7d861d9SBoojin Kim DINVALID2, 54b7d861d9SBoojin Kim DCCTRL6, /* Cacheable write-through, allocate on writes only */ 55b7d861d9SBoojin Kim DCCTRL7, /* Cacheable write-back, allocate on writes only */ 56b7d861d9SBoojin Kim }; 57b7d861d9SBoojin Kim 58b7d861d9SBoojin Kim enum pl330_byteswap { 59b7d861d9SBoojin Kim SWAP_NO, 60b7d861d9SBoojin Kim SWAP_2, 61b7d861d9SBoojin Kim SWAP_4, 62b7d861d9SBoojin Kim SWAP_8, 63b7d861d9SBoojin Kim SWAP_16, 64b7d861d9SBoojin Kim }; 65b7d861d9SBoojin Kim 66b7d861d9SBoojin Kim enum pl330_reqtype { 67b7d861d9SBoojin Kim MEMTOMEM, 68b7d861d9SBoojin Kim MEMTODEV, 69b7d861d9SBoojin Kim DEVTOMEM, 70b7d861d9SBoojin Kim DEVTODEV, 71b7d861d9SBoojin Kim }; 72b7d861d9SBoojin Kim 73b7d861d9SBoojin Kim /* Register and Bit field Definitions */ 74b7d861d9SBoojin Kim #define DS 0x0 75b7d861d9SBoojin Kim #define DS_ST_STOP 0x0 76b7d861d9SBoojin Kim #define DS_ST_EXEC 0x1 77b7d861d9SBoojin Kim #define DS_ST_CMISS 0x2 78b7d861d9SBoojin Kim #define DS_ST_UPDTPC 0x3 79b7d861d9SBoojin Kim #define DS_ST_WFE 0x4 80b7d861d9SBoojin Kim #define DS_ST_ATBRR 0x5 81b7d861d9SBoojin Kim #define DS_ST_QBUSY 0x6 82b7d861d9SBoojin Kim #define DS_ST_WFP 0x7 83b7d861d9SBoojin Kim #define DS_ST_KILL 0x8 84b7d861d9SBoojin Kim #define DS_ST_CMPLT 0x9 85b7d861d9SBoojin Kim #define DS_ST_FLTCMP 0xe 86b7d861d9SBoojin Kim #define DS_ST_FAULT 0xf 87b7d861d9SBoojin Kim 88b7d861d9SBoojin Kim #define DPC 0x4 89b7d861d9SBoojin Kim #define INTEN 0x20 90b7d861d9SBoojin Kim #define ES 0x24 91b7d861d9SBoojin Kim #define INTSTATUS 0x28 92b7d861d9SBoojin Kim #define INTCLR 0x2c 93b7d861d9SBoojin Kim #define FSM 0x30 94b7d861d9SBoojin Kim #define FSC 0x34 95b7d861d9SBoojin Kim #define FTM 0x38 96b7d861d9SBoojin Kim 97b7d861d9SBoojin Kim #define _FTC 0x40 98b7d861d9SBoojin Kim #define FTC(n) (_FTC + (n)*0x4) 99b7d861d9SBoojin Kim 100b7d861d9SBoojin Kim #define _CS 0x100 101b7d861d9SBoojin Kim #define CS(n) (_CS + (n)*0x8) 102b7d861d9SBoojin Kim #define CS_CNS (1 << 21) 103b7d861d9SBoojin Kim 104b7d861d9SBoojin Kim #define _CPC 0x104 105b7d861d9SBoojin Kim #define CPC(n) (_CPC + (n)*0x8) 106b7d861d9SBoojin Kim 107b7d861d9SBoojin Kim #define _SA 0x400 108b7d861d9SBoojin Kim #define SA(n) (_SA + (n)*0x20) 109b7d861d9SBoojin Kim 110b7d861d9SBoojin Kim #define _DA 0x404 111b7d861d9SBoojin Kim #define DA(n) (_DA + (n)*0x20) 112b7d861d9SBoojin Kim 113b7d861d9SBoojin Kim #define _CC 0x408 114b7d861d9SBoojin Kim #define CC(n) (_CC + (n)*0x20) 115b7d861d9SBoojin Kim 116b7d861d9SBoojin Kim #define CC_SRCINC (1 << 0) 117b7d861d9SBoojin Kim #define CC_DSTINC (1 << 14) 118b7d861d9SBoojin Kim #define CC_SRCPRI (1 << 8) 119b7d861d9SBoojin Kim #define CC_DSTPRI (1 << 22) 120b7d861d9SBoojin Kim #define CC_SRCNS (1 << 9) 121b7d861d9SBoojin Kim #define CC_DSTNS (1 << 23) 122b7d861d9SBoojin Kim #define CC_SRCIA (1 << 10) 123b7d861d9SBoojin Kim #define CC_DSTIA (1 << 24) 124b7d861d9SBoojin Kim #define CC_SRCBRSTLEN_SHFT 4 125b7d861d9SBoojin Kim #define CC_DSTBRSTLEN_SHFT 18 126b7d861d9SBoojin Kim #define CC_SRCBRSTSIZE_SHFT 1 127b7d861d9SBoojin Kim #define CC_DSTBRSTSIZE_SHFT 15 128b7d861d9SBoojin Kim #define CC_SRCCCTRL_SHFT 11 129b7d861d9SBoojin Kim #define CC_SRCCCTRL_MASK 0x7 130b7d861d9SBoojin Kim #define CC_DSTCCTRL_SHFT 25 131b7d861d9SBoojin Kim #define CC_DRCCCTRL_MASK 0x7 132b7d861d9SBoojin Kim #define CC_SWAP_SHFT 28 133b7d861d9SBoojin Kim 134b7d861d9SBoojin Kim #define _LC0 0x40c 135b7d861d9SBoojin Kim #define LC0(n) (_LC0 + (n)*0x20) 136b7d861d9SBoojin Kim 137b7d861d9SBoojin Kim #define _LC1 0x410 138b7d861d9SBoojin Kim #define LC1(n) (_LC1 + (n)*0x20) 139b7d861d9SBoojin Kim 140b7d861d9SBoojin Kim #define DBGSTATUS 0xd00 141b7d861d9SBoojin Kim #define DBG_BUSY (1 << 0) 142b7d861d9SBoojin Kim 143b7d861d9SBoojin Kim #define DBGCMD 0xd04 144b7d861d9SBoojin Kim #define DBGINST0 0xd08 145b7d861d9SBoojin Kim #define DBGINST1 0xd0c 146b7d861d9SBoojin Kim 147b7d861d9SBoojin Kim #define CR0 0xe00 148b7d861d9SBoojin Kim #define CR1 0xe04 149b7d861d9SBoojin Kim #define CR2 0xe08 150b7d861d9SBoojin Kim #define CR3 0xe0c 151b7d861d9SBoojin Kim #define CR4 0xe10 152b7d861d9SBoojin Kim #define CRD 0xe14 153b7d861d9SBoojin Kim 154b7d861d9SBoojin Kim #define PERIPH_ID 0xfe0 1553ecf51a4SBoojin Kim #define PERIPH_REV_SHIFT 20 1563ecf51a4SBoojin Kim #define PERIPH_REV_MASK 0xf 1573ecf51a4SBoojin Kim #define PERIPH_REV_R0P0 0 1583ecf51a4SBoojin Kim #define PERIPH_REV_R1P0 1 1593ecf51a4SBoojin Kim #define PERIPH_REV_R1P1 2 160b7d861d9SBoojin Kim #define PCELL_ID 0xff0 161b7d861d9SBoojin Kim 162b7d861d9SBoojin Kim #define CR0_PERIPH_REQ_SET (1 << 0) 163b7d861d9SBoojin Kim #define CR0_BOOT_EN_SET (1 << 1) 164b7d861d9SBoojin Kim #define CR0_BOOT_MAN_NS (1 << 2) 165b7d861d9SBoojin Kim #define CR0_NUM_CHANS_SHIFT 4 166b7d861d9SBoojin Kim #define CR0_NUM_CHANS_MASK 0x7 167b7d861d9SBoojin Kim #define CR0_NUM_PERIPH_SHIFT 12 168b7d861d9SBoojin Kim #define CR0_NUM_PERIPH_MASK 0x1f 169b7d861d9SBoojin Kim #define CR0_NUM_EVENTS_SHIFT 17 170b7d861d9SBoojin Kim #define CR0_NUM_EVENTS_MASK 0x1f 171b7d861d9SBoojin Kim 172b7d861d9SBoojin Kim #define CR1_ICACHE_LEN_SHIFT 0 173b7d861d9SBoojin Kim #define CR1_ICACHE_LEN_MASK 0x7 174b7d861d9SBoojin Kim #define CR1_NUM_ICACHELINES_SHIFT 4 175b7d861d9SBoojin Kim #define CR1_NUM_ICACHELINES_MASK 0xf 176b7d861d9SBoojin Kim 177b7d861d9SBoojin Kim #define CRD_DATA_WIDTH_SHIFT 0 178b7d861d9SBoojin Kim #define CRD_DATA_WIDTH_MASK 0x7 179b7d861d9SBoojin Kim #define CRD_WR_CAP_SHIFT 4 180b7d861d9SBoojin Kim #define CRD_WR_CAP_MASK 0x7 181b7d861d9SBoojin Kim #define CRD_WR_Q_DEP_SHIFT 8 182b7d861d9SBoojin Kim #define CRD_WR_Q_DEP_MASK 0xf 183b7d861d9SBoojin Kim #define CRD_RD_CAP_SHIFT 12 184b7d861d9SBoojin Kim #define CRD_RD_CAP_MASK 0x7 185b7d861d9SBoojin Kim #define CRD_RD_Q_DEP_SHIFT 16 186b7d861d9SBoojin Kim #define CRD_RD_Q_DEP_MASK 0xf 187b7d861d9SBoojin Kim #define CRD_DATA_BUFF_SHIFT 20 188b7d861d9SBoojin Kim #define CRD_DATA_BUFF_MASK 0x3ff 189b7d861d9SBoojin Kim 190b7d861d9SBoojin Kim #define PART 0x330 191b7d861d9SBoojin Kim #define DESIGNER 0x41 192b7d861d9SBoojin Kim #define REVISION 0x0 193b7d861d9SBoojin Kim #define INTEG_CFG 0x0 194b7d861d9SBoojin Kim #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) 195b7d861d9SBoojin Kim 196b7d861d9SBoojin Kim #define PCELL_ID_VAL 0xb105f00d 197b7d861d9SBoojin Kim 198b7d861d9SBoojin Kim #define PL330_STATE_STOPPED (1 << 0) 199b7d861d9SBoojin Kim #define PL330_STATE_EXECUTING (1 << 1) 200b7d861d9SBoojin Kim #define PL330_STATE_WFE (1 << 2) 201b7d861d9SBoojin Kim #define PL330_STATE_FAULTING (1 << 3) 202b7d861d9SBoojin Kim #define PL330_STATE_COMPLETING (1 << 4) 203b7d861d9SBoojin Kim #define PL330_STATE_WFP (1 << 5) 204b7d861d9SBoojin Kim #define PL330_STATE_KILLING (1 << 6) 205b7d861d9SBoojin Kim #define PL330_STATE_FAULT_COMPLETING (1 << 7) 206b7d861d9SBoojin Kim #define PL330_STATE_CACHEMISS (1 << 8) 207b7d861d9SBoojin Kim #define PL330_STATE_UPDTPC (1 << 9) 208b7d861d9SBoojin Kim #define PL330_STATE_ATBARRIER (1 << 10) 209b7d861d9SBoojin Kim #define PL330_STATE_QUEUEBUSY (1 << 11) 210b7d861d9SBoojin Kim #define PL330_STATE_INVALID (1 << 15) 211b7d861d9SBoojin Kim 212b7d861d9SBoojin Kim #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ 213b7d861d9SBoojin Kim | PL330_STATE_WFE | PL330_STATE_FAULTING) 214b7d861d9SBoojin Kim 215b7d861d9SBoojin Kim #define CMD_DMAADDH 0x54 216b7d861d9SBoojin Kim #define CMD_DMAEND 0x00 217b7d861d9SBoojin Kim #define CMD_DMAFLUSHP 0x35 218b7d861d9SBoojin Kim #define CMD_DMAGO 0xa0 219b7d861d9SBoojin Kim #define CMD_DMALD 0x04 220b7d861d9SBoojin Kim #define CMD_DMALDP 0x25 221b7d861d9SBoojin Kim #define CMD_DMALP 0x20 222b7d861d9SBoojin Kim #define CMD_DMALPEND 0x28 223b7d861d9SBoojin Kim #define CMD_DMAKILL 0x01 224b7d861d9SBoojin Kim #define CMD_DMAMOV 0xbc 225b7d861d9SBoojin Kim #define CMD_DMANOP 0x18 226b7d861d9SBoojin Kim #define CMD_DMARMB 0x12 227b7d861d9SBoojin Kim #define CMD_DMASEV 0x34 228b7d861d9SBoojin Kim #define CMD_DMAST 0x08 229b7d861d9SBoojin Kim #define CMD_DMASTP 0x29 230b7d861d9SBoojin Kim #define CMD_DMASTZ 0x0c 231b7d861d9SBoojin Kim #define CMD_DMAWFE 0x36 232b7d861d9SBoojin Kim #define CMD_DMAWFP 0x30 233b7d861d9SBoojin Kim #define CMD_DMAWMB 0x13 234b7d861d9SBoojin Kim 235b7d861d9SBoojin Kim #define SZ_DMAADDH 3 236b7d861d9SBoojin Kim #define SZ_DMAEND 1 237b7d861d9SBoojin Kim #define SZ_DMAFLUSHP 2 238b7d861d9SBoojin Kim #define SZ_DMALD 1 239b7d861d9SBoojin Kim #define SZ_DMALDP 2 240b7d861d9SBoojin Kim #define SZ_DMALP 2 241b7d861d9SBoojin Kim #define SZ_DMALPEND 2 242b7d861d9SBoojin Kim #define SZ_DMAKILL 1 243b7d861d9SBoojin Kim #define SZ_DMAMOV 6 244b7d861d9SBoojin Kim #define SZ_DMANOP 1 245b7d861d9SBoojin Kim #define SZ_DMARMB 1 246b7d861d9SBoojin Kim #define SZ_DMASEV 2 247b7d861d9SBoojin Kim #define SZ_DMAST 1 248b7d861d9SBoojin Kim #define SZ_DMASTP 2 249b7d861d9SBoojin Kim #define SZ_DMASTZ 1 250b7d861d9SBoojin Kim #define SZ_DMAWFE 2 251b7d861d9SBoojin Kim #define SZ_DMAWFP 2 252b7d861d9SBoojin Kim #define SZ_DMAWMB 1 253b7d861d9SBoojin Kim #define SZ_DMAGO 6 254b7d861d9SBoojin Kim 255b7d861d9SBoojin Kim #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) 256b7d861d9SBoojin Kim #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) 257b7d861d9SBoojin Kim 258b7d861d9SBoojin Kim #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) 259b7d861d9SBoojin Kim #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) 260b7d861d9SBoojin Kim 261b7d861d9SBoojin Kim /* 262b7d861d9SBoojin Kim * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req 263b7d861d9SBoojin Kim * at 1byte/burst for P<->M and M<->M respectively. 264b7d861d9SBoojin Kim * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req 265b7d861d9SBoojin Kim * should be enough for P<->M and M<->M respectively. 266b7d861d9SBoojin Kim */ 267b7d861d9SBoojin Kim #define MCODE_BUFF_PER_REQ 256 268b7d861d9SBoojin Kim 269b7d861d9SBoojin Kim /* If the _pl330_req is available to the client */ 270b7d861d9SBoojin Kim #define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND) 271b7d861d9SBoojin Kim 272b7d861d9SBoojin Kim /* Use this _only_ to wait on transient states */ 273b7d861d9SBoojin Kim #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); 274b7d861d9SBoojin Kim 275b7d861d9SBoojin Kim #ifdef PL330_DEBUG_MCGEN 276b7d861d9SBoojin Kim static unsigned cmd_line; 277b7d861d9SBoojin Kim #define PL330_DBGCMD_DUMP(off, x...) do { \ 278b7d861d9SBoojin Kim printk("%x:", cmd_line); \ 279b7d861d9SBoojin Kim printk(x); \ 280b7d861d9SBoojin Kim cmd_line += off; \ 281b7d861d9SBoojin Kim } while (0) 282b7d861d9SBoojin Kim #define PL330_DBGMC_START(addr) (cmd_line = addr) 283b7d861d9SBoojin Kim #else 284b7d861d9SBoojin Kim #define PL330_DBGCMD_DUMP(off, x...) do {} while (0) 285b7d861d9SBoojin Kim #define PL330_DBGMC_START(addr) do {} while (0) 286b7d861d9SBoojin Kim #endif 287b7d861d9SBoojin Kim 288b7d861d9SBoojin Kim /* The number of default descriptors */ 289d2ebfb33SRussell King - ARM Linux 290b3040e40SJassi Brar #define NR_DEFAULT_DESC 16 291b3040e40SJassi Brar 292b7d861d9SBoojin Kim /* Populated by the PL330 core driver for DMA API driver's info */ 293b7d861d9SBoojin Kim struct pl330_config { 294b7d861d9SBoojin Kim u32 periph_id; 295b7d861d9SBoojin Kim u32 pcell_id; 296b7d861d9SBoojin Kim #define DMAC_MODE_NS (1 << 0) 297b7d861d9SBoojin Kim unsigned int mode; 298b7d861d9SBoojin Kim unsigned int data_bus_width:10; /* In number of bits */ 299b7d861d9SBoojin Kim unsigned int data_buf_dep:10; 300b7d861d9SBoojin Kim unsigned int num_chan:4; 301b7d861d9SBoojin Kim unsigned int num_peri:6; 302b7d861d9SBoojin Kim u32 peri_ns; 303b7d861d9SBoojin Kim unsigned int num_events:6; 304b7d861d9SBoojin Kim u32 irq_ns; 305b7d861d9SBoojin Kim }; 306b7d861d9SBoojin Kim 307b7d861d9SBoojin Kim /* Handle to the DMAC provided to the PL330 core */ 308b7d861d9SBoojin Kim struct pl330_info { 309b7d861d9SBoojin Kim /* Owning device */ 310b7d861d9SBoojin Kim struct device *dev; 311b7d861d9SBoojin Kim /* Size of MicroCode buffers for each channel. */ 312b7d861d9SBoojin Kim unsigned mcbufsz; 313b7d861d9SBoojin Kim /* ioremap'ed address of PL330 registers. */ 314b7d861d9SBoojin Kim void __iomem *base; 315b7d861d9SBoojin Kim /* Client can freely use it. */ 316b7d861d9SBoojin Kim void *client_data; 317b7d861d9SBoojin Kim /* PL330 core data, Client must not touch it. */ 318b7d861d9SBoojin Kim void *pl330_data; 319b7d861d9SBoojin Kim /* Populated by the PL330 core driver during pl330_add */ 320b7d861d9SBoojin Kim struct pl330_config pcfg; 321b7d861d9SBoojin Kim /* 322b7d861d9SBoojin Kim * If the DMAC has some reset mechanism, then the 323b7d861d9SBoojin Kim * client may want to provide pointer to the method. 324b7d861d9SBoojin Kim */ 325b7d861d9SBoojin Kim void (*dmac_reset)(struct pl330_info *pi); 326b7d861d9SBoojin Kim }; 327b7d861d9SBoojin Kim 328b7d861d9SBoojin Kim /** 329b7d861d9SBoojin Kim * Request Configuration. 330b7d861d9SBoojin Kim * The PL330 core does not modify this and uses the last 331b7d861d9SBoojin Kim * working configuration if the request doesn't provide any. 332b7d861d9SBoojin Kim * 333b7d861d9SBoojin Kim * The Client may want to provide this info only for the 334b7d861d9SBoojin Kim * first request and a request with new settings. 335b7d861d9SBoojin Kim */ 336b7d861d9SBoojin Kim struct pl330_reqcfg { 337b7d861d9SBoojin Kim /* Address Incrementing */ 338b7d861d9SBoojin Kim unsigned dst_inc:1; 339b7d861d9SBoojin Kim unsigned src_inc:1; 340b7d861d9SBoojin Kim 341b7d861d9SBoojin Kim /* 342b7d861d9SBoojin Kim * For now, the SRC & DST protection levels 343b7d861d9SBoojin Kim * and burst size/length are assumed same. 344b7d861d9SBoojin Kim */ 345b7d861d9SBoojin Kim bool nonsecure; 346b7d861d9SBoojin Kim bool privileged; 347b7d861d9SBoojin Kim bool insnaccess; 348b7d861d9SBoojin Kim unsigned brst_len:5; 349b7d861d9SBoojin Kim unsigned brst_size:3; /* in power of 2 */ 350b7d861d9SBoojin Kim 351b7d861d9SBoojin Kim enum pl330_dstcachectrl dcctl; 352b7d861d9SBoojin Kim enum pl330_srccachectrl scctl; 353b7d861d9SBoojin Kim enum pl330_byteswap swap; 3543ecf51a4SBoojin Kim struct pl330_config *pcfg; 355b7d861d9SBoojin Kim }; 356b7d861d9SBoojin Kim 357b7d861d9SBoojin Kim /* 358b7d861d9SBoojin Kim * One cycle of DMAC operation. 359b7d861d9SBoojin Kim * There may be more than one xfer in a request. 360b7d861d9SBoojin Kim */ 361b7d861d9SBoojin Kim struct pl330_xfer { 362b7d861d9SBoojin Kim u32 src_addr; 363b7d861d9SBoojin Kim u32 dst_addr; 364b7d861d9SBoojin Kim /* Size to xfer */ 365b7d861d9SBoojin Kim u32 bytes; 366b7d861d9SBoojin Kim /* 367b7d861d9SBoojin Kim * Pointer to next xfer in the list. 368b7d861d9SBoojin Kim * The last xfer in the req must point to NULL. 369b7d861d9SBoojin Kim */ 370b7d861d9SBoojin Kim struct pl330_xfer *next; 371b7d861d9SBoojin Kim }; 372b7d861d9SBoojin Kim 373b7d861d9SBoojin Kim /* The xfer callbacks are made with one of these arguments. */ 374b7d861d9SBoojin Kim enum pl330_op_err { 375b7d861d9SBoojin Kim /* The all xfers in the request were success. */ 376b7d861d9SBoojin Kim PL330_ERR_NONE, 377b7d861d9SBoojin Kim /* If req aborted due to global error. */ 378b7d861d9SBoojin Kim PL330_ERR_ABORT, 379b7d861d9SBoojin Kim /* If req failed due to problem with Channel. */ 380b7d861d9SBoojin Kim PL330_ERR_FAIL, 381b7d861d9SBoojin Kim }; 382b7d861d9SBoojin Kim 383b7d861d9SBoojin Kim /* A request defining Scatter-Gather List ending with NULL xfer. */ 384b7d861d9SBoojin Kim struct pl330_req { 385b7d861d9SBoojin Kim enum pl330_reqtype rqtype; 386b7d861d9SBoojin Kim /* Index of peripheral for the xfer. */ 387b7d861d9SBoojin Kim unsigned peri:5; 388b7d861d9SBoojin Kim /* Unique token for this xfer, set by the client. */ 389b7d861d9SBoojin Kim void *token; 390b7d861d9SBoojin Kim /* Callback to be called after xfer. */ 391b7d861d9SBoojin Kim void (*xfer_cb)(void *token, enum pl330_op_err err); 392b7d861d9SBoojin Kim /* If NULL, req will be done at last set parameters. */ 393b7d861d9SBoojin Kim struct pl330_reqcfg *cfg; 394b7d861d9SBoojin Kim /* Pointer to first xfer in the request. */ 395b7d861d9SBoojin Kim struct pl330_xfer *x; 396fdec53d5SJavi Merino /* Hook to attach to DMAC's list of reqs with due callback */ 397fdec53d5SJavi Merino struct list_head rqd; 398b7d861d9SBoojin Kim }; 399b7d861d9SBoojin Kim 400b7d861d9SBoojin Kim /* 401b7d861d9SBoojin Kim * To know the status of the channel and DMAC, the client 402b7d861d9SBoojin Kim * provides a pointer to this structure. The PL330 core 403b7d861d9SBoojin Kim * fills it with current information. 404b7d861d9SBoojin Kim */ 405b7d861d9SBoojin Kim struct pl330_chanstatus { 406b7d861d9SBoojin Kim /* 407b7d861d9SBoojin Kim * If the DMAC engine halted due to some error, 408b7d861d9SBoojin Kim * the client should remove-add DMAC. 409b7d861d9SBoojin Kim */ 410b7d861d9SBoojin Kim bool dmac_halted; 411b7d861d9SBoojin Kim /* 412b7d861d9SBoojin Kim * If channel is halted due to some error, 413b7d861d9SBoojin Kim * the client should ABORT/FLUSH and START the channel. 414b7d861d9SBoojin Kim */ 415b7d861d9SBoojin Kim bool faulting; 416b7d861d9SBoojin Kim /* Location of last load */ 417b7d861d9SBoojin Kim u32 src_addr; 418b7d861d9SBoojin Kim /* Location of last store */ 419b7d861d9SBoojin Kim u32 dst_addr; 420b7d861d9SBoojin Kim /* 421b7d861d9SBoojin Kim * Pointer to the currently active req, NULL if channel is 422b7d861d9SBoojin Kim * inactive, even though the requests may be present. 423b7d861d9SBoojin Kim */ 424b7d861d9SBoojin Kim struct pl330_req *top_req; 425b7d861d9SBoojin Kim /* Pointer to req waiting second in the queue if any. */ 426b7d861d9SBoojin Kim struct pl330_req *wait_req; 427b7d861d9SBoojin Kim }; 428b7d861d9SBoojin Kim 429b7d861d9SBoojin Kim enum pl330_chan_op { 430b7d861d9SBoojin Kim /* Start the channel */ 431b7d861d9SBoojin Kim PL330_OP_START, 432b7d861d9SBoojin Kim /* Abort the active xfer */ 433b7d861d9SBoojin Kim PL330_OP_ABORT, 434b7d861d9SBoojin Kim /* Stop xfer and flush queue */ 435b7d861d9SBoojin Kim PL330_OP_FLUSH, 436b7d861d9SBoojin Kim }; 437b7d861d9SBoojin Kim 438b7d861d9SBoojin Kim struct _xfer_spec { 439b7d861d9SBoojin Kim u32 ccr; 440b7d861d9SBoojin Kim struct pl330_req *r; 441b7d861d9SBoojin Kim struct pl330_xfer *x; 442b7d861d9SBoojin Kim }; 443b7d861d9SBoojin Kim 444b7d861d9SBoojin Kim enum dmamov_dst { 445b7d861d9SBoojin Kim SAR = 0, 446b7d861d9SBoojin Kim CCR, 447b7d861d9SBoojin Kim DAR, 448b7d861d9SBoojin Kim }; 449b7d861d9SBoojin Kim 450b7d861d9SBoojin Kim enum pl330_dst { 451b7d861d9SBoojin Kim SRC = 0, 452b7d861d9SBoojin Kim DST, 453b7d861d9SBoojin Kim }; 454b7d861d9SBoojin Kim 455b7d861d9SBoojin Kim enum pl330_cond { 456b7d861d9SBoojin Kim SINGLE, 457b7d861d9SBoojin Kim BURST, 458b7d861d9SBoojin Kim ALWAYS, 459b7d861d9SBoojin Kim }; 460b7d861d9SBoojin Kim 461b7d861d9SBoojin Kim struct _pl330_req { 462b7d861d9SBoojin Kim u32 mc_bus; 463b7d861d9SBoojin Kim void *mc_cpu; 464b7d861d9SBoojin Kim /* Number of bytes taken to setup MC for the req */ 465b7d861d9SBoojin Kim u32 mc_len; 466b7d861d9SBoojin Kim struct pl330_req *r; 467b7d861d9SBoojin Kim }; 468b7d861d9SBoojin Kim 469b7d861d9SBoojin Kim /* ToBeDone for tasklet */ 470b7d861d9SBoojin Kim struct _pl330_tbd { 471b7d861d9SBoojin Kim bool reset_dmac; 472b7d861d9SBoojin Kim bool reset_mngr; 473b7d861d9SBoojin Kim u8 reset_chan; 474b7d861d9SBoojin Kim }; 475b7d861d9SBoojin Kim 476b7d861d9SBoojin Kim /* A DMAC Thread */ 477b7d861d9SBoojin Kim struct pl330_thread { 478b7d861d9SBoojin Kim u8 id; 479b7d861d9SBoojin Kim int ev; 480b7d861d9SBoojin Kim /* If the channel is not yet acquired by any client */ 481b7d861d9SBoojin Kim bool free; 482b7d861d9SBoojin Kim /* Parent DMAC */ 483b7d861d9SBoojin Kim struct pl330_dmac *dmac; 484b7d861d9SBoojin Kim /* Only two at a time */ 485b7d861d9SBoojin Kim struct _pl330_req req[2]; 486b7d861d9SBoojin Kim /* Index of the last enqueued request */ 487b7d861d9SBoojin Kim unsigned lstenq; 488b7d861d9SBoojin Kim /* Index of the last submitted request or -1 if the DMA is stopped */ 489b7d861d9SBoojin Kim int req_running; 490b7d861d9SBoojin Kim }; 491b7d861d9SBoojin Kim 492b7d861d9SBoojin Kim enum pl330_dmac_state { 493b7d861d9SBoojin Kim UNINIT, 494b7d861d9SBoojin Kim INIT, 495b7d861d9SBoojin Kim DYING, 496b7d861d9SBoojin Kim }; 497b7d861d9SBoojin Kim 498b7d861d9SBoojin Kim /* A DMAC */ 499b7d861d9SBoojin Kim struct pl330_dmac { 500b7d861d9SBoojin Kim spinlock_t lock; 501b7d861d9SBoojin Kim /* Holds list of reqs with due callbacks */ 502b7d861d9SBoojin Kim struct list_head req_done; 503b7d861d9SBoojin Kim /* Pointer to platform specific stuff */ 504b7d861d9SBoojin Kim struct pl330_info *pinfo; 505b7d861d9SBoojin Kim /* Maximum possible events/irqs */ 506b7d861d9SBoojin Kim int events[32]; 507b7d861d9SBoojin Kim /* BUS address of MicroCode buffer */ 508b7d861d9SBoojin Kim u32 mcode_bus; 509b7d861d9SBoojin Kim /* CPU address of MicroCode buffer */ 510b7d861d9SBoojin Kim void *mcode_cpu; 511b7d861d9SBoojin Kim /* List of all Channel threads */ 512b7d861d9SBoojin Kim struct pl330_thread *channels; 513b7d861d9SBoojin Kim /* Pointer to the MANAGER thread */ 514b7d861d9SBoojin Kim struct pl330_thread *manager; 515b7d861d9SBoojin Kim /* To handle bad news in interrupt */ 516b7d861d9SBoojin Kim struct tasklet_struct tasks; 517b7d861d9SBoojin Kim struct _pl330_tbd dmac_tbd; 518b7d861d9SBoojin Kim /* State of DMAC operation */ 519b7d861d9SBoojin Kim enum pl330_dmac_state state; 520b7d861d9SBoojin Kim }; 521b7d861d9SBoojin Kim 522b3040e40SJassi Brar enum desc_status { 523b3040e40SJassi Brar /* In the DMAC pool */ 524b3040e40SJassi Brar FREE, 525b3040e40SJassi Brar /* 526d73111c6SMasanari Iida * Allocated to some channel during prep_xxx 527b3040e40SJassi Brar * Also may be sitting on the work_list. 528b3040e40SJassi Brar */ 529b3040e40SJassi Brar PREP, 530b3040e40SJassi Brar /* 531b3040e40SJassi Brar * Sitting on the work_list and already submitted 532b3040e40SJassi Brar * to the PL330 core. Not more than two descriptors 533b3040e40SJassi Brar * of a channel can be BUSY at any time. 534b3040e40SJassi Brar */ 535b3040e40SJassi Brar BUSY, 536b3040e40SJassi Brar /* 537b3040e40SJassi Brar * Sitting on the channel work_list but xfer done 538b3040e40SJassi Brar * by PL330 core 539b3040e40SJassi Brar */ 540b3040e40SJassi Brar DONE, 541b3040e40SJassi Brar }; 542b3040e40SJassi Brar 543b3040e40SJassi Brar struct dma_pl330_chan { 544b3040e40SJassi Brar /* Schedule desc completion */ 545b3040e40SJassi Brar struct tasklet_struct task; 546b3040e40SJassi Brar 547b3040e40SJassi Brar /* DMA-Engine Channel */ 548b3040e40SJassi Brar struct dma_chan chan; 549b3040e40SJassi Brar 550b3040e40SJassi Brar /* List of to be xfered descriptors */ 551b3040e40SJassi Brar struct list_head work_list; 552b3040e40SJassi Brar 553b3040e40SJassi Brar /* Pointer to the DMAC that manages this channel, 554b3040e40SJassi Brar * NULL if the channel is available to be acquired. 555b3040e40SJassi Brar * As the parent, this DMAC also provides descriptors 556b3040e40SJassi Brar * to the channel. 557b3040e40SJassi Brar */ 558b3040e40SJassi Brar struct dma_pl330_dmac *dmac; 559b3040e40SJassi Brar 560b3040e40SJassi Brar /* To protect channel manipulation */ 561b3040e40SJassi Brar spinlock_t lock; 562b3040e40SJassi Brar 563b3040e40SJassi Brar /* Token of a hardware channel thread of PL330 DMAC 564b3040e40SJassi Brar * NULL if the channel is available to be acquired. 565b3040e40SJassi Brar */ 566b3040e40SJassi Brar void *pl330_chid; 5671b9bb715SBoojin Kim 5681b9bb715SBoojin Kim /* For D-to-M and M-to-D channels */ 5691b9bb715SBoojin Kim int burst_sz; /* the peripheral fifo width */ 5701d0c1d60SBoojin Kim int burst_len; /* the number of burst */ 5711b9bb715SBoojin Kim dma_addr_t fifo_addr; 57242bc9cf4SBoojin Kim 57342bc9cf4SBoojin Kim /* for cyclic capability */ 57442bc9cf4SBoojin Kim bool cyclic; 575b3040e40SJassi Brar }; 576b3040e40SJassi Brar 577b3040e40SJassi Brar struct dma_pl330_dmac { 578b3040e40SJassi Brar struct pl330_info pif; 579b3040e40SJassi Brar 580b3040e40SJassi Brar /* DMA-Engine Device */ 581b3040e40SJassi Brar struct dma_device ddma; 582b3040e40SJassi Brar 583b3040e40SJassi Brar /* Pool of descriptors available for the DMAC's channels */ 584b3040e40SJassi Brar struct list_head desc_pool; 585b3040e40SJassi Brar /* To protect desc_pool manipulation */ 586b3040e40SJassi Brar spinlock_t pool_lock; 587b3040e40SJassi Brar 588b3040e40SJassi Brar /* Peripheral channels connected to this DMAC */ 5894e0e6109SRob Herring struct dma_pl330_chan *peripherals; /* keep at end */ 590b3040e40SJassi Brar }; 591b3040e40SJassi Brar 592b3040e40SJassi Brar struct dma_pl330_desc { 593b3040e40SJassi Brar /* To attach to a queue as child */ 594b3040e40SJassi Brar struct list_head node; 595b3040e40SJassi Brar 596b3040e40SJassi Brar /* Descriptor for the DMA Engine API */ 597b3040e40SJassi Brar struct dma_async_tx_descriptor txd; 598b3040e40SJassi Brar 599b3040e40SJassi Brar /* Xfer for PL330 core */ 600b3040e40SJassi Brar struct pl330_xfer px; 601b3040e40SJassi Brar 602b3040e40SJassi Brar struct pl330_reqcfg rqcfg; 603b3040e40SJassi Brar struct pl330_req req; 604b3040e40SJassi Brar 605b3040e40SJassi Brar enum desc_status status; 606b3040e40SJassi Brar 607b3040e40SJassi Brar /* The channel which currently holds this desc */ 608b3040e40SJassi Brar struct dma_pl330_chan *pchan; 609b3040e40SJassi Brar }; 610b3040e40SJassi Brar 61134d19355SPadmavathi Venna struct dma_pl330_filter_args { 61234d19355SPadmavathi Venna struct dma_pl330_dmac *pdmac; 61334d19355SPadmavathi Venna unsigned int chan_id; 61434d19355SPadmavathi Venna }; 61534d19355SPadmavathi Venna 616b7d861d9SBoojin Kim static inline void _callback(struct pl330_req *r, enum pl330_op_err err) 617b7d861d9SBoojin Kim { 618b7d861d9SBoojin Kim if (r && r->xfer_cb) 619b7d861d9SBoojin Kim r->xfer_cb(r->token, err); 620b7d861d9SBoojin Kim } 621b7d861d9SBoojin Kim 622b7d861d9SBoojin Kim static inline bool _queue_empty(struct pl330_thread *thrd) 623b7d861d9SBoojin Kim { 624b7d861d9SBoojin Kim return (IS_FREE(&thrd->req[0]) && IS_FREE(&thrd->req[1])) 625b7d861d9SBoojin Kim ? true : false; 626b7d861d9SBoojin Kim } 627b7d861d9SBoojin Kim 628b7d861d9SBoojin Kim static inline bool _queue_full(struct pl330_thread *thrd) 629b7d861d9SBoojin Kim { 630b7d861d9SBoojin Kim return (IS_FREE(&thrd->req[0]) || IS_FREE(&thrd->req[1])) 631b7d861d9SBoojin Kim ? false : true; 632b7d861d9SBoojin Kim } 633b7d861d9SBoojin Kim 634b7d861d9SBoojin Kim static inline bool is_manager(struct pl330_thread *thrd) 635b7d861d9SBoojin Kim { 636b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 637b7d861d9SBoojin Kim 638b7d861d9SBoojin Kim /* MANAGER is indexed at the end */ 639b7d861d9SBoojin Kim if (thrd->id == pl330->pinfo->pcfg.num_chan) 640b7d861d9SBoojin Kim return true; 641b7d861d9SBoojin Kim else 642b7d861d9SBoojin Kim return false; 643b7d861d9SBoojin Kim } 644b7d861d9SBoojin Kim 645b7d861d9SBoojin Kim /* If manager of the thread is in Non-Secure mode */ 646b7d861d9SBoojin Kim static inline bool _manager_ns(struct pl330_thread *thrd) 647b7d861d9SBoojin Kim { 648b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 649b7d861d9SBoojin Kim 650b7d861d9SBoojin Kim return (pl330->pinfo->pcfg.mode & DMAC_MODE_NS) ? true : false; 651b7d861d9SBoojin Kim } 652b7d861d9SBoojin Kim 653b7d861d9SBoojin Kim static inline u32 get_id(struct pl330_info *pi, u32 off) 654b7d861d9SBoojin Kim { 655b7d861d9SBoojin Kim void __iomem *regs = pi->base; 656b7d861d9SBoojin Kim u32 id = 0; 657b7d861d9SBoojin Kim 658b7d861d9SBoojin Kim id |= (readb(regs + off + 0x0) << 0); 659b7d861d9SBoojin Kim id |= (readb(regs + off + 0x4) << 8); 660b7d861d9SBoojin Kim id |= (readb(regs + off + 0x8) << 16); 661b7d861d9SBoojin Kim id |= (readb(regs + off + 0xc) << 24); 662b7d861d9SBoojin Kim 663b7d861d9SBoojin Kim return id; 664b7d861d9SBoojin Kim } 665b7d861d9SBoojin Kim 6663ecf51a4SBoojin Kim static inline u32 get_revision(u32 periph_id) 6673ecf51a4SBoojin Kim { 6683ecf51a4SBoojin Kim return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; 6693ecf51a4SBoojin Kim } 6703ecf51a4SBoojin Kim 671b7d861d9SBoojin Kim static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[], 672b7d861d9SBoojin Kim enum pl330_dst da, u16 val) 673b7d861d9SBoojin Kim { 674b7d861d9SBoojin Kim if (dry_run) 675b7d861d9SBoojin Kim return SZ_DMAADDH; 676b7d861d9SBoojin Kim 677b7d861d9SBoojin Kim buf[0] = CMD_DMAADDH; 678b7d861d9SBoojin Kim buf[0] |= (da << 1); 679b7d861d9SBoojin Kim *((u16 *)&buf[1]) = val; 680b7d861d9SBoojin Kim 681b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n", 682b7d861d9SBoojin Kim da == 1 ? "DA" : "SA", val); 683b7d861d9SBoojin Kim 684b7d861d9SBoojin Kim return SZ_DMAADDH; 685b7d861d9SBoojin Kim } 686b7d861d9SBoojin Kim 687b7d861d9SBoojin Kim static inline u32 _emit_END(unsigned dry_run, u8 buf[]) 688b7d861d9SBoojin Kim { 689b7d861d9SBoojin Kim if (dry_run) 690b7d861d9SBoojin Kim return SZ_DMAEND; 691b7d861d9SBoojin Kim 692b7d861d9SBoojin Kim buf[0] = CMD_DMAEND; 693b7d861d9SBoojin Kim 694b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); 695b7d861d9SBoojin Kim 696b7d861d9SBoojin Kim return SZ_DMAEND; 697b7d861d9SBoojin Kim } 698b7d861d9SBoojin Kim 699b7d861d9SBoojin Kim static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) 700b7d861d9SBoojin Kim { 701b7d861d9SBoojin Kim if (dry_run) 702b7d861d9SBoojin Kim return SZ_DMAFLUSHP; 703b7d861d9SBoojin Kim 704b7d861d9SBoojin Kim buf[0] = CMD_DMAFLUSHP; 705b7d861d9SBoojin Kim 706b7d861d9SBoojin Kim peri &= 0x1f; 707b7d861d9SBoojin Kim peri <<= 3; 708b7d861d9SBoojin Kim buf[1] = peri; 709b7d861d9SBoojin Kim 710b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); 711b7d861d9SBoojin Kim 712b7d861d9SBoojin Kim return SZ_DMAFLUSHP; 713b7d861d9SBoojin Kim } 714b7d861d9SBoojin Kim 715b7d861d9SBoojin Kim static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) 716b7d861d9SBoojin Kim { 717b7d861d9SBoojin Kim if (dry_run) 718b7d861d9SBoojin Kim return SZ_DMALD; 719b7d861d9SBoojin Kim 720b7d861d9SBoojin Kim buf[0] = CMD_DMALD; 721b7d861d9SBoojin Kim 722b7d861d9SBoojin Kim if (cond == SINGLE) 723b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 724b7d861d9SBoojin Kim else if (cond == BURST) 725b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (1 << 0); 726b7d861d9SBoojin Kim 727b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", 728b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); 729b7d861d9SBoojin Kim 730b7d861d9SBoojin Kim return SZ_DMALD; 731b7d861d9SBoojin Kim } 732b7d861d9SBoojin Kim 733b7d861d9SBoojin Kim static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], 734b7d861d9SBoojin Kim enum pl330_cond cond, u8 peri) 735b7d861d9SBoojin Kim { 736b7d861d9SBoojin Kim if (dry_run) 737b7d861d9SBoojin Kim return SZ_DMALDP; 738b7d861d9SBoojin Kim 739b7d861d9SBoojin Kim buf[0] = CMD_DMALDP; 740b7d861d9SBoojin Kim 741b7d861d9SBoojin Kim if (cond == BURST) 742b7d861d9SBoojin Kim buf[0] |= (1 << 1); 743b7d861d9SBoojin Kim 744b7d861d9SBoojin Kim peri &= 0x1f; 745b7d861d9SBoojin Kim peri <<= 3; 746b7d861d9SBoojin Kim buf[1] = peri; 747b7d861d9SBoojin Kim 748b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", 749b7d861d9SBoojin Kim cond == SINGLE ? 'S' : 'B', peri >> 3); 750b7d861d9SBoojin Kim 751b7d861d9SBoojin Kim return SZ_DMALDP; 752b7d861d9SBoojin Kim } 753b7d861d9SBoojin Kim 754b7d861d9SBoojin Kim static inline u32 _emit_LP(unsigned dry_run, u8 buf[], 755b7d861d9SBoojin Kim unsigned loop, u8 cnt) 756b7d861d9SBoojin Kim { 757b7d861d9SBoojin Kim if (dry_run) 758b7d861d9SBoojin Kim return SZ_DMALP; 759b7d861d9SBoojin Kim 760b7d861d9SBoojin Kim buf[0] = CMD_DMALP; 761b7d861d9SBoojin Kim 762b7d861d9SBoojin Kim if (loop) 763b7d861d9SBoojin Kim buf[0] |= (1 << 1); 764b7d861d9SBoojin Kim 765b7d861d9SBoojin Kim cnt--; /* DMAC increments by 1 internally */ 766b7d861d9SBoojin Kim buf[1] = cnt; 767b7d861d9SBoojin Kim 768b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); 769b7d861d9SBoojin Kim 770b7d861d9SBoojin Kim return SZ_DMALP; 771b7d861d9SBoojin Kim } 772b7d861d9SBoojin Kim 773b7d861d9SBoojin Kim struct _arg_LPEND { 774b7d861d9SBoojin Kim enum pl330_cond cond; 775b7d861d9SBoojin Kim bool forever; 776b7d861d9SBoojin Kim unsigned loop; 777b7d861d9SBoojin Kim u8 bjump; 778b7d861d9SBoojin Kim }; 779b7d861d9SBoojin Kim 780b7d861d9SBoojin Kim static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], 781b7d861d9SBoojin Kim const struct _arg_LPEND *arg) 782b7d861d9SBoojin Kim { 783b7d861d9SBoojin Kim enum pl330_cond cond = arg->cond; 784b7d861d9SBoojin Kim bool forever = arg->forever; 785b7d861d9SBoojin Kim unsigned loop = arg->loop; 786b7d861d9SBoojin Kim u8 bjump = arg->bjump; 787b7d861d9SBoojin Kim 788b7d861d9SBoojin Kim if (dry_run) 789b7d861d9SBoojin Kim return SZ_DMALPEND; 790b7d861d9SBoojin Kim 791b7d861d9SBoojin Kim buf[0] = CMD_DMALPEND; 792b7d861d9SBoojin Kim 793b7d861d9SBoojin Kim if (loop) 794b7d861d9SBoojin Kim buf[0] |= (1 << 2); 795b7d861d9SBoojin Kim 796b7d861d9SBoojin Kim if (!forever) 797b7d861d9SBoojin Kim buf[0] |= (1 << 4); 798b7d861d9SBoojin Kim 799b7d861d9SBoojin Kim if (cond == SINGLE) 800b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 801b7d861d9SBoojin Kim else if (cond == BURST) 802b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (1 << 0); 803b7d861d9SBoojin Kim 804b7d861d9SBoojin Kim buf[1] = bjump; 805b7d861d9SBoojin Kim 806b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", 807b7d861d9SBoojin Kim forever ? "FE" : "END", 808b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), 809b7d861d9SBoojin Kim loop ? '1' : '0', 810b7d861d9SBoojin Kim bjump); 811b7d861d9SBoojin Kim 812b7d861d9SBoojin Kim return SZ_DMALPEND; 813b7d861d9SBoojin Kim } 814b7d861d9SBoojin Kim 815b7d861d9SBoojin Kim static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) 816b7d861d9SBoojin Kim { 817b7d861d9SBoojin Kim if (dry_run) 818b7d861d9SBoojin Kim return SZ_DMAKILL; 819b7d861d9SBoojin Kim 820b7d861d9SBoojin Kim buf[0] = CMD_DMAKILL; 821b7d861d9SBoojin Kim 822b7d861d9SBoojin Kim return SZ_DMAKILL; 823b7d861d9SBoojin Kim } 824b7d861d9SBoojin Kim 825b7d861d9SBoojin Kim static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], 826b7d861d9SBoojin Kim enum dmamov_dst dst, u32 val) 827b7d861d9SBoojin Kim { 828b7d861d9SBoojin Kim if (dry_run) 829b7d861d9SBoojin Kim return SZ_DMAMOV; 830b7d861d9SBoojin Kim 831b7d861d9SBoojin Kim buf[0] = CMD_DMAMOV; 832b7d861d9SBoojin Kim buf[1] = dst; 833b7d861d9SBoojin Kim *((u32 *)&buf[2]) = val; 834b7d861d9SBoojin Kim 835b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", 836b7d861d9SBoojin Kim dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); 837b7d861d9SBoojin Kim 838b7d861d9SBoojin Kim return SZ_DMAMOV; 839b7d861d9SBoojin Kim } 840b7d861d9SBoojin Kim 841b7d861d9SBoojin Kim static inline u32 _emit_NOP(unsigned dry_run, u8 buf[]) 842b7d861d9SBoojin Kim { 843b7d861d9SBoojin Kim if (dry_run) 844b7d861d9SBoojin Kim return SZ_DMANOP; 845b7d861d9SBoojin Kim 846b7d861d9SBoojin Kim buf[0] = CMD_DMANOP; 847b7d861d9SBoojin Kim 848b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n"); 849b7d861d9SBoojin Kim 850b7d861d9SBoojin Kim return SZ_DMANOP; 851b7d861d9SBoojin Kim } 852b7d861d9SBoojin Kim 853b7d861d9SBoojin Kim static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) 854b7d861d9SBoojin Kim { 855b7d861d9SBoojin Kim if (dry_run) 856b7d861d9SBoojin Kim return SZ_DMARMB; 857b7d861d9SBoojin Kim 858b7d861d9SBoojin Kim buf[0] = CMD_DMARMB; 859b7d861d9SBoojin Kim 860b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); 861b7d861d9SBoojin Kim 862b7d861d9SBoojin Kim return SZ_DMARMB; 863b7d861d9SBoojin Kim } 864b7d861d9SBoojin Kim 865b7d861d9SBoojin Kim static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) 866b7d861d9SBoojin Kim { 867b7d861d9SBoojin Kim if (dry_run) 868b7d861d9SBoojin Kim return SZ_DMASEV; 869b7d861d9SBoojin Kim 870b7d861d9SBoojin Kim buf[0] = CMD_DMASEV; 871b7d861d9SBoojin Kim 872b7d861d9SBoojin Kim ev &= 0x1f; 873b7d861d9SBoojin Kim ev <<= 3; 874b7d861d9SBoojin Kim buf[1] = ev; 875b7d861d9SBoojin Kim 876b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); 877b7d861d9SBoojin Kim 878b7d861d9SBoojin Kim return SZ_DMASEV; 879b7d861d9SBoojin Kim } 880b7d861d9SBoojin Kim 881b7d861d9SBoojin Kim static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) 882b7d861d9SBoojin Kim { 883b7d861d9SBoojin Kim if (dry_run) 884b7d861d9SBoojin Kim return SZ_DMAST; 885b7d861d9SBoojin Kim 886b7d861d9SBoojin Kim buf[0] = CMD_DMAST; 887b7d861d9SBoojin Kim 888b7d861d9SBoojin Kim if (cond == SINGLE) 889b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 890b7d861d9SBoojin Kim else if (cond == BURST) 891b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (1 << 0); 892b7d861d9SBoojin Kim 893b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", 894b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); 895b7d861d9SBoojin Kim 896b7d861d9SBoojin Kim return SZ_DMAST; 897b7d861d9SBoojin Kim } 898b7d861d9SBoojin Kim 899b7d861d9SBoojin Kim static inline u32 _emit_STP(unsigned dry_run, u8 buf[], 900b7d861d9SBoojin Kim enum pl330_cond cond, u8 peri) 901b7d861d9SBoojin Kim { 902b7d861d9SBoojin Kim if (dry_run) 903b7d861d9SBoojin Kim return SZ_DMASTP; 904b7d861d9SBoojin Kim 905b7d861d9SBoojin Kim buf[0] = CMD_DMASTP; 906b7d861d9SBoojin Kim 907b7d861d9SBoojin Kim if (cond == BURST) 908b7d861d9SBoojin Kim buf[0] |= (1 << 1); 909b7d861d9SBoojin Kim 910b7d861d9SBoojin Kim peri &= 0x1f; 911b7d861d9SBoojin Kim peri <<= 3; 912b7d861d9SBoojin Kim buf[1] = peri; 913b7d861d9SBoojin Kim 914b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", 915b7d861d9SBoojin Kim cond == SINGLE ? 'S' : 'B', peri >> 3); 916b7d861d9SBoojin Kim 917b7d861d9SBoojin Kim return SZ_DMASTP; 918b7d861d9SBoojin Kim } 919b7d861d9SBoojin Kim 920b7d861d9SBoojin Kim static inline u32 _emit_STZ(unsigned dry_run, u8 buf[]) 921b7d861d9SBoojin Kim { 922b7d861d9SBoojin Kim if (dry_run) 923b7d861d9SBoojin Kim return SZ_DMASTZ; 924b7d861d9SBoojin Kim 925b7d861d9SBoojin Kim buf[0] = CMD_DMASTZ; 926b7d861d9SBoojin Kim 927b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n"); 928b7d861d9SBoojin Kim 929b7d861d9SBoojin Kim return SZ_DMASTZ; 930b7d861d9SBoojin Kim } 931b7d861d9SBoojin Kim 932b7d861d9SBoojin Kim static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, 933b7d861d9SBoojin Kim unsigned invalidate) 934b7d861d9SBoojin Kim { 935b7d861d9SBoojin Kim if (dry_run) 936b7d861d9SBoojin Kim return SZ_DMAWFE; 937b7d861d9SBoojin Kim 938b7d861d9SBoojin Kim buf[0] = CMD_DMAWFE; 939b7d861d9SBoojin Kim 940b7d861d9SBoojin Kim ev &= 0x1f; 941b7d861d9SBoojin Kim ev <<= 3; 942b7d861d9SBoojin Kim buf[1] = ev; 943b7d861d9SBoojin Kim 944b7d861d9SBoojin Kim if (invalidate) 945b7d861d9SBoojin Kim buf[1] |= (1 << 1); 946b7d861d9SBoojin Kim 947b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n", 948b7d861d9SBoojin Kim ev >> 3, invalidate ? ", I" : ""); 949b7d861d9SBoojin Kim 950b7d861d9SBoojin Kim return SZ_DMAWFE; 951b7d861d9SBoojin Kim } 952b7d861d9SBoojin Kim 953b7d861d9SBoojin Kim static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], 954b7d861d9SBoojin Kim enum pl330_cond cond, u8 peri) 955b7d861d9SBoojin Kim { 956b7d861d9SBoojin Kim if (dry_run) 957b7d861d9SBoojin Kim return SZ_DMAWFP; 958b7d861d9SBoojin Kim 959b7d861d9SBoojin Kim buf[0] = CMD_DMAWFP; 960b7d861d9SBoojin Kim 961b7d861d9SBoojin Kim if (cond == SINGLE) 962b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (0 << 0); 963b7d861d9SBoojin Kim else if (cond == BURST) 964b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (0 << 0); 965b7d861d9SBoojin Kim else 966b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 967b7d861d9SBoojin Kim 968b7d861d9SBoojin Kim peri &= 0x1f; 969b7d861d9SBoojin Kim peri <<= 3; 970b7d861d9SBoojin Kim buf[1] = peri; 971b7d861d9SBoojin Kim 972b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", 973b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); 974b7d861d9SBoojin Kim 975b7d861d9SBoojin Kim return SZ_DMAWFP; 976b7d861d9SBoojin Kim } 977b7d861d9SBoojin Kim 978b7d861d9SBoojin Kim static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) 979b7d861d9SBoojin Kim { 980b7d861d9SBoojin Kim if (dry_run) 981b7d861d9SBoojin Kim return SZ_DMAWMB; 982b7d861d9SBoojin Kim 983b7d861d9SBoojin Kim buf[0] = CMD_DMAWMB; 984b7d861d9SBoojin Kim 985b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); 986b7d861d9SBoojin Kim 987b7d861d9SBoojin Kim return SZ_DMAWMB; 988b7d861d9SBoojin Kim } 989b7d861d9SBoojin Kim 990b7d861d9SBoojin Kim struct _arg_GO { 991b7d861d9SBoojin Kim u8 chan; 992b7d861d9SBoojin Kim u32 addr; 993b7d861d9SBoojin Kim unsigned ns; 994b7d861d9SBoojin Kim }; 995b7d861d9SBoojin Kim 996b7d861d9SBoojin Kim static inline u32 _emit_GO(unsigned dry_run, u8 buf[], 997b7d861d9SBoojin Kim const struct _arg_GO *arg) 998b7d861d9SBoojin Kim { 999b7d861d9SBoojin Kim u8 chan = arg->chan; 1000b7d861d9SBoojin Kim u32 addr = arg->addr; 1001b7d861d9SBoojin Kim unsigned ns = arg->ns; 1002b7d861d9SBoojin Kim 1003b7d861d9SBoojin Kim if (dry_run) 1004b7d861d9SBoojin Kim return SZ_DMAGO; 1005b7d861d9SBoojin Kim 1006b7d861d9SBoojin Kim buf[0] = CMD_DMAGO; 1007b7d861d9SBoojin Kim buf[0] |= (ns << 1); 1008b7d861d9SBoojin Kim 1009b7d861d9SBoojin Kim buf[1] = chan & 0x7; 1010b7d861d9SBoojin Kim 1011b7d861d9SBoojin Kim *((u32 *)&buf[2]) = addr; 1012b7d861d9SBoojin Kim 1013b7d861d9SBoojin Kim return SZ_DMAGO; 1014b7d861d9SBoojin Kim } 1015b7d861d9SBoojin Kim 1016b7d861d9SBoojin Kim #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 1017b7d861d9SBoojin Kim 1018b7d861d9SBoojin Kim /* Returns Time-Out */ 1019b7d861d9SBoojin Kim static bool _until_dmac_idle(struct pl330_thread *thrd) 1020b7d861d9SBoojin Kim { 1021b7d861d9SBoojin Kim void __iomem *regs = thrd->dmac->pinfo->base; 1022b7d861d9SBoojin Kim unsigned long loops = msecs_to_loops(5); 1023b7d861d9SBoojin Kim 1024b7d861d9SBoojin Kim do { 1025b7d861d9SBoojin Kim /* Until Manager is Idle */ 1026b7d861d9SBoojin Kim if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) 1027b7d861d9SBoojin Kim break; 1028b7d861d9SBoojin Kim 1029b7d861d9SBoojin Kim cpu_relax(); 1030b7d861d9SBoojin Kim } while (--loops); 1031b7d861d9SBoojin Kim 1032b7d861d9SBoojin Kim if (!loops) 1033b7d861d9SBoojin Kim return true; 1034b7d861d9SBoojin Kim 1035b7d861d9SBoojin Kim return false; 1036b7d861d9SBoojin Kim } 1037b7d861d9SBoojin Kim 1038b7d861d9SBoojin Kim static inline void _execute_DBGINSN(struct pl330_thread *thrd, 1039b7d861d9SBoojin Kim u8 insn[], bool as_manager) 1040b7d861d9SBoojin Kim { 1041b7d861d9SBoojin Kim void __iomem *regs = thrd->dmac->pinfo->base; 1042b7d861d9SBoojin Kim u32 val; 1043b7d861d9SBoojin Kim 1044b7d861d9SBoojin Kim val = (insn[0] << 16) | (insn[1] << 24); 1045b7d861d9SBoojin Kim if (!as_manager) { 1046b7d861d9SBoojin Kim val |= (1 << 0); 1047b7d861d9SBoojin Kim val |= (thrd->id << 8); /* Channel Number */ 1048b7d861d9SBoojin Kim } 1049b7d861d9SBoojin Kim writel(val, regs + DBGINST0); 1050b7d861d9SBoojin Kim 1051b7d861d9SBoojin Kim val = *((u32 *)&insn[2]); 1052b7d861d9SBoojin Kim writel(val, regs + DBGINST1); 1053b7d861d9SBoojin Kim 1054b7d861d9SBoojin Kim /* If timed out due to halted state-machine */ 1055b7d861d9SBoojin Kim if (_until_dmac_idle(thrd)) { 1056b7d861d9SBoojin Kim dev_err(thrd->dmac->pinfo->dev, "DMAC halted!\n"); 1057b7d861d9SBoojin Kim return; 1058b7d861d9SBoojin Kim } 1059b7d861d9SBoojin Kim 1060b7d861d9SBoojin Kim /* Get going */ 1061b7d861d9SBoojin Kim writel(0, regs + DBGCMD); 1062b7d861d9SBoojin Kim } 1063b7d861d9SBoojin Kim 1064b7d861d9SBoojin Kim /* 1065b7d861d9SBoojin Kim * Mark a _pl330_req as free. 1066b7d861d9SBoojin Kim * We do it by writing DMAEND as the first instruction 1067b7d861d9SBoojin Kim * because no valid request is going to have DMAEND as 1068b7d861d9SBoojin Kim * its first instruction to execute. 1069b7d861d9SBoojin Kim */ 1070b7d861d9SBoojin Kim static void mark_free(struct pl330_thread *thrd, int idx) 1071b7d861d9SBoojin Kim { 1072b7d861d9SBoojin Kim struct _pl330_req *req = &thrd->req[idx]; 1073b7d861d9SBoojin Kim 1074b7d861d9SBoojin Kim _emit_END(0, req->mc_cpu); 1075b7d861d9SBoojin Kim req->mc_len = 0; 1076b7d861d9SBoojin Kim 1077b7d861d9SBoojin Kim thrd->req_running = -1; 1078b7d861d9SBoojin Kim } 1079b7d861d9SBoojin Kim 1080b7d861d9SBoojin Kim static inline u32 _state(struct pl330_thread *thrd) 1081b7d861d9SBoojin Kim { 1082b7d861d9SBoojin Kim void __iomem *regs = thrd->dmac->pinfo->base; 1083b7d861d9SBoojin Kim u32 val; 1084b7d861d9SBoojin Kim 1085b7d861d9SBoojin Kim if (is_manager(thrd)) 1086b7d861d9SBoojin Kim val = readl(regs + DS) & 0xf; 1087b7d861d9SBoojin Kim else 1088b7d861d9SBoojin Kim val = readl(regs + CS(thrd->id)) & 0xf; 1089b7d861d9SBoojin Kim 1090b7d861d9SBoojin Kim switch (val) { 1091b7d861d9SBoojin Kim case DS_ST_STOP: 1092b7d861d9SBoojin Kim return PL330_STATE_STOPPED; 1093b7d861d9SBoojin Kim case DS_ST_EXEC: 1094b7d861d9SBoojin Kim return PL330_STATE_EXECUTING; 1095b7d861d9SBoojin Kim case DS_ST_CMISS: 1096b7d861d9SBoojin Kim return PL330_STATE_CACHEMISS; 1097b7d861d9SBoojin Kim case DS_ST_UPDTPC: 1098b7d861d9SBoojin Kim return PL330_STATE_UPDTPC; 1099b7d861d9SBoojin Kim case DS_ST_WFE: 1100b7d861d9SBoojin Kim return PL330_STATE_WFE; 1101b7d861d9SBoojin Kim case DS_ST_FAULT: 1102b7d861d9SBoojin Kim return PL330_STATE_FAULTING; 1103b7d861d9SBoojin Kim case DS_ST_ATBRR: 1104b7d861d9SBoojin Kim if (is_manager(thrd)) 1105b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1106b7d861d9SBoojin Kim else 1107b7d861d9SBoojin Kim return PL330_STATE_ATBARRIER; 1108b7d861d9SBoojin Kim case DS_ST_QBUSY: 1109b7d861d9SBoojin Kim if (is_manager(thrd)) 1110b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1111b7d861d9SBoojin Kim else 1112b7d861d9SBoojin Kim return PL330_STATE_QUEUEBUSY; 1113b7d861d9SBoojin Kim case DS_ST_WFP: 1114b7d861d9SBoojin Kim if (is_manager(thrd)) 1115b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1116b7d861d9SBoojin Kim else 1117b7d861d9SBoojin Kim return PL330_STATE_WFP; 1118b7d861d9SBoojin Kim case DS_ST_KILL: 1119b7d861d9SBoojin Kim if (is_manager(thrd)) 1120b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1121b7d861d9SBoojin Kim else 1122b7d861d9SBoojin Kim return PL330_STATE_KILLING; 1123b7d861d9SBoojin Kim case DS_ST_CMPLT: 1124b7d861d9SBoojin Kim if (is_manager(thrd)) 1125b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1126b7d861d9SBoojin Kim else 1127b7d861d9SBoojin Kim return PL330_STATE_COMPLETING; 1128b7d861d9SBoojin Kim case DS_ST_FLTCMP: 1129b7d861d9SBoojin Kim if (is_manager(thrd)) 1130b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1131b7d861d9SBoojin Kim else 1132b7d861d9SBoojin Kim return PL330_STATE_FAULT_COMPLETING; 1133b7d861d9SBoojin Kim default: 1134b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1135b7d861d9SBoojin Kim } 1136b7d861d9SBoojin Kim } 1137b7d861d9SBoojin Kim 1138b7d861d9SBoojin Kim static void _stop(struct pl330_thread *thrd) 1139b7d861d9SBoojin Kim { 1140b7d861d9SBoojin Kim void __iomem *regs = thrd->dmac->pinfo->base; 1141b7d861d9SBoojin Kim u8 insn[6] = {0, 0, 0, 0, 0, 0}; 1142b7d861d9SBoojin Kim 1143b7d861d9SBoojin Kim if (_state(thrd) == PL330_STATE_FAULT_COMPLETING) 1144b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); 1145b7d861d9SBoojin Kim 1146b7d861d9SBoojin Kim /* Return if nothing needs to be done */ 1147b7d861d9SBoojin Kim if (_state(thrd) == PL330_STATE_COMPLETING 1148b7d861d9SBoojin Kim || _state(thrd) == PL330_STATE_KILLING 1149b7d861d9SBoojin Kim || _state(thrd) == PL330_STATE_STOPPED) 1150b7d861d9SBoojin Kim return; 1151b7d861d9SBoojin Kim 1152b7d861d9SBoojin Kim _emit_KILL(0, insn); 1153b7d861d9SBoojin Kim 1154b7d861d9SBoojin Kim /* Stop generating interrupts for SEV */ 1155b7d861d9SBoojin Kim writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN); 1156b7d861d9SBoojin Kim 1157b7d861d9SBoojin Kim _execute_DBGINSN(thrd, insn, is_manager(thrd)); 1158b7d861d9SBoojin Kim } 1159b7d861d9SBoojin Kim 1160b7d861d9SBoojin Kim /* Start doing req 'idx' of thread 'thrd' */ 1161b7d861d9SBoojin Kim static bool _trigger(struct pl330_thread *thrd) 1162b7d861d9SBoojin Kim { 1163b7d861d9SBoojin Kim void __iomem *regs = thrd->dmac->pinfo->base; 1164b7d861d9SBoojin Kim struct _pl330_req *req; 1165b7d861d9SBoojin Kim struct pl330_req *r; 1166b7d861d9SBoojin Kim struct _arg_GO go; 1167b7d861d9SBoojin Kim unsigned ns; 1168b7d861d9SBoojin Kim u8 insn[6] = {0, 0, 0, 0, 0, 0}; 1169b7d861d9SBoojin Kim int idx; 1170b7d861d9SBoojin Kim 1171b7d861d9SBoojin Kim /* Return if already ACTIVE */ 1172b7d861d9SBoojin Kim if (_state(thrd) != PL330_STATE_STOPPED) 1173b7d861d9SBoojin Kim return true; 1174b7d861d9SBoojin Kim 1175b7d861d9SBoojin Kim idx = 1 - thrd->lstenq; 1176b7d861d9SBoojin Kim if (!IS_FREE(&thrd->req[idx])) 1177b7d861d9SBoojin Kim req = &thrd->req[idx]; 1178b7d861d9SBoojin Kim else { 1179b7d861d9SBoojin Kim idx = thrd->lstenq; 1180b7d861d9SBoojin Kim if (!IS_FREE(&thrd->req[idx])) 1181b7d861d9SBoojin Kim req = &thrd->req[idx]; 1182b7d861d9SBoojin Kim else 1183b7d861d9SBoojin Kim req = NULL; 1184b7d861d9SBoojin Kim } 1185b7d861d9SBoojin Kim 1186b7d861d9SBoojin Kim /* Return if no request */ 1187b7d861d9SBoojin Kim if (!req || !req->r) 1188b7d861d9SBoojin Kim return true; 1189b7d861d9SBoojin Kim 1190b7d861d9SBoojin Kim r = req->r; 1191b7d861d9SBoojin Kim 1192b7d861d9SBoojin Kim if (r->cfg) 1193b7d861d9SBoojin Kim ns = r->cfg->nonsecure ? 1 : 0; 1194b7d861d9SBoojin Kim else if (readl(regs + CS(thrd->id)) & CS_CNS) 1195b7d861d9SBoojin Kim ns = 1; 1196b7d861d9SBoojin Kim else 1197b7d861d9SBoojin Kim ns = 0; 1198b7d861d9SBoojin Kim 1199b7d861d9SBoojin Kim /* See 'Abort Sources' point-4 at Page 2-25 */ 1200b7d861d9SBoojin Kim if (_manager_ns(thrd) && !ns) 1201b7d861d9SBoojin Kim dev_info(thrd->dmac->pinfo->dev, "%s:%d Recipe for ABORT!\n", 1202b7d861d9SBoojin Kim __func__, __LINE__); 1203b7d861d9SBoojin Kim 1204b7d861d9SBoojin Kim go.chan = thrd->id; 1205b7d861d9SBoojin Kim go.addr = req->mc_bus; 1206b7d861d9SBoojin Kim go.ns = ns; 1207b7d861d9SBoojin Kim _emit_GO(0, insn, &go); 1208b7d861d9SBoojin Kim 1209b7d861d9SBoojin Kim /* Set to generate interrupts for SEV */ 1210b7d861d9SBoojin Kim writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); 1211b7d861d9SBoojin Kim 1212b7d861d9SBoojin Kim /* Only manager can execute GO */ 1213b7d861d9SBoojin Kim _execute_DBGINSN(thrd, insn, true); 1214b7d861d9SBoojin Kim 1215b7d861d9SBoojin Kim thrd->req_running = idx; 1216b7d861d9SBoojin Kim 1217b7d861d9SBoojin Kim return true; 1218b7d861d9SBoojin Kim } 1219b7d861d9SBoojin Kim 1220b7d861d9SBoojin Kim static bool _start(struct pl330_thread *thrd) 1221b7d861d9SBoojin Kim { 1222b7d861d9SBoojin Kim switch (_state(thrd)) { 1223b7d861d9SBoojin Kim case PL330_STATE_FAULT_COMPLETING: 1224b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); 1225b7d861d9SBoojin Kim 1226b7d861d9SBoojin Kim if (_state(thrd) == PL330_STATE_KILLING) 1227b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_STOPPED) 1228b7d861d9SBoojin Kim 1229b7d861d9SBoojin Kim case PL330_STATE_FAULTING: 1230b7d861d9SBoojin Kim _stop(thrd); 1231b7d861d9SBoojin Kim 1232b7d861d9SBoojin Kim case PL330_STATE_KILLING: 1233b7d861d9SBoojin Kim case PL330_STATE_COMPLETING: 1234b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_STOPPED) 1235b7d861d9SBoojin Kim 1236b7d861d9SBoojin Kim case PL330_STATE_STOPPED: 1237b7d861d9SBoojin Kim return _trigger(thrd); 1238b7d861d9SBoojin Kim 1239b7d861d9SBoojin Kim case PL330_STATE_WFP: 1240b7d861d9SBoojin Kim case PL330_STATE_QUEUEBUSY: 1241b7d861d9SBoojin Kim case PL330_STATE_ATBARRIER: 1242b7d861d9SBoojin Kim case PL330_STATE_UPDTPC: 1243b7d861d9SBoojin Kim case PL330_STATE_CACHEMISS: 1244b7d861d9SBoojin Kim case PL330_STATE_EXECUTING: 1245b7d861d9SBoojin Kim return true; 1246b7d861d9SBoojin Kim 1247b7d861d9SBoojin Kim case PL330_STATE_WFE: /* For RESUME, nothing yet */ 1248b7d861d9SBoojin Kim default: 1249b7d861d9SBoojin Kim return false; 1250b7d861d9SBoojin Kim } 1251b7d861d9SBoojin Kim } 1252b7d861d9SBoojin Kim 1253b7d861d9SBoojin Kim static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], 1254b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1255b7d861d9SBoojin Kim { 1256b7d861d9SBoojin Kim int off = 0; 12573ecf51a4SBoojin Kim struct pl330_config *pcfg = pxs->r->cfg->pcfg; 1258b7d861d9SBoojin Kim 12593ecf51a4SBoojin Kim /* check lock-up free version */ 12603ecf51a4SBoojin Kim if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { 12613ecf51a4SBoojin Kim while (cyc--) { 12623ecf51a4SBoojin Kim off += _emit_LD(dry_run, &buf[off], ALWAYS); 12633ecf51a4SBoojin Kim off += _emit_ST(dry_run, &buf[off], ALWAYS); 12643ecf51a4SBoojin Kim } 12653ecf51a4SBoojin Kim } else { 1266b7d861d9SBoojin Kim while (cyc--) { 1267b7d861d9SBoojin Kim off += _emit_LD(dry_run, &buf[off], ALWAYS); 1268b7d861d9SBoojin Kim off += _emit_RMB(dry_run, &buf[off]); 1269b7d861d9SBoojin Kim off += _emit_ST(dry_run, &buf[off], ALWAYS); 1270b7d861d9SBoojin Kim off += _emit_WMB(dry_run, &buf[off]); 1271b7d861d9SBoojin Kim } 12723ecf51a4SBoojin Kim } 1273b7d861d9SBoojin Kim 1274b7d861d9SBoojin Kim return off; 1275b7d861d9SBoojin Kim } 1276b7d861d9SBoojin Kim 1277b7d861d9SBoojin Kim static inline int _ldst_devtomem(unsigned dry_run, u8 buf[], 1278b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1279b7d861d9SBoojin Kim { 1280b7d861d9SBoojin Kim int off = 0; 1281b7d861d9SBoojin Kim 1282b7d861d9SBoojin Kim while (cyc--) { 1283b7d861d9SBoojin Kim off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri); 1284b7d861d9SBoojin Kim off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->r->peri); 1285b7d861d9SBoojin Kim off += _emit_ST(dry_run, &buf[off], ALWAYS); 1286b7d861d9SBoojin Kim off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri); 1287b7d861d9SBoojin Kim } 1288b7d861d9SBoojin Kim 1289b7d861d9SBoojin Kim return off; 1290b7d861d9SBoojin Kim } 1291b7d861d9SBoojin Kim 1292b7d861d9SBoojin Kim static inline int _ldst_memtodev(unsigned dry_run, u8 buf[], 1293b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1294b7d861d9SBoojin Kim { 1295b7d861d9SBoojin Kim int off = 0; 1296b7d861d9SBoojin Kim 1297b7d861d9SBoojin Kim while (cyc--) { 1298b7d861d9SBoojin Kim off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri); 1299b7d861d9SBoojin Kim off += _emit_LD(dry_run, &buf[off], ALWAYS); 1300b7d861d9SBoojin Kim off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->r->peri); 1301b7d861d9SBoojin Kim off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri); 1302b7d861d9SBoojin Kim } 1303b7d861d9SBoojin Kim 1304b7d861d9SBoojin Kim return off; 1305b7d861d9SBoojin Kim } 1306b7d861d9SBoojin Kim 1307b7d861d9SBoojin Kim static int _bursts(unsigned dry_run, u8 buf[], 1308b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1309b7d861d9SBoojin Kim { 1310b7d861d9SBoojin Kim int off = 0; 1311b7d861d9SBoojin Kim 1312b7d861d9SBoojin Kim switch (pxs->r->rqtype) { 1313b7d861d9SBoojin Kim case MEMTODEV: 1314b7d861d9SBoojin Kim off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc); 1315b7d861d9SBoojin Kim break; 1316b7d861d9SBoojin Kim case DEVTOMEM: 1317b7d861d9SBoojin Kim off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc); 1318b7d861d9SBoojin Kim break; 1319b7d861d9SBoojin Kim case MEMTOMEM: 1320b7d861d9SBoojin Kim off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); 1321b7d861d9SBoojin Kim break; 1322b7d861d9SBoojin Kim default: 1323b7d861d9SBoojin Kim off += 0x40000000; /* Scare off the Client */ 1324b7d861d9SBoojin Kim break; 1325b7d861d9SBoojin Kim } 1326b7d861d9SBoojin Kim 1327b7d861d9SBoojin Kim return off; 1328b7d861d9SBoojin Kim } 1329b7d861d9SBoojin Kim 1330b7d861d9SBoojin Kim /* Returns bytes consumed and updates bursts */ 1331b7d861d9SBoojin Kim static inline int _loop(unsigned dry_run, u8 buf[], 1332b7d861d9SBoojin Kim unsigned long *bursts, const struct _xfer_spec *pxs) 1333b7d861d9SBoojin Kim { 1334b7d861d9SBoojin Kim int cyc, cycmax, szlp, szlpend, szbrst, off; 1335b7d861d9SBoojin Kim unsigned lcnt0, lcnt1, ljmp0, ljmp1; 1336b7d861d9SBoojin Kim struct _arg_LPEND lpend; 1337b7d861d9SBoojin Kim 1338b7d861d9SBoojin Kim /* Max iterations possible in DMALP is 256 */ 1339b7d861d9SBoojin Kim if (*bursts >= 256*256) { 1340b7d861d9SBoojin Kim lcnt1 = 256; 1341b7d861d9SBoojin Kim lcnt0 = 256; 1342b7d861d9SBoojin Kim cyc = *bursts / lcnt1 / lcnt0; 1343b7d861d9SBoojin Kim } else if (*bursts > 256) { 1344b7d861d9SBoojin Kim lcnt1 = 256; 1345b7d861d9SBoojin Kim lcnt0 = *bursts / lcnt1; 1346b7d861d9SBoojin Kim cyc = 1; 1347b7d861d9SBoojin Kim } else { 1348b7d861d9SBoojin Kim lcnt1 = *bursts; 1349b7d861d9SBoojin Kim lcnt0 = 0; 1350b7d861d9SBoojin Kim cyc = 1; 1351b7d861d9SBoojin Kim } 1352b7d861d9SBoojin Kim 1353b7d861d9SBoojin Kim szlp = _emit_LP(1, buf, 0, 0); 1354b7d861d9SBoojin Kim szbrst = _bursts(1, buf, pxs, 1); 1355b7d861d9SBoojin Kim 1356b7d861d9SBoojin Kim lpend.cond = ALWAYS; 1357b7d861d9SBoojin Kim lpend.forever = false; 1358b7d861d9SBoojin Kim lpend.loop = 0; 1359b7d861d9SBoojin Kim lpend.bjump = 0; 1360b7d861d9SBoojin Kim szlpend = _emit_LPEND(1, buf, &lpend); 1361b7d861d9SBoojin Kim 1362b7d861d9SBoojin Kim if (lcnt0) { 1363b7d861d9SBoojin Kim szlp *= 2; 1364b7d861d9SBoojin Kim szlpend *= 2; 1365b7d861d9SBoojin Kim } 1366b7d861d9SBoojin Kim 1367b7d861d9SBoojin Kim /* 1368b7d861d9SBoojin Kim * Max bursts that we can unroll due to limit on the 1369b7d861d9SBoojin Kim * size of backward jump that can be encoded in DMALPEND 1370b7d861d9SBoojin Kim * which is 8-bits and hence 255 1371b7d861d9SBoojin Kim */ 1372b7d861d9SBoojin Kim cycmax = (255 - (szlp + szlpend)) / szbrst; 1373b7d861d9SBoojin Kim 1374b7d861d9SBoojin Kim cyc = (cycmax < cyc) ? cycmax : cyc; 1375b7d861d9SBoojin Kim 1376b7d861d9SBoojin Kim off = 0; 1377b7d861d9SBoojin Kim 1378b7d861d9SBoojin Kim if (lcnt0) { 1379b7d861d9SBoojin Kim off += _emit_LP(dry_run, &buf[off], 0, lcnt0); 1380b7d861d9SBoojin Kim ljmp0 = off; 1381b7d861d9SBoojin Kim } 1382b7d861d9SBoojin Kim 1383b7d861d9SBoojin Kim off += _emit_LP(dry_run, &buf[off], 1, lcnt1); 1384b7d861d9SBoojin Kim ljmp1 = off; 1385b7d861d9SBoojin Kim 1386b7d861d9SBoojin Kim off += _bursts(dry_run, &buf[off], pxs, cyc); 1387b7d861d9SBoojin Kim 1388b7d861d9SBoojin Kim lpend.cond = ALWAYS; 1389b7d861d9SBoojin Kim lpend.forever = false; 1390b7d861d9SBoojin Kim lpend.loop = 1; 1391b7d861d9SBoojin Kim lpend.bjump = off - ljmp1; 1392b7d861d9SBoojin Kim off += _emit_LPEND(dry_run, &buf[off], &lpend); 1393b7d861d9SBoojin Kim 1394b7d861d9SBoojin Kim if (lcnt0) { 1395b7d861d9SBoojin Kim lpend.cond = ALWAYS; 1396b7d861d9SBoojin Kim lpend.forever = false; 1397b7d861d9SBoojin Kim lpend.loop = 0; 1398b7d861d9SBoojin Kim lpend.bjump = off - ljmp0; 1399b7d861d9SBoojin Kim off += _emit_LPEND(dry_run, &buf[off], &lpend); 1400b7d861d9SBoojin Kim } 1401b7d861d9SBoojin Kim 1402b7d861d9SBoojin Kim *bursts = lcnt1 * cyc; 1403b7d861d9SBoojin Kim if (lcnt0) 1404b7d861d9SBoojin Kim *bursts *= lcnt0; 1405b7d861d9SBoojin Kim 1406b7d861d9SBoojin Kim return off; 1407b7d861d9SBoojin Kim } 1408b7d861d9SBoojin Kim 1409b7d861d9SBoojin Kim static inline int _setup_loops(unsigned dry_run, u8 buf[], 1410b7d861d9SBoojin Kim const struct _xfer_spec *pxs) 1411b7d861d9SBoojin Kim { 1412b7d861d9SBoojin Kim struct pl330_xfer *x = pxs->x; 1413b7d861d9SBoojin Kim u32 ccr = pxs->ccr; 1414b7d861d9SBoojin Kim unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); 1415b7d861d9SBoojin Kim int off = 0; 1416b7d861d9SBoojin Kim 1417b7d861d9SBoojin Kim while (bursts) { 1418b7d861d9SBoojin Kim c = bursts; 1419b7d861d9SBoojin Kim off += _loop(dry_run, &buf[off], &c, pxs); 1420b7d861d9SBoojin Kim bursts -= c; 1421b7d861d9SBoojin Kim } 1422b7d861d9SBoojin Kim 1423b7d861d9SBoojin Kim return off; 1424b7d861d9SBoojin Kim } 1425b7d861d9SBoojin Kim 1426b7d861d9SBoojin Kim static inline int _setup_xfer(unsigned dry_run, u8 buf[], 1427b7d861d9SBoojin Kim const struct _xfer_spec *pxs) 1428b7d861d9SBoojin Kim { 1429b7d861d9SBoojin Kim struct pl330_xfer *x = pxs->x; 1430b7d861d9SBoojin Kim int off = 0; 1431b7d861d9SBoojin Kim 1432b7d861d9SBoojin Kim /* DMAMOV SAR, x->src_addr */ 1433b7d861d9SBoojin Kim off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); 1434b7d861d9SBoojin Kim /* DMAMOV DAR, x->dst_addr */ 1435b7d861d9SBoojin Kim off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr); 1436b7d861d9SBoojin Kim 1437b7d861d9SBoojin Kim /* Setup Loop(s) */ 1438b7d861d9SBoojin Kim off += _setup_loops(dry_run, &buf[off], pxs); 1439b7d861d9SBoojin Kim 1440b7d861d9SBoojin Kim return off; 1441b7d861d9SBoojin Kim } 1442b7d861d9SBoojin Kim 1443b7d861d9SBoojin Kim /* 1444b7d861d9SBoojin Kim * A req is a sequence of one or more xfer units. 1445b7d861d9SBoojin Kim * Returns the number of bytes taken to setup the MC for the req. 1446b7d861d9SBoojin Kim */ 1447b7d861d9SBoojin Kim static int _setup_req(unsigned dry_run, struct pl330_thread *thrd, 1448b7d861d9SBoojin Kim unsigned index, struct _xfer_spec *pxs) 1449b7d861d9SBoojin Kim { 1450b7d861d9SBoojin Kim struct _pl330_req *req = &thrd->req[index]; 1451b7d861d9SBoojin Kim struct pl330_xfer *x; 1452b7d861d9SBoojin Kim u8 *buf = req->mc_cpu; 1453b7d861d9SBoojin Kim int off = 0; 1454b7d861d9SBoojin Kim 1455b7d861d9SBoojin Kim PL330_DBGMC_START(req->mc_bus); 1456b7d861d9SBoojin Kim 1457b7d861d9SBoojin Kim /* DMAMOV CCR, ccr */ 1458b7d861d9SBoojin Kim off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); 1459b7d861d9SBoojin Kim 1460b7d861d9SBoojin Kim x = pxs->r->x; 1461b7d861d9SBoojin Kim do { 1462b7d861d9SBoojin Kim /* Error if xfer length is not aligned at burst size */ 1463b7d861d9SBoojin Kim if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr))) 1464b7d861d9SBoojin Kim return -EINVAL; 1465b7d861d9SBoojin Kim 1466b7d861d9SBoojin Kim pxs->x = x; 1467b7d861d9SBoojin Kim off += _setup_xfer(dry_run, &buf[off], pxs); 1468b7d861d9SBoojin Kim 1469b7d861d9SBoojin Kim x = x->next; 1470b7d861d9SBoojin Kim } while (x); 1471b7d861d9SBoojin Kim 1472b7d861d9SBoojin Kim /* DMASEV peripheral/event */ 1473b7d861d9SBoojin Kim off += _emit_SEV(dry_run, &buf[off], thrd->ev); 1474b7d861d9SBoojin Kim /* DMAEND */ 1475b7d861d9SBoojin Kim off += _emit_END(dry_run, &buf[off]); 1476b7d861d9SBoojin Kim 1477b7d861d9SBoojin Kim return off; 1478b7d861d9SBoojin Kim } 1479b7d861d9SBoojin Kim 1480b7d861d9SBoojin Kim static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) 1481b7d861d9SBoojin Kim { 1482b7d861d9SBoojin Kim u32 ccr = 0; 1483b7d861d9SBoojin Kim 1484b7d861d9SBoojin Kim if (rqc->src_inc) 1485b7d861d9SBoojin Kim ccr |= CC_SRCINC; 1486b7d861d9SBoojin Kim 1487b7d861d9SBoojin Kim if (rqc->dst_inc) 1488b7d861d9SBoojin Kim ccr |= CC_DSTINC; 1489b7d861d9SBoojin Kim 1490b7d861d9SBoojin Kim /* We set same protection levels for Src and DST for now */ 1491b7d861d9SBoojin Kim if (rqc->privileged) 1492b7d861d9SBoojin Kim ccr |= CC_SRCPRI | CC_DSTPRI; 1493b7d861d9SBoojin Kim if (rqc->nonsecure) 1494b7d861d9SBoojin Kim ccr |= CC_SRCNS | CC_DSTNS; 1495b7d861d9SBoojin Kim if (rqc->insnaccess) 1496b7d861d9SBoojin Kim ccr |= CC_SRCIA | CC_DSTIA; 1497b7d861d9SBoojin Kim 1498b7d861d9SBoojin Kim ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); 1499b7d861d9SBoojin Kim ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); 1500b7d861d9SBoojin Kim 1501b7d861d9SBoojin Kim ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); 1502b7d861d9SBoojin Kim ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); 1503b7d861d9SBoojin Kim 1504b7d861d9SBoojin Kim ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); 1505b7d861d9SBoojin Kim ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); 1506b7d861d9SBoojin Kim 1507b7d861d9SBoojin Kim ccr |= (rqc->swap << CC_SWAP_SHFT); 1508b7d861d9SBoojin Kim 1509b7d861d9SBoojin Kim return ccr; 1510b7d861d9SBoojin Kim } 1511b7d861d9SBoojin Kim 1512b7d861d9SBoojin Kim static inline bool _is_valid(u32 ccr) 1513b7d861d9SBoojin Kim { 1514b7d861d9SBoojin Kim enum pl330_dstcachectrl dcctl; 1515b7d861d9SBoojin Kim enum pl330_srccachectrl scctl; 1516b7d861d9SBoojin Kim 1517b7d861d9SBoojin Kim dcctl = (ccr >> CC_DSTCCTRL_SHFT) & CC_DRCCCTRL_MASK; 1518b7d861d9SBoojin Kim scctl = (ccr >> CC_SRCCCTRL_SHFT) & CC_SRCCCTRL_MASK; 1519b7d861d9SBoojin Kim 1520b7d861d9SBoojin Kim if (dcctl == DINVALID1 || dcctl == DINVALID2 1521b7d861d9SBoojin Kim || scctl == SINVALID1 || scctl == SINVALID2) 1522b7d861d9SBoojin Kim return false; 1523b7d861d9SBoojin Kim else 1524b7d861d9SBoojin Kim return true; 1525b7d861d9SBoojin Kim } 1526b7d861d9SBoojin Kim 1527b7d861d9SBoojin Kim /* 1528b7d861d9SBoojin Kim * Submit a list of xfers after which the client wants notification. 1529b7d861d9SBoojin Kim * Client is not notified after each xfer unit, just once after all 1530b7d861d9SBoojin Kim * xfer units are done or some error occurs. 1531b7d861d9SBoojin Kim */ 1532b7d861d9SBoojin Kim static int pl330_submit_req(void *ch_id, struct pl330_req *r) 1533b7d861d9SBoojin Kim { 1534b7d861d9SBoojin Kim struct pl330_thread *thrd = ch_id; 1535b7d861d9SBoojin Kim struct pl330_dmac *pl330; 1536b7d861d9SBoojin Kim struct pl330_info *pi; 1537b7d861d9SBoojin Kim struct _xfer_spec xs; 1538b7d861d9SBoojin Kim unsigned long flags; 1539b7d861d9SBoojin Kim void __iomem *regs; 1540b7d861d9SBoojin Kim unsigned idx; 1541b7d861d9SBoojin Kim u32 ccr; 1542b7d861d9SBoojin Kim int ret = 0; 1543b7d861d9SBoojin Kim 1544b7d861d9SBoojin Kim /* No Req or Unacquired Channel or DMAC */ 1545b7d861d9SBoojin Kim if (!r || !thrd || thrd->free) 1546b7d861d9SBoojin Kim return -EINVAL; 1547b7d861d9SBoojin Kim 1548b7d861d9SBoojin Kim pl330 = thrd->dmac; 1549b7d861d9SBoojin Kim pi = pl330->pinfo; 1550b7d861d9SBoojin Kim regs = pi->base; 1551b7d861d9SBoojin Kim 1552b7d861d9SBoojin Kim if (pl330->state == DYING 1553b7d861d9SBoojin Kim || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { 1554b7d861d9SBoojin Kim dev_info(thrd->dmac->pinfo->dev, "%s:%d\n", 1555b7d861d9SBoojin Kim __func__, __LINE__); 1556b7d861d9SBoojin Kim return -EAGAIN; 1557b7d861d9SBoojin Kim } 1558b7d861d9SBoojin Kim 1559b7d861d9SBoojin Kim /* If request for non-existing peripheral */ 1560b7d861d9SBoojin Kim if (r->rqtype != MEMTOMEM && r->peri >= pi->pcfg.num_peri) { 1561b7d861d9SBoojin Kim dev_info(thrd->dmac->pinfo->dev, 1562b7d861d9SBoojin Kim "%s:%d Invalid peripheral(%u)!\n", 1563b7d861d9SBoojin Kim __func__, __LINE__, r->peri); 1564b7d861d9SBoojin Kim return -EINVAL; 1565b7d861d9SBoojin Kim } 1566b7d861d9SBoojin Kim 1567b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1568b7d861d9SBoojin Kim 1569b7d861d9SBoojin Kim if (_queue_full(thrd)) { 1570b7d861d9SBoojin Kim ret = -EAGAIN; 1571b7d861d9SBoojin Kim goto xfer_exit; 1572b7d861d9SBoojin Kim } 1573b7d861d9SBoojin Kim 15742e2c682bSSachin Kamat 15752e2c682bSSachin Kamat /* Use last settings, if not provided */ 15762e2c682bSSachin Kamat if (r->cfg) { 1577b7d861d9SBoojin Kim /* Prefer Secure Channel */ 1578b7d861d9SBoojin Kim if (!_manager_ns(thrd)) 1579b7d861d9SBoojin Kim r->cfg->nonsecure = 0; 1580b7d861d9SBoojin Kim else 1581b7d861d9SBoojin Kim r->cfg->nonsecure = 1; 1582b7d861d9SBoojin Kim 1583b7d861d9SBoojin Kim ccr = _prepare_ccr(r->cfg); 15842e2c682bSSachin Kamat } else { 1585b7d861d9SBoojin Kim ccr = readl(regs + CC(thrd->id)); 15862e2c682bSSachin Kamat } 1587b7d861d9SBoojin Kim 1588b7d861d9SBoojin Kim /* If this req doesn't have valid xfer settings */ 1589b7d861d9SBoojin Kim if (!_is_valid(ccr)) { 1590b7d861d9SBoojin Kim ret = -EINVAL; 1591b7d861d9SBoojin Kim dev_info(thrd->dmac->pinfo->dev, "%s:%d Invalid CCR(%x)!\n", 1592b7d861d9SBoojin Kim __func__, __LINE__, ccr); 1593b7d861d9SBoojin Kim goto xfer_exit; 1594b7d861d9SBoojin Kim } 1595b7d861d9SBoojin Kim 1596b7d861d9SBoojin Kim idx = IS_FREE(&thrd->req[0]) ? 0 : 1; 1597b7d861d9SBoojin Kim 1598b7d861d9SBoojin Kim xs.ccr = ccr; 1599b7d861d9SBoojin Kim xs.r = r; 1600b7d861d9SBoojin Kim 1601b7d861d9SBoojin Kim /* First dry run to check if req is acceptable */ 1602b7d861d9SBoojin Kim ret = _setup_req(1, thrd, idx, &xs); 1603b7d861d9SBoojin Kim if (ret < 0) 1604b7d861d9SBoojin Kim goto xfer_exit; 1605b7d861d9SBoojin Kim 1606b7d861d9SBoojin Kim if (ret > pi->mcbufsz / 2) { 1607b7d861d9SBoojin Kim dev_info(thrd->dmac->pinfo->dev, 1608b7d861d9SBoojin Kim "%s:%d Trying increasing mcbufsz\n", 1609b7d861d9SBoojin Kim __func__, __LINE__); 1610b7d861d9SBoojin Kim ret = -ENOMEM; 1611b7d861d9SBoojin Kim goto xfer_exit; 1612b7d861d9SBoojin Kim } 1613b7d861d9SBoojin Kim 1614b7d861d9SBoojin Kim /* Hook the request */ 1615b7d861d9SBoojin Kim thrd->lstenq = idx; 1616b7d861d9SBoojin Kim thrd->req[idx].mc_len = _setup_req(0, thrd, idx, &xs); 1617b7d861d9SBoojin Kim thrd->req[idx].r = r; 1618b7d861d9SBoojin Kim 1619b7d861d9SBoojin Kim ret = 0; 1620b7d861d9SBoojin Kim 1621b7d861d9SBoojin Kim xfer_exit: 1622b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1623b7d861d9SBoojin Kim 1624b7d861d9SBoojin Kim return ret; 1625b7d861d9SBoojin Kim } 1626b7d861d9SBoojin Kim 1627b7d861d9SBoojin Kim static void pl330_dotask(unsigned long data) 1628b7d861d9SBoojin Kim { 1629b7d861d9SBoojin Kim struct pl330_dmac *pl330 = (struct pl330_dmac *) data; 1630b7d861d9SBoojin Kim struct pl330_info *pi = pl330->pinfo; 1631b7d861d9SBoojin Kim unsigned long flags; 1632b7d861d9SBoojin Kim int i; 1633b7d861d9SBoojin Kim 1634b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1635b7d861d9SBoojin Kim 1636b7d861d9SBoojin Kim /* The DMAC itself gone nuts */ 1637b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_dmac) { 1638b7d861d9SBoojin Kim pl330->state = DYING; 1639b7d861d9SBoojin Kim /* Reset the manager too */ 1640b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = true; 1641b7d861d9SBoojin Kim /* Clear the reset flag */ 1642b7d861d9SBoojin Kim pl330->dmac_tbd.reset_dmac = false; 1643b7d861d9SBoojin Kim } 1644b7d861d9SBoojin Kim 1645b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_mngr) { 1646b7d861d9SBoojin Kim _stop(pl330->manager); 1647b7d861d9SBoojin Kim /* Reset all channels */ 1648b7d861d9SBoojin Kim pl330->dmac_tbd.reset_chan = (1 << pi->pcfg.num_chan) - 1; 1649b7d861d9SBoojin Kim /* Clear the reset flag */ 1650b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = false; 1651b7d861d9SBoojin Kim } 1652b7d861d9SBoojin Kim 1653b7d861d9SBoojin Kim for (i = 0; i < pi->pcfg.num_chan; i++) { 1654b7d861d9SBoojin Kim 1655b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_chan & (1 << i)) { 1656b7d861d9SBoojin Kim struct pl330_thread *thrd = &pl330->channels[i]; 1657b7d861d9SBoojin Kim void __iomem *regs = pi->base; 1658b7d861d9SBoojin Kim enum pl330_op_err err; 1659b7d861d9SBoojin Kim 1660b7d861d9SBoojin Kim _stop(thrd); 1661b7d861d9SBoojin Kim 1662b7d861d9SBoojin Kim if (readl(regs + FSC) & (1 << thrd->id)) 1663b7d861d9SBoojin Kim err = PL330_ERR_FAIL; 1664b7d861d9SBoojin Kim else 1665b7d861d9SBoojin Kim err = PL330_ERR_ABORT; 1666b7d861d9SBoojin Kim 1667b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1668b7d861d9SBoojin Kim 1669b7d861d9SBoojin Kim _callback(thrd->req[1 - thrd->lstenq].r, err); 1670b7d861d9SBoojin Kim _callback(thrd->req[thrd->lstenq].r, err); 1671b7d861d9SBoojin Kim 1672b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1673b7d861d9SBoojin Kim 1674b7d861d9SBoojin Kim thrd->req[0].r = NULL; 1675b7d861d9SBoojin Kim thrd->req[1].r = NULL; 1676b7d861d9SBoojin Kim mark_free(thrd, 0); 1677b7d861d9SBoojin Kim mark_free(thrd, 1); 1678b7d861d9SBoojin Kim 1679b7d861d9SBoojin Kim /* Clear the reset flag */ 1680b7d861d9SBoojin Kim pl330->dmac_tbd.reset_chan &= ~(1 << i); 1681b7d861d9SBoojin Kim } 1682b7d861d9SBoojin Kim } 1683b7d861d9SBoojin Kim 1684b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1685b7d861d9SBoojin Kim 1686b7d861d9SBoojin Kim return; 1687b7d861d9SBoojin Kim } 1688b7d861d9SBoojin Kim 1689b7d861d9SBoojin Kim /* Returns 1 if state was updated, 0 otherwise */ 1690b7d861d9SBoojin Kim static int pl330_update(const struct pl330_info *pi) 1691b7d861d9SBoojin Kim { 1692fdec53d5SJavi Merino struct pl330_req *rqdone, *tmp; 1693b7d861d9SBoojin Kim struct pl330_dmac *pl330; 1694b7d861d9SBoojin Kim unsigned long flags; 1695b7d861d9SBoojin Kim void __iomem *regs; 1696b7d861d9SBoojin Kim u32 val; 1697b7d861d9SBoojin Kim int id, ev, ret = 0; 1698b7d861d9SBoojin Kim 1699b7d861d9SBoojin Kim if (!pi || !pi->pl330_data) 1700b7d861d9SBoojin Kim return 0; 1701b7d861d9SBoojin Kim 1702b7d861d9SBoojin Kim regs = pi->base; 1703b7d861d9SBoojin Kim pl330 = pi->pl330_data; 1704b7d861d9SBoojin Kim 1705b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1706b7d861d9SBoojin Kim 1707b7d861d9SBoojin Kim val = readl(regs + FSM) & 0x1; 1708b7d861d9SBoojin Kim if (val) 1709b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = true; 1710b7d861d9SBoojin Kim else 1711b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = false; 1712b7d861d9SBoojin Kim 1713b7d861d9SBoojin Kim val = readl(regs + FSC) & ((1 << pi->pcfg.num_chan) - 1); 1714b7d861d9SBoojin Kim pl330->dmac_tbd.reset_chan |= val; 1715b7d861d9SBoojin Kim if (val) { 1716b7d861d9SBoojin Kim int i = 0; 1717b7d861d9SBoojin Kim while (i < pi->pcfg.num_chan) { 1718b7d861d9SBoojin Kim if (val & (1 << i)) { 1719b7d861d9SBoojin Kim dev_info(pi->dev, 1720b7d861d9SBoojin Kim "Reset Channel-%d\t CS-%x FTC-%x\n", 1721b7d861d9SBoojin Kim i, readl(regs + CS(i)), 1722b7d861d9SBoojin Kim readl(regs + FTC(i))); 1723b7d861d9SBoojin Kim _stop(&pl330->channels[i]); 1724b7d861d9SBoojin Kim } 1725b7d861d9SBoojin Kim i++; 1726b7d861d9SBoojin Kim } 1727b7d861d9SBoojin Kim } 1728b7d861d9SBoojin Kim 1729b7d861d9SBoojin Kim /* Check which event happened i.e, thread notified */ 1730b7d861d9SBoojin Kim val = readl(regs + ES); 1731b7d861d9SBoojin Kim if (pi->pcfg.num_events < 32 1732b7d861d9SBoojin Kim && val & ~((1 << pi->pcfg.num_events) - 1)) { 1733b7d861d9SBoojin Kim pl330->dmac_tbd.reset_dmac = true; 1734b7d861d9SBoojin Kim dev_err(pi->dev, "%s:%d Unexpected!\n", __func__, __LINE__); 1735b7d861d9SBoojin Kim ret = 1; 1736b7d861d9SBoojin Kim goto updt_exit; 1737b7d861d9SBoojin Kim } 1738b7d861d9SBoojin Kim 1739b7d861d9SBoojin Kim for (ev = 0; ev < pi->pcfg.num_events; ev++) { 1740b7d861d9SBoojin Kim if (val & (1 << ev)) { /* Event occurred */ 1741b7d861d9SBoojin Kim struct pl330_thread *thrd; 1742b7d861d9SBoojin Kim u32 inten = readl(regs + INTEN); 1743b7d861d9SBoojin Kim int active; 1744b7d861d9SBoojin Kim 1745b7d861d9SBoojin Kim /* Clear the event */ 1746b7d861d9SBoojin Kim if (inten & (1 << ev)) 1747b7d861d9SBoojin Kim writel(1 << ev, regs + INTCLR); 1748b7d861d9SBoojin Kim 1749b7d861d9SBoojin Kim ret = 1; 1750b7d861d9SBoojin Kim 1751b7d861d9SBoojin Kim id = pl330->events[ev]; 1752b7d861d9SBoojin Kim 1753b7d861d9SBoojin Kim thrd = &pl330->channels[id]; 1754b7d861d9SBoojin Kim 1755b7d861d9SBoojin Kim active = thrd->req_running; 1756b7d861d9SBoojin Kim if (active == -1) /* Aborted */ 1757b7d861d9SBoojin Kim continue; 1758b7d861d9SBoojin Kim 1759fdec53d5SJavi Merino /* Detach the req */ 1760fdec53d5SJavi Merino rqdone = thrd->req[active].r; 1761fdec53d5SJavi Merino thrd->req[active].r = NULL; 1762fdec53d5SJavi Merino 1763b7d861d9SBoojin Kim mark_free(thrd, active); 1764b7d861d9SBoojin Kim 1765b7d861d9SBoojin Kim /* Get going again ASAP */ 1766b7d861d9SBoojin Kim _start(thrd); 1767b7d861d9SBoojin Kim 1768b7d861d9SBoojin Kim /* For now, just make a list of callbacks to be done */ 1769b7d861d9SBoojin Kim list_add_tail(&rqdone->rqd, &pl330->req_done); 1770b7d861d9SBoojin Kim } 1771b7d861d9SBoojin Kim } 1772b7d861d9SBoojin Kim 1773b7d861d9SBoojin Kim /* Now that we are in no hurry, do the callbacks */ 1774fdec53d5SJavi Merino list_for_each_entry_safe(rqdone, tmp, &pl330->req_done, rqd) { 1775fdec53d5SJavi Merino list_del(&rqdone->rqd); 1776b7d861d9SBoojin Kim 1777b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1778fdec53d5SJavi Merino _callback(rqdone, PL330_ERR_NONE); 1779b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1780b7d861d9SBoojin Kim } 1781b7d861d9SBoojin Kim 1782b7d861d9SBoojin Kim updt_exit: 1783b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1784b7d861d9SBoojin Kim 1785b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_dmac 1786b7d861d9SBoojin Kim || pl330->dmac_tbd.reset_mngr 1787b7d861d9SBoojin Kim || pl330->dmac_tbd.reset_chan) { 1788b7d861d9SBoojin Kim ret = 1; 1789b7d861d9SBoojin Kim tasklet_schedule(&pl330->tasks); 1790b7d861d9SBoojin Kim } 1791b7d861d9SBoojin Kim 1792b7d861d9SBoojin Kim return ret; 1793b7d861d9SBoojin Kim } 1794b7d861d9SBoojin Kim 1795b7d861d9SBoojin Kim static int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op) 1796b7d861d9SBoojin Kim { 1797b7d861d9SBoojin Kim struct pl330_thread *thrd = ch_id; 1798b7d861d9SBoojin Kim struct pl330_dmac *pl330; 1799b7d861d9SBoojin Kim unsigned long flags; 1800ef08e782SLinus Torvalds int ret = 0, active; 1801b7d861d9SBoojin Kim 1802b7d861d9SBoojin Kim if (!thrd || thrd->free || thrd->dmac->state == DYING) 1803b7d861d9SBoojin Kim return -EINVAL; 1804b7d861d9SBoojin Kim 1805b7d861d9SBoojin Kim pl330 = thrd->dmac; 1806ef08e782SLinus Torvalds active = thrd->req_running; 1807b7d861d9SBoojin Kim 1808b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1809b7d861d9SBoojin Kim 1810b7d861d9SBoojin Kim switch (op) { 1811b7d861d9SBoojin Kim case PL330_OP_FLUSH: 1812b7d861d9SBoojin Kim /* Make sure the channel is stopped */ 1813b7d861d9SBoojin Kim _stop(thrd); 1814b7d861d9SBoojin Kim 1815b7d861d9SBoojin Kim thrd->req[0].r = NULL; 1816b7d861d9SBoojin Kim thrd->req[1].r = NULL; 1817b7d861d9SBoojin Kim mark_free(thrd, 0); 1818b7d861d9SBoojin Kim mark_free(thrd, 1); 1819b7d861d9SBoojin Kim break; 1820b7d861d9SBoojin Kim 1821b7d861d9SBoojin Kim case PL330_OP_ABORT: 1822b7d861d9SBoojin Kim /* Make sure the channel is stopped */ 1823b7d861d9SBoojin Kim _stop(thrd); 1824b7d861d9SBoojin Kim 1825b7d861d9SBoojin Kim /* ABORT is only for the active req */ 1826b7d861d9SBoojin Kim if (active == -1) 1827b7d861d9SBoojin Kim break; 1828b7d861d9SBoojin Kim 1829b7d861d9SBoojin Kim thrd->req[active].r = NULL; 1830b7d861d9SBoojin Kim mark_free(thrd, active); 1831b7d861d9SBoojin Kim 1832b7d861d9SBoojin Kim /* Start the next */ 1833b7d861d9SBoojin Kim case PL330_OP_START: 1834b7d861d9SBoojin Kim if ((active == -1) && !_start(thrd)) 1835b7d861d9SBoojin Kim ret = -EIO; 1836b7d861d9SBoojin Kim break; 1837b7d861d9SBoojin Kim 1838b7d861d9SBoojin Kim default: 1839b7d861d9SBoojin Kim ret = -EINVAL; 1840b7d861d9SBoojin Kim } 1841b7d861d9SBoojin Kim 1842b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1843b7d861d9SBoojin Kim return ret; 1844b7d861d9SBoojin Kim } 1845b7d861d9SBoojin Kim 1846b7d861d9SBoojin Kim /* Reserve an event */ 1847b7d861d9SBoojin Kim static inline int _alloc_event(struct pl330_thread *thrd) 1848b7d861d9SBoojin Kim { 1849b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 1850b7d861d9SBoojin Kim struct pl330_info *pi = pl330->pinfo; 1851b7d861d9SBoojin Kim int ev; 1852b7d861d9SBoojin Kim 1853b7d861d9SBoojin Kim for (ev = 0; ev < pi->pcfg.num_events; ev++) 1854b7d861d9SBoojin Kim if (pl330->events[ev] == -1) { 1855b7d861d9SBoojin Kim pl330->events[ev] = thrd->id; 1856b7d861d9SBoojin Kim return ev; 1857b7d861d9SBoojin Kim } 1858b7d861d9SBoojin Kim 1859b7d861d9SBoojin Kim return -1; 1860b7d861d9SBoojin Kim } 1861b7d861d9SBoojin Kim 1862b7d861d9SBoojin Kim static bool _chan_ns(const struct pl330_info *pi, int i) 1863b7d861d9SBoojin Kim { 1864b7d861d9SBoojin Kim return pi->pcfg.irq_ns & (1 << i); 1865b7d861d9SBoojin Kim } 1866b7d861d9SBoojin Kim 1867b7d861d9SBoojin Kim /* Upon success, returns IdentityToken for the 1868b7d861d9SBoojin Kim * allocated channel, NULL otherwise. 1869b7d861d9SBoojin Kim */ 1870b7d861d9SBoojin Kim static void *pl330_request_channel(const struct pl330_info *pi) 1871b7d861d9SBoojin Kim { 1872b7d861d9SBoojin Kim struct pl330_thread *thrd = NULL; 1873b7d861d9SBoojin Kim struct pl330_dmac *pl330; 1874b7d861d9SBoojin Kim unsigned long flags; 1875b7d861d9SBoojin Kim int chans, i; 1876b7d861d9SBoojin Kim 1877b7d861d9SBoojin Kim if (!pi || !pi->pl330_data) 1878b7d861d9SBoojin Kim return NULL; 1879b7d861d9SBoojin Kim 1880b7d861d9SBoojin Kim pl330 = pi->pl330_data; 1881b7d861d9SBoojin Kim 1882b7d861d9SBoojin Kim if (pl330->state == DYING) 1883b7d861d9SBoojin Kim return NULL; 1884b7d861d9SBoojin Kim 1885b7d861d9SBoojin Kim chans = pi->pcfg.num_chan; 1886b7d861d9SBoojin Kim 1887b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1888b7d861d9SBoojin Kim 1889b7d861d9SBoojin Kim for (i = 0; i < chans; i++) { 1890b7d861d9SBoojin Kim thrd = &pl330->channels[i]; 1891b7d861d9SBoojin Kim if ((thrd->free) && (!_manager_ns(thrd) || 1892b7d861d9SBoojin Kim _chan_ns(pi, i))) { 1893b7d861d9SBoojin Kim thrd->ev = _alloc_event(thrd); 1894b7d861d9SBoojin Kim if (thrd->ev >= 0) { 1895b7d861d9SBoojin Kim thrd->free = false; 1896b7d861d9SBoojin Kim thrd->lstenq = 1; 1897b7d861d9SBoojin Kim thrd->req[0].r = NULL; 1898b7d861d9SBoojin Kim mark_free(thrd, 0); 1899b7d861d9SBoojin Kim thrd->req[1].r = NULL; 1900b7d861d9SBoojin Kim mark_free(thrd, 1); 1901b7d861d9SBoojin Kim break; 1902b7d861d9SBoojin Kim } 1903b7d861d9SBoojin Kim } 1904b7d861d9SBoojin Kim thrd = NULL; 1905b7d861d9SBoojin Kim } 1906b7d861d9SBoojin Kim 1907b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1908b7d861d9SBoojin Kim 1909b7d861d9SBoojin Kim return thrd; 1910b7d861d9SBoojin Kim } 1911b7d861d9SBoojin Kim 1912b7d861d9SBoojin Kim /* Release an event */ 1913b7d861d9SBoojin Kim static inline void _free_event(struct pl330_thread *thrd, int ev) 1914b7d861d9SBoojin Kim { 1915b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 1916b7d861d9SBoojin Kim struct pl330_info *pi = pl330->pinfo; 1917b7d861d9SBoojin Kim 1918b7d861d9SBoojin Kim /* If the event is valid and was held by the thread */ 1919b7d861d9SBoojin Kim if (ev >= 0 && ev < pi->pcfg.num_events 1920b7d861d9SBoojin Kim && pl330->events[ev] == thrd->id) 1921b7d861d9SBoojin Kim pl330->events[ev] = -1; 1922b7d861d9SBoojin Kim } 1923b7d861d9SBoojin Kim 1924b7d861d9SBoojin Kim static void pl330_release_channel(void *ch_id) 1925b7d861d9SBoojin Kim { 1926b7d861d9SBoojin Kim struct pl330_thread *thrd = ch_id; 1927b7d861d9SBoojin Kim struct pl330_dmac *pl330; 1928b7d861d9SBoojin Kim unsigned long flags; 1929b7d861d9SBoojin Kim 1930b7d861d9SBoojin Kim if (!thrd || thrd->free) 1931b7d861d9SBoojin Kim return; 1932b7d861d9SBoojin Kim 1933b7d861d9SBoojin Kim _stop(thrd); 1934b7d861d9SBoojin Kim 1935b7d861d9SBoojin Kim _callback(thrd->req[1 - thrd->lstenq].r, PL330_ERR_ABORT); 1936b7d861d9SBoojin Kim _callback(thrd->req[thrd->lstenq].r, PL330_ERR_ABORT); 1937b7d861d9SBoojin Kim 1938b7d861d9SBoojin Kim pl330 = thrd->dmac; 1939b7d861d9SBoojin Kim 1940b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1941b7d861d9SBoojin Kim _free_event(thrd, thrd->ev); 1942b7d861d9SBoojin Kim thrd->free = true; 1943b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1944b7d861d9SBoojin Kim } 1945b7d861d9SBoojin Kim 1946b7d861d9SBoojin Kim /* Initialize the structure for PL330 configuration, that can be used 1947b7d861d9SBoojin Kim * by the client driver the make best use of the DMAC 1948b7d861d9SBoojin Kim */ 1949b7d861d9SBoojin Kim static void read_dmac_config(struct pl330_info *pi) 1950b7d861d9SBoojin Kim { 1951b7d861d9SBoojin Kim void __iomem *regs = pi->base; 1952b7d861d9SBoojin Kim u32 val; 1953b7d861d9SBoojin Kim 1954b7d861d9SBoojin Kim val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; 1955b7d861d9SBoojin Kim val &= CRD_DATA_WIDTH_MASK; 1956b7d861d9SBoojin Kim pi->pcfg.data_bus_width = 8 * (1 << val); 1957b7d861d9SBoojin Kim 1958b7d861d9SBoojin Kim val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; 1959b7d861d9SBoojin Kim val &= CRD_DATA_BUFF_MASK; 1960b7d861d9SBoojin Kim pi->pcfg.data_buf_dep = val + 1; 1961b7d861d9SBoojin Kim 1962b7d861d9SBoojin Kim val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; 1963b7d861d9SBoojin Kim val &= CR0_NUM_CHANS_MASK; 1964b7d861d9SBoojin Kim val += 1; 1965b7d861d9SBoojin Kim pi->pcfg.num_chan = val; 1966b7d861d9SBoojin Kim 1967b7d861d9SBoojin Kim val = readl(regs + CR0); 1968b7d861d9SBoojin Kim if (val & CR0_PERIPH_REQ_SET) { 1969b7d861d9SBoojin Kim val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; 1970b7d861d9SBoojin Kim val += 1; 1971b7d861d9SBoojin Kim pi->pcfg.num_peri = val; 1972b7d861d9SBoojin Kim pi->pcfg.peri_ns = readl(regs + CR4); 1973b7d861d9SBoojin Kim } else { 1974b7d861d9SBoojin Kim pi->pcfg.num_peri = 0; 1975b7d861d9SBoojin Kim } 1976b7d861d9SBoojin Kim 1977b7d861d9SBoojin Kim val = readl(regs + CR0); 1978b7d861d9SBoojin Kim if (val & CR0_BOOT_MAN_NS) 1979b7d861d9SBoojin Kim pi->pcfg.mode |= DMAC_MODE_NS; 1980b7d861d9SBoojin Kim else 1981b7d861d9SBoojin Kim pi->pcfg.mode &= ~DMAC_MODE_NS; 1982b7d861d9SBoojin Kim 1983b7d861d9SBoojin Kim val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; 1984b7d861d9SBoojin Kim val &= CR0_NUM_EVENTS_MASK; 1985b7d861d9SBoojin Kim val += 1; 1986b7d861d9SBoojin Kim pi->pcfg.num_events = val; 1987b7d861d9SBoojin Kim 1988b7d861d9SBoojin Kim pi->pcfg.irq_ns = readl(regs + CR3); 1989b7d861d9SBoojin Kim 1990b7d861d9SBoojin Kim pi->pcfg.periph_id = get_id(pi, PERIPH_ID); 1991b7d861d9SBoojin Kim pi->pcfg.pcell_id = get_id(pi, PCELL_ID); 1992b7d861d9SBoojin Kim } 1993b7d861d9SBoojin Kim 1994b7d861d9SBoojin Kim static inline void _reset_thread(struct pl330_thread *thrd) 1995b7d861d9SBoojin Kim { 1996b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 1997b7d861d9SBoojin Kim struct pl330_info *pi = pl330->pinfo; 1998b7d861d9SBoojin Kim 1999b7d861d9SBoojin Kim thrd->req[0].mc_cpu = pl330->mcode_cpu 2000b7d861d9SBoojin Kim + (thrd->id * pi->mcbufsz); 2001b7d861d9SBoojin Kim thrd->req[0].mc_bus = pl330->mcode_bus 2002b7d861d9SBoojin Kim + (thrd->id * pi->mcbufsz); 2003b7d861d9SBoojin Kim thrd->req[0].r = NULL; 2004b7d861d9SBoojin Kim mark_free(thrd, 0); 2005b7d861d9SBoojin Kim 2006b7d861d9SBoojin Kim thrd->req[1].mc_cpu = thrd->req[0].mc_cpu 2007b7d861d9SBoojin Kim + pi->mcbufsz / 2; 2008b7d861d9SBoojin Kim thrd->req[1].mc_bus = thrd->req[0].mc_bus 2009b7d861d9SBoojin Kim + pi->mcbufsz / 2; 2010b7d861d9SBoojin Kim thrd->req[1].r = NULL; 2011b7d861d9SBoojin Kim mark_free(thrd, 1); 2012b7d861d9SBoojin Kim } 2013b7d861d9SBoojin Kim 2014b7d861d9SBoojin Kim static int dmac_alloc_threads(struct pl330_dmac *pl330) 2015b7d861d9SBoojin Kim { 2016b7d861d9SBoojin Kim struct pl330_info *pi = pl330->pinfo; 2017b7d861d9SBoojin Kim int chans = pi->pcfg.num_chan; 2018b7d861d9SBoojin Kim struct pl330_thread *thrd; 2019b7d861d9SBoojin Kim int i; 2020b7d861d9SBoojin Kim 2021b7d861d9SBoojin Kim /* Allocate 1 Manager and 'chans' Channel threads */ 2022b7d861d9SBoojin Kim pl330->channels = kzalloc((1 + chans) * sizeof(*thrd), 2023b7d861d9SBoojin Kim GFP_KERNEL); 2024b7d861d9SBoojin Kim if (!pl330->channels) 2025b7d861d9SBoojin Kim return -ENOMEM; 2026b7d861d9SBoojin Kim 2027b7d861d9SBoojin Kim /* Init Channel threads */ 2028b7d861d9SBoojin Kim for (i = 0; i < chans; i++) { 2029b7d861d9SBoojin Kim thrd = &pl330->channels[i]; 2030b7d861d9SBoojin Kim thrd->id = i; 2031b7d861d9SBoojin Kim thrd->dmac = pl330; 2032b7d861d9SBoojin Kim _reset_thread(thrd); 2033b7d861d9SBoojin Kim thrd->free = true; 2034b7d861d9SBoojin Kim } 2035b7d861d9SBoojin Kim 2036b7d861d9SBoojin Kim /* MANAGER is indexed at the end */ 2037b7d861d9SBoojin Kim thrd = &pl330->channels[chans]; 2038b7d861d9SBoojin Kim thrd->id = chans; 2039b7d861d9SBoojin Kim thrd->dmac = pl330; 2040b7d861d9SBoojin Kim thrd->free = false; 2041b7d861d9SBoojin Kim pl330->manager = thrd; 2042b7d861d9SBoojin Kim 2043b7d861d9SBoojin Kim return 0; 2044b7d861d9SBoojin Kim } 2045b7d861d9SBoojin Kim 2046b7d861d9SBoojin Kim static int dmac_alloc_resources(struct pl330_dmac *pl330) 2047b7d861d9SBoojin Kim { 2048b7d861d9SBoojin Kim struct pl330_info *pi = pl330->pinfo; 2049b7d861d9SBoojin Kim int chans = pi->pcfg.num_chan; 2050b7d861d9SBoojin Kim int ret; 2051b7d861d9SBoojin Kim 2052b7d861d9SBoojin Kim /* 2053b7d861d9SBoojin Kim * Alloc MicroCode buffer for 'chans' Channel threads. 2054b7d861d9SBoojin Kim * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN) 2055b7d861d9SBoojin Kim */ 2056b7d861d9SBoojin Kim pl330->mcode_cpu = dma_alloc_coherent(pi->dev, 2057b7d861d9SBoojin Kim chans * pi->mcbufsz, 2058b7d861d9SBoojin Kim &pl330->mcode_bus, GFP_KERNEL); 2059b7d861d9SBoojin Kim if (!pl330->mcode_cpu) { 2060b7d861d9SBoojin Kim dev_err(pi->dev, "%s:%d Can't allocate memory!\n", 2061b7d861d9SBoojin Kim __func__, __LINE__); 2062b7d861d9SBoojin Kim return -ENOMEM; 2063b7d861d9SBoojin Kim } 2064b7d861d9SBoojin Kim 2065b7d861d9SBoojin Kim ret = dmac_alloc_threads(pl330); 2066b7d861d9SBoojin Kim if (ret) { 2067b7d861d9SBoojin Kim dev_err(pi->dev, "%s:%d Can't to create channels for DMAC!\n", 2068b7d861d9SBoojin Kim __func__, __LINE__); 2069b7d861d9SBoojin Kim dma_free_coherent(pi->dev, 2070b7d861d9SBoojin Kim chans * pi->mcbufsz, 2071b7d861d9SBoojin Kim pl330->mcode_cpu, pl330->mcode_bus); 2072b7d861d9SBoojin Kim return ret; 2073b7d861d9SBoojin Kim } 2074b7d861d9SBoojin Kim 2075b7d861d9SBoojin Kim return 0; 2076b7d861d9SBoojin Kim } 2077b7d861d9SBoojin Kim 2078b7d861d9SBoojin Kim static int pl330_add(struct pl330_info *pi) 2079b7d861d9SBoojin Kim { 2080b7d861d9SBoojin Kim struct pl330_dmac *pl330; 2081b7d861d9SBoojin Kim void __iomem *regs; 2082b7d861d9SBoojin Kim int i, ret; 2083b7d861d9SBoojin Kim 2084b7d861d9SBoojin Kim if (!pi || !pi->dev) 2085b7d861d9SBoojin Kim return -EINVAL; 2086b7d861d9SBoojin Kim 2087b7d861d9SBoojin Kim /* If already added */ 2088b7d861d9SBoojin Kim if (pi->pl330_data) 2089b7d861d9SBoojin Kim return -EINVAL; 2090b7d861d9SBoojin Kim 2091b7d861d9SBoojin Kim /* 2092b7d861d9SBoojin Kim * If the SoC can perform reset on the DMAC, then do it 2093b7d861d9SBoojin Kim * before reading its configuration. 2094b7d861d9SBoojin Kim */ 2095b7d861d9SBoojin Kim if (pi->dmac_reset) 2096b7d861d9SBoojin Kim pi->dmac_reset(pi); 2097b7d861d9SBoojin Kim 2098b7d861d9SBoojin Kim regs = pi->base; 2099b7d861d9SBoojin Kim 2100b7d861d9SBoojin Kim /* Check if we can handle this DMAC */ 2101b7d861d9SBoojin Kim if ((get_id(pi, PERIPH_ID) & 0xfffff) != PERIPH_ID_VAL 2102b7d861d9SBoojin Kim || get_id(pi, PCELL_ID) != PCELL_ID_VAL) { 2103b7d861d9SBoojin Kim dev_err(pi->dev, "PERIPH_ID 0x%x, PCELL_ID 0x%x !\n", 2104b7d861d9SBoojin Kim get_id(pi, PERIPH_ID), get_id(pi, PCELL_ID)); 2105b7d861d9SBoojin Kim return -EINVAL; 2106b7d861d9SBoojin Kim } 2107b7d861d9SBoojin Kim 2108b7d861d9SBoojin Kim /* Read the configuration of the DMAC */ 2109b7d861d9SBoojin Kim read_dmac_config(pi); 2110b7d861d9SBoojin Kim 2111b7d861d9SBoojin Kim if (pi->pcfg.num_events == 0) { 2112b7d861d9SBoojin Kim dev_err(pi->dev, "%s:%d Can't work without events!\n", 2113b7d861d9SBoojin Kim __func__, __LINE__); 2114b7d861d9SBoojin Kim return -EINVAL; 2115b7d861d9SBoojin Kim } 2116b7d861d9SBoojin Kim 2117b7d861d9SBoojin Kim pl330 = kzalloc(sizeof(*pl330), GFP_KERNEL); 2118b7d861d9SBoojin Kim if (!pl330) { 2119b7d861d9SBoojin Kim dev_err(pi->dev, "%s:%d Can't allocate memory!\n", 2120b7d861d9SBoojin Kim __func__, __LINE__); 2121b7d861d9SBoojin Kim return -ENOMEM; 2122b7d861d9SBoojin Kim } 2123b7d861d9SBoojin Kim 2124b7d861d9SBoojin Kim /* Assign the info structure and private data */ 2125b7d861d9SBoojin Kim pl330->pinfo = pi; 2126b7d861d9SBoojin Kim pi->pl330_data = pl330; 2127b7d861d9SBoojin Kim 2128b7d861d9SBoojin Kim spin_lock_init(&pl330->lock); 2129b7d861d9SBoojin Kim 2130b7d861d9SBoojin Kim INIT_LIST_HEAD(&pl330->req_done); 2131b7d861d9SBoojin Kim 2132b7d861d9SBoojin Kim /* Use default MC buffer size if not provided */ 2133b7d861d9SBoojin Kim if (!pi->mcbufsz) 2134b7d861d9SBoojin Kim pi->mcbufsz = MCODE_BUFF_PER_REQ * 2; 2135b7d861d9SBoojin Kim 2136b7d861d9SBoojin Kim /* Mark all events as free */ 2137b7d861d9SBoojin Kim for (i = 0; i < pi->pcfg.num_events; i++) 2138b7d861d9SBoojin Kim pl330->events[i] = -1; 2139b7d861d9SBoojin Kim 2140b7d861d9SBoojin Kim /* Allocate resources needed by the DMAC */ 2141b7d861d9SBoojin Kim ret = dmac_alloc_resources(pl330); 2142b7d861d9SBoojin Kim if (ret) { 2143b7d861d9SBoojin Kim dev_err(pi->dev, "Unable to create channels for DMAC\n"); 2144b7d861d9SBoojin Kim kfree(pl330); 2145b7d861d9SBoojin Kim return ret; 2146b7d861d9SBoojin Kim } 2147b7d861d9SBoojin Kim 2148b7d861d9SBoojin Kim tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330); 2149b7d861d9SBoojin Kim 2150b7d861d9SBoojin Kim pl330->state = INIT; 2151b7d861d9SBoojin Kim 2152b7d861d9SBoojin Kim return 0; 2153b7d861d9SBoojin Kim } 2154b7d861d9SBoojin Kim 2155b7d861d9SBoojin Kim static int dmac_free_threads(struct pl330_dmac *pl330) 2156b7d861d9SBoojin Kim { 2157b7d861d9SBoojin Kim struct pl330_info *pi = pl330->pinfo; 2158b7d861d9SBoojin Kim int chans = pi->pcfg.num_chan; 2159b7d861d9SBoojin Kim struct pl330_thread *thrd; 2160b7d861d9SBoojin Kim int i; 2161b7d861d9SBoojin Kim 2162b7d861d9SBoojin Kim /* Release Channel threads */ 2163b7d861d9SBoojin Kim for (i = 0; i < chans; i++) { 2164b7d861d9SBoojin Kim thrd = &pl330->channels[i]; 2165b7d861d9SBoojin Kim pl330_release_channel((void *)thrd); 2166b7d861d9SBoojin Kim } 2167b7d861d9SBoojin Kim 2168b7d861d9SBoojin Kim /* Free memory */ 2169b7d861d9SBoojin Kim kfree(pl330->channels); 2170b7d861d9SBoojin Kim 2171b7d861d9SBoojin Kim return 0; 2172b7d861d9SBoojin Kim } 2173b7d861d9SBoojin Kim 2174b7d861d9SBoojin Kim static void dmac_free_resources(struct pl330_dmac *pl330) 2175b7d861d9SBoojin Kim { 2176b7d861d9SBoojin Kim struct pl330_info *pi = pl330->pinfo; 2177b7d861d9SBoojin Kim int chans = pi->pcfg.num_chan; 2178b7d861d9SBoojin Kim 2179b7d861d9SBoojin Kim dmac_free_threads(pl330); 2180b7d861d9SBoojin Kim 2181b7d861d9SBoojin Kim dma_free_coherent(pi->dev, chans * pi->mcbufsz, 2182b7d861d9SBoojin Kim pl330->mcode_cpu, pl330->mcode_bus); 2183b7d861d9SBoojin Kim } 2184b7d861d9SBoojin Kim 2185b7d861d9SBoojin Kim static void pl330_del(struct pl330_info *pi) 2186b7d861d9SBoojin Kim { 2187b7d861d9SBoojin Kim struct pl330_dmac *pl330; 2188b7d861d9SBoojin Kim 2189b7d861d9SBoojin Kim if (!pi || !pi->pl330_data) 2190b7d861d9SBoojin Kim return; 2191b7d861d9SBoojin Kim 2192b7d861d9SBoojin Kim pl330 = pi->pl330_data; 2193b7d861d9SBoojin Kim 2194b7d861d9SBoojin Kim pl330->state = UNINIT; 2195b7d861d9SBoojin Kim 2196b7d861d9SBoojin Kim tasklet_kill(&pl330->tasks); 2197b7d861d9SBoojin Kim 2198b7d861d9SBoojin Kim /* Free DMAC resources */ 2199b7d861d9SBoojin Kim dmac_free_resources(pl330); 2200b7d861d9SBoojin Kim 2201b7d861d9SBoojin Kim kfree(pl330); 2202b7d861d9SBoojin Kim pi->pl330_data = NULL; 2203b7d861d9SBoojin Kim } 2204b7d861d9SBoojin Kim 22053e2ec13aSThomas Abraham /* forward declaration */ 22063e2ec13aSThomas Abraham static struct amba_driver pl330_driver; 22073e2ec13aSThomas Abraham 2208b3040e40SJassi Brar static inline struct dma_pl330_chan * 2209b3040e40SJassi Brar to_pchan(struct dma_chan *ch) 2210b3040e40SJassi Brar { 2211b3040e40SJassi Brar if (!ch) 2212b3040e40SJassi Brar return NULL; 2213b3040e40SJassi Brar 2214b3040e40SJassi Brar return container_of(ch, struct dma_pl330_chan, chan); 2215b3040e40SJassi Brar } 2216b3040e40SJassi Brar 2217b3040e40SJassi Brar static inline struct dma_pl330_desc * 2218b3040e40SJassi Brar to_desc(struct dma_async_tx_descriptor *tx) 2219b3040e40SJassi Brar { 2220b3040e40SJassi Brar return container_of(tx, struct dma_pl330_desc, txd); 2221b3040e40SJassi Brar } 2222b3040e40SJassi Brar 2223b3040e40SJassi Brar static inline void free_desc_list(struct list_head *list) 2224b3040e40SJassi Brar { 2225b3040e40SJassi Brar struct dma_pl330_dmac *pdmac; 2226b3040e40SJassi Brar struct dma_pl330_desc *desc; 2227c8473828SOlof Johansson struct dma_pl330_chan *pch = NULL; 2228b3040e40SJassi Brar unsigned long flags; 2229b3040e40SJassi Brar 2230b3040e40SJassi Brar /* Finish off the work list */ 2231b3040e40SJassi Brar list_for_each_entry(desc, list, node) { 2232b3040e40SJassi Brar dma_async_tx_callback callback; 2233b3040e40SJassi Brar void *param; 2234b3040e40SJassi Brar 2235b3040e40SJassi Brar /* All desc in a list belong to same channel */ 2236b3040e40SJassi Brar pch = desc->pchan; 2237b3040e40SJassi Brar callback = desc->txd.callback; 2238b3040e40SJassi Brar param = desc->txd.callback_param; 2239b3040e40SJassi Brar 2240b3040e40SJassi Brar if (callback) 2241b3040e40SJassi Brar callback(param); 2242b3040e40SJassi Brar 2243b3040e40SJassi Brar desc->pchan = NULL; 2244b3040e40SJassi Brar } 2245b3040e40SJassi Brar 2246c8473828SOlof Johansson /* pch will be unset if list was empty */ 2247c8473828SOlof Johansson if (!pch) 2248c8473828SOlof Johansson return; 2249c8473828SOlof Johansson 2250b3040e40SJassi Brar pdmac = pch->dmac; 2251b3040e40SJassi Brar 2252b3040e40SJassi Brar spin_lock_irqsave(&pdmac->pool_lock, flags); 2253b3040e40SJassi Brar list_splice_tail_init(list, &pdmac->desc_pool); 2254b3040e40SJassi Brar spin_unlock_irqrestore(&pdmac->pool_lock, flags); 2255b3040e40SJassi Brar } 2256b3040e40SJassi Brar 225742bc9cf4SBoojin Kim static inline void handle_cyclic_desc_list(struct list_head *list) 225842bc9cf4SBoojin Kim { 225942bc9cf4SBoojin Kim struct dma_pl330_desc *desc; 2260c8473828SOlof Johansson struct dma_pl330_chan *pch = NULL; 226142bc9cf4SBoojin Kim unsigned long flags; 226242bc9cf4SBoojin Kim 226342bc9cf4SBoojin Kim list_for_each_entry(desc, list, node) { 226442bc9cf4SBoojin Kim dma_async_tx_callback callback; 226542bc9cf4SBoojin Kim 226642bc9cf4SBoojin Kim /* Change status to reload it */ 226742bc9cf4SBoojin Kim desc->status = PREP; 226842bc9cf4SBoojin Kim pch = desc->pchan; 226942bc9cf4SBoojin Kim callback = desc->txd.callback; 227042bc9cf4SBoojin Kim if (callback) 227142bc9cf4SBoojin Kim callback(desc->txd.callback_param); 227242bc9cf4SBoojin Kim } 227342bc9cf4SBoojin Kim 2274c8473828SOlof Johansson /* pch will be unset if list was empty */ 2275c8473828SOlof Johansson if (!pch) 2276c8473828SOlof Johansson return; 2277c8473828SOlof Johansson 227842bc9cf4SBoojin Kim spin_lock_irqsave(&pch->lock, flags); 227942bc9cf4SBoojin Kim list_splice_tail_init(list, &pch->work_list); 228042bc9cf4SBoojin Kim spin_unlock_irqrestore(&pch->lock, flags); 228142bc9cf4SBoojin Kim } 228242bc9cf4SBoojin Kim 2283b3040e40SJassi Brar static inline void fill_queue(struct dma_pl330_chan *pch) 2284b3040e40SJassi Brar { 2285b3040e40SJassi Brar struct dma_pl330_desc *desc; 2286b3040e40SJassi Brar int ret; 2287b3040e40SJassi Brar 2288b3040e40SJassi Brar list_for_each_entry(desc, &pch->work_list, node) { 2289b3040e40SJassi Brar 2290b3040e40SJassi Brar /* If already submitted */ 2291b3040e40SJassi Brar if (desc->status == BUSY) 229230fb980bSJassi Brar continue; 2293b3040e40SJassi Brar 2294b3040e40SJassi Brar ret = pl330_submit_req(pch->pl330_chid, 2295b3040e40SJassi Brar &desc->req); 2296b3040e40SJassi Brar if (!ret) { 2297b3040e40SJassi Brar desc->status = BUSY; 2298b3040e40SJassi Brar } else if (ret == -EAGAIN) { 2299b3040e40SJassi Brar /* QFull or DMAC Dying */ 2300b3040e40SJassi Brar break; 2301b3040e40SJassi Brar } else { 2302b3040e40SJassi Brar /* Unacceptable request */ 2303b3040e40SJassi Brar desc->status = DONE; 2304b3040e40SJassi Brar dev_err(pch->dmac->pif.dev, "%s:%d Bad Desc(%d)\n", 2305b3040e40SJassi Brar __func__, __LINE__, desc->txd.cookie); 2306b3040e40SJassi Brar tasklet_schedule(&pch->task); 2307b3040e40SJassi Brar } 2308b3040e40SJassi Brar } 2309b3040e40SJassi Brar } 2310b3040e40SJassi Brar 2311b3040e40SJassi Brar static void pl330_tasklet(unsigned long data) 2312b3040e40SJassi Brar { 2313b3040e40SJassi Brar struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data; 2314b3040e40SJassi Brar struct dma_pl330_desc *desc, *_dt; 2315b3040e40SJassi Brar unsigned long flags; 2316b3040e40SJassi Brar LIST_HEAD(list); 2317b3040e40SJassi Brar 2318b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2319b3040e40SJassi Brar 2320b3040e40SJassi Brar /* Pick up ripe tomatoes */ 2321b3040e40SJassi Brar list_for_each_entry_safe(desc, _dt, &pch->work_list, node) 2322b3040e40SJassi Brar if (desc->status == DONE) { 232330c1dc0fSTushar Behera if (!pch->cyclic) 2324f7fbce07SRussell King - ARM Linux dma_cookie_complete(&desc->txd); 2325b3040e40SJassi Brar list_move_tail(&desc->node, &list); 2326b3040e40SJassi Brar } 2327b3040e40SJassi Brar 2328b3040e40SJassi Brar /* Try to submit a req imm. next to the last completed cookie */ 2329b3040e40SJassi Brar fill_queue(pch); 2330b3040e40SJassi Brar 2331b3040e40SJassi Brar /* Make sure the PL330 Channel thread is active */ 2332b3040e40SJassi Brar pl330_chan_ctrl(pch->pl330_chid, PL330_OP_START); 2333b3040e40SJassi Brar 2334b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 2335b3040e40SJassi Brar 233642bc9cf4SBoojin Kim if (pch->cyclic) 233742bc9cf4SBoojin Kim handle_cyclic_desc_list(&list); 233842bc9cf4SBoojin Kim else 2339b3040e40SJassi Brar free_desc_list(&list); 2340b3040e40SJassi Brar } 2341b3040e40SJassi Brar 2342b3040e40SJassi Brar static void dma_pl330_rqcb(void *token, enum pl330_op_err err) 2343b3040e40SJassi Brar { 2344b3040e40SJassi Brar struct dma_pl330_desc *desc = token; 2345b3040e40SJassi Brar struct dma_pl330_chan *pch = desc->pchan; 2346b3040e40SJassi Brar unsigned long flags; 2347b3040e40SJassi Brar 2348b3040e40SJassi Brar /* If desc aborted */ 2349b3040e40SJassi Brar if (!pch) 2350b3040e40SJassi Brar return; 2351b3040e40SJassi Brar 2352b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2353b3040e40SJassi Brar 2354b3040e40SJassi Brar desc->status = DONE; 2355b3040e40SJassi Brar 2356b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 2357b3040e40SJassi Brar 2358b3040e40SJassi Brar tasklet_schedule(&pch->task); 2359b3040e40SJassi Brar } 2360b3040e40SJassi Brar 236134d19355SPadmavathi Venna static bool pl330_dt_filter(struct dma_chan *chan, void *param) 236234d19355SPadmavathi Venna { 236334d19355SPadmavathi Venna struct dma_pl330_filter_args *fargs = param; 236434d19355SPadmavathi Venna 236534d19355SPadmavathi Venna if (chan->device != &fargs->pdmac->ddma) 236634d19355SPadmavathi Venna return false; 236734d19355SPadmavathi Venna 236834d19355SPadmavathi Venna return (chan->chan_id == fargs->chan_id); 236934d19355SPadmavathi Venna } 237034d19355SPadmavathi Venna 23713e2ec13aSThomas Abraham bool pl330_filter(struct dma_chan *chan, void *param) 23723e2ec13aSThomas Abraham { 2373cd072515SThomas Abraham u8 *peri_id; 23743e2ec13aSThomas Abraham 23753e2ec13aSThomas Abraham if (chan->device->dev->driver != &pl330_driver.drv) 23763e2ec13aSThomas Abraham return false; 23773e2ec13aSThomas Abraham 2378cd072515SThomas Abraham peri_id = chan->private; 2379cd072515SThomas Abraham return *peri_id == (unsigned)param; 23803e2ec13aSThomas Abraham } 23813e2ec13aSThomas Abraham EXPORT_SYMBOL(pl330_filter); 23823e2ec13aSThomas Abraham 2383a80258f9SPadmavathi Venna static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec, 2384a80258f9SPadmavathi Venna struct of_dma *ofdma) 2385a80258f9SPadmavathi Venna { 2386a80258f9SPadmavathi Venna int count = dma_spec->args_count; 2387a80258f9SPadmavathi Venna struct dma_pl330_dmac *pdmac = ofdma->of_dma_data; 2388a80258f9SPadmavathi Venna struct dma_pl330_filter_args fargs; 2389a80258f9SPadmavathi Venna dma_cap_mask_t cap; 2390a80258f9SPadmavathi Venna 2391a80258f9SPadmavathi Venna if (!pdmac) 2392a80258f9SPadmavathi Venna return NULL; 2393a80258f9SPadmavathi Venna 2394a80258f9SPadmavathi Venna if (count != 1) 2395a80258f9SPadmavathi Venna return NULL; 2396a80258f9SPadmavathi Venna 2397a80258f9SPadmavathi Venna fargs.pdmac = pdmac; 2398a80258f9SPadmavathi Venna fargs.chan_id = dma_spec->args[0]; 2399a80258f9SPadmavathi Venna 2400a80258f9SPadmavathi Venna dma_cap_zero(cap); 2401a80258f9SPadmavathi Venna dma_cap_set(DMA_SLAVE, cap); 2402a80258f9SPadmavathi Venna dma_cap_set(DMA_CYCLIC, cap); 2403a80258f9SPadmavathi Venna 2404a80258f9SPadmavathi Venna return dma_request_channel(cap, pl330_dt_filter, &fargs); 2405a80258f9SPadmavathi Venna } 2406a80258f9SPadmavathi Venna 2407b3040e40SJassi Brar static int pl330_alloc_chan_resources(struct dma_chan *chan) 2408b3040e40SJassi Brar { 2409b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2410b3040e40SJassi Brar struct dma_pl330_dmac *pdmac = pch->dmac; 2411b3040e40SJassi Brar unsigned long flags; 2412b3040e40SJassi Brar 2413b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2414b3040e40SJassi Brar 2415d3ee98cdSRussell King - ARM Linux dma_cookie_init(chan); 241642bc9cf4SBoojin Kim pch->cyclic = false; 2417b3040e40SJassi Brar 2418b3040e40SJassi Brar pch->pl330_chid = pl330_request_channel(&pdmac->pif); 2419b3040e40SJassi Brar if (!pch->pl330_chid) { 2420b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 242102747885SInderpal Singh return -ENOMEM; 2422b3040e40SJassi Brar } 2423b3040e40SJassi Brar 2424b3040e40SJassi Brar tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch); 2425b3040e40SJassi Brar 2426b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 2427b3040e40SJassi Brar 2428b3040e40SJassi Brar return 1; 2429b3040e40SJassi Brar } 2430b3040e40SJassi Brar 2431b3040e40SJassi Brar static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg) 2432b3040e40SJassi Brar { 2433b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2434ae43b886SBoojin Kim struct dma_pl330_desc *desc, *_dt; 2435b3040e40SJassi Brar unsigned long flags; 24361d0c1d60SBoojin Kim struct dma_pl330_dmac *pdmac = pch->dmac; 24371d0c1d60SBoojin Kim struct dma_slave_config *slave_config; 2438ae43b886SBoojin Kim LIST_HEAD(list); 2439b3040e40SJassi Brar 24401d0c1d60SBoojin Kim switch (cmd) { 24411d0c1d60SBoojin Kim case DMA_TERMINATE_ALL: 2442b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2443b3040e40SJassi Brar 2444b3040e40SJassi Brar /* FLUSH the PL330 Channel thread */ 2445b3040e40SJassi Brar pl330_chan_ctrl(pch->pl330_chid, PL330_OP_FLUSH); 2446b3040e40SJassi Brar 2447b3040e40SJassi Brar /* Mark all desc done */ 2448ae43b886SBoojin Kim list_for_each_entry_safe(desc, _dt, &pch->work_list , node) { 2449b3040e40SJassi Brar desc->status = DONE; 2450ae43b886SBoojin Kim list_move_tail(&desc->node, &list); 2451ae43b886SBoojin Kim } 2452b3040e40SJassi Brar 2453ae43b886SBoojin Kim list_splice_tail_init(&list, &pdmac->desc_pool); 2454b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 24551d0c1d60SBoojin Kim break; 24561d0c1d60SBoojin Kim case DMA_SLAVE_CONFIG: 24571d0c1d60SBoojin Kim slave_config = (struct dma_slave_config *)arg; 2458b3040e40SJassi Brar 2459db8196dfSVinod Koul if (slave_config->direction == DMA_MEM_TO_DEV) { 24601d0c1d60SBoojin Kim if (slave_config->dst_addr) 24611d0c1d60SBoojin Kim pch->fifo_addr = slave_config->dst_addr; 24621d0c1d60SBoojin Kim if (slave_config->dst_addr_width) 24631d0c1d60SBoojin Kim pch->burst_sz = __ffs(slave_config->dst_addr_width); 24641d0c1d60SBoojin Kim if (slave_config->dst_maxburst) 24651d0c1d60SBoojin Kim pch->burst_len = slave_config->dst_maxburst; 2466db8196dfSVinod Koul } else if (slave_config->direction == DMA_DEV_TO_MEM) { 24671d0c1d60SBoojin Kim if (slave_config->src_addr) 24681d0c1d60SBoojin Kim pch->fifo_addr = slave_config->src_addr; 24691d0c1d60SBoojin Kim if (slave_config->src_addr_width) 24701d0c1d60SBoojin Kim pch->burst_sz = __ffs(slave_config->src_addr_width); 24711d0c1d60SBoojin Kim if (slave_config->src_maxburst) 24721d0c1d60SBoojin Kim pch->burst_len = slave_config->src_maxburst; 24731d0c1d60SBoojin Kim } 24741d0c1d60SBoojin Kim break; 24751d0c1d60SBoojin Kim default: 24761d0c1d60SBoojin Kim dev_err(pch->dmac->pif.dev, "Not supported command.\n"); 24771d0c1d60SBoojin Kim return -ENXIO; 24781d0c1d60SBoojin Kim } 2479b3040e40SJassi Brar 2480b3040e40SJassi Brar return 0; 2481b3040e40SJassi Brar } 2482b3040e40SJassi Brar 2483b3040e40SJassi Brar static void pl330_free_chan_resources(struct dma_chan *chan) 2484b3040e40SJassi Brar { 2485b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2486b3040e40SJassi Brar unsigned long flags; 2487b3040e40SJassi Brar 2488b3040e40SJassi Brar tasklet_kill(&pch->task); 2489b3040e40SJassi Brar 2490da331ba8SBartlomiej Zolnierkiewicz spin_lock_irqsave(&pch->lock, flags); 2491da331ba8SBartlomiej Zolnierkiewicz 2492b3040e40SJassi Brar pl330_release_channel(pch->pl330_chid); 2493b3040e40SJassi Brar pch->pl330_chid = NULL; 2494b3040e40SJassi Brar 249542bc9cf4SBoojin Kim if (pch->cyclic) 249642bc9cf4SBoojin Kim list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); 249742bc9cf4SBoojin Kim 2498b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 2499b3040e40SJassi Brar } 2500b3040e40SJassi Brar 2501b3040e40SJassi Brar static enum dma_status 2502b3040e40SJassi Brar pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, 2503b3040e40SJassi Brar struct dma_tx_state *txstate) 2504b3040e40SJassi Brar { 250596a2af41SRussell King - ARM Linux return dma_cookie_status(chan, cookie, txstate); 2506b3040e40SJassi Brar } 2507b3040e40SJassi Brar 2508b3040e40SJassi Brar static void pl330_issue_pending(struct dma_chan *chan) 2509b3040e40SJassi Brar { 2510b3040e40SJassi Brar pl330_tasklet((unsigned long) to_pchan(chan)); 2511b3040e40SJassi Brar } 2512b3040e40SJassi Brar 2513b3040e40SJassi Brar /* 2514b3040e40SJassi Brar * We returned the last one of the circular list of descriptor(s) 2515b3040e40SJassi Brar * from prep_xxx, so the argument to submit corresponds to the last 2516b3040e40SJassi Brar * descriptor of the list. 2517b3040e40SJassi Brar */ 2518b3040e40SJassi Brar static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) 2519b3040e40SJassi Brar { 2520b3040e40SJassi Brar struct dma_pl330_desc *desc, *last = to_desc(tx); 2521b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(tx->chan); 2522b3040e40SJassi Brar dma_cookie_t cookie; 2523b3040e40SJassi Brar unsigned long flags; 2524b3040e40SJassi Brar 2525b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2526b3040e40SJassi Brar 2527b3040e40SJassi Brar /* Assign cookies to all nodes */ 2528b3040e40SJassi Brar while (!list_empty(&last->node)) { 2529b3040e40SJassi Brar desc = list_entry(last->node.next, struct dma_pl330_desc, node); 2530b3040e40SJassi Brar 2531884485e1SRussell King - ARM Linux dma_cookie_assign(&desc->txd); 2532b3040e40SJassi Brar 2533b3040e40SJassi Brar list_move_tail(&desc->node, &pch->work_list); 2534b3040e40SJassi Brar } 2535b3040e40SJassi Brar 2536884485e1SRussell King - ARM Linux cookie = dma_cookie_assign(&last->txd); 2537b3040e40SJassi Brar list_add_tail(&last->node, &pch->work_list); 2538b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 2539b3040e40SJassi Brar 2540b3040e40SJassi Brar return cookie; 2541b3040e40SJassi Brar } 2542b3040e40SJassi Brar 2543b3040e40SJassi Brar static inline void _init_desc(struct dma_pl330_desc *desc) 2544b3040e40SJassi Brar { 2545b3040e40SJassi Brar desc->pchan = NULL; 2546b3040e40SJassi Brar desc->req.x = &desc->px; 2547b3040e40SJassi Brar desc->req.token = desc; 2548b3040e40SJassi Brar desc->rqcfg.swap = SWAP_NO; 2549b3040e40SJassi Brar desc->rqcfg.privileged = 0; 2550b3040e40SJassi Brar desc->rqcfg.insnaccess = 0; 2551b3040e40SJassi Brar desc->rqcfg.scctl = SCCTRL0; 2552b3040e40SJassi Brar desc->rqcfg.dcctl = DCCTRL0; 2553b3040e40SJassi Brar desc->req.cfg = &desc->rqcfg; 2554b3040e40SJassi Brar desc->req.xfer_cb = dma_pl330_rqcb; 2555b3040e40SJassi Brar desc->txd.tx_submit = pl330_tx_submit; 2556b3040e40SJassi Brar 2557b3040e40SJassi Brar INIT_LIST_HEAD(&desc->node); 2558b3040e40SJassi Brar } 2559b3040e40SJassi Brar 2560b3040e40SJassi Brar /* Returns the number of descriptors added to the DMAC pool */ 25615a67ac57SSachin Kamat static int add_desc(struct dma_pl330_dmac *pdmac, gfp_t flg, int count) 2562b3040e40SJassi Brar { 2563b3040e40SJassi Brar struct dma_pl330_desc *desc; 2564b3040e40SJassi Brar unsigned long flags; 2565b3040e40SJassi Brar int i; 2566b3040e40SJassi Brar 2567b3040e40SJassi Brar if (!pdmac) 2568b3040e40SJassi Brar return 0; 2569b3040e40SJassi Brar 2570b3040e40SJassi Brar desc = kmalloc(count * sizeof(*desc), flg); 2571b3040e40SJassi Brar if (!desc) 2572b3040e40SJassi Brar return 0; 2573b3040e40SJassi Brar 2574b3040e40SJassi Brar spin_lock_irqsave(&pdmac->pool_lock, flags); 2575b3040e40SJassi Brar 2576b3040e40SJassi Brar for (i = 0; i < count; i++) { 2577b3040e40SJassi Brar _init_desc(&desc[i]); 2578b3040e40SJassi Brar list_add_tail(&desc[i].node, &pdmac->desc_pool); 2579b3040e40SJassi Brar } 2580b3040e40SJassi Brar 2581b3040e40SJassi Brar spin_unlock_irqrestore(&pdmac->pool_lock, flags); 2582b3040e40SJassi Brar 2583b3040e40SJassi Brar return count; 2584b3040e40SJassi Brar } 2585b3040e40SJassi Brar 2586b3040e40SJassi Brar static struct dma_pl330_desc * 2587b3040e40SJassi Brar pluck_desc(struct dma_pl330_dmac *pdmac) 2588b3040e40SJassi Brar { 2589b3040e40SJassi Brar struct dma_pl330_desc *desc = NULL; 2590b3040e40SJassi Brar unsigned long flags; 2591b3040e40SJassi Brar 2592b3040e40SJassi Brar if (!pdmac) 2593b3040e40SJassi Brar return NULL; 2594b3040e40SJassi Brar 2595b3040e40SJassi Brar spin_lock_irqsave(&pdmac->pool_lock, flags); 2596b3040e40SJassi Brar 2597b3040e40SJassi Brar if (!list_empty(&pdmac->desc_pool)) { 2598b3040e40SJassi Brar desc = list_entry(pdmac->desc_pool.next, 2599b3040e40SJassi Brar struct dma_pl330_desc, node); 2600b3040e40SJassi Brar 2601b3040e40SJassi Brar list_del_init(&desc->node); 2602b3040e40SJassi Brar 2603b3040e40SJassi Brar desc->status = PREP; 2604b3040e40SJassi Brar desc->txd.callback = NULL; 2605b3040e40SJassi Brar } 2606b3040e40SJassi Brar 2607b3040e40SJassi Brar spin_unlock_irqrestore(&pdmac->pool_lock, flags); 2608b3040e40SJassi Brar 2609b3040e40SJassi Brar return desc; 2610b3040e40SJassi Brar } 2611b3040e40SJassi Brar 2612b3040e40SJassi Brar static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) 2613b3040e40SJassi Brar { 2614b3040e40SJassi Brar struct dma_pl330_dmac *pdmac = pch->dmac; 2615cd072515SThomas Abraham u8 *peri_id = pch->chan.private; 2616b3040e40SJassi Brar struct dma_pl330_desc *desc; 2617b3040e40SJassi Brar 2618b3040e40SJassi Brar /* Pluck one desc from the pool of DMAC */ 2619b3040e40SJassi Brar desc = pluck_desc(pdmac); 2620b3040e40SJassi Brar 2621b3040e40SJassi Brar /* If the DMAC pool is empty, alloc new */ 2622b3040e40SJassi Brar if (!desc) { 2623b3040e40SJassi Brar if (!add_desc(pdmac, GFP_ATOMIC, 1)) 2624b3040e40SJassi Brar return NULL; 2625b3040e40SJassi Brar 2626b3040e40SJassi Brar /* Try again */ 2627b3040e40SJassi Brar desc = pluck_desc(pdmac); 2628b3040e40SJassi Brar if (!desc) { 2629b3040e40SJassi Brar dev_err(pch->dmac->pif.dev, 2630b3040e40SJassi Brar "%s:%d ALERT!\n", __func__, __LINE__); 2631b3040e40SJassi Brar return NULL; 2632b3040e40SJassi Brar } 2633b3040e40SJassi Brar } 2634b3040e40SJassi Brar 2635b3040e40SJassi Brar /* Initialize the descriptor */ 2636b3040e40SJassi Brar desc->pchan = pch; 2637b3040e40SJassi Brar desc->txd.cookie = 0; 2638b3040e40SJassi Brar async_tx_ack(&desc->txd); 2639b3040e40SJassi Brar 2640cd072515SThomas Abraham desc->req.peri = peri_id ? pch->chan.chan_id : 0; 26413ecf51a4SBoojin Kim desc->rqcfg.pcfg = &pch->dmac->pif.pcfg; 2642b3040e40SJassi Brar 2643b3040e40SJassi Brar dma_async_tx_descriptor_init(&desc->txd, &pch->chan); 2644b3040e40SJassi Brar 2645b3040e40SJassi Brar return desc; 2646b3040e40SJassi Brar } 2647b3040e40SJassi Brar 2648b3040e40SJassi Brar static inline void fill_px(struct pl330_xfer *px, 2649b3040e40SJassi Brar dma_addr_t dst, dma_addr_t src, size_t len) 2650b3040e40SJassi Brar { 2651b3040e40SJassi Brar px->next = NULL; 2652b3040e40SJassi Brar px->bytes = len; 2653b3040e40SJassi Brar px->dst_addr = dst; 2654b3040e40SJassi Brar px->src_addr = src; 2655b3040e40SJassi Brar } 2656b3040e40SJassi Brar 2657b3040e40SJassi Brar static struct dma_pl330_desc * 2658b3040e40SJassi Brar __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, 2659b3040e40SJassi Brar dma_addr_t src, size_t len) 2660b3040e40SJassi Brar { 2661b3040e40SJassi Brar struct dma_pl330_desc *desc = pl330_get_desc(pch); 2662b3040e40SJassi Brar 2663b3040e40SJassi Brar if (!desc) { 2664b3040e40SJassi Brar dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n", 2665b3040e40SJassi Brar __func__, __LINE__); 2666b3040e40SJassi Brar return NULL; 2667b3040e40SJassi Brar } 2668b3040e40SJassi Brar 2669b3040e40SJassi Brar /* 2670b3040e40SJassi Brar * Ideally we should lookout for reqs bigger than 2671b3040e40SJassi Brar * those that can be programmed with 256 bytes of 2672b3040e40SJassi Brar * MC buffer, but considering a req size is seldom 2673b3040e40SJassi Brar * going to be word-unaligned and more than 200MB, 2674b3040e40SJassi Brar * we take it easy. 2675b3040e40SJassi Brar * Also, should the limit is reached we'd rather 2676b3040e40SJassi Brar * have the platform increase MC buffer size than 2677b3040e40SJassi Brar * complicating this API driver. 2678b3040e40SJassi Brar */ 2679b3040e40SJassi Brar fill_px(&desc->px, dst, src, len); 2680b3040e40SJassi Brar 2681b3040e40SJassi Brar return desc; 2682b3040e40SJassi Brar } 2683b3040e40SJassi Brar 2684b3040e40SJassi Brar /* Call after fixing burst size */ 2685b3040e40SJassi Brar static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) 2686b3040e40SJassi Brar { 2687b3040e40SJassi Brar struct dma_pl330_chan *pch = desc->pchan; 2688b3040e40SJassi Brar struct pl330_info *pi = &pch->dmac->pif; 2689b3040e40SJassi Brar int burst_len; 2690b3040e40SJassi Brar 2691b3040e40SJassi Brar burst_len = pi->pcfg.data_bus_width / 8; 2692b3040e40SJassi Brar burst_len *= pi->pcfg.data_buf_dep; 2693b3040e40SJassi Brar burst_len >>= desc->rqcfg.brst_size; 2694b3040e40SJassi Brar 2695b3040e40SJassi Brar /* src/dst_burst_len can't be more than 16 */ 2696b3040e40SJassi Brar if (burst_len > 16) 2697b3040e40SJassi Brar burst_len = 16; 2698b3040e40SJassi Brar 2699b3040e40SJassi Brar while (burst_len > 1) { 2700b3040e40SJassi Brar if (!(len % (burst_len << desc->rqcfg.brst_size))) 2701b3040e40SJassi Brar break; 2702b3040e40SJassi Brar burst_len--; 2703b3040e40SJassi Brar } 2704b3040e40SJassi Brar 2705b3040e40SJassi Brar return burst_len; 2706b3040e40SJassi Brar } 2707b3040e40SJassi Brar 270842bc9cf4SBoojin Kim static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( 270942bc9cf4SBoojin Kim struct dma_chan *chan, dma_addr_t dma_addr, size_t len, 2710185ecb5fSAlexandre Bounine size_t period_len, enum dma_transfer_direction direction, 2711ec8b5e48SPeter Ujfalusi unsigned long flags, void *context) 271242bc9cf4SBoojin Kim { 271342bc9cf4SBoojin Kim struct dma_pl330_desc *desc; 271442bc9cf4SBoojin Kim struct dma_pl330_chan *pch = to_pchan(chan); 271542bc9cf4SBoojin Kim dma_addr_t dst; 271642bc9cf4SBoojin Kim dma_addr_t src; 271742bc9cf4SBoojin Kim 271842bc9cf4SBoojin Kim desc = pl330_get_desc(pch); 271942bc9cf4SBoojin Kim if (!desc) { 272042bc9cf4SBoojin Kim dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n", 272142bc9cf4SBoojin Kim __func__, __LINE__); 272242bc9cf4SBoojin Kim return NULL; 272342bc9cf4SBoojin Kim } 272442bc9cf4SBoojin Kim 272542bc9cf4SBoojin Kim switch (direction) { 2726db8196dfSVinod Koul case DMA_MEM_TO_DEV: 272742bc9cf4SBoojin Kim desc->rqcfg.src_inc = 1; 272842bc9cf4SBoojin Kim desc->rqcfg.dst_inc = 0; 2729cd072515SThomas Abraham desc->req.rqtype = MEMTODEV; 273042bc9cf4SBoojin Kim src = dma_addr; 273142bc9cf4SBoojin Kim dst = pch->fifo_addr; 273242bc9cf4SBoojin Kim break; 2733db8196dfSVinod Koul case DMA_DEV_TO_MEM: 273442bc9cf4SBoojin Kim desc->rqcfg.src_inc = 0; 273542bc9cf4SBoojin Kim desc->rqcfg.dst_inc = 1; 2736cd072515SThomas Abraham desc->req.rqtype = DEVTOMEM; 273742bc9cf4SBoojin Kim src = pch->fifo_addr; 273842bc9cf4SBoojin Kim dst = dma_addr; 273942bc9cf4SBoojin Kim break; 274042bc9cf4SBoojin Kim default: 274142bc9cf4SBoojin Kim dev_err(pch->dmac->pif.dev, "%s:%d Invalid dma direction\n", 274242bc9cf4SBoojin Kim __func__, __LINE__); 274342bc9cf4SBoojin Kim return NULL; 274442bc9cf4SBoojin Kim } 274542bc9cf4SBoojin Kim 274642bc9cf4SBoojin Kim desc->rqcfg.brst_size = pch->burst_sz; 274742bc9cf4SBoojin Kim desc->rqcfg.brst_len = 1; 274842bc9cf4SBoojin Kim 274942bc9cf4SBoojin Kim pch->cyclic = true; 275042bc9cf4SBoojin Kim 275142bc9cf4SBoojin Kim fill_px(&desc->px, dst, src, period_len); 275242bc9cf4SBoojin Kim 275342bc9cf4SBoojin Kim return &desc->txd; 275442bc9cf4SBoojin Kim } 275542bc9cf4SBoojin Kim 2756b3040e40SJassi Brar static struct dma_async_tx_descriptor * 2757b3040e40SJassi Brar pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, 2758b3040e40SJassi Brar dma_addr_t src, size_t len, unsigned long flags) 2759b3040e40SJassi Brar { 2760b3040e40SJassi Brar struct dma_pl330_desc *desc; 2761b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2762b3040e40SJassi Brar struct pl330_info *pi; 2763b3040e40SJassi Brar int burst; 2764b3040e40SJassi Brar 27654e0e6109SRob Herring if (unlikely(!pch || !len)) 2766b3040e40SJassi Brar return NULL; 2767b3040e40SJassi Brar 2768b3040e40SJassi Brar pi = &pch->dmac->pif; 2769b3040e40SJassi Brar 2770b3040e40SJassi Brar desc = __pl330_prep_dma_memcpy(pch, dst, src, len); 2771b3040e40SJassi Brar if (!desc) 2772b3040e40SJassi Brar return NULL; 2773b3040e40SJassi Brar 2774b3040e40SJassi Brar desc->rqcfg.src_inc = 1; 2775b3040e40SJassi Brar desc->rqcfg.dst_inc = 1; 2776cd072515SThomas Abraham desc->req.rqtype = MEMTOMEM; 2777b3040e40SJassi Brar 2778b3040e40SJassi Brar /* Select max possible burst size */ 2779b3040e40SJassi Brar burst = pi->pcfg.data_bus_width / 8; 2780b3040e40SJassi Brar 2781b3040e40SJassi Brar while (burst > 1) { 2782b3040e40SJassi Brar if (!(len % burst)) 2783b3040e40SJassi Brar break; 2784b3040e40SJassi Brar burst /= 2; 2785b3040e40SJassi Brar } 2786b3040e40SJassi Brar 2787b3040e40SJassi Brar desc->rqcfg.brst_size = 0; 2788b3040e40SJassi Brar while (burst != (1 << desc->rqcfg.brst_size)) 2789b3040e40SJassi Brar desc->rqcfg.brst_size++; 2790b3040e40SJassi Brar 2791b3040e40SJassi Brar desc->rqcfg.brst_len = get_burst_len(desc, len); 2792b3040e40SJassi Brar 2793b3040e40SJassi Brar desc->txd.flags = flags; 2794b3040e40SJassi Brar 2795b3040e40SJassi Brar return &desc->txd; 2796b3040e40SJassi Brar } 2797b3040e40SJassi Brar 2798b3040e40SJassi Brar static struct dma_async_tx_descriptor * 2799b3040e40SJassi Brar pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 2800db8196dfSVinod Koul unsigned int sg_len, enum dma_transfer_direction direction, 2801185ecb5fSAlexandre Bounine unsigned long flg, void *context) 2802b3040e40SJassi Brar { 2803b3040e40SJassi Brar struct dma_pl330_desc *first, *desc = NULL; 2804b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2805b3040e40SJassi Brar struct scatterlist *sg; 2806b3040e40SJassi Brar unsigned long flags; 28071b9bb715SBoojin Kim int i; 2808b3040e40SJassi Brar dma_addr_t addr; 2809b3040e40SJassi Brar 2810cd072515SThomas Abraham if (unlikely(!pch || !sgl || !sg_len)) 2811b3040e40SJassi Brar return NULL; 2812b3040e40SJassi Brar 28131b9bb715SBoojin Kim addr = pch->fifo_addr; 2814b3040e40SJassi Brar 2815b3040e40SJassi Brar first = NULL; 2816b3040e40SJassi Brar 2817b3040e40SJassi Brar for_each_sg(sgl, sg, sg_len, i) { 2818b3040e40SJassi Brar 2819b3040e40SJassi Brar desc = pl330_get_desc(pch); 2820b3040e40SJassi Brar if (!desc) { 2821b3040e40SJassi Brar struct dma_pl330_dmac *pdmac = pch->dmac; 2822b3040e40SJassi Brar 2823b3040e40SJassi Brar dev_err(pch->dmac->pif.dev, 2824b3040e40SJassi Brar "%s:%d Unable to fetch desc\n", 2825b3040e40SJassi Brar __func__, __LINE__); 2826b3040e40SJassi Brar if (!first) 2827b3040e40SJassi Brar return NULL; 2828b3040e40SJassi Brar 2829b3040e40SJassi Brar spin_lock_irqsave(&pdmac->pool_lock, flags); 2830b3040e40SJassi Brar 2831b3040e40SJassi Brar while (!list_empty(&first->node)) { 2832b3040e40SJassi Brar desc = list_entry(first->node.next, 2833b3040e40SJassi Brar struct dma_pl330_desc, node); 2834b3040e40SJassi Brar list_move_tail(&desc->node, &pdmac->desc_pool); 2835b3040e40SJassi Brar } 2836b3040e40SJassi Brar 2837b3040e40SJassi Brar list_move_tail(&first->node, &pdmac->desc_pool); 2838b3040e40SJassi Brar 2839b3040e40SJassi Brar spin_unlock_irqrestore(&pdmac->pool_lock, flags); 2840b3040e40SJassi Brar 2841b3040e40SJassi Brar return NULL; 2842b3040e40SJassi Brar } 2843b3040e40SJassi Brar 2844b3040e40SJassi Brar if (!first) 2845b3040e40SJassi Brar first = desc; 2846b3040e40SJassi Brar else 2847b3040e40SJassi Brar list_add_tail(&desc->node, &first->node); 2848b3040e40SJassi Brar 2849db8196dfSVinod Koul if (direction == DMA_MEM_TO_DEV) { 2850b3040e40SJassi Brar desc->rqcfg.src_inc = 1; 2851b3040e40SJassi Brar desc->rqcfg.dst_inc = 0; 2852cd072515SThomas Abraham desc->req.rqtype = MEMTODEV; 2853b3040e40SJassi Brar fill_px(&desc->px, 2854b3040e40SJassi Brar addr, sg_dma_address(sg), sg_dma_len(sg)); 2855b3040e40SJassi Brar } else { 2856b3040e40SJassi Brar desc->rqcfg.src_inc = 0; 2857b3040e40SJassi Brar desc->rqcfg.dst_inc = 1; 2858cd072515SThomas Abraham desc->req.rqtype = DEVTOMEM; 2859b3040e40SJassi Brar fill_px(&desc->px, 2860b3040e40SJassi Brar sg_dma_address(sg), addr, sg_dma_len(sg)); 2861b3040e40SJassi Brar } 2862b3040e40SJassi Brar 28631b9bb715SBoojin Kim desc->rqcfg.brst_size = pch->burst_sz; 2864b3040e40SJassi Brar desc->rqcfg.brst_len = 1; 2865b3040e40SJassi Brar } 2866b3040e40SJassi Brar 2867b3040e40SJassi Brar /* Return the last desc in the chain */ 2868b3040e40SJassi Brar desc->txd.flags = flg; 2869b3040e40SJassi Brar return &desc->txd; 2870b3040e40SJassi Brar } 2871b3040e40SJassi Brar 2872b3040e40SJassi Brar static irqreturn_t pl330_irq_handler(int irq, void *data) 2873b3040e40SJassi Brar { 2874b3040e40SJassi Brar if (pl330_update(data)) 2875b3040e40SJassi Brar return IRQ_HANDLED; 2876b3040e40SJassi Brar else 2877b3040e40SJassi Brar return IRQ_NONE; 2878b3040e40SJassi Brar } 2879b3040e40SJassi Brar 2880463a1f8bSBill Pemberton static int 2881aa25afadSRussell King pl330_probe(struct amba_device *adev, const struct amba_id *id) 2882b3040e40SJassi Brar { 2883b3040e40SJassi Brar struct dma_pl330_platdata *pdat; 2884b3040e40SJassi Brar struct dma_pl330_dmac *pdmac; 28850b94c577SPadmavathi Venna struct dma_pl330_chan *pch, *_p; 2886b3040e40SJassi Brar struct pl330_info *pi; 2887b3040e40SJassi Brar struct dma_device *pd; 2888b3040e40SJassi Brar struct resource *res; 2889b3040e40SJassi Brar int i, ret, irq; 28904e0e6109SRob Herring int num_chan; 2891b3040e40SJassi Brar 2892b3040e40SJassi Brar pdat = adev->dev.platform_data; 2893b3040e40SJassi Brar 2894b3040e40SJassi Brar /* Allocate a new DMAC and its Channels */ 2895e4d43c17SSachin Kamat pdmac = devm_kzalloc(&adev->dev, sizeof(*pdmac), GFP_KERNEL); 2896b3040e40SJassi Brar if (!pdmac) { 2897b3040e40SJassi Brar dev_err(&adev->dev, "unable to allocate mem\n"); 2898b3040e40SJassi Brar return -ENOMEM; 2899b3040e40SJassi Brar } 2900b3040e40SJassi Brar 2901b3040e40SJassi Brar pi = &pdmac->pif; 2902b3040e40SJassi Brar pi->dev = &adev->dev; 2903b3040e40SJassi Brar pi->pl330_data = NULL; 29044e0e6109SRob Herring pi->mcbufsz = pdat ? pdat->mcbuf_sz : 0; 2905b3040e40SJassi Brar 2906b3040e40SJassi Brar res = &adev->res; 2907bcc7fa95SSachin Kamat pi->base = devm_ioremap_resource(&adev->dev, res); 2908bcc7fa95SSachin Kamat if (IS_ERR(pi->base)) 2909bcc7fa95SSachin Kamat return PTR_ERR(pi->base); 2910b3040e40SJassi Brar 2911a2f5203fSBoojin Kim amba_set_drvdata(adev, pdmac); 2912a2f5203fSBoojin Kim 2913b3040e40SJassi Brar irq = adev->irq[0]; 2914b3040e40SJassi Brar ret = request_irq(irq, pl330_irq_handler, 0, 2915b3040e40SJassi Brar dev_name(&adev->dev), pi); 2916b3040e40SJassi Brar if (ret) 2917e4d43c17SSachin Kamat return ret; 2918b3040e40SJassi Brar 2919b3040e40SJassi Brar ret = pl330_add(pi); 2920b3040e40SJassi Brar if (ret) 2921e4d43c17SSachin Kamat goto probe_err1; 2922b3040e40SJassi Brar 2923b3040e40SJassi Brar INIT_LIST_HEAD(&pdmac->desc_pool); 2924b3040e40SJassi Brar spin_lock_init(&pdmac->pool_lock); 2925b3040e40SJassi Brar 2926b3040e40SJassi Brar /* Create a descriptor pool of default size */ 2927b3040e40SJassi Brar if (!add_desc(pdmac, GFP_KERNEL, NR_DEFAULT_DESC)) 2928b3040e40SJassi Brar dev_warn(&adev->dev, "unable to allocate desc\n"); 2929b3040e40SJassi Brar 2930b3040e40SJassi Brar pd = &pdmac->ddma; 2931b3040e40SJassi Brar INIT_LIST_HEAD(&pd->channels); 2932b3040e40SJassi Brar 2933b3040e40SJassi Brar /* Initialize channel parameters */ 2934c8473828SOlof Johansson if (pdat) 2935c8473828SOlof Johansson num_chan = max_t(int, pdat->nr_valid_peri, pi->pcfg.num_chan); 2936c8473828SOlof Johansson else 2937c8473828SOlof Johansson num_chan = max_t(int, pi->pcfg.num_peri, pi->pcfg.num_chan); 2938c8473828SOlof Johansson 29394e0e6109SRob Herring pdmac->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL); 294061c6e753SSachin Kamat if (!pdmac->peripherals) { 294161c6e753SSachin Kamat ret = -ENOMEM; 294261c6e753SSachin Kamat dev_err(&adev->dev, "unable to allocate pdmac->peripherals\n"); 2943e4d43c17SSachin Kamat goto probe_err2; 294461c6e753SSachin Kamat } 29454e0e6109SRob Herring 29464e0e6109SRob Herring for (i = 0; i < num_chan; i++) { 2947b3040e40SJassi Brar pch = &pdmac->peripherals[i]; 294893ed5544SThomas Abraham if (!adev->dev.of_node) 2949cd072515SThomas Abraham pch->chan.private = pdat ? &pdat->peri_id[i] : NULL; 295093ed5544SThomas Abraham else 295193ed5544SThomas Abraham pch->chan.private = adev->dev.of_node; 2952b3040e40SJassi Brar 2953b3040e40SJassi Brar INIT_LIST_HEAD(&pch->work_list); 2954b3040e40SJassi Brar spin_lock_init(&pch->lock); 2955b3040e40SJassi Brar pch->pl330_chid = NULL; 2956b3040e40SJassi Brar pch->chan.device = pd; 2957b3040e40SJassi Brar pch->dmac = pdmac; 2958b3040e40SJassi Brar 2959b3040e40SJassi Brar /* Add the channel to the DMAC list */ 2960b3040e40SJassi Brar list_add_tail(&pch->chan.device_node, &pd->channels); 2961b3040e40SJassi Brar } 2962b3040e40SJassi Brar 2963b3040e40SJassi Brar pd->dev = &adev->dev; 296493ed5544SThomas Abraham if (pdat) { 2965cd072515SThomas Abraham pd->cap_mask = pdat->cap_mask; 296693ed5544SThomas Abraham } else { 2967cd072515SThomas Abraham dma_cap_set(DMA_MEMCPY, pd->cap_mask); 296893ed5544SThomas Abraham if (pi->pcfg.num_peri) { 296993ed5544SThomas Abraham dma_cap_set(DMA_SLAVE, pd->cap_mask); 297093ed5544SThomas Abraham dma_cap_set(DMA_CYCLIC, pd->cap_mask); 29715557a419STushar Behera dma_cap_set(DMA_PRIVATE, pd->cap_mask); 297293ed5544SThomas Abraham } 297393ed5544SThomas Abraham } 2974b3040e40SJassi Brar 2975b3040e40SJassi Brar pd->device_alloc_chan_resources = pl330_alloc_chan_resources; 2976b3040e40SJassi Brar pd->device_free_chan_resources = pl330_free_chan_resources; 2977b3040e40SJassi Brar pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; 297842bc9cf4SBoojin Kim pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; 2979b3040e40SJassi Brar pd->device_tx_status = pl330_tx_status; 2980b3040e40SJassi Brar pd->device_prep_slave_sg = pl330_prep_slave_sg; 2981b3040e40SJassi Brar pd->device_control = pl330_control; 2982b3040e40SJassi Brar pd->device_issue_pending = pl330_issue_pending; 2983b3040e40SJassi Brar 2984b3040e40SJassi Brar ret = dma_async_device_register(pd); 2985b3040e40SJassi Brar if (ret) { 2986b3040e40SJassi Brar dev_err(&adev->dev, "unable to register DMAC\n"); 29870b94c577SPadmavathi Venna goto probe_err3; 29880b94c577SPadmavathi Venna } 29890b94c577SPadmavathi Venna 29900b94c577SPadmavathi Venna if (adev->dev.of_node) { 29910b94c577SPadmavathi Venna ret = of_dma_controller_register(adev->dev.of_node, 29920b94c577SPadmavathi Venna of_dma_pl330_xlate, pdmac); 29930b94c577SPadmavathi Venna if (ret) { 29940b94c577SPadmavathi Venna dev_err(&adev->dev, 29950b94c577SPadmavathi Venna "unable to register DMA to the generic DT DMA helpers\n"); 29960b94c577SPadmavathi Venna } 2997b3040e40SJassi Brar } 2998b3040e40SJassi Brar 2999b3040e40SJassi Brar dev_info(&adev->dev, 3000b3040e40SJassi Brar "Loaded driver for PL330 DMAC-%d\n", adev->periphid); 3001b3040e40SJassi Brar dev_info(&adev->dev, 3002b3040e40SJassi Brar "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", 3003b3040e40SJassi Brar pi->pcfg.data_buf_dep, 3004b3040e40SJassi Brar pi->pcfg.data_bus_width / 8, pi->pcfg.num_chan, 3005b3040e40SJassi Brar pi->pcfg.num_peri, pi->pcfg.num_events); 3006b3040e40SJassi Brar 3007b3040e40SJassi Brar return 0; 30080b94c577SPadmavathi Venna probe_err3: 30090b94c577SPadmavathi Venna amba_set_drvdata(adev, NULL); 3010b3040e40SJassi Brar 30110b94c577SPadmavathi Venna /* Idle the DMAC */ 30120b94c577SPadmavathi Venna list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels, 30130b94c577SPadmavathi Venna chan.device_node) { 30140b94c577SPadmavathi Venna 30150b94c577SPadmavathi Venna /* Remove the channel */ 30160b94c577SPadmavathi Venna list_del(&pch->chan.device_node); 30170b94c577SPadmavathi Venna 30180b94c577SPadmavathi Venna /* Flush the channel */ 30190b94c577SPadmavathi Venna pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); 30200b94c577SPadmavathi Venna pl330_free_chan_resources(&pch->chan); 30210b94c577SPadmavathi Venna } 3022b3040e40SJassi Brar probe_err2: 3023e4d43c17SSachin Kamat pl330_del(pi); 3024b3040e40SJassi Brar probe_err1: 3025e4d43c17SSachin Kamat free_irq(irq, pi); 3026b3040e40SJassi Brar 3027b3040e40SJassi Brar return ret; 3028b3040e40SJassi Brar } 3029b3040e40SJassi Brar 30304bf27b8bSGreg Kroah-Hartman static int pl330_remove(struct amba_device *adev) 3031b3040e40SJassi Brar { 3032b3040e40SJassi Brar struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev); 3033b3040e40SJassi Brar struct dma_pl330_chan *pch, *_p; 3034b3040e40SJassi Brar struct pl330_info *pi; 3035b3040e40SJassi Brar int irq; 3036b3040e40SJassi Brar 3037b3040e40SJassi Brar if (!pdmac) 3038b3040e40SJassi Brar return 0; 3039b3040e40SJassi Brar 30400b94c577SPadmavathi Venna if (adev->dev.of_node) 3041421da89aSPadmavathi Venna of_dma_controller_free(adev->dev.of_node); 3042421da89aSPadmavathi Venna 30430b94c577SPadmavathi Venna dma_async_device_unregister(&pdmac->ddma); 3044b3040e40SJassi Brar amba_set_drvdata(adev, NULL); 3045b3040e40SJassi Brar 3046b3040e40SJassi Brar /* Idle the DMAC */ 3047b3040e40SJassi Brar list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels, 3048b3040e40SJassi Brar chan.device_node) { 3049b3040e40SJassi Brar 3050b3040e40SJassi Brar /* Remove the channel */ 3051b3040e40SJassi Brar list_del(&pch->chan.device_node); 3052b3040e40SJassi Brar 3053b3040e40SJassi Brar /* Flush the channel */ 3054b3040e40SJassi Brar pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); 3055b3040e40SJassi Brar pl330_free_chan_resources(&pch->chan); 3056b3040e40SJassi Brar } 3057b3040e40SJassi Brar 3058b3040e40SJassi Brar pi = &pdmac->pif; 3059b3040e40SJassi Brar 3060b3040e40SJassi Brar pl330_del(pi); 3061b3040e40SJassi Brar 3062b3040e40SJassi Brar irq = adev->irq[0]; 3063b3040e40SJassi Brar free_irq(irq, pi); 3064b3040e40SJassi Brar 3065b3040e40SJassi Brar return 0; 3066b3040e40SJassi Brar } 3067b3040e40SJassi Brar 3068b3040e40SJassi Brar static struct amba_id pl330_ids[] = { 3069b3040e40SJassi Brar { 3070b3040e40SJassi Brar .id = 0x00041330, 3071b3040e40SJassi Brar .mask = 0x000fffff, 3072b3040e40SJassi Brar }, 3073b3040e40SJassi Brar { 0, 0 }, 3074b3040e40SJassi Brar }; 3075b3040e40SJassi Brar 3076e8fa516aSDave Martin MODULE_DEVICE_TABLE(amba, pl330_ids); 3077e8fa516aSDave Martin 3078b3040e40SJassi Brar static struct amba_driver pl330_driver = { 3079b3040e40SJassi Brar .drv = { 3080b3040e40SJassi Brar .owner = THIS_MODULE, 3081b3040e40SJassi Brar .name = "dma-pl330", 3082b3040e40SJassi Brar }, 3083b3040e40SJassi Brar .id_table = pl330_ids, 3084b3040e40SJassi Brar .probe = pl330_probe, 3085b3040e40SJassi Brar .remove = pl330_remove, 3086b3040e40SJassi Brar }; 3087b3040e40SJassi Brar 30889e5ed094Sviresh kumar module_amba_driver(pl330_driver); 3089b3040e40SJassi Brar 3090b3040e40SJassi Brar MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); 3091b3040e40SJassi Brar MODULE_DESCRIPTION("API Driver for PL330 DMAC"); 3092b3040e40SJassi Brar MODULE_LICENSE("GPL"); 3093