12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2b7d861d9SBoojin Kim /* 3b7d861d9SBoojin Kim * Copyright (c) 2012 Samsung Electronics Co., Ltd. 4b7d861d9SBoojin Kim * http://www.samsung.com 5b3040e40SJassi Brar * 6b3040e40SJassi Brar * Copyright (C) 2010 Samsung Electronics Co. Ltd. 7b3040e40SJassi Brar * Jaswinder Singh <jassi.brar@samsung.com> 8b3040e40SJassi Brar */ 9b3040e40SJassi Brar 10b45aef3aSKatsuhiro Suzuki #include <linux/debugfs.h> 11b7d861d9SBoojin Kim #include <linux/kernel.h> 12b3040e40SJassi Brar #include <linux/io.h> 13b3040e40SJassi Brar #include <linux/init.h> 14b3040e40SJassi Brar #include <linux/slab.h> 15b3040e40SJassi Brar #include <linux/module.h> 16b7d861d9SBoojin Kim #include <linux/string.h> 17b7d861d9SBoojin Kim #include <linux/delay.h> 18b7d861d9SBoojin Kim #include <linux/interrupt.h> 19b7d861d9SBoojin Kim #include <linux/dma-mapping.h> 20b3040e40SJassi Brar #include <linux/dmaengine.h> 21b3040e40SJassi Brar #include <linux/amba/bus.h> 221b9bb715SBoojin Kim #include <linux/scatterlist.h> 2393ed5544SThomas Abraham #include <linux/of.h> 24a80258f9SPadmavathi Venna #include <linux/of_dma.h> 25bcc7fa95SSachin Kamat #include <linux/err.h> 26ae43b328SKrzysztof Kozlowski #include <linux/pm_runtime.h> 271d48745bSFrank Mori Hess #include <linux/bug.h> 280eaab70aSDinh Nguyen #include <linux/reset.h> 29b3040e40SJassi Brar 30d2ebfb33SRussell King - ARM Linux #include "dmaengine.h" 31b7d861d9SBoojin Kim #define PL330_MAX_CHAN 8 32b7d861d9SBoojin Kim #define PL330_MAX_IRQS 32 33b7d861d9SBoojin Kim #define PL330_MAX_PERI 32 3486a8ce7dSShawn Lin #define PL330_MAX_BURST 16 35b7d861d9SBoojin Kim 36271e1b86SAddy Ke #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0) 375fb9e3a3SSugar Zhang #define PL330_QUIRK_PERIPH_BURST BIT(1) 38271e1b86SAddy Ke 39f0564c7eSLars-Peter Clausen enum pl330_cachectrl { 40f0564c7eSLars-Peter Clausen CCTRL0, /* Noncacheable and nonbufferable */ 41f0564c7eSLars-Peter Clausen CCTRL1, /* Bufferable only */ 42f0564c7eSLars-Peter Clausen CCTRL2, /* Cacheable, but do not allocate */ 43f0564c7eSLars-Peter Clausen CCTRL3, /* Cacheable and bufferable, but do not allocate */ 44f0564c7eSLars-Peter Clausen INVALID1, /* AWCACHE = 0x1000 */ 45f0564c7eSLars-Peter Clausen INVALID2, 46f0564c7eSLars-Peter Clausen CCTRL6, /* Cacheable write-through, allocate on writes only */ 47f0564c7eSLars-Peter Clausen CCTRL7, /* Cacheable write-back, allocate on writes only */ 48b7d861d9SBoojin Kim }; 49b7d861d9SBoojin Kim 50b7d861d9SBoojin Kim enum pl330_byteswap { 51b7d861d9SBoojin Kim SWAP_NO, 52b7d861d9SBoojin Kim SWAP_2, 53b7d861d9SBoojin Kim SWAP_4, 54b7d861d9SBoojin Kim SWAP_8, 55b7d861d9SBoojin Kim SWAP_16, 56b7d861d9SBoojin Kim }; 57b7d861d9SBoojin Kim 58b7d861d9SBoojin Kim /* Register and Bit field Definitions */ 59b7d861d9SBoojin Kim #define DS 0x0 60b7d861d9SBoojin Kim #define DS_ST_STOP 0x0 61b7d861d9SBoojin Kim #define DS_ST_EXEC 0x1 62b7d861d9SBoojin Kim #define DS_ST_CMISS 0x2 63b7d861d9SBoojin Kim #define DS_ST_UPDTPC 0x3 64b7d861d9SBoojin Kim #define DS_ST_WFE 0x4 65b7d861d9SBoojin Kim #define DS_ST_ATBRR 0x5 66b7d861d9SBoojin Kim #define DS_ST_QBUSY 0x6 67b7d861d9SBoojin Kim #define DS_ST_WFP 0x7 68b7d861d9SBoojin Kim #define DS_ST_KILL 0x8 69b7d861d9SBoojin Kim #define DS_ST_CMPLT 0x9 70b7d861d9SBoojin Kim #define DS_ST_FLTCMP 0xe 71b7d861d9SBoojin Kim #define DS_ST_FAULT 0xf 72b7d861d9SBoojin Kim 73b7d861d9SBoojin Kim #define DPC 0x4 74b7d861d9SBoojin Kim #define INTEN 0x20 75b7d861d9SBoojin Kim #define ES 0x24 76b7d861d9SBoojin Kim #define INTSTATUS 0x28 77b7d861d9SBoojin Kim #define INTCLR 0x2c 78b7d861d9SBoojin Kim #define FSM 0x30 79b7d861d9SBoojin Kim #define FSC 0x34 80b7d861d9SBoojin Kim #define FTM 0x38 81b7d861d9SBoojin Kim 82b7d861d9SBoojin Kim #define _FTC 0x40 83b7d861d9SBoojin Kim #define FTC(n) (_FTC + (n)*0x4) 84b7d861d9SBoojin Kim 85b7d861d9SBoojin Kim #define _CS 0x100 86b7d861d9SBoojin Kim #define CS(n) (_CS + (n)*0x8) 87b7d861d9SBoojin Kim #define CS_CNS (1 << 21) 88b7d861d9SBoojin Kim 89b7d861d9SBoojin Kim #define _CPC 0x104 90b7d861d9SBoojin Kim #define CPC(n) (_CPC + (n)*0x8) 91b7d861d9SBoojin Kim 92b7d861d9SBoojin Kim #define _SA 0x400 93b7d861d9SBoojin Kim #define SA(n) (_SA + (n)*0x20) 94b7d861d9SBoojin Kim 95b7d861d9SBoojin Kim #define _DA 0x404 96b7d861d9SBoojin Kim #define DA(n) (_DA + (n)*0x20) 97b7d861d9SBoojin Kim 98b7d861d9SBoojin Kim #define _CC 0x408 99b7d861d9SBoojin Kim #define CC(n) (_CC + (n)*0x20) 100b7d861d9SBoojin Kim 101b7d861d9SBoojin Kim #define CC_SRCINC (1 << 0) 102b7d861d9SBoojin Kim #define CC_DSTINC (1 << 14) 103b7d861d9SBoojin Kim #define CC_SRCPRI (1 << 8) 104b7d861d9SBoojin Kim #define CC_DSTPRI (1 << 22) 105b7d861d9SBoojin Kim #define CC_SRCNS (1 << 9) 106b7d861d9SBoojin Kim #define CC_DSTNS (1 << 23) 107b7d861d9SBoojin Kim #define CC_SRCIA (1 << 10) 108b7d861d9SBoojin Kim #define CC_DSTIA (1 << 24) 109b7d861d9SBoojin Kim #define CC_SRCBRSTLEN_SHFT 4 110b7d861d9SBoojin Kim #define CC_DSTBRSTLEN_SHFT 18 111b7d861d9SBoojin Kim #define CC_SRCBRSTSIZE_SHFT 1 112b7d861d9SBoojin Kim #define CC_DSTBRSTSIZE_SHFT 15 113b7d861d9SBoojin Kim #define CC_SRCCCTRL_SHFT 11 114b7d861d9SBoojin Kim #define CC_SRCCCTRL_MASK 0x7 115b7d861d9SBoojin Kim #define CC_DSTCCTRL_SHFT 25 116b7d861d9SBoojin Kim #define CC_DRCCCTRL_MASK 0x7 117b7d861d9SBoojin Kim #define CC_SWAP_SHFT 28 118b7d861d9SBoojin Kim 119b7d861d9SBoojin Kim #define _LC0 0x40c 120b7d861d9SBoojin Kim #define LC0(n) (_LC0 + (n)*0x20) 121b7d861d9SBoojin Kim 122b7d861d9SBoojin Kim #define _LC1 0x410 123b7d861d9SBoojin Kim #define LC1(n) (_LC1 + (n)*0x20) 124b7d861d9SBoojin Kim 125b7d861d9SBoojin Kim #define DBGSTATUS 0xd00 126b7d861d9SBoojin Kim #define DBG_BUSY (1 << 0) 127b7d861d9SBoojin Kim 128b7d861d9SBoojin Kim #define DBGCMD 0xd04 129b7d861d9SBoojin Kim #define DBGINST0 0xd08 130b7d861d9SBoojin Kim #define DBGINST1 0xd0c 131b7d861d9SBoojin Kim 132b7d861d9SBoojin Kim #define CR0 0xe00 133b7d861d9SBoojin Kim #define CR1 0xe04 134b7d861d9SBoojin Kim #define CR2 0xe08 135b7d861d9SBoojin Kim #define CR3 0xe0c 136b7d861d9SBoojin Kim #define CR4 0xe10 137b7d861d9SBoojin Kim #define CRD 0xe14 138b7d861d9SBoojin Kim 139b7d861d9SBoojin Kim #define PERIPH_ID 0xfe0 1403ecf51a4SBoojin Kim #define PERIPH_REV_SHIFT 20 1413ecf51a4SBoojin Kim #define PERIPH_REV_MASK 0xf 1423ecf51a4SBoojin Kim #define PERIPH_REV_R0P0 0 1433ecf51a4SBoojin Kim #define PERIPH_REV_R1P0 1 1443ecf51a4SBoojin Kim #define PERIPH_REV_R1P1 2 145b7d861d9SBoojin Kim 146b7d861d9SBoojin Kim #define CR0_PERIPH_REQ_SET (1 << 0) 147b7d861d9SBoojin Kim #define CR0_BOOT_EN_SET (1 << 1) 148b7d861d9SBoojin Kim #define CR0_BOOT_MAN_NS (1 << 2) 149b7d861d9SBoojin Kim #define CR0_NUM_CHANS_SHIFT 4 150b7d861d9SBoojin Kim #define CR0_NUM_CHANS_MASK 0x7 151b7d861d9SBoojin Kim #define CR0_NUM_PERIPH_SHIFT 12 152b7d861d9SBoojin Kim #define CR0_NUM_PERIPH_MASK 0x1f 153b7d861d9SBoojin Kim #define CR0_NUM_EVENTS_SHIFT 17 154b7d861d9SBoojin Kim #define CR0_NUM_EVENTS_MASK 0x1f 155b7d861d9SBoojin Kim 156b7d861d9SBoojin Kim #define CR1_ICACHE_LEN_SHIFT 0 157b7d861d9SBoojin Kim #define CR1_ICACHE_LEN_MASK 0x7 158b7d861d9SBoojin Kim #define CR1_NUM_ICACHELINES_SHIFT 4 159b7d861d9SBoojin Kim #define CR1_NUM_ICACHELINES_MASK 0xf 160b7d861d9SBoojin Kim 161b7d861d9SBoojin Kim #define CRD_DATA_WIDTH_SHIFT 0 162b7d861d9SBoojin Kim #define CRD_DATA_WIDTH_MASK 0x7 163b7d861d9SBoojin Kim #define CRD_WR_CAP_SHIFT 4 164b7d861d9SBoojin Kim #define CRD_WR_CAP_MASK 0x7 165b7d861d9SBoojin Kim #define CRD_WR_Q_DEP_SHIFT 8 166b7d861d9SBoojin Kim #define CRD_WR_Q_DEP_MASK 0xf 167b7d861d9SBoojin Kim #define CRD_RD_CAP_SHIFT 12 168b7d861d9SBoojin Kim #define CRD_RD_CAP_MASK 0x7 169b7d861d9SBoojin Kim #define CRD_RD_Q_DEP_SHIFT 16 170b7d861d9SBoojin Kim #define CRD_RD_Q_DEP_MASK 0xf 171b7d861d9SBoojin Kim #define CRD_DATA_BUFF_SHIFT 20 172b7d861d9SBoojin Kim #define CRD_DATA_BUFF_MASK 0x3ff 173b7d861d9SBoojin Kim 174b7d861d9SBoojin Kim #define PART 0x330 175b7d861d9SBoojin Kim #define DESIGNER 0x41 176b7d861d9SBoojin Kim #define REVISION 0x0 177b7d861d9SBoojin Kim #define INTEG_CFG 0x0 178b7d861d9SBoojin Kim #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) 179b7d861d9SBoojin Kim 180b7d861d9SBoojin Kim #define PL330_STATE_STOPPED (1 << 0) 181b7d861d9SBoojin Kim #define PL330_STATE_EXECUTING (1 << 1) 182b7d861d9SBoojin Kim #define PL330_STATE_WFE (1 << 2) 183b7d861d9SBoojin Kim #define PL330_STATE_FAULTING (1 << 3) 184b7d861d9SBoojin Kim #define PL330_STATE_COMPLETING (1 << 4) 185b7d861d9SBoojin Kim #define PL330_STATE_WFP (1 << 5) 186b7d861d9SBoojin Kim #define PL330_STATE_KILLING (1 << 6) 187b7d861d9SBoojin Kim #define PL330_STATE_FAULT_COMPLETING (1 << 7) 188b7d861d9SBoojin Kim #define PL330_STATE_CACHEMISS (1 << 8) 189b7d861d9SBoojin Kim #define PL330_STATE_UPDTPC (1 << 9) 190b7d861d9SBoojin Kim #define PL330_STATE_ATBARRIER (1 << 10) 191b7d861d9SBoojin Kim #define PL330_STATE_QUEUEBUSY (1 << 11) 192b7d861d9SBoojin Kim #define PL330_STATE_INVALID (1 << 15) 193b7d861d9SBoojin Kim 194b7d861d9SBoojin Kim #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ 195b7d861d9SBoojin Kim | PL330_STATE_WFE | PL330_STATE_FAULTING) 196b7d861d9SBoojin Kim 197b7d861d9SBoojin Kim #define CMD_DMAADDH 0x54 198b7d861d9SBoojin Kim #define CMD_DMAEND 0x00 199b7d861d9SBoojin Kim #define CMD_DMAFLUSHP 0x35 200b7d861d9SBoojin Kim #define CMD_DMAGO 0xa0 201b7d861d9SBoojin Kim #define CMD_DMALD 0x04 202b7d861d9SBoojin Kim #define CMD_DMALDP 0x25 203b7d861d9SBoojin Kim #define CMD_DMALP 0x20 204b7d861d9SBoojin Kim #define CMD_DMALPEND 0x28 205b7d861d9SBoojin Kim #define CMD_DMAKILL 0x01 206b7d861d9SBoojin Kim #define CMD_DMAMOV 0xbc 207b7d861d9SBoojin Kim #define CMD_DMANOP 0x18 208b7d861d9SBoojin Kim #define CMD_DMARMB 0x12 209b7d861d9SBoojin Kim #define CMD_DMASEV 0x34 210b7d861d9SBoojin Kim #define CMD_DMAST 0x08 211b7d861d9SBoojin Kim #define CMD_DMASTP 0x29 212b7d861d9SBoojin Kim #define CMD_DMASTZ 0x0c 213b7d861d9SBoojin Kim #define CMD_DMAWFE 0x36 214b7d861d9SBoojin Kim #define CMD_DMAWFP 0x30 215b7d861d9SBoojin Kim #define CMD_DMAWMB 0x13 216b7d861d9SBoojin Kim 217b7d861d9SBoojin Kim #define SZ_DMAADDH 3 218b7d861d9SBoojin Kim #define SZ_DMAEND 1 219b7d861d9SBoojin Kim #define SZ_DMAFLUSHP 2 220b7d861d9SBoojin Kim #define SZ_DMALD 1 221b7d861d9SBoojin Kim #define SZ_DMALDP 2 222b7d861d9SBoojin Kim #define SZ_DMALP 2 223b7d861d9SBoojin Kim #define SZ_DMALPEND 2 224b7d861d9SBoojin Kim #define SZ_DMAKILL 1 225b7d861d9SBoojin Kim #define SZ_DMAMOV 6 226b7d861d9SBoojin Kim #define SZ_DMANOP 1 227b7d861d9SBoojin Kim #define SZ_DMARMB 1 228b7d861d9SBoojin Kim #define SZ_DMASEV 2 229b7d861d9SBoojin Kim #define SZ_DMAST 1 230b7d861d9SBoojin Kim #define SZ_DMASTP 2 231b7d861d9SBoojin Kim #define SZ_DMASTZ 1 232b7d861d9SBoojin Kim #define SZ_DMAWFE 2 233b7d861d9SBoojin Kim #define SZ_DMAWFP 2 234b7d861d9SBoojin Kim #define SZ_DMAWMB 1 235b7d861d9SBoojin Kim #define SZ_DMAGO 6 236b7d861d9SBoojin Kim 237b7d861d9SBoojin Kim #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) 238b7d861d9SBoojin Kim #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) 239b7d861d9SBoojin Kim 240b7d861d9SBoojin Kim #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) 241b7d861d9SBoojin Kim #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) 242b7d861d9SBoojin Kim 243b7d861d9SBoojin Kim /* 244b7d861d9SBoojin Kim * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req 245b7d861d9SBoojin Kim * at 1byte/burst for P<->M and M<->M respectively. 246b7d861d9SBoojin Kim * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req 247b7d861d9SBoojin Kim * should be enough for P<->M and M<->M respectively. 248b7d861d9SBoojin Kim */ 249b7d861d9SBoojin Kim #define MCODE_BUFF_PER_REQ 256 250b7d861d9SBoojin Kim 251b7d861d9SBoojin Kim /* Use this _only_ to wait on transient states */ 252b7d861d9SBoojin Kim #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); 253b7d861d9SBoojin Kim 254b7d861d9SBoojin Kim #ifdef PL330_DEBUG_MCGEN 255b7d861d9SBoojin Kim static unsigned cmd_line; 256b7d861d9SBoojin Kim #define PL330_DBGCMD_DUMP(off, x...) do { \ 257b7d861d9SBoojin Kim printk("%x:", cmd_line); \ 258112ec61bSŁukasz Stelmach printk(KERN_CONT x); \ 259b7d861d9SBoojin Kim cmd_line += off; \ 260b7d861d9SBoojin Kim } while (0) 261b7d861d9SBoojin Kim #define PL330_DBGMC_START(addr) (cmd_line = addr) 262b7d861d9SBoojin Kim #else 263b7d861d9SBoojin Kim #define PL330_DBGCMD_DUMP(off, x...) do {} while (0) 264b7d861d9SBoojin Kim #define PL330_DBGMC_START(addr) do {} while (0) 265b7d861d9SBoojin Kim #endif 266b7d861d9SBoojin Kim 267b7d861d9SBoojin Kim /* The number of default descriptors */ 268d2ebfb33SRussell King - ARM Linux 269b3040e40SJassi Brar #define NR_DEFAULT_DESC 16 270b3040e40SJassi Brar 271ae43b328SKrzysztof Kozlowski /* Delay for runtime PM autosuspend, ms */ 272ae43b328SKrzysztof Kozlowski #define PL330_AUTOSUSPEND_DELAY 20 273ae43b328SKrzysztof Kozlowski 274b7d861d9SBoojin Kim /* Populated by the PL330 core driver for DMA API driver's info */ 275b7d861d9SBoojin Kim struct pl330_config { 276b7d861d9SBoojin Kim u32 periph_id; 277b7d861d9SBoojin Kim #define DMAC_MODE_NS (1 << 0) 278b7d861d9SBoojin Kim unsigned int mode; 279b7d861d9SBoojin Kim unsigned int data_bus_width:10; /* In number of bits */ 2801f0a5cbfSLiviu Dudau unsigned int data_buf_dep:11; 281b7d861d9SBoojin Kim unsigned int num_chan:4; 282b7d861d9SBoojin Kim unsigned int num_peri:6; 283b7d861d9SBoojin Kim u32 peri_ns; 284b7d861d9SBoojin Kim unsigned int num_events:6; 285b7d861d9SBoojin Kim u32 irq_ns; 286b7d861d9SBoojin Kim }; 287b7d861d9SBoojin Kim 288f9e036dfSLee Jones /* 289b7d861d9SBoojin Kim * Request Configuration. 290b7d861d9SBoojin Kim * The PL330 core does not modify this and uses the last 291b7d861d9SBoojin Kim * working configuration if the request doesn't provide any. 292b7d861d9SBoojin Kim * 293b7d861d9SBoojin Kim * The Client may want to provide this info only for the 294b7d861d9SBoojin Kim * first request and a request with new settings. 295b7d861d9SBoojin Kim */ 296b7d861d9SBoojin Kim struct pl330_reqcfg { 297b7d861d9SBoojin Kim /* Address Incrementing */ 298b7d861d9SBoojin Kim unsigned dst_inc:1; 299b7d861d9SBoojin Kim unsigned src_inc:1; 300b7d861d9SBoojin Kim 301b7d861d9SBoojin Kim /* 302b7d861d9SBoojin Kim * For now, the SRC & DST protection levels 303b7d861d9SBoojin Kim * and burst size/length are assumed same. 304b7d861d9SBoojin Kim */ 305b7d861d9SBoojin Kim bool nonsecure; 306b7d861d9SBoojin Kim bool privileged; 307b7d861d9SBoojin Kim bool insnaccess; 308b7d861d9SBoojin Kim unsigned brst_len:5; 309b7d861d9SBoojin Kim unsigned brst_size:3; /* in power of 2 */ 310b7d861d9SBoojin Kim 311f0564c7eSLars-Peter Clausen enum pl330_cachectrl dcctl; 312f0564c7eSLars-Peter Clausen enum pl330_cachectrl scctl; 313b7d861d9SBoojin Kim enum pl330_byteswap swap; 3143ecf51a4SBoojin Kim struct pl330_config *pcfg; 315b7d861d9SBoojin Kim }; 316b7d861d9SBoojin Kim 317b7d861d9SBoojin Kim /* 318b7d861d9SBoojin Kim * One cycle of DMAC operation. 319b7d861d9SBoojin Kim * There may be more than one xfer in a request. 320b7d861d9SBoojin Kim */ 321b7d861d9SBoojin Kim struct pl330_xfer { 322b7d861d9SBoojin Kim u32 src_addr; 323b7d861d9SBoojin Kim u32 dst_addr; 324b7d861d9SBoojin Kim /* Size to xfer */ 325b7d861d9SBoojin Kim u32 bytes; 326b7d861d9SBoojin Kim }; 327b7d861d9SBoojin Kim 328b7d861d9SBoojin Kim /* The xfer callbacks are made with one of these arguments. */ 329b7d861d9SBoojin Kim enum pl330_op_err { 330b7d861d9SBoojin Kim /* The all xfers in the request were success. */ 331b7d861d9SBoojin Kim PL330_ERR_NONE, 332b7d861d9SBoojin Kim /* If req aborted due to global error. */ 333b7d861d9SBoojin Kim PL330_ERR_ABORT, 334b7d861d9SBoojin Kim /* If req failed due to problem with Channel. */ 335b7d861d9SBoojin Kim PL330_ERR_FAIL, 336b7d861d9SBoojin Kim }; 337b7d861d9SBoojin Kim 338b7d861d9SBoojin Kim enum dmamov_dst { 339b7d861d9SBoojin Kim SAR = 0, 340b7d861d9SBoojin Kim CCR, 341b7d861d9SBoojin Kim DAR, 342b7d861d9SBoojin Kim }; 343b7d861d9SBoojin Kim 344b7d861d9SBoojin Kim enum pl330_dst { 345b7d861d9SBoojin Kim SRC = 0, 346b7d861d9SBoojin Kim DST, 347b7d861d9SBoojin Kim }; 348b7d861d9SBoojin Kim 349b7d861d9SBoojin Kim enum pl330_cond { 350b7d861d9SBoojin Kim SINGLE, 351b7d861d9SBoojin Kim BURST, 352b7d861d9SBoojin Kim ALWAYS, 353b7d861d9SBoojin Kim }; 354b7d861d9SBoojin Kim 3559dc5a315SLars-Peter Clausen struct dma_pl330_desc; 3569dc5a315SLars-Peter Clausen 357b7d861d9SBoojin Kim struct _pl330_req { 358b7d861d9SBoojin Kim u32 mc_bus; 359b7d861d9SBoojin Kim void *mc_cpu; 3609dc5a315SLars-Peter Clausen struct dma_pl330_desc *desc; 361b7d861d9SBoojin Kim }; 362b7d861d9SBoojin Kim 363b7d861d9SBoojin Kim /* ToBeDone for tasklet */ 364b7d861d9SBoojin Kim struct _pl330_tbd { 365b7d861d9SBoojin Kim bool reset_dmac; 366b7d861d9SBoojin Kim bool reset_mngr; 367b7d861d9SBoojin Kim u8 reset_chan; 368b7d861d9SBoojin Kim }; 369b7d861d9SBoojin Kim 370b7d861d9SBoojin Kim /* A DMAC Thread */ 371b7d861d9SBoojin Kim struct pl330_thread { 372b7d861d9SBoojin Kim u8 id; 373b7d861d9SBoojin Kim int ev; 374b7d861d9SBoojin Kim /* If the channel is not yet acquired by any client */ 375b7d861d9SBoojin Kim bool free; 376b7d861d9SBoojin Kim /* Parent DMAC */ 377b7d861d9SBoojin Kim struct pl330_dmac *dmac; 378b7d861d9SBoojin Kim /* Only two at a time */ 379b7d861d9SBoojin Kim struct _pl330_req req[2]; 380b7d861d9SBoojin Kim /* Index of the last enqueued request */ 381b7d861d9SBoojin Kim unsigned lstenq; 382b7d861d9SBoojin Kim /* Index of the last submitted request or -1 if the DMA is stopped */ 383b7d861d9SBoojin Kim int req_running; 384b7d861d9SBoojin Kim }; 385b7d861d9SBoojin Kim 386b7d861d9SBoojin Kim enum pl330_dmac_state { 387b7d861d9SBoojin Kim UNINIT, 388b7d861d9SBoojin Kim INIT, 389b7d861d9SBoojin Kim DYING, 390b7d861d9SBoojin Kim }; 391b7d861d9SBoojin Kim 392b3040e40SJassi Brar enum desc_status { 393b3040e40SJassi Brar /* In the DMAC pool */ 394b3040e40SJassi Brar FREE, 395b3040e40SJassi Brar /* 396d73111c6SMasanari Iida * Allocated to some channel during prep_xxx 397b3040e40SJassi Brar * Also may be sitting on the work_list. 398b3040e40SJassi Brar */ 399b3040e40SJassi Brar PREP, 400b3040e40SJassi Brar /* 401b3040e40SJassi Brar * Sitting on the work_list and already submitted 402b3040e40SJassi Brar * to the PL330 core. Not more than two descriptors 403b3040e40SJassi Brar * of a channel can be BUSY at any time. 404b3040e40SJassi Brar */ 405b3040e40SJassi Brar BUSY, 406b3040e40SJassi Brar /* 407b3040e40SJassi Brar * Sitting on the channel work_list but xfer done 408b3040e40SJassi Brar * by PL330 core 409b3040e40SJassi Brar */ 410b3040e40SJassi Brar DONE, 411b3040e40SJassi Brar }; 412b3040e40SJassi Brar 413b3040e40SJassi Brar struct dma_pl330_chan { 414b3040e40SJassi Brar /* Schedule desc completion */ 415b3040e40SJassi Brar struct tasklet_struct task; 416b3040e40SJassi Brar 417b3040e40SJassi Brar /* DMA-Engine Channel */ 418b3040e40SJassi Brar struct dma_chan chan; 419b3040e40SJassi Brar 42004abf5daSLars-Peter Clausen /* List of submitted descriptors */ 42104abf5daSLars-Peter Clausen struct list_head submitted_list; 42204abf5daSLars-Peter Clausen /* List of issued descriptors */ 423b3040e40SJassi Brar struct list_head work_list; 42439ff8613SLars-Peter Clausen /* List of completed descriptors */ 42539ff8613SLars-Peter Clausen struct list_head completed_list; 426b3040e40SJassi Brar 427b3040e40SJassi Brar /* Pointer to the DMAC that manages this channel, 428b3040e40SJassi Brar * NULL if the channel is available to be acquired. 429b3040e40SJassi Brar * As the parent, this DMAC also provides descriptors 430b3040e40SJassi Brar * to the channel. 431b3040e40SJassi Brar */ 432f6f2421cSLars-Peter Clausen struct pl330_dmac *dmac; 433b3040e40SJassi Brar 434b3040e40SJassi Brar /* To protect channel manipulation */ 435b3040e40SJassi Brar spinlock_t lock; 436b3040e40SJassi Brar 43765ad6060SLars-Peter Clausen /* 43865ad6060SLars-Peter Clausen * Hardware channel thread of PL330 DMAC. NULL if the channel is 43965ad6060SLars-Peter Clausen * available. 440b3040e40SJassi Brar */ 44165ad6060SLars-Peter Clausen struct pl330_thread *thread; 4421b9bb715SBoojin Kim 4431b9bb715SBoojin Kim /* For D-to-M and M-to-D channels */ 4441b9bb715SBoojin Kim int burst_sz; /* the peripheral fifo width */ 4451d0c1d60SBoojin Kim int burst_len; /* the number of burst */ 4464d6d74e2SRobin Murphy phys_addr_t fifo_addr; 4474d6d74e2SRobin Murphy /* DMA-mapped view of the FIFO; may differ if an IOMMU is present */ 4484d6d74e2SRobin Murphy dma_addr_t fifo_dma; 4494d6d74e2SRobin Murphy enum dma_data_direction dir; 450445897cbSVinod Koul struct dma_slave_config slave_config; 45142bc9cf4SBoojin Kim 45242bc9cf4SBoojin Kim /* for cyclic capability */ 45342bc9cf4SBoojin Kim bool cyclic; 4545c9e6c2bSMarek Szyprowski 4555c9e6c2bSMarek Szyprowski /* for runtime pm tracking */ 4565c9e6c2bSMarek Szyprowski bool active; 457b3040e40SJassi Brar }; 458b3040e40SJassi Brar 459f6f2421cSLars-Peter Clausen struct pl330_dmac { 460b3040e40SJassi Brar /* DMA-Engine Device */ 461b3040e40SJassi Brar struct dma_device ddma; 462b3040e40SJassi Brar 463b3040e40SJassi Brar /* Pool of descriptors available for the DMAC's channels */ 464b3040e40SJassi Brar struct list_head desc_pool; 465b3040e40SJassi Brar /* To protect desc_pool manipulation */ 466b3040e40SJassi Brar spinlock_t pool_lock; 467b3040e40SJassi Brar 468f6f2421cSLars-Peter Clausen /* Size of MicroCode buffers for each channel. */ 469f6f2421cSLars-Peter Clausen unsigned mcbufsz; 470f6f2421cSLars-Peter Clausen /* ioremap'ed address of PL330 registers. */ 471f6f2421cSLars-Peter Clausen void __iomem *base; 472f6f2421cSLars-Peter Clausen /* Populated by the PL330 core driver during pl330_add */ 473f6f2421cSLars-Peter Clausen struct pl330_config pcfg; 474f6f2421cSLars-Peter Clausen 475f6f2421cSLars-Peter Clausen spinlock_t lock; 476f6f2421cSLars-Peter Clausen /* Maximum possible events/irqs */ 477f6f2421cSLars-Peter Clausen int events[32]; 478f6f2421cSLars-Peter Clausen /* BUS address of MicroCode buffer */ 479f6f2421cSLars-Peter Clausen dma_addr_t mcode_bus; 480f6f2421cSLars-Peter Clausen /* CPU address of MicroCode buffer */ 481f6f2421cSLars-Peter Clausen void *mcode_cpu; 482f6f2421cSLars-Peter Clausen /* List of all Channel threads */ 483f6f2421cSLars-Peter Clausen struct pl330_thread *channels; 484f6f2421cSLars-Peter Clausen /* Pointer to the MANAGER thread */ 485f6f2421cSLars-Peter Clausen struct pl330_thread *manager; 486f6f2421cSLars-Peter Clausen /* To handle bad news in interrupt */ 487f6f2421cSLars-Peter Clausen struct tasklet_struct tasks; 488f6f2421cSLars-Peter Clausen struct _pl330_tbd dmac_tbd; 489f6f2421cSLars-Peter Clausen /* State of DMAC operation */ 490f6f2421cSLars-Peter Clausen enum pl330_dmac_state state; 491f6f2421cSLars-Peter Clausen /* Holds list of reqs with due callbacks */ 492f6f2421cSLars-Peter Clausen struct list_head req_done; 493f6f2421cSLars-Peter Clausen 494b3040e40SJassi Brar /* Peripheral channels connected to this DMAC */ 49570cbb163SLars-Peter Clausen unsigned int num_peripherals; 4964e0e6109SRob Herring struct dma_pl330_chan *peripherals; /* keep at end */ 497271e1b86SAddy Ke int quirks; 4980eaab70aSDinh Nguyen 4990eaab70aSDinh Nguyen struct reset_control *rstc; 5000eaab70aSDinh Nguyen struct reset_control *rstc_ocp; 501271e1b86SAddy Ke }; 502271e1b86SAddy Ke 503271e1b86SAddy Ke static struct pl330_of_quirks { 504271e1b86SAddy Ke char *quirk; 505271e1b86SAddy Ke int id; 506271e1b86SAddy Ke } of_quirks[] = { 507271e1b86SAddy Ke { 508271e1b86SAddy Ke .quirk = "arm,pl330-broken-no-flushp", 509271e1b86SAddy Ke .id = PL330_QUIRK_BROKEN_NO_FLUSHP, 5105fb9e3a3SSugar Zhang }, 5115fb9e3a3SSugar Zhang { 5125fb9e3a3SSugar Zhang .quirk = "arm,pl330-periph-burst", 5135fb9e3a3SSugar Zhang .id = PL330_QUIRK_PERIPH_BURST, 514271e1b86SAddy Ke } 515b3040e40SJassi Brar }; 516b3040e40SJassi Brar 517b3040e40SJassi Brar struct dma_pl330_desc { 518b3040e40SJassi Brar /* To attach to a queue as child */ 519b3040e40SJassi Brar struct list_head node; 520b3040e40SJassi Brar 521b3040e40SJassi Brar /* Descriptor for the DMA Engine API */ 522b3040e40SJassi Brar struct dma_async_tx_descriptor txd; 523b3040e40SJassi Brar 524b3040e40SJassi Brar /* Xfer for PL330 core */ 525b3040e40SJassi Brar struct pl330_xfer px; 526b3040e40SJassi Brar 527b3040e40SJassi Brar struct pl330_reqcfg rqcfg; 528b3040e40SJassi Brar 529b3040e40SJassi Brar enum desc_status status; 530b3040e40SJassi Brar 531aee4d1faSRobert Baldyga int bytes_requested; 532aee4d1faSRobert Baldyga bool last; 533aee4d1faSRobert Baldyga 534b3040e40SJassi Brar /* The channel which currently holds this desc */ 535b3040e40SJassi Brar struct dma_pl330_chan *pchan; 5369dc5a315SLars-Peter Clausen 5379dc5a315SLars-Peter Clausen enum dma_transfer_direction rqtype; 5389dc5a315SLars-Peter Clausen /* Index of peripheral for the xfer. */ 5399dc5a315SLars-Peter Clausen unsigned peri:5; 5409dc5a315SLars-Peter Clausen /* Hook to attach to DMAC's list of reqs with due callback */ 5419dc5a315SLars-Peter Clausen struct list_head rqd; 5429dc5a315SLars-Peter Clausen }; 5439dc5a315SLars-Peter Clausen 5449dc5a315SLars-Peter Clausen struct _xfer_spec { 5459dc5a315SLars-Peter Clausen u32 ccr; 5469dc5a315SLars-Peter Clausen struct dma_pl330_desc *desc; 547b3040e40SJassi Brar }; 548b3040e40SJassi Brar 549445897cbSVinod Koul static int pl330_config_write(struct dma_chan *chan, 550445897cbSVinod Koul struct dma_slave_config *slave_config, 551445897cbSVinod Koul enum dma_transfer_direction direction); 552445897cbSVinod Koul 553b7d861d9SBoojin Kim static inline bool _queue_full(struct pl330_thread *thrd) 554b7d861d9SBoojin Kim { 5558ed30a14SLars-Peter Clausen return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL; 556b7d861d9SBoojin Kim } 557b7d861d9SBoojin Kim 558b7d861d9SBoojin Kim static inline bool is_manager(struct pl330_thread *thrd) 559b7d861d9SBoojin Kim { 560fbbcd9beSLars-Peter Clausen return thrd->dmac->manager == thrd; 561b7d861d9SBoojin Kim } 562b7d861d9SBoojin Kim 563b7d861d9SBoojin Kim /* If manager of the thread is in Non-Secure mode */ 564b7d861d9SBoojin Kim static inline bool _manager_ns(struct pl330_thread *thrd) 565b7d861d9SBoojin Kim { 566f6f2421cSLars-Peter Clausen return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false; 567b7d861d9SBoojin Kim } 568b7d861d9SBoojin Kim 5693ecf51a4SBoojin Kim static inline u32 get_revision(u32 periph_id) 5703ecf51a4SBoojin Kim { 5713ecf51a4SBoojin Kim return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; 5723ecf51a4SBoojin Kim } 5733ecf51a4SBoojin Kim 574b7d861d9SBoojin Kim static inline u32 _emit_END(unsigned dry_run, u8 buf[]) 575b7d861d9SBoojin Kim { 576b7d861d9SBoojin Kim if (dry_run) 577b7d861d9SBoojin Kim return SZ_DMAEND; 578b7d861d9SBoojin Kim 579b7d861d9SBoojin Kim buf[0] = CMD_DMAEND; 580b7d861d9SBoojin Kim 581b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); 582b7d861d9SBoojin Kim 583b7d861d9SBoojin Kim return SZ_DMAEND; 584b7d861d9SBoojin Kim } 585b7d861d9SBoojin Kim 586b7d861d9SBoojin Kim static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) 587b7d861d9SBoojin Kim { 588b7d861d9SBoojin Kim if (dry_run) 589b7d861d9SBoojin Kim return SZ_DMAFLUSHP; 590b7d861d9SBoojin Kim 591b7d861d9SBoojin Kim buf[0] = CMD_DMAFLUSHP; 592b7d861d9SBoojin Kim 593b7d861d9SBoojin Kim peri &= 0x1f; 594b7d861d9SBoojin Kim peri <<= 3; 595b7d861d9SBoojin Kim buf[1] = peri; 596b7d861d9SBoojin Kim 597b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); 598b7d861d9SBoojin Kim 599b7d861d9SBoojin Kim return SZ_DMAFLUSHP; 600b7d861d9SBoojin Kim } 601b7d861d9SBoojin Kim 602b7d861d9SBoojin Kim static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) 603b7d861d9SBoojin Kim { 604b7d861d9SBoojin Kim if (dry_run) 605b7d861d9SBoojin Kim return SZ_DMALD; 606b7d861d9SBoojin Kim 607b7d861d9SBoojin Kim buf[0] = CMD_DMALD; 608b7d861d9SBoojin Kim 609b7d861d9SBoojin Kim if (cond == SINGLE) 610b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 611b7d861d9SBoojin Kim else if (cond == BURST) 612b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (1 << 0); 613b7d861d9SBoojin Kim 614b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", 615b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); 616b7d861d9SBoojin Kim 617b7d861d9SBoojin Kim return SZ_DMALD; 618b7d861d9SBoojin Kim } 619b7d861d9SBoojin Kim 620b7d861d9SBoojin Kim static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], 621b7d861d9SBoojin Kim enum pl330_cond cond, u8 peri) 622b7d861d9SBoojin Kim { 623b7d861d9SBoojin Kim if (dry_run) 624b7d861d9SBoojin Kim return SZ_DMALDP; 625b7d861d9SBoojin Kim 626b7d861d9SBoojin Kim buf[0] = CMD_DMALDP; 627b7d861d9SBoojin Kim 628b7d861d9SBoojin Kim if (cond == BURST) 629b7d861d9SBoojin Kim buf[0] |= (1 << 1); 630b7d861d9SBoojin Kim 631b7d861d9SBoojin Kim peri &= 0x1f; 632b7d861d9SBoojin Kim peri <<= 3; 633b7d861d9SBoojin Kim buf[1] = peri; 634b7d861d9SBoojin Kim 635b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", 636b7d861d9SBoojin Kim cond == SINGLE ? 'S' : 'B', peri >> 3); 637b7d861d9SBoojin Kim 638b7d861d9SBoojin Kim return SZ_DMALDP; 639b7d861d9SBoojin Kim } 640b7d861d9SBoojin Kim 641b7d861d9SBoojin Kim static inline u32 _emit_LP(unsigned dry_run, u8 buf[], 642b7d861d9SBoojin Kim unsigned loop, u8 cnt) 643b7d861d9SBoojin Kim { 644b7d861d9SBoojin Kim if (dry_run) 645b7d861d9SBoojin Kim return SZ_DMALP; 646b7d861d9SBoojin Kim 647b7d861d9SBoojin Kim buf[0] = CMD_DMALP; 648b7d861d9SBoojin Kim 649b7d861d9SBoojin Kim if (loop) 650b7d861d9SBoojin Kim buf[0] |= (1 << 1); 651b7d861d9SBoojin Kim 652b7d861d9SBoojin Kim cnt--; /* DMAC increments by 1 internally */ 653b7d861d9SBoojin Kim buf[1] = cnt; 654b7d861d9SBoojin Kim 655b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); 656b7d861d9SBoojin Kim 657b7d861d9SBoojin Kim return SZ_DMALP; 658b7d861d9SBoojin Kim } 659b7d861d9SBoojin Kim 660b7d861d9SBoojin Kim struct _arg_LPEND { 661b7d861d9SBoojin Kim enum pl330_cond cond; 662b7d861d9SBoojin Kim bool forever; 663b7d861d9SBoojin Kim unsigned loop; 664b7d861d9SBoojin Kim u8 bjump; 665b7d861d9SBoojin Kim }; 666b7d861d9SBoojin Kim 667b7d861d9SBoojin Kim static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], 668b7d861d9SBoojin Kim const struct _arg_LPEND *arg) 669b7d861d9SBoojin Kim { 670b7d861d9SBoojin Kim enum pl330_cond cond = arg->cond; 671b7d861d9SBoojin Kim bool forever = arg->forever; 672b7d861d9SBoojin Kim unsigned loop = arg->loop; 673b7d861d9SBoojin Kim u8 bjump = arg->bjump; 674b7d861d9SBoojin Kim 675b7d861d9SBoojin Kim if (dry_run) 676b7d861d9SBoojin Kim return SZ_DMALPEND; 677b7d861d9SBoojin Kim 678b7d861d9SBoojin Kim buf[0] = CMD_DMALPEND; 679b7d861d9SBoojin Kim 680b7d861d9SBoojin Kim if (loop) 681b7d861d9SBoojin Kim buf[0] |= (1 << 2); 682b7d861d9SBoojin Kim 683b7d861d9SBoojin Kim if (!forever) 684b7d861d9SBoojin Kim buf[0] |= (1 << 4); 685b7d861d9SBoojin Kim 686b7d861d9SBoojin Kim if (cond == SINGLE) 687b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 688b7d861d9SBoojin Kim else if (cond == BURST) 689b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (1 << 0); 690b7d861d9SBoojin Kim 691b7d861d9SBoojin Kim buf[1] = bjump; 692b7d861d9SBoojin Kim 693b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", 694b7d861d9SBoojin Kim forever ? "FE" : "END", 695b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), 696b7d861d9SBoojin Kim loop ? '1' : '0', 697b7d861d9SBoojin Kim bjump); 698b7d861d9SBoojin Kim 699b7d861d9SBoojin Kim return SZ_DMALPEND; 700b7d861d9SBoojin Kim } 701b7d861d9SBoojin Kim 702b7d861d9SBoojin Kim static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) 703b7d861d9SBoojin Kim { 704b7d861d9SBoojin Kim if (dry_run) 705b7d861d9SBoojin Kim return SZ_DMAKILL; 706b7d861d9SBoojin Kim 707b7d861d9SBoojin Kim buf[0] = CMD_DMAKILL; 708b7d861d9SBoojin Kim 709b7d861d9SBoojin Kim return SZ_DMAKILL; 710b7d861d9SBoojin Kim } 711b7d861d9SBoojin Kim 712b7d861d9SBoojin Kim static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], 713b7d861d9SBoojin Kim enum dmamov_dst dst, u32 val) 714b7d861d9SBoojin Kim { 715b7d861d9SBoojin Kim if (dry_run) 716b7d861d9SBoojin Kim return SZ_DMAMOV; 717b7d861d9SBoojin Kim 718b7d861d9SBoojin Kim buf[0] = CMD_DMAMOV; 719b7d861d9SBoojin Kim buf[1] = dst; 720d07c9e1eSVladimir Murzin buf[2] = val; 721d07c9e1eSVladimir Murzin buf[3] = val >> 8; 722d07c9e1eSVladimir Murzin buf[4] = val >> 16; 723d07c9e1eSVladimir Murzin buf[5] = val >> 24; 724b7d861d9SBoojin Kim 725b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", 726b7d861d9SBoojin Kim dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); 727b7d861d9SBoojin Kim 728b7d861d9SBoojin Kim return SZ_DMAMOV; 729b7d861d9SBoojin Kim } 730b7d861d9SBoojin Kim 731b7d861d9SBoojin Kim static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) 732b7d861d9SBoojin Kim { 733b7d861d9SBoojin Kim if (dry_run) 734b7d861d9SBoojin Kim return SZ_DMARMB; 735b7d861d9SBoojin Kim 736b7d861d9SBoojin Kim buf[0] = CMD_DMARMB; 737b7d861d9SBoojin Kim 738b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); 739b7d861d9SBoojin Kim 740b7d861d9SBoojin Kim return SZ_DMARMB; 741b7d861d9SBoojin Kim } 742b7d861d9SBoojin Kim 743b7d861d9SBoojin Kim static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) 744b7d861d9SBoojin Kim { 745b7d861d9SBoojin Kim if (dry_run) 746b7d861d9SBoojin Kim return SZ_DMASEV; 747b7d861d9SBoojin Kim 748b7d861d9SBoojin Kim buf[0] = CMD_DMASEV; 749b7d861d9SBoojin Kim 750b7d861d9SBoojin Kim ev &= 0x1f; 751b7d861d9SBoojin Kim ev <<= 3; 752b7d861d9SBoojin Kim buf[1] = ev; 753b7d861d9SBoojin Kim 754b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); 755b7d861d9SBoojin Kim 756b7d861d9SBoojin Kim return SZ_DMASEV; 757b7d861d9SBoojin Kim } 758b7d861d9SBoojin Kim 759b7d861d9SBoojin Kim static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) 760b7d861d9SBoojin Kim { 761b7d861d9SBoojin Kim if (dry_run) 762b7d861d9SBoojin Kim return SZ_DMAST; 763b7d861d9SBoojin Kim 764b7d861d9SBoojin Kim buf[0] = CMD_DMAST; 765b7d861d9SBoojin Kim 766b7d861d9SBoojin Kim if (cond == SINGLE) 767b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 768b7d861d9SBoojin Kim else if (cond == BURST) 769b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (1 << 0); 770b7d861d9SBoojin Kim 771b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", 772b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); 773b7d861d9SBoojin Kim 774b7d861d9SBoojin Kim return SZ_DMAST; 775b7d861d9SBoojin Kim } 776b7d861d9SBoojin Kim 777b7d861d9SBoojin Kim static inline u32 _emit_STP(unsigned dry_run, u8 buf[], 778b7d861d9SBoojin Kim enum pl330_cond cond, u8 peri) 779b7d861d9SBoojin Kim { 780b7d861d9SBoojin Kim if (dry_run) 781b7d861d9SBoojin Kim return SZ_DMASTP; 782b7d861d9SBoojin Kim 783b7d861d9SBoojin Kim buf[0] = CMD_DMASTP; 784b7d861d9SBoojin Kim 785b7d861d9SBoojin Kim if (cond == BURST) 786b7d861d9SBoojin Kim buf[0] |= (1 << 1); 787b7d861d9SBoojin Kim 788b7d861d9SBoojin Kim peri &= 0x1f; 789b7d861d9SBoojin Kim peri <<= 3; 790b7d861d9SBoojin Kim buf[1] = peri; 791b7d861d9SBoojin Kim 792b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", 793b7d861d9SBoojin Kim cond == SINGLE ? 'S' : 'B', peri >> 3); 794b7d861d9SBoojin Kim 795b7d861d9SBoojin Kim return SZ_DMASTP; 796b7d861d9SBoojin Kim } 797b7d861d9SBoojin Kim 798b7d861d9SBoojin Kim static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], 799b7d861d9SBoojin Kim enum pl330_cond cond, u8 peri) 800b7d861d9SBoojin Kim { 801b7d861d9SBoojin Kim if (dry_run) 802b7d861d9SBoojin Kim return SZ_DMAWFP; 803b7d861d9SBoojin Kim 804b7d861d9SBoojin Kim buf[0] = CMD_DMAWFP; 805b7d861d9SBoojin Kim 806b7d861d9SBoojin Kim if (cond == SINGLE) 807b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (0 << 0); 808b7d861d9SBoojin Kim else if (cond == BURST) 809b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (0 << 0); 810b7d861d9SBoojin Kim else 811b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 812b7d861d9SBoojin Kim 813b7d861d9SBoojin Kim peri &= 0x1f; 814b7d861d9SBoojin Kim peri <<= 3; 815b7d861d9SBoojin Kim buf[1] = peri; 816b7d861d9SBoojin Kim 817b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", 818b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); 819b7d861d9SBoojin Kim 820b7d861d9SBoojin Kim return SZ_DMAWFP; 821b7d861d9SBoojin Kim } 822b7d861d9SBoojin Kim 823b7d861d9SBoojin Kim static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) 824b7d861d9SBoojin Kim { 825b7d861d9SBoojin Kim if (dry_run) 826b7d861d9SBoojin Kim return SZ_DMAWMB; 827b7d861d9SBoojin Kim 828b7d861d9SBoojin Kim buf[0] = CMD_DMAWMB; 829b7d861d9SBoojin Kim 830b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); 831b7d861d9SBoojin Kim 832b7d861d9SBoojin Kim return SZ_DMAWMB; 833b7d861d9SBoojin Kim } 834b7d861d9SBoojin Kim 835b7d861d9SBoojin Kim struct _arg_GO { 836b7d861d9SBoojin Kim u8 chan; 837b7d861d9SBoojin Kim u32 addr; 838b7d861d9SBoojin Kim unsigned ns; 839b7d861d9SBoojin Kim }; 840b7d861d9SBoojin Kim 841b7d861d9SBoojin Kim static inline u32 _emit_GO(unsigned dry_run, u8 buf[], 842b7d861d9SBoojin Kim const struct _arg_GO *arg) 843b7d861d9SBoojin Kim { 844b7d861d9SBoojin Kim u8 chan = arg->chan; 845b7d861d9SBoojin Kim u32 addr = arg->addr; 846b7d861d9SBoojin Kim unsigned ns = arg->ns; 847b7d861d9SBoojin Kim 848b7d861d9SBoojin Kim if (dry_run) 849b7d861d9SBoojin Kim return SZ_DMAGO; 850b7d861d9SBoojin Kim 851b7d861d9SBoojin Kim buf[0] = CMD_DMAGO; 852b7d861d9SBoojin Kim buf[0] |= (ns << 1); 853b7d861d9SBoojin Kim buf[1] = chan & 0x7; 854d07c9e1eSVladimir Murzin buf[2] = addr; 855d07c9e1eSVladimir Murzin buf[3] = addr >> 8; 856d07c9e1eSVladimir Murzin buf[4] = addr >> 16; 857d07c9e1eSVladimir Murzin buf[5] = addr >> 24; 858b7d861d9SBoojin Kim 859b7d861d9SBoojin Kim return SZ_DMAGO; 860b7d861d9SBoojin Kim } 861b7d861d9SBoojin Kim 862b7d861d9SBoojin Kim #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 863b7d861d9SBoojin Kim 864b7d861d9SBoojin Kim /* Returns Time-Out */ 865b7d861d9SBoojin Kim static bool _until_dmac_idle(struct pl330_thread *thrd) 866b7d861d9SBoojin Kim { 867f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 868b7d861d9SBoojin Kim unsigned long loops = msecs_to_loops(5); 869b7d861d9SBoojin Kim 870b7d861d9SBoojin Kim do { 871b7d861d9SBoojin Kim /* Until Manager is Idle */ 872b7d861d9SBoojin Kim if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) 873b7d861d9SBoojin Kim break; 874b7d861d9SBoojin Kim 875b7d861d9SBoojin Kim cpu_relax(); 876b7d861d9SBoojin Kim } while (--loops); 877b7d861d9SBoojin Kim 878b7d861d9SBoojin Kim if (!loops) 879b7d861d9SBoojin Kim return true; 880b7d861d9SBoojin Kim 881b7d861d9SBoojin Kim return false; 882b7d861d9SBoojin Kim } 883b7d861d9SBoojin Kim 884b7d861d9SBoojin Kim static inline void _execute_DBGINSN(struct pl330_thread *thrd, 885b7d861d9SBoojin Kim u8 insn[], bool as_manager) 886b7d861d9SBoojin Kim { 887f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 888b7d861d9SBoojin Kim u32 val; 889b7d861d9SBoojin Kim 890d12ea559SSugar Zhang /* If timed out due to halted state-machine */ 891d12ea559SSugar Zhang if (_until_dmac_idle(thrd)) { 892d12ea559SSugar Zhang dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n"); 893d12ea559SSugar Zhang return; 894d12ea559SSugar Zhang } 895d12ea559SSugar Zhang 896b7d861d9SBoojin Kim val = (insn[0] << 16) | (insn[1] << 24); 897b7d861d9SBoojin Kim if (!as_manager) { 898b7d861d9SBoojin Kim val |= (1 << 0); 899b7d861d9SBoojin Kim val |= (thrd->id << 8); /* Channel Number */ 900b7d861d9SBoojin Kim } 901b7d861d9SBoojin Kim writel(val, regs + DBGINST0); 902b7d861d9SBoojin Kim 9033a2307f7SBen Dooks val = le32_to_cpu(*((__le32 *)&insn[2])); 904b7d861d9SBoojin Kim writel(val, regs + DBGINST1); 905b7d861d9SBoojin Kim 906b7d861d9SBoojin Kim /* Get going */ 907b7d861d9SBoojin Kim writel(0, regs + DBGCMD); 908b7d861d9SBoojin Kim } 909b7d861d9SBoojin Kim 910b7d861d9SBoojin Kim static inline u32 _state(struct pl330_thread *thrd) 911b7d861d9SBoojin Kim { 912f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 913b7d861d9SBoojin Kim u32 val; 914b7d861d9SBoojin Kim 915b7d861d9SBoojin Kim if (is_manager(thrd)) 916b7d861d9SBoojin Kim val = readl(regs + DS) & 0xf; 917b7d861d9SBoojin Kim else 918b7d861d9SBoojin Kim val = readl(regs + CS(thrd->id)) & 0xf; 919b7d861d9SBoojin Kim 920b7d861d9SBoojin Kim switch (val) { 921b7d861d9SBoojin Kim case DS_ST_STOP: 922b7d861d9SBoojin Kim return PL330_STATE_STOPPED; 923b7d861d9SBoojin Kim case DS_ST_EXEC: 924b7d861d9SBoojin Kim return PL330_STATE_EXECUTING; 925b7d861d9SBoojin Kim case DS_ST_CMISS: 926b7d861d9SBoojin Kim return PL330_STATE_CACHEMISS; 927b7d861d9SBoojin Kim case DS_ST_UPDTPC: 928b7d861d9SBoojin Kim return PL330_STATE_UPDTPC; 929b7d861d9SBoojin Kim case DS_ST_WFE: 930b7d861d9SBoojin Kim return PL330_STATE_WFE; 931b7d861d9SBoojin Kim case DS_ST_FAULT: 932b7d861d9SBoojin Kim return PL330_STATE_FAULTING; 933b7d861d9SBoojin Kim case DS_ST_ATBRR: 934b7d861d9SBoojin Kim if (is_manager(thrd)) 935b7d861d9SBoojin Kim return PL330_STATE_INVALID; 936b7d861d9SBoojin Kim else 937b7d861d9SBoojin Kim return PL330_STATE_ATBARRIER; 938b7d861d9SBoojin Kim case DS_ST_QBUSY: 939b7d861d9SBoojin Kim if (is_manager(thrd)) 940b7d861d9SBoojin Kim return PL330_STATE_INVALID; 941b7d861d9SBoojin Kim else 942b7d861d9SBoojin Kim return PL330_STATE_QUEUEBUSY; 943b7d861d9SBoojin Kim case DS_ST_WFP: 944b7d861d9SBoojin Kim if (is_manager(thrd)) 945b7d861d9SBoojin Kim return PL330_STATE_INVALID; 946b7d861d9SBoojin Kim else 947b7d861d9SBoojin Kim return PL330_STATE_WFP; 948b7d861d9SBoojin Kim case DS_ST_KILL: 949b7d861d9SBoojin Kim if (is_manager(thrd)) 950b7d861d9SBoojin Kim return PL330_STATE_INVALID; 951b7d861d9SBoojin Kim else 952b7d861d9SBoojin Kim return PL330_STATE_KILLING; 953b7d861d9SBoojin Kim case DS_ST_CMPLT: 954b7d861d9SBoojin Kim if (is_manager(thrd)) 955b7d861d9SBoojin Kim return PL330_STATE_INVALID; 956b7d861d9SBoojin Kim else 957b7d861d9SBoojin Kim return PL330_STATE_COMPLETING; 958b7d861d9SBoojin Kim case DS_ST_FLTCMP: 959b7d861d9SBoojin Kim if (is_manager(thrd)) 960b7d861d9SBoojin Kim return PL330_STATE_INVALID; 961b7d861d9SBoojin Kim else 962b7d861d9SBoojin Kim return PL330_STATE_FAULT_COMPLETING; 963b7d861d9SBoojin Kim default: 964b7d861d9SBoojin Kim return PL330_STATE_INVALID; 965b7d861d9SBoojin Kim } 966b7d861d9SBoojin Kim } 967b7d861d9SBoojin Kim 968b7d861d9SBoojin Kim static void _stop(struct pl330_thread *thrd) 969b7d861d9SBoojin Kim { 970f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 971b7d861d9SBoojin Kim u8 insn[6] = {0, 0, 0, 0, 0, 0}; 9722da254ccSSugar Zhang u32 inten = readl(regs + INTEN); 973b7d861d9SBoojin Kim 974b7d861d9SBoojin Kim if (_state(thrd) == PL330_STATE_FAULT_COMPLETING) 975b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); 976b7d861d9SBoojin Kim 977b7d861d9SBoojin Kim /* Return if nothing needs to be done */ 978b7d861d9SBoojin Kim if (_state(thrd) == PL330_STATE_COMPLETING 979b7d861d9SBoojin Kim || _state(thrd) == PL330_STATE_KILLING 980b7d861d9SBoojin Kim || _state(thrd) == PL330_STATE_STOPPED) 981b7d861d9SBoojin Kim return; 982b7d861d9SBoojin Kim 983b7d861d9SBoojin Kim _emit_KILL(0, insn); 984b7d861d9SBoojin Kim 985b7d861d9SBoojin Kim _execute_DBGINSN(thrd, insn, is_manager(thrd)); 9862da254ccSSugar Zhang 9872da254ccSSugar Zhang /* clear the event */ 9882da254ccSSugar Zhang if (inten & (1 << thrd->ev)) 9892da254ccSSugar Zhang writel(1 << thrd->ev, regs + INTCLR); 9902da254ccSSugar Zhang /* Stop generating interrupts for SEV */ 9912da254ccSSugar Zhang writel(inten & ~(1 << thrd->ev), regs + INTEN); 992b7d861d9SBoojin Kim } 993b7d861d9SBoojin Kim 994b7d861d9SBoojin Kim /* Start doing req 'idx' of thread 'thrd' */ 995b7d861d9SBoojin Kim static bool _trigger(struct pl330_thread *thrd) 996b7d861d9SBoojin Kim { 997f6f2421cSLars-Peter Clausen void __iomem *regs = thrd->dmac->base; 998b7d861d9SBoojin Kim struct _pl330_req *req; 9999dc5a315SLars-Peter Clausen struct dma_pl330_desc *desc; 1000b7d861d9SBoojin Kim struct _arg_GO go; 1001b7d861d9SBoojin Kim unsigned ns; 1002b7d861d9SBoojin Kim u8 insn[6] = {0, 0, 0, 0, 0, 0}; 1003b7d861d9SBoojin Kim int idx; 1004b7d861d9SBoojin Kim 1005b7d861d9SBoojin Kim /* Return if already ACTIVE */ 1006b7d861d9SBoojin Kim if (_state(thrd) != PL330_STATE_STOPPED) 1007b7d861d9SBoojin Kim return true; 1008b7d861d9SBoojin Kim 1009b7d861d9SBoojin Kim idx = 1 - thrd->lstenq; 10108ed30a14SLars-Peter Clausen if (thrd->req[idx].desc != NULL) { 1011b7d861d9SBoojin Kim req = &thrd->req[idx]; 10128ed30a14SLars-Peter Clausen } else { 1013b7d861d9SBoojin Kim idx = thrd->lstenq; 10148ed30a14SLars-Peter Clausen if (thrd->req[idx].desc != NULL) 1015b7d861d9SBoojin Kim req = &thrd->req[idx]; 1016b7d861d9SBoojin Kim else 1017b7d861d9SBoojin Kim req = NULL; 1018b7d861d9SBoojin Kim } 1019b7d861d9SBoojin Kim 1020b7d861d9SBoojin Kim /* Return if no request */ 10218ed30a14SLars-Peter Clausen if (!req) 1022b7d861d9SBoojin Kim return true; 1023b7d861d9SBoojin Kim 10240091b9d6SAddy Ke /* Return if req is running */ 10250091b9d6SAddy Ke if (idx == thrd->req_running) 10260091b9d6SAddy Ke return true; 10270091b9d6SAddy Ke 10289dc5a315SLars-Peter Clausen desc = req->desc; 1029b7d861d9SBoojin Kim 10309dc5a315SLars-Peter Clausen ns = desc->rqcfg.nonsecure ? 1 : 0; 1031b7d861d9SBoojin Kim 1032b7d861d9SBoojin Kim /* See 'Abort Sources' point-4 at Page 2-25 */ 1033b7d861d9SBoojin Kim if (_manager_ns(thrd) && !ns) 1034f6f2421cSLars-Peter Clausen dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n", 1035b7d861d9SBoojin Kim __func__, __LINE__); 1036b7d861d9SBoojin Kim 1037b7d861d9SBoojin Kim go.chan = thrd->id; 1038b7d861d9SBoojin Kim go.addr = req->mc_bus; 1039b7d861d9SBoojin Kim go.ns = ns; 1040b7d861d9SBoojin Kim _emit_GO(0, insn, &go); 1041b7d861d9SBoojin Kim 1042b7d861d9SBoojin Kim /* Set to generate interrupts for SEV */ 1043b7d861d9SBoojin Kim writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); 1044b7d861d9SBoojin Kim 1045b7d861d9SBoojin Kim /* Only manager can execute GO */ 1046b7d861d9SBoojin Kim _execute_DBGINSN(thrd, insn, true); 1047b7d861d9SBoojin Kim 1048b7d861d9SBoojin Kim thrd->req_running = idx; 1049b7d861d9SBoojin Kim 1050b7d861d9SBoojin Kim return true; 1051b7d861d9SBoojin Kim } 1052b7d861d9SBoojin Kim 1053b7d861d9SBoojin Kim static bool _start(struct pl330_thread *thrd) 1054b7d861d9SBoojin Kim { 1055b7d861d9SBoojin Kim switch (_state(thrd)) { 1056b7d861d9SBoojin Kim case PL330_STATE_FAULT_COMPLETING: 1057b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); 1058b7d861d9SBoojin Kim 1059b7d861d9SBoojin Kim if (_state(thrd) == PL330_STATE_KILLING) 1060b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_STOPPED) 1061df561f66SGustavo A. R. Silva fallthrough; 1062b7d861d9SBoojin Kim 1063b7d861d9SBoojin Kim case PL330_STATE_FAULTING: 1064b7d861d9SBoojin Kim _stop(thrd); 1065df561f66SGustavo A. R. Silva fallthrough; 1066b7d861d9SBoojin Kim 1067b7d861d9SBoojin Kim case PL330_STATE_KILLING: 1068b7d861d9SBoojin Kim case PL330_STATE_COMPLETING: 1069b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_STOPPED) 1070df561f66SGustavo A. R. Silva fallthrough; 1071b7d861d9SBoojin Kim 1072b7d861d9SBoojin Kim case PL330_STATE_STOPPED: 1073b7d861d9SBoojin Kim return _trigger(thrd); 1074b7d861d9SBoojin Kim 1075b7d861d9SBoojin Kim case PL330_STATE_WFP: 1076b7d861d9SBoojin Kim case PL330_STATE_QUEUEBUSY: 1077b7d861d9SBoojin Kim case PL330_STATE_ATBARRIER: 1078b7d861d9SBoojin Kim case PL330_STATE_UPDTPC: 1079b7d861d9SBoojin Kim case PL330_STATE_CACHEMISS: 1080b7d861d9SBoojin Kim case PL330_STATE_EXECUTING: 1081b7d861d9SBoojin Kim return true; 1082b7d861d9SBoojin Kim 1083b7d861d9SBoojin Kim case PL330_STATE_WFE: /* For RESUME, nothing yet */ 1084b7d861d9SBoojin Kim default: 1085b7d861d9SBoojin Kim return false; 1086b7d861d9SBoojin Kim } 1087b7d861d9SBoojin Kim } 1088b7d861d9SBoojin Kim 1089b7d861d9SBoojin Kim static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], 1090b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1091b7d861d9SBoojin Kim { 1092b7d861d9SBoojin Kim int off = 0; 10939dc5a315SLars-Peter Clausen struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg; 1094b7d861d9SBoojin Kim 10953ecf51a4SBoojin Kim /* check lock-up free version */ 10963ecf51a4SBoojin Kim if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { 10973ecf51a4SBoojin Kim while (cyc--) { 10983ecf51a4SBoojin Kim off += _emit_LD(dry_run, &buf[off], ALWAYS); 10993ecf51a4SBoojin Kim off += _emit_ST(dry_run, &buf[off], ALWAYS); 11003ecf51a4SBoojin Kim } 11013ecf51a4SBoojin Kim } else { 1102b7d861d9SBoojin Kim while (cyc--) { 1103b7d861d9SBoojin Kim off += _emit_LD(dry_run, &buf[off], ALWAYS); 1104b7d861d9SBoojin Kim off += _emit_RMB(dry_run, &buf[off]); 1105b7d861d9SBoojin Kim off += _emit_ST(dry_run, &buf[off], ALWAYS); 1106b7d861d9SBoojin Kim off += _emit_WMB(dry_run, &buf[off]); 1107b7d861d9SBoojin Kim } 11083ecf51a4SBoojin Kim } 1109b7d861d9SBoojin Kim 1110b7d861d9SBoojin Kim return off; 1111b7d861d9SBoojin Kim } 1112b7d861d9SBoojin Kim 11131d48745bSFrank Mori Hess static u32 _emit_load(unsigned int dry_run, u8 buf[], 11141d48745bSFrank Mori Hess enum pl330_cond cond, enum dma_transfer_direction direction, 11151d48745bSFrank Mori Hess u8 peri) 1116b7d861d9SBoojin Kim { 1117b7d861d9SBoojin Kim int off = 0; 1118848e9776SBoojin Kim 11191d48745bSFrank Mori Hess switch (direction) { 11201d48745bSFrank Mori Hess case DMA_MEM_TO_MEM: 11211d48745bSFrank Mori Hess case DMA_MEM_TO_DEV: 11221d48745bSFrank Mori Hess off += _emit_LD(dry_run, &buf[off], cond); 11231d48745bSFrank Mori Hess break; 1124b7d861d9SBoojin Kim 11251d48745bSFrank Mori Hess case DMA_DEV_TO_MEM: 11261d48745bSFrank Mori Hess if (cond == ALWAYS) { 11271d48745bSFrank Mori Hess off += _emit_LDP(dry_run, &buf[off], SINGLE, 11281d48745bSFrank Mori Hess peri); 11291d48745bSFrank Mori Hess off += _emit_LDP(dry_run, &buf[off], BURST, 11301d48745bSFrank Mori Hess peri); 11311d48745bSFrank Mori Hess } else { 11321d48745bSFrank Mori Hess off += _emit_LDP(dry_run, &buf[off], cond, 11331d48745bSFrank Mori Hess peri); 11341d48745bSFrank Mori Hess } 11351d48745bSFrank Mori Hess break; 1136271e1b86SAddy Ke 11371d48745bSFrank Mori Hess default: 11381d48745bSFrank Mori Hess /* this code should be unreachable */ 11391d48745bSFrank Mori Hess WARN_ON(1); 11401d48745bSFrank Mori Hess break; 1141b7d861d9SBoojin Kim } 1142b7d861d9SBoojin Kim 1143b7d861d9SBoojin Kim return off; 1144b7d861d9SBoojin Kim } 1145b7d861d9SBoojin Kim 11461d48745bSFrank Mori Hess static inline u32 _emit_store(unsigned int dry_run, u8 buf[], 11471d48745bSFrank Mori Hess enum pl330_cond cond, enum dma_transfer_direction direction, 11481d48745bSFrank Mori Hess u8 peri) 1149b7d861d9SBoojin Kim { 1150b7d861d9SBoojin Kim int off = 0; 11511d48745bSFrank Mori Hess 11521d48745bSFrank Mori Hess switch (direction) { 11531d48745bSFrank Mori Hess case DMA_MEM_TO_MEM: 11541d48745bSFrank Mori Hess case DMA_DEV_TO_MEM: 11551d48745bSFrank Mori Hess off += _emit_ST(dry_run, &buf[off], cond); 11561d48745bSFrank Mori Hess break; 11571d48745bSFrank Mori Hess 11581d48745bSFrank Mori Hess case DMA_MEM_TO_DEV: 11591d48745bSFrank Mori Hess if (cond == ALWAYS) { 11601d48745bSFrank Mori Hess off += _emit_STP(dry_run, &buf[off], SINGLE, 11611d48745bSFrank Mori Hess peri); 11621d48745bSFrank Mori Hess off += _emit_STP(dry_run, &buf[off], BURST, 11631d48745bSFrank Mori Hess peri); 11641d48745bSFrank Mori Hess } else { 11651d48745bSFrank Mori Hess off += _emit_STP(dry_run, &buf[off], cond, 11661d48745bSFrank Mori Hess peri); 11671d48745bSFrank Mori Hess } 11681d48745bSFrank Mori Hess break; 11691d48745bSFrank Mori Hess 11701d48745bSFrank Mori Hess default: 11711d48745bSFrank Mori Hess /* this code should be unreachable */ 11721d48745bSFrank Mori Hess WARN_ON(1); 11731d48745bSFrank Mori Hess break; 11741d48745bSFrank Mori Hess } 11751d48745bSFrank Mori Hess 11761d48745bSFrank Mori Hess return off; 11771d48745bSFrank Mori Hess } 11781d48745bSFrank Mori Hess 11791d48745bSFrank Mori Hess static inline int _ldst_peripheral(struct pl330_dmac *pl330, 11801d48745bSFrank Mori Hess unsigned dry_run, u8 buf[], 11811d48745bSFrank Mori Hess const struct _xfer_spec *pxs, int cyc, 11821d48745bSFrank Mori Hess enum pl330_cond cond) 11831d48745bSFrank Mori Hess { 11841d48745bSFrank Mori Hess int off = 0; 1185848e9776SBoojin Kim 11861d48745bSFrank Mori Hess /* 11871d48745bSFrank Mori Hess * do FLUSHP at beginning to clear any stale dma requests before the 11881d48745bSFrank Mori Hess * first WFP. 11891d48745bSFrank Mori Hess */ 11901d48745bSFrank Mori Hess if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)) 11911d48745bSFrank Mori Hess off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri); 1192b7d861d9SBoojin Kim while (cyc--) { 1193848e9776SBoojin Kim off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri); 11941d48745bSFrank Mori Hess off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype, 11951d48745bSFrank Mori Hess pxs->desc->peri); 11961d48745bSFrank Mori Hess off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype, 1197271e1b86SAddy Ke pxs->desc->peri); 1198b7d861d9SBoojin Kim } 1199b7d861d9SBoojin Kim 1200b7d861d9SBoojin Kim return off; 1201b7d861d9SBoojin Kim } 1202b7d861d9SBoojin Kim 1203271e1b86SAddy Ke static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[], 1204b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1205b7d861d9SBoojin Kim { 1206b7d861d9SBoojin Kim int off = 0; 12071d48745bSFrank Mori Hess enum pl330_cond cond = BRST_LEN(pxs->ccr) > 1 ? BURST : SINGLE; 1208b7d861d9SBoojin Kim 12095fb9e3a3SSugar Zhang if (pl330->quirks & PL330_QUIRK_PERIPH_BURST) 12105fb9e3a3SSugar Zhang cond = BURST; 12115fb9e3a3SSugar Zhang 12129dc5a315SLars-Peter Clausen switch (pxs->desc->rqtype) { 1213585a9d0bSLars-Peter Clausen case DMA_MEM_TO_DEV: 1214585a9d0bSLars-Peter Clausen case DMA_DEV_TO_MEM: 12151d48745bSFrank Mori Hess off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, cyc, 12161d48745bSFrank Mori Hess cond); 1217b7d861d9SBoojin Kim break; 12181d48745bSFrank Mori Hess 1219585a9d0bSLars-Peter Clausen case DMA_MEM_TO_MEM: 1220b7d861d9SBoojin Kim off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); 1221b7d861d9SBoojin Kim break; 12221d48745bSFrank Mori Hess 1223b7d861d9SBoojin Kim default: 12241d48745bSFrank Mori Hess /* this code should be unreachable */ 12251d48745bSFrank Mori Hess WARN_ON(1); 12261d48745bSFrank Mori Hess break; 12271d48745bSFrank Mori Hess } 12281d48745bSFrank Mori Hess 12291d48745bSFrank Mori Hess return off; 12301d48745bSFrank Mori Hess } 12311d48745bSFrank Mori Hess 12321d48745bSFrank Mori Hess /* 12333e7f0bd8SSugar Zhang * only the unaligned burst transfers have the dregs. 12343e7f0bd8SSugar Zhang * so, still transfer dregs with a reduced size burst 12353e7f0bd8SSugar Zhang * for mem-to-mem, mem-to-dev or dev-to-mem. 12361d48745bSFrank Mori Hess */ 12371d48745bSFrank Mori Hess static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[], 12381d48745bSFrank Mori Hess const struct _xfer_spec *pxs, int transfer_length) 12391d48745bSFrank Mori Hess { 12401d48745bSFrank Mori Hess int off = 0; 12411d48745bSFrank Mori Hess int dregs_ccr; 12421d48745bSFrank Mori Hess 12431d48745bSFrank Mori Hess if (transfer_length == 0) 12441d48745bSFrank Mori Hess return off; 12451d48745bSFrank Mori Hess 12463e7f0bd8SSugar Zhang /* 12473e7f0bd8SSugar Zhang * dregs_len = (total bytes - BURST_TO_BYTE(bursts, ccr)) / 12483e7f0bd8SSugar Zhang * BRST_SIZE(ccr) 12493e7f0bd8SSugar Zhang * the dregs len must be smaller than burst len, 12503e7f0bd8SSugar Zhang * so, for higher efficiency, we can modify CCR 12513e7f0bd8SSugar Zhang * to use a reduced size burst len for the dregs. 12523e7f0bd8SSugar Zhang */ 12531d48745bSFrank Mori Hess dregs_ccr = pxs->ccr; 12541d48745bSFrank Mori Hess dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) | 12551d48745bSFrank Mori Hess (0xf << CC_DSTBRSTLEN_SHFT)); 12561d48745bSFrank Mori Hess dregs_ccr |= (((transfer_length - 1) & 0xf) << 12571d48745bSFrank Mori Hess CC_SRCBRSTLEN_SHFT); 12581d48745bSFrank Mori Hess dregs_ccr |= (((transfer_length - 1) & 0xf) << 12591d48745bSFrank Mori Hess CC_DSTBRSTLEN_SHFT); 12603e7f0bd8SSugar Zhang 12613e7f0bd8SSugar Zhang switch (pxs->desc->rqtype) { 12623e7f0bd8SSugar Zhang case DMA_MEM_TO_DEV: 12633e7f0bd8SSugar Zhang case DMA_DEV_TO_MEM: 12643e7f0bd8SSugar Zhang off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr); 12653e7f0bd8SSugar Zhang off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, 1, 12663e7f0bd8SSugar Zhang BURST); 12673e7f0bd8SSugar Zhang break; 12683e7f0bd8SSugar Zhang 12693e7f0bd8SSugar Zhang case DMA_MEM_TO_MEM: 12701d48745bSFrank Mori Hess off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr); 12711d48745bSFrank Mori Hess off += _ldst_memtomem(dry_run, &buf[off], pxs, 1); 12721d48745bSFrank Mori Hess break; 12731d48745bSFrank Mori Hess 12741d48745bSFrank Mori Hess default: 12751d48745bSFrank Mori Hess /* this code should be unreachable */ 12761d48745bSFrank Mori Hess WARN_ON(1); 1277b7d861d9SBoojin Kim break; 1278b7d861d9SBoojin Kim } 1279b7d861d9SBoojin Kim 1280b7d861d9SBoojin Kim return off; 1281b7d861d9SBoojin Kim } 1282b7d861d9SBoojin Kim 1283b7d861d9SBoojin Kim /* Returns bytes consumed and updates bursts */ 1284271e1b86SAddy Ke static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[], 1285b7d861d9SBoojin Kim unsigned long *bursts, const struct _xfer_spec *pxs) 1286b7d861d9SBoojin Kim { 1287b7d861d9SBoojin Kim int cyc, cycmax, szlp, szlpend, szbrst, off; 1288b7d861d9SBoojin Kim unsigned lcnt0, lcnt1, ljmp0, ljmp1; 1289b7d861d9SBoojin Kim struct _arg_LPEND lpend; 1290b7d861d9SBoojin Kim 129131495d60SMichal Suchanek if (*bursts == 1) 1292848e9776SBoojin Kim return _bursts(pl330, dry_run, buf, pxs, 1); 129331495d60SMichal Suchanek 1294b7d861d9SBoojin Kim /* Max iterations possible in DMALP is 256 */ 1295b7d861d9SBoojin Kim if (*bursts >= 256*256) { 1296b7d861d9SBoojin Kim lcnt1 = 256; 1297b7d861d9SBoojin Kim lcnt0 = 256; 1298b7d861d9SBoojin Kim cyc = *bursts / lcnt1 / lcnt0; 1299b7d861d9SBoojin Kim } else if (*bursts > 256) { 1300b7d861d9SBoojin Kim lcnt1 = 256; 1301b7d861d9SBoojin Kim lcnt0 = *bursts / lcnt1; 1302b7d861d9SBoojin Kim cyc = 1; 1303b7d861d9SBoojin Kim } else { 1304b7d861d9SBoojin Kim lcnt1 = *bursts; 1305b7d861d9SBoojin Kim lcnt0 = 0; 1306b7d861d9SBoojin Kim cyc = 1; 1307b7d861d9SBoojin Kim } 1308b7d861d9SBoojin Kim 1309b7d861d9SBoojin Kim szlp = _emit_LP(1, buf, 0, 0); 1310271e1b86SAddy Ke szbrst = _bursts(pl330, 1, buf, pxs, 1); 1311b7d861d9SBoojin Kim 1312b7d861d9SBoojin Kim lpend.cond = ALWAYS; 1313b7d861d9SBoojin Kim lpend.forever = false; 1314b7d861d9SBoojin Kim lpend.loop = 0; 1315b7d861d9SBoojin Kim lpend.bjump = 0; 1316b7d861d9SBoojin Kim szlpend = _emit_LPEND(1, buf, &lpend); 1317b7d861d9SBoojin Kim 1318b7d861d9SBoojin Kim if (lcnt0) { 1319b7d861d9SBoojin Kim szlp *= 2; 1320b7d861d9SBoojin Kim szlpend *= 2; 1321b7d861d9SBoojin Kim } 1322b7d861d9SBoojin Kim 1323b7d861d9SBoojin Kim /* 1324b7d861d9SBoojin Kim * Max bursts that we can unroll due to limit on the 1325b7d861d9SBoojin Kim * size of backward jump that can be encoded in DMALPEND 1326b7d861d9SBoojin Kim * which is 8-bits and hence 255 1327b7d861d9SBoojin Kim */ 1328b7d861d9SBoojin Kim cycmax = (255 - (szlp + szlpend)) / szbrst; 1329b7d861d9SBoojin Kim 1330b7d861d9SBoojin Kim cyc = (cycmax < cyc) ? cycmax : cyc; 1331b7d861d9SBoojin Kim 1332b7d861d9SBoojin Kim off = 0; 1333b7d861d9SBoojin Kim 1334b7d861d9SBoojin Kim if (lcnt0) { 1335b7d861d9SBoojin Kim off += _emit_LP(dry_run, &buf[off], 0, lcnt0); 1336b7d861d9SBoojin Kim ljmp0 = off; 1337b7d861d9SBoojin Kim } 1338b7d861d9SBoojin Kim 1339b7d861d9SBoojin Kim off += _emit_LP(dry_run, &buf[off], 1, lcnt1); 1340b7d861d9SBoojin Kim ljmp1 = off; 1341b7d861d9SBoojin Kim 1342271e1b86SAddy Ke off += _bursts(pl330, dry_run, &buf[off], pxs, cyc); 1343b7d861d9SBoojin Kim 1344b7d861d9SBoojin Kim lpend.cond = ALWAYS; 1345b7d861d9SBoojin Kim lpend.forever = false; 1346b7d861d9SBoojin Kim lpend.loop = 1; 1347b7d861d9SBoojin Kim lpend.bjump = off - ljmp1; 1348b7d861d9SBoojin Kim off += _emit_LPEND(dry_run, &buf[off], &lpend); 1349b7d861d9SBoojin Kim 1350b7d861d9SBoojin Kim if (lcnt0) { 1351b7d861d9SBoojin Kim lpend.cond = ALWAYS; 1352b7d861d9SBoojin Kim lpend.forever = false; 1353b7d861d9SBoojin Kim lpend.loop = 0; 1354b7d861d9SBoojin Kim lpend.bjump = off - ljmp0; 1355b7d861d9SBoojin Kim off += _emit_LPEND(dry_run, &buf[off], &lpend); 1356b7d861d9SBoojin Kim } 1357b7d861d9SBoojin Kim 1358b7d861d9SBoojin Kim *bursts = lcnt1 * cyc; 1359b7d861d9SBoojin Kim if (lcnt0) 1360b7d861d9SBoojin Kim *bursts *= lcnt0; 1361b7d861d9SBoojin Kim 1362b7d861d9SBoojin Kim return off; 1363b7d861d9SBoojin Kim } 1364b7d861d9SBoojin Kim 1365271e1b86SAddy Ke static inline int _setup_loops(struct pl330_dmac *pl330, 1366271e1b86SAddy Ke unsigned dry_run, u8 buf[], 1367b7d861d9SBoojin Kim const struct _xfer_spec *pxs) 1368b7d861d9SBoojin Kim { 13699dc5a315SLars-Peter Clausen struct pl330_xfer *x = &pxs->desc->px; 1370b7d861d9SBoojin Kim u32 ccr = pxs->ccr; 1371b7d861d9SBoojin Kim unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); 13721d48745bSFrank Mori Hess int num_dregs = (x->bytes - BURST_TO_BYTE(bursts, ccr)) / 13731d48745bSFrank Mori Hess BRST_SIZE(ccr); 1374b7d861d9SBoojin Kim int off = 0; 1375b7d861d9SBoojin Kim 1376b7d861d9SBoojin Kim while (bursts) { 1377b7d861d9SBoojin Kim c = bursts; 1378271e1b86SAddy Ke off += _loop(pl330, dry_run, &buf[off], &c, pxs); 1379b7d861d9SBoojin Kim bursts -= c; 1380b7d861d9SBoojin Kim } 13811d48745bSFrank Mori Hess off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs); 1382b7d861d9SBoojin Kim 1383b7d861d9SBoojin Kim return off; 1384b7d861d9SBoojin Kim } 1385b7d861d9SBoojin Kim 1386271e1b86SAddy Ke static inline int _setup_xfer(struct pl330_dmac *pl330, 1387271e1b86SAddy Ke unsigned dry_run, u8 buf[], 1388b7d861d9SBoojin Kim const struct _xfer_spec *pxs) 1389b7d861d9SBoojin Kim { 13909dc5a315SLars-Peter Clausen struct pl330_xfer *x = &pxs->desc->px; 1391b7d861d9SBoojin Kim int off = 0; 1392b7d861d9SBoojin Kim 1393b7d861d9SBoojin Kim /* DMAMOV SAR, x->src_addr */ 1394b7d861d9SBoojin Kim off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); 1395b7d861d9SBoojin Kim /* DMAMOV DAR, x->dst_addr */ 1396b7d861d9SBoojin Kim off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr); 1397b7d861d9SBoojin Kim 1398b7d861d9SBoojin Kim /* Setup Loop(s) */ 1399271e1b86SAddy Ke off += _setup_loops(pl330, dry_run, &buf[off], pxs); 1400b7d861d9SBoojin Kim 1401b7d861d9SBoojin Kim return off; 1402b7d861d9SBoojin Kim } 1403b7d861d9SBoojin Kim 1404b7d861d9SBoojin Kim /* 1405b7d861d9SBoojin Kim * A req is a sequence of one or more xfer units. 1406b7d861d9SBoojin Kim * Returns the number of bytes taken to setup the MC for the req. 1407b7d861d9SBoojin Kim */ 1408271e1b86SAddy Ke static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run, 1409271e1b86SAddy Ke struct pl330_thread *thrd, unsigned index, 1410271e1b86SAddy Ke struct _xfer_spec *pxs) 1411b7d861d9SBoojin Kim { 1412b7d861d9SBoojin Kim struct _pl330_req *req = &thrd->req[index]; 1413b7d861d9SBoojin Kim u8 *buf = req->mc_cpu; 1414b7d861d9SBoojin Kim int off = 0; 1415b7d861d9SBoojin Kim 1416b7d861d9SBoojin Kim PL330_DBGMC_START(req->mc_bus); 1417b7d861d9SBoojin Kim 1418b7d861d9SBoojin Kim /* DMAMOV CCR, ccr */ 1419b7d861d9SBoojin Kim off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); 1420b7d861d9SBoojin Kim 1421271e1b86SAddy Ke off += _setup_xfer(pl330, dry_run, &buf[off], pxs); 1422b7d861d9SBoojin Kim 1423b7d861d9SBoojin Kim /* DMASEV peripheral/event */ 1424b7d861d9SBoojin Kim off += _emit_SEV(dry_run, &buf[off], thrd->ev); 1425b7d861d9SBoojin Kim /* DMAEND */ 1426b7d861d9SBoojin Kim off += _emit_END(dry_run, &buf[off]); 1427b7d861d9SBoojin Kim 1428b7d861d9SBoojin Kim return off; 1429b7d861d9SBoojin Kim } 1430b7d861d9SBoojin Kim 1431b7d861d9SBoojin Kim static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) 1432b7d861d9SBoojin Kim { 1433b7d861d9SBoojin Kim u32 ccr = 0; 1434b7d861d9SBoojin Kim 1435b7d861d9SBoojin Kim if (rqc->src_inc) 1436b7d861d9SBoojin Kim ccr |= CC_SRCINC; 1437b7d861d9SBoojin Kim 1438b7d861d9SBoojin Kim if (rqc->dst_inc) 1439b7d861d9SBoojin Kim ccr |= CC_DSTINC; 1440b7d861d9SBoojin Kim 1441b7d861d9SBoojin Kim /* We set same protection levels for Src and DST for now */ 1442b7d861d9SBoojin Kim if (rqc->privileged) 1443b7d861d9SBoojin Kim ccr |= CC_SRCPRI | CC_DSTPRI; 1444b7d861d9SBoojin Kim if (rqc->nonsecure) 1445b7d861d9SBoojin Kim ccr |= CC_SRCNS | CC_DSTNS; 1446b7d861d9SBoojin Kim if (rqc->insnaccess) 1447b7d861d9SBoojin Kim ccr |= CC_SRCIA | CC_DSTIA; 1448b7d861d9SBoojin Kim 1449b7d861d9SBoojin Kim ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); 1450b7d861d9SBoojin Kim ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); 1451b7d861d9SBoojin Kim 1452b7d861d9SBoojin Kim ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); 1453b7d861d9SBoojin Kim ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); 1454b7d861d9SBoojin Kim 1455b7d861d9SBoojin Kim ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); 1456b7d861d9SBoojin Kim ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); 1457b7d861d9SBoojin Kim 1458b7d861d9SBoojin Kim ccr |= (rqc->swap << CC_SWAP_SHFT); 1459b7d861d9SBoojin Kim 1460b7d861d9SBoojin Kim return ccr; 1461b7d861d9SBoojin Kim } 1462b7d861d9SBoojin Kim 1463b7d861d9SBoojin Kim /* 1464b7d861d9SBoojin Kim * Submit a list of xfers after which the client wants notification. 1465b7d861d9SBoojin Kim * Client is not notified after each xfer unit, just once after all 1466b7d861d9SBoojin Kim * xfer units are done or some error occurs. 1467b7d861d9SBoojin Kim */ 14689dc5a315SLars-Peter Clausen static int pl330_submit_req(struct pl330_thread *thrd, 14699dc5a315SLars-Peter Clausen struct dma_pl330_desc *desc) 1470b7d861d9SBoojin Kim { 1471f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = thrd->dmac; 1472b7d861d9SBoojin Kim struct _xfer_spec xs; 1473b7d861d9SBoojin Kim unsigned long flags; 1474b7d861d9SBoojin Kim unsigned idx; 1475b7d861d9SBoojin Kim u32 ccr; 1476b7d861d9SBoojin Kim int ret = 0; 1477b7d861d9SBoojin Kim 14781d48745bSFrank Mori Hess switch (desc->rqtype) { 14791d48745bSFrank Mori Hess case DMA_MEM_TO_DEV: 14801d48745bSFrank Mori Hess break; 14811d48745bSFrank Mori Hess 14821d48745bSFrank Mori Hess case DMA_DEV_TO_MEM: 14831d48745bSFrank Mori Hess break; 14841d48745bSFrank Mori Hess 14851d48745bSFrank Mori Hess case DMA_MEM_TO_MEM: 14861d48745bSFrank Mori Hess break; 14871d48745bSFrank Mori Hess 14881d48745bSFrank Mori Hess default: 14891d48745bSFrank Mori Hess return -ENOTSUPP; 14901d48745bSFrank Mori Hess } 14911d48745bSFrank Mori Hess 1492b7d861d9SBoojin Kim if (pl330->state == DYING 1493b7d861d9SBoojin Kim || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { 1494f6f2421cSLars-Peter Clausen dev_info(thrd->dmac->ddma.dev, "%s:%d\n", 1495b7d861d9SBoojin Kim __func__, __LINE__); 1496b7d861d9SBoojin Kim return -EAGAIN; 1497b7d861d9SBoojin Kim } 1498b7d861d9SBoojin Kim 1499b7d861d9SBoojin Kim /* If request for non-existing peripheral */ 15009dc5a315SLars-Peter Clausen if (desc->rqtype != DMA_MEM_TO_MEM && 15019dc5a315SLars-Peter Clausen desc->peri >= pl330->pcfg.num_peri) { 1502f6f2421cSLars-Peter Clausen dev_info(thrd->dmac->ddma.dev, 1503b7d861d9SBoojin Kim "%s:%d Invalid peripheral(%u)!\n", 15049dc5a315SLars-Peter Clausen __func__, __LINE__, desc->peri); 1505b7d861d9SBoojin Kim return -EINVAL; 1506b7d861d9SBoojin Kim } 1507b7d861d9SBoojin Kim 1508b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1509b7d861d9SBoojin Kim 1510b7d861d9SBoojin Kim if (_queue_full(thrd)) { 1511b7d861d9SBoojin Kim ret = -EAGAIN; 1512b7d861d9SBoojin Kim goto xfer_exit; 1513b7d861d9SBoojin Kim } 1514b7d861d9SBoojin Kim 1515b7d861d9SBoojin Kim /* Prefer Secure Channel */ 1516b7d861d9SBoojin Kim if (!_manager_ns(thrd)) 15179dc5a315SLars-Peter Clausen desc->rqcfg.nonsecure = 0; 1518b7d861d9SBoojin Kim else 15199dc5a315SLars-Peter Clausen desc->rqcfg.nonsecure = 1; 1520b7d861d9SBoojin Kim 15219dc5a315SLars-Peter Clausen ccr = _prepare_ccr(&desc->rqcfg); 1522b7d861d9SBoojin Kim 15238ed30a14SLars-Peter Clausen idx = thrd->req[0].desc == NULL ? 0 : 1; 1524b7d861d9SBoojin Kim 1525b7d861d9SBoojin Kim xs.ccr = ccr; 15269dc5a315SLars-Peter Clausen xs.desc = desc; 1527b7d861d9SBoojin Kim 1528b7d861d9SBoojin Kim /* First dry run to check if req is acceptable */ 1529271e1b86SAddy Ke ret = _setup_req(pl330, 1, thrd, idx, &xs); 1530b7d861d9SBoojin Kim if (ret < 0) 1531b7d861d9SBoojin Kim goto xfer_exit; 1532b7d861d9SBoojin Kim 1533f6f2421cSLars-Peter Clausen if (ret > pl330->mcbufsz / 2) { 1534e5489d5eSMichal Suchanek dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n", 1535e5489d5eSMichal Suchanek __func__, __LINE__, ret, pl330->mcbufsz / 2); 1536b7d861d9SBoojin Kim ret = -ENOMEM; 1537b7d861d9SBoojin Kim goto xfer_exit; 1538b7d861d9SBoojin Kim } 1539b7d861d9SBoojin Kim 1540b7d861d9SBoojin Kim /* Hook the request */ 1541b7d861d9SBoojin Kim thrd->lstenq = idx; 15429dc5a315SLars-Peter Clausen thrd->req[idx].desc = desc; 1543271e1b86SAddy Ke _setup_req(pl330, 0, thrd, idx, &xs); 1544b7d861d9SBoojin Kim 1545b7d861d9SBoojin Kim ret = 0; 1546b7d861d9SBoojin Kim 1547b7d861d9SBoojin Kim xfer_exit: 1548b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1549b7d861d9SBoojin Kim 1550b7d861d9SBoojin Kim return ret; 1551b7d861d9SBoojin Kim } 1552b7d861d9SBoojin Kim 15539dc5a315SLars-Peter Clausen static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err) 15546079d38cSLars-Peter Clausen { 1555b1e51d77SJavier Martinez Canillas struct dma_pl330_chan *pch; 15566079d38cSLars-Peter Clausen unsigned long flags; 15576079d38cSLars-Peter Clausen 1558b1e51d77SJavier Martinez Canillas if (!desc) 1559b1e51d77SJavier Martinez Canillas return; 1560b1e51d77SJavier Martinez Canillas 1561b1e51d77SJavier Martinez Canillas pch = desc->pchan; 1562b1e51d77SJavier Martinez Canillas 15636079d38cSLars-Peter Clausen /* If desc aborted */ 15646079d38cSLars-Peter Clausen if (!pch) 15656079d38cSLars-Peter Clausen return; 15666079d38cSLars-Peter Clausen 15676079d38cSLars-Peter Clausen spin_lock_irqsave(&pch->lock, flags); 15686079d38cSLars-Peter Clausen 15696079d38cSLars-Peter Clausen desc->status = DONE; 15706079d38cSLars-Peter Clausen 15716079d38cSLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 15726079d38cSLars-Peter Clausen 15736079d38cSLars-Peter Clausen tasklet_schedule(&pch->task); 15746079d38cSLars-Peter Clausen } 15756079d38cSLars-Peter Clausen 1576ab2a98aeSAllen Pais static void pl330_dotask(struct tasklet_struct *t) 1577b7d861d9SBoojin Kim { 1578ab2a98aeSAllen Pais struct pl330_dmac *pl330 = from_tasklet(pl330, t, tasks); 1579b7d861d9SBoojin Kim unsigned long flags; 1580b7d861d9SBoojin Kim int i; 1581b7d861d9SBoojin Kim 1582b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1583b7d861d9SBoojin Kim 1584b7d861d9SBoojin Kim /* The DMAC itself gone nuts */ 1585b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_dmac) { 1586b7d861d9SBoojin Kim pl330->state = DYING; 1587b7d861d9SBoojin Kim /* Reset the manager too */ 1588b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = true; 1589b7d861d9SBoojin Kim /* Clear the reset flag */ 1590b7d861d9SBoojin Kim pl330->dmac_tbd.reset_dmac = false; 1591b7d861d9SBoojin Kim } 1592b7d861d9SBoojin Kim 1593b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_mngr) { 1594b7d861d9SBoojin Kim _stop(pl330->manager); 1595b7d861d9SBoojin Kim /* Reset all channels */ 1596f6f2421cSLars-Peter Clausen pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1; 1597b7d861d9SBoojin Kim /* Clear the reset flag */ 1598b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = false; 1599b7d861d9SBoojin Kim } 1600b7d861d9SBoojin Kim 1601f6f2421cSLars-Peter Clausen for (i = 0; i < pl330->pcfg.num_chan; i++) { 1602b7d861d9SBoojin Kim 1603b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_chan & (1 << i)) { 1604b7d861d9SBoojin Kim struct pl330_thread *thrd = &pl330->channels[i]; 1605f6f2421cSLars-Peter Clausen void __iomem *regs = pl330->base; 1606b7d861d9SBoojin Kim enum pl330_op_err err; 1607b7d861d9SBoojin Kim 1608b7d861d9SBoojin Kim _stop(thrd); 1609b7d861d9SBoojin Kim 1610b7d861d9SBoojin Kim if (readl(regs + FSC) & (1 << thrd->id)) 1611b7d861d9SBoojin Kim err = PL330_ERR_FAIL; 1612b7d861d9SBoojin Kim else 1613b7d861d9SBoojin Kim err = PL330_ERR_ABORT; 1614b7d861d9SBoojin Kim 1615b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 16169dc5a315SLars-Peter Clausen dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err); 16179dc5a315SLars-Peter Clausen dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err); 1618b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1619b7d861d9SBoojin Kim 16209dc5a315SLars-Peter Clausen thrd->req[0].desc = NULL; 16219dc5a315SLars-Peter Clausen thrd->req[1].desc = NULL; 16228ed30a14SLars-Peter Clausen thrd->req_running = -1; 1623b7d861d9SBoojin Kim 1624b7d861d9SBoojin Kim /* Clear the reset flag */ 1625b7d861d9SBoojin Kim pl330->dmac_tbd.reset_chan &= ~(1 << i); 1626b7d861d9SBoojin Kim } 1627b7d861d9SBoojin Kim } 1628b7d861d9SBoojin Kim 1629b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1630b7d861d9SBoojin Kim 1631b7d861d9SBoojin Kim return; 1632b7d861d9SBoojin Kim } 1633b7d861d9SBoojin Kim 1634b7d861d9SBoojin Kim /* Returns 1 if state was updated, 0 otherwise */ 1635f6f2421cSLars-Peter Clausen static int pl330_update(struct pl330_dmac *pl330) 1636b7d861d9SBoojin Kim { 1637a3ca8312SQi Hou struct dma_pl330_desc *descdone; 1638b7d861d9SBoojin Kim unsigned long flags; 1639b7d861d9SBoojin Kim void __iomem *regs; 1640b7d861d9SBoojin Kim u32 val; 1641b7d861d9SBoojin Kim int id, ev, ret = 0; 1642b7d861d9SBoojin Kim 1643f6f2421cSLars-Peter Clausen regs = pl330->base; 1644b7d861d9SBoojin Kim 1645b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1646b7d861d9SBoojin Kim 1647b7d861d9SBoojin Kim val = readl(regs + FSM) & 0x1; 1648b7d861d9SBoojin Kim if (val) 1649b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = true; 1650b7d861d9SBoojin Kim else 1651b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = false; 1652b7d861d9SBoojin Kim 1653f6f2421cSLars-Peter Clausen val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1); 1654b7d861d9SBoojin Kim pl330->dmac_tbd.reset_chan |= val; 1655b7d861d9SBoojin Kim if (val) { 1656b7d861d9SBoojin Kim int i = 0; 1657f6f2421cSLars-Peter Clausen while (i < pl330->pcfg.num_chan) { 1658b7d861d9SBoojin Kim if (val & (1 << i)) { 1659f6f2421cSLars-Peter Clausen dev_info(pl330->ddma.dev, 1660b7d861d9SBoojin Kim "Reset Channel-%d\t CS-%x FTC-%x\n", 1661b7d861d9SBoojin Kim i, readl(regs + CS(i)), 1662b7d861d9SBoojin Kim readl(regs + FTC(i))); 1663b7d861d9SBoojin Kim _stop(&pl330->channels[i]); 1664b7d861d9SBoojin Kim } 1665b7d861d9SBoojin Kim i++; 1666b7d861d9SBoojin Kim } 1667b7d861d9SBoojin Kim } 1668b7d861d9SBoojin Kim 1669b7d861d9SBoojin Kim /* Check which event happened i.e, thread notified */ 1670b7d861d9SBoojin Kim val = readl(regs + ES); 1671f6f2421cSLars-Peter Clausen if (pl330->pcfg.num_events < 32 1672f6f2421cSLars-Peter Clausen && val & ~((1 << pl330->pcfg.num_events) - 1)) { 1673b7d861d9SBoojin Kim pl330->dmac_tbd.reset_dmac = true; 1674f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__, 1675f6f2421cSLars-Peter Clausen __LINE__); 1676b7d861d9SBoojin Kim ret = 1; 1677b7d861d9SBoojin Kim goto updt_exit; 1678b7d861d9SBoojin Kim } 1679b7d861d9SBoojin Kim 1680f6f2421cSLars-Peter Clausen for (ev = 0; ev < pl330->pcfg.num_events; ev++) { 1681b7d861d9SBoojin Kim if (val & (1 << ev)) { /* Event occurred */ 1682b7d861d9SBoojin Kim struct pl330_thread *thrd; 1683b7d861d9SBoojin Kim u32 inten = readl(regs + INTEN); 1684b7d861d9SBoojin Kim int active; 1685b7d861d9SBoojin Kim 1686b7d861d9SBoojin Kim /* Clear the event */ 1687b7d861d9SBoojin Kim if (inten & (1 << ev)) 1688b7d861d9SBoojin Kim writel(1 << ev, regs + INTCLR); 1689b7d861d9SBoojin Kim 1690b7d861d9SBoojin Kim ret = 1; 1691b7d861d9SBoojin Kim 1692b7d861d9SBoojin Kim id = pl330->events[ev]; 1693b7d861d9SBoojin Kim 1694b7d861d9SBoojin Kim thrd = &pl330->channels[id]; 1695b7d861d9SBoojin Kim 1696b7d861d9SBoojin Kim active = thrd->req_running; 1697b7d861d9SBoojin Kim if (active == -1) /* Aborted */ 1698b7d861d9SBoojin Kim continue; 1699b7d861d9SBoojin Kim 1700fdec53d5SJavi Merino /* Detach the req */ 17019dc5a315SLars-Peter Clausen descdone = thrd->req[active].desc; 17029dc5a315SLars-Peter Clausen thrd->req[active].desc = NULL; 1703fdec53d5SJavi Merino 17040091b9d6SAddy Ke thrd->req_running = -1; 17050091b9d6SAddy Ke 1706b7d861d9SBoojin Kim /* Get going again ASAP */ 1707b7d861d9SBoojin Kim _start(thrd); 1708b7d861d9SBoojin Kim 1709b7d861d9SBoojin Kim /* For now, just make a list of callbacks to be done */ 17109dc5a315SLars-Peter Clausen list_add_tail(&descdone->rqd, &pl330->req_done); 1711b7d861d9SBoojin Kim } 1712b7d861d9SBoojin Kim } 1713b7d861d9SBoojin Kim 1714b7d861d9SBoojin Kim /* Now that we are in no hurry, do the callbacks */ 1715a3ca8312SQi Hou while (!list_empty(&pl330->req_done)) { 1716a3ca8312SQi Hou descdone = list_first_entry(&pl330->req_done, 1717a3ca8312SQi Hou struct dma_pl330_desc, rqd); 17189dc5a315SLars-Peter Clausen list_del(&descdone->rqd); 1719b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 17209dc5a315SLars-Peter Clausen dma_pl330_rqcb(descdone, PL330_ERR_NONE); 1721b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1722b7d861d9SBoojin Kim } 1723b7d861d9SBoojin Kim 1724b7d861d9SBoojin Kim updt_exit: 1725b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1726b7d861d9SBoojin Kim 1727b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_dmac 1728b7d861d9SBoojin Kim || pl330->dmac_tbd.reset_mngr 1729b7d861d9SBoojin Kim || pl330->dmac_tbd.reset_chan) { 1730b7d861d9SBoojin Kim ret = 1; 1731b7d861d9SBoojin Kim tasklet_schedule(&pl330->tasks); 1732b7d861d9SBoojin Kim } 1733b7d861d9SBoojin Kim 1734b7d861d9SBoojin Kim return ret; 1735b7d861d9SBoojin Kim } 1736b7d861d9SBoojin Kim 1737b7d861d9SBoojin Kim /* Reserve an event */ 1738b7d861d9SBoojin Kim static inline int _alloc_event(struct pl330_thread *thrd) 1739b7d861d9SBoojin Kim { 1740b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 1741b7d861d9SBoojin Kim int ev; 1742b7d861d9SBoojin Kim 1743f6f2421cSLars-Peter Clausen for (ev = 0; ev < pl330->pcfg.num_events; ev++) 1744b7d861d9SBoojin Kim if (pl330->events[ev] == -1) { 1745b7d861d9SBoojin Kim pl330->events[ev] = thrd->id; 1746b7d861d9SBoojin Kim return ev; 1747b7d861d9SBoojin Kim } 1748b7d861d9SBoojin Kim 1749b7d861d9SBoojin Kim return -1; 1750b7d861d9SBoojin Kim } 1751b7d861d9SBoojin Kim 1752f6f2421cSLars-Peter Clausen static bool _chan_ns(const struct pl330_dmac *pl330, int i) 1753b7d861d9SBoojin Kim { 1754f6f2421cSLars-Peter Clausen return pl330->pcfg.irq_ns & (1 << i); 1755b7d861d9SBoojin Kim } 1756b7d861d9SBoojin Kim 1757b7d861d9SBoojin Kim /* Upon success, returns IdentityToken for the 1758b7d861d9SBoojin Kim * allocated channel, NULL otherwise. 1759b7d861d9SBoojin Kim */ 1760f6f2421cSLars-Peter Clausen static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330) 1761b7d861d9SBoojin Kim { 1762b7d861d9SBoojin Kim struct pl330_thread *thrd = NULL; 1763b7d861d9SBoojin Kim int chans, i; 1764b7d861d9SBoojin Kim 1765b7d861d9SBoojin Kim if (pl330->state == DYING) 1766b7d861d9SBoojin Kim return NULL; 1767b7d861d9SBoojin Kim 1768f6f2421cSLars-Peter Clausen chans = pl330->pcfg.num_chan; 1769b7d861d9SBoojin Kim 1770b7d861d9SBoojin Kim for (i = 0; i < chans; i++) { 1771b7d861d9SBoojin Kim thrd = &pl330->channels[i]; 1772b7d861d9SBoojin Kim if ((thrd->free) && (!_manager_ns(thrd) || 1773f6f2421cSLars-Peter Clausen _chan_ns(pl330, i))) { 1774b7d861d9SBoojin Kim thrd->ev = _alloc_event(thrd); 1775b7d861d9SBoojin Kim if (thrd->ev >= 0) { 1776b7d861d9SBoojin Kim thrd->free = false; 1777b7d861d9SBoojin Kim thrd->lstenq = 1; 17789dc5a315SLars-Peter Clausen thrd->req[0].desc = NULL; 17799dc5a315SLars-Peter Clausen thrd->req[1].desc = NULL; 17808ed30a14SLars-Peter Clausen thrd->req_running = -1; 1781b7d861d9SBoojin Kim break; 1782b7d861d9SBoojin Kim } 1783b7d861d9SBoojin Kim } 1784b7d861d9SBoojin Kim thrd = NULL; 1785b7d861d9SBoojin Kim } 1786b7d861d9SBoojin Kim 1787b7d861d9SBoojin Kim return thrd; 1788b7d861d9SBoojin Kim } 1789b7d861d9SBoojin Kim 1790b7d861d9SBoojin Kim /* Release an event */ 1791b7d861d9SBoojin Kim static inline void _free_event(struct pl330_thread *thrd, int ev) 1792b7d861d9SBoojin Kim { 1793b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 1794b7d861d9SBoojin Kim 1795b7d861d9SBoojin Kim /* If the event is valid and was held by the thread */ 1796f6f2421cSLars-Peter Clausen if (ev >= 0 && ev < pl330->pcfg.num_events 1797b7d861d9SBoojin Kim && pl330->events[ev] == thrd->id) 1798b7d861d9SBoojin Kim pl330->events[ev] = -1; 1799b7d861d9SBoojin Kim } 1800b7d861d9SBoojin Kim 180165ad6060SLars-Peter Clausen static void pl330_release_channel(struct pl330_thread *thrd) 1802b7d861d9SBoojin Kim { 1803b7d861d9SBoojin Kim if (!thrd || thrd->free) 1804b7d861d9SBoojin Kim return; 1805b7d861d9SBoojin Kim 1806b7d861d9SBoojin Kim _stop(thrd); 1807b7d861d9SBoojin Kim 18089dc5a315SLars-Peter Clausen dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT); 18099dc5a315SLars-Peter Clausen dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT); 1810b7d861d9SBoojin Kim 1811b7d861d9SBoojin Kim _free_event(thrd, thrd->ev); 1812b7d861d9SBoojin Kim thrd->free = true; 1813b7d861d9SBoojin Kim } 1814b7d861d9SBoojin Kim 1815b7d861d9SBoojin Kim /* Initialize the structure for PL330 configuration, that can be used 1816b7d861d9SBoojin Kim * by the client driver the make best use of the DMAC 1817b7d861d9SBoojin Kim */ 1818f6f2421cSLars-Peter Clausen static void read_dmac_config(struct pl330_dmac *pl330) 1819b7d861d9SBoojin Kim { 1820f6f2421cSLars-Peter Clausen void __iomem *regs = pl330->base; 1821b7d861d9SBoojin Kim u32 val; 1822b7d861d9SBoojin Kim 1823b7d861d9SBoojin Kim val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; 1824b7d861d9SBoojin Kim val &= CRD_DATA_WIDTH_MASK; 1825f6f2421cSLars-Peter Clausen pl330->pcfg.data_bus_width = 8 * (1 << val); 1826b7d861d9SBoojin Kim 1827b7d861d9SBoojin Kim val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; 1828b7d861d9SBoojin Kim val &= CRD_DATA_BUFF_MASK; 1829f6f2421cSLars-Peter Clausen pl330->pcfg.data_buf_dep = val + 1; 1830b7d861d9SBoojin Kim 1831b7d861d9SBoojin Kim val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; 1832b7d861d9SBoojin Kim val &= CR0_NUM_CHANS_MASK; 1833b7d861d9SBoojin Kim val += 1; 1834f6f2421cSLars-Peter Clausen pl330->pcfg.num_chan = val; 1835b7d861d9SBoojin Kim 1836b7d861d9SBoojin Kim val = readl(regs + CR0); 1837b7d861d9SBoojin Kim if (val & CR0_PERIPH_REQ_SET) { 1838b7d861d9SBoojin Kim val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; 1839b7d861d9SBoojin Kim val += 1; 1840f6f2421cSLars-Peter Clausen pl330->pcfg.num_peri = val; 1841f6f2421cSLars-Peter Clausen pl330->pcfg.peri_ns = readl(regs + CR4); 1842b7d861d9SBoojin Kim } else { 1843f6f2421cSLars-Peter Clausen pl330->pcfg.num_peri = 0; 1844b7d861d9SBoojin Kim } 1845b7d861d9SBoojin Kim 1846b7d861d9SBoojin Kim val = readl(regs + CR0); 1847b7d861d9SBoojin Kim if (val & CR0_BOOT_MAN_NS) 1848f6f2421cSLars-Peter Clausen pl330->pcfg.mode |= DMAC_MODE_NS; 1849b7d861d9SBoojin Kim else 1850f6f2421cSLars-Peter Clausen pl330->pcfg.mode &= ~DMAC_MODE_NS; 1851b7d861d9SBoojin Kim 1852b7d861d9SBoojin Kim val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; 1853b7d861d9SBoojin Kim val &= CR0_NUM_EVENTS_MASK; 1854b7d861d9SBoojin Kim val += 1; 1855f6f2421cSLars-Peter Clausen pl330->pcfg.num_events = val; 1856b7d861d9SBoojin Kim 1857f6f2421cSLars-Peter Clausen pl330->pcfg.irq_ns = readl(regs + CR3); 1858b7d861d9SBoojin Kim } 1859b7d861d9SBoojin Kim 1860b7d861d9SBoojin Kim static inline void _reset_thread(struct pl330_thread *thrd) 1861b7d861d9SBoojin Kim { 1862b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 1863b7d861d9SBoojin Kim 1864b7d861d9SBoojin Kim thrd->req[0].mc_cpu = pl330->mcode_cpu 1865f6f2421cSLars-Peter Clausen + (thrd->id * pl330->mcbufsz); 1866b7d861d9SBoojin Kim thrd->req[0].mc_bus = pl330->mcode_bus 1867f6f2421cSLars-Peter Clausen + (thrd->id * pl330->mcbufsz); 18689dc5a315SLars-Peter Clausen thrd->req[0].desc = NULL; 1869b7d861d9SBoojin Kim 1870b7d861d9SBoojin Kim thrd->req[1].mc_cpu = thrd->req[0].mc_cpu 1871f6f2421cSLars-Peter Clausen + pl330->mcbufsz / 2; 1872b7d861d9SBoojin Kim thrd->req[1].mc_bus = thrd->req[0].mc_bus 1873f6f2421cSLars-Peter Clausen + pl330->mcbufsz / 2; 18749dc5a315SLars-Peter Clausen thrd->req[1].desc = NULL; 18758ed30a14SLars-Peter Clausen 18768ed30a14SLars-Peter Clausen thrd->req_running = -1; 1877b7d861d9SBoojin Kim } 1878b7d861d9SBoojin Kim 1879b7d861d9SBoojin Kim static int dmac_alloc_threads(struct pl330_dmac *pl330) 1880b7d861d9SBoojin Kim { 1881f6f2421cSLars-Peter Clausen int chans = pl330->pcfg.num_chan; 1882b7d861d9SBoojin Kim struct pl330_thread *thrd; 1883b7d861d9SBoojin Kim int i; 1884b7d861d9SBoojin Kim 1885b7d861d9SBoojin Kim /* Allocate 1 Manager and 'chans' Channel threads */ 18866396bb22SKees Cook pl330->channels = kcalloc(1 + chans, sizeof(*thrd), 1887b7d861d9SBoojin Kim GFP_KERNEL); 1888b7d861d9SBoojin Kim if (!pl330->channels) 1889b7d861d9SBoojin Kim return -ENOMEM; 1890b7d861d9SBoojin Kim 1891b7d861d9SBoojin Kim /* Init Channel threads */ 1892b7d861d9SBoojin Kim for (i = 0; i < chans; i++) { 1893b7d861d9SBoojin Kim thrd = &pl330->channels[i]; 1894b7d861d9SBoojin Kim thrd->id = i; 1895b7d861d9SBoojin Kim thrd->dmac = pl330; 1896b7d861d9SBoojin Kim _reset_thread(thrd); 1897b7d861d9SBoojin Kim thrd->free = true; 1898b7d861d9SBoojin Kim } 1899b7d861d9SBoojin Kim 1900b7d861d9SBoojin Kim /* MANAGER is indexed at the end */ 1901b7d861d9SBoojin Kim thrd = &pl330->channels[chans]; 1902b7d861d9SBoojin Kim thrd->id = chans; 1903b7d861d9SBoojin Kim thrd->dmac = pl330; 1904b7d861d9SBoojin Kim thrd->free = false; 1905b7d861d9SBoojin Kim pl330->manager = thrd; 1906b7d861d9SBoojin Kim 1907b7d861d9SBoojin Kim return 0; 1908b7d861d9SBoojin Kim } 1909b7d861d9SBoojin Kim 1910b7d861d9SBoojin Kim static int dmac_alloc_resources(struct pl330_dmac *pl330) 1911b7d861d9SBoojin Kim { 1912f6f2421cSLars-Peter Clausen int chans = pl330->pcfg.num_chan; 1913b7d861d9SBoojin Kim int ret; 1914b7d861d9SBoojin Kim 1915b7d861d9SBoojin Kim /* 1916b7d861d9SBoojin Kim * Alloc MicroCode buffer for 'chans' Channel threads. 1917b7d861d9SBoojin Kim * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN) 1918b7d861d9SBoojin Kim */ 19191b2354dbSMitchel Humpherys pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev, 1920f6f2421cSLars-Peter Clausen chans * pl330->mcbufsz, 19211b2354dbSMitchel Humpherys &pl330->mcode_bus, GFP_KERNEL, 19221b2354dbSMitchel Humpherys DMA_ATTR_PRIVILEGED); 1923b7d861d9SBoojin Kim if (!pl330->mcode_cpu) { 1924f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n", 1925b7d861d9SBoojin Kim __func__, __LINE__); 1926b7d861d9SBoojin Kim return -ENOMEM; 1927b7d861d9SBoojin Kim } 1928b7d861d9SBoojin Kim 1929b7d861d9SBoojin Kim ret = dmac_alloc_threads(pl330); 1930b7d861d9SBoojin Kim if (ret) { 1931f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n", 1932b7d861d9SBoojin Kim __func__, __LINE__); 1933d1b622f6SFuqian Huang dma_free_attrs(pl330->ddma.dev, 1934f6f2421cSLars-Peter Clausen chans * pl330->mcbufsz, 1935d1b622f6SFuqian Huang pl330->mcode_cpu, pl330->mcode_bus, 1936d1b622f6SFuqian Huang DMA_ATTR_PRIVILEGED); 1937b7d861d9SBoojin Kim return ret; 1938b7d861d9SBoojin Kim } 1939b7d861d9SBoojin Kim 1940b7d861d9SBoojin Kim return 0; 1941b7d861d9SBoojin Kim } 1942b7d861d9SBoojin Kim 1943f6f2421cSLars-Peter Clausen static int pl330_add(struct pl330_dmac *pl330) 1944b7d861d9SBoojin Kim { 1945b7d861d9SBoojin Kim int i, ret; 1946b7d861d9SBoojin Kim 1947b7d861d9SBoojin Kim /* Check if we can handle this DMAC */ 1948f6f2421cSLars-Peter Clausen if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) { 1949f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n", 1950f6f2421cSLars-Peter Clausen pl330->pcfg.periph_id); 1951b7d861d9SBoojin Kim return -EINVAL; 1952b7d861d9SBoojin Kim } 1953b7d861d9SBoojin Kim 1954b7d861d9SBoojin Kim /* Read the configuration of the DMAC */ 1955f6f2421cSLars-Peter Clausen read_dmac_config(pl330); 1956b7d861d9SBoojin Kim 1957f6f2421cSLars-Peter Clausen if (pl330->pcfg.num_events == 0) { 1958f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n", 1959b7d861d9SBoojin Kim __func__, __LINE__); 1960b7d861d9SBoojin Kim return -EINVAL; 1961b7d861d9SBoojin Kim } 1962b7d861d9SBoojin Kim 1963b7d861d9SBoojin Kim spin_lock_init(&pl330->lock); 1964b7d861d9SBoojin Kim 1965b7d861d9SBoojin Kim INIT_LIST_HEAD(&pl330->req_done); 1966b7d861d9SBoojin Kim 1967b7d861d9SBoojin Kim /* Use default MC buffer size if not provided */ 1968f6f2421cSLars-Peter Clausen if (!pl330->mcbufsz) 1969f6f2421cSLars-Peter Clausen pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2; 1970b7d861d9SBoojin Kim 1971b7d861d9SBoojin Kim /* Mark all events as free */ 1972f6f2421cSLars-Peter Clausen for (i = 0; i < pl330->pcfg.num_events; i++) 1973b7d861d9SBoojin Kim pl330->events[i] = -1; 1974b7d861d9SBoojin Kim 1975b7d861d9SBoojin Kim /* Allocate resources needed by the DMAC */ 1976b7d861d9SBoojin Kim ret = dmac_alloc_resources(pl330); 1977b7d861d9SBoojin Kim if (ret) { 1978f6f2421cSLars-Peter Clausen dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n"); 1979b7d861d9SBoojin Kim return ret; 1980b7d861d9SBoojin Kim } 1981b7d861d9SBoojin Kim 1982ab2a98aeSAllen Pais tasklet_setup(&pl330->tasks, pl330_dotask); 1983b7d861d9SBoojin Kim 1984b7d861d9SBoojin Kim pl330->state = INIT; 1985b7d861d9SBoojin Kim 1986b7d861d9SBoojin Kim return 0; 1987b7d861d9SBoojin Kim } 1988b7d861d9SBoojin Kim 1989b7d861d9SBoojin Kim static int dmac_free_threads(struct pl330_dmac *pl330) 1990b7d861d9SBoojin Kim { 1991b7d861d9SBoojin Kim struct pl330_thread *thrd; 1992b7d861d9SBoojin Kim int i; 1993b7d861d9SBoojin Kim 1994b7d861d9SBoojin Kim /* Release Channel threads */ 1995f6f2421cSLars-Peter Clausen for (i = 0; i < pl330->pcfg.num_chan; i++) { 1996b7d861d9SBoojin Kim thrd = &pl330->channels[i]; 199765ad6060SLars-Peter Clausen pl330_release_channel(thrd); 1998b7d861d9SBoojin Kim } 1999b7d861d9SBoojin Kim 2000b7d861d9SBoojin Kim /* Free memory */ 2001b7d861d9SBoojin Kim kfree(pl330->channels); 2002b7d861d9SBoojin Kim 2003b7d861d9SBoojin Kim return 0; 2004b7d861d9SBoojin Kim } 2005b7d861d9SBoojin Kim 2006f6f2421cSLars-Peter Clausen static void pl330_del(struct pl330_dmac *pl330) 2007b7d861d9SBoojin Kim { 2008b7d861d9SBoojin Kim pl330->state = UNINIT; 2009b7d861d9SBoojin Kim 2010b7d861d9SBoojin Kim tasklet_kill(&pl330->tasks); 2011b7d861d9SBoojin Kim 2012b7d861d9SBoojin Kim /* Free DMAC resources */ 2013f6f2421cSLars-Peter Clausen dmac_free_threads(pl330); 2014b7d861d9SBoojin Kim 2015d1b622f6SFuqian Huang dma_free_attrs(pl330->ddma.dev, 2016f6f2421cSLars-Peter Clausen pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu, 2017d1b622f6SFuqian Huang pl330->mcode_bus, DMA_ATTR_PRIVILEGED); 2018b7d861d9SBoojin Kim } 2019b7d861d9SBoojin Kim 20203e2ec13aSThomas Abraham /* forward declaration */ 20213e2ec13aSThomas Abraham static struct amba_driver pl330_driver; 20223e2ec13aSThomas Abraham 2023b3040e40SJassi Brar static inline struct dma_pl330_chan * 2024b3040e40SJassi Brar to_pchan(struct dma_chan *ch) 2025b3040e40SJassi Brar { 2026b3040e40SJassi Brar if (!ch) 2027b3040e40SJassi Brar return NULL; 2028b3040e40SJassi Brar 2029b3040e40SJassi Brar return container_of(ch, struct dma_pl330_chan, chan); 2030b3040e40SJassi Brar } 2031b3040e40SJassi Brar 2032b3040e40SJassi Brar static inline struct dma_pl330_desc * 2033b3040e40SJassi Brar to_desc(struct dma_async_tx_descriptor *tx) 2034b3040e40SJassi Brar { 2035b3040e40SJassi Brar return container_of(tx, struct dma_pl330_desc, txd); 2036b3040e40SJassi Brar } 2037b3040e40SJassi Brar 2038b3040e40SJassi Brar static inline void fill_queue(struct dma_pl330_chan *pch) 2039b3040e40SJassi Brar { 2040b3040e40SJassi Brar struct dma_pl330_desc *desc; 2041b3040e40SJassi Brar int ret; 2042b3040e40SJassi Brar 2043b3040e40SJassi Brar list_for_each_entry(desc, &pch->work_list, node) { 2044b3040e40SJassi Brar 2045b3040e40SJassi Brar /* If already submitted */ 2046b3040e40SJassi Brar if (desc->status == BUSY) 204730fb980bSJassi Brar continue; 2048b3040e40SJassi Brar 20499dc5a315SLars-Peter Clausen ret = pl330_submit_req(pch->thread, desc); 2050b3040e40SJassi Brar if (!ret) { 2051b3040e40SJassi Brar desc->status = BUSY; 2052b3040e40SJassi Brar } else if (ret == -EAGAIN) { 2053b3040e40SJassi Brar /* QFull or DMAC Dying */ 2054b3040e40SJassi Brar break; 2055b3040e40SJassi Brar } else { 2056b3040e40SJassi Brar /* Unacceptable request */ 2057b3040e40SJassi Brar desc->status = DONE; 2058f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n", 2059b3040e40SJassi Brar __func__, __LINE__, desc->txd.cookie); 2060b3040e40SJassi Brar tasklet_schedule(&pch->task); 2061b3040e40SJassi Brar } 2062b3040e40SJassi Brar } 2063b3040e40SJassi Brar } 2064b3040e40SJassi Brar 2065ab2a98aeSAllen Pais static void pl330_tasklet(struct tasklet_struct *t) 2066b3040e40SJassi Brar { 2067ab2a98aeSAllen Pais struct dma_pl330_chan *pch = from_tasklet(pch, t, task); 2068b3040e40SJassi Brar struct dma_pl330_desc *desc, *_dt; 2069b3040e40SJassi Brar unsigned long flags; 2070ae43b328SKrzysztof Kozlowski bool power_down = false; 2071b3040e40SJassi Brar 2072b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2073b3040e40SJassi Brar 2074b3040e40SJassi Brar /* Pick up ripe tomatoes */ 2075b3040e40SJassi Brar list_for_each_entry_safe(desc, _dt, &pch->work_list, node) 2076b3040e40SJassi Brar if (desc->status == DONE) { 207730c1dc0fSTushar Behera if (!pch->cyclic) 2078f7fbce07SRussell King - ARM Linux dma_cookie_complete(&desc->txd); 207939ff8613SLars-Peter Clausen list_move_tail(&desc->node, &pch->completed_list); 2080b3040e40SJassi Brar } 2081b3040e40SJassi Brar 2082b3040e40SJassi Brar /* Try to submit a req imm. next to the last completed cookie */ 2083b3040e40SJassi Brar fill_queue(pch); 2084b3040e40SJassi Brar 2085ae43b328SKrzysztof Kozlowski if (list_empty(&pch->work_list)) { 2086ae43b328SKrzysztof Kozlowski spin_lock(&pch->thread->dmac->lock); 2087ae43b328SKrzysztof Kozlowski _stop(pch->thread); 2088ae43b328SKrzysztof Kozlowski spin_unlock(&pch->thread->dmac->lock); 2089ae43b328SKrzysztof Kozlowski power_down = true; 20905c9e6c2bSMarek Szyprowski pch->active = false; 2091ae43b328SKrzysztof Kozlowski } else { 2092b3040e40SJassi Brar /* Make sure the PL330 Channel thread is active */ 2093c26939e5SLars-Peter Clausen spin_lock(&pch->thread->dmac->lock); 2094c26939e5SLars-Peter Clausen _start(pch->thread); 2095c26939e5SLars-Peter Clausen spin_unlock(&pch->thread->dmac->lock); 2096ae43b328SKrzysztof Kozlowski } 2097b3040e40SJassi Brar 209839ff8613SLars-Peter Clausen while (!list_empty(&pch->completed_list)) { 2099f08462c6SDave Jiang struct dmaengine_desc_callback cb; 2100b3040e40SJassi Brar 210139ff8613SLars-Peter Clausen desc = list_first_entry(&pch->completed_list, 210239ff8613SLars-Peter Clausen struct dma_pl330_desc, node); 210339ff8613SLars-Peter Clausen 2104f08462c6SDave Jiang dmaengine_desc_get_callback(&desc->txd, &cb); 210539ff8613SLars-Peter Clausen 210639ff8613SLars-Peter Clausen if (pch->cyclic) { 210739ff8613SLars-Peter Clausen desc->status = PREP; 210839ff8613SLars-Peter Clausen list_move_tail(&desc->node, &pch->work_list); 2109ae43b328SKrzysztof Kozlowski if (power_down) { 21105c9e6c2bSMarek Szyprowski pch->active = true; 2111ae43b328SKrzysztof Kozlowski spin_lock(&pch->thread->dmac->lock); 2112ae43b328SKrzysztof Kozlowski _start(pch->thread); 2113ae43b328SKrzysztof Kozlowski spin_unlock(&pch->thread->dmac->lock); 2114ae43b328SKrzysztof Kozlowski power_down = false; 2115ae43b328SKrzysztof Kozlowski } 211639ff8613SLars-Peter Clausen } else { 211739ff8613SLars-Peter Clausen desc->status = FREE; 211839ff8613SLars-Peter Clausen list_move_tail(&desc->node, &pch->dmac->desc_pool); 211939ff8613SLars-Peter Clausen } 212039ff8613SLars-Peter Clausen 2121d38a8c62SDan Williams dma_descriptor_unmap(&desc->txd); 2122d38a8c62SDan Williams 2123f08462c6SDave Jiang if (dmaengine_desc_callback_valid(&cb)) { 212439ff8613SLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 2125f08462c6SDave Jiang dmaengine_desc_callback_invoke(&cb, NULL); 212639ff8613SLars-Peter Clausen spin_lock_irqsave(&pch->lock, flags); 212739ff8613SLars-Peter Clausen } 212839ff8613SLars-Peter Clausen } 212939ff8613SLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 2130ae43b328SKrzysztof Kozlowski 2131ae43b328SKrzysztof Kozlowski /* If work list empty, power down */ 2132ae43b328SKrzysztof Kozlowski if (power_down) { 2133ae43b328SKrzysztof Kozlowski pm_runtime_mark_last_busy(pch->dmac->ddma.dev); 2134ae43b328SKrzysztof Kozlowski pm_runtime_put_autosuspend(pch->dmac->ddma.dev); 2135ae43b328SKrzysztof Kozlowski } 2136b3040e40SJassi Brar } 2137b3040e40SJassi Brar 2138a80258f9SPadmavathi Venna static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec, 2139a80258f9SPadmavathi Venna struct of_dma *ofdma) 2140a80258f9SPadmavathi Venna { 2141a80258f9SPadmavathi Venna int count = dma_spec->args_count; 2142f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = ofdma->of_dma_data; 214370cbb163SLars-Peter Clausen unsigned int chan_id; 2144a80258f9SPadmavathi Venna 2145f6f2421cSLars-Peter Clausen if (!pl330) 2146f6f2421cSLars-Peter Clausen return NULL; 2147f6f2421cSLars-Peter Clausen 2148a80258f9SPadmavathi Venna if (count != 1) 2149a80258f9SPadmavathi Venna return NULL; 2150a80258f9SPadmavathi Venna 215170cbb163SLars-Peter Clausen chan_id = dma_spec->args[0]; 2152f6f2421cSLars-Peter Clausen if (chan_id >= pl330->num_peripherals) 215370cbb163SLars-Peter Clausen return NULL; 2154a80258f9SPadmavathi Venna 2155f6f2421cSLars-Peter Clausen return dma_get_slave_channel(&pl330->peripherals[chan_id].chan); 2156a80258f9SPadmavathi Venna } 2157a80258f9SPadmavathi Venna 2158b3040e40SJassi Brar static int pl330_alloc_chan_resources(struct dma_chan *chan) 2159b3040e40SJassi Brar { 2160b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2161f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2162b3040e40SJassi Brar unsigned long flags; 2163b3040e40SJassi Brar 216491539eb1SIago Abal spin_lock_irqsave(&pl330->lock, flags); 2165b3040e40SJassi Brar 2166d3ee98cdSRussell King - ARM Linux dma_cookie_init(chan); 216742bc9cf4SBoojin Kim pch->cyclic = false; 2168b3040e40SJassi Brar 2169f6f2421cSLars-Peter Clausen pch->thread = pl330_request_channel(pl330); 217065ad6060SLars-Peter Clausen if (!pch->thread) { 217191539eb1SIago Abal spin_unlock_irqrestore(&pl330->lock, flags); 217202747885SInderpal Singh return -ENOMEM; 2173b3040e40SJassi Brar } 2174b3040e40SJassi Brar 2175ab2a98aeSAllen Pais tasklet_setup(&pch->task, pl330_tasklet); 2176b3040e40SJassi Brar 217791539eb1SIago Abal spin_unlock_irqrestore(&pl330->lock, flags); 2178b3040e40SJassi Brar 2179b3040e40SJassi Brar return 1; 2180b3040e40SJassi Brar } 2181b3040e40SJassi Brar 21824d6d74e2SRobin Murphy /* 21834d6d74e2SRobin Murphy * We need the data direction between the DMAC (the dma-mapping "device") and 21844d6d74e2SRobin Murphy * the FIFO (the dmaengine "dev"), from the FIFO's point of view. Confusing! 21854d6d74e2SRobin Murphy */ 21864d6d74e2SRobin Murphy static enum dma_data_direction 21874d6d74e2SRobin Murphy pl330_dma_slave_map_dir(enum dma_transfer_direction dir) 21884d6d74e2SRobin Murphy { 21894d6d74e2SRobin Murphy switch (dir) { 21904d6d74e2SRobin Murphy case DMA_MEM_TO_DEV: 21914d6d74e2SRobin Murphy return DMA_FROM_DEVICE; 21924d6d74e2SRobin Murphy case DMA_DEV_TO_MEM: 21934d6d74e2SRobin Murphy return DMA_TO_DEVICE; 21944d6d74e2SRobin Murphy case DMA_DEV_TO_DEV: 21954d6d74e2SRobin Murphy return DMA_BIDIRECTIONAL; 21964d6d74e2SRobin Murphy default: 21974d6d74e2SRobin Murphy return DMA_NONE; 21984d6d74e2SRobin Murphy } 21994d6d74e2SRobin Murphy } 22004d6d74e2SRobin Murphy 22014d6d74e2SRobin Murphy static void pl330_unprep_slave_fifo(struct dma_pl330_chan *pch) 22024d6d74e2SRobin Murphy { 22034d6d74e2SRobin Murphy if (pch->dir != DMA_NONE) 22044d6d74e2SRobin Murphy dma_unmap_resource(pch->chan.device->dev, pch->fifo_dma, 22054d6d74e2SRobin Murphy 1 << pch->burst_sz, pch->dir, 0); 22064d6d74e2SRobin Murphy pch->dir = DMA_NONE; 22074d6d74e2SRobin Murphy } 22084d6d74e2SRobin Murphy 22094d6d74e2SRobin Murphy 22104d6d74e2SRobin Murphy static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch, 22114d6d74e2SRobin Murphy enum dma_transfer_direction dir) 22124d6d74e2SRobin Murphy { 22134d6d74e2SRobin Murphy struct device *dev = pch->chan.device->dev; 22144d6d74e2SRobin Murphy enum dma_data_direction dma_dir = pl330_dma_slave_map_dir(dir); 22154d6d74e2SRobin Murphy 22164d6d74e2SRobin Murphy /* Already mapped for this config? */ 22174d6d74e2SRobin Murphy if (pch->dir == dma_dir) 22184d6d74e2SRobin Murphy return true; 22194d6d74e2SRobin Murphy 22204d6d74e2SRobin Murphy pl330_unprep_slave_fifo(pch); 22214d6d74e2SRobin Murphy pch->fifo_dma = dma_map_resource(dev, pch->fifo_addr, 22224d6d74e2SRobin Murphy 1 << pch->burst_sz, dma_dir, 0); 22234d6d74e2SRobin Murphy if (dma_mapping_error(dev, pch->fifo_dma)) 22244d6d74e2SRobin Murphy return false; 22254d6d74e2SRobin Murphy 22264d6d74e2SRobin Murphy pch->dir = dma_dir; 22274d6d74e2SRobin Murphy return true; 22284d6d74e2SRobin Murphy } 22294d6d74e2SRobin Murphy 22301d48745bSFrank Mori Hess static int fixup_burst_len(int max_burst_len, int quirks) 22311d48745bSFrank Mori Hess { 223205611a93SSugar Zhang if (max_burst_len > PL330_MAX_BURST) 22331d48745bSFrank Mori Hess return PL330_MAX_BURST; 22341d48745bSFrank Mori Hess else if (max_burst_len < 1) 22351d48745bSFrank Mori Hess return 1; 22361d48745bSFrank Mori Hess else 22371d48745bSFrank Mori Hess return max_burst_len; 22381d48745bSFrank Mori Hess } 22391d48745bSFrank Mori Hess 2240445897cbSVinod Koul static int pl330_config_write(struct dma_chan *chan, 2241445897cbSVinod Koul struct dma_slave_config *slave_config, 2242445897cbSVinod Koul enum dma_transfer_direction direction) 2243740aa957SMaxime Ripard { 2244740aa957SMaxime Ripard struct dma_pl330_chan *pch = to_pchan(chan); 2245740aa957SMaxime Ripard 22464d6d74e2SRobin Murphy pl330_unprep_slave_fifo(pch); 2247445897cbSVinod Koul if (direction == DMA_MEM_TO_DEV) { 2248740aa957SMaxime Ripard if (slave_config->dst_addr) 2249740aa957SMaxime Ripard pch->fifo_addr = slave_config->dst_addr; 2250740aa957SMaxime Ripard if (slave_config->dst_addr_width) 2251740aa957SMaxime Ripard pch->burst_sz = __ffs(slave_config->dst_addr_width); 22521d48745bSFrank Mori Hess pch->burst_len = fixup_burst_len(slave_config->dst_maxburst, 22531d48745bSFrank Mori Hess pch->dmac->quirks); 2254445897cbSVinod Koul } else if (direction == DMA_DEV_TO_MEM) { 2255740aa957SMaxime Ripard if (slave_config->src_addr) 2256740aa957SMaxime Ripard pch->fifo_addr = slave_config->src_addr; 2257740aa957SMaxime Ripard if (slave_config->src_addr_width) 2258740aa957SMaxime Ripard pch->burst_sz = __ffs(slave_config->src_addr_width); 22591d48745bSFrank Mori Hess pch->burst_len = fixup_burst_len(slave_config->src_maxburst, 22601d48745bSFrank Mori Hess pch->dmac->quirks); 2261740aa957SMaxime Ripard } 2262740aa957SMaxime Ripard 2263740aa957SMaxime Ripard return 0; 2264740aa957SMaxime Ripard } 2265740aa957SMaxime Ripard 2266445897cbSVinod Koul static int pl330_config(struct dma_chan *chan, 2267445897cbSVinod Koul struct dma_slave_config *slave_config) 2268445897cbSVinod Koul { 2269445897cbSVinod Koul struct dma_pl330_chan *pch = to_pchan(chan); 2270445897cbSVinod Koul 2271445897cbSVinod Koul memcpy(&pch->slave_config, slave_config, sizeof(*slave_config)); 2272445897cbSVinod Koul 2273445897cbSVinod Koul return 0; 2274445897cbSVinod Koul } 2275445897cbSVinod Koul 2276740aa957SMaxime Ripard static int pl330_terminate_all(struct dma_chan *chan) 2277b3040e40SJassi Brar { 2278b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 227939ff8613SLars-Peter Clausen struct dma_pl330_desc *desc; 2280b3040e40SJassi Brar unsigned long flags; 2281f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 22825c9e6c2bSMarek Szyprowski bool power_down = false; 2283b3040e40SJassi Brar 228481cc6edcSKrzysztof Kozlowski pm_runtime_get_sync(pl330->ddma.dev); 2285b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2286e4975654SJohn Keeping 2287c26939e5SLars-Peter Clausen spin_lock(&pl330->lock); 2288c26939e5SLars-Peter Clausen _stop(pch->thread); 2289c26939e5SLars-Peter Clausen pch->thread->req[0].desc = NULL; 2290c26939e5SLars-Peter Clausen pch->thread->req[1].desc = NULL; 2291c26939e5SLars-Peter Clausen pch->thread->req_running = -1; 2292e4975654SJohn Keeping spin_unlock(&pl330->lock); 2293e4975654SJohn Keeping 22945c9e6c2bSMarek Szyprowski power_down = pch->active; 22955c9e6c2bSMarek Szyprowski pch->active = false; 2296b3040e40SJassi Brar 2297b3040e40SJassi Brar /* Mark all desc done */ 229804abf5daSLars-Peter Clausen list_for_each_entry(desc, &pch->submitted_list, node) { 229904abf5daSLars-Peter Clausen desc->status = FREE; 230004abf5daSLars-Peter Clausen dma_cookie_complete(&desc->txd); 230104abf5daSLars-Peter Clausen } 230204abf5daSLars-Peter Clausen 230339ff8613SLars-Peter Clausen list_for_each_entry(desc, &pch->work_list , node) { 230439ff8613SLars-Peter Clausen desc->status = FREE; 230539ff8613SLars-Peter Clausen dma_cookie_complete(&desc->txd); 2306ae43b886SBoojin Kim } 2307b3040e40SJassi Brar 2308f6f2421cSLars-Peter Clausen list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool); 2309f6f2421cSLars-Peter Clausen list_splice_tail_init(&pch->work_list, &pl330->desc_pool); 2310f6f2421cSLars-Peter Clausen list_splice_tail_init(&pch->completed_list, &pl330->desc_pool); 2311b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 231281cc6edcSKrzysztof Kozlowski pm_runtime_mark_last_busy(pl330->ddma.dev); 23135c9e6c2bSMarek Szyprowski if (power_down) 23145c9e6c2bSMarek Szyprowski pm_runtime_put_autosuspend(pl330->ddma.dev); 231581cc6edcSKrzysztof Kozlowski pm_runtime_put_autosuspend(pl330->ddma.dev); 2316b3040e40SJassi Brar 2317b3040e40SJassi Brar return 0; 2318b3040e40SJassi Brar } 2319b3040e40SJassi Brar 232088987d2cSRobert Baldyga /* 232188987d2cSRobert Baldyga * We don't support DMA_RESUME command because of hardware 232288987d2cSRobert Baldyga * limitations, so after pausing the channel we cannot restore 232388987d2cSRobert Baldyga * it to active state. We have to terminate channel and setup 232488987d2cSRobert Baldyga * DMA transfer again. This pause feature was implemented to 232588987d2cSRobert Baldyga * allow safely read residue before channel termination. 232688987d2cSRobert Baldyga */ 23275503aed8SBen Dooks static int pl330_pause(struct dma_chan *chan) 232888987d2cSRobert Baldyga { 232988987d2cSRobert Baldyga struct dma_pl330_chan *pch = to_pchan(chan); 233088987d2cSRobert Baldyga struct pl330_dmac *pl330 = pch->dmac; 233188987d2cSRobert Baldyga unsigned long flags; 233288987d2cSRobert Baldyga 233388987d2cSRobert Baldyga pm_runtime_get_sync(pl330->ddma.dev); 233488987d2cSRobert Baldyga spin_lock_irqsave(&pch->lock, flags); 233588987d2cSRobert Baldyga 233688987d2cSRobert Baldyga spin_lock(&pl330->lock); 233788987d2cSRobert Baldyga _stop(pch->thread); 233888987d2cSRobert Baldyga spin_unlock(&pl330->lock); 233988987d2cSRobert Baldyga 234088987d2cSRobert Baldyga spin_unlock_irqrestore(&pch->lock, flags); 234188987d2cSRobert Baldyga pm_runtime_mark_last_busy(pl330->ddma.dev); 234288987d2cSRobert Baldyga pm_runtime_put_autosuspend(pl330->ddma.dev); 234388987d2cSRobert Baldyga 234488987d2cSRobert Baldyga return 0; 234588987d2cSRobert Baldyga } 234688987d2cSRobert Baldyga 2347b3040e40SJassi Brar static void pl330_free_chan_resources(struct dma_chan *chan) 2348b3040e40SJassi Brar { 2349b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 235091539eb1SIago Abal struct pl330_dmac *pl330 = pch->dmac; 2351b3040e40SJassi Brar unsigned long flags; 2352b3040e40SJassi Brar 2353b3040e40SJassi Brar tasklet_kill(&pch->task); 2354b3040e40SJassi Brar 2355ae43b328SKrzysztof Kozlowski pm_runtime_get_sync(pch->dmac->ddma.dev); 235691539eb1SIago Abal spin_lock_irqsave(&pl330->lock, flags); 2357da331ba8SBartlomiej Zolnierkiewicz 235865ad6060SLars-Peter Clausen pl330_release_channel(pch->thread); 235965ad6060SLars-Peter Clausen pch->thread = NULL; 2360b3040e40SJassi Brar 236142bc9cf4SBoojin Kim if (pch->cyclic) 236242bc9cf4SBoojin Kim list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); 236342bc9cf4SBoojin Kim 236491539eb1SIago Abal spin_unlock_irqrestore(&pl330->lock, flags); 2365ae43b328SKrzysztof Kozlowski pm_runtime_mark_last_busy(pch->dmac->ddma.dev); 2366ae43b328SKrzysztof Kozlowski pm_runtime_put_autosuspend(pch->dmac->ddma.dev); 23674d6d74e2SRobin Murphy pl330_unprep_slave_fifo(pch); 2368b3040e40SJassi Brar } 2369b3040e40SJassi Brar 23705503aed8SBen Dooks static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch, 2371aee4d1faSRobert Baldyga struct dma_pl330_desc *desc) 2372aee4d1faSRobert Baldyga { 2373aee4d1faSRobert Baldyga struct pl330_thread *thrd = pch->thread; 2374aee4d1faSRobert Baldyga struct pl330_dmac *pl330 = pch->dmac; 2375aee4d1faSRobert Baldyga void __iomem *regs = thrd->dmac->base; 2376aee4d1faSRobert Baldyga u32 val, addr; 2377aee4d1faSRobert Baldyga 2378aee4d1faSRobert Baldyga pm_runtime_get_sync(pl330->ddma.dev); 2379aee4d1faSRobert Baldyga val = addr = 0; 2380aee4d1faSRobert Baldyga if (desc->rqcfg.src_inc) { 2381aee4d1faSRobert Baldyga val = readl(regs + SA(thrd->id)); 2382aee4d1faSRobert Baldyga addr = desc->px.src_addr; 2383aee4d1faSRobert Baldyga } else { 2384aee4d1faSRobert Baldyga val = readl(regs + DA(thrd->id)); 2385aee4d1faSRobert Baldyga addr = desc->px.dst_addr; 2386aee4d1faSRobert Baldyga } 2387aee4d1faSRobert Baldyga pm_runtime_mark_last_busy(pch->dmac->ddma.dev); 2388aee4d1faSRobert Baldyga pm_runtime_put_autosuspend(pl330->ddma.dev); 2389c44da03dSStephen Barber 2390c44da03dSStephen Barber /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */ 2391c44da03dSStephen Barber if (!val) 2392c44da03dSStephen Barber return 0; 2393c44da03dSStephen Barber 2394aee4d1faSRobert Baldyga return val - addr; 2395aee4d1faSRobert Baldyga } 2396aee4d1faSRobert Baldyga 2397b3040e40SJassi Brar static enum dma_status 2398b3040e40SJassi Brar pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, 2399b3040e40SJassi Brar struct dma_tx_state *txstate) 2400b3040e40SJassi Brar { 2401aee4d1faSRobert Baldyga enum dma_status ret; 2402aee4d1faSRobert Baldyga unsigned long flags; 2403d64e9a2cSStephen Barber struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL; 2404aee4d1faSRobert Baldyga struct dma_pl330_chan *pch = to_pchan(chan); 2405aee4d1faSRobert Baldyga unsigned int transferred, residual = 0; 2406aee4d1faSRobert Baldyga 2407aee4d1faSRobert Baldyga ret = dma_cookie_status(chan, cookie, txstate); 2408aee4d1faSRobert Baldyga 2409aee4d1faSRobert Baldyga if (!txstate) 2410aee4d1faSRobert Baldyga return ret; 2411aee4d1faSRobert Baldyga 2412aee4d1faSRobert Baldyga if (ret == DMA_COMPLETE) 2413aee4d1faSRobert Baldyga goto out; 2414aee4d1faSRobert Baldyga 2415aee4d1faSRobert Baldyga spin_lock_irqsave(&pch->lock, flags); 2416a40235a2SHsin-Yu Chao spin_lock(&pch->thread->dmac->lock); 2417aee4d1faSRobert Baldyga 2418aee4d1faSRobert Baldyga if (pch->thread->req_running != -1) 2419aee4d1faSRobert Baldyga running = pch->thread->req[pch->thread->req_running].desc; 2420aee4d1faSRobert Baldyga 2421d64e9a2cSStephen Barber last_enq = pch->thread->req[pch->thread->lstenq].desc; 2422d64e9a2cSStephen Barber 2423aee4d1faSRobert Baldyga /* Check in pending list */ 2424aee4d1faSRobert Baldyga list_for_each_entry(desc, &pch->work_list, node) { 2425aee4d1faSRobert Baldyga if (desc->status == DONE) 2426aee4d1faSRobert Baldyga transferred = desc->bytes_requested; 2427aee4d1faSRobert Baldyga else if (running && desc == running) 2428aee4d1faSRobert Baldyga transferred = 2429aee4d1faSRobert Baldyga pl330_get_current_xferred_count(pch, desc); 2430d64e9a2cSStephen Barber else if (desc->status == BUSY) 2431d64e9a2cSStephen Barber /* 2432d64e9a2cSStephen Barber * Busy but not running means either just enqueued, 2433d64e9a2cSStephen Barber * or finished and not yet marked done 2434d64e9a2cSStephen Barber */ 2435d64e9a2cSStephen Barber if (desc == last_enq) 2436d64e9a2cSStephen Barber transferred = 0; 2437d64e9a2cSStephen Barber else 2438d64e9a2cSStephen Barber transferred = desc->bytes_requested; 2439aee4d1faSRobert Baldyga else 2440aee4d1faSRobert Baldyga transferred = 0; 2441aee4d1faSRobert Baldyga residual += desc->bytes_requested - transferred; 2442aee4d1faSRobert Baldyga if (desc->txd.cookie == cookie) { 244375967b78SBen Dooks switch (desc->status) { 244475967b78SBen Dooks case DONE: 244575967b78SBen Dooks ret = DMA_COMPLETE; 244675967b78SBen Dooks break; 244775967b78SBen Dooks case PREP: 244875967b78SBen Dooks case BUSY: 244975967b78SBen Dooks ret = DMA_IN_PROGRESS; 245075967b78SBen Dooks break; 245175967b78SBen Dooks default: 245275967b78SBen Dooks WARN_ON(1); 245375967b78SBen Dooks } 2454aee4d1faSRobert Baldyga break; 2455aee4d1faSRobert Baldyga } 2456aee4d1faSRobert Baldyga if (desc->last) 2457aee4d1faSRobert Baldyga residual = 0; 2458aee4d1faSRobert Baldyga } 2459a40235a2SHsin-Yu Chao spin_unlock(&pch->thread->dmac->lock); 2460aee4d1faSRobert Baldyga spin_unlock_irqrestore(&pch->lock, flags); 2461aee4d1faSRobert Baldyga 2462aee4d1faSRobert Baldyga out: 2463aee4d1faSRobert Baldyga dma_set_residue(txstate, residual); 2464aee4d1faSRobert Baldyga 2465aee4d1faSRobert Baldyga return ret; 2466b3040e40SJassi Brar } 2467b3040e40SJassi Brar 2468b3040e40SJassi Brar static void pl330_issue_pending(struct dma_chan *chan) 2469b3040e40SJassi Brar { 247004abf5daSLars-Peter Clausen struct dma_pl330_chan *pch = to_pchan(chan); 247104abf5daSLars-Peter Clausen unsigned long flags; 247204abf5daSLars-Peter Clausen 247304abf5daSLars-Peter Clausen spin_lock_irqsave(&pch->lock, flags); 2474ae43b328SKrzysztof Kozlowski if (list_empty(&pch->work_list)) { 2475ae43b328SKrzysztof Kozlowski /* 2476ae43b328SKrzysztof Kozlowski * Warn on nothing pending. Empty submitted_list may 2477ae43b328SKrzysztof Kozlowski * break our pm_runtime usage counter as it is 2478ae43b328SKrzysztof Kozlowski * updated on work_list emptiness status. 2479ae43b328SKrzysztof Kozlowski */ 2480ae43b328SKrzysztof Kozlowski WARN_ON(list_empty(&pch->submitted_list)); 24815c9e6c2bSMarek Szyprowski pch->active = true; 2482ae43b328SKrzysztof Kozlowski pm_runtime_get_sync(pch->dmac->ddma.dev); 2483ae43b328SKrzysztof Kozlowski } 248404abf5daSLars-Peter Clausen list_splice_tail_init(&pch->submitted_list, &pch->work_list); 248504abf5daSLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 248604abf5daSLars-Peter Clausen 248704abf5daSLars-Peter Clausen pl330_tasklet((unsigned long)pch); 2488b3040e40SJassi Brar } 2489b3040e40SJassi Brar 2490b3040e40SJassi Brar /* 2491b3040e40SJassi Brar * We returned the last one of the circular list of descriptor(s) 2492b3040e40SJassi Brar * from prep_xxx, so the argument to submit corresponds to the last 2493b3040e40SJassi Brar * descriptor of the list. 2494b3040e40SJassi Brar */ 2495b3040e40SJassi Brar static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) 2496b3040e40SJassi Brar { 2497b3040e40SJassi Brar struct dma_pl330_desc *desc, *last = to_desc(tx); 2498b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(tx->chan); 2499b3040e40SJassi Brar dma_cookie_t cookie; 2500b3040e40SJassi Brar unsigned long flags; 2501b3040e40SJassi Brar 2502b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2503b3040e40SJassi Brar 2504b3040e40SJassi Brar /* Assign cookies to all nodes */ 2505b3040e40SJassi Brar while (!list_empty(&last->node)) { 2506b3040e40SJassi Brar desc = list_entry(last->node.next, struct dma_pl330_desc, node); 2507fc514460SLars-Peter Clausen if (pch->cyclic) { 2508fc514460SLars-Peter Clausen desc->txd.callback = last->txd.callback; 2509fc514460SLars-Peter Clausen desc->txd.callback_param = last->txd.callback_param; 2510fc514460SLars-Peter Clausen } 25115dd90e5bSKrzysztof Kozlowski desc->last = false; 2512b3040e40SJassi Brar 2513884485e1SRussell King - ARM Linux dma_cookie_assign(&desc->txd); 2514b3040e40SJassi Brar 251504abf5daSLars-Peter Clausen list_move_tail(&desc->node, &pch->submitted_list); 2516b3040e40SJassi Brar } 2517b3040e40SJassi Brar 2518aee4d1faSRobert Baldyga last->last = true; 2519884485e1SRussell King - ARM Linux cookie = dma_cookie_assign(&last->txd); 252004abf5daSLars-Peter Clausen list_add_tail(&last->node, &pch->submitted_list); 2521b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 2522b3040e40SJassi Brar 2523b3040e40SJassi Brar return cookie; 2524b3040e40SJassi Brar } 2525b3040e40SJassi Brar 2526b3040e40SJassi Brar static inline void _init_desc(struct dma_pl330_desc *desc) 2527b3040e40SJassi Brar { 2528b3040e40SJassi Brar desc->rqcfg.swap = SWAP_NO; 2529f0564c7eSLars-Peter Clausen desc->rqcfg.scctl = CCTRL0; 2530f0564c7eSLars-Peter Clausen desc->rqcfg.dcctl = CCTRL0; 2531b3040e40SJassi Brar desc->txd.tx_submit = pl330_tx_submit; 2532b3040e40SJassi Brar 2533b3040e40SJassi Brar INIT_LIST_HEAD(&desc->node); 2534b3040e40SJassi Brar } 2535b3040e40SJassi Brar 2536b3040e40SJassi Brar /* Returns the number of descriptors added to the DMAC pool */ 2537e5887103SAlexander Kochetkov static int add_desc(struct list_head *pool, spinlock_t *lock, 2538e5887103SAlexander Kochetkov gfp_t flg, int count) 2539b3040e40SJassi Brar { 2540b3040e40SJassi Brar struct dma_pl330_desc *desc; 2541b3040e40SJassi Brar unsigned long flags; 2542b3040e40SJassi Brar int i; 2543b3040e40SJassi Brar 25440baf8f6aSWill Deacon desc = kcalloc(count, sizeof(*desc), flg); 2545b3040e40SJassi Brar if (!desc) 2546b3040e40SJassi Brar return 0; 2547b3040e40SJassi Brar 2548e5887103SAlexander Kochetkov spin_lock_irqsave(lock, flags); 2549b3040e40SJassi Brar 2550b3040e40SJassi Brar for (i = 0; i < count; i++) { 2551b3040e40SJassi Brar _init_desc(&desc[i]); 2552e5887103SAlexander Kochetkov list_add_tail(&desc[i].node, pool); 2553b3040e40SJassi Brar } 2554b3040e40SJassi Brar 2555e5887103SAlexander Kochetkov spin_unlock_irqrestore(lock, flags); 2556b3040e40SJassi Brar 2557b3040e40SJassi Brar return count; 2558b3040e40SJassi Brar } 2559b3040e40SJassi Brar 2560e5887103SAlexander Kochetkov static struct dma_pl330_desc *pluck_desc(struct list_head *pool, 2561e5887103SAlexander Kochetkov spinlock_t *lock) 2562b3040e40SJassi Brar { 2563b3040e40SJassi Brar struct dma_pl330_desc *desc = NULL; 2564b3040e40SJassi Brar unsigned long flags; 2565b3040e40SJassi Brar 2566e5887103SAlexander Kochetkov spin_lock_irqsave(lock, flags); 2567b3040e40SJassi Brar 2568e5887103SAlexander Kochetkov if (!list_empty(pool)) { 2569e5887103SAlexander Kochetkov desc = list_entry(pool->next, 2570b3040e40SJassi Brar struct dma_pl330_desc, node); 2571b3040e40SJassi Brar 2572b3040e40SJassi Brar list_del_init(&desc->node); 2573b3040e40SJassi Brar 2574b3040e40SJassi Brar desc->status = PREP; 2575b3040e40SJassi Brar desc->txd.callback = NULL; 2576b3040e40SJassi Brar } 2577b3040e40SJassi Brar 2578e5887103SAlexander Kochetkov spin_unlock_irqrestore(lock, flags); 2579b3040e40SJassi Brar 2580b3040e40SJassi Brar return desc; 2581b3040e40SJassi Brar } 2582b3040e40SJassi Brar 2583b3040e40SJassi Brar static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) 2584b3040e40SJassi Brar { 2585f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2586cd072515SThomas Abraham u8 *peri_id = pch->chan.private; 2587b3040e40SJassi Brar struct dma_pl330_desc *desc; 2588b3040e40SJassi Brar 2589b3040e40SJassi Brar /* Pluck one desc from the pool of DMAC */ 2590e5887103SAlexander Kochetkov desc = pluck_desc(&pl330->desc_pool, &pl330->pool_lock); 2591b3040e40SJassi Brar 2592b3040e40SJassi Brar /* If the DMAC pool is empty, alloc new */ 2593b3040e40SJassi Brar if (!desc) { 2594e5887103SAlexander Kochetkov DEFINE_SPINLOCK(lock); 2595e5887103SAlexander Kochetkov LIST_HEAD(pool); 2596e5887103SAlexander Kochetkov 2597e5887103SAlexander Kochetkov if (!add_desc(&pool, &lock, GFP_ATOMIC, 1)) 2598b3040e40SJassi Brar return NULL; 2599b3040e40SJassi Brar 2600e5887103SAlexander Kochetkov desc = pluck_desc(&pool, &lock); 2601e5887103SAlexander Kochetkov WARN_ON(!desc || !list_empty(&pool)); 2602b3040e40SJassi Brar } 2603b3040e40SJassi Brar 2604b3040e40SJassi Brar /* Initialize the descriptor */ 2605b3040e40SJassi Brar desc->pchan = pch; 2606b3040e40SJassi Brar desc->txd.cookie = 0; 2607b3040e40SJassi Brar async_tx_ack(&desc->txd); 2608b3040e40SJassi Brar 26099dc5a315SLars-Peter Clausen desc->peri = peri_id ? pch->chan.chan_id : 0; 2610f6f2421cSLars-Peter Clausen desc->rqcfg.pcfg = &pch->dmac->pcfg; 2611b3040e40SJassi Brar 2612b3040e40SJassi Brar dma_async_tx_descriptor_init(&desc->txd, &pch->chan); 2613b3040e40SJassi Brar 2614b3040e40SJassi Brar return desc; 2615b3040e40SJassi Brar } 2616b3040e40SJassi Brar 2617b3040e40SJassi Brar static inline void fill_px(struct pl330_xfer *px, 2618b3040e40SJassi Brar dma_addr_t dst, dma_addr_t src, size_t len) 2619b3040e40SJassi Brar { 2620b3040e40SJassi Brar px->bytes = len; 2621b3040e40SJassi Brar px->dst_addr = dst; 2622b3040e40SJassi Brar px->src_addr = src; 2623b3040e40SJassi Brar } 2624b3040e40SJassi Brar 2625b3040e40SJassi Brar static struct dma_pl330_desc * 2626b3040e40SJassi Brar __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, 2627b3040e40SJassi Brar dma_addr_t src, size_t len) 2628b3040e40SJassi Brar { 2629b3040e40SJassi Brar struct dma_pl330_desc *desc = pl330_get_desc(pch); 2630b3040e40SJassi Brar 2631b3040e40SJassi Brar if (!desc) { 2632f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", 2633b3040e40SJassi Brar __func__, __LINE__); 2634b3040e40SJassi Brar return NULL; 2635b3040e40SJassi Brar } 2636b3040e40SJassi Brar 2637b3040e40SJassi Brar /* 2638b3040e40SJassi Brar * Ideally we should lookout for reqs bigger than 2639b3040e40SJassi Brar * those that can be programmed with 256 bytes of 2640b3040e40SJassi Brar * MC buffer, but considering a req size is seldom 2641b3040e40SJassi Brar * going to be word-unaligned and more than 200MB, 2642b3040e40SJassi Brar * we take it easy. 2643b3040e40SJassi Brar * Also, should the limit is reached we'd rather 2644b3040e40SJassi Brar * have the platform increase MC buffer size than 2645b3040e40SJassi Brar * complicating this API driver. 2646b3040e40SJassi Brar */ 2647b3040e40SJassi Brar fill_px(&desc->px, dst, src, len); 2648b3040e40SJassi Brar 2649b3040e40SJassi Brar return desc; 2650b3040e40SJassi Brar } 2651b3040e40SJassi Brar 2652b3040e40SJassi Brar /* Call after fixing burst size */ 2653b3040e40SJassi Brar static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) 2654b3040e40SJassi Brar { 2655b3040e40SJassi Brar struct dma_pl330_chan *pch = desc->pchan; 2656f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2657b3040e40SJassi Brar int burst_len; 2658b3040e40SJassi Brar 2659f6f2421cSLars-Peter Clausen burst_len = pl330->pcfg.data_bus_width / 8; 2660c27f9556SJon Medhurst burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan; 2661b3040e40SJassi Brar burst_len >>= desc->rqcfg.brst_size; 2662b3040e40SJassi Brar 2663b3040e40SJassi Brar /* src/dst_burst_len can't be more than 16 */ 26641d48745bSFrank Mori Hess if (burst_len > PL330_MAX_BURST) 26651d48745bSFrank Mori Hess burst_len = PL330_MAX_BURST; 2666b3040e40SJassi Brar 2667b3040e40SJassi Brar return burst_len; 2668b3040e40SJassi Brar } 2669b3040e40SJassi Brar 267042bc9cf4SBoojin Kim static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( 267142bc9cf4SBoojin Kim struct dma_chan *chan, dma_addr_t dma_addr, size_t len, 2672185ecb5fSAlexandre Bounine size_t period_len, enum dma_transfer_direction direction, 267331c1e5a1SLaurent Pinchart unsigned long flags) 267442bc9cf4SBoojin Kim { 2675fc514460SLars-Peter Clausen struct dma_pl330_desc *desc = NULL, *first = NULL; 267642bc9cf4SBoojin Kim struct dma_pl330_chan *pch = to_pchan(chan); 2677f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2678fc514460SLars-Peter Clausen unsigned int i; 267942bc9cf4SBoojin Kim dma_addr_t dst; 268042bc9cf4SBoojin Kim dma_addr_t src; 268142bc9cf4SBoojin Kim 2682fc514460SLars-Peter Clausen if (len % period_len != 0) 2683fc514460SLars-Peter Clausen return NULL; 2684fc514460SLars-Peter Clausen 2685fc514460SLars-Peter Clausen if (!is_slave_direction(direction)) { 2686f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n", 2687fc514460SLars-Peter Clausen __func__, __LINE__); 2688fc514460SLars-Peter Clausen return NULL; 2689fc514460SLars-Peter Clausen } 2690fc514460SLars-Peter Clausen 2691445897cbSVinod Koul pl330_config_write(chan, &pch->slave_config, direction); 2692445897cbSVinod Koul 26934d6d74e2SRobin Murphy if (!pl330_prep_slave_fifo(pch, direction)) 26944d6d74e2SRobin Murphy return NULL; 26954d6d74e2SRobin Murphy 2696fc514460SLars-Peter Clausen for (i = 0; i < len / period_len; i++) { 269742bc9cf4SBoojin Kim desc = pl330_get_desc(pch); 269842bc9cf4SBoojin Kim if (!desc) { 2699f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", 270042bc9cf4SBoojin Kim __func__, __LINE__); 2701fc514460SLars-Peter Clausen 2702fc514460SLars-Peter Clausen if (!first) 2703fc514460SLars-Peter Clausen return NULL; 2704fc514460SLars-Peter Clausen 2705f6f2421cSLars-Peter Clausen spin_lock_irqsave(&pl330->pool_lock, flags); 2706fc514460SLars-Peter Clausen 2707fc514460SLars-Peter Clausen while (!list_empty(&first->node)) { 2708fc514460SLars-Peter Clausen desc = list_entry(first->node.next, 2709fc514460SLars-Peter Clausen struct dma_pl330_desc, node); 2710f6f2421cSLars-Peter Clausen list_move_tail(&desc->node, &pl330->desc_pool); 2711fc514460SLars-Peter Clausen } 2712fc514460SLars-Peter Clausen 2713f6f2421cSLars-Peter Clausen list_move_tail(&first->node, &pl330->desc_pool); 2714fc514460SLars-Peter Clausen 2715f6f2421cSLars-Peter Clausen spin_unlock_irqrestore(&pl330->pool_lock, flags); 2716fc514460SLars-Peter Clausen 271742bc9cf4SBoojin Kim return NULL; 271842bc9cf4SBoojin Kim } 271942bc9cf4SBoojin Kim 272042bc9cf4SBoojin Kim switch (direction) { 2721db8196dfSVinod Koul case DMA_MEM_TO_DEV: 272242bc9cf4SBoojin Kim desc->rqcfg.src_inc = 1; 272342bc9cf4SBoojin Kim desc->rqcfg.dst_inc = 0; 272442bc9cf4SBoojin Kim src = dma_addr; 27254d6d74e2SRobin Murphy dst = pch->fifo_dma; 272642bc9cf4SBoojin Kim break; 2727db8196dfSVinod Koul case DMA_DEV_TO_MEM: 272842bc9cf4SBoojin Kim desc->rqcfg.src_inc = 0; 272942bc9cf4SBoojin Kim desc->rqcfg.dst_inc = 1; 27304d6d74e2SRobin Murphy src = pch->fifo_dma; 273142bc9cf4SBoojin Kim dst = dma_addr; 273242bc9cf4SBoojin Kim break; 273342bc9cf4SBoojin Kim default: 2734fc514460SLars-Peter Clausen break; 273542bc9cf4SBoojin Kim } 273642bc9cf4SBoojin Kim 27379dc5a315SLars-Peter Clausen desc->rqtype = direction; 273842bc9cf4SBoojin Kim desc->rqcfg.brst_size = pch->burst_sz; 27391d48745bSFrank Mori Hess desc->rqcfg.brst_len = pch->burst_len; 2740aee4d1faSRobert Baldyga desc->bytes_requested = period_len; 2741fc514460SLars-Peter Clausen fill_px(&desc->px, dst, src, period_len); 2742fc514460SLars-Peter Clausen 2743fc514460SLars-Peter Clausen if (!first) 2744fc514460SLars-Peter Clausen first = desc; 2745fc514460SLars-Peter Clausen else 2746fc514460SLars-Peter Clausen list_add_tail(&desc->node, &first->node); 2747fc514460SLars-Peter Clausen 2748fc514460SLars-Peter Clausen dma_addr += period_len; 2749fc514460SLars-Peter Clausen } 2750fc514460SLars-Peter Clausen 2751fc514460SLars-Peter Clausen if (!desc) 2752fc514460SLars-Peter Clausen return NULL; 275342bc9cf4SBoojin Kim 275442bc9cf4SBoojin Kim pch->cyclic = true; 2755fc514460SLars-Peter Clausen desc->txd.flags = flags; 275642bc9cf4SBoojin Kim 275742bc9cf4SBoojin Kim return &desc->txd; 275842bc9cf4SBoojin Kim } 275942bc9cf4SBoojin Kim 2760b3040e40SJassi Brar static struct dma_async_tx_descriptor * 2761b3040e40SJassi Brar pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, 2762b3040e40SJassi Brar dma_addr_t src, size_t len, unsigned long flags) 2763b3040e40SJassi Brar { 2764b3040e40SJassi Brar struct dma_pl330_desc *desc; 2765b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2766f5636854SManinder Singh struct pl330_dmac *pl330; 2767b3040e40SJassi Brar int burst; 2768b3040e40SJassi Brar 27694e0e6109SRob Herring if (unlikely(!pch || !len)) 2770b3040e40SJassi Brar return NULL; 2771b3040e40SJassi Brar 2772f5636854SManinder Singh pl330 = pch->dmac; 2773f5636854SManinder Singh 2774b3040e40SJassi Brar desc = __pl330_prep_dma_memcpy(pch, dst, src, len); 2775b3040e40SJassi Brar if (!desc) 2776b3040e40SJassi Brar return NULL; 2777b3040e40SJassi Brar 2778b3040e40SJassi Brar desc->rqcfg.src_inc = 1; 2779b3040e40SJassi Brar desc->rqcfg.dst_inc = 1; 27809dc5a315SLars-Peter Clausen desc->rqtype = DMA_MEM_TO_MEM; 2781b3040e40SJassi Brar 2782b3040e40SJassi Brar /* Select max possible burst size */ 2783f6f2421cSLars-Peter Clausen burst = pl330->pcfg.data_bus_width / 8; 2784b3040e40SJassi Brar 2785137bd110SJon Medhurst /* 2786137bd110SJon Medhurst * Make sure we use a burst size that aligns with all the memcpy 2787137bd110SJon Medhurst * parameters because our DMA programming algorithm doesn't cope with 2788137bd110SJon Medhurst * transfers which straddle an entry in the DMA device's MFIFO. 2789137bd110SJon Medhurst */ 2790137bd110SJon Medhurst while ((src | dst | len) & (burst - 1)) 2791b3040e40SJassi Brar burst /= 2; 2792b3040e40SJassi Brar 2793b3040e40SJassi Brar desc->rqcfg.brst_size = 0; 2794b3040e40SJassi Brar while (burst != (1 << desc->rqcfg.brst_size)) 2795b3040e40SJassi Brar desc->rqcfg.brst_size++; 2796b3040e40SJassi Brar 27970661cef6SMarek Szyprowski desc->rqcfg.brst_len = get_burst_len(desc, len); 2798137bd110SJon Medhurst /* 2799137bd110SJon Medhurst * If burst size is smaller than bus width then make sure we only 2800137bd110SJon Medhurst * transfer one at a time to avoid a burst stradling an MFIFO entry. 2801137bd110SJon Medhurst */ 2802137bd110SJon Medhurst if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width) 2803137bd110SJon Medhurst desc->rqcfg.brst_len = 1; 2804137bd110SJon Medhurst 2805ae128293SKrzysztof Kozlowski desc->bytes_requested = len; 2806b3040e40SJassi Brar 2807b3040e40SJassi Brar desc->txd.flags = flags; 2808b3040e40SJassi Brar 2809b3040e40SJassi Brar return &desc->txd; 2810b3040e40SJassi Brar } 2811b3040e40SJassi Brar 2812f6f2421cSLars-Peter Clausen static void __pl330_giveback_desc(struct pl330_dmac *pl330, 281352a9d179SChanho Park struct dma_pl330_desc *first) 281452a9d179SChanho Park { 281552a9d179SChanho Park unsigned long flags; 281652a9d179SChanho Park struct dma_pl330_desc *desc; 281752a9d179SChanho Park 281852a9d179SChanho Park if (!first) 281952a9d179SChanho Park return; 282052a9d179SChanho Park 2821f6f2421cSLars-Peter Clausen spin_lock_irqsave(&pl330->pool_lock, flags); 282252a9d179SChanho Park 282352a9d179SChanho Park while (!list_empty(&first->node)) { 282452a9d179SChanho Park desc = list_entry(first->node.next, 282552a9d179SChanho Park struct dma_pl330_desc, node); 2826f6f2421cSLars-Peter Clausen list_move_tail(&desc->node, &pl330->desc_pool); 282752a9d179SChanho Park } 282852a9d179SChanho Park 2829f6f2421cSLars-Peter Clausen list_move_tail(&first->node, &pl330->desc_pool); 283052a9d179SChanho Park 2831f6f2421cSLars-Peter Clausen spin_unlock_irqrestore(&pl330->pool_lock, flags); 283252a9d179SChanho Park } 283352a9d179SChanho Park 2834b3040e40SJassi Brar static struct dma_async_tx_descriptor * 2835b3040e40SJassi Brar pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 2836db8196dfSVinod Koul unsigned int sg_len, enum dma_transfer_direction direction, 2837185ecb5fSAlexandre Bounine unsigned long flg, void *context) 2838b3040e40SJassi Brar { 2839b3040e40SJassi Brar struct dma_pl330_desc *first, *desc = NULL; 2840b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2841b3040e40SJassi Brar struct scatterlist *sg; 28421b9bb715SBoojin Kim int i; 2843b3040e40SJassi Brar 2844cd072515SThomas Abraham if (unlikely(!pch || !sgl || !sg_len)) 2845b3040e40SJassi Brar return NULL; 2846b3040e40SJassi Brar 2847445897cbSVinod Koul pl330_config_write(chan, &pch->slave_config, direction); 2848445897cbSVinod Koul 28494d6d74e2SRobin Murphy if (!pl330_prep_slave_fifo(pch, direction)) 28504d6d74e2SRobin Murphy return NULL; 2851b3040e40SJassi Brar 2852b3040e40SJassi Brar first = NULL; 2853b3040e40SJassi Brar 2854b3040e40SJassi Brar for_each_sg(sgl, sg, sg_len, i) { 2855b3040e40SJassi Brar 2856b3040e40SJassi Brar desc = pl330_get_desc(pch); 2857b3040e40SJassi Brar if (!desc) { 2858f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = pch->dmac; 2859b3040e40SJassi Brar 2860f6f2421cSLars-Peter Clausen dev_err(pch->dmac->ddma.dev, 2861b3040e40SJassi Brar "%s:%d Unable to fetch desc\n", 2862b3040e40SJassi Brar __func__, __LINE__); 2863f6f2421cSLars-Peter Clausen __pl330_giveback_desc(pl330, first); 2864b3040e40SJassi Brar 2865b3040e40SJassi Brar return NULL; 2866b3040e40SJassi Brar } 2867b3040e40SJassi Brar 2868b3040e40SJassi Brar if (!first) 2869b3040e40SJassi Brar first = desc; 2870b3040e40SJassi Brar else 2871b3040e40SJassi Brar list_add_tail(&desc->node, &first->node); 2872b3040e40SJassi Brar 2873db8196dfSVinod Koul if (direction == DMA_MEM_TO_DEV) { 2874b3040e40SJassi Brar desc->rqcfg.src_inc = 1; 2875b3040e40SJassi Brar desc->rqcfg.dst_inc = 0; 28764d6d74e2SRobin Murphy fill_px(&desc->px, pch->fifo_dma, sg_dma_address(sg), 28774d6d74e2SRobin Murphy sg_dma_len(sg)); 2878b3040e40SJassi Brar } else { 2879b3040e40SJassi Brar desc->rqcfg.src_inc = 0; 2880b3040e40SJassi Brar desc->rqcfg.dst_inc = 1; 28814d6d74e2SRobin Murphy fill_px(&desc->px, sg_dma_address(sg), pch->fifo_dma, 28824d6d74e2SRobin Murphy sg_dma_len(sg)); 2883b3040e40SJassi Brar } 2884b3040e40SJassi Brar 28851b9bb715SBoojin Kim desc->rqcfg.brst_size = pch->burst_sz; 28861d48745bSFrank Mori Hess desc->rqcfg.brst_len = pch->burst_len; 28879dc5a315SLars-Peter Clausen desc->rqtype = direction; 2888aee4d1faSRobert Baldyga desc->bytes_requested = sg_dma_len(sg); 2889b3040e40SJassi Brar } 2890b3040e40SJassi Brar 2891b3040e40SJassi Brar /* Return the last desc in the chain */ 2892b3040e40SJassi Brar desc->txd.flags = flg; 2893b3040e40SJassi Brar return &desc->txd; 2894b3040e40SJassi Brar } 2895b3040e40SJassi Brar 2896b3040e40SJassi Brar static irqreturn_t pl330_irq_handler(int irq, void *data) 2897b3040e40SJassi Brar { 2898b3040e40SJassi Brar if (pl330_update(data)) 2899b3040e40SJassi Brar return IRQ_HANDLED; 2900b3040e40SJassi Brar else 2901b3040e40SJassi Brar return IRQ_NONE; 2902b3040e40SJassi Brar } 2903b3040e40SJassi Brar 2904ca38ff13SLars-Peter Clausen #define PL330_DMA_BUSWIDTHS \ 2905ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ 2906ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 2907ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 2908ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ 2909ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) 2910ca38ff13SLars-Peter Clausen 2911b45aef3aSKatsuhiro Suzuki #ifdef CONFIG_DEBUG_FS 2912b45aef3aSKatsuhiro Suzuki static int pl330_debugfs_show(struct seq_file *s, void *data) 2913b45aef3aSKatsuhiro Suzuki { 2914b45aef3aSKatsuhiro Suzuki struct pl330_dmac *pl330 = s->private; 2915b45aef3aSKatsuhiro Suzuki int chans, pchs, ch, pr; 2916b45aef3aSKatsuhiro Suzuki 2917b45aef3aSKatsuhiro Suzuki chans = pl330->pcfg.num_chan; 2918b45aef3aSKatsuhiro Suzuki pchs = pl330->num_peripherals; 2919b45aef3aSKatsuhiro Suzuki 2920b45aef3aSKatsuhiro Suzuki seq_puts(s, "PL330 physical channels:\n"); 2921b45aef3aSKatsuhiro Suzuki seq_puts(s, "THREAD:\t\tCHANNEL:\n"); 2922b45aef3aSKatsuhiro Suzuki seq_puts(s, "--------\t-----\n"); 2923b45aef3aSKatsuhiro Suzuki for (ch = 0; ch < chans; ch++) { 2924b45aef3aSKatsuhiro Suzuki struct pl330_thread *thrd = &pl330->channels[ch]; 2925b45aef3aSKatsuhiro Suzuki int found = -1; 2926b45aef3aSKatsuhiro Suzuki 2927b45aef3aSKatsuhiro Suzuki for (pr = 0; pr < pchs; pr++) { 2928b45aef3aSKatsuhiro Suzuki struct dma_pl330_chan *pch = &pl330->peripherals[pr]; 2929b45aef3aSKatsuhiro Suzuki 2930b45aef3aSKatsuhiro Suzuki if (!pch->thread || thrd->id != pch->thread->id) 2931b45aef3aSKatsuhiro Suzuki continue; 2932b45aef3aSKatsuhiro Suzuki 2933b45aef3aSKatsuhiro Suzuki found = pr; 2934b45aef3aSKatsuhiro Suzuki } 2935b45aef3aSKatsuhiro Suzuki 2936b45aef3aSKatsuhiro Suzuki seq_printf(s, "%d\t\t", thrd->id); 2937b45aef3aSKatsuhiro Suzuki if (found == -1) 2938b45aef3aSKatsuhiro Suzuki seq_puts(s, "--\n"); 2939b45aef3aSKatsuhiro Suzuki else 2940b45aef3aSKatsuhiro Suzuki seq_printf(s, "%d\n", found); 2941b45aef3aSKatsuhiro Suzuki } 2942b45aef3aSKatsuhiro Suzuki 2943b45aef3aSKatsuhiro Suzuki return 0; 2944b45aef3aSKatsuhiro Suzuki } 2945b45aef3aSKatsuhiro Suzuki 2946b45aef3aSKatsuhiro Suzuki DEFINE_SHOW_ATTRIBUTE(pl330_debugfs); 2947b45aef3aSKatsuhiro Suzuki 2948b45aef3aSKatsuhiro Suzuki static inline void init_pl330_debugfs(struct pl330_dmac *pl330) 2949b45aef3aSKatsuhiro Suzuki { 2950b45aef3aSKatsuhiro Suzuki debugfs_create_file(dev_name(pl330->ddma.dev), 2951b45aef3aSKatsuhiro Suzuki S_IFREG | 0444, NULL, pl330, 2952b45aef3aSKatsuhiro Suzuki &pl330_debugfs_fops); 2953b45aef3aSKatsuhiro Suzuki } 2954b45aef3aSKatsuhiro Suzuki #else 2955b45aef3aSKatsuhiro Suzuki static inline void init_pl330_debugfs(struct pl330_dmac *pl330) 2956b45aef3aSKatsuhiro Suzuki { 2957b45aef3aSKatsuhiro Suzuki } 2958b45aef3aSKatsuhiro Suzuki #endif 2959b45aef3aSKatsuhiro Suzuki 2960b816ccc5SKrzysztof Kozlowski /* 2961b816ccc5SKrzysztof Kozlowski * Runtime PM callbacks are provided by amba/bus.c driver. 2962b816ccc5SKrzysztof Kozlowski * 2963b816ccc5SKrzysztof Kozlowski * It is assumed here that IRQ safe runtime PM is chosen in probe and amba 2964b816ccc5SKrzysztof Kozlowski * bus driver will only disable/enable the clock in runtime PM callbacks. 2965b816ccc5SKrzysztof Kozlowski */ 2966b816ccc5SKrzysztof Kozlowski static int __maybe_unused pl330_suspend(struct device *dev) 2967b816ccc5SKrzysztof Kozlowski { 2968b816ccc5SKrzysztof Kozlowski struct amba_device *pcdev = to_amba_device(dev); 2969b816ccc5SKrzysztof Kozlowski 2970a39cddc9SUlf Hansson pm_runtime_force_suspend(dev); 2971b816ccc5SKrzysztof Kozlowski amba_pclk_unprepare(pcdev); 2972b816ccc5SKrzysztof Kozlowski 2973b816ccc5SKrzysztof Kozlowski return 0; 2974b816ccc5SKrzysztof Kozlowski } 2975b816ccc5SKrzysztof Kozlowski 2976b816ccc5SKrzysztof Kozlowski static int __maybe_unused pl330_resume(struct device *dev) 2977b816ccc5SKrzysztof Kozlowski { 2978b816ccc5SKrzysztof Kozlowski struct amba_device *pcdev = to_amba_device(dev); 2979b816ccc5SKrzysztof Kozlowski int ret; 2980b816ccc5SKrzysztof Kozlowski 2981b816ccc5SKrzysztof Kozlowski ret = amba_pclk_prepare(pcdev); 2982b816ccc5SKrzysztof Kozlowski if (ret) 2983b816ccc5SKrzysztof Kozlowski return ret; 2984b816ccc5SKrzysztof Kozlowski 2985a39cddc9SUlf Hansson pm_runtime_force_resume(dev); 2986b816ccc5SKrzysztof Kozlowski 2987b816ccc5SKrzysztof Kozlowski return ret; 2988b816ccc5SKrzysztof Kozlowski } 2989b816ccc5SKrzysztof Kozlowski 2990f68190c8SUlf Hansson static const struct dev_pm_ops pl330_pm = { 2991f68190c8SUlf Hansson SET_LATE_SYSTEM_SLEEP_PM_OPS(pl330_suspend, pl330_resume) 2992f68190c8SUlf Hansson }; 2993b816ccc5SKrzysztof Kozlowski 2994463a1f8bSBill Pemberton static int 2995aa25afadSRussell King pl330_probe(struct amba_device *adev, const struct amba_id *id) 2996b3040e40SJassi Brar { 2997f6f2421cSLars-Peter Clausen struct pl330_config *pcfg; 2998f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330; 29990b94c577SPadmavathi Venna struct dma_pl330_chan *pch, *_p; 3000b3040e40SJassi Brar struct dma_device *pd; 3001b3040e40SJassi Brar struct resource *res; 3002b3040e40SJassi Brar int i, ret, irq; 30034e0e6109SRob Herring int num_chan; 3004271e1b86SAddy Ke struct device_node *np = adev->dev.of_node; 3005b3040e40SJassi Brar 300664113016SRussell King ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32)); 300764113016SRussell King if (ret) 300864113016SRussell King return ret; 300964113016SRussell King 3010b3040e40SJassi Brar /* Allocate a new DMAC and its Channels */ 3011f6f2421cSLars-Peter Clausen pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL); 3012aef94feaSPeter Griffin if (!pl330) 3013b3040e40SJassi Brar return -ENOMEM; 3014b3040e40SJassi Brar 3015cee42392SAndrew Jackson pd = &pl330->ddma; 3016cee42392SAndrew Jackson pd->dev = &adev->dev; 3017cee42392SAndrew Jackson 3018e8bb4673SMarek Szyprowski pl330->mcbufsz = 0; 3019b3040e40SJassi Brar 3020271e1b86SAddy Ke /* get quirk */ 3021271e1b86SAddy Ke for (i = 0; i < ARRAY_SIZE(of_quirks); i++) 3022271e1b86SAddy Ke if (of_property_read_bool(np, of_quirks[i].quirk)) 3023271e1b86SAddy Ke pl330->quirks |= of_quirks[i].id; 3024271e1b86SAddy Ke 3025b3040e40SJassi Brar res = &adev->res; 3026f6f2421cSLars-Peter Clausen pl330->base = devm_ioremap_resource(&adev->dev, res); 3027f6f2421cSLars-Peter Clausen if (IS_ERR(pl330->base)) 3028f6f2421cSLars-Peter Clausen return PTR_ERR(pl330->base); 3029b3040e40SJassi Brar 3030f6f2421cSLars-Peter Clausen amba_set_drvdata(adev, pl330); 3031a2f5203fSBoojin Kim 30320eaab70aSDinh Nguyen pl330->rstc = devm_reset_control_get_optional(&adev->dev, "dma"); 30330eaab70aSDinh Nguyen if (IS_ERR(pl330->rstc)) { 3034af53bef5SKrzysztof Kozlowski return dev_err_probe(&adev->dev, PTR_ERR(pl330->rstc), "Failed to get reset!\n"); 30350eaab70aSDinh Nguyen } else { 30360eaab70aSDinh Nguyen ret = reset_control_deassert(pl330->rstc); 30370eaab70aSDinh Nguyen if (ret) { 30380eaab70aSDinh Nguyen dev_err(&adev->dev, "Couldn't deassert the device from reset!\n"); 30390eaab70aSDinh Nguyen return ret; 30400eaab70aSDinh Nguyen } 30410eaab70aSDinh Nguyen } 30420eaab70aSDinh Nguyen 30430eaab70aSDinh Nguyen pl330->rstc_ocp = devm_reset_control_get_optional(&adev->dev, "dma-ocp"); 30440eaab70aSDinh Nguyen if (IS_ERR(pl330->rstc_ocp)) { 3045af53bef5SKrzysztof Kozlowski return dev_err_probe(&adev->dev, PTR_ERR(pl330->rstc_ocp), 3046af53bef5SKrzysztof Kozlowski "Failed to get OCP reset!\n"); 30470eaab70aSDinh Nguyen } else { 30480eaab70aSDinh Nguyen ret = reset_control_deassert(pl330->rstc_ocp); 30490eaab70aSDinh Nguyen if (ret) { 30500eaab70aSDinh Nguyen dev_err(&adev->dev, "Couldn't deassert the device from OCP reset!\n"); 30510eaab70aSDinh Nguyen return ret; 30520eaab70aSDinh Nguyen } 30530eaab70aSDinh Nguyen } 30540eaab70aSDinh Nguyen 305502808b42SDan Carpenter for (i = 0; i < AMBA_NR_IRQS; i++) { 3056e98b3cafSMichal Simek irq = adev->irq[i]; 3057e98b3cafSMichal Simek if (irq) { 3058e98b3cafSMichal Simek ret = devm_request_irq(&adev->dev, irq, 3059e98b3cafSMichal Simek pl330_irq_handler, 0, 3060f6f2421cSLars-Peter Clausen dev_name(&adev->dev), pl330); 3061b3040e40SJassi Brar if (ret) 3062e4d43c17SSachin Kamat return ret; 3063e98b3cafSMichal Simek } else { 3064e98b3cafSMichal Simek break; 3065e98b3cafSMichal Simek } 3066e98b3cafSMichal Simek } 3067b3040e40SJassi Brar 3068f6f2421cSLars-Peter Clausen pcfg = &pl330->pcfg; 3069f6f2421cSLars-Peter Clausen 3070f6f2421cSLars-Peter Clausen pcfg->periph_id = adev->periphid; 3071f6f2421cSLars-Peter Clausen ret = pl330_add(pl330); 3072b3040e40SJassi Brar if (ret) 3073173e838cSMichal Simek return ret; 3074b3040e40SJassi Brar 3075f6f2421cSLars-Peter Clausen INIT_LIST_HEAD(&pl330->desc_pool); 3076f6f2421cSLars-Peter Clausen spin_lock_init(&pl330->pool_lock); 3077b3040e40SJassi Brar 3078b3040e40SJassi Brar /* Create a descriptor pool of default size */ 3079e5887103SAlexander Kochetkov if (!add_desc(&pl330->desc_pool, &pl330->pool_lock, 3080e5887103SAlexander Kochetkov GFP_KERNEL, NR_DEFAULT_DESC)) 3081b3040e40SJassi Brar dev_warn(&adev->dev, "unable to allocate desc\n"); 3082b3040e40SJassi Brar 3083b3040e40SJassi Brar INIT_LIST_HEAD(&pd->channels); 3084b3040e40SJassi Brar 3085b3040e40SJassi Brar /* Initialize channel parameters */ 3086f6f2421cSLars-Peter Clausen num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan); 3087c8473828SOlof Johansson 3088f6f2421cSLars-Peter Clausen pl330->num_peripherals = num_chan; 308970cbb163SLars-Peter Clausen 30906396bb22SKees Cook pl330->peripherals = kcalloc(num_chan, sizeof(*pch), GFP_KERNEL); 3091f6f2421cSLars-Peter Clausen if (!pl330->peripherals) { 309261c6e753SSachin Kamat ret = -ENOMEM; 3093e4d43c17SSachin Kamat goto probe_err2; 309461c6e753SSachin Kamat } 30954e0e6109SRob Herring 30964e0e6109SRob Herring for (i = 0; i < num_chan; i++) { 3097f6f2421cSLars-Peter Clausen pch = &pl330->peripherals[i]; 3098b3040e40SJassi Brar 3099e8bb4673SMarek Szyprowski pch->chan.private = adev->dev.of_node; 310004abf5daSLars-Peter Clausen INIT_LIST_HEAD(&pch->submitted_list); 3101b3040e40SJassi Brar INIT_LIST_HEAD(&pch->work_list); 310239ff8613SLars-Peter Clausen INIT_LIST_HEAD(&pch->completed_list); 3103b3040e40SJassi Brar spin_lock_init(&pch->lock); 310465ad6060SLars-Peter Clausen pch->thread = NULL; 3105b3040e40SJassi Brar pch->chan.device = pd; 3106f6f2421cSLars-Peter Clausen pch->dmac = pl330; 31074d6d74e2SRobin Murphy pch->dir = DMA_NONE; 3108b3040e40SJassi Brar 3109b3040e40SJassi Brar /* Add the channel to the DMAC list */ 3110b3040e40SJassi Brar list_add_tail(&pch->chan.device_node, &pd->channels); 3111b3040e40SJassi Brar } 3112b3040e40SJassi Brar 3113cd072515SThomas Abraham dma_cap_set(DMA_MEMCPY, pd->cap_mask); 3114f6f2421cSLars-Peter Clausen if (pcfg->num_peri) { 311593ed5544SThomas Abraham dma_cap_set(DMA_SLAVE, pd->cap_mask); 311693ed5544SThomas Abraham dma_cap_set(DMA_CYCLIC, pd->cap_mask); 31175557a419STushar Behera dma_cap_set(DMA_PRIVATE, pd->cap_mask); 311893ed5544SThomas Abraham } 3119b3040e40SJassi Brar 3120b3040e40SJassi Brar pd->device_alloc_chan_resources = pl330_alloc_chan_resources; 3121b3040e40SJassi Brar pd->device_free_chan_resources = pl330_free_chan_resources; 3122b3040e40SJassi Brar pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; 312342bc9cf4SBoojin Kim pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; 3124b3040e40SJassi Brar pd->device_tx_status = pl330_tx_status; 3125b3040e40SJassi Brar pd->device_prep_slave_sg = pl330_prep_slave_sg; 3126740aa957SMaxime Ripard pd->device_config = pl330_config; 312788987d2cSRobert Baldyga pd->device_pause = pl330_pause; 3128740aa957SMaxime Ripard pd->device_terminate_all = pl330_terminate_all; 3129b3040e40SJassi Brar pd->device_issue_pending = pl330_issue_pending; 3130dcabe456SMaxime Ripard pd->src_addr_widths = PL330_DMA_BUSWIDTHS; 3131dcabe456SMaxime Ripard pd->dst_addr_widths = PL330_DMA_BUSWIDTHS; 3132dcabe456SMaxime Ripard pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 3133e3f329c6SMarek Szyprowski pd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 313405611a93SSugar Zhang pd->max_burst = PL330_MAX_BURST; 3135b3040e40SJassi Brar 3136b3040e40SJassi Brar ret = dma_async_device_register(pd); 3137b3040e40SJassi Brar if (ret) { 3138b3040e40SJassi Brar dev_err(&adev->dev, "unable to register DMAC\n"); 31390b94c577SPadmavathi Venna goto probe_err3; 31400b94c577SPadmavathi Venna } 31410b94c577SPadmavathi Venna 31420b94c577SPadmavathi Venna if (adev->dev.of_node) { 31430b94c577SPadmavathi Venna ret = of_dma_controller_register(adev->dev.of_node, 3144f6f2421cSLars-Peter Clausen of_dma_pl330_xlate, pl330); 31450b94c577SPadmavathi Venna if (ret) { 31460b94c577SPadmavathi Venna dev_err(&adev->dev, 31470b94c577SPadmavathi Venna "unable to register DMA to the generic DT DMA helpers\n"); 31480b94c577SPadmavathi Venna } 3149b3040e40SJassi Brar } 3150b714b84eSLars-Peter Clausen 3151dbaf6d85SVinod Koul /* 3152dbaf6d85SVinod Koul * This is the limit for transfers with a buswidth of 1, larger 3153dbaf6d85SVinod Koul * buswidths will have larger limits. 3154dbaf6d85SVinod Koul */ 3155dbaf6d85SVinod Koul ret = dma_set_max_seg_size(&adev->dev, 1900800); 3156dbaf6d85SVinod Koul if (ret) 3157dbaf6d85SVinod Koul dev_err(&adev->dev, "unable to set the seg size\n"); 3158dbaf6d85SVinod Koul 3159b3040e40SJassi Brar 3160b45aef3aSKatsuhiro Suzuki init_pl330_debugfs(pl330); 3161b3040e40SJassi Brar dev_info(&adev->dev, 31621f0a5cbfSLiviu Dudau "Loaded driver for PL330 DMAC-%x\n", adev->periphid); 3163b3040e40SJassi Brar dev_info(&adev->dev, 3164b3040e40SJassi Brar "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", 3165f6f2421cSLars-Peter Clausen pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan, 3166f6f2421cSLars-Peter Clausen pcfg->num_peri, pcfg->num_events); 3167b3040e40SJassi Brar 3168ae43b328SKrzysztof Kozlowski pm_runtime_irq_safe(&adev->dev); 3169ae43b328SKrzysztof Kozlowski pm_runtime_use_autosuspend(&adev->dev); 3170ae43b328SKrzysztof Kozlowski pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY); 3171ae43b328SKrzysztof Kozlowski pm_runtime_mark_last_busy(&adev->dev); 3172ae43b328SKrzysztof Kozlowski pm_runtime_put_autosuspend(&adev->dev); 3173ae43b328SKrzysztof Kozlowski 3174b3040e40SJassi Brar return 0; 31750b94c577SPadmavathi Venna probe_err3: 31760b94c577SPadmavathi Venna /* Idle the DMAC */ 3177f6f2421cSLars-Peter Clausen list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, 31780b94c577SPadmavathi Venna chan.device_node) { 31790b94c577SPadmavathi Venna 31800b94c577SPadmavathi Venna /* Remove the channel */ 31810b94c577SPadmavathi Venna list_del(&pch->chan.device_node); 31820b94c577SPadmavathi Venna 31830b94c577SPadmavathi Venna /* Flush the channel */ 31840f5ebabdSKrzysztof Kozlowski if (pch->thread) { 3185740aa957SMaxime Ripard pl330_terminate_all(&pch->chan); 31860b94c577SPadmavathi Venna pl330_free_chan_resources(&pch->chan); 31870b94c577SPadmavathi Venna } 31880f5ebabdSKrzysztof Kozlowski } 3189b3040e40SJassi Brar probe_err2: 3190f6f2421cSLars-Peter Clausen pl330_del(pl330); 3191b3040e40SJassi Brar 31920eaab70aSDinh Nguyen if (pl330->rstc_ocp) 31930eaab70aSDinh Nguyen reset_control_assert(pl330->rstc_ocp); 31940eaab70aSDinh Nguyen 31950eaab70aSDinh Nguyen if (pl330->rstc) 31960eaab70aSDinh Nguyen reset_control_assert(pl330->rstc); 3197b3040e40SJassi Brar return ret; 3198b3040e40SJassi Brar } 3199b3040e40SJassi Brar 32004bf27b8bSGreg Kroah-Hartman static int pl330_remove(struct amba_device *adev) 3201b3040e40SJassi Brar { 3202f6f2421cSLars-Peter Clausen struct pl330_dmac *pl330 = amba_get_drvdata(adev); 3203b3040e40SJassi Brar struct dma_pl330_chan *pch, *_p; 320446cf94d6SVinod Koul int i, irq; 3205b3040e40SJassi Brar 3206ae43b328SKrzysztof Kozlowski pm_runtime_get_noresume(pl330->ddma.dev); 3207ae43b328SKrzysztof Kozlowski 32080b94c577SPadmavathi Venna if (adev->dev.of_node) 3209421da89aSPadmavathi Venna of_dma_controller_free(adev->dev.of_node); 3210421da89aSPadmavathi Venna 321146cf94d6SVinod Koul for (i = 0; i < AMBA_NR_IRQS; i++) { 321246cf94d6SVinod Koul irq = adev->irq[i]; 3213ebcdaee4SJean-Philippe Brucker if (irq) 321446cf94d6SVinod Koul devm_free_irq(&adev->dev, irq, pl330); 321546cf94d6SVinod Koul } 321646cf94d6SVinod Koul 3217f6f2421cSLars-Peter Clausen dma_async_device_unregister(&pl330->ddma); 3218b3040e40SJassi Brar 3219b3040e40SJassi Brar /* Idle the DMAC */ 3220f6f2421cSLars-Peter Clausen list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, 3221b3040e40SJassi Brar chan.device_node) { 3222b3040e40SJassi Brar 3223b3040e40SJassi Brar /* Remove the channel */ 3224b3040e40SJassi Brar list_del(&pch->chan.device_node); 3225b3040e40SJassi Brar 3226b3040e40SJassi Brar /* Flush the channel */ 32276e4a2a83SKrzysztof Kozlowski if (pch->thread) { 3228740aa957SMaxime Ripard pl330_terminate_all(&pch->chan); 3229b3040e40SJassi Brar pl330_free_chan_resources(&pch->chan); 3230b3040e40SJassi Brar } 32316e4a2a83SKrzysztof Kozlowski } 3232b3040e40SJassi Brar 3233f6f2421cSLars-Peter Clausen pl330_del(pl330); 3234b3040e40SJassi Brar 32350eaab70aSDinh Nguyen if (pl330->rstc_ocp) 32360eaab70aSDinh Nguyen reset_control_assert(pl330->rstc_ocp); 32370eaab70aSDinh Nguyen 32380eaab70aSDinh Nguyen if (pl330->rstc) 32390eaab70aSDinh Nguyen reset_control_assert(pl330->rstc); 3240b3040e40SJassi Brar return 0; 3241b3040e40SJassi Brar } 3242b3040e40SJassi Brar 3243b753351eSArvind Yadav static const struct amba_id pl330_ids[] = { 3244b3040e40SJassi Brar { 3245b3040e40SJassi Brar .id = 0x00041330, 3246b3040e40SJassi Brar .mask = 0x000fffff, 3247b3040e40SJassi Brar }, 3248b3040e40SJassi Brar { 0, 0 }, 3249b3040e40SJassi Brar }; 3250b3040e40SJassi Brar 3251e8fa516aSDave Martin MODULE_DEVICE_TABLE(amba, pl330_ids); 3252e8fa516aSDave Martin 3253b3040e40SJassi Brar static struct amba_driver pl330_driver = { 3254b3040e40SJassi Brar .drv = { 3255b3040e40SJassi Brar .owner = THIS_MODULE, 3256b3040e40SJassi Brar .name = "dma-pl330", 3257b816ccc5SKrzysztof Kozlowski .pm = &pl330_pm, 3258b3040e40SJassi Brar }, 3259b3040e40SJassi Brar .id_table = pl330_ids, 3260b3040e40SJassi Brar .probe = pl330_probe, 3261b3040e40SJassi Brar .remove = pl330_remove, 3262b3040e40SJassi Brar }; 3263b3040e40SJassi Brar 32649e5ed094Sviresh kumar module_amba_driver(pl330_driver); 3265b3040e40SJassi Brar 3266046209f6SJassi Brar MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>"); 3267b3040e40SJassi Brar MODULE_DESCRIPTION("API Driver for PL330 DMAC"); 3268b3040e40SJassi Brar MODULE_LICENSE("GPL"); 3269