1b7d861d9SBoojin Kim /* 2b7d861d9SBoojin Kim * Copyright (c) 2012 Samsung Electronics Co., Ltd. 3b7d861d9SBoojin Kim * http://www.samsung.com 4b3040e40SJassi Brar * 5b3040e40SJassi Brar * Copyright (C) 2010 Samsung Electronics Co. Ltd. 6b3040e40SJassi Brar * Jaswinder Singh <jassi.brar@samsung.com> 7b3040e40SJassi Brar * 8b3040e40SJassi Brar * This program is free software; you can redistribute it and/or modify 9b3040e40SJassi Brar * it under the terms of the GNU General Public License as published by 10b3040e40SJassi Brar * the Free Software Foundation; either version 2 of the License, or 11b3040e40SJassi Brar * (at your option) any later version. 12b3040e40SJassi Brar */ 13b3040e40SJassi Brar 14b7d861d9SBoojin Kim #include <linux/kernel.h> 15b3040e40SJassi Brar #include <linux/io.h> 16b3040e40SJassi Brar #include <linux/init.h> 17b3040e40SJassi Brar #include <linux/slab.h> 18b3040e40SJassi Brar #include <linux/module.h> 19b7d861d9SBoojin Kim #include <linux/string.h> 20b7d861d9SBoojin Kim #include <linux/delay.h> 21b7d861d9SBoojin Kim #include <linux/interrupt.h> 22b7d861d9SBoojin Kim #include <linux/dma-mapping.h> 23b3040e40SJassi Brar #include <linux/dmaengine.h> 24b3040e40SJassi Brar #include <linux/amba/bus.h> 25b3040e40SJassi Brar #include <linux/amba/pl330.h> 261b9bb715SBoojin Kim #include <linux/scatterlist.h> 2793ed5544SThomas Abraham #include <linux/of.h> 28a80258f9SPadmavathi Venna #include <linux/of_dma.h> 29bcc7fa95SSachin Kamat #include <linux/err.h> 30b3040e40SJassi Brar 31d2ebfb33SRussell King - ARM Linux #include "dmaengine.h" 32b7d861d9SBoojin Kim #define PL330_MAX_CHAN 8 33b7d861d9SBoojin Kim #define PL330_MAX_IRQS 32 34b7d861d9SBoojin Kim #define PL330_MAX_PERI 32 35b7d861d9SBoojin Kim 36f0564c7eSLars-Peter Clausen enum pl330_cachectrl { 37f0564c7eSLars-Peter Clausen CCTRL0, /* Noncacheable and nonbufferable */ 38f0564c7eSLars-Peter Clausen CCTRL1, /* Bufferable only */ 39f0564c7eSLars-Peter Clausen CCTRL2, /* Cacheable, but do not allocate */ 40f0564c7eSLars-Peter Clausen CCTRL3, /* Cacheable and bufferable, but do not allocate */ 41f0564c7eSLars-Peter Clausen INVALID1, /* AWCACHE = 0x1000 */ 42f0564c7eSLars-Peter Clausen INVALID2, 43f0564c7eSLars-Peter Clausen CCTRL6, /* Cacheable write-through, allocate on writes only */ 44f0564c7eSLars-Peter Clausen CCTRL7, /* Cacheable write-back, allocate on writes only */ 45b7d861d9SBoojin Kim }; 46b7d861d9SBoojin Kim 47b7d861d9SBoojin Kim enum pl330_byteswap { 48b7d861d9SBoojin Kim SWAP_NO, 49b7d861d9SBoojin Kim SWAP_2, 50b7d861d9SBoojin Kim SWAP_4, 51b7d861d9SBoojin Kim SWAP_8, 52b7d861d9SBoojin Kim SWAP_16, 53b7d861d9SBoojin Kim }; 54b7d861d9SBoojin Kim 55b7d861d9SBoojin Kim /* Register and Bit field Definitions */ 56b7d861d9SBoojin Kim #define DS 0x0 57b7d861d9SBoojin Kim #define DS_ST_STOP 0x0 58b7d861d9SBoojin Kim #define DS_ST_EXEC 0x1 59b7d861d9SBoojin Kim #define DS_ST_CMISS 0x2 60b7d861d9SBoojin Kim #define DS_ST_UPDTPC 0x3 61b7d861d9SBoojin Kim #define DS_ST_WFE 0x4 62b7d861d9SBoojin Kim #define DS_ST_ATBRR 0x5 63b7d861d9SBoojin Kim #define DS_ST_QBUSY 0x6 64b7d861d9SBoojin Kim #define DS_ST_WFP 0x7 65b7d861d9SBoojin Kim #define DS_ST_KILL 0x8 66b7d861d9SBoojin Kim #define DS_ST_CMPLT 0x9 67b7d861d9SBoojin Kim #define DS_ST_FLTCMP 0xe 68b7d861d9SBoojin Kim #define DS_ST_FAULT 0xf 69b7d861d9SBoojin Kim 70b7d861d9SBoojin Kim #define DPC 0x4 71b7d861d9SBoojin Kim #define INTEN 0x20 72b7d861d9SBoojin Kim #define ES 0x24 73b7d861d9SBoojin Kim #define INTSTATUS 0x28 74b7d861d9SBoojin Kim #define INTCLR 0x2c 75b7d861d9SBoojin Kim #define FSM 0x30 76b7d861d9SBoojin Kim #define FSC 0x34 77b7d861d9SBoojin Kim #define FTM 0x38 78b7d861d9SBoojin Kim 79b7d861d9SBoojin Kim #define _FTC 0x40 80b7d861d9SBoojin Kim #define FTC(n) (_FTC + (n)*0x4) 81b7d861d9SBoojin Kim 82b7d861d9SBoojin Kim #define _CS 0x100 83b7d861d9SBoojin Kim #define CS(n) (_CS + (n)*0x8) 84b7d861d9SBoojin Kim #define CS_CNS (1 << 21) 85b7d861d9SBoojin Kim 86b7d861d9SBoojin Kim #define _CPC 0x104 87b7d861d9SBoojin Kim #define CPC(n) (_CPC + (n)*0x8) 88b7d861d9SBoojin Kim 89b7d861d9SBoojin Kim #define _SA 0x400 90b7d861d9SBoojin Kim #define SA(n) (_SA + (n)*0x20) 91b7d861d9SBoojin Kim 92b7d861d9SBoojin Kim #define _DA 0x404 93b7d861d9SBoojin Kim #define DA(n) (_DA + (n)*0x20) 94b7d861d9SBoojin Kim 95b7d861d9SBoojin Kim #define _CC 0x408 96b7d861d9SBoojin Kim #define CC(n) (_CC + (n)*0x20) 97b7d861d9SBoojin Kim 98b7d861d9SBoojin Kim #define CC_SRCINC (1 << 0) 99b7d861d9SBoojin Kim #define CC_DSTINC (1 << 14) 100b7d861d9SBoojin Kim #define CC_SRCPRI (1 << 8) 101b7d861d9SBoojin Kim #define CC_DSTPRI (1 << 22) 102b7d861d9SBoojin Kim #define CC_SRCNS (1 << 9) 103b7d861d9SBoojin Kim #define CC_DSTNS (1 << 23) 104b7d861d9SBoojin Kim #define CC_SRCIA (1 << 10) 105b7d861d9SBoojin Kim #define CC_DSTIA (1 << 24) 106b7d861d9SBoojin Kim #define CC_SRCBRSTLEN_SHFT 4 107b7d861d9SBoojin Kim #define CC_DSTBRSTLEN_SHFT 18 108b7d861d9SBoojin Kim #define CC_SRCBRSTSIZE_SHFT 1 109b7d861d9SBoojin Kim #define CC_DSTBRSTSIZE_SHFT 15 110b7d861d9SBoojin Kim #define CC_SRCCCTRL_SHFT 11 111b7d861d9SBoojin Kim #define CC_SRCCCTRL_MASK 0x7 112b7d861d9SBoojin Kim #define CC_DSTCCTRL_SHFT 25 113b7d861d9SBoojin Kim #define CC_DRCCCTRL_MASK 0x7 114b7d861d9SBoojin Kim #define CC_SWAP_SHFT 28 115b7d861d9SBoojin Kim 116b7d861d9SBoojin Kim #define _LC0 0x40c 117b7d861d9SBoojin Kim #define LC0(n) (_LC0 + (n)*0x20) 118b7d861d9SBoojin Kim 119b7d861d9SBoojin Kim #define _LC1 0x410 120b7d861d9SBoojin Kim #define LC1(n) (_LC1 + (n)*0x20) 121b7d861d9SBoojin Kim 122b7d861d9SBoojin Kim #define DBGSTATUS 0xd00 123b7d861d9SBoojin Kim #define DBG_BUSY (1 << 0) 124b7d861d9SBoojin Kim 125b7d861d9SBoojin Kim #define DBGCMD 0xd04 126b7d861d9SBoojin Kim #define DBGINST0 0xd08 127b7d861d9SBoojin Kim #define DBGINST1 0xd0c 128b7d861d9SBoojin Kim 129b7d861d9SBoojin Kim #define CR0 0xe00 130b7d861d9SBoojin Kim #define CR1 0xe04 131b7d861d9SBoojin Kim #define CR2 0xe08 132b7d861d9SBoojin Kim #define CR3 0xe0c 133b7d861d9SBoojin Kim #define CR4 0xe10 134b7d861d9SBoojin Kim #define CRD 0xe14 135b7d861d9SBoojin Kim 136b7d861d9SBoojin Kim #define PERIPH_ID 0xfe0 1373ecf51a4SBoojin Kim #define PERIPH_REV_SHIFT 20 1383ecf51a4SBoojin Kim #define PERIPH_REV_MASK 0xf 1393ecf51a4SBoojin Kim #define PERIPH_REV_R0P0 0 1403ecf51a4SBoojin Kim #define PERIPH_REV_R1P0 1 1413ecf51a4SBoojin Kim #define PERIPH_REV_R1P1 2 142b7d861d9SBoojin Kim 143b7d861d9SBoojin Kim #define CR0_PERIPH_REQ_SET (1 << 0) 144b7d861d9SBoojin Kim #define CR0_BOOT_EN_SET (1 << 1) 145b7d861d9SBoojin Kim #define CR0_BOOT_MAN_NS (1 << 2) 146b7d861d9SBoojin Kim #define CR0_NUM_CHANS_SHIFT 4 147b7d861d9SBoojin Kim #define CR0_NUM_CHANS_MASK 0x7 148b7d861d9SBoojin Kim #define CR0_NUM_PERIPH_SHIFT 12 149b7d861d9SBoojin Kim #define CR0_NUM_PERIPH_MASK 0x1f 150b7d861d9SBoojin Kim #define CR0_NUM_EVENTS_SHIFT 17 151b7d861d9SBoojin Kim #define CR0_NUM_EVENTS_MASK 0x1f 152b7d861d9SBoojin Kim 153b7d861d9SBoojin Kim #define CR1_ICACHE_LEN_SHIFT 0 154b7d861d9SBoojin Kim #define CR1_ICACHE_LEN_MASK 0x7 155b7d861d9SBoojin Kim #define CR1_NUM_ICACHELINES_SHIFT 4 156b7d861d9SBoojin Kim #define CR1_NUM_ICACHELINES_MASK 0xf 157b7d861d9SBoojin Kim 158b7d861d9SBoojin Kim #define CRD_DATA_WIDTH_SHIFT 0 159b7d861d9SBoojin Kim #define CRD_DATA_WIDTH_MASK 0x7 160b7d861d9SBoojin Kim #define CRD_WR_CAP_SHIFT 4 161b7d861d9SBoojin Kim #define CRD_WR_CAP_MASK 0x7 162b7d861d9SBoojin Kim #define CRD_WR_Q_DEP_SHIFT 8 163b7d861d9SBoojin Kim #define CRD_WR_Q_DEP_MASK 0xf 164b7d861d9SBoojin Kim #define CRD_RD_CAP_SHIFT 12 165b7d861d9SBoojin Kim #define CRD_RD_CAP_MASK 0x7 166b7d861d9SBoojin Kim #define CRD_RD_Q_DEP_SHIFT 16 167b7d861d9SBoojin Kim #define CRD_RD_Q_DEP_MASK 0xf 168b7d861d9SBoojin Kim #define CRD_DATA_BUFF_SHIFT 20 169b7d861d9SBoojin Kim #define CRD_DATA_BUFF_MASK 0x3ff 170b7d861d9SBoojin Kim 171b7d861d9SBoojin Kim #define PART 0x330 172b7d861d9SBoojin Kim #define DESIGNER 0x41 173b7d861d9SBoojin Kim #define REVISION 0x0 174b7d861d9SBoojin Kim #define INTEG_CFG 0x0 175b7d861d9SBoojin Kim #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) 176b7d861d9SBoojin Kim 177b7d861d9SBoojin Kim #define PL330_STATE_STOPPED (1 << 0) 178b7d861d9SBoojin Kim #define PL330_STATE_EXECUTING (1 << 1) 179b7d861d9SBoojin Kim #define PL330_STATE_WFE (1 << 2) 180b7d861d9SBoojin Kim #define PL330_STATE_FAULTING (1 << 3) 181b7d861d9SBoojin Kim #define PL330_STATE_COMPLETING (1 << 4) 182b7d861d9SBoojin Kim #define PL330_STATE_WFP (1 << 5) 183b7d861d9SBoojin Kim #define PL330_STATE_KILLING (1 << 6) 184b7d861d9SBoojin Kim #define PL330_STATE_FAULT_COMPLETING (1 << 7) 185b7d861d9SBoojin Kim #define PL330_STATE_CACHEMISS (1 << 8) 186b7d861d9SBoojin Kim #define PL330_STATE_UPDTPC (1 << 9) 187b7d861d9SBoojin Kim #define PL330_STATE_ATBARRIER (1 << 10) 188b7d861d9SBoojin Kim #define PL330_STATE_QUEUEBUSY (1 << 11) 189b7d861d9SBoojin Kim #define PL330_STATE_INVALID (1 << 15) 190b7d861d9SBoojin Kim 191b7d861d9SBoojin Kim #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ 192b7d861d9SBoojin Kim | PL330_STATE_WFE | PL330_STATE_FAULTING) 193b7d861d9SBoojin Kim 194b7d861d9SBoojin Kim #define CMD_DMAADDH 0x54 195b7d861d9SBoojin Kim #define CMD_DMAEND 0x00 196b7d861d9SBoojin Kim #define CMD_DMAFLUSHP 0x35 197b7d861d9SBoojin Kim #define CMD_DMAGO 0xa0 198b7d861d9SBoojin Kim #define CMD_DMALD 0x04 199b7d861d9SBoojin Kim #define CMD_DMALDP 0x25 200b7d861d9SBoojin Kim #define CMD_DMALP 0x20 201b7d861d9SBoojin Kim #define CMD_DMALPEND 0x28 202b7d861d9SBoojin Kim #define CMD_DMAKILL 0x01 203b7d861d9SBoojin Kim #define CMD_DMAMOV 0xbc 204b7d861d9SBoojin Kim #define CMD_DMANOP 0x18 205b7d861d9SBoojin Kim #define CMD_DMARMB 0x12 206b7d861d9SBoojin Kim #define CMD_DMASEV 0x34 207b7d861d9SBoojin Kim #define CMD_DMAST 0x08 208b7d861d9SBoojin Kim #define CMD_DMASTP 0x29 209b7d861d9SBoojin Kim #define CMD_DMASTZ 0x0c 210b7d861d9SBoojin Kim #define CMD_DMAWFE 0x36 211b7d861d9SBoojin Kim #define CMD_DMAWFP 0x30 212b7d861d9SBoojin Kim #define CMD_DMAWMB 0x13 213b7d861d9SBoojin Kim 214b7d861d9SBoojin Kim #define SZ_DMAADDH 3 215b7d861d9SBoojin Kim #define SZ_DMAEND 1 216b7d861d9SBoojin Kim #define SZ_DMAFLUSHP 2 217b7d861d9SBoojin Kim #define SZ_DMALD 1 218b7d861d9SBoojin Kim #define SZ_DMALDP 2 219b7d861d9SBoojin Kim #define SZ_DMALP 2 220b7d861d9SBoojin Kim #define SZ_DMALPEND 2 221b7d861d9SBoojin Kim #define SZ_DMAKILL 1 222b7d861d9SBoojin Kim #define SZ_DMAMOV 6 223b7d861d9SBoojin Kim #define SZ_DMANOP 1 224b7d861d9SBoojin Kim #define SZ_DMARMB 1 225b7d861d9SBoojin Kim #define SZ_DMASEV 2 226b7d861d9SBoojin Kim #define SZ_DMAST 1 227b7d861d9SBoojin Kim #define SZ_DMASTP 2 228b7d861d9SBoojin Kim #define SZ_DMASTZ 1 229b7d861d9SBoojin Kim #define SZ_DMAWFE 2 230b7d861d9SBoojin Kim #define SZ_DMAWFP 2 231b7d861d9SBoojin Kim #define SZ_DMAWMB 1 232b7d861d9SBoojin Kim #define SZ_DMAGO 6 233b7d861d9SBoojin Kim 234b7d861d9SBoojin Kim #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) 235b7d861d9SBoojin Kim #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) 236b7d861d9SBoojin Kim 237b7d861d9SBoojin Kim #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) 238b7d861d9SBoojin Kim #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) 239b7d861d9SBoojin Kim 240b7d861d9SBoojin Kim /* 241b7d861d9SBoojin Kim * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req 242b7d861d9SBoojin Kim * at 1byte/burst for P<->M and M<->M respectively. 243b7d861d9SBoojin Kim * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req 244b7d861d9SBoojin Kim * should be enough for P<->M and M<->M respectively. 245b7d861d9SBoojin Kim */ 246b7d861d9SBoojin Kim #define MCODE_BUFF_PER_REQ 256 247b7d861d9SBoojin Kim 248b7d861d9SBoojin Kim /* If the _pl330_req is available to the client */ 249b7d861d9SBoojin Kim #define IS_FREE(req) (*((u8 *)((req)->mc_cpu)) == CMD_DMAEND) 250b7d861d9SBoojin Kim 251b7d861d9SBoojin Kim /* Use this _only_ to wait on transient states */ 252b7d861d9SBoojin Kim #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); 253b7d861d9SBoojin Kim 254b7d861d9SBoojin Kim #ifdef PL330_DEBUG_MCGEN 255b7d861d9SBoojin Kim static unsigned cmd_line; 256b7d861d9SBoojin Kim #define PL330_DBGCMD_DUMP(off, x...) do { \ 257b7d861d9SBoojin Kim printk("%x:", cmd_line); \ 258b7d861d9SBoojin Kim printk(x); \ 259b7d861d9SBoojin Kim cmd_line += off; \ 260b7d861d9SBoojin Kim } while (0) 261b7d861d9SBoojin Kim #define PL330_DBGMC_START(addr) (cmd_line = addr) 262b7d861d9SBoojin Kim #else 263b7d861d9SBoojin Kim #define PL330_DBGCMD_DUMP(off, x...) do {} while (0) 264b7d861d9SBoojin Kim #define PL330_DBGMC_START(addr) do {} while (0) 265b7d861d9SBoojin Kim #endif 266b7d861d9SBoojin Kim 267b7d861d9SBoojin Kim /* The number of default descriptors */ 268d2ebfb33SRussell King - ARM Linux 269b3040e40SJassi Brar #define NR_DEFAULT_DESC 16 270b3040e40SJassi Brar 271b7d861d9SBoojin Kim /* Populated by the PL330 core driver for DMA API driver's info */ 272b7d861d9SBoojin Kim struct pl330_config { 273b7d861d9SBoojin Kim u32 periph_id; 274b7d861d9SBoojin Kim #define DMAC_MODE_NS (1 << 0) 275b7d861d9SBoojin Kim unsigned int mode; 276b7d861d9SBoojin Kim unsigned int data_bus_width:10; /* In number of bits */ 277b7d861d9SBoojin Kim unsigned int data_buf_dep:10; 278b7d861d9SBoojin Kim unsigned int num_chan:4; 279b7d861d9SBoojin Kim unsigned int num_peri:6; 280b7d861d9SBoojin Kim u32 peri_ns; 281b7d861d9SBoojin Kim unsigned int num_events:6; 282b7d861d9SBoojin Kim u32 irq_ns; 283b7d861d9SBoojin Kim }; 284b7d861d9SBoojin Kim 285b7d861d9SBoojin Kim /* Handle to the DMAC provided to the PL330 core */ 286b7d861d9SBoojin Kim struct pl330_info { 287b7d861d9SBoojin Kim /* Owning device */ 288b7d861d9SBoojin Kim struct device *dev; 289b7d861d9SBoojin Kim /* Size of MicroCode buffers for each channel. */ 290b7d861d9SBoojin Kim unsigned mcbufsz; 291b7d861d9SBoojin Kim /* ioremap'ed address of PL330 registers. */ 292b7d861d9SBoojin Kim void __iomem *base; 293b7d861d9SBoojin Kim /* PL330 core data, Client must not touch it. */ 294b7d861d9SBoojin Kim void *pl330_data; 295b7d861d9SBoojin Kim /* Populated by the PL330 core driver during pl330_add */ 296b7d861d9SBoojin Kim struct pl330_config pcfg; 297b7d861d9SBoojin Kim }; 298b7d861d9SBoojin Kim 299b7d861d9SBoojin Kim /** 300b7d861d9SBoojin Kim * Request Configuration. 301b7d861d9SBoojin Kim * The PL330 core does not modify this and uses the last 302b7d861d9SBoojin Kim * working configuration if the request doesn't provide any. 303b7d861d9SBoojin Kim * 304b7d861d9SBoojin Kim * The Client may want to provide this info only for the 305b7d861d9SBoojin Kim * first request and a request with new settings. 306b7d861d9SBoojin Kim */ 307b7d861d9SBoojin Kim struct pl330_reqcfg { 308b7d861d9SBoojin Kim /* Address Incrementing */ 309b7d861d9SBoojin Kim unsigned dst_inc:1; 310b7d861d9SBoojin Kim unsigned src_inc:1; 311b7d861d9SBoojin Kim 312b7d861d9SBoojin Kim /* 313b7d861d9SBoojin Kim * For now, the SRC & DST protection levels 314b7d861d9SBoojin Kim * and burst size/length are assumed same. 315b7d861d9SBoojin Kim */ 316b7d861d9SBoojin Kim bool nonsecure; 317b7d861d9SBoojin Kim bool privileged; 318b7d861d9SBoojin Kim bool insnaccess; 319b7d861d9SBoojin Kim unsigned brst_len:5; 320b7d861d9SBoojin Kim unsigned brst_size:3; /* in power of 2 */ 321b7d861d9SBoojin Kim 322f0564c7eSLars-Peter Clausen enum pl330_cachectrl dcctl; 323f0564c7eSLars-Peter Clausen enum pl330_cachectrl scctl; 324b7d861d9SBoojin Kim enum pl330_byteswap swap; 3253ecf51a4SBoojin Kim struct pl330_config *pcfg; 326b7d861d9SBoojin Kim }; 327b7d861d9SBoojin Kim 328b7d861d9SBoojin Kim /* 329b7d861d9SBoojin Kim * One cycle of DMAC operation. 330b7d861d9SBoojin Kim * There may be more than one xfer in a request. 331b7d861d9SBoojin Kim */ 332b7d861d9SBoojin Kim struct pl330_xfer { 333b7d861d9SBoojin Kim u32 src_addr; 334b7d861d9SBoojin Kim u32 dst_addr; 335b7d861d9SBoojin Kim /* Size to xfer */ 336b7d861d9SBoojin Kim u32 bytes; 337b7d861d9SBoojin Kim }; 338b7d861d9SBoojin Kim 339b7d861d9SBoojin Kim /* The xfer callbacks are made with one of these arguments. */ 340b7d861d9SBoojin Kim enum pl330_op_err { 341b7d861d9SBoojin Kim /* The all xfers in the request were success. */ 342b7d861d9SBoojin Kim PL330_ERR_NONE, 343b7d861d9SBoojin Kim /* If req aborted due to global error. */ 344b7d861d9SBoojin Kim PL330_ERR_ABORT, 345b7d861d9SBoojin Kim /* If req failed due to problem with Channel. */ 346b7d861d9SBoojin Kim PL330_ERR_FAIL, 347b7d861d9SBoojin Kim }; 348b7d861d9SBoojin Kim 349b7d861d9SBoojin Kim /* A request defining Scatter-Gather List ending with NULL xfer. */ 350b7d861d9SBoojin Kim struct pl330_req { 351585a9d0bSLars-Peter Clausen enum dma_transfer_direction rqtype; 352b7d861d9SBoojin Kim /* Index of peripheral for the xfer. */ 353b7d861d9SBoojin Kim unsigned peri:5; 354b7d861d9SBoojin Kim /* If NULL, req will be done at last set parameters. */ 355b7d861d9SBoojin Kim struct pl330_reqcfg *cfg; 356b7d861d9SBoojin Kim /* Pointer to first xfer in the request. */ 357b7d861d9SBoojin Kim struct pl330_xfer *x; 358fdec53d5SJavi Merino /* Hook to attach to DMAC's list of reqs with due callback */ 359fdec53d5SJavi Merino struct list_head rqd; 360b7d861d9SBoojin Kim }; 361b7d861d9SBoojin Kim 362b7d861d9SBoojin Kim enum pl330_chan_op { 363b7d861d9SBoojin Kim /* Start the channel */ 364b7d861d9SBoojin Kim PL330_OP_START, 365b7d861d9SBoojin Kim /* Abort the active xfer */ 366b7d861d9SBoojin Kim PL330_OP_ABORT, 367b7d861d9SBoojin Kim /* Stop xfer and flush queue */ 368b7d861d9SBoojin Kim PL330_OP_FLUSH, 369b7d861d9SBoojin Kim }; 370b7d861d9SBoojin Kim 371b7d861d9SBoojin Kim struct _xfer_spec { 372b7d861d9SBoojin Kim u32 ccr; 373b7d861d9SBoojin Kim struct pl330_req *r; 374b7d861d9SBoojin Kim struct pl330_xfer *x; 375b7d861d9SBoojin Kim }; 376b7d861d9SBoojin Kim 377b7d861d9SBoojin Kim enum dmamov_dst { 378b7d861d9SBoojin Kim SAR = 0, 379b7d861d9SBoojin Kim CCR, 380b7d861d9SBoojin Kim DAR, 381b7d861d9SBoojin Kim }; 382b7d861d9SBoojin Kim 383b7d861d9SBoojin Kim enum pl330_dst { 384b7d861d9SBoojin Kim SRC = 0, 385b7d861d9SBoojin Kim DST, 386b7d861d9SBoojin Kim }; 387b7d861d9SBoojin Kim 388b7d861d9SBoojin Kim enum pl330_cond { 389b7d861d9SBoojin Kim SINGLE, 390b7d861d9SBoojin Kim BURST, 391b7d861d9SBoojin Kim ALWAYS, 392b7d861d9SBoojin Kim }; 393b7d861d9SBoojin Kim 394b7d861d9SBoojin Kim struct _pl330_req { 395b7d861d9SBoojin Kim u32 mc_bus; 396b7d861d9SBoojin Kim void *mc_cpu; 397b7d861d9SBoojin Kim struct pl330_req *r; 398b7d861d9SBoojin Kim }; 399b7d861d9SBoojin Kim 400b7d861d9SBoojin Kim /* ToBeDone for tasklet */ 401b7d861d9SBoojin Kim struct _pl330_tbd { 402b7d861d9SBoojin Kim bool reset_dmac; 403b7d861d9SBoojin Kim bool reset_mngr; 404b7d861d9SBoojin Kim u8 reset_chan; 405b7d861d9SBoojin Kim }; 406b7d861d9SBoojin Kim 407b7d861d9SBoojin Kim /* A DMAC Thread */ 408b7d861d9SBoojin Kim struct pl330_thread { 409b7d861d9SBoojin Kim u8 id; 410b7d861d9SBoojin Kim int ev; 411b7d861d9SBoojin Kim /* If the channel is not yet acquired by any client */ 412b7d861d9SBoojin Kim bool free; 413b7d861d9SBoojin Kim /* Parent DMAC */ 414b7d861d9SBoojin Kim struct pl330_dmac *dmac; 415b7d861d9SBoojin Kim /* Only two at a time */ 416b7d861d9SBoojin Kim struct _pl330_req req[2]; 417b7d861d9SBoojin Kim /* Index of the last enqueued request */ 418b7d861d9SBoojin Kim unsigned lstenq; 419b7d861d9SBoojin Kim /* Index of the last submitted request or -1 if the DMA is stopped */ 420b7d861d9SBoojin Kim int req_running; 421b7d861d9SBoojin Kim }; 422b7d861d9SBoojin Kim 423b7d861d9SBoojin Kim enum pl330_dmac_state { 424b7d861d9SBoojin Kim UNINIT, 425b7d861d9SBoojin Kim INIT, 426b7d861d9SBoojin Kim DYING, 427b7d861d9SBoojin Kim }; 428b7d861d9SBoojin Kim 429b7d861d9SBoojin Kim /* A DMAC */ 430b7d861d9SBoojin Kim struct pl330_dmac { 431b7d861d9SBoojin Kim spinlock_t lock; 432b7d861d9SBoojin Kim /* Holds list of reqs with due callbacks */ 433b7d861d9SBoojin Kim struct list_head req_done; 434b7d861d9SBoojin Kim /* Pointer to platform specific stuff */ 435b7d861d9SBoojin Kim struct pl330_info *pinfo; 436b7d861d9SBoojin Kim /* Maximum possible events/irqs */ 437b7d861d9SBoojin Kim int events[32]; 438b7d861d9SBoojin Kim /* BUS address of MicroCode buffer */ 439fed8c457SWill Deacon dma_addr_t mcode_bus; 440b7d861d9SBoojin Kim /* CPU address of MicroCode buffer */ 441b7d861d9SBoojin Kim void *mcode_cpu; 442b7d861d9SBoojin Kim /* List of all Channel threads */ 443b7d861d9SBoojin Kim struct pl330_thread *channels; 444b7d861d9SBoojin Kim /* Pointer to the MANAGER thread */ 445b7d861d9SBoojin Kim struct pl330_thread *manager; 446b7d861d9SBoojin Kim /* To handle bad news in interrupt */ 447b7d861d9SBoojin Kim struct tasklet_struct tasks; 448b7d861d9SBoojin Kim struct _pl330_tbd dmac_tbd; 449b7d861d9SBoojin Kim /* State of DMAC operation */ 450b7d861d9SBoojin Kim enum pl330_dmac_state state; 451b7d861d9SBoojin Kim }; 452b7d861d9SBoojin Kim 453b3040e40SJassi Brar enum desc_status { 454b3040e40SJassi Brar /* In the DMAC pool */ 455b3040e40SJassi Brar FREE, 456b3040e40SJassi Brar /* 457d73111c6SMasanari Iida * Allocated to some channel during prep_xxx 458b3040e40SJassi Brar * Also may be sitting on the work_list. 459b3040e40SJassi Brar */ 460b3040e40SJassi Brar PREP, 461b3040e40SJassi Brar /* 462b3040e40SJassi Brar * Sitting on the work_list and already submitted 463b3040e40SJassi Brar * to the PL330 core. Not more than two descriptors 464b3040e40SJassi Brar * of a channel can be BUSY at any time. 465b3040e40SJassi Brar */ 466b3040e40SJassi Brar BUSY, 467b3040e40SJassi Brar /* 468b3040e40SJassi Brar * Sitting on the channel work_list but xfer done 469b3040e40SJassi Brar * by PL330 core 470b3040e40SJassi Brar */ 471b3040e40SJassi Brar DONE, 472b3040e40SJassi Brar }; 473b3040e40SJassi Brar 474b3040e40SJassi Brar struct dma_pl330_chan { 475b3040e40SJassi Brar /* Schedule desc completion */ 476b3040e40SJassi Brar struct tasklet_struct task; 477b3040e40SJassi Brar 478b3040e40SJassi Brar /* DMA-Engine Channel */ 479b3040e40SJassi Brar struct dma_chan chan; 480b3040e40SJassi Brar 48104abf5daSLars-Peter Clausen /* List of submitted descriptors */ 48204abf5daSLars-Peter Clausen struct list_head submitted_list; 48304abf5daSLars-Peter Clausen /* List of issued descriptors */ 484b3040e40SJassi Brar struct list_head work_list; 48539ff8613SLars-Peter Clausen /* List of completed descriptors */ 48639ff8613SLars-Peter Clausen struct list_head completed_list; 487b3040e40SJassi Brar 488b3040e40SJassi Brar /* Pointer to the DMAC that manages this channel, 489b3040e40SJassi Brar * NULL if the channel is available to be acquired. 490b3040e40SJassi Brar * As the parent, this DMAC also provides descriptors 491b3040e40SJassi Brar * to the channel. 492b3040e40SJassi Brar */ 493b3040e40SJassi Brar struct dma_pl330_dmac *dmac; 494b3040e40SJassi Brar 495b3040e40SJassi Brar /* To protect channel manipulation */ 496b3040e40SJassi Brar spinlock_t lock; 497b3040e40SJassi Brar 49865ad6060SLars-Peter Clausen /* 49965ad6060SLars-Peter Clausen * Hardware channel thread of PL330 DMAC. NULL if the channel is 50065ad6060SLars-Peter Clausen * available. 501b3040e40SJassi Brar */ 50265ad6060SLars-Peter Clausen struct pl330_thread *thread; 5031b9bb715SBoojin Kim 5041b9bb715SBoojin Kim /* For D-to-M and M-to-D channels */ 5051b9bb715SBoojin Kim int burst_sz; /* the peripheral fifo width */ 5061d0c1d60SBoojin Kim int burst_len; /* the number of burst */ 5071b9bb715SBoojin Kim dma_addr_t fifo_addr; 50842bc9cf4SBoojin Kim 50942bc9cf4SBoojin Kim /* for cyclic capability */ 51042bc9cf4SBoojin Kim bool cyclic; 511b3040e40SJassi Brar }; 512b3040e40SJassi Brar 513b3040e40SJassi Brar struct dma_pl330_dmac { 514b3040e40SJassi Brar struct pl330_info pif; 515b3040e40SJassi Brar 516b3040e40SJassi Brar /* DMA-Engine Device */ 517b3040e40SJassi Brar struct dma_device ddma; 518b3040e40SJassi Brar 519b714b84eSLars-Peter Clausen /* Holds info about sg limitations */ 520b714b84eSLars-Peter Clausen struct device_dma_parameters dma_parms; 521b714b84eSLars-Peter Clausen 522b3040e40SJassi Brar /* Pool of descriptors available for the DMAC's channels */ 523b3040e40SJassi Brar struct list_head desc_pool; 524b3040e40SJassi Brar /* To protect desc_pool manipulation */ 525b3040e40SJassi Brar spinlock_t pool_lock; 526b3040e40SJassi Brar 527b3040e40SJassi Brar /* Peripheral channels connected to this DMAC */ 52870cbb163SLars-Peter Clausen unsigned int num_peripherals; 5294e0e6109SRob Herring struct dma_pl330_chan *peripherals; /* keep at end */ 530b3040e40SJassi Brar }; 531b3040e40SJassi Brar 532b3040e40SJassi Brar struct dma_pl330_desc { 533b3040e40SJassi Brar /* To attach to a queue as child */ 534b3040e40SJassi Brar struct list_head node; 535b3040e40SJassi Brar 536b3040e40SJassi Brar /* Descriptor for the DMA Engine API */ 537b3040e40SJassi Brar struct dma_async_tx_descriptor txd; 538b3040e40SJassi Brar 539b3040e40SJassi Brar /* Xfer for PL330 core */ 540b3040e40SJassi Brar struct pl330_xfer px; 541b3040e40SJassi Brar 542b3040e40SJassi Brar struct pl330_reqcfg rqcfg; 543b3040e40SJassi Brar struct pl330_req req; 544b3040e40SJassi Brar 545b3040e40SJassi Brar enum desc_status status; 546b3040e40SJassi Brar 547b3040e40SJassi Brar /* The channel which currently holds this desc */ 548b3040e40SJassi Brar struct dma_pl330_chan *pchan; 549b3040e40SJassi Brar }; 550b3040e40SJassi Brar 551b7d861d9SBoojin Kim static inline bool _queue_empty(struct pl330_thread *thrd) 552b7d861d9SBoojin Kim { 553b7d861d9SBoojin Kim return (IS_FREE(&thrd->req[0]) && IS_FREE(&thrd->req[1])) 554b7d861d9SBoojin Kim ? true : false; 555b7d861d9SBoojin Kim } 556b7d861d9SBoojin Kim 557b7d861d9SBoojin Kim static inline bool _queue_full(struct pl330_thread *thrd) 558b7d861d9SBoojin Kim { 559b7d861d9SBoojin Kim return (IS_FREE(&thrd->req[0]) || IS_FREE(&thrd->req[1])) 560b7d861d9SBoojin Kim ? false : true; 561b7d861d9SBoojin Kim } 562b7d861d9SBoojin Kim 563b7d861d9SBoojin Kim static inline bool is_manager(struct pl330_thread *thrd) 564b7d861d9SBoojin Kim { 565b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 566b7d861d9SBoojin Kim 567b7d861d9SBoojin Kim /* MANAGER is indexed at the end */ 568b7d861d9SBoojin Kim if (thrd->id == pl330->pinfo->pcfg.num_chan) 569b7d861d9SBoojin Kim return true; 570b7d861d9SBoojin Kim else 571b7d861d9SBoojin Kim return false; 572b7d861d9SBoojin Kim } 573b7d861d9SBoojin Kim 574b7d861d9SBoojin Kim /* If manager of the thread is in Non-Secure mode */ 575b7d861d9SBoojin Kim static inline bool _manager_ns(struct pl330_thread *thrd) 576b7d861d9SBoojin Kim { 577b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 578b7d861d9SBoojin Kim 579b7d861d9SBoojin Kim return (pl330->pinfo->pcfg.mode & DMAC_MODE_NS) ? true : false; 580b7d861d9SBoojin Kim } 581b7d861d9SBoojin Kim 5823ecf51a4SBoojin Kim static inline u32 get_revision(u32 periph_id) 5833ecf51a4SBoojin Kim { 5843ecf51a4SBoojin Kim return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; 5853ecf51a4SBoojin Kim } 5863ecf51a4SBoojin Kim 587b7d861d9SBoojin Kim static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[], 588b7d861d9SBoojin Kim enum pl330_dst da, u16 val) 589b7d861d9SBoojin Kim { 590b7d861d9SBoojin Kim if (dry_run) 591b7d861d9SBoojin Kim return SZ_DMAADDH; 592b7d861d9SBoojin Kim 593b7d861d9SBoojin Kim buf[0] = CMD_DMAADDH; 594b7d861d9SBoojin Kim buf[0] |= (da << 1); 595b7d861d9SBoojin Kim *((u16 *)&buf[1]) = val; 596b7d861d9SBoojin Kim 597b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n", 598b7d861d9SBoojin Kim da == 1 ? "DA" : "SA", val); 599b7d861d9SBoojin Kim 600b7d861d9SBoojin Kim return SZ_DMAADDH; 601b7d861d9SBoojin Kim } 602b7d861d9SBoojin Kim 603b7d861d9SBoojin Kim static inline u32 _emit_END(unsigned dry_run, u8 buf[]) 604b7d861d9SBoojin Kim { 605b7d861d9SBoojin Kim if (dry_run) 606b7d861d9SBoojin Kim return SZ_DMAEND; 607b7d861d9SBoojin Kim 608b7d861d9SBoojin Kim buf[0] = CMD_DMAEND; 609b7d861d9SBoojin Kim 610b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); 611b7d861d9SBoojin Kim 612b7d861d9SBoojin Kim return SZ_DMAEND; 613b7d861d9SBoojin Kim } 614b7d861d9SBoojin Kim 615b7d861d9SBoojin Kim static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) 616b7d861d9SBoojin Kim { 617b7d861d9SBoojin Kim if (dry_run) 618b7d861d9SBoojin Kim return SZ_DMAFLUSHP; 619b7d861d9SBoojin Kim 620b7d861d9SBoojin Kim buf[0] = CMD_DMAFLUSHP; 621b7d861d9SBoojin Kim 622b7d861d9SBoojin Kim peri &= 0x1f; 623b7d861d9SBoojin Kim peri <<= 3; 624b7d861d9SBoojin Kim buf[1] = peri; 625b7d861d9SBoojin Kim 626b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); 627b7d861d9SBoojin Kim 628b7d861d9SBoojin Kim return SZ_DMAFLUSHP; 629b7d861d9SBoojin Kim } 630b7d861d9SBoojin Kim 631b7d861d9SBoojin Kim static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) 632b7d861d9SBoojin Kim { 633b7d861d9SBoojin Kim if (dry_run) 634b7d861d9SBoojin Kim return SZ_DMALD; 635b7d861d9SBoojin Kim 636b7d861d9SBoojin Kim buf[0] = CMD_DMALD; 637b7d861d9SBoojin Kim 638b7d861d9SBoojin Kim if (cond == SINGLE) 639b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 640b7d861d9SBoojin Kim else if (cond == BURST) 641b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (1 << 0); 642b7d861d9SBoojin Kim 643b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", 644b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); 645b7d861d9SBoojin Kim 646b7d861d9SBoojin Kim return SZ_DMALD; 647b7d861d9SBoojin Kim } 648b7d861d9SBoojin Kim 649b7d861d9SBoojin Kim static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], 650b7d861d9SBoojin Kim enum pl330_cond cond, u8 peri) 651b7d861d9SBoojin Kim { 652b7d861d9SBoojin Kim if (dry_run) 653b7d861d9SBoojin Kim return SZ_DMALDP; 654b7d861d9SBoojin Kim 655b7d861d9SBoojin Kim buf[0] = CMD_DMALDP; 656b7d861d9SBoojin Kim 657b7d861d9SBoojin Kim if (cond == BURST) 658b7d861d9SBoojin Kim buf[0] |= (1 << 1); 659b7d861d9SBoojin Kim 660b7d861d9SBoojin Kim peri &= 0x1f; 661b7d861d9SBoojin Kim peri <<= 3; 662b7d861d9SBoojin Kim buf[1] = peri; 663b7d861d9SBoojin Kim 664b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", 665b7d861d9SBoojin Kim cond == SINGLE ? 'S' : 'B', peri >> 3); 666b7d861d9SBoojin Kim 667b7d861d9SBoojin Kim return SZ_DMALDP; 668b7d861d9SBoojin Kim } 669b7d861d9SBoojin Kim 670b7d861d9SBoojin Kim static inline u32 _emit_LP(unsigned dry_run, u8 buf[], 671b7d861d9SBoojin Kim unsigned loop, u8 cnt) 672b7d861d9SBoojin Kim { 673b7d861d9SBoojin Kim if (dry_run) 674b7d861d9SBoojin Kim return SZ_DMALP; 675b7d861d9SBoojin Kim 676b7d861d9SBoojin Kim buf[0] = CMD_DMALP; 677b7d861d9SBoojin Kim 678b7d861d9SBoojin Kim if (loop) 679b7d861d9SBoojin Kim buf[0] |= (1 << 1); 680b7d861d9SBoojin Kim 681b7d861d9SBoojin Kim cnt--; /* DMAC increments by 1 internally */ 682b7d861d9SBoojin Kim buf[1] = cnt; 683b7d861d9SBoojin Kim 684b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); 685b7d861d9SBoojin Kim 686b7d861d9SBoojin Kim return SZ_DMALP; 687b7d861d9SBoojin Kim } 688b7d861d9SBoojin Kim 689b7d861d9SBoojin Kim struct _arg_LPEND { 690b7d861d9SBoojin Kim enum pl330_cond cond; 691b7d861d9SBoojin Kim bool forever; 692b7d861d9SBoojin Kim unsigned loop; 693b7d861d9SBoojin Kim u8 bjump; 694b7d861d9SBoojin Kim }; 695b7d861d9SBoojin Kim 696b7d861d9SBoojin Kim static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], 697b7d861d9SBoojin Kim const struct _arg_LPEND *arg) 698b7d861d9SBoojin Kim { 699b7d861d9SBoojin Kim enum pl330_cond cond = arg->cond; 700b7d861d9SBoojin Kim bool forever = arg->forever; 701b7d861d9SBoojin Kim unsigned loop = arg->loop; 702b7d861d9SBoojin Kim u8 bjump = arg->bjump; 703b7d861d9SBoojin Kim 704b7d861d9SBoojin Kim if (dry_run) 705b7d861d9SBoojin Kim return SZ_DMALPEND; 706b7d861d9SBoojin Kim 707b7d861d9SBoojin Kim buf[0] = CMD_DMALPEND; 708b7d861d9SBoojin Kim 709b7d861d9SBoojin Kim if (loop) 710b7d861d9SBoojin Kim buf[0] |= (1 << 2); 711b7d861d9SBoojin Kim 712b7d861d9SBoojin Kim if (!forever) 713b7d861d9SBoojin Kim buf[0] |= (1 << 4); 714b7d861d9SBoojin Kim 715b7d861d9SBoojin Kim if (cond == SINGLE) 716b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 717b7d861d9SBoojin Kim else if (cond == BURST) 718b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (1 << 0); 719b7d861d9SBoojin Kim 720b7d861d9SBoojin Kim buf[1] = bjump; 721b7d861d9SBoojin Kim 722b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", 723b7d861d9SBoojin Kim forever ? "FE" : "END", 724b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), 725b7d861d9SBoojin Kim loop ? '1' : '0', 726b7d861d9SBoojin Kim bjump); 727b7d861d9SBoojin Kim 728b7d861d9SBoojin Kim return SZ_DMALPEND; 729b7d861d9SBoojin Kim } 730b7d861d9SBoojin Kim 731b7d861d9SBoojin Kim static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) 732b7d861d9SBoojin Kim { 733b7d861d9SBoojin Kim if (dry_run) 734b7d861d9SBoojin Kim return SZ_DMAKILL; 735b7d861d9SBoojin Kim 736b7d861d9SBoojin Kim buf[0] = CMD_DMAKILL; 737b7d861d9SBoojin Kim 738b7d861d9SBoojin Kim return SZ_DMAKILL; 739b7d861d9SBoojin Kim } 740b7d861d9SBoojin Kim 741b7d861d9SBoojin Kim static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], 742b7d861d9SBoojin Kim enum dmamov_dst dst, u32 val) 743b7d861d9SBoojin Kim { 744b7d861d9SBoojin Kim if (dry_run) 745b7d861d9SBoojin Kim return SZ_DMAMOV; 746b7d861d9SBoojin Kim 747b7d861d9SBoojin Kim buf[0] = CMD_DMAMOV; 748b7d861d9SBoojin Kim buf[1] = dst; 749b7d861d9SBoojin Kim *((u32 *)&buf[2]) = val; 750b7d861d9SBoojin Kim 751b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", 752b7d861d9SBoojin Kim dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); 753b7d861d9SBoojin Kim 754b7d861d9SBoojin Kim return SZ_DMAMOV; 755b7d861d9SBoojin Kim } 756b7d861d9SBoojin Kim 757b7d861d9SBoojin Kim static inline u32 _emit_NOP(unsigned dry_run, u8 buf[]) 758b7d861d9SBoojin Kim { 759b7d861d9SBoojin Kim if (dry_run) 760b7d861d9SBoojin Kim return SZ_DMANOP; 761b7d861d9SBoojin Kim 762b7d861d9SBoojin Kim buf[0] = CMD_DMANOP; 763b7d861d9SBoojin Kim 764b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n"); 765b7d861d9SBoojin Kim 766b7d861d9SBoojin Kim return SZ_DMANOP; 767b7d861d9SBoojin Kim } 768b7d861d9SBoojin Kim 769b7d861d9SBoojin Kim static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) 770b7d861d9SBoojin Kim { 771b7d861d9SBoojin Kim if (dry_run) 772b7d861d9SBoojin Kim return SZ_DMARMB; 773b7d861d9SBoojin Kim 774b7d861d9SBoojin Kim buf[0] = CMD_DMARMB; 775b7d861d9SBoojin Kim 776b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); 777b7d861d9SBoojin Kim 778b7d861d9SBoojin Kim return SZ_DMARMB; 779b7d861d9SBoojin Kim } 780b7d861d9SBoojin Kim 781b7d861d9SBoojin Kim static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) 782b7d861d9SBoojin Kim { 783b7d861d9SBoojin Kim if (dry_run) 784b7d861d9SBoojin Kim return SZ_DMASEV; 785b7d861d9SBoojin Kim 786b7d861d9SBoojin Kim buf[0] = CMD_DMASEV; 787b7d861d9SBoojin Kim 788b7d861d9SBoojin Kim ev &= 0x1f; 789b7d861d9SBoojin Kim ev <<= 3; 790b7d861d9SBoojin Kim buf[1] = ev; 791b7d861d9SBoojin Kim 792b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); 793b7d861d9SBoojin Kim 794b7d861d9SBoojin Kim return SZ_DMASEV; 795b7d861d9SBoojin Kim } 796b7d861d9SBoojin Kim 797b7d861d9SBoojin Kim static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) 798b7d861d9SBoojin Kim { 799b7d861d9SBoojin Kim if (dry_run) 800b7d861d9SBoojin Kim return SZ_DMAST; 801b7d861d9SBoojin Kim 802b7d861d9SBoojin Kim buf[0] = CMD_DMAST; 803b7d861d9SBoojin Kim 804b7d861d9SBoojin Kim if (cond == SINGLE) 805b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 806b7d861d9SBoojin Kim else if (cond == BURST) 807b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (1 << 0); 808b7d861d9SBoojin Kim 809b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", 810b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); 811b7d861d9SBoojin Kim 812b7d861d9SBoojin Kim return SZ_DMAST; 813b7d861d9SBoojin Kim } 814b7d861d9SBoojin Kim 815b7d861d9SBoojin Kim static inline u32 _emit_STP(unsigned dry_run, u8 buf[], 816b7d861d9SBoojin Kim enum pl330_cond cond, u8 peri) 817b7d861d9SBoojin Kim { 818b7d861d9SBoojin Kim if (dry_run) 819b7d861d9SBoojin Kim return SZ_DMASTP; 820b7d861d9SBoojin Kim 821b7d861d9SBoojin Kim buf[0] = CMD_DMASTP; 822b7d861d9SBoojin Kim 823b7d861d9SBoojin Kim if (cond == BURST) 824b7d861d9SBoojin Kim buf[0] |= (1 << 1); 825b7d861d9SBoojin Kim 826b7d861d9SBoojin Kim peri &= 0x1f; 827b7d861d9SBoojin Kim peri <<= 3; 828b7d861d9SBoojin Kim buf[1] = peri; 829b7d861d9SBoojin Kim 830b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", 831b7d861d9SBoojin Kim cond == SINGLE ? 'S' : 'B', peri >> 3); 832b7d861d9SBoojin Kim 833b7d861d9SBoojin Kim return SZ_DMASTP; 834b7d861d9SBoojin Kim } 835b7d861d9SBoojin Kim 836b7d861d9SBoojin Kim static inline u32 _emit_STZ(unsigned dry_run, u8 buf[]) 837b7d861d9SBoojin Kim { 838b7d861d9SBoojin Kim if (dry_run) 839b7d861d9SBoojin Kim return SZ_DMASTZ; 840b7d861d9SBoojin Kim 841b7d861d9SBoojin Kim buf[0] = CMD_DMASTZ; 842b7d861d9SBoojin Kim 843b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n"); 844b7d861d9SBoojin Kim 845b7d861d9SBoojin Kim return SZ_DMASTZ; 846b7d861d9SBoojin Kim } 847b7d861d9SBoojin Kim 848b7d861d9SBoojin Kim static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, 849b7d861d9SBoojin Kim unsigned invalidate) 850b7d861d9SBoojin Kim { 851b7d861d9SBoojin Kim if (dry_run) 852b7d861d9SBoojin Kim return SZ_DMAWFE; 853b7d861d9SBoojin Kim 854b7d861d9SBoojin Kim buf[0] = CMD_DMAWFE; 855b7d861d9SBoojin Kim 856b7d861d9SBoojin Kim ev &= 0x1f; 857b7d861d9SBoojin Kim ev <<= 3; 858b7d861d9SBoojin Kim buf[1] = ev; 859b7d861d9SBoojin Kim 860b7d861d9SBoojin Kim if (invalidate) 861b7d861d9SBoojin Kim buf[1] |= (1 << 1); 862b7d861d9SBoojin Kim 863b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n", 864b7d861d9SBoojin Kim ev >> 3, invalidate ? ", I" : ""); 865b7d861d9SBoojin Kim 866b7d861d9SBoojin Kim return SZ_DMAWFE; 867b7d861d9SBoojin Kim } 868b7d861d9SBoojin Kim 869b7d861d9SBoojin Kim static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], 870b7d861d9SBoojin Kim enum pl330_cond cond, u8 peri) 871b7d861d9SBoojin Kim { 872b7d861d9SBoojin Kim if (dry_run) 873b7d861d9SBoojin Kim return SZ_DMAWFP; 874b7d861d9SBoojin Kim 875b7d861d9SBoojin Kim buf[0] = CMD_DMAWFP; 876b7d861d9SBoojin Kim 877b7d861d9SBoojin Kim if (cond == SINGLE) 878b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (0 << 0); 879b7d861d9SBoojin Kim else if (cond == BURST) 880b7d861d9SBoojin Kim buf[0] |= (1 << 1) | (0 << 0); 881b7d861d9SBoojin Kim else 882b7d861d9SBoojin Kim buf[0] |= (0 << 1) | (1 << 0); 883b7d861d9SBoojin Kim 884b7d861d9SBoojin Kim peri &= 0x1f; 885b7d861d9SBoojin Kim peri <<= 3; 886b7d861d9SBoojin Kim buf[1] = peri; 887b7d861d9SBoojin Kim 888b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", 889b7d861d9SBoojin Kim cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); 890b7d861d9SBoojin Kim 891b7d861d9SBoojin Kim return SZ_DMAWFP; 892b7d861d9SBoojin Kim } 893b7d861d9SBoojin Kim 894b7d861d9SBoojin Kim static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) 895b7d861d9SBoojin Kim { 896b7d861d9SBoojin Kim if (dry_run) 897b7d861d9SBoojin Kim return SZ_DMAWMB; 898b7d861d9SBoojin Kim 899b7d861d9SBoojin Kim buf[0] = CMD_DMAWMB; 900b7d861d9SBoojin Kim 901b7d861d9SBoojin Kim PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); 902b7d861d9SBoojin Kim 903b7d861d9SBoojin Kim return SZ_DMAWMB; 904b7d861d9SBoojin Kim } 905b7d861d9SBoojin Kim 906b7d861d9SBoojin Kim struct _arg_GO { 907b7d861d9SBoojin Kim u8 chan; 908b7d861d9SBoojin Kim u32 addr; 909b7d861d9SBoojin Kim unsigned ns; 910b7d861d9SBoojin Kim }; 911b7d861d9SBoojin Kim 912b7d861d9SBoojin Kim static inline u32 _emit_GO(unsigned dry_run, u8 buf[], 913b7d861d9SBoojin Kim const struct _arg_GO *arg) 914b7d861d9SBoojin Kim { 915b7d861d9SBoojin Kim u8 chan = arg->chan; 916b7d861d9SBoojin Kim u32 addr = arg->addr; 917b7d861d9SBoojin Kim unsigned ns = arg->ns; 918b7d861d9SBoojin Kim 919b7d861d9SBoojin Kim if (dry_run) 920b7d861d9SBoojin Kim return SZ_DMAGO; 921b7d861d9SBoojin Kim 922b7d861d9SBoojin Kim buf[0] = CMD_DMAGO; 923b7d861d9SBoojin Kim buf[0] |= (ns << 1); 924b7d861d9SBoojin Kim 925b7d861d9SBoojin Kim buf[1] = chan & 0x7; 926b7d861d9SBoojin Kim 927b7d861d9SBoojin Kim *((u32 *)&buf[2]) = addr; 928b7d861d9SBoojin Kim 929b7d861d9SBoojin Kim return SZ_DMAGO; 930b7d861d9SBoojin Kim } 931b7d861d9SBoojin Kim 932b7d861d9SBoojin Kim #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 933b7d861d9SBoojin Kim 934b7d861d9SBoojin Kim /* Returns Time-Out */ 935b7d861d9SBoojin Kim static bool _until_dmac_idle(struct pl330_thread *thrd) 936b7d861d9SBoojin Kim { 937b7d861d9SBoojin Kim void __iomem *regs = thrd->dmac->pinfo->base; 938b7d861d9SBoojin Kim unsigned long loops = msecs_to_loops(5); 939b7d861d9SBoojin Kim 940b7d861d9SBoojin Kim do { 941b7d861d9SBoojin Kim /* Until Manager is Idle */ 942b7d861d9SBoojin Kim if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) 943b7d861d9SBoojin Kim break; 944b7d861d9SBoojin Kim 945b7d861d9SBoojin Kim cpu_relax(); 946b7d861d9SBoojin Kim } while (--loops); 947b7d861d9SBoojin Kim 948b7d861d9SBoojin Kim if (!loops) 949b7d861d9SBoojin Kim return true; 950b7d861d9SBoojin Kim 951b7d861d9SBoojin Kim return false; 952b7d861d9SBoojin Kim } 953b7d861d9SBoojin Kim 954b7d861d9SBoojin Kim static inline void _execute_DBGINSN(struct pl330_thread *thrd, 955b7d861d9SBoojin Kim u8 insn[], bool as_manager) 956b7d861d9SBoojin Kim { 957b7d861d9SBoojin Kim void __iomem *regs = thrd->dmac->pinfo->base; 958b7d861d9SBoojin Kim u32 val; 959b7d861d9SBoojin Kim 960b7d861d9SBoojin Kim val = (insn[0] << 16) | (insn[1] << 24); 961b7d861d9SBoojin Kim if (!as_manager) { 962b7d861d9SBoojin Kim val |= (1 << 0); 963b7d861d9SBoojin Kim val |= (thrd->id << 8); /* Channel Number */ 964b7d861d9SBoojin Kim } 965b7d861d9SBoojin Kim writel(val, regs + DBGINST0); 966b7d861d9SBoojin Kim 967b7d861d9SBoojin Kim val = *((u32 *)&insn[2]); 968b7d861d9SBoojin Kim writel(val, regs + DBGINST1); 969b7d861d9SBoojin Kim 970b7d861d9SBoojin Kim /* If timed out due to halted state-machine */ 971b7d861d9SBoojin Kim if (_until_dmac_idle(thrd)) { 972b7d861d9SBoojin Kim dev_err(thrd->dmac->pinfo->dev, "DMAC halted!\n"); 973b7d861d9SBoojin Kim return; 974b7d861d9SBoojin Kim } 975b7d861d9SBoojin Kim 976b7d861d9SBoojin Kim /* Get going */ 977b7d861d9SBoojin Kim writel(0, regs + DBGCMD); 978b7d861d9SBoojin Kim } 979b7d861d9SBoojin Kim 980b7d861d9SBoojin Kim /* 981b7d861d9SBoojin Kim * Mark a _pl330_req as free. 982b7d861d9SBoojin Kim * We do it by writing DMAEND as the first instruction 983b7d861d9SBoojin Kim * because no valid request is going to have DMAEND as 984b7d861d9SBoojin Kim * its first instruction to execute. 985b7d861d9SBoojin Kim */ 986b7d861d9SBoojin Kim static void mark_free(struct pl330_thread *thrd, int idx) 987b7d861d9SBoojin Kim { 988b7d861d9SBoojin Kim struct _pl330_req *req = &thrd->req[idx]; 989b7d861d9SBoojin Kim 990b7d861d9SBoojin Kim _emit_END(0, req->mc_cpu); 991b7d861d9SBoojin Kim 992b7d861d9SBoojin Kim thrd->req_running = -1; 993b7d861d9SBoojin Kim } 994b7d861d9SBoojin Kim 995b7d861d9SBoojin Kim static inline u32 _state(struct pl330_thread *thrd) 996b7d861d9SBoojin Kim { 997b7d861d9SBoojin Kim void __iomem *regs = thrd->dmac->pinfo->base; 998b7d861d9SBoojin Kim u32 val; 999b7d861d9SBoojin Kim 1000b7d861d9SBoojin Kim if (is_manager(thrd)) 1001b7d861d9SBoojin Kim val = readl(regs + DS) & 0xf; 1002b7d861d9SBoojin Kim else 1003b7d861d9SBoojin Kim val = readl(regs + CS(thrd->id)) & 0xf; 1004b7d861d9SBoojin Kim 1005b7d861d9SBoojin Kim switch (val) { 1006b7d861d9SBoojin Kim case DS_ST_STOP: 1007b7d861d9SBoojin Kim return PL330_STATE_STOPPED; 1008b7d861d9SBoojin Kim case DS_ST_EXEC: 1009b7d861d9SBoojin Kim return PL330_STATE_EXECUTING; 1010b7d861d9SBoojin Kim case DS_ST_CMISS: 1011b7d861d9SBoojin Kim return PL330_STATE_CACHEMISS; 1012b7d861d9SBoojin Kim case DS_ST_UPDTPC: 1013b7d861d9SBoojin Kim return PL330_STATE_UPDTPC; 1014b7d861d9SBoojin Kim case DS_ST_WFE: 1015b7d861d9SBoojin Kim return PL330_STATE_WFE; 1016b7d861d9SBoojin Kim case DS_ST_FAULT: 1017b7d861d9SBoojin Kim return PL330_STATE_FAULTING; 1018b7d861d9SBoojin Kim case DS_ST_ATBRR: 1019b7d861d9SBoojin Kim if (is_manager(thrd)) 1020b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1021b7d861d9SBoojin Kim else 1022b7d861d9SBoojin Kim return PL330_STATE_ATBARRIER; 1023b7d861d9SBoojin Kim case DS_ST_QBUSY: 1024b7d861d9SBoojin Kim if (is_manager(thrd)) 1025b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1026b7d861d9SBoojin Kim else 1027b7d861d9SBoojin Kim return PL330_STATE_QUEUEBUSY; 1028b7d861d9SBoojin Kim case DS_ST_WFP: 1029b7d861d9SBoojin Kim if (is_manager(thrd)) 1030b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1031b7d861d9SBoojin Kim else 1032b7d861d9SBoojin Kim return PL330_STATE_WFP; 1033b7d861d9SBoojin Kim case DS_ST_KILL: 1034b7d861d9SBoojin Kim if (is_manager(thrd)) 1035b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1036b7d861d9SBoojin Kim else 1037b7d861d9SBoojin Kim return PL330_STATE_KILLING; 1038b7d861d9SBoojin Kim case DS_ST_CMPLT: 1039b7d861d9SBoojin Kim if (is_manager(thrd)) 1040b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1041b7d861d9SBoojin Kim else 1042b7d861d9SBoojin Kim return PL330_STATE_COMPLETING; 1043b7d861d9SBoojin Kim case DS_ST_FLTCMP: 1044b7d861d9SBoojin Kim if (is_manager(thrd)) 1045b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1046b7d861d9SBoojin Kim else 1047b7d861d9SBoojin Kim return PL330_STATE_FAULT_COMPLETING; 1048b7d861d9SBoojin Kim default: 1049b7d861d9SBoojin Kim return PL330_STATE_INVALID; 1050b7d861d9SBoojin Kim } 1051b7d861d9SBoojin Kim } 1052b7d861d9SBoojin Kim 1053b7d861d9SBoojin Kim static void _stop(struct pl330_thread *thrd) 1054b7d861d9SBoojin Kim { 1055b7d861d9SBoojin Kim void __iomem *regs = thrd->dmac->pinfo->base; 1056b7d861d9SBoojin Kim u8 insn[6] = {0, 0, 0, 0, 0, 0}; 1057b7d861d9SBoojin Kim 1058b7d861d9SBoojin Kim if (_state(thrd) == PL330_STATE_FAULT_COMPLETING) 1059b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); 1060b7d861d9SBoojin Kim 1061b7d861d9SBoojin Kim /* Return if nothing needs to be done */ 1062b7d861d9SBoojin Kim if (_state(thrd) == PL330_STATE_COMPLETING 1063b7d861d9SBoojin Kim || _state(thrd) == PL330_STATE_KILLING 1064b7d861d9SBoojin Kim || _state(thrd) == PL330_STATE_STOPPED) 1065b7d861d9SBoojin Kim return; 1066b7d861d9SBoojin Kim 1067b7d861d9SBoojin Kim _emit_KILL(0, insn); 1068b7d861d9SBoojin Kim 1069b7d861d9SBoojin Kim /* Stop generating interrupts for SEV */ 1070b7d861d9SBoojin Kim writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN); 1071b7d861d9SBoojin Kim 1072b7d861d9SBoojin Kim _execute_DBGINSN(thrd, insn, is_manager(thrd)); 1073b7d861d9SBoojin Kim } 1074b7d861d9SBoojin Kim 1075b7d861d9SBoojin Kim /* Start doing req 'idx' of thread 'thrd' */ 1076b7d861d9SBoojin Kim static bool _trigger(struct pl330_thread *thrd) 1077b7d861d9SBoojin Kim { 1078b7d861d9SBoojin Kim void __iomem *regs = thrd->dmac->pinfo->base; 1079b7d861d9SBoojin Kim struct _pl330_req *req; 1080b7d861d9SBoojin Kim struct pl330_req *r; 1081b7d861d9SBoojin Kim struct _arg_GO go; 1082b7d861d9SBoojin Kim unsigned ns; 1083b7d861d9SBoojin Kim u8 insn[6] = {0, 0, 0, 0, 0, 0}; 1084b7d861d9SBoojin Kim int idx; 1085b7d861d9SBoojin Kim 1086b7d861d9SBoojin Kim /* Return if already ACTIVE */ 1087b7d861d9SBoojin Kim if (_state(thrd) != PL330_STATE_STOPPED) 1088b7d861d9SBoojin Kim return true; 1089b7d861d9SBoojin Kim 1090b7d861d9SBoojin Kim idx = 1 - thrd->lstenq; 1091b7d861d9SBoojin Kim if (!IS_FREE(&thrd->req[idx])) 1092b7d861d9SBoojin Kim req = &thrd->req[idx]; 1093b7d861d9SBoojin Kim else { 1094b7d861d9SBoojin Kim idx = thrd->lstenq; 1095b7d861d9SBoojin Kim if (!IS_FREE(&thrd->req[idx])) 1096b7d861d9SBoojin Kim req = &thrd->req[idx]; 1097b7d861d9SBoojin Kim else 1098b7d861d9SBoojin Kim req = NULL; 1099b7d861d9SBoojin Kim } 1100b7d861d9SBoojin Kim 1101b7d861d9SBoojin Kim /* Return if no request */ 1102b7d861d9SBoojin Kim if (!req || !req->r) 1103b7d861d9SBoojin Kim return true; 1104b7d861d9SBoojin Kim 1105b7d861d9SBoojin Kim r = req->r; 1106b7d861d9SBoojin Kim 1107b7d861d9SBoojin Kim if (r->cfg) 1108b7d861d9SBoojin Kim ns = r->cfg->nonsecure ? 1 : 0; 1109b7d861d9SBoojin Kim else if (readl(regs + CS(thrd->id)) & CS_CNS) 1110b7d861d9SBoojin Kim ns = 1; 1111b7d861d9SBoojin Kim else 1112b7d861d9SBoojin Kim ns = 0; 1113b7d861d9SBoojin Kim 1114b7d861d9SBoojin Kim /* See 'Abort Sources' point-4 at Page 2-25 */ 1115b7d861d9SBoojin Kim if (_manager_ns(thrd) && !ns) 1116b7d861d9SBoojin Kim dev_info(thrd->dmac->pinfo->dev, "%s:%d Recipe for ABORT!\n", 1117b7d861d9SBoojin Kim __func__, __LINE__); 1118b7d861d9SBoojin Kim 1119b7d861d9SBoojin Kim go.chan = thrd->id; 1120b7d861d9SBoojin Kim go.addr = req->mc_bus; 1121b7d861d9SBoojin Kim go.ns = ns; 1122b7d861d9SBoojin Kim _emit_GO(0, insn, &go); 1123b7d861d9SBoojin Kim 1124b7d861d9SBoojin Kim /* Set to generate interrupts for SEV */ 1125b7d861d9SBoojin Kim writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); 1126b7d861d9SBoojin Kim 1127b7d861d9SBoojin Kim /* Only manager can execute GO */ 1128b7d861d9SBoojin Kim _execute_DBGINSN(thrd, insn, true); 1129b7d861d9SBoojin Kim 1130b7d861d9SBoojin Kim thrd->req_running = idx; 1131b7d861d9SBoojin Kim 1132b7d861d9SBoojin Kim return true; 1133b7d861d9SBoojin Kim } 1134b7d861d9SBoojin Kim 1135b7d861d9SBoojin Kim static bool _start(struct pl330_thread *thrd) 1136b7d861d9SBoojin Kim { 1137b7d861d9SBoojin Kim switch (_state(thrd)) { 1138b7d861d9SBoojin Kim case PL330_STATE_FAULT_COMPLETING: 1139b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); 1140b7d861d9SBoojin Kim 1141b7d861d9SBoojin Kim if (_state(thrd) == PL330_STATE_KILLING) 1142b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_STOPPED) 1143b7d861d9SBoojin Kim 1144b7d861d9SBoojin Kim case PL330_STATE_FAULTING: 1145b7d861d9SBoojin Kim _stop(thrd); 1146b7d861d9SBoojin Kim 1147b7d861d9SBoojin Kim case PL330_STATE_KILLING: 1148b7d861d9SBoojin Kim case PL330_STATE_COMPLETING: 1149b7d861d9SBoojin Kim UNTIL(thrd, PL330_STATE_STOPPED) 1150b7d861d9SBoojin Kim 1151b7d861d9SBoojin Kim case PL330_STATE_STOPPED: 1152b7d861d9SBoojin Kim return _trigger(thrd); 1153b7d861d9SBoojin Kim 1154b7d861d9SBoojin Kim case PL330_STATE_WFP: 1155b7d861d9SBoojin Kim case PL330_STATE_QUEUEBUSY: 1156b7d861d9SBoojin Kim case PL330_STATE_ATBARRIER: 1157b7d861d9SBoojin Kim case PL330_STATE_UPDTPC: 1158b7d861d9SBoojin Kim case PL330_STATE_CACHEMISS: 1159b7d861d9SBoojin Kim case PL330_STATE_EXECUTING: 1160b7d861d9SBoojin Kim return true; 1161b7d861d9SBoojin Kim 1162b7d861d9SBoojin Kim case PL330_STATE_WFE: /* For RESUME, nothing yet */ 1163b7d861d9SBoojin Kim default: 1164b7d861d9SBoojin Kim return false; 1165b7d861d9SBoojin Kim } 1166b7d861d9SBoojin Kim } 1167b7d861d9SBoojin Kim 1168b7d861d9SBoojin Kim static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], 1169b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1170b7d861d9SBoojin Kim { 1171b7d861d9SBoojin Kim int off = 0; 11723ecf51a4SBoojin Kim struct pl330_config *pcfg = pxs->r->cfg->pcfg; 1173b7d861d9SBoojin Kim 11743ecf51a4SBoojin Kim /* check lock-up free version */ 11753ecf51a4SBoojin Kim if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { 11763ecf51a4SBoojin Kim while (cyc--) { 11773ecf51a4SBoojin Kim off += _emit_LD(dry_run, &buf[off], ALWAYS); 11783ecf51a4SBoojin Kim off += _emit_ST(dry_run, &buf[off], ALWAYS); 11793ecf51a4SBoojin Kim } 11803ecf51a4SBoojin Kim } else { 1181b7d861d9SBoojin Kim while (cyc--) { 1182b7d861d9SBoojin Kim off += _emit_LD(dry_run, &buf[off], ALWAYS); 1183b7d861d9SBoojin Kim off += _emit_RMB(dry_run, &buf[off]); 1184b7d861d9SBoojin Kim off += _emit_ST(dry_run, &buf[off], ALWAYS); 1185b7d861d9SBoojin Kim off += _emit_WMB(dry_run, &buf[off]); 1186b7d861d9SBoojin Kim } 11873ecf51a4SBoojin Kim } 1188b7d861d9SBoojin Kim 1189b7d861d9SBoojin Kim return off; 1190b7d861d9SBoojin Kim } 1191b7d861d9SBoojin Kim 1192b7d861d9SBoojin Kim static inline int _ldst_devtomem(unsigned dry_run, u8 buf[], 1193b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1194b7d861d9SBoojin Kim { 1195b7d861d9SBoojin Kim int off = 0; 1196b7d861d9SBoojin Kim 1197b7d861d9SBoojin Kim while (cyc--) { 1198b7d861d9SBoojin Kim off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri); 1199b7d861d9SBoojin Kim off += _emit_LDP(dry_run, &buf[off], SINGLE, pxs->r->peri); 1200b7d861d9SBoojin Kim off += _emit_ST(dry_run, &buf[off], ALWAYS); 1201b7d861d9SBoojin Kim off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri); 1202b7d861d9SBoojin Kim } 1203b7d861d9SBoojin Kim 1204b7d861d9SBoojin Kim return off; 1205b7d861d9SBoojin Kim } 1206b7d861d9SBoojin Kim 1207b7d861d9SBoojin Kim static inline int _ldst_memtodev(unsigned dry_run, u8 buf[], 1208b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1209b7d861d9SBoojin Kim { 1210b7d861d9SBoojin Kim int off = 0; 1211b7d861d9SBoojin Kim 1212b7d861d9SBoojin Kim while (cyc--) { 1213b7d861d9SBoojin Kim off += _emit_WFP(dry_run, &buf[off], SINGLE, pxs->r->peri); 1214b7d861d9SBoojin Kim off += _emit_LD(dry_run, &buf[off], ALWAYS); 1215b7d861d9SBoojin Kim off += _emit_STP(dry_run, &buf[off], SINGLE, pxs->r->peri); 1216b7d861d9SBoojin Kim off += _emit_FLUSHP(dry_run, &buf[off], pxs->r->peri); 1217b7d861d9SBoojin Kim } 1218b7d861d9SBoojin Kim 1219b7d861d9SBoojin Kim return off; 1220b7d861d9SBoojin Kim } 1221b7d861d9SBoojin Kim 1222b7d861d9SBoojin Kim static int _bursts(unsigned dry_run, u8 buf[], 1223b7d861d9SBoojin Kim const struct _xfer_spec *pxs, int cyc) 1224b7d861d9SBoojin Kim { 1225b7d861d9SBoojin Kim int off = 0; 1226b7d861d9SBoojin Kim 1227b7d861d9SBoojin Kim switch (pxs->r->rqtype) { 1228585a9d0bSLars-Peter Clausen case DMA_MEM_TO_DEV: 1229b7d861d9SBoojin Kim off += _ldst_memtodev(dry_run, &buf[off], pxs, cyc); 1230b7d861d9SBoojin Kim break; 1231585a9d0bSLars-Peter Clausen case DMA_DEV_TO_MEM: 1232b7d861d9SBoojin Kim off += _ldst_devtomem(dry_run, &buf[off], pxs, cyc); 1233b7d861d9SBoojin Kim break; 1234585a9d0bSLars-Peter Clausen case DMA_MEM_TO_MEM: 1235b7d861d9SBoojin Kim off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); 1236b7d861d9SBoojin Kim break; 1237b7d861d9SBoojin Kim default: 1238b7d861d9SBoojin Kim off += 0x40000000; /* Scare off the Client */ 1239b7d861d9SBoojin Kim break; 1240b7d861d9SBoojin Kim } 1241b7d861d9SBoojin Kim 1242b7d861d9SBoojin Kim return off; 1243b7d861d9SBoojin Kim } 1244b7d861d9SBoojin Kim 1245b7d861d9SBoojin Kim /* Returns bytes consumed and updates bursts */ 1246b7d861d9SBoojin Kim static inline int _loop(unsigned dry_run, u8 buf[], 1247b7d861d9SBoojin Kim unsigned long *bursts, const struct _xfer_spec *pxs) 1248b7d861d9SBoojin Kim { 1249b7d861d9SBoojin Kim int cyc, cycmax, szlp, szlpend, szbrst, off; 1250b7d861d9SBoojin Kim unsigned lcnt0, lcnt1, ljmp0, ljmp1; 1251b7d861d9SBoojin Kim struct _arg_LPEND lpend; 1252b7d861d9SBoojin Kim 1253b7d861d9SBoojin Kim /* Max iterations possible in DMALP is 256 */ 1254b7d861d9SBoojin Kim if (*bursts >= 256*256) { 1255b7d861d9SBoojin Kim lcnt1 = 256; 1256b7d861d9SBoojin Kim lcnt0 = 256; 1257b7d861d9SBoojin Kim cyc = *bursts / lcnt1 / lcnt0; 1258b7d861d9SBoojin Kim } else if (*bursts > 256) { 1259b7d861d9SBoojin Kim lcnt1 = 256; 1260b7d861d9SBoojin Kim lcnt0 = *bursts / lcnt1; 1261b7d861d9SBoojin Kim cyc = 1; 1262b7d861d9SBoojin Kim } else { 1263b7d861d9SBoojin Kim lcnt1 = *bursts; 1264b7d861d9SBoojin Kim lcnt0 = 0; 1265b7d861d9SBoojin Kim cyc = 1; 1266b7d861d9SBoojin Kim } 1267b7d861d9SBoojin Kim 1268b7d861d9SBoojin Kim szlp = _emit_LP(1, buf, 0, 0); 1269b7d861d9SBoojin Kim szbrst = _bursts(1, buf, pxs, 1); 1270b7d861d9SBoojin Kim 1271b7d861d9SBoojin Kim lpend.cond = ALWAYS; 1272b7d861d9SBoojin Kim lpend.forever = false; 1273b7d861d9SBoojin Kim lpend.loop = 0; 1274b7d861d9SBoojin Kim lpend.bjump = 0; 1275b7d861d9SBoojin Kim szlpend = _emit_LPEND(1, buf, &lpend); 1276b7d861d9SBoojin Kim 1277b7d861d9SBoojin Kim if (lcnt0) { 1278b7d861d9SBoojin Kim szlp *= 2; 1279b7d861d9SBoojin Kim szlpend *= 2; 1280b7d861d9SBoojin Kim } 1281b7d861d9SBoojin Kim 1282b7d861d9SBoojin Kim /* 1283b7d861d9SBoojin Kim * Max bursts that we can unroll due to limit on the 1284b7d861d9SBoojin Kim * size of backward jump that can be encoded in DMALPEND 1285b7d861d9SBoojin Kim * which is 8-bits and hence 255 1286b7d861d9SBoojin Kim */ 1287b7d861d9SBoojin Kim cycmax = (255 - (szlp + szlpend)) / szbrst; 1288b7d861d9SBoojin Kim 1289b7d861d9SBoojin Kim cyc = (cycmax < cyc) ? cycmax : cyc; 1290b7d861d9SBoojin Kim 1291b7d861d9SBoojin Kim off = 0; 1292b7d861d9SBoojin Kim 1293b7d861d9SBoojin Kim if (lcnt0) { 1294b7d861d9SBoojin Kim off += _emit_LP(dry_run, &buf[off], 0, lcnt0); 1295b7d861d9SBoojin Kim ljmp0 = off; 1296b7d861d9SBoojin Kim } 1297b7d861d9SBoojin Kim 1298b7d861d9SBoojin Kim off += _emit_LP(dry_run, &buf[off], 1, lcnt1); 1299b7d861d9SBoojin Kim ljmp1 = off; 1300b7d861d9SBoojin Kim 1301b7d861d9SBoojin Kim off += _bursts(dry_run, &buf[off], pxs, cyc); 1302b7d861d9SBoojin Kim 1303b7d861d9SBoojin Kim lpend.cond = ALWAYS; 1304b7d861d9SBoojin Kim lpend.forever = false; 1305b7d861d9SBoojin Kim lpend.loop = 1; 1306b7d861d9SBoojin Kim lpend.bjump = off - ljmp1; 1307b7d861d9SBoojin Kim off += _emit_LPEND(dry_run, &buf[off], &lpend); 1308b7d861d9SBoojin Kim 1309b7d861d9SBoojin Kim if (lcnt0) { 1310b7d861d9SBoojin Kim lpend.cond = ALWAYS; 1311b7d861d9SBoojin Kim lpend.forever = false; 1312b7d861d9SBoojin Kim lpend.loop = 0; 1313b7d861d9SBoojin Kim lpend.bjump = off - ljmp0; 1314b7d861d9SBoojin Kim off += _emit_LPEND(dry_run, &buf[off], &lpend); 1315b7d861d9SBoojin Kim } 1316b7d861d9SBoojin Kim 1317b7d861d9SBoojin Kim *bursts = lcnt1 * cyc; 1318b7d861d9SBoojin Kim if (lcnt0) 1319b7d861d9SBoojin Kim *bursts *= lcnt0; 1320b7d861d9SBoojin Kim 1321b7d861d9SBoojin Kim return off; 1322b7d861d9SBoojin Kim } 1323b7d861d9SBoojin Kim 1324b7d861d9SBoojin Kim static inline int _setup_loops(unsigned dry_run, u8 buf[], 1325b7d861d9SBoojin Kim const struct _xfer_spec *pxs) 1326b7d861d9SBoojin Kim { 1327b7d861d9SBoojin Kim struct pl330_xfer *x = pxs->x; 1328b7d861d9SBoojin Kim u32 ccr = pxs->ccr; 1329b7d861d9SBoojin Kim unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); 1330b7d861d9SBoojin Kim int off = 0; 1331b7d861d9SBoojin Kim 1332b7d861d9SBoojin Kim while (bursts) { 1333b7d861d9SBoojin Kim c = bursts; 1334b7d861d9SBoojin Kim off += _loop(dry_run, &buf[off], &c, pxs); 1335b7d861d9SBoojin Kim bursts -= c; 1336b7d861d9SBoojin Kim } 1337b7d861d9SBoojin Kim 1338b7d861d9SBoojin Kim return off; 1339b7d861d9SBoojin Kim } 1340b7d861d9SBoojin Kim 1341b7d861d9SBoojin Kim static inline int _setup_xfer(unsigned dry_run, u8 buf[], 1342b7d861d9SBoojin Kim const struct _xfer_spec *pxs) 1343b7d861d9SBoojin Kim { 1344b7d861d9SBoojin Kim struct pl330_xfer *x = pxs->x; 1345b7d861d9SBoojin Kim int off = 0; 1346b7d861d9SBoojin Kim 1347b7d861d9SBoojin Kim /* DMAMOV SAR, x->src_addr */ 1348b7d861d9SBoojin Kim off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); 1349b7d861d9SBoojin Kim /* DMAMOV DAR, x->dst_addr */ 1350b7d861d9SBoojin Kim off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr); 1351b7d861d9SBoojin Kim 1352b7d861d9SBoojin Kim /* Setup Loop(s) */ 1353b7d861d9SBoojin Kim off += _setup_loops(dry_run, &buf[off], pxs); 1354b7d861d9SBoojin Kim 1355b7d861d9SBoojin Kim return off; 1356b7d861d9SBoojin Kim } 1357b7d861d9SBoojin Kim 1358b7d861d9SBoojin Kim /* 1359b7d861d9SBoojin Kim * A req is a sequence of one or more xfer units. 1360b7d861d9SBoojin Kim * Returns the number of bytes taken to setup the MC for the req. 1361b7d861d9SBoojin Kim */ 1362b7d861d9SBoojin Kim static int _setup_req(unsigned dry_run, struct pl330_thread *thrd, 1363b7d861d9SBoojin Kim unsigned index, struct _xfer_spec *pxs) 1364b7d861d9SBoojin Kim { 1365b7d861d9SBoojin Kim struct _pl330_req *req = &thrd->req[index]; 1366b7d861d9SBoojin Kim struct pl330_xfer *x; 1367b7d861d9SBoojin Kim u8 *buf = req->mc_cpu; 1368b7d861d9SBoojin Kim int off = 0; 1369b7d861d9SBoojin Kim 1370b7d861d9SBoojin Kim PL330_DBGMC_START(req->mc_bus); 1371b7d861d9SBoojin Kim 1372b7d861d9SBoojin Kim /* DMAMOV CCR, ccr */ 1373b7d861d9SBoojin Kim off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); 1374b7d861d9SBoojin Kim 1375b7d861d9SBoojin Kim x = pxs->r->x; 1376b7d861d9SBoojin Kim /* Error if xfer length is not aligned at burst size */ 1377b7d861d9SBoojin Kim if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr))) 1378b7d861d9SBoojin Kim return -EINVAL; 1379b7d861d9SBoojin Kim 1380b7d861d9SBoojin Kim pxs->x = x; 1381b7d861d9SBoojin Kim off += _setup_xfer(dry_run, &buf[off], pxs); 1382b7d861d9SBoojin Kim 1383b7d861d9SBoojin Kim /* DMASEV peripheral/event */ 1384b7d861d9SBoojin Kim off += _emit_SEV(dry_run, &buf[off], thrd->ev); 1385b7d861d9SBoojin Kim /* DMAEND */ 1386b7d861d9SBoojin Kim off += _emit_END(dry_run, &buf[off]); 1387b7d861d9SBoojin Kim 1388b7d861d9SBoojin Kim return off; 1389b7d861d9SBoojin Kim } 1390b7d861d9SBoojin Kim 1391b7d861d9SBoojin Kim static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) 1392b7d861d9SBoojin Kim { 1393b7d861d9SBoojin Kim u32 ccr = 0; 1394b7d861d9SBoojin Kim 1395b7d861d9SBoojin Kim if (rqc->src_inc) 1396b7d861d9SBoojin Kim ccr |= CC_SRCINC; 1397b7d861d9SBoojin Kim 1398b7d861d9SBoojin Kim if (rqc->dst_inc) 1399b7d861d9SBoojin Kim ccr |= CC_DSTINC; 1400b7d861d9SBoojin Kim 1401b7d861d9SBoojin Kim /* We set same protection levels for Src and DST for now */ 1402b7d861d9SBoojin Kim if (rqc->privileged) 1403b7d861d9SBoojin Kim ccr |= CC_SRCPRI | CC_DSTPRI; 1404b7d861d9SBoojin Kim if (rqc->nonsecure) 1405b7d861d9SBoojin Kim ccr |= CC_SRCNS | CC_DSTNS; 1406b7d861d9SBoojin Kim if (rqc->insnaccess) 1407b7d861d9SBoojin Kim ccr |= CC_SRCIA | CC_DSTIA; 1408b7d861d9SBoojin Kim 1409b7d861d9SBoojin Kim ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); 1410b7d861d9SBoojin Kim ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); 1411b7d861d9SBoojin Kim 1412b7d861d9SBoojin Kim ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); 1413b7d861d9SBoojin Kim ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); 1414b7d861d9SBoojin Kim 1415b7d861d9SBoojin Kim ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); 1416b7d861d9SBoojin Kim ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); 1417b7d861d9SBoojin Kim 1418b7d861d9SBoojin Kim ccr |= (rqc->swap << CC_SWAP_SHFT); 1419b7d861d9SBoojin Kim 1420b7d861d9SBoojin Kim return ccr; 1421b7d861d9SBoojin Kim } 1422b7d861d9SBoojin Kim 1423b7d861d9SBoojin Kim static inline bool _is_valid(u32 ccr) 1424b7d861d9SBoojin Kim { 1425f0564c7eSLars-Peter Clausen enum pl330_cachectrl dcctl; 1426f0564c7eSLars-Peter Clausen enum pl330_cachectrl scctl; 1427b7d861d9SBoojin Kim 1428b7d861d9SBoojin Kim dcctl = (ccr >> CC_DSTCCTRL_SHFT) & CC_DRCCCTRL_MASK; 1429b7d861d9SBoojin Kim scctl = (ccr >> CC_SRCCCTRL_SHFT) & CC_SRCCCTRL_MASK; 1430b7d861d9SBoojin Kim 1431f0564c7eSLars-Peter Clausen if (dcctl == INVALID1 || dcctl == INVALID2 1432f0564c7eSLars-Peter Clausen || scctl == INVALID1 || scctl == INVALID2) 1433b7d861d9SBoojin Kim return false; 1434b7d861d9SBoojin Kim else 1435b7d861d9SBoojin Kim return true; 1436b7d861d9SBoojin Kim } 1437b7d861d9SBoojin Kim 1438b7d861d9SBoojin Kim /* 1439b7d861d9SBoojin Kim * Submit a list of xfers after which the client wants notification. 1440b7d861d9SBoojin Kim * Client is not notified after each xfer unit, just once after all 1441b7d861d9SBoojin Kim * xfer units are done or some error occurs. 1442b7d861d9SBoojin Kim */ 144365ad6060SLars-Peter Clausen static int pl330_submit_req(struct pl330_thread *thrd, struct pl330_req *r) 1444b7d861d9SBoojin Kim { 1445b7d861d9SBoojin Kim struct pl330_dmac *pl330; 1446b7d861d9SBoojin Kim struct pl330_info *pi; 1447b7d861d9SBoojin Kim struct _xfer_spec xs; 1448b7d861d9SBoojin Kim unsigned long flags; 1449b7d861d9SBoojin Kim void __iomem *regs; 1450b7d861d9SBoojin Kim unsigned idx; 1451b7d861d9SBoojin Kim u32 ccr; 1452b7d861d9SBoojin Kim int ret = 0; 1453b7d861d9SBoojin Kim 1454b7d861d9SBoojin Kim /* No Req or Unacquired Channel or DMAC */ 1455b7d861d9SBoojin Kim if (!r || !thrd || thrd->free) 1456b7d861d9SBoojin Kim return -EINVAL; 1457b7d861d9SBoojin Kim 1458b7d861d9SBoojin Kim pl330 = thrd->dmac; 1459b7d861d9SBoojin Kim pi = pl330->pinfo; 1460b7d861d9SBoojin Kim regs = pi->base; 1461b7d861d9SBoojin Kim 1462b7d861d9SBoojin Kim if (pl330->state == DYING 1463b7d861d9SBoojin Kim || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { 1464b7d861d9SBoojin Kim dev_info(thrd->dmac->pinfo->dev, "%s:%d\n", 1465b7d861d9SBoojin Kim __func__, __LINE__); 1466b7d861d9SBoojin Kim return -EAGAIN; 1467b7d861d9SBoojin Kim } 1468b7d861d9SBoojin Kim 1469b7d861d9SBoojin Kim /* If request for non-existing peripheral */ 1470585a9d0bSLars-Peter Clausen if (r->rqtype != DMA_MEM_TO_MEM && r->peri >= pi->pcfg.num_peri) { 1471b7d861d9SBoojin Kim dev_info(thrd->dmac->pinfo->dev, 1472b7d861d9SBoojin Kim "%s:%d Invalid peripheral(%u)!\n", 1473b7d861d9SBoojin Kim __func__, __LINE__, r->peri); 1474b7d861d9SBoojin Kim return -EINVAL; 1475b7d861d9SBoojin Kim } 1476b7d861d9SBoojin Kim 1477b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1478b7d861d9SBoojin Kim 1479b7d861d9SBoojin Kim if (_queue_full(thrd)) { 1480b7d861d9SBoojin Kim ret = -EAGAIN; 1481b7d861d9SBoojin Kim goto xfer_exit; 1482b7d861d9SBoojin Kim } 1483b7d861d9SBoojin Kim 14842e2c682bSSachin Kamat 14852e2c682bSSachin Kamat /* Use last settings, if not provided */ 14862e2c682bSSachin Kamat if (r->cfg) { 1487b7d861d9SBoojin Kim /* Prefer Secure Channel */ 1488b7d861d9SBoojin Kim if (!_manager_ns(thrd)) 1489b7d861d9SBoojin Kim r->cfg->nonsecure = 0; 1490b7d861d9SBoojin Kim else 1491b7d861d9SBoojin Kim r->cfg->nonsecure = 1; 1492b7d861d9SBoojin Kim 1493b7d861d9SBoojin Kim ccr = _prepare_ccr(r->cfg); 14942e2c682bSSachin Kamat } else { 1495b7d861d9SBoojin Kim ccr = readl(regs + CC(thrd->id)); 14962e2c682bSSachin Kamat } 1497b7d861d9SBoojin Kim 1498b7d861d9SBoojin Kim /* If this req doesn't have valid xfer settings */ 1499b7d861d9SBoojin Kim if (!_is_valid(ccr)) { 1500b7d861d9SBoojin Kim ret = -EINVAL; 1501b7d861d9SBoojin Kim dev_info(thrd->dmac->pinfo->dev, "%s:%d Invalid CCR(%x)!\n", 1502b7d861d9SBoojin Kim __func__, __LINE__, ccr); 1503b7d861d9SBoojin Kim goto xfer_exit; 1504b7d861d9SBoojin Kim } 1505b7d861d9SBoojin Kim 1506b7d861d9SBoojin Kim idx = IS_FREE(&thrd->req[0]) ? 0 : 1; 1507b7d861d9SBoojin Kim 1508b7d861d9SBoojin Kim xs.ccr = ccr; 1509b7d861d9SBoojin Kim xs.r = r; 1510b7d861d9SBoojin Kim 1511b7d861d9SBoojin Kim /* First dry run to check if req is acceptable */ 1512b7d861d9SBoojin Kim ret = _setup_req(1, thrd, idx, &xs); 1513b7d861d9SBoojin Kim if (ret < 0) 1514b7d861d9SBoojin Kim goto xfer_exit; 1515b7d861d9SBoojin Kim 1516b7d861d9SBoojin Kim if (ret > pi->mcbufsz / 2) { 1517b7d861d9SBoojin Kim dev_info(thrd->dmac->pinfo->dev, 1518b7d861d9SBoojin Kim "%s:%d Trying increasing mcbufsz\n", 1519b7d861d9SBoojin Kim __func__, __LINE__); 1520b7d861d9SBoojin Kim ret = -ENOMEM; 1521b7d861d9SBoojin Kim goto xfer_exit; 1522b7d861d9SBoojin Kim } 1523b7d861d9SBoojin Kim 1524b7d861d9SBoojin Kim /* Hook the request */ 1525b7d861d9SBoojin Kim thrd->lstenq = idx; 1526b7d861d9SBoojin Kim thrd->req[idx].r = r; 1527be025329SLars-Peter Clausen _setup_req(0, thrd, idx, &xs); 1528b7d861d9SBoojin Kim 1529b7d861d9SBoojin Kim ret = 0; 1530b7d861d9SBoojin Kim 1531b7d861d9SBoojin Kim xfer_exit: 1532b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1533b7d861d9SBoojin Kim 1534b7d861d9SBoojin Kim return ret; 1535b7d861d9SBoojin Kim } 1536b7d861d9SBoojin Kim 15376079d38cSLars-Peter Clausen static void dma_pl330_rqcb(struct pl330_req *req, enum pl330_op_err err) 15386079d38cSLars-Peter Clausen { 15396079d38cSLars-Peter Clausen struct dma_pl330_desc *desc = container_of(req, struct dma_pl330_desc, req); 15406079d38cSLars-Peter Clausen struct dma_pl330_chan *pch = desc->pchan; 15416079d38cSLars-Peter Clausen unsigned long flags; 15426079d38cSLars-Peter Clausen 15436079d38cSLars-Peter Clausen /* If desc aborted */ 15446079d38cSLars-Peter Clausen if (!pch) 15456079d38cSLars-Peter Clausen return; 15466079d38cSLars-Peter Clausen 15476079d38cSLars-Peter Clausen spin_lock_irqsave(&pch->lock, flags); 15486079d38cSLars-Peter Clausen 15496079d38cSLars-Peter Clausen desc->status = DONE; 15506079d38cSLars-Peter Clausen 15516079d38cSLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 15526079d38cSLars-Peter Clausen 15536079d38cSLars-Peter Clausen tasklet_schedule(&pch->task); 15546079d38cSLars-Peter Clausen } 15556079d38cSLars-Peter Clausen 1556b7d861d9SBoojin Kim static void pl330_dotask(unsigned long data) 1557b7d861d9SBoojin Kim { 1558b7d861d9SBoojin Kim struct pl330_dmac *pl330 = (struct pl330_dmac *) data; 1559b7d861d9SBoojin Kim struct pl330_info *pi = pl330->pinfo; 1560b7d861d9SBoojin Kim unsigned long flags; 1561b7d861d9SBoojin Kim int i; 1562b7d861d9SBoojin Kim 1563b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1564b7d861d9SBoojin Kim 1565b7d861d9SBoojin Kim /* The DMAC itself gone nuts */ 1566b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_dmac) { 1567b7d861d9SBoojin Kim pl330->state = DYING; 1568b7d861d9SBoojin Kim /* Reset the manager too */ 1569b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = true; 1570b7d861d9SBoojin Kim /* Clear the reset flag */ 1571b7d861d9SBoojin Kim pl330->dmac_tbd.reset_dmac = false; 1572b7d861d9SBoojin Kim } 1573b7d861d9SBoojin Kim 1574b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_mngr) { 1575b7d861d9SBoojin Kim _stop(pl330->manager); 1576b7d861d9SBoojin Kim /* Reset all channels */ 1577b7d861d9SBoojin Kim pl330->dmac_tbd.reset_chan = (1 << pi->pcfg.num_chan) - 1; 1578b7d861d9SBoojin Kim /* Clear the reset flag */ 1579b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = false; 1580b7d861d9SBoojin Kim } 1581b7d861d9SBoojin Kim 1582b7d861d9SBoojin Kim for (i = 0; i < pi->pcfg.num_chan; i++) { 1583b7d861d9SBoojin Kim 1584b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_chan & (1 << i)) { 1585b7d861d9SBoojin Kim struct pl330_thread *thrd = &pl330->channels[i]; 1586b7d861d9SBoojin Kim void __iomem *regs = pi->base; 1587b7d861d9SBoojin Kim enum pl330_op_err err; 1588b7d861d9SBoojin Kim 1589b7d861d9SBoojin Kim _stop(thrd); 1590b7d861d9SBoojin Kim 1591b7d861d9SBoojin Kim if (readl(regs + FSC) & (1 << thrd->id)) 1592b7d861d9SBoojin Kim err = PL330_ERR_FAIL; 1593b7d861d9SBoojin Kim else 1594b7d861d9SBoojin Kim err = PL330_ERR_ABORT; 1595b7d861d9SBoojin Kim 1596b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 15976079d38cSLars-Peter Clausen dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].r, err); 15986079d38cSLars-Peter Clausen dma_pl330_rqcb(thrd->req[thrd->lstenq].r, err); 1599b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1600b7d861d9SBoojin Kim 1601b7d861d9SBoojin Kim thrd->req[0].r = NULL; 1602b7d861d9SBoojin Kim thrd->req[1].r = NULL; 1603b7d861d9SBoojin Kim mark_free(thrd, 0); 1604b7d861d9SBoojin Kim mark_free(thrd, 1); 1605b7d861d9SBoojin Kim 1606b7d861d9SBoojin Kim /* Clear the reset flag */ 1607b7d861d9SBoojin Kim pl330->dmac_tbd.reset_chan &= ~(1 << i); 1608b7d861d9SBoojin Kim } 1609b7d861d9SBoojin Kim } 1610b7d861d9SBoojin Kim 1611b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1612b7d861d9SBoojin Kim 1613b7d861d9SBoojin Kim return; 1614b7d861d9SBoojin Kim } 1615b7d861d9SBoojin Kim 1616b7d861d9SBoojin Kim /* Returns 1 if state was updated, 0 otherwise */ 1617b7d861d9SBoojin Kim static int pl330_update(const struct pl330_info *pi) 1618b7d861d9SBoojin Kim { 1619fdec53d5SJavi Merino struct pl330_req *rqdone, *tmp; 1620b7d861d9SBoojin Kim struct pl330_dmac *pl330; 1621b7d861d9SBoojin Kim unsigned long flags; 1622b7d861d9SBoojin Kim void __iomem *regs; 1623b7d861d9SBoojin Kim u32 val; 1624b7d861d9SBoojin Kim int id, ev, ret = 0; 1625b7d861d9SBoojin Kim 1626b7d861d9SBoojin Kim if (!pi || !pi->pl330_data) 1627b7d861d9SBoojin Kim return 0; 1628b7d861d9SBoojin Kim 1629b7d861d9SBoojin Kim regs = pi->base; 1630b7d861d9SBoojin Kim pl330 = pi->pl330_data; 1631b7d861d9SBoojin Kim 1632b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1633b7d861d9SBoojin Kim 1634b7d861d9SBoojin Kim val = readl(regs + FSM) & 0x1; 1635b7d861d9SBoojin Kim if (val) 1636b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = true; 1637b7d861d9SBoojin Kim else 1638b7d861d9SBoojin Kim pl330->dmac_tbd.reset_mngr = false; 1639b7d861d9SBoojin Kim 1640b7d861d9SBoojin Kim val = readl(regs + FSC) & ((1 << pi->pcfg.num_chan) - 1); 1641b7d861d9SBoojin Kim pl330->dmac_tbd.reset_chan |= val; 1642b7d861d9SBoojin Kim if (val) { 1643b7d861d9SBoojin Kim int i = 0; 1644b7d861d9SBoojin Kim while (i < pi->pcfg.num_chan) { 1645b7d861d9SBoojin Kim if (val & (1 << i)) { 1646b7d861d9SBoojin Kim dev_info(pi->dev, 1647b7d861d9SBoojin Kim "Reset Channel-%d\t CS-%x FTC-%x\n", 1648b7d861d9SBoojin Kim i, readl(regs + CS(i)), 1649b7d861d9SBoojin Kim readl(regs + FTC(i))); 1650b7d861d9SBoojin Kim _stop(&pl330->channels[i]); 1651b7d861d9SBoojin Kim } 1652b7d861d9SBoojin Kim i++; 1653b7d861d9SBoojin Kim } 1654b7d861d9SBoojin Kim } 1655b7d861d9SBoojin Kim 1656b7d861d9SBoojin Kim /* Check which event happened i.e, thread notified */ 1657b7d861d9SBoojin Kim val = readl(regs + ES); 1658b7d861d9SBoojin Kim if (pi->pcfg.num_events < 32 1659b7d861d9SBoojin Kim && val & ~((1 << pi->pcfg.num_events) - 1)) { 1660b7d861d9SBoojin Kim pl330->dmac_tbd.reset_dmac = true; 1661b7d861d9SBoojin Kim dev_err(pi->dev, "%s:%d Unexpected!\n", __func__, __LINE__); 1662b7d861d9SBoojin Kim ret = 1; 1663b7d861d9SBoojin Kim goto updt_exit; 1664b7d861d9SBoojin Kim } 1665b7d861d9SBoojin Kim 1666b7d861d9SBoojin Kim for (ev = 0; ev < pi->pcfg.num_events; ev++) { 1667b7d861d9SBoojin Kim if (val & (1 << ev)) { /* Event occurred */ 1668b7d861d9SBoojin Kim struct pl330_thread *thrd; 1669b7d861d9SBoojin Kim u32 inten = readl(regs + INTEN); 1670b7d861d9SBoojin Kim int active; 1671b7d861d9SBoojin Kim 1672b7d861d9SBoojin Kim /* Clear the event */ 1673b7d861d9SBoojin Kim if (inten & (1 << ev)) 1674b7d861d9SBoojin Kim writel(1 << ev, regs + INTCLR); 1675b7d861d9SBoojin Kim 1676b7d861d9SBoojin Kim ret = 1; 1677b7d861d9SBoojin Kim 1678b7d861d9SBoojin Kim id = pl330->events[ev]; 1679b7d861d9SBoojin Kim 1680b7d861d9SBoojin Kim thrd = &pl330->channels[id]; 1681b7d861d9SBoojin Kim 1682b7d861d9SBoojin Kim active = thrd->req_running; 1683b7d861d9SBoojin Kim if (active == -1) /* Aborted */ 1684b7d861d9SBoojin Kim continue; 1685b7d861d9SBoojin Kim 1686fdec53d5SJavi Merino /* Detach the req */ 1687fdec53d5SJavi Merino rqdone = thrd->req[active].r; 1688fdec53d5SJavi Merino thrd->req[active].r = NULL; 1689fdec53d5SJavi Merino 1690b7d861d9SBoojin Kim mark_free(thrd, active); 1691b7d861d9SBoojin Kim 1692b7d861d9SBoojin Kim /* Get going again ASAP */ 1693b7d861d9SBoojin Kim _start(thrd); 1694b7d861d9SBoojin Kim 1695b7d861d9SBoojin Kim /* For now, just make a list of callbacks to be done */ 1696b7d861d9SBoojin Kim list_add_tail(&rqdone->rqd, &pl330->req_done); 1697b7d861d9SBoojin Kim } 1698b7d861d9SBoojin Kim } 1699b7d861d9SBoojin Kim 1700b7d861d9SBoojin Kim /* Now that we are in no hurry, do the callbacks */ 1701fdec53d5SJavi Merino list_for_each_entry_safe(rqdone, tmp, &pl330->req_done, rqd) { 1702fdec53d5SJavi Merino list_del(&rqdone->rqd); 1703b7d861d9SBoojin Kim 1704b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 17056079d38cSLars-Peter Clausen dma_pl330_rqcb(rqdone, PL330_ERR_NONE); 1706b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1707b7d861d9SBoojin Kim } 1708b7d861d9SBoojin Kim 1709b7d861d9SBoojin Kim updt_exit: 1710b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1711b7d861d9SBoojin Kim 1712b7d861d9SBoojin Kim if (pl330->dmac_tbd.reset_dmac 1713b7d861d9SBoojin Kim || pl330->dmac_tbd.reset_mngr 1714b7d861d9SBoojin Kim || pl330->dmac_tbd.reset_chan) { 1715b7d861d9SBoojin Kim ret = 1; 1716b7d861d9SBoojin Kim tasklet_schedule(&pl330->tasks); 1717b7d861d9SBoojin Kim } 1718b7d861d9SBoojin Kim 1719b7d861d9SBoojin Kim return ret; 1720b7d861d9SBoojin Kim } 1721b7d861d9SBoojin Kim 172265ad6060SLars-Peter Clausen static int pl330_chan_ctrl(struct pl330_thread *thrd, enum pl330_chan_op op) 1723b7d861d9SBoojin Kim { 1724b7d861d9SBoojin Kim struct pl330_dmac *pl330; 1725b7d861d9SBoojin Kim unsigned long flags; 1726ef08e782SLinus Torvalds int ret = 0, active; 1727b7d861d9SBoojin Kim 1728b7d861d9SBoojin Kim if (!thrd || thrd->free || thrd->dmac->state == DYING) 1729b7d861d9SBoojin Kim return -EINVAL; 1730b7d861d9SBoojin Kim 1731b7d861d9SBoojin Kim pl330 = thrd->dmac; 1732ef08e782SLinus Torvalds active = thrd->req_running; 1733b7d861d9SBoojin Kim 1734b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1735b7d861d9SBoojin Kim 1736b7d861d9SBoojin Kim switch (op) { 1737b7d861d9SBoojin Kim case PL330_OP_FLUSH: 1738b7d861d9SBoojin Kim /* Make sure the channel is stopped */ 1739b7d861d9SBoojin Kim _stop(thrd); 1740b7d861d9SBoojin Kim 1741b7d861d9SBoojin Kim thrd->req[0].r = NULL; 1742b7d861d9SBoojin Kim thrd->req[1].r = NULL; 1743b7d861d9SBoojin Kim mark_free(thrd, 0); 1744b7d861d9SBoojin Kim mark_free(thrd, 1); 1745b7d861d9SBoojin Kim break; 1746b7d861d9SBoojin Kim 1747b7d861d9SBoojin Kim case PL330_OP_ABORT: 1748b7d861d9SBoojin Kim /* Make sure the channel is stopped */ 1749b7d861d9SBoojin Kim _stop(thrd); 1750b7d861d9SBoojin Kim 1751b7d861d9SBoojin Kim /* ABORT is only for the active req */ 1752b7d861d9SBoojin Kim if (active == -1) 1753b7d861d9SBoojin Kim break; 1754b7d861d9SBoojin Kim 1755b7d861d9SBoojin Kim thrd->req[active].r = NULL; 1756b7d861d9SBoojin Kim mark_free(thrd, active); 1757b7d861d9SBoojin Kim 1758b7d861d9SBoojin Kim /* Start the next */ 1759b7d861d9SBoojin Kim case PL330_OP_START: 1760b7d861d9SBoojin Kim if ((active == -1) && !_start(thrd)) 1761b7d861d9SBoojin Kim ret = -EIO; 1762b7d861d9SBoojin Kim break; 1763b7d861d9SBoojin Kim 1764b7d861d9SBoojin Kim default: 1765b7d861d9SBoojin Kim ret = -EINVAL; 1766b7d861d9SBoojin Kim } 1767b7d861d9SBoojin Kim 1768b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1769b7d861d9SBoojin Kim return ret; 1770b7d861d9SBoojin Kim } 1771b7d861d9SBoojin Kim 1772b7d861d9SBoojin Kim /* Reserve an event */ 1773b7d861d9SBoojin Kim static inline int _alloc_event(struct pl330_thread *thrd) 1774b7d861d9SBoojin Kim { 1775b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 1776b7d861d9SBoojin Kim struct pl330_info *pi = pl330->pinfo; 1777b7d861d9SBoojin Kim int ev; 1778b7d861d9SBoojin Kim 1779b7d861d9SBoojin Kim for (ev = 0; ev < pi->pcfg.num_events; ev++) 1780b7d861d9SBoojin Kim if (pl330->events[ev] == -1) { 1781b7d861d9SBoojin Kim pl330->events[ev] = thrd->id; 1782b7d861d9SBoojin Kim return ev; 1783b7d861d9SBoojin Kim } 1784b7d861d9SBoojin Kim 1785b7d861d9SBoojin Kim return -1; 1786b7d861d9SBoojin Kim } 1787b7d861d9SBoojin Kim 1788b7d861d9SBoojin Kim static bool _chan_ns(const struct pl330_info *pi, int i) 1789b7d861d9SBoojin Kim { 1790b7d861d9SBoojin Kim return pi->pcfg.irq_ns & (1 << i); 1791b7d861d9SBoojin Kim } 1792b7d861d9SBoojin Kim 1793b7d861d9SBoojin Kim /* Upon success, returns IdentityToken for the 1794b7d861d9SBoojin Kim * allocated channel, NULL otherwise. 1795b7d861d9SBoojin Kim */ 179665ad6060SLars-Peter Clausen static struct pl330_thread *pl330_request_channel(const struct pl330_info *pi) 1797b7d861d9SBoojin Kim { 1798b7d861d9SBoojin Kim struct pl330_thread *thrd = NULL; 1799b7d861d9SBoojin Kim struct pl330_dmac *pl330; 1800b7d861d9SBoojin Kim unsigned long flags; 1801b7d861d9SBoojin Kim int chans, i; 1802b7d861d9SBoojin Kim 1803b7d861d9SBoojin Kim if (!pi || !pi->pl330_data) 1804b7d861d9SBoojin Kim return NULL; 1805b7d861d9SBoojin Kim 1806b7d861d9SBoojin Kim pl330 = pi->pl330_data; 1807b7d861d9SBoojin Kim 1808b7d861d9SBoojin Kim if (pl330->state == DYING) 1809b7d861d9SBoojin Kim return NULL; 1810b7d861d9SBoojin Kim 1811b7d861d9SBoojin Kim chans = pi->pcfg.num_chan; 1812b7d861d9SBoojin Kim 1813b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1814b7d861d9SBoojin Kim 1815b7d861d9SBoojin Kim for (i = 0; i < chans; i++) { 1816b7d861d9SBoojin Kim thrd = &pl330->channels[i]; 1817b7d861d9SBoojin Kim if ((thrd->free) && (!_manager_ns(thrd) || 1818b7d861d9SBoojin Kim _chan_ns(pi, i))) { 1819b7d861d9SBoojin Kim thrd->ev = _alloc_event(thrd); 1820b7d861d9SBoojin Kim if (thrd->ev >= 0) { 1821b7d861d9SBoojin Kim thrd->free = false; 1822b7d861d9SBoojin Kim thrd->lstenq = 1; 1823b7d861d9SBoojin Kim thrd->req[0].r = NULL; 1824b7d861d9SBoojin Kim mark_free(thrd, 0); 1825b7d861d9SBoojin Kim thrd->req[1].r = NULL; 1826b7d861d9SBoojin Kim mark_free(thrd, 1); 1827b7d861d9SBoojin Kim break; 1828b7d861d9SBoojin Kim } 1829b7d861d9SBoojin Kim } 1830b7d861d9SBoojin Kim thrd = NULL; 1831b7d861d9SBoojin Kim } 1832b7d861d9SBoojin Kim 1833b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1834b7d861d9SBoojin Kim 1835b7d861d9SBoojin Kim return thrd; 1836b7d861d9SBoojin Kim } 1837b7d861d9SBoojin Kim 1838b7d861d9SBoojin Kim /* Release an event */ 1839b7d861d9SBoojin Kim static inline void _free_event(struct pl330_thread *thrd, int ev) 1840b7d861d9SBoojin Kim { 1841b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 1842b7d861d9SBoojin Kim struct pl330_info *pi = pl330->pinfo; 1843b7d861d9SBoojin Kim 1844b7d861d9SBoojin Kim /* If the event is valid and was held by the thread */ 1845b7d861d9SBoojin Kim if (ev >= 0 && ev < pi->pcfg.num_events 1846b7d861d9SBoojin Kim && pl330->events[ev] == thrd->id) 1847b7d861d9SBoojin Kim pl330->events[ev] = -1; 1848b7d861d9SBoojin Kim } 1849b7d861d9SBoojin Kim 185065ad6060SLars-Peter Clausen static void pl330_release_channel(struct pl330_thread *thrd) 1851b7d861d9SBoojin Kim { 1852b7d861d9SBoojin Kim struct pl330_dmac *pl330; 1853b7d861d9SBoojin Kim unsigned long flags; 1854b7d861d9SBoojin Kim 1855b7d861d9SBoojin Kim if (!thrd || thrd->free) 1856b7d861d9SBoojin Kim return; 1857b7d861d9SBoojin Kim 1858b7d861d9SBoojin Kim _stop(thrd); 1859b7d861d9SBoojin Kim 18606079d38cSLars-Peter Clausen dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].r, PL330_ERR_ABORT); 18616079d38cSLars-Peter Clausen dma_pl330_rqcb(thrd->req[thrd->lstenq].r, PL330_ERR_ABORT); 1862b7d861d9SBoojin Kim 1863b7d861d9SBoojin Kim pl330 = thrd->dmac; 1864b7d861d9SBoojin Kim 1865b7d861d9SBoojin Kim spin_lock_irqsave(&pl330->lock, flags); 1866b7d861d9SBoojin Kim _free_event(thrd, thrd->ev); 1867b7d861d9SBoojin Kim thrd->free = true; 1868b7d861d9SBoojin Kim spin_unlock_irqrestore(&pl330->lock, flags); 1869b7d861d9SBoojin Kim } 1870b7d861d9SBoojin Kim 1871b7d861d9SBoojin Kim /* Initialize the structure for PL330 configuration, that can be used 1872b7d861d9SBoojin Kim * by the client driver the make best use of the DMAC 1873b7d861d9SBoojin Kim */ 1874b7d861d9SBoojin Kim static void read_dmac_config(struct pl330_info *pi) 1875b7d861d9SBoojin Kim { 1876b7d861d9SBoojin Kim void __iomem *regs = pi->base; 1877b7d861d9SBoojin Kim u32 val; 1878b7d861d9SBoojin Kim 1879b7d861d9SBoojin Kim val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; 1880b7d861d9SBoojin Kim val &= CRD_DATA_WIDTH_MASK; 1881b7d861d9SBoojin Kim pi->pcfg.data_bus_width = 8 * (1 << val); 1882b7d861d9SBoojin Kim 1883b7d861d9SBoojin Kim val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; 1884b7d861d9SBoojin Kim val &= CRD_DATA_BUFF_MASK; 1885b7d861d9SBoojin Kim pi->pcfg.data_buf_dep = val + 1; 1886b7d861d9SBoojin Kim 1887b7d861d9SBoojin Kim val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; 1888b7d861d9SBoojin Kim val &= CR0_NUM_CHANS_MASK; 1889b7d861d9SBoojin Kim val += 1; 1890b7d861d9SBoojin Kim pi->pcfg.num_chan = val; 1891b7d861d9SBoojin Kim 1892b7d861d9SBoojin Kim val = readl(regs + CR0); 1893b7d861d9SBoojin Kim if (val & CR0_PERIPH_REQ_SET) { 1894b7d861d9SBoojin Kim val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; 1895b7d861d9SBoojin Kim val += 1; 1896b7d861d9SBoojin Kim pi->pcfg.num_peri = val; 1897b7d861d9SBoojin Kim pi->pcfg.peri_ns = readl(regs + CR4); 1898b7d861d9SBoojin Kim } else { 1899b7d861d9SBoojin Kim pi->pcfg.num_peri = 0; 1900b7d861d9SBoojin Kim } 1901b7d861d9SBoojin Kim 1902b7d861d9SBoojin Kim val = readl(regs + CR0); 1903b7d861d9SBoojin Kim if (val & CR0_BOOT_MAN_NS) 1904b7d861d9SBoojin Kim pi->pcfg.mode |= DMAC_MODE_NS; 1905b7d861d9SBoojin Kim else 1906b7d861d9SBoojin Kim pi->pcfg.mode &= ~DMAC_MODE_NS; 1907b7d861d9SBoojin Kim 1908b7d861d9SBoojin Kim val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; 1909b7d861d9SBoojin Kim val &= CR0_NUM_EVENTS_MASK; 1910b7d861d9SBoojin Kim val += 1; 1911b7d861d9SBoojin Kim pi->pcfg.num_events = val; 1912b7d861d9SBoojin Kim 1913b7d861d9SBoojin Kim pi->pcfg.irq_ns = readl(regs + CR3); 1914b7d861d9SBoojin Kim } 1915b7d861d9SBoojin Kim 1916b7d861d9SBoojin Kim static inline void _reset_thread(struct pl330_thread *thrd) 1917b7d861d9SBoojin Kim { 1918b7d861d9SBoojin Kim struct pl330_dmac *pl330 = thrd->dmac; 1919b7d861d9SBoojin Kim struct pl330_info *pi = pl330->pinfo; 1920b7d861d9SBoojin Kim 1921b7d861d9SBoojin Kim thrd->req[0].mc_cpu = pl330->mcode_cpu 1922b7d861d9SBoojin Kim + (thrd->id * pi->mcbufsz); 1923b7d861d9SBoojin Kim thrd->req[0].mc_bus = pl330->mcode_bus 1924b7d861d9SBoojin Kim + (thrd->id * pi->mcbufsz); 1925b7d861d9SBoojin Kim thrd->req[0].r = NULL; 1926b7d861d9SBoojin Kim mark_free(thrd, 0); 1927b7d861d9SBoojin Kim 1928b7d861d9SBoojin Kim thrd->req[1].mc_cpu = thrd->req[0].mc_cpu 1929b7d861d9SBoojin Kim + pi->mcbufsz / 2; 1930b7d861d9SBoojin Kim thrd->req[1].mc_bus = thrd->req[0].mc_bus 1931b7d861d9SBoojin Kim + pi->mcbufsz / 2; 1932b7d861d9SBoojin Kim thrd->req[1].r = NULL; 1933b7d861d9SBoojin Kim mark_free(thrd, 1); 1934b7d861d9SBoojin Kim } 1935b7d861d9SBoojin Kim 1936b7d861d9SBoojin Kim static int dmac_alloc_threads(struct pl330_dmac *pl330) 1937b7d861d9SBoojin Kim { 1938b7d861d9SBoojin Kim struct pl330_info *pi = pl330->pinfo; 1939b7d861d9SBoojin Kim int chans = pi->pcfg.num_chan; 1940b7d861d9SBoojin Kim struct pl330_thread *thrd; 1941b7d861d9SBoojin Kim int i; 1942b7d861d9SBoojin Kim 1943b7d861d9SBoojin Kim /* Allocate 1 Manager and 'chans' Channel threads */ 1944b7d861d9SBoojin Kim pl330->channels = kzalloc((1 + chans) * sizeof(*thrd), 1945b7d861d9SBoojin Kim GFP_KERNEL); 1946b7d861d9SBoojin Kim if (!pl330->channels) 1947b7d861d9SBoojin Kim return -ENOMEM; 1948b7d861d9SBoojin Kim 1949b7d861d9SBoojin Kim /* Init Channel threads */ 1950b7d861d9SBoojin Kim for (i = 0; i < chans; i++) { 1951b7d861d9SBoojin Kim thrd = &pl330->channels[i]; 1952b7d861d9SBoojin Kim thrd->id = i; 1953b7d861d9SBoojin Kim thrd->dmac = pl330; 1954b7d861d9SBoojin Kim _reset_thread(thrd); 1955b7d861d9SBoojin Kim thrd->free = true; 1956b7d861d9SBoojin Kim } 1957b7d861d9SBoojin Kim 1958b7d861d9SBoojin Kim /* MANAGER is indexed at the end */ 1959b7d861d9SBoojin Kim thrd = &pl330->channels[chans]; 1960b7d861d9SBoojin Kim thrd->id = chans; 1961b7d861d9SBoojin Kim thrd->dmac = pl330; 1962b7d861d9SBoojin Kim thrd->free = false; 1963b7d861d9SBoojin Kim pl330->manager = thrd; 1964b7d861d9SBoojin Kim 1965b7d861d9SBoojin Kim return 0; 1966b7d861d9SBoojin Kim } 1967b7d861d9SBoojin Kim 1968b7d861d9SBoojin Kim static int dmac_alloc_resources(struct pl330_dmac *pl330) 1969b7d861d9SBoojin Kim { 1970b7d861d9SBoojin Kim struct pl330_info *pi = pl330->pinfo; 1971b7d861d9SBoojin Kim int chans = pi->pcfg.num_chan; 1972b7d861d9SBoojin Kim int ret; 1973b7d861d9SBoojin Kim 1974b7d861d9SBoojin Kim /* 1975b7d861d9SBoojin Kim * Alloc MicroCode buffer for 'chans' Channel threads. 1976b7d861d9SBoojin Kim * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN) 1977b7d861d9SBoojin Kim */ 1978b7d861d9SBoojin Kim pl330->mcode_cpu = dma_alloc_coherent(pi->dev, 1979b7d861d9SBoojin Kim chans * pi->mcbufsz, 1980b7d861d9SBoojin Kim &pl330->mcode_bus, GFP_KERNEL); 1981b7d861d9SBoojin Kim if (!pl330->mcode_cpu) { 1982b7d861d9SBoojin Kim dev_err(pi->dev, "%s:%d Can't allocate memory!\n", 1983b7d861d9SBoojin Kim __func__, __LINE__); 1984b7d861d9SBoojin Kim return -ENOMEM; 1985b7d861d9SBoojin Kim } 1986b7d861d9SBoojin Kim 1987b7d861d9SBoojin Kim ret = dmac_alloc_threads(pl330); 1988b7d861d9SBoojin Kim if (ret) { 1989b7d861d9SBoojin Kim dev_err(pi->dev, "%s:%d Can't to create channels for DMAC!\n", 1990b7d861d9SBoojin Kim __func__, __LINE__); 1991b7d861d9SBoojin Kim dma_free_coherent(pi->dev, 1992b7d861d9SBoojin Kim chans * pi->mcbufsz, 1993b7d861d9SBoojin Kim pl330->mcode_cpu, pl330->mcode_bus); 1994b7d861d9SBoojin Kim return ret; 1995b7d861d9SBoojin Kim } 1996b7d861d9SBoojin Kim 1997b7d861d9SBoojin Kim return 0; 1998b7d861d9SBoojin Kim } 1999b7d861d9SBoojin Kim 2000b7d861d9SBoojin Kim static int pl330_add(struct pl330_info *pi) 2001b7d861d9SBoojin Kim { 2002b7d861d9SBoojin Kim struct pl330_dmac *pl330; 2003b7d861d9SBoojin Kim void __iomem *regs; 2004b7d861d9SBoojin Kim int i, ret; 2005b7d861d9SBoojin Kim 2006b7d861d9SBoojin Kim if (!pi || !pi->dev) 2007b7d861d9SBoojin Kim return -EINVAL; 2008b7d861d9SBoojin Kim 2009b7d861d9SBoojin Kim /* If already added */ 2010b7d861d9SBoojin Kim if (pi->pl330_data) 2011b7d861d9SBoojin Kim return -EINVAL; 2012b7d861d9SBoojin Kim 2013b7d861d9SBoojin Kim regs = pi->base; 2014b7d861d9SBoojin Kim 2015b7d861d9SBoojin Kim /* Check if we can handle this DMAC */ 201609677176SWill Deacon if ((pi->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) { 201709677176SWill Deacon dev_err(pi->dev, "PERIPH_ID 0x%x !\n", pi->pcfg.periph_id); 2018b7d861d9SBoojin Kim return -EINVAL; 2019b7d861d9SBoojin Kim } 2020b7d861d9SBoojin Kim 2021b7d861d9SBoojin Kim /* Read the configuration of the DMAC */ 2022b7d861d9SBoojin Kim read_dmac_config(pi); 2023b7d861d9SBoojin Kim 2024b7d861d9SBoojin Kim if (pi->pcfg.num_events == 0) { 2025b7d861d9SBoojin Kim dev_err(pi->dev, "%s:%d Can't work without events!\n", 2026b7d861d9SBoojin Kim __func__, __LINE__); 2027b7d861d9SBoojin Kim return -EINVAL; 2028b7d861d9SBoojin Kim } 2029b7d861d9SBoojin Kim 2030b7d861d9SBoojin Kim pl330 = kzalloc(sizeof(*pl330), GFP_KERNEL); 2031b7d861d9SBoojin Kim if (!pl330) { 2032b7d861d9SBoojin Kim dev_err(pi->dev, "%s:%d Can't allocate memory!\n", 2033b7d861d9SBoojin Kim __func__, __LINE__); 2034b7d861d9SBoojin Kim return -ENOMEM; 2035b7d861d9SBoojin Kim } 2036b7d861d9SBoojin Kim 2037b7d861d9SBoojin Kim /* Assign the info structure and private data */ 2038b7d861d9SBoojin Kim pl330->pinfo = pi; 2039b7d861d9SBoojin Kim pi->pl330_data = pl330; 2040b7d861d9SBoojin Kim 2041b7d861d9SBoojin Kim spin_lock_init(&pl330->lock); 2042b7d861d9SBoojin Kim 2043b7d861d9SBoojin Kim INIT_LIST_HEAD(&pl330->req_done); 2044b7d861d9SBoojin Kim 2045b7d861d9SBoojin Kim /* Use default MC buffer size if not provided */ 2046b7d861d9SBoojin Kim if (!pi->mcbufsz) 2047b7d861d9SBoojin Kim pi->mcbufsz = MCODE_BUFF_PER_REQ * 2; 2048b7d861d9SBoojin Kim 2049b7d861d9SBoojin Kim /* Mark all events as free */ 2050b7d861d9SBoojin Kim for (i = 0; i < pi->pcfg.num_events; i++) 2051b7d861d9SBoojin Kim pl330->events[i] = -1; 2052b7d861d9SBoojin Kim 2053b7d861d9SBoojin Kim /* Allocate resources needed by the DMAC */ 2054b7d861d9SBoojin Kim ret = dmac_alloc_resources(pl330); 2055b7d861d9SBoojin Kim if (ret) { 2056b7d861d9SBoojin Kim dev_err(pi->dev, "Unable to create channels for DMAC\n"); 2057b7d861d9SBoojin Kim kfree(pl330); 2058b7d861d9SBoojin Kim return ret; 2059b7d861d9SBoojin Kim } 2060b7d861d9SBoojin Kim 2061b7d861d9SBoojin Kim tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330); 2062b7d861d9SBoojin Kim 2063b7d861d9SBoojin Kim pl330->state = INIT; 2064b7d861d9SBoojin Kim 2065b7d861d9SBoojin Kim return 0; 2066b7d861d9SBoojin Kim } 2067b7d861d9SBoojin Kim 2068b7d861d9SBoojin Kim static int dmac_free_threads(struct pl330_dmac *pl330) 2069b7d861d9SBoojin Kim { 2070b7d861d9SBoojin Kim struct pl330_info *pi = pl330->pinfo; 2071b7d861d9SBoojin Kim int chans = pi->pcfg.num_chan; 2072b7d861d9SBoojin Kim struct pl330_thread *thrd; 2073b7d861d9SBoojin Kim int i; 2074b7d861d9SBoojin Kim 2075b7d861d9SBoojin Kim /* Release Channel threads */ 2076b7d861d9SBoojin Kim for (i = 0; i < chans; i++) { 2077b7d861d9SBoojin Kim thrd = &pl330->channels[i]; 207865ad6060SLars-Peter Clausen pl330_release_channel(thrd); 2079b7d861d9SBoojin Kim } 2080b7d861d9SBoojin Kim 2081b7d861d9SBoojin Kim /* Free memory */ 2082b7d861d9SBoojin Kim kfree(pl330->channels); 2083b7d861d9SBoojin Kim 2084b7d861d9SBoojin Kim return 0; 2085b7d861d9SBoojin Kim } 2086b7d861d9SBoojin Kim 2087b7d861d9SBoojin Kim static void dmac_free_resources(struct pl330_dmac *pl330) 2088b7d861d9SBoojin Kim { 2089b7d861d9SBoojin Kim struct pl330_info *pi = pl330->pinfo; 2090b7d861d9SBoojin Kim int chans = pi->pcfg.num_chan; 2091b7d861d9SBoojin Kim 2092b7d861d9SBoojin Kim dmac_free_threads(pl330); 2093b7d861d9SBoojin Kim 2094b7d861d9SBoojin Kim dma_free_coherent(pi->dev, chans * pi->mcbufsz, 2095b7d861d9SBoojin Kim pl330->mcode_cpu, pl330->mcode_bus); 2096b7d861d9SBoojin Kim } 2097b7d861d9SBoojin Kim 2098b7d861d9SBoojin Kim static void pl330_del(struct pl330_info *pi) 2099b7d861d9SBoojin Kim { 2100b7d861d9SBoojin Kim struct pl330_dmac *pl330; 2101b7d861d9SBoojin Kim 2102b7d861d9SBoojin Kim if (!pi || !pi->pl330_data) 2103b7d861d9SBoojin Kim return; 2104b7d861d9SBoojin Kim 2105b7d861d9SBoojin Kim pl330 = pi->pl330_data; 2106b7d861d9SBoojin Kim 2107b7d861d9SBoojin Kim pl330->state = UNINIT; 2108b7d861d9SBoojin Kim 2109b7d861d9SBoojin Kim tasklet_kill(&pl330->tasks); 2110b7d861d9SBoojin Kim 2111b7d861d9SBoojin Kim /* Free DMAC resources */ 2112b7d861d9SBoojin Kim dmac_free_resources(pl330); 2113b7d861d9SBoojin Kim 2114b7d861d9SBoojin Kim kfree(pl330); 2115b7d861d9SBoojin Kim pi->pl330_data = NULL; 2116b7d861d9SBoojin Kim } 2117b7d861d9SBoojin Kim 21183e2ec13aSThomas Abraham /* forward declaration */ 21193e2ec13aSThomas Abraham static struct amba_driver pl330_driver; 21203e2ec13aSThomas Abraham 2121b3040e40SJassi Brar static inline struct dma_pl330_chan * 2122b3040e40SJassi Brar to_pchan(struct dma_chan *ch) 2123b3040e40SJassi Brar { 2124b3040e40SJassi Brar if (!ch) 2125b3040e40SJassi Brar return NULL; 2126b3040e40SJassi Brar 2127b3040e40SJassi Brar return container_of(ch, struct dma_pl330_chan, chan); 2128b3040e40SJassi Brar } 2129b3040e40SJassi Brar 2130b3040e40SJassi Brar static inline struct dma_pl330_desc * 2131b3040e40SJassi Brar to_desc(struct dma_async_tx_descriptor *tx) 2132b3040e40SJassi Brar { 2133b3040e40SJassi Brar return container_of(tx, struct dma_pl330_desc, txd); 2134b3040e40SJassi Brar } 2135b3040e40SJassi Brar 2136b3040e40SJassi Brar static inline void fill_queue(struct dma_pl330_chan *pch) 2137b3040e40SJassi Brar { 2138b3040e40SJassi Brar struct dma_pl330_desc *desc; 2139b3040e40SJassi Brar int ret; 2140b3040e40SJassi Brar 2141b3040e40SJassi Brar list_for_each_entry(desc, &pch->work_list, node) { 2142b3040e40SJassi Brar 2143b3040e40SJassi Brar /* If already submitted */ 2144b3040e40SJassi Brar if (desc->status == BUSY) 214530fb980bSJassi Brar continue; 2146b3040e40SJassi Brar 214765ad6060SLars-Peter Clausen ret = pl330_submit_req(pch->thread, &desc->req); 2148b3040e40SJassi Brar if (!ret) { 2149b3040e40SJassi Brar desc->status = BUSY; 2150b3040e40SJassi Brar } else if (ret == -EAGAIN) { 2151b3040e40SJassi Brar /* QFull or DMAC Dying */ 2152b3040e40SJassi Brar break; 2153b3040e40SJassi Brar } else { 2154b3040e40SJassi Brar /* Unacceptable request */ 2155b3040e40SJassi Brar desc->status = DONE; 2156b3040e40SJassi Brar dev_err(pch->dmac->pif.dev, "%s:%d Bad Desc(%d)\n", 2157b3040e40SJassi Brar __func__, __LINE__, desc->txd.cookie); 2158b3040e40SJassi Brar tasklet_schedule(&pch->task); 2159b3040e40SJassi Brar } 2160b3040e40SJassi Brar } 2161b3040e40SJassi Brar } 2162b3040e40SJassi Brar 2163b3040e40SJassi Brar static void pl330_tasklet(unsigned long data) 2164b3040e40SJassi Brar { 2165b3040e40SJassi Brar struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data; 2166b3040e40SJassi Brar struct dma_pl330_desc *desc, *_dt; 2167b3040e40SJassi Brar unsigned long flags; 2168b3040e40SJassi Brar 2169b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2170b3040e40SJassi Brar 2171b3040e40SJassi Brar /* Pick up ripe tomatoes */ 2172b3040e40SJassi Brar list_for_each_entry_safe(desc, _dt, &pch->work_list, node) 2173b3040e40SJassi Brar if (desc->status == DONE) { 217430c1dc0fSTushar Behera if (!pch->cyclic) 2175f7fbce07SRussell King - ARM Linux dma_cookie_complete(&desc->txd); 217639ff8613SLars-Peter Clausen list_move_tail(&desc->node, &pch->completed_list); 2177b3040e40SJassi Brar } 2178b3040e40SJassi Brar 2179b3040e40SJassi Brar /* Try to submit a req imm. next to the last completed cookie */ 2180b3040e40SJassi Brar fill_queue(pch); 2181b3040e40SJassi Brar 2182b3040e40SJassi Brar /* Make sure the PL330 Channel thread is active */ 218365ad6060SLars-Peter Clausen pl330_chan_ctrl(pch->thread, PL330_OP_START); 2184b3040e40SJassi Brar 218539ff8613SLars-Peter Clausen while (!list_empty(&pch->completed_list)) { 218639ff8613SLars-Peter Clausen dma_async_tx_callback callback; 218739ff8613SLars-Peter Clausen void *callback_param; 2188b3040e40SJassi Brar 218939ff8613SLars-Peter Clausen desc = list_first_entry(&pch->completed_list, 219039ff8613SLars-Peter Clausen struct dma_pl330_desc, node); 219139ff8613SLars-Peter Clausen 219239ff8613SLars-Peter Clausen callback = desc->txd.callback; 219339ff8613SLars-Peter Clausen callback_param = desc->txd.callback_param; 219439ff8613SLars-Peter Clausen 219539ff8613SLars-Peter Clausen if (pch->cyclic) { 219639ff8613SLars-Peter Clausen desc->status = PREP; 219739ff8613SLars-Peter Clausen list_move_tail(&desc->node, &pch->work_list); 219839ff8613SLars-Peter Clausen } else { 219939ff8613SLars-Peter Clausen desc->status = FREE; 220039ff8613SLars-Peter Clausen list_move_tail(&desc->node, &pch->dmac->desc_pool); 220139ff8613SLars-Peter Clausen } 220239ff8613SLars-Peter Clausen 2203d38a8c62SDan Williams dma_descriptor_unmap(&desc->txd); 2204d38a8c62SDan Williams 220539ff8613SLars-Peter Clausen if (callback) { 220639ff8613SLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 220739ff8613SLars-Peter Clausen callback(callback_param); 220839ff8613SLars-Peter Clausen spin_lock_irqsave(&pch->lock, flags); 220939ff8613SLars-Peter Clausen } 221039ff8613SLars-Peter Clausen } 221139ff8613SLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 2212b3040e40SJassi Brar } 2213b3040e40SJassi Brar 22143e2ec13aSThomas Abraham bool pl330_filter(struct dma_chan *chan, void *param) 22153e2ec13aSThomas Abraham { 2216cd072515SThomas Abraham u8 *peri_id; 22173e2ec13aSThomas Abraham 22183e2ec13aSThomas Abraham if (chan->device->dev->driver != &pl330_driver.drv) 22193e2ec13aSThomas Abraham return false; 22203e2ec13aSThomas Abraham 2221cd072515SThomas Abraham peri_id = chan->private; 22222f986ec6SDan Carpenter return *peri_id == (unsigned long)param; 22233e2ec13aSThomas Abraham } 22243e2ec13aSThomas Abraham EXPORT_SYMBOL(pl330_filter); 22253e2ec13aSThomas Abraham 2226a80258f9SPadmavathi Venna static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec, 2227a80258f9SPadmavathi Venna struct of_dma *ofdma) 2228a80258f9SPadmavathi Venna { 2229a80258f9SPadmavathi Venna int count = dma_spec->args_count; 2230a80258f9SPadmavathi Venna struct dma_pl330_dmac *pdmac = ofdma->of_dma_data; 223170cbb163SLars-Peter Clausen unsigned int chan_id; 2232a80258f9SPadmavathi Venna 2233a80258f9SPadmavathi Venna if (count != 1) 2234a80258f9SPadmavathi Venna return NULL; 2235a80258f9SPadmavathi Venna 223670cbb163SLars-Peter Clausen chan_id = dma_spec->args[0]; 223770cbb163SLars-Peter Clausen if (chan_id >= pdmac->num_peripherals) 223870cbb163SLars-Peter Clausen return NULL; 2239a80258f9SPadmavathi Venna 224070cbb163SLars-Peter Clausen return dma_get_slave_channel(&pdmac->peripherals[chan_id].chan); 2241a80258f9SPadmavathi Venna } 2242a80258f9SPadmavathi Venna 2243b3040e40SJassi Brar static int pl330_alloc_chan_resources(struct dma_chan *chan) 2244b3040e40SJassi Brar { 2245b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2246b3040e40SJassi Brar struct dma_pl330_dmac *pdmac = pch->dmac; 2247b3040e40SJassi Brar unsigned long flags; 2248b3040e40SJassi Brar 2249b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2250b3040e40SJassi Brar 2251d3ee98cdSRussell King - ARM Linux dma_cookie_init(chan); 225242bc9cf4SBoojin Kim pch->cyclic = false; 2253b3040e40SJassi Brar 225465ad6060SLars-Peter Clausen pch->thread = pl330_request_channel(&pdmac->pif); 225565ad6060SLars-Peter Clausen if (!pch->thread) { 2256b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 225702747885SInderpal Singh return -ENOMEM; 2258b3040e40SJassi Brar } 2259b3040e40SJassi Brar 2260b3040e40SJassi Brar tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch); 2261b3040e40SJassi Brar 2262b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 2263b3040e40SJassi Brar 2264b3040e40SJassi Brar return 1; 2265b3040e40SJassi Brar } 2266b3040e40SJassi Brar 2267b3040e40SJassi Brar static int pl330_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg) 2268b3040e40SJassi Brar { 2269b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 227039ff8613SLars-Peter Clausen struct dma_pl330_desc *desc; 2271b3040e40SJassi Brar unsigned long flags; 22721d0c1d60SBoojin Kim struct dma_pl330_dmac *pdmac = pch->dmac; 22731d0c1d60SBoojin Kim struct dma_slave_config *slave_config; 2274ae43b886SBoojin Kim LIST_HEAD(list); 2275b3040e40SJassi Brar 22761d0c1d60SBoojin Kim switch (cmd) { 22771d0c1d60SBoojin Kim case DMA_TERMINATE_ALL: 2278b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2279b3040e40SJassi Brar 2280b3040e40SJassi Brar /* FLUSH the PL330 Channel thread */ 228165ad6060SLars-Peter Clausen pl330_chan_ctrl(pch->thread, PL330_OP_FLUSH); 2282b3040e40SJassi Brar 2283b3040e40SJassi Brar /* Mark all desc done */ 228404abf5daSLars-Peter Clausen list_for_each_entry(desc, &pch->submitted_list, node) { 228504abf5daSLars-Peter Clausen desc->status = FREE; 228604abf5daSLars-Peter Clausen dma_cookie_complete(&desc->txd); 228704abf5daSLars-Peter Clausen } 228804abf5daSLars-Peter Clausen 228939ff8613SLars-Peter Clausen list_for_each_entry(desc, &pch->work_list , node) { 229039ff8613SLars-Peter Clausen desc->status = FREE; 229139ff8613SLars-Peter Clausen dma_cookie_complete(&desc->txd); 2292ae43b886SBoojin Kim } 2293b3040e40SJassi Brar 229439ff8613SLars-Peter Clausen list_for_each_entry(desc, &pch->completed_list , node) { 229539ff8613SLars-Peter Clausen desc->status = FREE; 229639ff8613SLars-Peter Clausen dma_cookie_complete(&desc->txd); 229739ff8613SLars-Peter Clausen } 229839ff8613SLars-Peter Clausen 229904abf5daSLars-Peter Clausen list_splice_tail_init(&pch->submitted_list, &pdmac->desc_pool); 230039ff8613SLars-Peter Clausen list_splice_tail_init(&pch->work_list, &pdmac->desc_pool); 230139ff8613SLars-Peter Clausen list_splice_tail_init(&pch->completed_list, &pdmac->desc_pool); 2302b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 23031d0c1d60SBoojin Kim break; 23041d0c1d60SBoojin Kim case DMA_SLAVE_CONFIG: 23051d0c1d60SBoojin Kim slave_config = (struct dma_slave_config *)arg; 2306b3040e40SJassi Brar 2307db8196dfSVinod Koul if (slave_config->direction == DMA_MEM_TO_DEV) { 23081d0c1d60SBoojin Kim if (slave_config->dst_addr) 23091d0c1d60SBoojin Kim pch->fifo_addr = slave_config->dst_addr; 23101d0c1d60SBoojin Kim if (slave_config->dst_addr_width) 23111d0c1d60SBoojin Kim pch->burst_sz = __ffs(slave_config->dst_addr_width); 23121d0c1d60SBoojin Kim if (slave_config->dst_maxburst) 23131d0c1d60SBoojin Kim pch->burst_len = slave_config->dst_maxburst; 2314db8196dfSVinod Koul } else if (slave_config->direction == DMA_DEV_TO_MEM) { 23151d0c1d60SBoojin Kim if (slave_config->src_addr) 23161d0c1d60SBoojin Kim pch->fifo_addr = slave_config->src_addr; 23171d0c1d60SBoojin Kim if (slave_config->src_addr_width) 23181d0c1d60SBoojin Kim pch->burst_sz = __ffs(slave_config->src_addr_width); 23191d0c1d60SBoojin Kim if (slave_config->src_maxburst) 23201d0c1d60SBoojin Kim pch->burst_len = slave_config->src_maxburst; 23211d0c1d60SBoojin Kim } 23221d0c1d60SBoojin Kim break; 23231d0c1d60SBoojin Kim default: 23241d0c1d60SBoojin Kim dev_err(pch->dmac->pif.dev, "Not supported command.\n"); 23251d0c1d60SBoojin Kim return -ENXIO; 23261d0c1d60SBoojin Kim } 2327b3040e40SJassi Brar 2328b3040e40SJassi Brar return 0; 2329b3040e40SJassi Brar } 2330b3040e40SJassi Brar 2331b3040e40SJassi Brar static void pl330_free_chan_resources(struct dma_chan *chan) 2332b3040e40SJassi Brar { 2333b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2334b3040e40SJassi Brar unsigned long flags; 2335b3040e40SJassi Brar 2336b3040e40SJassi Brar tasklet_kill(&pch->task); 2337b3040e40SJassi Brar 2338da331ba8SBartlomiej Zolnierkiewicz spin_lock_irqsave(&pch->lock, flags); 2339da331ba8SBartlomiej Zolnierkiewicz 234065ad6060SLars-Peter Clausen pl330_release_channel(pch->thread); 234165ad6060SLars-Peter Clausen pch->thread = NULL; 2342b3040e40SJassi Brar 234342bc9cf4SBoojin Kim if (pch->cyclic) 234442bc9cf4SBoojin Kim list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); 234542bc9cf4SBoojin Kim 2346b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 2347b3040e40SJassi Brar } 2348b3040e40SJassi Brar 2349b3040e40SJassi Brar static enum dma_status 2350b3040e40SJassi Brar pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, 2351b3040e40SJassi Brar struct dma_tx_state *txstate) 2352b3040e40SJassi Brar { 235396a2af41SRussell King - ARM Linux return dma_cookie_status(chan, cookie, txstate); 2354b3040e40SJassi Brar } 2355b3040e40SJassi Brar 2356b3040e40SJassi Brar static void pl330_issue_pending(struct dma_chan *chan) 2357b3040e40SJassi Brar { 235804abf5daSLars-Peter Clausen struct dma_pl330_chan *pch = to_pchan(chan); 235904abf5daSLars-Peter Clausen unsigned long flags; 236004abf5daSLars-Peter Clausen 236104abf5daSLars-Peter Clausen spin_lock_irqsave(&pch->lock, flags); 236204abf5daSLars-Peter Clausen list_splice_tail_init(&pch->submitted_list, &pch->work_list); 236304abf5daSLars-Peter Clausen spin_unlock_irqrestore(&pch->lock, flags); 236404abf5daSLars-Peter Clausen 236504abf5daSLars-Peter Clausen pl330_tasklet((unsigned long)pch); 2366b3040e40SJassi Brar } 2367b3040e40SJassi Brar 2368b3040e40SJassi Brar /* 2369b3040e40SJassi Brar * We returned the last one of the circular list of descriptor(s) 2370b3040e40SJassi Brar * from prep_xxx, so the argument to submit corresponds to the last 2371b3040e40SJassi Brar * descriptor of the list. 2372b3040e40SJassi Brar */ 2373b3040e40SJassi Brar static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) 2374b3040e40SJassi Brar { 2375b3040e40SJassi Brar struct dma_pl330_desc *desc, *last = to_desc(tx); 2376b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(tx->chan); 2377b3040e40SJassi Brar dma_cookie_t cookie; 2378b3040e40SJassi Brar unsigned long flags; 2379b3040e40SJassi Brar 2380b3040e40SJassi Brar spin_lock_irqsave(&pch->lock, flags); 2381b3040e40SJassi Brar 2382b3040e40SJassi Brar /* Assign cookies to all nodes */ 2383b3040e40SJassi Brar while (!list_empty(&last->node)) { 2384b3040e40SJassi Brar desc = list_entry(last->node.next, struct dma_pl330_desc, node); 2385fc514460SLars-Peter Clausen if (pch->cyclic) { 2386fc514460SLars-Peter Clausen desc->txd.callback = last->txd.callback; 2387fc514460SLars-Peter Clausen desc->txd.callback_param = last->txd.callback_param; 2388fc514460SLars-Peter Clausen } 2389b3040e40SJassi Brar 2390884485e1SRussell King - ARM Linux dma_cookie_assign(&desc->txd); 2391b3040e40SJassi Brar 239204abf5daSLars-Peter Clausen list_move_tail(&desc->node, &pch->submitted_list); 2393b3040e40SJassi Brar } 2394b3040e40SJassi Brar 2395884485e1SRussell King - ARM Linux cookie = dma_cookie_assign(&last->txd); 239604abf5daSLars-Peter Clausen list_add_tail(&last->node, &pch->submitted_list); 2397b3040e40SJassi Brar spin_unlock_irqrestore(&pch->lock, flags); 2398b3040e40SJassi Brar 2399b3040e40SJassi Brar return cookie; 2400b3040e40SJassi Brar } 2401b3040e40SJassi Brar 2402b3040e40SJassi Brar static inline void _init_desc(struct dma_pl330_desc *desc) 2403b3040e40SJassi Brar { 2404b3040e40SJassi Brar desc->req.x = &desc->px; 2405b3040e40SJassi Brar desc->rqcfg.swap = SWAP_NO; 2406f0564c7eSLars-Peter Clausen desc->rqcfg.scctl = CCTRL0; 2407f0564c7eSLars-Peter Clausen desc->rqcfg.dcctl = CCTRL0; 2408b3040e40SJassi Brar desc->req.cfg = &desc->rqcfg; 2409b3040e40SJassi Brar desc->txd.tx_submit = pl330_tx_submit; 2410b3040e40SJassi Brar 2411b3040e40SJassi Brar INIT_LIST_HEAD(&desc->node); 2412b3040e40SJassi Brar } 2413b3040e40SJassi Brar 2414b3040e40SJassi Brar /* Returns the number of descriptors added to the DMAC pool */ 24155a67ac57SSachin Kamat static int add_desc(struct dma_pl330_dmac *pdmac, gfp_t flg, int count) 2416b3040e40SJassi Brar { 2417b3040e40SJassi Brar struct dma_pl330_desc *desc; 2418b3040e40SJassi Brar unsigned long flags; 2419b3040e40SJassi Brar int i; 2420b3040e40SJassi Brar 2421b3040e40SJassi Brar if (!pdmac) 2422b3040e40SJassi Brar return 0; 2423b3040e40SJassi Brar 24240baf8f6aSWill Deacon desc = kcalloc(count, sizeof(*desc), flg); 2425b3040e40SJassi Brar if (!desc) 2426b3040e40SJassi Brar return 0; 2427b3040e40SJassi Brar 2428b3040e40SJassi Brar spin_lock_irqsave(&pdmac->pool_lock, flags); 2429b3040e40SJassi Brar 2430b3040e40SJassi Brar for (i = 0; i < count; i++) { 2431b3040e40SJassi Brar _init_desc(&desc[i]); 2432b3040e40SJassi Brar list_add_tail(&desc[i].node, &pdmac->desc_pool); 2433b3040e40SJassi Brar } 2434b3040e40SJassi Brar 2435b3040e40SJassi Brar spin_unlock_irqrestore(&pdmac->pool_lock, flags); 2436b3040e40SJassi Brar 2437b3040e40SJassi Brar return count; 2438b3040e40SJassi Brar } 2439b3040e40SJassi Brar 2440b3040e40SJassi Brar static struct dma_pl330_desc * 2441b3040e40SJassi Brar pluck_desc(struct dma_pl330_dmac *pdmac) 2442b3040e40SJassi Brar { 2443b3040e40SJassi Brar struct dma_pl330_desc *desc = NULL; 2444b3040e40SJassi Brar unsigned long flags; 2445b3040e40SJassi Brar 2446b3040e40SJassi Brar if (!pdmac) 2447b3040e40SJassi Brar return NULL; 2448b3040e40SJassi Brar 2449b3040e40SJassi Brar spin_lock_irqsave(&pdmac->pool_lock, flags); 2450b3040e40SJassi Brar 2451b3040e40SJassi Brar if (!list_empty(&pdmac->desc_pool)) { 2452b3040e40SJassi Brar desc = list_entry(pdmac->desc_pool.next, 2453b3040e40SJassi Brar struct dma_pl330_desc, node); 2454b3040e40SJassi Brar 2455b3040e40SJassi Brar list_del_init(&desc->node); 2456b3040e40SJassi Brar 2457b3040e40SJassi Brar desc->status = PREP; 2458b3040e40SJassi Brar desc->txd.callback = NULL; 2459b3040e40SJassi Brar } 2460b3040e40SJassi Brar 2461b3040e40SJassi Brar spin_unlock_irqrestore(&pdmac->pool_lock, flags); 2462b3040e40SJassi Brar 2463b3040e40SJassi Brar return desc; 2464b3040e40SJassi Brar } 2465b3040e40SJassi Brar 2466b3040e40SJassi Brar static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) 2467b3040e40SJassi Brar { 2468b3040e40SJassi Brar struct dma_pl330_dmac *pdmac = pch->dmac; 2469cd072515SThomas Abraham u8 *peri_id = pch->chan.private; 2470b3040e40SJassi Brar struct dma_pl330_desc *desc; 2471b3040e40SJassi Brar 2472b3040e40SJassi Brar /* Pluck one desc from the pool of DMAC */ 2473b3040e40SJassi Brar desc = pluck_desc(pdmac); 2474b3040e40SJassi Brar 2475b3040e40SJassi Brar /* If the DMAC pool is empty, alloc new */ 2476b3040e40SJassi Brar if (!desc) { 2477b3040e40SJassi Brar if (!add_desc(pdmac, GFP_ATOMIC, 1)) 2478b3040e40SJassi Brar return NULL; 2479b3040e40SJassi Brar 2480b3040e40SJassi Brar /* Try again */ 2481b3040e40SJassi Brar desc = pluck_desc(pdmac); 2482b3040e40SJassi Brar if (!desc) { 2483b3040e40SJassi Brar dev_err(pch->dmac->pif.dev, 2484b3040e40SJassi Brar "%s:%d ALERT!\n", __func__, __LINE__); 2485b3040e40SJassi Brar return NULL; 2486b3040e40SJassi Brar } 2487b3040e40SJassi Brar } 2488b3040e40SJassi Brar 2489b3040e40SJassi Brar /* Initialize the descriptor */ 2490b3040e40SJassi Brar desc->pchan = pch; 2491b3040e40SJassi Brar desc->txd.cookie = 0; 2492b3040e40SJassi Brar async_tx_ack(&desc->txd); 2493b3040e40SJassi Brar 2494cd072515SThomas Abraham desc->req.peri = peri_id ? pch->chan.chan_id : 0; 24953ecf51a4SBoojin Kim desc->rqcfg.pcfg = &pch->dmac->pif.pcfg; 2496b3040e40SJassi Brar 2497b3040e40SJassi Brar dma_async_tx_descriptor_init(&desc->txd, &pch->chan); 2498b3040e40SJassi Brar 2499b3040e40SJassi Brar return desc; 2500b3040e40SJassi Brar } 2501b3040e40SJassi Brar 2502b3040e40SJassi Brar static inline void fill_px(struct pl330_xfer *px, 2503b3040e40SJassi Brar dma_addr_t dst, dma_addr_t src, size_t len) 2504b3040e40SJassi Brar { 2505b3040e40SJassi Brar px->bytes = len; 2506b3040e40SJassi Brar px->dst_addr = dst; 2507b3040e40SJassi Brar px->src_addr = src; 2508b3040e40SJassi Brar } 2509b3040e40SJassi Brar 2510b3040e40SJassi Brar static struct dma_pl330_desc * 2511b3040e40SJassi Brar __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, 2512b3040e40SJassi Brar dma_addr_t src, size_t len) 2513b3040e40SJassi Brar { 2514b3040e40SJassi Brar struct dma_pl330_desc *desc = pl330_get_desc(pch); 2515b3040e40SJassi Brar 2516b3040e40SJassi Brar if (!desc) { 2517b3040e40SJassi Brar dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n", 2518b3040e40SJassi Brar __func__, __LINE__); 2519b3040e40SJassi Brar return NULL; 2520b3040e40SJassi Brar } 2521b3040e40SJassi Brar 2522b3040e40SJassi Brar /* 2523b3040e40SJassi Brar * Ideally we should lookout for reqs bigger than 2524b3040e40SJassi Brar * those that can be programmed with 256 bytes of 2525b3040e40SJassi Brar * MC buffer, but considering a req size is seldom 2526b3040e40SJassi Brar * going to be word-unaligned and more than 200MB, 2527b3040e40SJassi Brar * we take it easy. 2528b3040e40SJassi Brar * Also, should the limit is reached we'd rather 2529b3040e40SJassi Brar * have the platform increase MC buffer size than 2530b3040e40SJassi Brar * complicating this API driver. 2531b3040e40SJassi Brar */ 2532b3040e40SJassi Brar fill_px(&desc->px, dst, src, len); 2533b3040e40SJassi Brar 2534b3040e40SJassi Brar return desc; 2535b3040e40SJassi Brar } 2536b3040e40SJassi Brar 2537b3040e40SJassi Brar /* Call after fixing burst size */ 2538b3040e40SJassi Brar static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) 2539b3040e40SJassi Brar { 2540b3040e40SJassi Brar struct dma_pl330_chan *pch = desc->pchan; 2541b3040e40SJassi Brar struct pl330_info *pi = &pch->dmac->pif; 2542b3040e40SJassi Brar int burst_len; 2543b3040e40SJassi Brar 2544b3040e40SJassi Brar burst_len = pi->pcfg.data_bus_width / 8; 2545b3040e40SJassi Brar burst_len *= pi->pcfg.data_buf_dep; 2546b3040e40SJassi Brar burst_len >>= desc->rqcfg.brst_size; 2547b3040e40SJassi Brar 2548b3040e40SJassi Brar /* src/dst_burst_len can't be more than 16 */ 2549b3040e40SJassi Brar if (burst_len > 16) 2550b3040e40SJassi Brar burst_len = 16; 2551b3040e40SJassi Brar 2552b3040e40SJassi Brar while (burst_len > 1) { 2553b3040e40SJassi Brar if (!(len % (burst_len << desc->rqcfg.brst_size))) 2554b3040e40SJassi Brar break; 2555b3040e40SJassi Brar burst_len--; 2556b3040e40SJassi Brar } 2557b3040e40SJassi Brar 2558b3040e40SJassi Brar return burst_len; 2559b3040e40SJassi Brar } 2560b3040e40SJassi Brar 256142bc9cf4SBoojin Kim static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( 256242bc9cf4SBoojin Kim struct dma_chan *chan, dma_addr_t dma_addr, size_t len, 2563185ecb5fSAlexandre Bounine size_t period_len, enum dma_transfer_direction direction, 2564ec8b5e48SPeter Ujfalusi unsigned long flags, void *context) 256542bc9cf4SBoojin Kim { 2566fc514460SLars-Peter Clausen struct dma_pl330_desc *desc = NULL, *first = NULL; 256742bc9cf4SBoojin Kim struct dma_pl330_chan *pch = to_pchan(chan); 2568fc514460SLars-Peter Clausen struct dma_pl330_dmac *pdmac = pch->dmac; 2569fc514460SLars-Peter Clausen unsigned int i; 257042bc9cf4SBoojin Kim dma_addr_t dst; 257142bc9cf4SBoojin Kim dma_addr_t src; 257242bc9cf4SBoojin Kim 2573fc514460SLars-Peter Clausen if (len % period_len != 0) 2574fc514460SLars-Peter Clausen return NULL; 2575fc514460SLars-Peter Clausen 2576fc514460SLars-Peter Clausen if (!is_slave_direction(direction)) { 2577fc514460SLars-Peter Clausen dev_err(pch->dmac->pif.dev, "%s:%d Invalid dma direction\n", 2578fc514460SLars-Peter Clausen __func__, __LINE__); 2579fc514460SLars-Peter Clausen return NULL; 2580fc514460SLars-Peter Clausen } 2581fc514460SLars-Peter Clausen 2582fc514460SLars-Peter Clausen for (i = 0; i < len / period_len; i++) { 258342bc9cf4SBoojin Kim desc = pl330_get_desc(pch); 258442bc9cf4SBoojin Kim if (!desc) { 258542bc9cf4SBoojin Kim dev_err(pch->dmac->pif.dev, "%s:%d Unable to fetch desc\n", 258642bc9cf4SBoojin Kim __func__, __LINE__); 2587fc514460SLars-Peter Clausen 2588fc514460SLars-Peter Clausen if (!first) 2589fc514460SLars-Peter Clausen return NULL; 2590fc514460SLars-Peter Clausen 2591fc514460SLars-Peter Clausen spin_lock_irqsave(&pdmac->pool_lock, flags); 2592fc514460SLars-Peter Clausen 2593fc514460SLars-Peter Clausen while (!list_empty(&first->node)) { 2594fc514460SLars-Peter Clausen desc = list_entry(first->node.next, 2595fc514460SLars-Peter Clausen struct dma_pl330_desc, node); 2596fc514460SLars-Peter Clausen list_move_tail(&desc->node, &pdmac->desc_pool); 2597fc514460SLars-Peter Clausen } 2598fc514460SLars-Peter Clausen 2599fc514460SLars-Peter Clausen list_move_tail(&first->node, &pdmac->desc_pool); 2600fc514460SLars-Peter Clausen 2601fc514460SLars-Peter Clausen spin_unlock_irqrestore(&pdmac->pool_lock, flags); 2602fc514460SLars-Peter Clausen 260342bc9cf4SBoojin Kim return NULL; 260442bc9cf4SBoojin Kim } 260542bc9cf4SBoojin Kim 260642bc9cf4SBoojin Kim switch (direction) { 2607db8196dfSVinod Koul case DMA_MEM_TO_DEV: 260842bc9cf4SBoojin Kim desc->rqcfg.src_inc = 1; 260942bc9cf4SBoojin Kim desc->rqcfg.dst_inc = 0; 261042bc9cf4SBoojin Kim src = dma_addr; 261142bc9cf4SBoojin Kim dst = pch->fifo_addr; 261242bc9cf4SBoojin Kim break; 2613db8196dfSVinod Koul case DMA_DEV_TO_MEM: 261442bc9cf4SBoojin Kim desc->rqcfg.src_inc = 0; 261542bc9cf4SBoojin Kim desc->rqcfg.dst_inc = 1; 261642bc9cf4SBoojin Kim src = pch->fifo_addr; 261742bc9cf4SBoojin Kim dst = dma_addr; 261842bc9cf4SBoojin Kim break; 261942bc9cf4SBoojin Kim default: 2620fc514460SLars-Peter Clausen break; 262142bc9cf4SBoojin Kim } 262242bc9cf4SBoojin Kim 2623585a9d0bSLars-Peter Clausen desc->req.rqtype = direction; 262442bc9cf4SBoojin Kim desc->rqcfg.brst_size = pch->burst_sz; 262542bc9cf4SBoojin Kim desc->rqcfg.brst_len = 1; 2626fc514460SLars-Peter Clausen fill_px(&desc->px, dst, src, period_len); 2627fc514460SLars-Peter Clausen 2628fc514460SLars-Peter Clausen if (!first) 2629fc514460SLars-Peter Clausen first = desc; 2630fc514460SLars-Peter Clausen else 2631fc514460SLars-Peter Clausen list_add_tail(&desc->node, &first->node); 2632fc514460SLars-Peter Clausen 2633fc514460SLars-Peter Clausen dma_addr += period_len; 2634fc514460SLars-Peter Clausen } 2635fc514460SLars-Peter Clausen 2636fc514460SLars-Peter Clausen if (!desc) 2637fc514460SLars-Peter Clausen return NULL; 263842bc9cf4SBoojin Kim 263942bc9cf4SBoojin Kim pch->cyclic = true; 2640fc514460SLars-Peter Clausen desc->txd.flags = flags; 264142bc9cf4SBoojin Kim 264242bc9cf4SBoojin Kim return &desc->txd; 264342bc9cf4SBoojin Kim } 264442bc9cf4SBoojin Kim 2645b3040e40SJassi Brar static struct dma_async_tx_descriptor * 2646b3040e40SJassi Brar pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, 2647b3040e40SJassi Brar dma_addr_t src, size_t len, unsigned long flags) 2648b3040e40SJassi Brar { 2649b3040e40SJassi Brar struct dma_pl330_desc *desc; 2650b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2651b3040e40SJassi Brar struct pl330_info *pi; 2652b3040e40SJassi Brar int burst; 2653b3040e40SJassi Brar 26544e0e6109SRob Herring if (unlikely(!pch || !len)) 2655b3040e40SJassi Brar return NULL; 2656b3040e40SJassi Brar 2657b3040e40SJassi Brar pi = &pch->dmac->pif; 2658b3040e40SJassi Brar 2659b3040e40SJassi Brar desc = __pl330_prep_dma_memcpy(pch, dst, src, len); 2660b3040e40SJassi Brar if (!desc) 2661b3040e40SJassi Brar return NULL; 2662b3040e40SJassi Brar 2663b3040e40SJassi Brar desc->rqcfg.src_inc = 1; 2664b3040e40SJassi Brar desc->rqcfg.dst_inc = 1; 2665585a9d0bSLars-Peter Clausen desc->req.rqtype = DMA_MEM_TO_MEM; 2666b3040e40SJassi Brar 2667b3040e40SJassi Brar /* Select max possible burst size */ 2668b3040e40SJassi Brar burst = pi->pcfg.data_bus_width / 8; 2669b3040e40SJassi Brar 2670b3040e40SJassi Brar while (burst > 1) { 2671b3040e40SJassi Brar if (!(len % burst)) 2672b3040e40SJassi Brar break; 2673b3040e40SJassi Brar burst /= 2; 2674b3040e40SJassi Brar } 2675b3040e40SJassi Brar 2676b3040e40SJassi Brar desc->rqcfg.brst_size = 0; 2677b3040e40SJassi Brar while (burst != (1 << desc->rqcfg.brst_size)) 2678b3040e40SJassi Brar desc->rqcfg.brst_size++; 2679b3040e40SJassi Brar 2680b3040e40SJassi Brar desc->rqcfg.brst_len = get_burst_len(desc, len); 2681b3040e40SJassi Brar 2682b3040e40SJassi Brar desc->txd.flags = flags; 2683b3040e40SJassi Brar 2684b3040e40SJassi Brar return &desc->txd; 2685b3040e40SJassi Brar } 2686b3040e40SJassi Brar 268752a9d179SChanho Park static void __pl330_giveback_desc(struct dma_pl330_dmac *pdmac, 268852a9d179SChanho Park struct dma_pl330_desc *first) 268952a9d179SChanho Park { 269052a9d179SChanho Park unsigned long flags; 269152a9d179SChanho Park struct dma_pl330_desc *desc; 269252a9d179SChanho Park 269352a9d179SChanho Park if (!first) 269452a9d179SChanho Park return; 269552a9d179SChanho Park 269652a9d179SChanho Park spin_lock_irqsave(&pdmac->pool_lock, flags); 269752a9d179SChanho Park 269852a9d179SChanho Park while (!list_empty(&first->node)) { 269952a9d179SChanho Park desc = list_entry(first->node.next, 270052a9d179SChanho Park struct dma_pl330_desc, node); 270152a9d179SChanho Park list_move_tail(&desc->node, &pdmac->desc_pool); 270252a9d179SChanho Park } 270352a9d179SChanho Park 270452a9d179SChanho Park list_move_tail(&first->node, &pdmac->desc_pool); 270552a9d179SChanho Park 270652a9d179SChanho Park spin_unlock_irqrestore(&pdmac->pool_lock, flags); 270752a9d179SChanho Park } 270852a9d179SChanho Park 2709b3040e40SJassi Brar static struct dma_async_tx_descriptor * 2710b3040e40SJassi Brar pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 2711db8196dfSVinod Koul unsigned int sg_len, enum dma_transfer_direction direction, 2712185ecb5fSAlexandre Bounine unsigned long flg, void *context) 2713b3040e40SJassi Brar { 2714b3040e40SJassi Brar struct dma_pl330_desc *first, *desc = NULL; 2715b3040e40SJassi Brar struct dma_pl330_chan *pch = to_pchan(chan); 2716b3040e40SJassi Brar struct scatterlist *sg; 27171b9bb715SBoojin Kim int i; 2718b3040e40SJassi Brar dma_addr_t addr; 2719b3040e40SJassi Brar 2720cd072515SThomas Abraham if (unlikely(!pch || !sgl || !sg_len)) 2721b3040e40SJassi Brar return NULL; 2722b3040e40SJassi Brar 27231b9bb715SBoojin Kim addr = pch->fifo_addr; 2724b3040e40SJassi Brar 2725b3040e40SJassi Brar first = NULL; 2726b3040e40SJassi Brar 2727b3040e40SJassi Brar for_each_sg(sgl, sg, sg_len, i) { 2728b3040e40SJassi Brar 2729b3040e40SJassi Brar desc = pl330_get_desc(pch); 2730b3040e40SJassi Brar if (!desc) { 2731b3040e40SJassi Brar struct dma_pl330_dmac *pdmac = pch->dmac; 2732b3040e40SJassi Brar 2733b3040e40SJassi Brar dev_err(pch->dmac->pif.dev, 2734b3040e40SJassi Brar "%s:%d Unable to fetch desc\n", 2735b3040e40SJassi Brar __func__, __LINE__); 273652a9d179SChanho Park __pl330_giveback_desc(pdmac, first); 2737b3040e40SJassi Brar 2738b3040e40SJassi Brar return NULL; 2739b3040e40SJassi Brar } 2740b3040e40SJassi Brar 2741b3040e40SJassi Brar if (!first) 2742b3040e40SJassi Brar first = desc; 2743b3040e40SJassi Brar else 2744b3040e40SJassi Brar list_add_tail(&desc->node, &first->node); 2745b3040e40SJassi Brar 2746db8196dfSVinod Koul if (direction == DMA_MEM_TO_DEV) { 2747b3040e40SJassi Brar desc->rqcfg.src_inc = 1; 2748b3040e40SJassi Brar desc->rqcfg.dst_inc = 0; 2749b3040e40SJassi Brar fill_px(&desc->px, 2750b3040e40SJassi Brar addr, sg_dma_address(sg), sg_dma_len(sg)); 2751b3040e40SJassi Brar } else { 2752b3040e40SJassi Brar desc->rqcfg.src_inc = 0; 2753b3040e40SJassi Brar desc->rqcfg.dst_inc = 1; 2754b3040e40SJassi Brar fill_px(&desc->px, 2755b3040e40SJassi Brar sg_dma_address(sg), addr, sg_dma_len(sg)); 2756b3040e40SJassi Brar } 2757b3040e40SJassi Brar 27581b9bb715SBoojin Kim desc->rqcfg.brst_size = pch->burst_sz; 2759b3040e40SJassi Brar desc->rqcfg.brst_len = 1; 2760585a9d0bSLars-Peter Clausen desc->req.rqtype = direction; 2761b3040e40SJassi Brar } 2762b3040e40SJassi Brar 2763b3040e40SJassi Brar /* Return the last desc in the chain */ 2764b3040e40SJassi Brar desc->txd.flags = flg; 2765b3040e40SJassi Brar return &desc->txd; 2766b3040e40SJassi Brar } 2767b3040e40SJassi Brar 2768b3040e40SJassi Brar static irqreturn_t pl330_irq_handler(int irq, void *data) 2769b3040e40SJassi Brar { 2770b3040e40SJassi Brar if (pl330_update(data)) 2771b3040e40SJassi Brar return IRQ_HANDLED; 2772b3040e40SJassi Brar else 2773b3040e40SJassi Brar return IRQ_NONE; 2774b3040e40SJassi Brar } 2775b3040e40SJassi Brar 2776ca38ff13SLars-Peter Clausen #define PL330_DMA_BUSWIDTHS \ 2777ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ 2778ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 2779ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 2780ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ 2781ca38ff13SLars-Peter Clausen BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) 2782ca38ff13SLars-Peter Clausen 2783ca38ff13SLars-Peter Clausen static int pl330_dma_device_slave_caps(struct dma_chan *dchan, 2784ca38ff13SLars-Peter Clausen struct dma_slave_caps *caps) 2785ca38ff13SLars-Peter Clausen { 2786ca38ff13SLars-Peter Clausen caps->src_addr_widths = PL330_DMA_BUSWIDTHS; 2787ca38ff13SLars-Peter Clausen caps->dstn_addr_widths = PL330_DMA_BUSWIDTHS; 2788ca38ff13SLars-Peter Clausen caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 2789ca38ff13SLars-Peter Clausen caps->cmd_pause = false; 2790ca38ff13SLars-Peter Clausen caps->cmd_terminate = true; 2791bfb9bb42SLars-Peter Clausen caps->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; 2792ca38ff13SLars-Peter Clausen 2793ca38ff13SLars-Peter Clausen return 0; 2794ca38ff13SLars-Peter Clausen } 2795ca38ff13SLars-Peter Clausen 2796463a1f8bSBill Pemberton static int 2797aa25afadSRussell King pl330_probe(struct amba_device *adev, const struct amba_id *id) 2798b3040e40SJassi Brar { 2799b3040e40SJassi Brar struct dma_pl330_platdata *pdat; 2800b3040e40SJassi Brar struct dma_pl330_dmac *pdmac; 28010b94c577SPadmavathi Venna struct dma_pl330_chan *pch, *_p; 2802b3040e40SJassi Brar struct pl330_info *pi; 2803b3040e40SJassi Brar struct dma_device *pd; 2804b3040e40SJassi Brar struct resource *res; 2805b3040e40SJassi Brar int i, ret, irq; 28064e0e6109SRob Herring int num_chan; 2807b3040e40SJassi Brar 2808d4adcc01SJingoo Han pdat = dev_get_platdata(&adev->dev); 2809b3040e40SJassi Brar 281064113016SRussell King ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32)); 281164113016SRussell King if (ret) 281264113016SRussell King return ret; 281364113016SRussell King 2814b3040e40SJassi Brar /* Allocate a new DMAC and its Channels */ 2815e4d43c17SSachin Kamat pdmac = devm_kzalloc(&adev->dev, sizeof(*pdmac), GFP_KERNEL); 2816b3040e40SJassi Brar if (!pdmac) { 2817b3040e40SJassi Brar dev_err(&adev->dev, "unable to allocate mem\n"); 2818b3040e40SJassi Brar return -ENOMEM; 2819b3040e40SJassi Brar } 2820b3040e40SJassi Brar 2821b3040e40SJassi Brar pi = &pdmac->pif; 2822b3040e40SJassi Brar pi->dev = &adev->dev; 2823b3040e40SJassi Brar pi->pl330_data = NULL; 28244e0e6109SRob Herring pi->mcbufsz = pdat ? pdat->mcbuf_sz : 0; 2825b3040e40SJassi Brar 2826b3040e40SJassi Brar res = &adev->res; 2827bcc7fa95SSachin Kamat pi->base = devm_ioremap_resource(&adev->dev, res); 2828bcc7fa95SSachin Kamat if (IS_ERR(pi->base)) 2829bcc7fa95SSachin Kamat return PTR_ERR(pi->base); 2830b3040e40SJassi Brar 2831a2f5203fSBoojin Kim amba_set_drvdata(adev, pdmac); 2832a2f5203fSBoojin Kim 283302808b42SDan Carpenter for (i = 0; i < AMBA_NR_IRQS; i++) { 2834e98b3cafSMichal Simek irq = adev->irq[i]; 2835e98b3cafSMichal Simek if (irq) { 2836e98b3cafSMichal Simek ret = devm_request_irq(&adev->dev, irq, 2837e98b3cafSMichal Simek pl330_irq_handler, 0, 2838b3040e40SJassi Brar dev_name(&adev->dev), pi); 2839b3040e40SJassi Brar if (ret) 2840e4d43c17SSachin Kamat return ret; 2841e98b3cafSMichal Simek } else { 2842e98b3cafSMichal Simek break; 2843e98b3cafSMichal Simek } 2844e98b3cafSMichal Simek } 2845b3040e40SJassi Brar 284609677176SWill Deacon pi->pcfg.periph_id = adev->periphid; 2847b3040e40SJassi Brar ret = pl330_add(pi); 2848b3040e40SJassi Brar if (ret) 2849173e838cSMichal Simek return ret; 2850b3040e40SJassi Brar 2851b3040e40SJassi Brar INIT_LIST_HEAD(&pdmac->desc_pool); 2852b3040e40SJassi Brar spin_lock_init(&pdmac->pool_lock); 2853b3040e40SJassi Brar 2854b3040e40SJassi Brar /* Create a descriptor pool of default size */ 2855b3040e40SJassi Brar if (!add_desc(pdmac, GFP_KERNEL, NR_DEFAULT_DESC)) 2856b3040e40SJassi Brar dev_warn(&adev->dev, "unable to allocate desc\n"); 2857b3040e40SJassi Brar 2858b3040e40SJassi Brar pd = &pdmac->ddma; 2859b3040e40SJassi Brar INIT_LIST_HEAD(&pd->channels); 2860b3040e40SJassi Brar 2861b3040e40SJassi Brar /* Initialize channel parameters */ 2862c8473828SOlof Johansson if (pdat) 2863c8473828SOlof Johansson num_chan = max_t(int, pdat->nr_valid_peri, pi->pcfg.num_chan); 2864c8473828SOlof Johansson else 2865c8473828SOlof Johansson num_chan = max_t(int, pi->pcfg.num_peri, pi->pcfg.num_chan); 2866c8473828SOlof Johansson 286770cbb163SLars-Peter Clausen pdmac->num_peripherals = num_chan; 286870cbb163SLars-Peter Clausen 28694e0e6109SRob Herring pdmac->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL); 287061c6e753SSachin Kamat if (!pdmac->peripherals) { 287161c6e753SSachin Kamat ret = -ENOMEM; 287261c6e753SSachin Kamat dev_err(&adev->dev, "unable to allocate pdmac->peripherals\n"); 2873e4d43c17SSachin Kamat goto probe_err2; 287461c6e753SSachin Kamat } 28754e0e6109SRob Herring 28764e0e6109SRob Herring for (i = 0; i < num_chan; i++) { 2877b3040e40SJassi Brar pch = &pdmac->peripherals[i]; 287893ed5544SThomas Abraham if (!adev->dev.of_node) 2879cd072515SThomas Abraham pch->chan.private = pdat ? &pdat->peri_id[i] : NULL; 288093ed5544SThomas Abraham else 288193ed5544SThomas Abraham pch->chan.private = adev->dev.of_node; 2882b3040e40SJassi Brar 288304abf5daSLars-Peter Clausen INIT_LIST_HEAD(&pch->submitted_list); 2884b3040e40SJassi Brar INIT_LIST_HEAD(&pch->work_list); 288539ff8613SLars-Peter Clausen INIT_LIST_HEAD(&pch->completed_list); 2886b3040e40SJassi Brar spin_lock_init(&pch->lock); 288765ad6060SLars-Peter Clausen pch->thread = NULL; 2888b3040e40SJassi Brar pch->chan.device = pd; 2889b3040e40SJassi Brar pch->dmac = pdmac; 2890b3040e40SJassi Brar 2891b3040e40SJassi Brar /* Add the channel to the DMAC list */ 2892b3040e40SJassi Brar list_add_tail(&pch->chan.device_node, &pd->channels); 2893b3040e40SJassi Brar } 2894b3040e40SJassi Brar 2895b3040e40SJassi Brar pd->dev = &adev->dev; 289693ed5544SThomas Abraham if (pdat) { 2897cd072515SThomas Abraham pd->cap_mask = pdat->cap_mask; 289893ed5544SThomas Abraham } else { 2899cd072515SThomas Abraham dma_cap_set(DMA_MEMCPY, pd->cap_mask); 290093ed5544SThomas Abraham if (pi->pcfg.num_peri) { 290193ed5544SThomas Abraham dma_cap_set(DMA_SLAVE, pd->cap_mask); 290293ed5544SThomas Abraham dma_cap_set(DMA_CYCLIC, pd->cap_mask); 29035557a419STushar Behera dma_cap_set(DMA_PRIVATE, pd->cap_mask); 290493ed5544SThomas Abraham } 290593ed5544SThomas Abraham } 2906b3040e40SJassi Brar 2907b3040e40SJassi Brar pd->device_alloc_chan_resources = pl330_alloc_chan_resources; 2908b3040e40SJassi Brar pd->device_free_chan_resources = pl330_free_chan_resources; 2909b3040e40SJassi Brar pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; 291042bc9cf4SBoojin Kim pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; 2911b3040e40SJassi Brar pd->device_tx_status = pl330_tx_status; 2912b3040e40SJassi Brar pd->device_prep_slave_sg = pl330_prep_slave_sg; 2913b3040e40SJassi Brar pd->device_control = pl330_control; 2914b3040e40SJassi Brar pd->device_issue_pending = pl330_issue_pending; 2915ca38ff13SLars-Peter Clausen pd->device_slave_caps = pl330_dma_device_slave_caps; 2916b3040e40SJassi Brar 2917b3040e40SJassi Brar ret = dma_async_device_register(pd); 2918b3040e40SJassi Brar if (ret) { 2919b3040e40SJassi Brar dev_err(&adev->dev, "unable to register DMAC\n"); 29200b94c577SPadmavathi Venna goto probe_err3; 29210b94c577SPadmavathi Venna } 29220b94c577SPadmavathi Venna 29230b94c577SPadmavathi Venna if (adev->dev.of_node) { 29240b94c577SPadmavathi Venna ret = of_dma_controller_register(adev->dev.of_node, 29250b94c577SPadmavathi Venna of_dma_pl330_xlate, pdmac); 29260b94c577SPadmavathi Venna if (ret) { 29270b94c577SPadmavathi Venna dev_err(&adev->dev, 29280b94c577SPadmavathi Venna "unable to register DMA to the generic DT DMA helpers\n"); 29290b94c577SPadmavathi Venna } 2930b3040e40SJassi Brar } 2931b714b84eSLars-Peter Clausen 2932b714b84eSLars-Peter Clausen adev->dev.dma_parms = &pdmac->dma_parms; 2933b714b84eSLars-Peter Clausen 2934dbaf6d85SVinod Koul /* 2935dbaf6d85SVinod Koul * This is the limit for transfers with a buswidth of 1, larger 2936dbaf6d85SVinod Koul * buswidths will have larger limits. 2937dbaf6d85SVinod Koul */ 2938dbaf6d85SVinod Koul ret = dma_set_max_seg_size(&adev->dev, 1900800); 2939dbaf6d85SVinod Koul if (ret) 2940dbaf6d85SVinod Koul dev_err(&adev->dev, "unable to set the seg size\n"); 2941dbaf6d85SVinod Koul 2942b3040e40SJassi Brar 2943b3040e40SJassi Brar dev_info(&adev->dev, 2944b3040e40SJassi Brar "Loaded driver for PL330 DMAC-%d\n", adev->periphid); 2945b3040e40SJassi Brar dev_info(&adev->dev, 2946b3040e40SJassi Brar "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", 2947b3040e40SJassi Brar pi->pcfg.data_buf_dep, 2948b3040e40SJassi Brar pi->pcfg.data_bus_width / 8, pi->pcfg.num_chan, 2949b3040e40SJassi Brar pi->pcfg.num_peri, pi->pcfg.num_events); 2950b3040e40SJassi Brar 2951b3040e40SJassi Brar return 0; 29520b94c577SPadmavathi Venna probe_err3: 29530b94c577SPadmavathi Venna /* Idle the DMAC */ 29540b94c577SPadmavathi Venna list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels, 29550b94c577SPadmavathi Venna chan.device_node) { 29560b94c577SPadmavathi Venna 29570b94c577SPadmavathi Venna /* Remove the channel */ 29580b94c577SPadmavathi Venna list_del(&pch->chan.device_node); 29590b94c577SPadmavathi Venna 29600b94c577SPadmavathi Venna /* Flush the channel */ 29610b94c577SPadmavathi Venna pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); 29620b94c577SPadmavathi Venna pl330_free_chan_resources(&pch->chan); 29630b94c577SPadmavathi Venna } 2964b3040e40SJassi Brar probe_err2: 2965e4d43c17SSachin Kamat pl330_del(pi); 2966b3040e40SJassi Brar 2967b3040e40SJassi Brar return ret; 2968b3040e40SJassi Brar } 2969b3040e40SJassi Brar 29704bf27b8bSGreg Kroah-Hartman static int pl330_remove(struct amba_device *adev) 2971b3040e40SJassi Brar { 2972b3040e40SJassi Brar struct dma_pl330_dmac *pdmac = amba_get_drvdata(adev); 2973b3040e40SJassi Brar struct dma_pl330_chan *pch, *_p; 2974b3040e40SJassi Brar struct pl330_info *pi; 2975b3040e40SJassi Brar 2976b3040e40SJassi Brar if (!pdmac) 2977b3040e40SJassi Brar return 0; 2978b3040e40SJassi Brar 29790b94c577SPadmavathi Venna if (adev->dev.of_node) 2980421da89aSPadmavathi Venna of_dma_controller_free(adev->dev.of_node); 2981421da89aSPadmavathi Venna 29820b94c577SPadmavathi Venna dma_async_device_unregister(&pdmac->ddma); 2983b3040e40SJassi Brar 2984b3040e40SJassi Brar /* Idle the DMAC */ 2985b3040e40SJassi Brar list_for_each_entry_safe(pch, _p, &pdmac->ddma.channels, 2986b3040e40SJassi Brar chan.device_node) { 2987b3040e40SJassi Brar 2988b3040e40SJassi Brar /* Remove the channel */ 2989b3040e40SJassi Brar list_del(&pch->chan.device_node); 2990b3040e40SJassi Brar 2991b3040e40SJassi Brar /* Flush the channel */ 2992b3040e40SJassi Brar pl330_control(&pch->chan, DMA_TERMINATE_ALL, 0); 2993b3040e40SJassi Brar pl330_free_chan_resources(&pch->chan); 2994b3040e40SJassi Brar } 2995b3040e40SJassi Brar 2996b3040e40SJassi Brar pi = &pdmac->pif; 2997b3040e40SJassi Brar 2998b3040e40SJassi Brar pl330_del(pi); 2999b3040e40SJassi Brar 3000b3040e40SJassi Brar return 0; 3001b3040e40SJassi Brar } 3002b3040e40SJassi Brar 3003b3040e40SJassi Brar static struct amba_id pl330_ids[] = { 3004b3040e40SJassi Brar { 3005b3040e40SJassi Brar .id = 0x00041330, 3006b3040e40SJassi Brar .mask = 0x000fffff, 3007b3040e40SJassi Brar }, 3008b3040e40SJassi Brar { 0, 0 }, 3009b3040e40SJassi Brar }; 3010b3040e40SJassi Brar 3011e8fa516aSDave Martin MODULE_DEVICE_TABLE(amba, pl330_ids); 3012e8fa516aSDave Martin 3013b3040e40SJassi Brar static struct amba_driver pl330_driver = { 3014b3040e40SJassi Brar .drv = { 3015b3040e40SJassi Brar .owner = THIS_MODULE, 3016b3040e40SJassi Brar .name = "dma-pl330", 3017b3040e40SJassi Brar }, 3018b3040e40SJassi Brar .id_table = pl330_ids, 3019b3040e40SJassi Brar .probe = pl330_probe, 3020b3040e40SJassi Brar .remove = pl330_remove, 3021b3040e40SJassi Brar }; 3022b3040e40SJassi Brar 30239e5ed094Sviresh kumar module_amba_driver(pl330_driver); 3024b3040e40SJassi Brar 3025b3040e40SJassi Brar MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); 3026b3040e40SJassi Brar MODULE_DESCRIPTION("API Driver for PL330 DMAC"); 3027b3040e40SJassi Brar MODULE_LICENSE("GPL"); 3028